drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/sctp.h>
  39 #include <linux/pkt_sched.h>
  40 #include <linux/ipv6.h>
  41 #include <linux/slab.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <linux/ethtool.h>
  45 #include <linux/if.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/prefetch.h>
  48 #include <scsi/fc/fc_fcoe.h>
  49
  50 #include "ixgbe.h"
  51 #include "ixgbe_common.h"
  52 #include "ixgbe_dcb_82599.h"
  53 #include "ixgbe_sriov.h"
  54
  55 char ixgbe_driver_name[] = "ixgbe";
  56 static const char ixgbe_driver_string[] =
  57                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  58 #define MAJ 3
  59 #define MIN 4
  60 #define BUILD 8
  61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  62         __stringify(BUILD) "-k"
  63 const char ixgbe_driver_version[] = DRV_VERSION;
  64 static const char ixgbe_copyright[] =
  65                                 "Copyright (c) 1999-2011 Intel Corporation.";
  66
  67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  68         [board_82598] = &ixgbe_82598_info,
  69         [board_82599] = &ixgbe_82599_info,
  70         [board_X540] = &ixgbe_X540_info,
  71 };
  72
  73 /* ixgbe_pci_tbl - PCI Device ID Table
  74  *
  75  * Wildcard entries (PCI_ANY_ID) should come last
  76  * Last entry must be all 0s
  77  *
  78  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  79  *   Class, Class Mask, private data (not used) }
  80  */
  81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
 108         /* required last entry */
 109         {0, }
 110 };
 111 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 112
 113 #ifdef CONFIG_IXGBE_DCA
 114 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 115                             void *p);
 116 static struct notifier_block dca_notifier = {
 117         .notifier_call = ixgbe_notify_dca,
 118         .next          = NULL,
 119         .priority      = 0
 120 };
 121 #endif
 122
 123 #ifdef CONFIG_PCI_IOV
 124 static unsigned int max_vfs;
 125 module_param(max_vfs, uint, 0);
 126 MODULE_PARM_DESC(max_vfs,
 127                  "Maximum number of virtual functions to allocate per physical function");
 128 #endif /* CONFIG_PCI_IOV */
 129
 130 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 131 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 132 MODULE_LICENSE("GPL");
 133 MODULE_VERSION(DRV_VERSION);
 134
 135 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 136
 137 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 138 {
 139         struct ixgbe_hw *hw = &adapter->hw;
 140         u32 gcr;
 141         u32 gpie;
 142         u32 vmdctl;
 143
 144 #ifdef CONFIG_PCI_IOV
 145         /* disable iov and allow time for transactions to clear */
 146         pci_disable_sriov(adapter->pdev);
 147 #endif
 148
 149         /* turn off device IOV mode */
 150         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 151         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 152         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 153         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 154         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 155         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 156
 157         /* set default pool back to 0 */
 158         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 159         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 160         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 161         IXGBE_WRITE_FLUSH(hw);
 162
 163         /* take a breather then clean up driver data */
 164         msleep(100);
 165
 166         kfree(adapter->vfinfo);
 167         adapter->vfinfo = NULL;
 168
 169         adapter->num_vfs = 0;
 170         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 171 }
 172
 173 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 174 {
 175         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 176             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 177                 schedule_work(&adapter->service_task);
 178 }
 179
 180 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 181 {
 182         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 183
 184         /* flush memory to make sure state is correct before next watchog */
 185         smp_mb__before_clear_bit();
 186         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 187 }
 188
 189 struct ixgbe_reg_info {
 190         u32 ofs;
 191         char *name;
 192 };
 193
 194 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 195
 196         /* General Registers */
 197         {IXGBE_CTRL, "CTRL"},
 198         {IXGBE_STATUS, "STATUS"},
 199         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 200
 201         /* Interrupt Registers */
 202         {IXGBE_EICR, "EICR"},
 203
 204         /* RX Registers */
 205         {IXGBE_SRRCTL(0), "SRRCTL"},
 206         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 207         {IXGBE_RDLEN(0), "RDLEN"},
 208         {IXGBE_RDH(0), "RDH"},
 209         {IXGBE_RDT(0), "RDT"},
 210         {IXGBE_RXDCTL(0), "RXDCTL"},
 211         {IXGBE_RDBAL(0), "RDBAL"},
 212         {IXGBE_RDBAH(0), "RDBAH"},
 213
 214         /* TX Registers */
 215         {IXGBE_TDBAL(0), "TDBAL"},
 216         {IXGBE_TDBAH(0), "TDBAH"},
 217         {IXGBE_TDLEN(0), "TDLEN"},
 218         {IXGBE_TDH(0), "TDH"},
 219         {IXGBE_TDT(0), "TDT"},
 220         {IXGBE_TXDCTL(0), "TXDCTL"},
 221
 222         /* List Terminator */
 223         {}
 224 };
 225
 226
 227 /*
 228  * ixgbe_regdump - register printout routine
 229  */
 230 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 231 {
 232         int i = 0, j = 0;
 233         char rname[16];
 234         u32 regs[64];
 235
 236         switch (reginfo->ofs) {
 237         case IXGBE_SRRCTL(0):
 238                 for (i = 0; i < 64; i++)
 239                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 240                 break;
 241         case IXGBE_DCA_RXCTRL(0):
 242                 for (i = 0; i < 64; i++)
 243                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 244                 break;
 245         case IXGBE_RDLEN(0):
 246                 for (i = 0; i < 64; i++)
 247                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 248                 break;
 249         case IXGBE_RDH(0):
 250                 for (i = 0; i < 64; i++)
 251                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 252                 break;
 253         case IXGBE_RDT(0):
 254                 for (i = 0; i < 64; i++)
 255                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 256                 break;
 257         case IXGBE_RXDCTL(0):
 258                 for (i = 0; i < 64; i++)
 259                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 260                 break;
 261         case IXGBE_RDBAL(0):
 262                 for (i = 0; i < 64; i++)
 263                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 264                 break;
 265         case IXGBE_RDBAH(0):
 266                 for (i = 0; i < 64; i++)
 267                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 268                 break;
 269         case IXGBE_TDBAL(0):
 270                 for (i = 0; i < 64; i++)
 271                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 272                 break;
 273         case IXGBE_TDBAH(0):
 274                 for (i = 0; i < 64; i++)
 275                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 276                 break;
 277         case IXGBE_TDLEN(0):
 278                 for (i = 0; i < 64; i++)
 279                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 280                 break;
 281         case IXGBE_TDH(0):
 282                 for (i = 0; i < 64; i++)
 283                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 284                 break;
 285         case IXGBE_TDT(0):
 286                 for (i = 0; i < 64; i++)
 287                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 288                 break;
 289         case IXGBE_TXDCTL(0):
 290                 for (i = 0; i < 64; i++)
 291                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 292                 break;
 293         default:
 294                 pr_info("%-15s %08x\n", reginfo->name,
 295                         IXGBE_READ_REG(hw, reginfo->ofs));
 296                 return;
 297         }
 298
 299         for (i = 0; i < 8; i++) {
 300                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 301                 pr_err("%-15s", rname);
 302                 for (j = 0; j < 8; j++)
 303                         pr_cont(" %08x", regs[i*8+j]);
 304                 pr_cont("\n");
 305         }
 306
 307 }
 308
 309 /*
 310  * ixgbe_dump - Print registers, tx-rings and rx-rings
 311  */
 312 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 313 {
 314         struct net_device *netdev = adapter->netdev;
 315         struct ixgbe_hw *hw = &adapter->hw;
 316         struct ixgbe_reg_info *reginfo;
 317         int n = 0;
 318         struct ixgbe_ring *tx_ring;
 319         struct ixgbe_tx_buffer *tx_buffer_info;
 320         union ixgbe_adv_tx_desc *tx_desc;
 321         struct my_u0 { u64 a; u64 b; } *u0;
 322         struct ixgbe_ring *rx_ring;
 323         union ixgbe_adv_rx_desc *rx_desc;
 324         struct ixgbe_rx_buffer *rx_buffer_info;
 325         u32 staterr;
 326         int i = 0;
 327
 328         if (!netif_msg_hw(adapter))
 329                 return;
 330
 331         /* Print netdevice Info */
 332         if (netdev) {
 333                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 334                 pr_info("Device Name     state            "
 335                         "trans_start      last_rx\n");
 336                 pr_info("%-15s %016lX %016lX %016lX\n",
 337                         netdev->name,
 338                         netdev->state,
 339                         netdev->trans_start,
 340                         netdev->last_rx);
 341         }
 342
 343         /* Print Registers */
 344         dev_info(&adapter->pdev->dev, "Register Dump\n");
 345         pr_info(" Register Name   Value\n");
 346         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 347              reginfo->name; reginfo++) {
 348                 ixgbe_regdump(hw, reginfo);
 349         }
 350
 351         /* Print TX Ring Summary */
 352         if (!netdev || !netif_running(netdev))
 353                 goto exit;
 354
 355         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 356         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 357         for (n = 0; n < adapter->num_tx_queues; n++) {
 358                 tx_ring = adapter->tx_ring[n];
 359                 tx_buffer_info =
 360                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 361                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 362                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 363                            (u64)tx_buffer_info->dma,
 364                            tx_buffer_info->length,
 365                            tx_buffer_info->next_to_watch,
 366                            (u64)tx_buffer_info->time_stamp);
 367         }
 368
 369         /* Print TX Rings */
 370         if (!netif_msg_tx_done(adapter))
 371                 goto rx_ring_summary;
 372
 373         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 374
 375         /* Transmit Descriptor Formats
 376          *
 377          * Advanced Transmit Descriptor
 378          *   +--------------------------------------------------------------+
 379          * 0 |         Buffer Address [63:0]                                |
 380          *   +--------------------------------------------------------------+
 381          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 382          *   +--------------------------------------------------------------+
 383          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 384          */
 385
 386         for (n = 0; n < adapter->num_tx_queues; n++) {
 387                 tx_ring = adapter->tx_ring[n];
 388                 pr_info("------------------------------------\n");
 389                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 390                 pr_info("------------------------------------\n");
 391                 pr_info("T [desc]     [address 63:0  ] "
 392                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 393                         "leng  ntw timestamp        bi->skb\n");
 394
 395                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 396                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 397                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 398                         u0 = (struct my_u0 *)tx_desc;
 399                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 400                                 " %04X  %p %016llX %p", i,
 401                                 le64_to_cpu(u0->a),
 402                                 le64_to_cpu(u0->b),
 403                                 (u64)tx_buffer_info->dma,
 404                                 tx_buffer_info->length,
 405                                 tx_buffer_info->next_to_watch,
 406                                 (u64)tx_buffer_info->time_stamp,
 407                                 tx_buffer_info->skb);
 408                         if (i == tx_ring->next_to_use &&
 409                                 i == tx_ring->next_to_clean)
 410                                 pr_cont(" NTC/U\n");
 411                         else if (i == tx_ring->next_to_use)
 412                                 pr_cont(" NTU\n");
 413                         else if (i == tx_ring->next_to_clean)
 414                                 pr_cont(" NTC\n");
 415                         else
 416                                 pr_cont("\n");
 417
 418                         if (netif_msg_pktdata(adapter) &&
 419                                 tx_buffer_info->dma != 0)
 420                                 print_hex_dump(KERN_INFO, "",
 421                                         DUMP_PREFIX_ADDRESS, 16, 1,
 422                                         phys_to_virt(tx_buffer_info->dma),
 423                                         tx_buffer_info->length, true);
 424                 }
 425         }
 426
 427         /* Print RX Rings Summary */
 428 rx_ring_summary:
 429         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 430         pr_info("Queue [NTU] [NTC]\n");
 431         for (n = 0; n < adapter->num_rx_queues; n++) {
 432                 rx_ring = adapter->rx_ring[n];
 433                 pr_info("%5d %5X %5X\n",
 434                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 435         }
 436
 437         /* Print RX Rings */
 438         if (!netif_msg_rx_status(adapter))
 439                 goto exit;
 440
 441         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 442
 443         /* Advanced Receive Descriptor (Read) Format
 444          *    63                                           1        0
 445          *    +-----------------------------------------------------+
 446          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 447          *    +----------------------------------------------+------+
 448          *  8 |       Header Buffer Address [63:1]           |  DD  |
 449          *    +-----------------------------------------------------+
 450          *
 451          *
 452          * Advanced Receive Descriptor (Write-Back) Format
 453          *
 454          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 455          *   +------------------------------------------------------+
 456          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 457          *   | Checksum   Ident  |   |           |    | Type | Type |
 458          *   +------------------------------------------------------+
 459          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 460          *   +------------------------------------------------------+
 461          *   63       48 47    32 31            20 19               0
 462          */
 463         for (n = 0; n < adapter->num_rx_queues; n++) {
 464                 rx_ring = adapter->rx_ring[n];
 465                 pr_info("------------------------------------\n");
 466                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 467                 pr_info("------------------------------------\n");
 468                 pr_info("R  [desc]      [ PktBuf     A0] "
 469                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 470                         "<-- Adv Rx Read format\n");
 471                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 472                         "[vl er S cks ln] ---------------- [bi->skb] "
 473                         "<-- Adv Rx Write-Back format\n");
 474
 475                 for (i = 0; i < rx_ring->count; i++) {
 476                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 477                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 478                         u0 = (struct my_u0 *)rx_desc;
 479                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 480                         if (staterr & IXGBE_RXD_STAT_DD) {
 481                                 /* Descriptor Done */
 482                                 pr_info("RWB[0x%03X]     %016llX "
 483                                         "%016llX ---------------- %p", i,
 484                                         le64_to_cpu(u0->a),
 485                                         le64_to_cpu(u0->b),
 486                                         rx_buffer_info->skb);
 487                         } else {
 488                                 pr_info("R  [0x%03X]     %016llX "
 489                                         "%016llX %016llX %p", i,
 490                                         le64_to_cpu(u0->a),
 491                                         le64_to_cpu(u0->b),
 492                                         (u64)rx_buffer_info->dma,
 493                                         rx_buffer_info->skb);
 494
 495                                 if (netif_msg_pktdata(adapter)) {
 496                                         print_hex_dump(KERN_INFO, "",
 497                                            DUMP_PREFIX_ADDRESS, 16, 1,
 498                                            phys_to_virt(rx_buffer_info->dma),
 499                                            rx_ring->rx_buf_len, true);
 500
 501                                         if (rx_ring->rx_buf_len
 502                                                 < IXGBE_RXBUFFER_2048)
 503                                                 print_hex_dump(KERN_INFO, "",
 504                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 505                                                   phys_to_virt(
 506                                                     rx_buffer_info->page_dma +
 507                                                     rx_buffer_info->page_offset
 508                                                   ),
 509                                                   PAGE_SIZE/2, true);
 510                                 }
 511                         }
 512
 513                         if (i == rx_ring->next_to_use)
 514                                 pr_cont(" NTU\n");
 515                         else if (i == rx_ring->next_to_clean)
 516                                 pr_cont(" NTC\n");
 517                         else
 518                                 pr_cont("\n");
 519
 520                 }
 521         }
 522
 523 exit:
 524         return;
 525 }
 526
 527 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 528 {
 529         u32 ctrl_ext;
 530
 531         /* Let firmware take over control of h/w */
 532         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 533         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 534                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 535 }
 536
 537 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 538 {
 539         u32 ctrl_ext;
 540
 541         /* Let firmware know the driver has taken over */
 542         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 543         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 544                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 545 }
 546
 547 /*
 548  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 549  * @adapter: pointer to adapter struct
 550  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 551  * @queue: queue to map the corresponding interrupt to
 552  * @msix_vector: the vector to map to the corresponding queue
 553  *
 554  */
 555 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 556                            u8 queue, u8 msix_vector)
 557 {
 558         u32 ivar, index;
 559         struct ixgbe_hw *hw = &adapter->hw;
 560         switch (hw->mac.type) {
 561         case ixgbe_mac_82598EB:
 562                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 563                 if (direction == -1)
 564                         direction = 0;
 565                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 566                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 567                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 568                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 569                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 570                 break;
 571         case ixgbe_mac_82599EB:
 572         case ixgbe_mac_X540:
 573                 if (direction == -1) {
 574                         /* other causes */
 575                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 576                         index = ((queue & 1) * 8);
 577                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 578                         ivar &= ~(0xFF << index);
 579                         ivar |= (msix_vector << index);
 580                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 581                         break;
 582                 } else {
 583                         /* tx or rx causes */
 584                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 585                         index = ((16 * (queue & 1)) + (8 * direction));
 586                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 587                         ivar &= ~(0xFF << index);
 588                         ivar |= (msix_vector << index);
 589                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 590                         break;
 591                 }
 592         default:
 593                 break;
 594         }
 595 }
 596
 597 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 598                                           u64 qmask)
 599 {
 600         u32 mask;
 601
 602         switch (adapter->hw.mac.type) {
 603         case ixgbe_mac_82598EB:
 604                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 605                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 606                 break;
 607         case ixgbe_mac_82599EB:
 608         case ixgbe_mac_X540:
 609                 mask = (qmask & 0xFFFFFFFF);
 610                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 611                 mask = (qmask >> 32);
 612                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 613                 break;
 614         default:
 615                 break;
 616         }
 617 }
 618
 619 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
 620                                            struct ixgbe_tx_buffer *tx_buffer)
 621 {
 622         if (tx_buffer->dma) {
 623                 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
 624                         dma_unmap_page(ring->dev,
 625                                        tx_buffer->dma,
 626                                        tx_buffer->length,
 627                                        DMA_TO_DEVICE);
 628                 else
 629                         dma_unmap_single(ring->dev,
 630                                          tx_buffer->dma,
 631                                          tx_buffer->length,
 632                                          DMA_TO_DEVICE);
 633         }
 634         tx_buffer->dma = 0;
 635 }
 636
 637 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 638                                       struct ixgbe_tx_buffer *tx_buffer_info)
 639 {
 640         ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
 641         if (tx_buffer_info->skb)
 642                 dev_kfree_skb_any(tx_buffer_info->skb);
 643         tx_buffer_info->skb = NULL;
 644         /* tx_buffer_info must be completely set up in the transmit path */
 645 }
 646
 647 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 648 {
 649         struct ixgbe_hw *hw = &adapter->hw;
 650         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 651         u32 data = 0;
 652         u32 xoff[8] = {0};
 653         int i;
 654
 655         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 656             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 657                 switch (hw->mac.type) {
 658                 case ixgbe_mac_82598EB:
 659                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 660                         break;
 661                 default:
 662                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 663                 }
 664                 hwstats->lxoffrxc += data;
 665
 666                 /* refill credits (no tx hang) if we received xoff */
 667                 if (!data)
 668                         return;
 669
 670                 for (i = 0; i < adapter->num_tx_queues; i++)
 671                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 672                                   &adapter->tx_ring[i]->state);
 673                 return;
 674         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 675                 return;
 676
 677         /* update stats for each tc, only valid with PFC enabled */
 678         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 679                 switch (hw->mac.type) {
 680                 case ixgbe_mac_82598EB:
 681                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 682                         break;
 683                 default:
 684                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 685                 }
 686                 hwstats->pxoffrxc[i] += xoff[i];
 687         }
 688
 689         /* disarm tx queues that have received xoff frames */
 690         for (i = 0; i < adapter->num_tx_queues; i++) {
 691                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 692                 u8 tc = tx_ring->dcb_tc;
 693
 694                 if (xoff[tc])
 695                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 696         }
 697 }
 698
 699 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 700 {
 701         return ring->tx_stats.completed;
 702 }
 703
 704 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 705 {
 706         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 707         struct ixgbe_hw *hw = &adapter->hw;
 708
 709         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 710         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 711
 712         if (head != tail)
 713                 return (head < tail) ?
 714                         tail - head : (tail + ring->count - head);
 715
 716         return 0;
 717 }
 718
 719 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 720 {
 721         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 722         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 723         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 724         bool ret = false;
 725
 726         clear_check_for_tx_hang(tx_ring);
 727
 728         /*
 729          * Check for a hung queue, but be thorough. This verifies
 730          * that a transmit has been completed since the previous
 731          * check AND there is at least one packet pending. The
 732          * ARMED bit is set to indicate a potential hang. The
 733          * bit is cleared if a pause frame is received to remove
 734          * false hang detection due to PFC or 802.3x frames. By
 735          * requiring this to fail twice we avoid races with
 736          * pfc clearing the ARMED bit and conditions where we
 737          * run the check_tx_hang logic with a transmit completion
 738          * pending but without time to complete it yet.
 739          */
 740         if ((tx_done_old == tx_done) && tx_pending) {
 741                 /* make sure it is true for two checks in a row */
 742                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 743                                        &tx_ring->state);
 744         } else {
 745                 /* update completed stats and continue */
 746                 tx_ring->tx_stats.tx_done_old = tx_done;
 747                 /* reset the countdown */
 748                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 749         }
 750
 751         return ret;
 752 }
 753
 754 /**
 755  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 756  * @adapter: driver private struct
 757  **/
 758 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 759 {
 760
 761         /* Do the reset outside of interrupt context */
 762         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 763                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 764                 ixgbe_service_event_schedule(adapter);
 765         }
 766 }
 767
 768 /**
 769  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 770  * @q_vector: structure containing interrupt and ring information
 771  * @tx_ring: tx ring to clean
 772  **/
 773 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 774                                struct ixgbe_ring *tx_ring)
 775 {
 776         struct ixgbe_adapter *adapter = q_vector->adapter;
 777         struct ixgbe_tx_buffer *tx_buffer;
 778         union ixgbe_adv_tx_desc *tx_desc;
 779         unsigned int total_bytes = 0, total_packets = 0;
 780         unsigned int budget = q_vector->tx.work_limit;
 781         u16 i = tx_ring->next_to_clean;
 782
 783         tx_buffer = &tx_ring->tx_buffer_info[i];
 784         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 785
 786         for (; budget; budget--) {
 787                 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
 788
 789                 /* if next_to_watch is not set then there is no work pending */
 790                 if (!eop_desc)
 791                         break;
 792
 793                 /* if DD is not set pending work has not been completed */
 794                 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
 795                         break;
 796
 797                 /* count the packet as being completed */
 798                 tx_ring->tx_stats.completed++;
 799
 800                 /* clear next_to_watch to prevent false hangs */
 801                 tx_buffer->next_to_watch = NULL;
 802
 803                 /* prevent any other reads prior to eop_desc being verified */
 804                 rmb();
 805
 806                 do {
 807                         ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
 808                         tx_desc->wb.status = 0;
 809                         if (likely(tx_desc == eop_desc)) {
 810                                 eop_desc = NULL;
 811                                 dev_kfree_skb_any(tx_buffer->skb);
 812                                 tx_buffer->skb = NULL;
 813
 814                                 total_bytes += tx_buffer->bytecount;
 815                                 total_packets += tx_buffer->gso_segs;
 816                         }
 817
 818                         tx_buffer++;
 819                         tx_desc++;
 820                         i++;
 821                         if (unlikely(i == tx_ring->count)) {
 822                                 i = 0;
 823
 824                                 tx_buffer = tx_ring->tx_buffer_info;
 825                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
 826                         }
 827
 828                 } while (eop_desc);
 829         }
 830
 831         tx_ring->next_to_clean = i;
 832         u64_stats_update_begin(&tx_ring->syncp);
 833         tx_ring->stats.bytes += total_bytes;
 834         tx_ring->stats.packets += total_packets;
 835         u64_stats_update_end(&tx_ring->syncp);
 836         q_vector->tx.total_bytes += total_bytes;
 837         q_vector->tx.total_packets += total_packets;
 838
 839         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 840                 /* schedule immediate reset if we believe we hung */
 841                 struct ixgbe_hw *hw = &adapter->hw;
 842                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 843                 e_err(drv, "Detected Tx Unit Hang\n"
 844                         "  Tx Queue             <%d>\n"
 845                         "  TDH, TDT             <%x>, <%x>\n"
 846                         "  next_to_use          <%x>\n"
 847                         "  next_to_clean        <%x>\n"
 848                         "tx_buffer_info[next_to_clean]\n"
 849                         "  time_stamp           <%lx>\n"
 850                         "  jiffies              <%lx>\n",
 851                         tx_ring->queue_index,
 852                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 853                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 854                         tx_ring->next_to_use, i,
 855                         tx_ring->tx_buffer_info[i].time_stamp, jiffies);
 856
 857                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 858
 859                 e_info(probe,
 860                        "tx hang %d detected on queue %d, resetting adapter\n",
 861                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 862
 863                 /* schedule immediate reset if we believe we hung */
 864                 ixgbe_tx_timeout_reset(adapter);
 865
 866                 /* the adapter is about to reset, no point in enabling stuff */
 867                 return true;
 868         }
 869
 870 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 871         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 872                      (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
 873                 /* Make sure that anybody stopping the queue after this
 874                  * sees the new next_to_clean.
 875                  */
 876                 smp_mb();
 877                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 878                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 879                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 880                         ++tx_ring->tx_stats.restart_queue;
 881                 }
 882         }
 883
 884         return !!budget;
 885 }
 886
 887 #ifdef CONFIG_IXGBE_DCA
 888 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 889                                 struct ixgbe_ring *rx_ring,
 890                                 int cpu)
 891 {
 892         struct ixgbe_hw *hw = &adapter->hw;
 893         u32 rxctrl;
 894         u8 reg_idx = rx_ring->reg_idx;
 895
 896         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 897         switch (hw->mac.type) {
 898         case ixgbe_mac_82598EB:
 899                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 900                 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
 901                 break;
 902         case ixgbe_mac_82599EB:
 903         case ixgbe_mac_X540:
 904                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 905                 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
 906                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 907                 break;
 908         default:
 909                 break;
 910         }
 911         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 912         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 913         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 914         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 915 }
 916
 917 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 918                                 struct ixgbe_ring *tx_ring,
 919                                 int cpu)
 920 {
 921         struct ixgbe_hw *hw = &adapter->hw;
 922         u32 txctrl;
 923         u8 reg_idx = tx_ring->reg_idx;
 924
 925         switch (hw->mac.type) {
 926         case ixgbe_mac_82598EB:
 927                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 928                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 929                 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
 930                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 931                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 932                 break;
 933         case ixgbe_mac_82599EB:
 934         case ixgbe_mac_X540:
 935                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 936                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 937                 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
 938                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 939                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 940                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 941                 break;
 942         default:
 943                 break;
 944         }
 945 }
 946
 947 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 948 {
 949         struct ixgbe_adapter *adapter = q_vector->adapter;
 950         struct ixgbe_ring *ring;
 951         int cpu = get_cpu();
 952
 953         if (q_vector->cpu == cpu)
 954                 goto out_no_update;
 955
 956         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
 957                 ixgbe_update_tx_dca(adapter, ring, cpu);
 958
 959         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
 960                 ixgbe_update_rx_dca(adapter, ring, cpu);
 961
 962         q_vector->cpu = cpu;
 963 out_no_update:
 964         put_cpu();
 965 }
 966
 967 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 968 {
 969         int num_q_vectors;
 970         int i;
 971
 972         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 973                 return;
 974
 975         /* always use CB2 mode, difference is masked in the CB driver */
 976         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 977
 978         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 979                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 980         else
 981                 num_q_vectors = 1;
 982
 983         for (i = 0; i < num_q_vectors; i++) {
 984                 adapter->q_vector[i]->cpu = -1;
 985                 ixgbe_update_dca(adapter->q_vector[i]);
 986         }
 987 }
 988
 989 static int __ixgbe_notify_dca(struct device *dev, void *data)
 990 {
 991         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 992         unsigned long event = *(unsigned long *)data;
 993
 994         if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
 995                 return 0;
 996
 997         switch (event) {
 998         case DCA_PROVIDER_ADD:
 999                 /* if we're already enabled, don't do it again */
1000                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1001                         break;
1002                 if (dca_add_requester(dev) == 0) {
1003                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1004                         ixgbe_setup_dca(adapter);
1005                         break;
1006                 }
1007                 /* Fall Through since DCA is disabled. */
1008         case DCA_PROVIDER_REMOVE:
1009                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1010                         dca_remove_requester(dev);
1011                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1012                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1013                 }
1014                 break;
1015         }
1016
1017         return 0;
1018 }
1019 #endif /* CONFIG_IXGBE_DCA */
1020
1021 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1022                                  struct sk_buff *skb)
1023 {
1024         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1025 }
1026
1027 /**
1028  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1029  * @adapter: address of board private structure
1030  * @rx_desc: advanced rx descriptor
1031  *
1032  * Returns : true if it is FCoE pkt
1033  */
1034 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1035                                     union ixgbe_adv_rx_desc *rx_desc)
1036 {
1037         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1038
1039         return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1040                ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1041                 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1042                              IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1043 }
1044
1045 /**
1046  * ixgbe_receive_skb - Send a completed packet up the stack
1047  * @adapter: board private structure
1048  * @skb: packet to send up
1049  * @status: hardware indication of status of receive
1050  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1051  * @rx_desc: rx descriptor
1052  **/
1053 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1054                               struct sk_buff *skb, u8 status,
1055                               struct ixgbe_ring *ring,
1056                               union ixgbe_adv_rx_desc *rx_desc)
1057 {
1058         struct ixgbe_adapter *adapter = q_vector->adapter;
1059         struct napi_struct *napi = &q_vector->napi;
1060         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1061         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1062
1063         if (is_vlan && (tag & VLAN_VID_MASK))
1064                 __vlan_hwaccel_put_tag(skb, tag);
1065
1066         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1067                 napi_gro_receive(napi, skb);
1068         else
1069                 netif_rx(skb);
1070 }
1071
1072 /**
1073  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1074  * @adapter: address of board private structure
1075  * @status_err: hardware indication of status of receive
1076  * @skb: skb currently being received and modified
1077  * @status_err: status error value of last descriptor in packet
1078  **/
1079 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1080                                      union ixgbe_adv_rx_desc *rx_desc,
1081                                      struct sk_buff *skb,
1082                                      u32 status_err)
1083 {
1084         skb->ip_summed = CHECKSUM_NONE;
1085
1086         /* Rx csum disabled */
1087         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1088                 return;
1089
1090         /* if IP and error */
1091         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1092             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1093                 adapter->hw_csum_rx_error++;
1094                 return;
1095         }
1096
1097         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1098                 return;
1099
1100         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1101                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1102
1103                 /*
1104                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1105                  * checksum errors.
1106                  */
1107                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1108                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1109                         return;
1110
1111                 adapter->hw_csum_rx_error++;
1112                 return;
1113         }
1114
1115         /* It must be a TCP or UDP packet with a valid checksum */
1116         skb->ip_summed = CHECKSUM_UNNECESSARY;
1117 }
1118
1119 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1120 {
1121         /*
1122          * Force memory writes to complete before letting h/w
1123          * know there are new descriptors to fetch.  (Only
1124          * applicable for weak-ordered memory model archs,
1125          * such as IA-64).
1126          */
1127         wmb();
1128         writel(val, rx_ring->tail);
1129 }
1130
1131 /**
1132  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1133  * @rx_ring: ring to place buffers on
1134  * @cleaned_count: number of buffers to replace
1135  **/
1136 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1137 {
1138         union ixgbe_adv_rx_desc *rx_desc;
1139         struct ixgbe_rx_buffer *bi;
1140         struct sk_buff *skb;
1141         u16 i = rx_ring->next_to_use;
1142
1143         /* do nothing if no valid netdev defined */
1144         if (!rx_ring->netdev)
1145                 return;
1146
1147         while (cleaned_count--) {
1148                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1149                 bi = &rx_ring->rx_buffer_info[i];
1150                 skb = bi->skb;
1151
1152                 if (!skb) {
1153                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1154                                                         rx_ring->rx_buf_len);
1155                         if (!skb) {
1156                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1157                                 goto no_buffers;
1158                         }
1159                         /* initialize queue mapping */
1160                         skb_record_rx_queue(skb, rx_ring->queue_index);
1161                         bi->skb = skb;
1162                 }
1163
1164                 if (!bi->dma) {
1165                         bi->dma = dma_map_single(rx_ring->dev,
1166                                                  skb->data,
1167                                                  rx_ring->rx_buf_len,
1168                                                  DMA_FROM_DEVICE);
1169                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1170                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1171                                 bi->dma = 0;
1172                                 goto no_buffers;
1173                         }
1174                 }
1175
1176                 if (ring_is_ps_enabled(rx_ring)) {
1177                         if (!bi->page) {
1178                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1179                                 if (!bi->page) {
1180                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1181                                         goto no_buffers;
1182                                 }
1183                         }
1184
1185                         if (!bi->page_dma) {
1186                                 /* use a half page if we're re-using */
1187                                 bi->page_offset ^= PAGE_SIZE / 2;
1188                                 bi->page_dma = dma_map_page(rx_ring->dev,
1189                                                             bi->page,
1190                                                             bi->page_offset,
1191                                                             PAGE_SIZE / 2,
1192                                                             DMA_FROM_DEVICE);
1193                                 if (dma_mapping_error(rx_ring->dev,
1194                                                       bi->page_dma)) {
1195                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1196                                         bi->page_dma = 0;
1197                                         goto no_buffers;
1198                                 }
1199                         }
1200
1201                         /* Refresh the desc even if buffer_addrs didn't change
1202                          * because each write-back erases this info. */
1203                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1204                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1205                 } else {
1206                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1207                         rx_desc->read.hdr_addr = 0;
1208                 }
1209
1210                 i++;
1211                 if (i == rx_ring->count)
1212                         i = 0;
1213         }
1214
1215 no_buffers:
1216         if (rx_ring->next_to_use != i) {
1217                 rx_ring->next_to_use = i;
1218                 ixgbe_release_rx_desc(rx_ring, i);
1219         }
1220 }
1221
1222 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1223 {
1224         /* HW will not DMA in data larger than the given buffer, even if it
1225          * parses the (NFS, of course) header to be larger.  In that case, it
1226          * fills the header buffer and spills the rest into the page.
1227          */
1228         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1229         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1230                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1231         if (hlen > IXGBE_RX_HDR_SIZE)
1232                 hlen = IXGBE_RX_HDR_SIZE;
1233         return hlen;
1234 }
1235
1236 /**
1237  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1238  * @skb: pointer to the last skb in the rsc queue
1239  *
1240  * This function changes a queue full of hw rsc buffers into a completed
1241  * packet.  It uses the ->prev pointers to find the first packet and then
1242  * turns it into the frag list owner.
1243  **/
1244 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1245 {
1246         unsigned int frag_list_size = 0;
1247         unsigned int skb_cnt = 1;
1248
1249         while (skb->prev) {
1250                 struct sk_buff *prev = skb->prev;
1251                 frag_list_size += skb->len;
1252                 skb->prev = NULL;
1253                 skb = prev;
1254                 skb_cnt++;
1255         }
1256
1257         skb_shinfo(skb)->frag_list = skb->next;
1258         skb->next = NULL;
1259         skb->len += frag_list_size;
1260         skb->data_len += frag_list_size;
1261         skb->truesize += frag_list_size;
1262         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1263
1264         return skb;
1265 }
1266
1267 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1268 {
1269         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1270                 IXGBE_RXDADV_RSCCNT_MASK);
1271 }
1272
1273 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1274                                struct ixgbe_ring *rx_ring,
1275                                int budget)
1276 {
1277         struct ixgbe_adapter *adapter = q_vector->adapter;
1278         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1279         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1280         struct sk_buff *skb;
1281         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1282         const int current_node = numa_node_id();
1283 #ifdef IXGBE_FCOE
1284         int ddp_bytes = 0;
1285 #endif /* IXGBE_FCOE */
1286         u32 staterr;
1287         u16 i;
1288         u16 cleaned_count = 0;
1289         bool pkt_is_rsc = false;
1290
1291         i = rx_ring->next_to_clean;
1292         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1293         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1294
1295         while (staterr & IXGBE_RXD_STAT_DD) {
1296                 u32 upper_len = 0;
1297
1298                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1299
1300                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1301
1302                 skb = rx_buffer_info->skb;
1303                 rx_buffer_info->skb = NULL;
1304                 prefetch(skb->data);
1305
1306                 if (ring_is_rsc_enabled(rx_ring))
1307                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1308
1309                 /* if this is a skb from previous receive DMA will be 0 */
1310                 if (rx_buffer_info->dma) {
1311                         u16 hlen;
1312                         if (pkt_is_rsc &&
1313                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1314                             !skb->prev) {
1315                                 /*
1316                                  * When HWRSC is enabled, delay unmapping
1317                                  * of the first packet. It carries the
1318                                  * header information, HW may still
1319                                  * access the header after the writeback.
1320                                  * Only unmap it when EOP is reached
1321                                  */
1322                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1323                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1324                         } else {
1325                                 dma_unmap_single(rx_ring->dev,
1326                                                  rx_buffer_info->dma,
1327                                                  rx_ring->rx_buf_len,
1328                                                  DMA_FROM_DEVICE);
1329                         }
1330                         rx_buffer_info->dma = 0;
1331
1332                         if (ring_is_ps_enabled(rx_ring)) {
1333                                 hlen = ixgbe_get_hlen(rx_desc);
1334                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1335                         } else {
1336                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1337                         }
1338
1339                         skb_put(skb, hlen);
1340                 } else {
1341                         /* assume packet split since header is unmapped */
1342                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1343                 }
1344
1345                 if (upper_len) {
1346                         dma_unmap_page(rx_ring->dev,
1347                                        rx_buffer_info->page_dma,
1348                                        PAGE_SIZE / 2,
1349                                        DMA_FROM_DEVICE);
1350                         rx_buffer_info->page_dma = 0;
1351                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1352                                            rx_buffer_info->page,
1353                                            rx_buffer_info->page_offset,
1354                                            upper_len);
1355
1356                         if ((page_count(rx_buffer_info->page) == 1) &&
1357                             (page_to_nid(rx_buffer_info->page) == current_node))
1358                                 get_page(rx_buffer_info->page);
1359                         else
1360                                 rx_buffer_info->page = NULL;
1361
1362                         skb->len += upper_len;
1363                         skb->data_len += upper_len;
1364                         skb->truesize += upper_len;
1365                 }
1366
1367                 i++;
1368                 if (i == rx_ring->count)
1369                         i = 0;
1370
1371                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1372                 prefetch(next_rxd);
1373                 cleaned_count++;
1374
1375                 if (pkt_is_rsc) {
1376                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1377                                      IXGBE_RXDADV_NEXTP_SHIFT;
1378                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1379                 } else {
1380                         next_buffer = &rx_ring->rx_buffer_info[i];
1381                 }
1382
1383                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1384                         if (ring_is_ps_enabled(rx_ring)) {
1385                                 rx_buffer_info->skb = next_buffer->skb;
1386                                 rx_buffer_info->dma = next_buffer->dma;
1387                                 next_buffer->skb = skb;
1388                                 next_buffer->dma = 0;
1389                         } else {
1390                                 skb->next = next_buffer->skb;
1391                                 skb->next->prev = skb;
1392                         }
1393                         rx_ring->rx_stats.non_eop_descs++;
1394                         goto next_desc;
1395                 }
1396
1397                 if (skb->prev) {
1398                         skb = ixgbe_transform_rsc_queue(skb);
1399                         /* if we got here without RSC the packet is invalid */
1400                         if (!pkt_is_rsc) {
1401                                 __pskb_trim(skb, 0);
1402                                 rx_buffer_info->skb = skb;
1403                                 goto next_desc;
1404                         }
1405                 }
1406
1407                 if (ring_is_rsc_enabled(rx_ring)) {
1408                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1409                                 dma_unmap_single(rx_ring->dev,
1410                                                  IXGBE_RSC_CB(skb)->dma,
1411                                                  rx_ring->rx_buf_len,
1412                                                  DMA_FROM_DEVICE);
1413                                 IXGBE_RSC_CB(skb)->dma = 0;
1414                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1415                         }
1416                 }
1417                 if (pkt_is_rsc) {
1418                         if (ring_is_ps_enabled(rx_ring))
1419                                 rx_ring->rx_stats.rsc_count +=
1420                                         skb_shinfo(skb)->nr_frags;
1421                         else
1422                                 rx_ring->rx_stats.rsc_count +=
1423                                         IXGBE_RSC_CB(skb)->skb_cnt;
1424                         rx_ring->rx_stats.rsc_flush++;
1425                 }
1426
1427                 /* ERR_MASK will only have valid bits if EOP set */
1428                 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1429                         dev_kfree_skb_any(skb);
1430                         goto next_desc;
1431                 }
1432
1433                 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1434                 if (adapter->netdev->features & NETIF_F_RXHASH)
1435                         ixgbe_rx_hash(rx_desc, skb);
1436
1437                 /* probably a little skewed due to removing CRC */
1438                 total_rx_bytes += skb->len;
1439                 total_rx_packets++;
1440
1441                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1442 #ifdef IXGBE_FCOE
1443                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1444                 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1445                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1446                                                    staterr);
1447                         if (!ddp_bytes) {
1448                                 dev_kfree_skb_any(skb);
1449                                 goto next_desc;
1450                         }
1451                 }
1452 #endif /* IXGBE_FCOE */
1453                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1454
1455                 budget--;
1456 next_desc:
1457                 rx_desc->wb.upper.status_error = 0;
1458
1459                 if (!budget)
1460                         break;
1461
1462                 /* return some buffers to hardware, one at a time is too slow */
1463                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1464                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1465                         cleaned_count = 0;
1466                 }
1467
1468                 /* use prefetched values */
1469                 rx_desc = next_rxd;
1470                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1471         }
1472
1473         rx_ring->next_to_clean = i;
1474         cleaned_count = ixgbe_desc_unused(rx_ring);
1475
1476         if (cleaned_count)
1477                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1478
1479 #ifdef IXGBE_FCOE
1480         /* include DDPed FCoE data */
1481         if (ddp_bytes > 0) {
1482                 unsigned int mss;
1483
1484                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1485                         sizeof(struct fc_frame_header) -
1486                         sizeof(struct fcoe_crc_eof);
1487                 if (mss > 512)
1488                         mss &= ~511;
1489                 total_rx_bytes += ddp_bytes;
1490                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1491         }
1492 #endif /* IXGBE_FCOE */
1493
1494         u64_stats_update_begin(&rx_ring->syncp);
1495         rx_ring->stats.packets += total_rx_packets;
1496         rx_ring->stats.bytes += total_rx_bytes;
1497         u64_stats_update_end(&rx_ring->syncp);
1498         q_vector->rx.total_packets += total_rx_packets;
1499         q_vector->rx.total_bytes += total_rx_bytes;
1500
1501         return !!budget;
1502 }
1503
1504 /**
1505  * ixgbe_configure_msix - Configure MSI-X hardware
1506  * @adapter: board private structure
1507  *
1508  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1509  * interrupts.
1510  **/
1511 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1512 {
1513         struct ixgbe_q_vector *q_vector;
1514         int q_vectors, v_idx;
1515         u32 mask;
1516
1517         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1518
1519         /*
1520          * Populate the IVAR table and set the ITR values to the
1521          * corresponding register.
1522          */
1523         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1524                 struct ixgbe_ring *ring;
1525                 q_vector = adapter->q_vector[v_idx];
1526
1527                 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1528                         ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1529
1530                 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1531                         ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1532
1533                 if (q_vector->tx.ring && !q_vector->rx.ring)
1534                         /* tx only */
1535                         q_vector->eitr = adapter->tx_eitr_param;
1536                 else if (q_vector->rx.ring)
1537                         /* rx or mixed */
1538                         q_vector->eitr = adapter->rx_eitr_param;
1539
1540                 ixgbe_write_eitr(q_vector);
1541         }
1542
1543         switch (adapter->hw.mac.type) {
1544         case ixgbe_mac_82598EB:
1545                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1546                                v_idx);
1547                 break;
1548         case ixgbe_mac_82599EB:
1549         case ixgbe_mac_X540:
1550                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1551                 break;
1552
1553         default:
1554                 break;
1555         }
1556         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1557
1558         /* set up to autoclear timer, and the vectors */
1559         mask = IXGBE_EIMS_ENABLE_MASK;
1560         if (adapter->num_vfs)
1561                 mask &= ~(IXGBE_EIMS_OTHER |
1562                           IXGBE_EIMS_MAILBOX |
1563                           IXGBE_EIMS_LSC);
1564         else
1565                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1566         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1567 }
1568
1569 enum latency_range {
1570         lowest_latency = 0,
1571         low_latency = 1,
1572         bulk_latency = 2,
1573         latency_invalid = 255
1574 };
1575
1576 /**
1577  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1578  * @q_vector: structure containing interrupt and ring information
1579  * @ring_container: structure containing ring performance data
1580  *
1581  *      Stores a new ITR value based on packets and byte
1582  *      counts during the last interrupt.  The advantage of per interrupt
1583  *      computation is faster updates and more accurate ITR for the current
1584  *      traffic pattern.  Constants in this function were computed
1585  *      based on theoretical maximum wire speed and thresholds were set based
1586  *      on testing data as well as attempting to minimize response time
1587  *      while increasing bulk throughput.
1588  *      this functionality is controlled by the InterruptThrottleRate module
1589  *      parameter (see ixgbe_param.c)
1590  **/
1591 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1592                              struct ixgbe_ring_container *ring_container)
1593 {
1594         u64 bytes_perint;
1595         struct ixgbe_adapter *adapter = q_vector->adapter;
1596         int bytes = ring_container->total_bytes;
1597         int packets = ring_container->total_packets;
1598         u32 timepassed_us;
1599         u8 itr_setting = ring_container->itr;
1600
1601         if (packets == 0)
1602                 return;
1603
1604         /* simple throttlerate management
1605          *    0-20MB/s lowest (100000 ints/s)
1606          *   20-100MB/s low   (20000 ints/s)
1607          *  100-1249MB/s bulk (8000 ints/s)
1608          */
1609         /* what was last interrupt timeslice? */
1610         timepassed_us = 1000000/q_vector->eitr;
1611         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1612
1613         switch (itr_setting) {
1614         case lowest_latency:
1615                 if (bytes_perint > adapter->eitr_low)
1616                         itr_setting = low_latency;
1617                 break;
1618         case low_latency:
1619                 if (bytes_perint > adapter->eitr_high)
1620                         itr_setting = bulk_latency;
1621                 else if (bytes_perint <= adapter->eitr_low)
1622                         itr_setting = lowest_latency;
1623                 break;
1624         case bulk_latency:
1625                 if (bytes_perint <= adapter->eitr_high)
1626                         itr_setting = low_latency;
1627                 break;
1628         }
1629
1630         /* clear work counters since we have the values we need */
1631         ring_container->total_bytes = 0;
1632         ring_container->total_packets = 0;
1633
1634         /* write updated itr to ring container */
1635         ring_container->itr = itr_setting;
1636 }
1637
1638 /**
1639  * ixgbe_write_eitr - write EITR register in hardware specific way
1640  * @q_vector: structure containing interrupt and ring information
1641  *
1642  * This function is made to be called by ethtool and by the driver
1643  * when it needs to update EITR registers at runtime.  Hardware
1644  * specific quirks/differences are taken care of here.
1645  */
1646 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1647 {
1648         struct ixgbe_adapter *adapter = q_vector->adapter;
1649         struct ixgbe_hw *hw = &adapter->hw;
1650         int v_idx = q_vector->v_idx;
1651         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1652
1653         switch (adapter->hw.mac.type) {
1654         case ixgbe_mac_82598EB:
1655                 /* must write high and low 16 bits to reset counter */
1656                 itr_reg |= (itr_reg << 16);
1657                 break;
1658         case ixgbe_mac_82599EB:
1659         case ixgbe_mac_X540:
1660                 /*
1661                  * 82599 and X540 can support a value of zero, so allow it for
1662                  * max interrupt rate, but there is an errata where it can
1663                  * not be zero with RSC
1664                  */
1665                 if (itr_reg == 8 &&
1666                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1667                         itr_reg = 0;
1668
1669                 /*
1670                  * set the WDIS bit to not clear the timer bits and cause an
1671                  * immediate assertion of the interrupt
1672                  */
1673                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1674                 break;
1675         default:
1676                 break;
1677         }
1678         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1679 }
1680
1681 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1682 {
1683         u32 new_itr = q_vector->eitr;
1684         u8 current_itr;
1685
1686         ixgbe_update_itr(q_vector, &q_vector->tx);
1687         ixgbe_update_itr(q_vector, &q_vector->rx);
1688
1689         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1690
1691         switch (current_itr) {
1692         /* counts and packets in update_itr are dependent on these numbers */
1693         case lowest_latency:
1694                 new_itr = 100000;
1695                 break;
1696         case low_latency:
1697                 new_itr = 20000; /* aka hwitr = ~200 */
1698                 break;
1699         case bulk_latency:
1700                 new_itr = 8000;
1701                 break;
1702         default:
1703                 break;
1704         }
1705
1706         if (new_itr != q_vector->eitr) {
1707                 /* do an exponential smoothing */
1708                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1709
1710                 /* save the algorithm value here */
1711                 q_vector->eitr = new_itr;
1712
1713                 ixgbe_write_eitr(q_vector);
1714         }
1715 }
1716
1717 /**
1718  * ixgbe_check_overtemp_subtask - check for over tempurature
1719  * @adapter: pointer to adapter
1720  **/
1721 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1722 {
1723         struct ixgbe_hw *hw = &adapter->hw;
1724         u32 eicr = adapter->interrupt_event;
1725
1726         if (test_bit(__IXGBE_DOWN, &adapter->state))
1727                 return;
1728
1729         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1730             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1731                 return;
1732
1733         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1734
1735         switch (hw->device_id) {
1736         case IXGBE_DEV_ID_82599_T3_LOM:
1737                 /*
1738                  * Since the warning interrupt is for both ports
1739                  * we don't have to check if:
1740                  *  - This interrupt wasn't for our port.
1741                  *  - We may have missed the interrupt so always have to
1742                  *    check if we  got a LSC
1743                  */
1744                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1745                     !(eicr & IXGBE_EICR_LSC))
1746                         return;
1747
1748                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1749                         u32 autoneg;
1750                         bool link_up = false;
1751
1752                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1753
1754                         if (link_up)
1755                                 return;
1756                 }
1757
1758                 /* Check if this is not due to overtemp */
1759                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1760                         return;
1761
1762                 break;
1763         default:
1764                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1765                         return;
1766                 break;
1767         }
1768         e_crit(drv,
1769                "Network adapter has been stopped because it has over heated. "
1770                "Restart the computer. If the problem persists, "
1771                "power off the system and replace the adapter\n");
1772
1773         adapter->interrupt_event = 0;
1774 }
1775
1776 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1777 {
1778         struct ixgbe_hw *hw = &adapter->hw;
1779
1780         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1781             (eicr & IXGBE_EICR_GPI_SDP1)) {
1782                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1783                 /* write to clear the interrupt */
1784                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1785         }
1786 }
1787
1788 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1789 {
1790         struct ixgbe_hw *hw = &adapter->hw;
1791
1792         if (eicr & IXGBE_EICR_GPI_SDP2) {
1793                 /* Clear the interrupt */
1794                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1795                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1796                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1797                         ixgbe_service_event_schedule(adapter);
1798                 }
1799         }
1800
1801         if (eicr & IXGBE_EICR_GPI_SDP1) {
1802                 /* Clear the interrupt */
1803                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1804                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1805                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1806                         ixgbe_service_event_schedule(adapter);
1807                 }
1808         }
1809 }
1810
1811 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1812 {
1813         struct ixgbe_hw *hw = &adapter->hw;
1814
1815         adapter->lsc_int++;
1816         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1817         adapter->link_check_timeout = jiffies;
1818         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1819                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1820                 IXGBE_WRITE_FLUSH(hw);
1821                 ixgbe_service_event_schedule(adapter);
1822         }
1823 }
1824
1825 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1826 {
1827         struct ixgbe_adapter *adapter = data;
1828         struct ixgbe_hw *hw = &adapter->hw;
1829         u32 eicr;
1830
1831         /*
1832          * Workaround for Silicon errata.  Use clear-by-write instead
1833          * of clear-by-read.  Reading with EICS will return the
1834          * interrupt causes without clearing, which later be done
1835          * with the write to EICR.
1836          */
1837         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1838         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1839
1840         if (eicr & IXGBE_EICR_LSC)
1841                 ixgbe_check_lsc(adapter);
1842
1843         if (eicr & IXGBE_EICR_MAILBOX)
1844                 ixgbe_msg_task(adapter);
1845
1846         switch (hw->mac.type) {
1847         case ixgbe_mac_82599EB:
1848         case ixgbe_mac_X540:
1849                 /* Handle Flow Director Full threshold interrupt */
1850                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1851                         int reinit_count = 0;
1852                         int i;
1853                         for (i = 0; i < adapter->num_tx_queues; i++) {
1854                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1855                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1856                                                        &ring->state))
1857                                         reinit_count++;
1858                         }
1859                         if (reinit_count) {
1860                                 /* no more flow director interrupts until after init */
1861                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1862                                 eicr &= ~IXGBE_EICR_FLOW_DIR;
1863                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1864                                 ixgbe_service_event_schedule(adapter);
1865                         }
1866                 }
1867                 ixgbe_check_sfp_event(adapter, eicr);
1868                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1869                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1870                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1871                                 adapter->interrupt_event = eicr;
1872                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1873                                 ixgbe_service_event_schedule(adapter);
1874                         }
1875                 }
1876                 break;
1877         default:
1878                 break;
1879         }
1880
1881         ixgbe_check_fan_failure(adapter, eicr);
1882
1883         /* re-enable the original interrupt state, no lsc, no queues */
1884         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1885                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1886                                 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1887
1888         return IRQ_HANDLED;
1889 }
1890
1891 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1892                                            u64 qmask)
1893 {
1894         u32 mask;
1895         struct ixgbe_hw *hw = &adapter->hw;
1896
1897         switch (hw->mac.type) {
1898         case ixgbe_mac_82598EB:
1899                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1900                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1901                 break;
1902         case ixgbe_mac_82599EB:
1903         case ixgbe_mac_X540:
1904                 mask = (qmask & 0xFFFFFFFF);
1905                 if (mask)
1906                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1907                 mask = (qmask >> 32);
1908                 if (mask)
1909                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1910                 break;
1911         default:
1912                 break;
1913         }
1914         /* skip the flush */
1915 }
1916
1917 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1918                                             u64 qmask)
1919 {
1920         u32 mask;
1921         struct ixgbe_hw *hw = &adapter->hw;
1922
1923         switch (hw->mac.type) {
1924         case ixgbe_mac_82598EB:
1925                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1927                 break;
1928         case ixgbe_mac_82599EB:
1929         case ixgbe_mac_X540:
1930                 mask = (qmask & 0xFFFFFFFF);
1931                 if (mask)
1932                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1933                 mask = (qmask >> 32);
1934                 if (mask)
1935                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1936                 break;
1937         default:
1938                 break;
1939         }
1940         /* skip the flush */
1941 }
1942
1943 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1944 {
1945         struct ixgbe_q_vector *q_vector = data;
1946
1947         /* EIAM disabled interrupts (on this vector) for us */
1948
1949         if (q_vector->rx.ring || q_vector->tx.ring)
1950                 napi_schedule(&q_vector->napi);
1951
1952         return IRQ_HANDLED;
1953 }
1954
1955 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1956                                      int r_idx)
1957 {
1958         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1959         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
1960
1961         rx_ring->q_vector = q_vector;
1962         rx_ring->next = q_vector->rx.ring;
1963         q_vector->rx.ring = rx_ring;
1964         q_vector->rx.count++;
1965 }
1966
1967 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1968                                      int t_idx)
1969 {
1970         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1971         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
1972
1973         tx_ring->q_vector = q_vector;
1974         tx_ring->next = q_vector->tx.ring;
1975         q_vector->tx.ring = tx_ring;
1976         q_vector->tx.count++;
1977         q_vector->tx.work_limit = a->tx_work_limit;
1978 }
1979
1980 /**
1981  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1982  * @adapter: board private structure to initialize
1983  *
1984  * This function maps descriptor rings to the queue-specific vectors
1985  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1986  * one vector per ring/queue, but on a constrained vector budget, we
1987  * group the rings as "efficiently" as possible.  You would add new
1988  * mapping configurations in here.
1989  **/
1990 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
1991 {
1992         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1993         int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
1994         int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
1995         int v_start = 0;
1996
1997         /* only one q_vector if MSI-X is disabled. */
1998         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1999                 q_vectors = 1;
2000
2001         /*
2002          * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2003          * group them so there are multiple queues per vector.
2004          *
2005          * Re-adjusting *qpv takes care of the remainder.
2006          */
2007         for (; v_start < q_vectors && rxr_remaining; v_start++) {
2008                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2009                 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2010                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2011         }
2012
2013         /*
2014          * If there are not enough q_vectors for each ring to have it's own
2015          * vector then we must pair up Rx/Tx on a each vector
2016          */
2017         if ((v_start + txr_remaining) > q_vectors)
2018                 v_start = 0;
2019
2020         for (; v_start < q_vectors && txr_remaining; v_start++) {
2021                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2022                 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2023                         map_vector_to_txq(adapter, v_start, txr_idx);
2024         }
2025 }
2026
2027 /**
2028  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2029  * @adapter: board private structure
2030  *
2031  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2032  * interrupts from the kernel.
2033  **/
2034 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2035 {
2036         struct net_device *netdev = adapter->netdev;
2037         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2038         int vector, err;
2039         int ri = 0, ti = 0;
2040
2041         for (vector = 0; vector < q_vectors; vector++) {
2042                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2043                 struct msix_entry *entry = &adapter->msix_entries[vector];
2044
2045                 if (q_vector->tx.ring && q_vector->rx.ring) {
2046                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2047                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2048                         ti++;
2049                 } else if (q_vector->rx.ring) {
2050                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2051                                  "%s-%s-%d", netdev->name, "rx", ri++);
2052                 } else if (q_vector->tx.ring) {
2053                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2054                                  "%s-%s-%d", netdev->name, "tx", ti++);
2055                 } else {
2056                         /* skip this unused q_vector */
2057                         continue;
2058                 }
2059                 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2060                                   q_vector->name, q_vector);
2061                 if (err) {
2062                         e_err(probe, "request_irq failed for MSIX interrupt "
2063                               "Error: %d\n", err);
2064                         goto free_queue_irqs;
2065                 }
2066                 /* If Flow Director is enabled, set interrupt affinity */
2067                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2068                         /* assign the mask for this irq */
2069                         irq_set_affinity_hint(entry->vector,
2070                                               q_vector->affinity_mask);
2071                 }
2072         }
2073
2074         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2075         err = request_irq(adapter->msix_entries[vector].vector,
2076                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2077         if (err) {
2078                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2079                 goto free_queue_irqs;
2080         }
2081
2082         return 0;
2083
2084 free_queue_irqs:
2085         while (vector) {
2086                 vector--;
2087                 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2088                                       NULL);
2089                 free_irq(adapter->msix_entries[vector].vector,
2090                          adapter->q_vector[vector]);
2091         }
2092         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2093         pci_disable_msix(adapter->pdev);
2094         kfree(adapter->msix_entries);
2095         adapter->msix_entries = NULL;
2096         return err;
2097 }
2098
2099 /**
2100  * ixgbe_irq_enable - Enable default interrupt generation settings
2101  * @adapter: board private structure
2102  **/
2103 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2104                                     bool flush)
2105 {
2106         u32 mask;
2107
2108         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2109         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2110                 mask |= IXGBE_EIMS_GPI_SDP0;
2111         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2112                 mask |= IXGBE_EIMS_GPI_SDP1;
2113         switch (adapter->hw.mac.type) {
2114         case ixgbe_mac_82599EB:
2115         case ixgbe_mac_X540:
2116                 mask |= IXGBE_EIMS_ECC;
2117                 mask |= IXGBE_EIMS_GPI_SDP1;
2118                 mask |= IXGBE_EIMS_GPI_SDP2;
2119                 if (adapter->num_vfs)
2120                         mask |= IXGBE_EIMS_MAILBOX;
2121                 break;
2122         default:
2123                 break;
2124         }
2125         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2126                 mask |= IXGBE_EIMS_FLOW_DIR;
2127
2128         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2129         if (queues)
2130                 ixgbe_irq_enable_queues(adapter, ~0);
2131         if (flush)
2132                 IXGBE_WRITE_FLUSH(&adapter->hw);
2133
2134         if (adapter->num_vfs > 32) {
2135                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2136                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2137         }
2138 }
2139
2140 /**
2141  * ixgbe_intr - legacy mode Interrupt Handler
2142  * @irq: interrupt number
2143  * @data: pointer to a network interface device structure
2144  **/
2145 static irqreturn_t ixgbe_intr(int irq, void *data)
2146 {
2147         struct ixgbe_adapter *adapter = data;
2148         struct ixgbe_hw *hw = &adapter->hw;
2149         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2150         u32 eicr;
2151
2152         /*
2153          * Workaround for silicon errata on 82598.  Mask the interrupts
2154          * before the read of EICR.
2155          */
2156         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2157
2158         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2159          * therefore no explict interrupt disable is necessary */
2160         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2161         if (!eicr) {
2162                 /*
2163                  * shared interrupt alert!
2164                  * make sure interrupts are enabled because the read will
2165                  * have disabled interrupts due to EIAM
2166                  * finish the workaround of silicon errata on 82598.  Unmask
2167                  * the interrupt that we masked before the EICR read.
2168                  */
2169                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2170                         ixgbe_irq_enable(adapter, true, true);
2171                 return IRQ_NONE;        /* Not our interrupt */
2172         }
2173
2174         if (eicr & IXGBE_EICR_LSC)
2175                 ixgbe_check_lsc(adapter);
2176
2177         switch (hw->mac.type) {
2178         case ixgbe_mac_82599EB:
2179                 ixgbe_check_sfp_event(adapter, eicr);
2180                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2181                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2182                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2183                                 adapter->interrupt_event = eicr;
2184                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2185                                 ixgbe_service_event_schedule(adapter);
2186                         }
2187                 }
2188                 break;
2189         default:
2190                 break;
2191         }
2192
2193         ixgbe_check_fan_failure(adapter, eicr);
2194
2195         if (napi_schedule_prep(&(q_vector->napi))) {
2196                 /* would disable interrupts here but EIAM disabled it */
2197                 __napi_schedule(&(q_vector->napi));
2198         }
2199
2200         /*
2201          * re-enable link(maybe) and non-queue interrupts, no flush.
2202          * ixgbe_poll will re-enable the queue interrupts
2203          */
2204
2205         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2206                 ixgbe_irq_enable(adapter, false, false);
2207
2208         return IRQ_HANDLED;
2209 }
2210
2211 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2212 {
2213         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2214         int i;
2215
2216         /* legacy and MSI only use one vector */
2217         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2218                 q_vectors = 1;
2219
2220         for (i = 0; i < adapter->num_rx_queues; i++) {
2221                 adapter->rx_ring[i]->q_vector = NULL;
2222                 adapter->rx_ring[i]->next = NULL;
2223         }
2224         for (i = 0; i < adapter->num_tx_queues; i++) {
2225                 adapter->tx_ring[i]->q_vector = NULL;
2226                 adapter->tx_ring[i]->next = NULL;
2227         }
2228
2229         for (i = 0; i < q_vectors; i++) {
2230                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2231                 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2232                 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2233         }
2234 }
2235
2236 /**
2237  * ixgbe_request_irq - initialize interrupts
2238  * @adapter: board private structure
2239  *
2240  * Attempts to configure interrupts using the best available
2241  * capabilities of the hardware and kernel.
2242  **/
2243 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2244 {
2245         struct net_device *netdev = adapter->netdev;
2246         int err;
2247
2248         /* map all of the rings to the q_vectors */
2249         ixgbe_map_rings_to_vectors(adapter);
2250
2251         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2252                 err = ixgbe_request_msix_irqs(adapter);
2253         else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2254                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2255                                   netdev->name, adapter);
2256         else
2257                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2258                                   netdev->name, adapter);
2259
2260         if (err) {
2261                 e_err(probe, "request_irq failed, Error %d\n", err);
2262
2263                 /* place q_vectors and rings back into a known good state */
2264                 ixgbe_reset_q_vectors(adapter);
2265         }
2266
2267         return err;
2268 }
2269
2270 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2271 {
2272         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2273                 int i, q_vectors;
2274
2275                 q_vectors = adapter->num_msix_vectors;
2276                 i = q_vectors - 1;
2277                 free_irq(adapter->msix_entries[i].vector, adapter);
2278                 i--;
2279
2280                 for (; i >= 0; i--) {
2281                         /* free only the irqs that were actually requested */
2282                         if (!adapter->q_vector[i]->rx.ring &&
2283                             !adapter->q_vector[i]->tx.ring)
2284                                 continue;
2285
2286                         /* clear the affinity_mask in the IRQ descriptor */
2287                         irq_set_affinity_hint(adapter->msix_entries[i].vector,
2288                                               NULL);
2289
2290                         free_irq(adapter->msix_entries[i].vector,
2291                                  adapter->q_vector[i]);
2292                 }
2293         } else {
2294                 free_irq(adapter->pdev->irq, adapter);
2295         }
2296
2297         /* clear q_vector state information */
2298         ixgbe_reset_q_vectors(adapter);
2299 }
2300
2301 /**
2302  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2303  * @adapter: board private structure
2304  **/
2305 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2306 {
2307         switch (adapter->hw.mac.type) {
2308         case ixgbe_mac_82598EB:
2309                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2310                 break;
2311         case ixgbe_mac_82599EB:
2312         case ixgbe_mac_X540:
2313                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2314                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2315                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2316                 if (adapter->num_vfs > 32)
2317                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2318                 break;
2319         default:
2320                 break;
2321         }
2322         IXGBE_WRITE_FLUSH(&adapter->hw);
2323         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2324                 int i;
2325                 for (i = 0; i < adapter->num_msix_vectors; i++)
2326                         synchronize_irq(adapter->msix_entries[i].vector);
2327         } else {
2328                 synchronize_irq(adapter->pdev->irq);
2329         }
2330 }
2331
2332 /**
2333  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2334  *
2335  **/
2336 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2337 {
2338         struct ixgbe_hw *hw = &adapter->hw;
2339
2340         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2341                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2342
2343         ixgbe_set_ivar(adapter, 0, 0, 0);
2344         ixgbe_set_ivar(adapter, 1, 0, 0);
2345
2346         e_info(hw, "Legacy interrupt IVAR setup done\n");
2347 }
2348
2349 /**
2350  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2351  * @adapter: board private structure
2352  * @ring: structure containing ring specific data
2353  *
2354  * Configure the Tx descriptor ring after a reset.
2355  **/
2356 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2357                              struct ixgbe_ring *ring)
2358 {
2359         struct ixgbe_hw *hw = &adapter->hw;
2360         u64 tdba = ring->dma;
2361         int wait_loop = 10;
2362         u32 txdctl = IXGBE_TXDCTL_ENABLE;
2363         u8 reg_idx = ring->reg_idx;
2364
2365         /* disable queue to avoid issues while updating state */
2366         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2367         IXGBE_WRITE_FLUSH(hw);
2368
2369         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2370                         (tdba & DMA_BIT_MASK(32)));
2371         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2372         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2373                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2374         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2375         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2376         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2377
2378         /*
2379          * set WTHRESH to encourage burst writeback, it should not be set
2380          * higher than 1 when ITR is 0 as it could cause false TX hangs
2381          *
2382          * In order to avoid issues WTHRESH + PTHRESH should always be equal
2383          * to or less than the number of on chip descriptors, which is
2384          * currently 40.
2385          */
2386         if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2387                 txdctl |= (1 << 16);    /* WTHRESH = 1 */
2388         else
2389                 txdctl |= (8 << 16);    /* WTHRESH = 8 */
2390
2391         /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2392         txdctl |= (1 << 8) |    /* HTHRESH = 1 */
2393                    32;          /* PTHRESH = 32 */
2394
2395         /* reinitialize flowdirector state */
2396         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2397             adapter->atr_sample_rate) {
2398                 ring->atr_sample_rate = adapter->atr_sample_rate;
2399                 ring->atr_count = 0;
2400                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2401         } else {
2402                 ring->atr_sample_rate = 0;
2403         }
2404
2405         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2406
2407         /* enable queue */
2408         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2409
2410         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2411         if (hw->mac.type == ixgbe_mac_82598EB &&
2412             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2413                 return;
2414
2415         /* poll to verify queue is enabled */
2416         do {
2417                 usleep_range(1000, 2000);
2418                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2419         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2420         if (!wait_loop)
2421                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2422 }
2423
2424 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2425 {
2426         struct ixgbe_hw *hw = &adapter->hw;
2427         u32 rttdcs;
2428         u32 reg;
2429         u8 tcs = netdev_get_num_tc(adapter->netdev);
2430
2431         if (hw->mac.type == ixgbe_mac_82598EB)
2432                 return;
2433
2434         /* disable the arbiter while setting MTQC */
2435         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2436         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2437         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2438
2439         /* set transmit pool layout */
2440         switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2441         case (IXGBE_FLAG_SRIOV_ENABLED):
2442                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2443                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2444                 break;
2445         default:
2446                 if (!tcs)
2447                         reg = IXGBE_MTQC_64Q_1PB;
2448                 else if (tcs <= 4)
2449                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2450                 else
2451                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2452
2453                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2454
2455                 /* Enable Security TX Buffer IFG for multiple pb */
2456                 if (tcs) {
2457                         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2458                         reg |= IXGBE_SECTX_DCB;
2459                         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2460                 }
2461                 break;
2462         }
2463
2464         /* re-enable the arbiter */
2465         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2466         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2467 }
2468
2469 /**
2470  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2471  * @adapter: board private structure
2472  *
2473  * Configure the Tx unit of the MAC after a reset.
2474  **/
2475 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2476 {
2477         struct ixgbe_hw *hw = &adapter->hw;
2478         u32 dmatxctl;
2479         u32 i;
2480
2481         ixgbe_setup_mtqc(adapter);
2482
2483         if (hw->mac.type != ixgbe_mac_82598EB) {
2484                 /* DMATXCTL.EN must be before Tx queues are enabled */
2485                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2486                 dmatxctl |= IXGBE_DMATXCTL_TE;
2487                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2488         }
2489
2490         /* Setup the HW Tx Head and Tail descriptor pointers */
2491         for (i = 0; i < adapter->num_tx_queues; i++)
2492                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2493 }
2494
2495 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2496
2497 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2498                                    struct ixgbe_ring *rx_ring)
2499 {
2500         u32 srrctl;
2501         u8 reg_idx = rx_ring->reg_idx;
2502
2503         switch (adapter->hw.mac.type) {
2504         case ixgbe_mac_82598EB: {
2505                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2506                 const int mask = feature[RING_F_RSS].mask;
2507                 reg_idx = reg_idx & mask;
2508         }
2509                 break;
2510         case ixgbe_mac_82599EB:
2511         case ixgbe_mac_X540:
2512         default:
2513                 break;
2514         }
2515
2516         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2517
2518         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2519         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2520         if (adapter->num_vfs)
2521                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2522
2523         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2524                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2525
2526         if (ring_is_ps_enabled(rx_ring)) {
2527 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2528                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2529 #else
2530                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2531 #endif
2532                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2533         } else {
2534                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2535                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2536                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2537         }
2538
2539         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2540 }
2541
2542 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2543 {
2544         struct ixgbe_hw *hw = &adapter->hw;
2545         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2546                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2547                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2548         u32 mrqc = 0, reta = 0;
2549         u32 rxcsum;
2550         int i, j;
2551         u8 tcs = netdev_get_num_tc(adapter->netdev);
2552         int maxq = adapter->ring_feature[RING_F_RSS].indices;
2553
2554         if (tcs)
2555                 maxq = min(maxq, adapter->num_tx_queues / tcs);
2556
2557         /* Fill out hash function seeds */
2558         for (i = 0; i < 10; i++)
2559                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2560
2561         /* Fill out redirection table */
2562         for (i = 0, j = 0; i < 128; i++, j++) {
2563                 if (j == maxq)
2564                         j = 0;
2565                 /* reta = 4-byte sliding window of
2566                  * 0x00..(indices-1)(indices-1)00..etc. */
2567                 reta = (reta << 8) | (j * 0x11);
2568                 if ((i & 3) == 3)
2569                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2570         }
2571
2572         /* Disable indicating checksum in descriptor, enables RSS hash */
2573         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2574         rxcsum |= IXGBE_RXCSUM_PCSD;
2575         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2576
2577         if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2578             (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2579                 mrqc = IXGBE_MRQC_RSSEN;
2580         } else {
2581                 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2582                                              | IXGBE_FLAG_SRIOV_ENABLED);
2583
2584                 switch (mask) {
2585                 case (IXGBE_FLAG_RSS_ENABLED):
2586                         if (!tcs)
2587                                 mrqc = IXGBE_MRQC_RSSEN;
2588                         else if (tcs <= 4)
2589                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2590                         else
2591                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2592                         break;
2593                 case (IXGBE_FLAG_SRIOV_ENABLED):
2594                         mrqc = IXGBE_MRQC_VMDQEN;
2595                         break;
2596                 default:
2597                         break;
2598                 }
2599         }
2600
2601         /* Perform hash on these packet types */
2602         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2603               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2604               | IXGBE_MRQC_RSS_FIELD_IPV6
2605               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2606
2607         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2608 }
2609
2610 /**
2611  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2612  * @adapter:    address of board private structure
2613  * @index:      index of ring to set
2614  **/
2615 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2616                                    struct ixgbe_ring *ring)
2617 {
2618         struct ixgbe_hw *hw = &adapter->hw;
2619         u32 rscctrl;
2620         int rx_buf_len;
2621         u8 reg_idx = ring->reg_idx;
2622
2623         if (!ring_is_rsc_enabled(ring))
2624                 return;
2625
2626         rx_buf_len = ring->rx_buf_len;
2627         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2628         rscctrl |= IXGBE_RSCCTL_RSCEN;
2629         /*
2630          * we must limit the number of descriptors so that the
2631          * total size of max desc * buf_len is not greater
2632          * than 65535
2633          */
2634         if (ring_is_ps_enabled(ring)) {
2635 #if (MAX_SKB_FRAGS > 16)
2636                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2637 #elif (MAX_SKB_FRAGS > 8)
2638                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2639 #elif (MAX_SKB_FRAGS > 4)
2640                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2641 #else
2642                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2643 #endif
2644         } else {
2645                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2646                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2647                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2648                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2649                 else
2650                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2651         }
2652         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2653 }
2654
2655 /**
2656  *  ixgbe_set_uta - Set unicast filter table address
2657  *  @adapter: board private structure
2658  *
2659  *  The unicast table address is a register array of 32-bit registers.
2660  *  The table is meant to be used in a way similar to how the MTA is used
2661  *  however due to certain limitations in the hardware it is necessary to
2662  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2663  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2664  **/
2665 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2666 {
2667         struct ixgbe_hw *hw = &adapter->hw;
2668         int i;
2669
2670         /* The UTA table only exists on 82599 hardware and newer */
2671         if (hw->mac.type < ixgbe_mac_82599EB)
2672                 return;
2673
2674         /* we only need to do this if VMDq is enabled */
2675         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2676                 return;
2677
2678         for (i = 0; i < 128; i++)
2679                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2680 }
2681
2682 #define IXGBE_MAX_RX_DESC_POLL 10
2683 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2684                                        struct ixgbe_ring *ring)
2685 {
2686         struct ixgbe_hw *hw = &adapter->hw;
2687         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2688         u32 rxdctl;
2689         u8 reg_idx = ring->reg_idx;
2690
2691         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2692         if (hw->mac.type == ixgbe_mac_82598EB &&
2693             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2694                 return;
2695
2696         do {
2697                 usleep_range(1000, 2000);
2698                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2699         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2700
2701         if (!wait_loop) {
2702                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2703                       "the polling period\n", reg_idx);
2704         }
2705 }
2706
2707 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2708                             struct ixgbe_ring *ring)
2709 {
2710         struct ixgbe_hw *hw = &adapter->hw;
2711         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2712         u32 rxdctl;
2713         u8 reg_idx = ring->reg_idx;
2714
2715         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2716         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2717
2718         /* write value back with RXDCTL.ENABLE bit cleared */
2719         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2720
2721         if (hw->mac.type == ixgbe_mac_82598EB &&
2722             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2723                 return;
2724
2725         /* the hardware may take up to 100us to really disable the rx queue */
2726         do {
2727                 udelay(10);
2728                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2729         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2730
2731         if (!wait_loop) {
2732                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2733                       "the polling period\n", reg_idx);
2734         }
2735 }
2736
2737 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2738                              struct ixgbe_ring *ring)
2739 {
2740         struct ixgbe_hw *hw = &adapter->hw;
2741         u64 rdba = ring->dma;
2742         u32 rxdctl;
2743         u8 reg_idx = ring->reg_idx;
2744
2745         /* disable queue to avoid issues while updating state */
2746         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2747         ixgbe_disable_rx_queue(adapter, ring);
2748
2749         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2750         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2751         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2752                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2753         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2754         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2755         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2756
2757         ixgbe_configure_srrctl(adapter, ring);
2758         ixgbe_configure_rscctl(adapter, ring);
2759
2760         /* If operating in IOV mode set RLPML for X540 */
2761         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2762             hw->mac.type == ixgbe_mac_X540) {
2763                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2764                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2765                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2766         }
2767
2768         if (hw->mac.type == ixgbe_mac_82598EB) {
2769                 /*
2770                  * enable cache line friendly hardware writes:
2771                  * PTHRESH=32 descriptors (half the internal cache),
2772                  * this also removes ugly rx_no_buffer_count increment
2773                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2774                  * WTHRESH=8 burst writeback up to two cache lines
2775                  */
2776                 rxdctl &= ~0x3FFFFF;
2777                 rxdctl |=  0x080420;
2778         }
2779
2780         /* enable receive descriptor ring */
2781         rxdctl |= IXGBE_RXDCTL_ENABLE;
2782         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2783
2784         ixgbe_rx_desc_queue_enable(adapter, ring);
2785         ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2786 }
2787
2788 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2789 {
2790         struct ixgbe_hw *hw = &adapter->hw;
2791         int p;
2792
2793         /* PSRTYPE must be initialized in non 82598 adapters */
2794         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2795                       IXGBE_PSRTYPE_UDPHDR |
2796                       IXGBE_PSRTYPE_IPV4HDR |
2797                       IXGBE_PSRTYPE_L2HDR |
2798                       IXGBE_PSRTYPE_IPV6HDR;
2799
2800         if (hw->mac.type == ixgbe_mac_82598EB)
2801                 return;
2802
2803         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2804                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2805
2806         for (p = 0; p < adapter->num_rx_pools; p++)
2807                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2808                                 psrtype);
2809 }
2810
2811 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2812 {
2813         struct ixgbe_hw *hw = &adapter->hw;
2814         u32 gcr_ext;
2815         u32 vt_reg_bits;
2816         u32 reg_offset, vf_shift;
2817         u32 vmdctl;
2818
2819         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2820                 return;
2821
2822         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2823         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2824         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2825         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2826
2827         vf_shift = adapter->num_vfs % 32;
2828         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2829
2830         /* Enable only the PF's pool for Tx/Rx */
2831         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2832         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2833         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2834         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2835         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2836
2837         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2838         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2839
2840         /*
2841          * Set up VF register offsets for selected VT Mode,
2842          * i.e. 32 or 64 VFs for SR-IOV
2843          */
2844         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2845         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2846         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2847         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2848
2849         /* enable Tx loopback for VF/PF communication */
2850         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2851         /* Enable MAC Anti-Spoofing */
2852         hw->mac.ops.set_mac_anti_spoofing(hw,
2853                                           (adapter->antispoofing_enabled =
2854                                            (adapter->num_vfs != 0)),
2855                                           adapter->num_vfs);
2856 }
2857
2858 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2859 {
2860         struct ixgbe_hw *hw = &adapter->hw;
2861         struct net_device *netdev = adapter->netdev;
2862         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2863         int rx_buf_len;
2864         struct ixgbe_ring *rx_ring;
2865         int i;
2866         u32 mhadd, hlreg0;
2867
2868         /* Decide whether to use packet split mode or not */
2869         /* On by default */
2870         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2871
2872         /* Do not use packet split if we're in SR-IOV Mode */
2873         if (adapter->num_vfs)
2874                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2875
2876         /* Disable packet split due to 82599 erratum #45 */
2877         if (hw->mac.type == ixgbe_mac_82599EB)
2878                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2879
2880         /* Set the RX buffer length according to the mode */
2881         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2882                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2883         } else {
2884                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2885                     (netdev->mtu <= ETH_DATA_LEN))
2886                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2887                 else
2888                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2889         }
2890
2891 #ifdef IXGBE_FCOE
2892         /* adjust max frame to be able to do baby jumbo for FCoE */
2893         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2894             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2895                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2896
2897 #endif /* IXGBE_FCOE */
2898         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2899         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2900                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2901                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2902
2903                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2904         }
2905
2906         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2907         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2908         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2909         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2910
2911         /*
2912          * Setup the HW Rx Head and Tail Descriptor Pointers and
2913          * the Base and Length of the Rx Descriptor Ring
2914          */
2915         for (i = 0; i < adapter->num_rx_queues; i++) {
2916                 rx_ring = adapter->rx_ring[i];
2917                 rx_ring->rx_buf_len = rx_buf_len;
2918
2919                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2920                         set_ring_ps_enabled(rx_ring);
2921                 else
2922                         clear_ring_ps_enabled(rx_ring);
2923
2924                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2925                         set_ring_rsc_enabled(rx_ring);
2926                 else
2927                         clear_ring_rsc_enabled(rx_ring);
2928
2929 #ifdef IXGBE_FCOE
2930                 if (netdev->features & NETIF_F_FCOE_MTU) {
2931                         struct ixgbe_ring_feature *f;
2932                         f = &adapter->ring_feature[RING_F_FCOE];
2933                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2934                                 clear_ring_ps_enabled(rx_ring);
2935                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2936                                         rx_ring->rx_buf_len =
2937                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2938                         } else if (!ring_is_rsc_enabled(rx_ring) &&
2939                                    !ring_is_ps_enabled(rx_ring)) {
2940                                 rx_ring->rx_buf_len =
2941                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2942                         }
2943                 }
2944 #endif /* IXGBE_FCOE */
2945         }
2946 }
2947
2948 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2949 {
2950         struct ixgbe_hw *hw = &adapter->hw;
2951         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2952
2953         switch (hw->mac.type) {
2954         case ixgbe_mac_82598EB:
2955                 /*
2956                  * For VMDq support of different descriptor types or
2957                  * buffer sizes through the use of multiple SRRCTL
2958                  * registers, RDRXCTL.MVMEN must be set to 1
2959                  *
2960                  * also, the manual doesn't mention it clearly but DCA hints
2961                  * will only use queue 0's tags unless this bit is set.  Side
2962                  * effects of setting this bit are only that SRRCTL must be
2963                  * fully programmed [0..15]
2964                  */
2965                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2966                 break;
2967         case ixgbe_mac_82599EB:
2968         case ixgbe_mac_X540:
2969                 /* Disable RSC for ACK packets */
2970                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2971                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2972                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2973                 /* hardware requires some bits to be set by default */
2974                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2975                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2976                 break;
2977         default:
2978                 /* We should do nothing since we don't know this hardware */
2979                 return;
2980         }
2981
2982         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2983 }
2984
2985 /**
2986  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2987  * @adapter: board private structure
2988  *
2989  * Configure the Rx unit of the MAC after a reset.
2990  **/
2991 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2992 {
2993         struct ixgbe_hw *hw = &adapter->hw;
2994         int i;
2995         u32 rxctrl;
2996
2997         /* disable receives while setting up the descriptors */
2998         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2999         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3000
3001         ixgbe_setup_psrtype(adapter);
3002         ixgbe_setup_rdrxctl(adapter);
3003
3004         /* Program registers for the distribution of queues */
3005         ixgbe_setup_mrqc(adapter);
3006
3007         ixgbe_set_uta(adapter);
3008
3009         /* set_rx_buffer_len must be called before ring initialization */
3010         ixgbe_set_rx_buffer_len(adapter);
3011
3012         /*
3013          * Setup the HW Rx Head and Tail Descriptor Pointers and
3014          * the Base and Length of the Rx Descriptor Ring
3015          */
3016         for (i = 0; i < adapter->num_rx_queues; i++)
3017                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3018
3019         /* disable drop enable for 82598 parts */
3020         if (hw->mac.type == ixgbe_mac_82598EB)
3021                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3022
3023         /* enable all receives */
3024         rxctrl |= IXGBE_RXCTRL_RXEN;
3025         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3026 }
3027
3028 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3029 {
3030         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3031         struct ixgbe_hw *hw = &adapter->hw;
3032         int pool_ndx = adapter->num_vfs;
3033
3034         /* add VID to filter table */
3035         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3036         set_bit(vid, adapter->active_vlans);
3037 }
3038
3039 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3040 {
3041         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3042         struct ixgbe_hw *hw = &adapter->hw;
3043         int pool_ndx = adapter->num_vfs;
3044
3045         /* remove VID from filter table */
3046         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3047         clear_bit(vid, adapter->active_vlans);
3048 }
3049
3050 /**
3051  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3052  * @adapter: driver data
3053  */
3054 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3055 {
3056         struct ixgbe_hw *hw = &adapter->hw;
3057         u32 vlnctrl;
3058
3059         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3060         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3061         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3062 }
3063
3064 /**
3065  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3066  * @adapter: driver data
3067  */
3068 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3069 {
3070         struct ixgbe_hw *hw = &adapter->hw;
3071         u32 vlnctrl;
3072
3073         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3074         vlnctrl |= IXGBE_VLNCTRL_VFE;
3075         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3076         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3077 }
3078
3079 /**
3080  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3081  * @adapter: driver data
3082  */
3083 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3084 {
3085         struct ixgbe_hw *hw = &adapter->hw;
3086         u32 vlnctrl;
3087         int i, j;
3088
3089         switch (hw->mac.type) {
3090         case ixgbe_mac_82598EB:
3091                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3092                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3093                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3094                 break;
3095         case ixgbe_mac_82599EB:
3096         case ixgbe_mac_X540:
3097                 for (i = 0; i < adapter->num_rx_queues; i++) {
3098                         j = adapter->rx_ring[i]->reg_idx;
3099                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3100                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3101                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3102                 }
3103                 break;
3104         default:
3105                 break;
3106         }
3107 }
3108
3109 /**
3110  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3111  * @adapter: driver data
3112  */
3113 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3114 {
3115         struct ixgbe_hw *hw = &adapter->hw;
3116         u32 vlnctrl;
3117         int i, j;
3118
3119         switch (hw->mac.type) {
3120         case ixgbe_mac_82598EB:
3121                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3122                 vlnctrl |= IXGBE_VLNCTRL_VME;
3123                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3124                 break;
3125         case ixgbe_mac_82599EB:
3126         case ixgbe_mac_X540:
3127                 for (i = 0; i < adapter->num_rx_queues; i++) {
3128                         j = adapter->rx_ring[i]->reg_idx;
3129                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3130                         vlnctrl |= IXGBE_RXDCTL_VME;
3131                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3132                 }
3133                 break;
3134         default:
3135                 break;
3136         }
3137 }
3138
3139 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3140 {
3141         u16 vid;
3142
3143         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3144
3145         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3146                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3147 }
3148
3149 /**
3150  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3151  * @netdev: network interface device structure
3152  *
3153  * Writes unicast address list to the RAR table.
3154  * Returns: -ENOMEM on failure/insufficient address space
3155  *                0 on no addresses written
3156  *                X on writing X addresses to the RAR table
3157  **/
3158 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3159 {
3160         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3161         struct ixgbe_hw *hw = &adapter->hw;
3162         unsigned int vfn = adapter->num_vfs;
3163         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3164         int count = 0;
3165
3166         /* return ENOMEM indicating insufficient memory for addresses */
3167         if (netdev_uc_count(netdev) > rar_entries)
3168                 return -ENOMEM;
3169
3170         if (!netdev_uc_empty(netdev) && rar_entries) {
3171                 struct netdev_hw_addr *ha;
3172                 /* return error if we do not support writing to RAR table */
3173                 if (!hw->mac.ops.set_rar)
3174                         return -ENOMEM;
3175
3176                 netdev_for_each_uc_addr(ha, netdev) {
3177                         if (!rar_entries)
3178                                 break;
3179                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3180                                             vfn, IXGBE_RAH_AV);
3181                         count++;
3182                 }
3183         }
3184         /* write the addresses in reverse order to avoid write combining */
3185         for (; rar_entries > 0 ; rar_entries--)
3186                 hw->mac.ops.clear_rar(hw, rar_entries);
3187
3188         return count;
3189 }
3190
3191 /**
3192  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3193  * @netdev: network interface device structure
3194  *
3195  * The set_rx_method entry point is called whenever the unicast/multicast
3196  * address list or the network interface flags are updated.  This routine is
3197  * responsible for configuring the hardware for proper unicast, multicast and
3198  * promiscuous mode.
3199  **/
3200 void ixgbe_set_rx_mode(struct net_device *netdev)
3201 {
3202         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3203         struct ixgbe_hw *hw = &adapter->hw;
3204         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3205         int count;
3206
3207         /* Check for Promiscuous and All Multicast modes */
3208
3209         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3210
3211         /* set all bits that we expect to always be set */
3212         fctrl |= IXGBE_FCTRL_BAM;
3213         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3214         fctrl |= IXGBE_FCTRL_PMCF;
3215
3216         /* clear the bits we are changing the status of */
3217         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3218
3219         if (netdev->flags & IFF_PROMISC) {
3220                 hw->addr_ctrl.user_set_promisc = true;
3221                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3222                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3223                 /* don't hardware filter vlans in promisc mode */
3224                 ixgbe_vlan_filter_disable(adapter);
3225         } else {
3226                 if (netdev->flags & IFF_ALLMULTI) {
3227                         fctrl |= IXGBE_FCTRL_MPE;
3228                         vmolr |= IXGBE_VMOLR_MPE;
3229                 } else {
3230                         /*
3231                          * Write addresses to the MTA, if the attempt fails
3232                          * then we should just turn on promiscuous mode so
3233                          * that we can at least receive multicast traffic
3234                          */
3235                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3236                         vmolr |= IXGBE_VMOLR_ROMPE;
3237                 }
3238                 ixgbe_vlan_filter_enable(adapter);
3239                 hw->addr_ctrl.user_set_promisc = false;
3240                 /*
3241                  * Write addresses to available RAR registers, if there is not
3242                  * sufficient space to store all the addresses then enable
3243                  * unicast promiscuous mode
3244                  */
3245                 count = ixgbe_write_uc_addr_list(netdev);
3246                 if (count < 0) {
3247                         fctrl |= IXGBE_FCTRL_UPE;
3248                         vmolr |= IXGBE_VMOLR_ROPE;
3249                 }
3250         }
3251
3252         if (adapter->num_vfs) {
3253                 ixgbe_restore_vf_multicasts(adapter);
3254                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3255                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3256                            IXGBE_VMOLR_ROPE);
3257                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3258         }
3259
3260         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3261
3262         if (netdev->features & NETIF_F_HW_VLAN_RX)
3263                 ixgbe_vlan_strip_enable(adapter);
3264         else
3265                 ixgbe_vlan_strip_disable(adapter);
3266 }
3267
3268 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3269 {
3270         int q_idx;
3271         struct ixgbe_q_vector *q_vector;
3272         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3273
3274         /* legacy and MSI only use one vector */
3275         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3276                 q_vectors = 1;
3277
3278         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3279                 q_vector = adapter->q_vector[q_idx];
3280                 napi_enable(&q_vector->napi);
3281         }
3282 }
3283
3284 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3285 {
3286         int q_idx;
3287         struct ixgbe_q_vector *q_vector;
3288         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3289
3290         /* legacy and MSI only use one vector */
3291         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3292                 q_vectors = 1;
3293
3294         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3295                 q_vector = adapter->q_vector[q_idx];
3296                 napi_disable(&q_vector->napi);
3297         }
3298 }
3299
3300 #ifdef CONFIG_IXGBE_DCB
3301 /*
3302  * ixgbe_configure_dcb - Configure DCB hardware
3303  * @adapter: ixgbe adapter struct
3304  *
3305  * This is called by the driver on open to configure the DCB hardware.
3306  * This is also called by the gennetlink interface when reconfiguring
3307  * the DCB state.
3308  */
3309 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3310 {
3311         struct ixgbe_hw *hw = &adapter->hw;
3312         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3313
3314         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3315                 if (hw->mac.type == ixgbe_mac_82598EB)
3316                         netif_set_gso_max_size(adapter->netdev, 65536);
3317                 return;
3318         }
3319
3320         if (hw->mac.type == ixgbe_mac_82598EB)
3321                 netif_set_gso_max_size(adapter->netdev, 32768);
3322
3323
3324         /* Enable VLAN tag insert/strip */
3325         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3326
3327         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3328
3329         /* reconfigure the hardware */
3330         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3331 #ifdef IXGBE_FCOE
3332                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3333                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3334 #endif
3335                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3336                                                 DCB_TX_CONFIG);
3337                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3338                                                 DCB_RX_CONFIG);
3339                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3340         } else {
3341                 struct net_device *dev = adapter->netdev;
3342
3343                 if (adapter->ixgbe_ieee_ets)
3344                         dev->dcbnl_ops->ieee_setets(dev,
3345                                                     adapter->ixgbe_ieee_ets);
3346                 if (adapter->ixgbe_ieee_pfc)
3347                         dev->dcbnl_ops->ieee_setpfc(dev,
3348                                                     adapter->ixgbe_ieee_pfc);
3349         }
3350
3351         /* Enable RSS Hash per TC */
3352         if (hw->mac.type != ixgbe_mac_82598EB) {
3353                 int i;
3354                 u32 reg = 0;
3355
3356                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3357                         u8 msb = 0;
3358                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3359
3360                         while (cnt >>= 1)
3361                                 msb++;
3362
3363                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3364                 }
3365                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3366         }
3367 }
3368
3369 #endif
3370
3371 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3372 {
3373         int hdrm = 0;
3374         int num_tc = netdev_get_num_tc(adapter->netdev);
3375         struct ixgbe_hw *hw = &adapter->hw;
3376
3377         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3378             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3379                 hdrm = 64 << adapter->fdir_pballoc;
3380
3381         hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3382 }
3383
3384 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3385 {
3386         struct ixgbe_hw *hw = &adapter->hw;
3387         struct hlist_node *node, *node2;
3388         struct ixgbe_fdir_filter *filter;
3389
3390         spin_lock(&adapter->fdir_perfect_lock);
3391
3392         if (!hlist_empty(&adapter->fdir_filter_list))
3393                 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3394
3395         hlist_for_each_entry_safe(filter, node, node2,
3396                                   &adapter->fdir_filter_list, fdir_node) {
3397                 ixgbe_fdir_write_perfect_filter_82599(hw,
3398                                 &filter->filter,
3399                                 filter->sw_idx,
3400                                 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3401                                 IXGBE_FDIR_DROP_QUEUE :
3402                                 adapter->rx_ring[filter->action]->reg_idx);
3403         }
3404
3405         spin_unlock(&adapter->fdir_perfect_lock);
3406 }
3407
3408 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3409 {
3410         struct net_device *netdev = adapter->netdev;
3411         struct ixgbe_hw *hw = &adapter->hw;
3412         int i;
3413
3414         ixgbe_configure_pb(adapter);
3415 #ifdef CONFIG_IXGBE_DCB
3416         ixgbe_configure_dcb(adapter);
3417 #endif
3418
3419         ixgbe_set_rx_mode(netdev);
3420         ixgbe_restore_vlan(adapter);
3421
3422 #ifdef IXGBE_FCOE
3423         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3424                 ixgbe_configure_fcoe(adapter);
3425
3426 #endif /* IXGBE_FCOE */
3427         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3428                 for (i = 0; i < adapter->num_tx_queues; i++)
3429                         adapter->tx_ring[i]->atr_sample_rate =
3430                                                        adapter->atr_sample_rate;
3431                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3432         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3433                 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3434                                               adapter->fdir_pballoc);
3435                 ixgbe_fdir_filter_restore(adapter);
3436         }
3437         ixgbe_configure_virtualization(adapter);
3438
3439         ixgbe_configure_tx(adapter);
3440         ixgbe_configure_rx(adapter);
3441 }
3442
3443 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3444 {
3445         switch (hw->phy.type) {
3446         case ixgbe_phy_sfp_avago:
3447         case ixgbe_phy_sfp_ftl:
3448         case ixgbe_phy_sfp_intel:
3449         case ixgbe_phy_sfp_unknown:
3450         case ixgbe_phy_sfp_passive_tyco:
3451         case ixgbe_phy_sfp_passive_unknown:
3452         case ixgbe_phy_sfp_active_unknown:
3453         case ixgbe_phy_sfp_ftl_active:
3454                 return true;
3455         default:
3456                 return false;
3457         }
3458 }
3459
3460 /**
3461  * ixgbe_sfp_link_config - set up SFP+ link
3462  * @adapter: pointer to private adapter struct
3463  **/
3464 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3465 {
3466         /*
3467          * We are assuming the worst case scenerio here, and that
3468          * is that an SFP was inserted/removed after the reset
3469          * but before SFP detection was enabled.  As such the best
3470          * solution is to just start searching as soon as we start
3471          */
3472         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3473                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3474
3475         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3476 }
3477
3478 /**
3479  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3480  * @hw: pointer to private hardware struct
3481  *
3482  * Returns 0 on success, negative on failure
3483  **/
3484 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3485 {
3486         u32 autoneg;
3487         bool negotiation, link_up = false;
3488         u32 ret = IXGBE_ERR_LINK_SETUP;
3489
3490         if (hw->mac.ops.check_link)
3491                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3492
3493         if (ret)
3494                 goto link_cfg_out;
3495
3496         autoneg = hw->phy.autoneg_advertised;
3497         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3498                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3499                                                         &negotiation);
3500         if (ret)
3501                 goto link_cfg_out;
3502
3503         if (hw->mac.ops.setup_link)
3504                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3505 link_cfg_out:
3506         return ret;
3507 }
3508
3509 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3510 {
3511         struct ixgbe_hw *hw = &adapter->hw;
3512         u32 gpie = 0;
3513
3514         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3515                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3516                        IXGBE_GPIE_OCD;
3517                 gpie |= IXGBE_GPIE_EIAME;
3518                 /*
3519                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3520                  * this saves a register write for every interrupt
3521                  */
3522                 switch (hw->mac.type) {
3523                 case ixgbe_mac_82598EB:
3524                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3525                         break;
3526                 case ixgbe_mac_82599EB:
3527                 case ixgbe_mac_X540:
3528                 default:
3529                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3530                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3531                         break;
3532                 }
3533         } else {
3534                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3535                  * specifically only auto mask tx and rx interrupts */
3536                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3537         }
3538
3539         /* XXX: to interrupt immediately for EICS writes, enable this */
3540         /* gpie |= IXGBE_GPIE_EIMEN; */
3541
3542         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3543                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3544                 gpie |= IXGBE_GPIE_VTMODE_64;
3545         }
3546
3547         /* Enable fan failure interrupt */
3548         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3549                 gpie |= IXGBE_SDP1_GPIEN;
3550
3551         if (hw->mac.type == ixgbe_mac_82599EB) {
3552                 gpie |= IXGBE_SDP1_GPIEN;
3553                 gpie |= IXGBE_SDP2_GPIEN;
3554         }
3555
3556         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3557 }
3558
3559 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3560 {
3561         struct ixgbe_hw *hw = &adapter->hw;
3562         int err;
3563         u32 ctrl_ext;
3564
3565         ixgbe_get_hw_control(adapter);
3566         ixgbe_setup_gpie(adapter);
3567
3568         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3569                 ixgbe_configure_msix(adapter);
3570         else
3571                 ixgbe_configure_msi_and_legacy(adapter);
3572
3573         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3574         if (hw->mac.ops.enable_tx_laser &&
3575             ((hw->phy.multispeed_fiber) ||
3576              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3577               (hw->mac.type == ixgbe_mac_82599EB))))
3578                 hw->mac.ops.enable_tx_laser(hw);
3579
3580         clear_bit(__IXGBE_DOWN, &adapter->state);
3581         ixgbe_napi_enable_all(adapter);
3582
3583         if (ixgbe_is_sfp(hw)) {
3584                 ixgbe_sfp_link_config(adapter);
3585         } else {
3586                 err = ixgbe_non_sfp_link_config(hw);
3587                 if (err)
3588                         e_err(probe, "link_config FAILED %d\n", err);
3589         }
3590
3591         /* clear any pending interrupts, may auto mask */
3592         IXGBE_READ_REG(hw, IXGBE_EICR);
3593         ixgbe_irq_enable(adapter, true, true);
3594
3595         /*
3596          * If this adapter has a fan, check to see if we had a failure
3597          * before we enabled the interrupt.
3598          */
3599         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3600                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3601                 if (esdp & IXGBE_ESDP_SDP1)
3602                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3603         }
3604
3605         /* enable transmits */
3606         netif_tx_start_all_queues(adapter->netdev);
3607
3608         /* bring the link up in the watchdog, this could race with our first
3609          * link up interrupt but shouldn't be a problem */
3610         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3611         adapter->link_check_timeout = jiffies;
3612         mod_timer(&adapter->service_timer, jiffies);
3613
3614         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3615         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3616         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3617         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3618
3619         return 0;
3620 }
3621
3622 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3623 {
3624         WARN_ON(in_interrupt());
3625         /* put off any impending NetWatchDogTimeout */
3626         adapter->netdev->trans_start = jiffies;
3627
3628         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3629                 usleep_range(1000, 2000);
3630         ixgbe_down(adapter);
3631         /*
3632          * If SR-IOV enabled then wait a bit before bringing the adapter
3633          * back up to give the VFs time to respond to the reset.  The
3634          * two second wait is based upon the watchdog timer cycle in
3635          * the VF driver.
3636          */
3637         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3638                 msleep(2000);
3639         ixgbe_up(adapter);
3640         clear_bit(__IXGBE_RESETTING, &adapter->state);
3641 }
3642
3643 int ixgbe_up(struct ixgbe_adapter *adapter)
3644 {
3645         /* hardware has been reset, we need to reload some things */
3646         ixgbe_configure(adapter);
3647
3648         return ixgbe_up_complete(adapter);
3649 }
3650
3651 void ixgbe_reset(struct ixgbe_adapter *adapter)
3652 {
3653         struct ixgbe_hw *hw = &adapter->hw;
3654         int err;
3655
3656         /* lock SFP init bit to prevent race conditions with the watchdog */
3657         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3658                 usleep_range(1000, 2000);
3659
3660         /* clear all SFP and link config related flags while holding SFP_INIT */
3661         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3662                              IXGBE_FLAG2_SFP_NEEDS_RESET);
3663         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3664
3665         err = hw->mac.ops.init_hw(hw);
3666         switch (err) {
3667         case 0:
3668         case IXGBE_ERR_SFP_NOT_PRESENT:
3669         case IXGBE_ERR_SFP_NOT_SUPPORTED:
3670                 break;
3671         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3672                 e_dev_err("master disable timed out\n");
3673                 break;
3674         case IXGBE_ERR_EEPROM_VERSION:
3675                 /* We are running on a pre-production device, log a warning */
3676                 e_dev_warn("This device is a pre-production adapter/LOM. "
3677                            "Please be aware there may be issuesassociated with "
3678                            "your hardware.  If you are experiencing problems "
3679                            "please contact your Intel or hardware "
3680                            "representative who provided you with this "
3681                            "hardware.\n");
3682                 break;
3683         default:
3684                 e_dev_err("Hardware Error: %d\n", err);
3685         }
3686
3687         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3688
3689         /* reprogram the RAR[0] in case user changed it. */
3690         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3691                             IXGBE_RAH_AV);
3692 }
3693
3694 /**
3695  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3696  * @rx_ring: ring to free buffers from
3697  **/
3698 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3699 {
3700         struct device *dev = rx_ring->dev;
3701         unsigned long size;
3702         u16 i;
3703
3704         /* ring already cleared, nothing to do */
3705         if (!rx_ring->rx_buffer_info)
3706                 return;
3707
3708         /* Free all the Rx ring sk_buffs */
3709         for (i = 0; i < rx_ring->count; i++) {
3710                 struct ixgbe_rx_buffer *rx_buffer_info;
3711
3712                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3713                 if (rx_buffer_info->dma) {
3714                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3715                                          rx_ring->rx_buf_len,
3716                                          DMA_FROM_DEVICE);
3717                         rx_buffer_info->dma = 0;
3718                 }
3719                 if (rx_buffer_info->skb) {
3720                         struct sk_buff *skb = rx_buffer_info->skb;
3721                         rx_buffer_info->skb = NULL;
3722                         do {
3723                                 struct sk_buff *this = skb;
3724                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3725                                         dma_unmap_single(dev,
3726                                                          IXGBE_RSC_CB(this)->dma,
3727                                                          rx_ring->rx_buf_len,
3728                                                          DMA_FROM_DEVICE);
3729                                         IXGBE_RSC_CB(this)->dma = 0;
3730                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3731                                 }
3732                                 skb = skb->prev;
3733                                 dev_kfree_skb(this);
3734                         } while (skb);
3735                 }
3736                 if (!rx_buffer_info->page)
3737                         continue;
3738                 if (rx_buffer_info->page_dma) {
3739                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3740                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3741                         rx_buffer_info->page_dma = 0;
3742                 }
3743                 put_page(rx_buffer_info->page);
3744                 rx_buffer_info->page = NULL;
3745                 rx_buffer_info->page_offset = 0;
3746         }
3747
3748         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3749         memset(rx_ring->rx_buffer_info, 0, size);
3750
3751         /* Zero out the descriptor ring */
3752         memset(rx_ring->desc, 0, rx_ring->size);
3753
3754         rx_ring->next_to_clean = 0;
3755         rx_ring->next_to_use = 0;
3756 }
3757
3758 /**
3759  * ixgbe_clean_tx_ring - Free Tx Buffers
3760  * @tx_ring: ring to be cleaned
3761  **/
3762 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3763 {
3764         struct ixgbe_tx_buffer *tx_buffer_info;
3765         unsigned long size;
3766         u16 i;
3767
3768         /* ring already cleared, nothing to do */
3769         if (!tx_ring->tx_buffer_info)
3770                 return;
3771
3772         /* Free all the Tx ring sk_buffs */
3773         for (i = 0; i < tx_ring->count; i++) {
3774                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3775                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3776         }
3777
3778         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3779         memset(tx_ring->tx_buffer_info, 0, size);
3780
3781         /* Zero out the descriptor ring */
3782         memset(tx_ring->desc, 0, tx_ring->size);
3783
3784         tx_ring->next_to_use = 0;
3785         tx_ring->next_to_clean = 0;
3786 }
3787
3788 /**
3789  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3790  * @adapter: board private structure
3791  **/
3792 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3793 {
3794         int i;
3795
3796         for (i = 0; i < adapter->num_rx_queues; i++)
3797                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3798 }
3799
3800 /**
3801  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3802  * @adapter: board private structure
3803  **/
3804 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3805 {
3806         int i;
3807
3808         for (i = 0; i < adapter->num_tx_queues; i++)
3809                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3810 }
3811
3812 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3813 {
3814         struct hlist_node *node, *node2;
3815         struct ixgbe_fdir_filter *filter;
3816
3817         spin_lock(&adapter->fdir_perfect_lock);
3818
3819         hlist_for_each_entry_safe(filter, node, node2,
3820                                   &adapter->fdir_filter_list, fdir_node) {
3821                 hlist_del(&filter->fdir_node);
3822                 kfree(filter);
3823         }
3824         adapter->fdir_filter_count = 0;
3825
3826         spin_unlock(&adapter->fdir_perfect_lock);
3827 }
3828
3829 void ixgbe_down(struct ixgbe_adapter *adapter)
3830 {
3831         struct net_device *netdev = adapter->netdev;
3832         struct ixgbe_hw *hw = &adapter->hw;
3833         u32 rxctrl;
3834         int i;
3835
3836         /* signal that we are down to the interrupt handler */
3837         set_bit(__IXGBE_DOWN, &adapter->state);
3838
3839         /* disable receives */
3840         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3841         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3842
3843         /* disable all enabled rx queues */
3844         for (i = 0; i < adapter->num_rx_queues; i++)
3845                 /* this call also flushes the previous write */
3846                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3847
3848         usleep_range(10000, 20000);
3849
3850         netif_tx_stop_all_queues(netdev);
3851
3852         /* call carrier off first to avoid false dev_watchdog timeouts */
3853         netif_carrier_off(netdev);
3854         netif_tx_disable(netdev);
3855
3856         ixgbe_irq_disable(adapter);
3857
3858         ixgbe_napi_disable_all(adapter);
3859
3860         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
3861                              IXGBE_FLAG2_RESET_REQUESTED);
3862         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3863
3864         del_timer_sync(&adapter->service_timer);
3865
3866         /* disable receive for all VFs and wait one second */
3867         if (adapter->num_vfs) {
3868                 /* ping all the active vfs to let them know we are going down */
3869                 ixgbe_ping_all_vfs(adapter);
3870
3871                 /* Disable all VFTE/VFRE TX/RX */
3872                 ixgbe_disable_tx_rx(adapter);
3873
3874                 /* Mark all the VFs as inactive */
3875                 for (i = 0 ; i < adapter->num_vfs; i++)
3876                         adapter->vfinfo[i].clear_to_send = 0;
3877         }
3878
3879         /* disable transmits in the hardware now that interrupts are off */
3880         for (i = 0; i < adapter->num_tx_queues; i++) {
3881                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
3882                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
3883         }
3884
3885         /* Disable the Tx DMA engine on 82599 and X540 */
3886         switch (hw->mac.type) {
3887         case ixgbe_mac_82599EB:
3888         case ixgbe_mac_X540:
3889                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3890                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3891                                  ~IXGBE_DMATXCTL_TE));
3892                 break;
3893         default:
3894                 break;
3895         }
3896
3897         if (!pci_channel_offline(adapter->pdev))
3898                 ixgbe_reset(adapter);
3899
3900         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
3901         if (hw->mac.ops.disable_tx_laser &&
3902             ((hw->phy.multispeed_fiber) ||
3903              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3904               (hw->mac.type == ixgbe_mac_82599EB))))
3905                 hw->mac.ops.disable_tx_laser(hw);
3906
3907         ixgbe_clean_all_tx_rings(adapter);
3908         ixgbe_clean_all_rx_rings(adapter);
3909
3910 #ifdef CONFIG_IXGBE_DCA
3911         /* since we reset the hardware DCA settings were cleared */
3912         ixgbe_setup_dca(adapter);
3913 #endif
3914 }
3915
3916 /**
3917  * ixgbe_poll - NAPI Rx polling callback
3918  * @napi: structure for representing this polling device
3919  * @budget: how many packets driver is allowed to clean
3920  *
3921  * This function is used for legacy and MSI, NAPI mode
3922  **/
3923 static int ixgbe_poll(struct napi_struct *napi, int budget)
3924 {
3925         struct ixgbe_q_vector *q_vector =
3926                                 container_of(napi, struct ixgbe_q_vector, napi);
3927         struct ixgbe_adapter *adapter = q_vector->adapter;
3928         struct ixgbe_ring *ring;
3929         int per_ring_budget;
3930         bool clean_complete = true;
3931
3932 #ifdef CONFIG_IXGBE_DCA
3933         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3934                 ixgbe_update_dca(q_vector);
3935 #endif
3936
3937         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
3938                 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
3939
3940         /* attempt to distribute budget to each queue fairly, but don't allow
3941          * the budget to go below 1 because we'll exit polling */
3942         if (q_vector->rx.count > 1)
3943                 per_ring_budget = max(budget/q_vector->rx.count, 1);
3944         else
3945                 per_ring_budget = budget;
3946
3947         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
3948                 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
3949                                                      per_ring_budget);
3950
3951         /* If all work not completed, return budget and keep polling */
3952         if (!clean_complete)
3953                 return budget;
3954
3955         /* all work done, exit the polling mode */
3956         napi_complete(napi);
3957         if (adapter->rx_itr_setting & 1)
3958                 ixgbe_set_itr(q_vector);
3959         if (!test_bit(__IXGBE_DOWN, &adapter->state))
3960                 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
3961
3962         return 0;
3963 }
3964
3965 /**
3966  * ixgbe_tx_timeout - Respond to a Tx Hang
3967  * @netdev: network interface device structure
3968  **/
3969 static void ixgbe_tx_timeout(struct net_device *netdev)
3970 {
3971         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3972
3973         /* Do the reset outside of interrupt context */
3974         ixgbe_tx_timeout_reset(adapter);
3975 }
3976
3977 /**
3978  * ixgbe_set_rss_queues: Allocate queues for RSS
3979  * @adapter: board private structure to initialize
3980  *
3981  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3982  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3983  *
3984  **/
3985 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3986 {
3987         bool ret = false;
3988         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3989
3990         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3991                 f->mask = 0xF;
3992                 adapter->num_rx_queues = f->indices;
3993                 adapter->num_tx_queues = f->indices;
3994                 ret = true;
3995         } else {
3996                 ret = false;
3997         }
3998
3999         return ret;
4000 }
4001
4002 /**
4003  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4004  * @adapter: board private structure to initialize
4005  *
4006  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4007  * to the original CPU that initiated the Tx session.  This runs in addition
4008  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4009  * Rx load across CPUs using RSS.
4010  *
4011  **/
4012 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4013 {
4014         bool ret = false;
4015         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4016
4017         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4018         f_fdir->mask = 0;
4019
4020         /* Flow Director must have RSS enabled */
4021         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4022             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4023                 adapter->num_tx_queues = f_fdir->indices;
4024                 adapter->num_rx_queues = f_fdir->indices;
4025                 ret = true;
4026         } else {
4027                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4028         }
4029         return ret;
4030 }
4031
4032 #ifdef IXGBE_FCOE
4033 /**
4034  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4035  * @adapter: board private structure to initialize
4036  *
4037  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4038  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4039  * rx queues out of the max number of rx queues, instead, it is used as the
4040  * index of the first rx queue used by FCoE.
4041  *
4042  **/
4043 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4044 {
4045         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4046
4047         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4048                 return false;
4049
4050         f->indices = min((int)num_online_cpus(), f->indices);
4051
4052         adapter->num_rx_queues = 1;
4053         adapter->num_tx_queues = 1;
4054
4055         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4056                 e_info(probe, "FCoE enabled with RSS\n");
4057                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4058                         ixgbe_set_fdir_queues(adapter);
4059                 else
4060                         ixgbe_set_rss_queues(adapter);
4061         }
4062
4063         /* adding FCoE rx rings to the end */
4064         f->mask = adapter->num_rx_queues;
4065         adapter->num_rx_queues += f->indices;
4066         adapter->num_tx_queues += f->indices;
4067
4068         return true;
4069 }
4070 #endif /* IXGBE_FCOE */
4071
4072 /* Artificial max queue cap per traffic class in DCB mode */
4073 #define DCB_QUEUE_CAP 8
4074
4075 #ifdef CONFIG_IXGBE_DCB
4076 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4077 {
4078         int per_tc_q, q, i, offset = 0;
4079         struct net_device *dev = adapter->netdev;
4080         int tcs = netdev_get_num_tc(dev);
4081
4082         if (!tcs)
4083                 return false;
4084
4085         /* Map queue offset and counts onto allocated tx queues */
4086         per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4087         q = min((int)num_online_cpus(), per_tc_q);
4088
4089         for (i = 0; i < tcs; i++) {
4090                 netdev_set_prio_tc_map(dev, i, i);
4091                 netdev_set_tc_queue(dev, i, q, offset);
4092                 offset += q;
4093         }
4094
4095         adapter->num_tx_queues = q * tcs;
4096         adapter->num_rx_queues = q * tcs;
4097
4098 #ifdef IXGBE_FCOE
4099         /* FCoE enabled queues require special configuration indexed
4100          * by feature specific indices and mask. Here we map FCoE
4101          * indices onto the DCB queue pairs allowing FCoE to own
4102          * configuration later.
4103          */
4104         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4105                 int tc;
4106                 struct ixgbe_ring_feature *f =
4107                                         &adapter->ring_feature[RING_F_FCOE];
4108
4109                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4110                 f->indices = dev->tc_to_txq[tc].count;
4111                 f->mask = dev->tc_to_txq[tc].offset;
4112         }
4113 #endif
4114
4115         return true;
4116 }
4117 #endif
4118
4119 /**
4120  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4121  * @adapter: board private structure to initialize
4122  *
4123  * IOV doesn't actually use anything, so just NAK the
4124  * request for now and let the other queue routines
4125  * figure out what to do.
4126  */
4127 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4128 {
4129         return false;
4130 }
4131
4132 /*
4133  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4134  * @adapter: board private structure to initialize
4135  *
4136  * This is the top level queue allocation routine.  The order here is very
4137  * important, starting with the "most" number of features turned on at once,
4138  * and ending with the smallest set of features.  This way large combinations
4139  * can be allocated if they're turned on, and smaller combinations are the
4140  * fallthrough conditions.
4141  *
4142  **/
4143 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4144 {
4145         /* Start with base case */
4146         adapter->num_rx_queues = 1;
4147         adapter->num_tx_queues = 1;
4148         adapter->num_rx_pools = adapter->num_rx_queues;
4149         adapter->num_rx_queues_per_pool = 1;
4150
4151         if (ixgbe_set_sriov_queues(adapter))
4152                 goto done;
4153
4154 #ifdef CONFIG_IXGBE_DCB
4155         if (ixgbe_set_dcb_queues(adapter))
4156                 goto done;
4157
4158 #endif
4159 #ifdef IXGBE_FCOE
4160         if (ixgbe_set_fcoe_queues(adapter))
4161                 goto done;
4162
4163 #endif /* IXGBE_FCOE */
4164         if (ixgbe_set_fdir_queues(adapter))
4165                 goto done;
4166
4167         if (ixgbe_set_rss_queues(adapter))
4168                 goto done;
4169
4170         /* fallback to base case */
4171         adapter->num_rx_queues = 1;
4172         adapter->num_tx_queues = 1;
4173
4174 done:
4175         /* Notify the stack of the (possibly) reduced queue counts. */
4176         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4177         return netif_set_real_num_rx_queues(adapter->netdev,
4178                                             adapter->num_rx_queues);
4179 }
4180
4181 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4182                                        int vectors)
4183 {
4184         int err, vector_threshold;
4185
4186         /* We'll want at least 3 (vector_threshold):
4187          * 1) TxQ[0] Cleanup
4188          * 2) RxQ[0] Cleanup
4189          * 3) Other (Link Status Change, etc.)
4190          * 4) TCP Timer (optional)
4191          */
4192         vector_threshold = MIN_MSIX_COUNT;
4193
4194         /* The more we get, the more we will assign to Tx/Rx Cleanup
4195          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4196          * Right now, we simply care about how many we'll get; we'll
4197          * set them up later while requesting irq's.
4198          */
4199         while (vectors >= vector_threshold) {
4200                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4201                                       vectors);
4202                 if (!err) /* Success in acquiring all requested vectors. */
4203                         break;
4204                 else if (err < 0)
4205                         vectors = 0; /* Nasty failure, quit now */
4206                 else /* err == number of vectors we should try again with */
4207                         vectors = err;
4208         }
4209
4210         if (vectors < vector_threshold) {
4211                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4212                  * This just means we'll go with either a single MSI
4213                  * vector or fall back to legacy interrupts.
4214                  */
4215                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4216                              "Unable to allocate MSI-X interrupts\n");
4217                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4218                 kfree(adapter->msix_entries);
4219                 adapter->msix_entries = NULL;
4220         } else {
4221                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4222                 /*
4223                  * Adjust for only the vectors we'll use, which is minimum
4224                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4225                  * vectors we were allocated.
4226                  */
4227                 adapter->num_msix_vectors = min(vectors,
4228                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4229         }
4230 }
4231
4232 /**
4233  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4234  * @adapter: board private structure to initialize
4235  *
4236  * Cache the descriptor ring offsets for RSS to the assigned rings.
4237  *
4238  **/
4239 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4240 {
4241         int i;
4242
4243         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4244                 return false;
4245
4246         for (i = 0; i < adapter->num_rx_queues; i++)
4247                 adapter->rx_ring[i]->reg_idx = i;
4248         for (i = 0; i < adapter->num_tx_queues; i++)
4249                 adapter->tx_ring[i]->reg_idx = i;
4250
4251         return true;
4252 }
4253
4254 #ifdef CONFIG_IXGBE_DCB
4255
4256 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4257 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4258                                     unsigned int *tx, unsigned int *rx)
4259 {
4260         struct net_device *dev = adapter->netdev;
4261         struct ixgbe_hw *hw = &adapter->hw;
4262         u8 num_tcs = netdev_get_num_tc(dev);
4263
4264         *tx = 0;
4265         *rx = 0;
4266
4267         switch (hw->mac.type) {
4268         case ixgbe_mac_82598EB:
4269                 *tx = tc << 2;
4270                 *rx = tc << 3;
4271                 break;
4272         case ixgbe_mac_82599EB:
4273         case ixgbe_mac_X540:
4274                 if (num_tcs > 4) {
4275                         if (tc < 3) {
4276                                 *tx = tc << 5;
4277                                 *rx = tc << 4;
4278                         } else if (tc <  5) {
4279                                 *tx = ((tc + 2) << 4);
4280                                 *rx = tc << 4;
4281                         } else if (tc < num_tcs) {
4282                                 *tx = ((tc + 8) << 3);
4283                                 *rx = tc << 4;
4284                         }
4285                 } else {
4286                         *rx =  tc << 5;
4287                         switch (tc) {
4288                         case 0:
4289                                 *tx =  0;
4290                                 break;
4291                         case 1:
4292                                 *tx = 64;
4293                                 break;
4294                         case 2:
4295                                 *tx = 96;
4296                                 break;
4297                         case 3:
4298                                 *tx = 112;
4299                                 break;
4300                         default:
4301                                 break;
4302                         }
4303                 }
4304                 break;
4305         default:
4306                 break;
4307         }
4308 }
4309
4310 /**
4311  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4312  * @adapter: board private structure to initialize
4313  *
4314  * Cache the descriptor ring offsets for DCB to the assigned rings.
4315  *
4316  **/
4317 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4318 {
4319         struct net_device *dev = adapter->netdev;
4320         int i, j, k;
4321         u8 num_tcs = netdev_get_num_tc(dev);
4322
4323         if (!num_tcs)
4324                 return false;
4325
4326         for (i = 0, k = 0; i < num_tcs; i++) {
4327                 unsigned int tx_s, rx_s;
4328                 u16 count = dev->tc_to_txq[i].count;
4329
4330                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4331                 for (j = 0; j < count; j++, k++) {
4332                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4333                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4334                         adapter->tx_ring[k]->dcb_tc = i;
4335                         adapter->rx_ring[k]->dcb_tc = i;
4336                 }
4337         }
4338
4339         return true;
4340 }
4341 #endif
4342
4343 /**
4344  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4345  * @adapter: board private structure to initialize
4346  *
4347  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4348  *
4349  **/
4350 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4351 {
4352         int i;
4353         bool ret = false;
4354
4355         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4356             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4357                 for (i = 0; i < adapter->num_rx_queues; i++)
4358                         adapter->rx_ring[i]->reg_idx = i;
4359                 for (i = 0; i < adapter->num_tx_queues; i++)
4360                         adapter->tx_ring[i]->reg_idx = i;
4361                 ret = true;
4362         }
4363
4364         return ret;
4365 }
4366
4367 #ifdef IXGBE_FCOE
4368 /**
4369  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4370  * @adapter: board private structure to initialize
4371  *
4372  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4373  *
4374  */
4375 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4376 {
4377         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4378         int i;
4379         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4380
4381         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4382                 return false;
4383
4384         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4385                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4386                         ixgbe_cache_ring_fdir(adapter);
4387                 else
4388                         ixgbe_cache_ring_rss(adapter);
4389
4390                 fcoe_rx_i = f->mask;
4391                 fcoe_tx_i = f->mask;
4392         }
4393         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4394                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4395                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4396         }
4397         return true;
4398 }
4399
4400 #endif /* IXGBE_FCOE */
4401 /**
4402  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4403  * @adapter: board private structure to initialize
4404  *
4405  * SR-IOV doesn't use any descriptor rings but changes the default if
4406  * no other mapping is used.
4407  *
4408  */
4409 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4410 {
4411         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4412         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4413         if (adapter->num_vfs)
4414                 return true;
4415         else
4416                 return false;
4417 }
4418
4419 /**
4420  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4421  * @adapter: board private structure to initialize
4422  *
4423  * Once we know the feature-set enabled for the device, we'll cache
4424  * the register offset the descriptor ring is assigned to.
4425  *
4426  * Note, the order the various feature calls is important.  It must start with
4427  * the "most" features enabled at the same time, then trickle down to the
4428  * least amount of features turned on at once.
4429  **/
4430 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4431 {
4432         /* start with default case */
4433         adapter->rx_ring[0]->reg_idx = 0;
4434         adapter->tx_ring[0]->reg_idx = 0;
4435
4436         if (ixgbe_cache_ring_sriov(adapter))
4437                 return;
4438
4439 #ifdef CONFIG_IXGBE_DCB
4440         if (ixgbe_cache_ring_dcb(adapter))
4441                 return;
4442 #endif
4443
4444 #ifdef IXGBE_FCOE
4445         if (ixgbe_cache_ring_fcoe(adapter))
4446                 return;
4447 #endif /* IXGBE_FCOE */
4448
4449         if (ixgbe_cache_ring_fdir(adapter))
4450                 return;
4451
4452         if (ixgbe_cache_ring_rss(adapter))
4453                 return;
4454 }
4455
4456 /**
4457  * ixgbe_alloc_queues - Allocate memory for all rings
4458  * @adapter: board private structure to initialize
4459  *
4460  * We allocate one ring per queue at run-time since we don't know the
4461  * number of queues at compile-time.  The polling_netdev array is
4462  * intended for Multiqueue, but should work fine with a single queue.
4463  **/
4464 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4465 {
4466         int rx = 0, tx = 0, nid = adapter->node;
4467
4468         if (nid < 0 || !node_online(nid))
4469                 nid = first_online_node;
4470
4471         for (; tx < adapter->num_tx_queues; tx++) {
4472                 struct ixgbe_ring *ring;
4473
4474                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4475                 if (!ring)
4476                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4477                 if (!ring)
4478                         goto err_allocation;
4479                 ring->count = adapter->tx_ring_count;
4480                 ring->queue_index = tx;
4481                 ring->numa_node = nid;
4482                 ring->dev = &adapter->pdev->dev;
4483                 ring->netdev = adapter->netdev;
4484
4485                 adapter->tx_ring[tx] = ring;
4486         }
4487
4488         for (; rx < adapter->num_rx_queues; rx++) {
4489                 struct ixgbe_ring *ring;
4490
4491                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4492                 if (!ring)
4493                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4494                 if (!ring)
4495                         goto err_allocation;
4496                 ring->count = adapter->rx_ring_count;
4497                 ring->queue_index = rx;
4498                 ring->numa_node = nid;
4499                 ring->dev = &adapter->pdev->dev;
4500                 ring->netdev = adapter->netdev;
4501
4502                 adapter->rx_ring[rx] = ring;
4503         }
4504
4505         ixgbe_cache_ring_register(adapter);
4506
4507         return 0;
4508
4509 err_allocation:
4510         while (tx)
4511                 kfree(adapter->tx_ring[--tx]);
4512
4513         while (rx)
4514                 kfree(adapter->rx_ring[--rx]);
4515         return -ENOMEM;
4516 }
4517
4518 /**
4519  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4520  * @adapter: board private structure to initialize
4521  *
4522  * Attempt to configure the interrupts using the best available
4523  * capabilities of the hardware and the kernel.
4524  **/
4525 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4526 {
4527         struct ixgbe_hw *hw = &adapter->hw;
4528         int err = 0;
4529         int vector, v_budget;
4530
4531         /*
4532          * It's easy to be greedy for MSI-X vectors, but it really
4533          * doesn't do us much good if we have a lot more vectors
4534          * than CPU's.  So let's be conservative and only ask for
4535          * (roughly) the same number of vectors as there are CPU's.
4536          */
4537         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4538                        (int)num_online_cpus()) + NON_Q_VECTORS;
4539
4540         /*
4541          * At the same time, hardware can only support a maximum of
4542          * hw.mac->max_msix_vectors vectors.  With features
4543          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4544          * descriptor queues supported by our device.  Thus, we cap it off in
4545          * those rare cases where the cpu count also exceeds our vector limit.
4546          */
4547         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4548
4549         /* A failure in MSI-X entry allocation isn't fatal, but it does
4550          * mean we disable MSI-X capabilities of the adapter. */
4551         adapter->msix_entries = kcalloc(v_budget,
4552                                         sizeof(struct msix_entry), GFP_KERNEL);
4553         if (adapter->msix_entries) {
4554                 for (vector = 0; vector < v_budget; vector++)
4555                         adapter->msix_entries[vector].entry = vector;
4556
4557                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4558
4559                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4560                         goto out;
4561         }
4562
4563         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4564         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4565         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4566                 e_err(probe,
4567                       "ATR is not supported while multiple "
4568                       "queues are disabled.  Disabling Flow Director\n");
4569         }
4570         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4571         adapter->atr_sample_rate = 0;
4572         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4573                 ixgbe_disable_sriov(adapter);
4574
4575         err = ixgbe_set_num_queues(adapter);
4576         if (err)
4577                 return err;
4578
4579         err = pci_enable_msi(adapter->pdev);
4580         if (!err) {
4581                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4582         } else {
4583                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4584                              "Unable to allocate MSI interrupt, "
4585                              "falling back to legacy.  Error: %d\n", err);
4586                 /* reset err */
4587                 err = 0;
4588         }
4589
4590 out:
4591         return err;
4592 }
4593
4594 /**
4595  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4596  * @adapter: board private structure to initialize
4597  *
4598  * We allocate one q_vector per queue interrupt.  If allocation fails we
4599  * return -ENOMEM.
4600  **/
4601 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4602 {
4603         int v_idx, num_q_vectors;
4604         struct ixgbe_q_vector *q_vector;
4605
4606         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4607                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4608         else
4609                 num_q_vectors = 1;
4610
4611         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4612                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4613                                         GFP_KERNEL, adapter->node);
4614                 if (!q_vector)
4615                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4616                                            GFP_KERNEL);
4617                 if (!q_vector)
4618                         goto err_out;
4619
4620                 q_vector->adapter = adapter;
4621                 q_vector->v_idx = v_idx;
4622
4623                 /* Allocate the affinity_hint cpumask, configure the mask */
4624                 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4625                         goto err_out;
4626                 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4627
4628                 if (q_vector->tx.count && !q_vector->rx.count)
4629                         q_vector->eitr = adapter->tx_eitr_param;
4630                 else
4631                         q_vector->eitr = adapter->rx_eitr_param;
4632
4633                 netif_napi_add(adapter->netdev, &q_vector->napi,
4634                                ixgbe_poll, 64);
4635                 adapter->q_vector[v_idx] = q_vector;
4636         }
4637
4638         return 0;
4639
4640 err_out:
4641         while (v_idx) {
4642                 v_idx--;
4643                 q_vector = adapter->q_vector[v_idx];
4644                 netif_napi_del(&q_vector->napi);
4645                 free_cpumask_var(q_vector->affinity_mask);
4646                 kfree(q_vector);
4647                 adapter->q_vector[v_idx] = NULL;
4648         }
4649         return -ENOMEM;
4650 }
4651
4652 /**
4653  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4654  * @adapter: board private structure to initialize
4655  *
4656  * This function frees the memory allocated to the q_vectors.  In addition if
4657  * NAPI is enabled it will delete any references to the NAPI struct prior
4658  * to freeing the q_vector.
4659  **/
4660 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4661 {
4662         int v_idx, num_q_vectors;
4663
4664         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4665                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4666         else
4667                 num_q_vectors = 1;
4668
4669         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4670                 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4671                 adapter->q_vector[v_idx] = NULL;
4672                 netif_napi_del(&q_vector->napi);
4673                 free_cpumask_var(q_vector->affinity_mask);
4674                 kfree(q_vector);
4675         }
4676 }
4677
4678 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4679 {
4680         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4681                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4682                 pci_disable_msix(adapter->pdev);
4683                 kfree(adapter->msix_entries);
4684                 adapter->msix_entries = NULL;
4685         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4686                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4687                 pci_disable_msi(adapter->pdev);
4688         }
4689 }
4690
4691 /**
4692  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4693  * @adapter: board private structure to initialize
4694  *
4695  * We determine which interrupt scheme to use based on...
4696  * - Kernel support (MSI, MSI-X)
4697  *   - which can be user-defined (via MODULE_PARAM)
4698  * - Hardware queue count (num_*_queues)
4699  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4700  **/
4701 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4702 {
4703         int err;
4704
4705         /* Number of supported queues */
4706         err = ixgbe_set_num_queues(adapter);
4707         if (err)
4708                 return err;
4709
4710         err = ixgbe_set_interrupt_capability(adapter);
4711         if (err) {
4712                 e_dev_err("Unable to setup interrupt capabilities\n");
4713                 goto err_set_interrupt;
4714         }
4715
4716         err = ixgbe_alloc_q_vectors(adapter);
4717         if (err) {
4718                 e_dev_err("Unable to allocate memory for queue vectors\n");
4719                 goto err_alloc_q_vectors;
4720         }
4721
4722         err = ixgbe_alloc_queues(adapter);
4723         if (err) {
4724                 e_dev_err("Unable to allocate memory for queues\n");
4725                 goto err_alloc_queues;
4726         }
4727
4728         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4729                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4730                    adapter->num_rx_queues, adapter->num_tx_queues);
4731
4732         set_bit(__IXGBE_DOWN, &adapter->state);
4733
4734         return 0;
4735
4736 err_alloc_queues:
4737         ixgbe_free_q_vectors(adapter);
4738 err_alloc_q_vectors:
4739         ixgbe_reset_interrupt_capability(adapter);
4740 err_set_interrupt:
4741         return err;
4742 }
4743
4744 /**
4745  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4746  * @adapter: board private structure to clear interrupt scheme on
4747  *
4748  * We go through and clear interrupt specific resources and reset the structure
4749  * to pre-load conditions
4750  **/
4751 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4752 {
4753         int i;
4754
4755         for (i = 0; i < adapter->num_tx_queues; i++) {
4756                 kfree(adapter->tx_ring[i]);
4757                 adapter->tx_ring[i] = NULL;
4758         }
4759         for (i = 0; i < adapter->num_rx_queues; i++) {
4760                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4761
4762                 /* ixgbe_get_stats64() might access this ring, we must wait
4763                  * a grace period before freeing it.
4764                  */
4765                 kfree_rcu(ring, rcu);
4766                 adapter->rx_ring[i] = NULL;
4767         }
4768
4769         adapter->num_tx_queues = 0;
4770         adapter->num_rx_queues = 0;
4771
4772         ixgbe_free_q_vectors(adapter);
4773         ixgbe_reset_interrupt_capability(adapter);
4774 }
4775
4776 /**
4777  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4778  * @adapter: board private structure to initialize
4779  *
4780  * ixgbe_sw_init initializes the Adapter private data structure.
4781  * Fields are initialized based on PCI device information and
4782  * OS network device settings (MTU size).
4783  **/
4784 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4785 {
4786         struct ixgbe_hw *hw = &adapter->hw;
4787         struct pci_dev *pdev = adapter->pdev;
4788         struct net_device *dev = adapter->netdev;
4789         unsigned int rss;
4790 #ifdef CONFIG_IXGBE_DCB
4791         int j;
4792         struct tc_configuration *tc;
4793 #endif
4794         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4795
4796         /* PCI config space info */
4797
4798         hw->vendor_id = pdev->vendor;
4799         hw->device_id = pdev->device;
4800         hw->revision_id = pdev->revision;
4801         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4802         hw->subsystem_device_id = pdev->subsystem_device;
4803
4804         /* Set capability flags */
4805         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4806         adapter->ring_feature[RING_F_RSS].indices = rss;
4807         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4808         switch (hw->mac.type) {
4809         case ixgbe_mac_82598EB:
4810                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4811                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4812                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4813                 break;
4814         case ixgbe_mac_82599EB:
4815         case ixgbe_mac_X540:
4816                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4817                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4818                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4819                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4820                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4821                 /* Flow Director hash filters enabled */
4822                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4823                 adapter->atr_sample_rate = 20;
4824                 adapter->ring_feature[RING_F_FDIR].indices =
4825                                                          IXGBE_MAX_FDIR_INDICES;
4826                 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4827 #ifdef IXGBE_FCOE
4828                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4829                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4830                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4831 #ifdef CONFIG_IXGBE_DCB
4832                 /* Default traffic class to use for FCoE */
4833                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4834 #endif
4835 #endif /* IXGBE_FCOE */
4836                 break;
4837         default:
4838                 break;
4839         }
4840
4841         /* n-tuple support exists, always init our spinlock */
4842         spin_lock_init(&adapter->fdir_perfect_lock);
4843
4844 #ifdef CONFIG_IXGBE_DCB
4845         /* Configure DCB traffic classes */
4846         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4847                 tc = &adapter->dcb_cfg.tc_config[j];
4848                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4849                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4850                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4851                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4852                 tc->dcb_pfc = pfc_disabled;
4853         }
4854         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4855         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4856         adapter->dcb_cfg.pfc_mode_enable = false;
4857         adapter->dcb_set_bitmap = 0x00;
4858         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4859         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4860                            MAX_TRAFFIC_CLASS);
4861
4862 #endif
4863
4864         /* default flow control settings */
4865         hw->fc.requested_mode = ixgbe_fc_full;
4866         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4867 #ifdef CONFIG_DCB
4868         adapter->last_lfc_mode = hw->fc.current_mode;
4869 #endif
4870         hw->fc.high_water = FC_HIGH_WATER(max_frame);
4871         hw->fc.low_water = FC_LOW_WATER(max_frame);
4872         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4873         hw->fc.send_xon = true;
4874         hw->fc.disable_fc_autoneg = false;
4875
4876         /* enable itr by default in dynamic mode */
4877         adapter->rx_itr_setting = 1;
4878         adapter->rx_eitr_param = 20000;
4879         adapter->tx_itr_setting = 1;
4880         adapter->tx_eitr_param = 10000;
4881
4882         /* set defaults for eitr in MegaBytes */
4883         adapter->eitr_low = 10;
4884         adapter->eitr_high = 20;
4885
4886         /* set default ring sizes */
4887         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4888         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4889
4890         /* set default work limits */
4891         adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4892
4893         /* initialize eeprom parameters */
4894         if (ixgbe_init_eeprom_params_generic(hw)) {
4895                 e_dev_err("EEPROM initialization failed\n");
4896                 return -EIO;
4897         }
4898
4899         /* enable rx csum by default */
4900         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4901
4902         /* get assigned NUMA node */
4903         adapter->node = dev_to_node(&pdev->dev);
4904
4905         set_bit(__IXGBE_DOWN, &adapter->state);
4906
4907         return 0;
4908 }
4909
4910 /**
4911  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4912  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4913  *
4914  * Return 0 on success, negative on failure
4915  **/
4916 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4917 {
4918         struct device *dev = tx_ring->dev;
4919         int size;
4920
4921         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4922         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
4923         if (!tx_ring->tx_buffer_info)
4924                 tx_ring->tx_buffer_info = vzalloc(size);
4925         if (!tx_ring->tx_buffer_info)
4926                 goto err;
4927
4928         /* round up to nearest 4K */
4929         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4930         tx_ring->size = ALIGN(tx_ring->size, 4096);
4931
4932         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4933                                            &tx_ring->dma, GFP_KERNEL);
4934         if (!tx_ring->desc)
4935                 goto err;
4936
4937         tx_ring->next_to_use = 0;
4938         tx_ring->next_to_clean = 0;
4939         return 0;
4940
4941 err:
4942         vfree(tx_ring->tx_buffer_info);
4943         tx_ring->tx_buffer_info = NULL;
4944         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4945         return -ENOMEM;
4946 }
4947
4948 /**
4949  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4950  * @adapter: board private structure
4951  *
4952  * If this function returns with an error, then it's possible one or
4953  * more of the rings is populated (while the rest are not).  It is the
4954  * callers duty to clean those orphaned rings.
4955  *
4956  * Return 0 on success, negative on failure
4957  **/
4958 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4959 {
4960         int i, err = 0;
4961
4962         for (i = 0; i < adapter->num_tx_queues; i++) {
4963                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4964                 if (!err)
4965                         continue;
4966                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4967                 break;
4968         }
4969
4970         return err;
4971 }
4972
4973 /**
4974  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4975  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
4976  *
4977  * Returns 0 on success, negative on failure
4978  **/
4979 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4980 {
4981         struct device *dev = rx_ring->dev;
4982         int size;
4983
4984         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4985         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
4986         if (!rx_ring->rx_buffer_info)
4987                 rx_ring->rx_buffer_info = vzalloc(size);
4988         if (!rx_ring->rx_buffer_info)
4989                 goto err;
4990
4991         /* Round up to nearest 4K */
4992         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4993         rx_ring->size = ALIGN(rx_ring->size, 4096);
4994
4995         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4996                                            &rx_ring->dma, GFP_KERNEL);
4997
4998         if (!rx_ring->desc)
4999                 goto err;
5000
5001         rx_ring->next_to_clean = 0;
5002         rx_ring->next_to_use = 0;
5003
5004         return 0;
5005 err:
5006         vfree(rx_ring->rx_buffer_info);
5007         rx_ring->rx_buffer_info = NULL;
5008         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5009         return -ENOMEM;
5010 }
5011
5012 /**
5013  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5014  * @adapter: board private structure
5015  *
5016  * If this function returns with an error, then it's possible one or
5017  * more of the rings is populated (while the rest are not).  It is the
5018  * callers duty to clean those orphaned rings.
5019  *
5020  * Return 0 on success, negative on failure
5021  **/
5022 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5023 {
5024         int i, err = 0;
5025
5026         for (i = 0; i < adapter->num_rx_queues; i++) {
5027                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5028                 if (!err)
5029                         continue;
5030                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5031                 break;
5032         }
5033
5034         return err;
5035 }
5036
5037 /**
5038  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5039  * @tx_ring: Tx descriptor ring for a specific queue
5040  *
5041  * Free all transmit software resources
5042  **/
5043 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5044 {
5045         ixgbe_clean_tx_ring(tx_ring);
5046
5047         vfree(tx_ring->tx_buffer_info);
5048         tx_ring->tx_buffer_info = NULL;
5049
5050         /* if not set, then don't free */
5051         if (!tx_ring->desc)
5052                 return;
5053
5054         dma_free_coherent(tx_ring->dev, tx_ring->size,
5055                           tx_ring->desc, tx_ring->dma);
5056
5057         tx_ring->desc = NULL;
5058 }
5059
5060 /**
5061  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5062  * @adapter: board private structure
5063  *
5064  * Free all transmit software resources
5065  **/
5066 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5067 {
5068         int i;
5069
5070         for (i = 0; i < adapter->num_tx_queues; i++)
5071                 if (adapter->tx_ring[i]->desc)
5072                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5073 }
5074
5075 /**
5076  * ixgbe_free_rx_resources - Free Rx Resources
5077  * @rx_ring: ring to clean the resources from
5078  *
5079  * Free all receive software resources
5080  **/
5081 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5082 {
5083         ixgbe_clean_rx_ring(rx_ring);
5084
5085         vfree(rx_ring->rx_buffer_info);
5086         rx_ring->rx_buffer_info = NULL;
5087
5088         /* if not set, then don't free */
5089         if (!rx_ring->desc)
5090                 return;
5091
5092         dma_free_coherent(rx_ring->dev, rx_ring->size,
5093                           rx_ring->desc, rx_ring->dma);
5094
5095         rx_ring->desc = NULL;
5096 }
5097
5098 /**
5099  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5100  * @adapter: board private structure
5101  *
5102  * Free all receive software resources
5103  **/
5104 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5105 {
5106         int i;
5107
5108         for (i = 0; i < adapter->num_rx_queues; i++)
5109                 if (adapter->rx_ring[i]->desc)
5110                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5111 }
5112
5113 /**
5114  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5115  * @netdev: network interface device structure
5116  * @new_mtu: new value for maximum frame size
5117  *
5118  * Returns 0 on success, negative on failure
5119  **/
5120 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5121 {
5122         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5123         struct ixgbe_hw *hw = &adapter->hw;
5124         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5125
5126         /* MTU < 68 is an error and causes problems on some kernels */
5127         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5128             hw->mac.type != ixgbe_mac_X540) {
5129                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5130                         return -EINVAL;
5131         } else {
5132                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5133                         return -EINVAL;
5134         }
5135
5136         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5137         /* must set new MTU before calling down or up */
5138         netdev->mtu = new_mtu;
5139
5140         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5141         hw->fc.low_water = FC_LOW_WATER(max_frame);
5142
5143         if (netif_running(netdev))
5144                 ixgbe_reinit_locked(adapter);
5145
5146         return 0;
5147 }
5148
5149 /**
5150  * ixgbe_open - Called when a network interface is made active
5151  * @netdev: network interface device structure
5152  *
5153  * Returns 0 on success, negative value on failure
5154  *
5155  * The open entry point is called when a network interface is made
5156  * active by the system (IFF_UP).  At this point all resources needed
5157  * for transmit and receive operations are allocated, the interrupt
5158  * handler is registered with the OS, the watchdog timer is started,
5159  * and the stack is notified that the interface is ready.
5160  **/
5161 static int ixgbe_open(struct net_device *netdev)
5162 {
5163         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5164         int err;
5165
5166         /* disallow open during test */
5167         if (test_bit(__IXGBE_TESTING, &adapter->state))
5168                 return -EBUSY;
5169
5170         netif_carrier_off(netdev);
5171
5172         /* allocate transmit descriptors */
5173         err = ixgbe_setup_all_tx_resources(adapter);
5174         if (err)
5175                 goto err_setup_tx;
5176
5177         /* allocate receive descriptors */
5178         err = ixgbe_setup_all_rx_resources(adapter);
5179         if (err)
5180                 goto err_setup_rx;
5181
5182         ixgbe_configure(adapter);
5183
5184         err = ixgbe_request_irq(adapter);
5185         if (err)
5186                 goto err_req_irq;
5187
5188         err = ixgbe_up_complete(adapter);
5189         if (err)
5190                 goto err_up;
5191
5192         netif_tx_start_all_queues(netdev);
5193
5194         return 0;
5195
5196 err_up:
5197         ixgbe_release_hw_control(adapter);
5198         ixgbe_free_irq(adapter);
5199 err_req_irq:
5200 err_setup_rx:
5201         ixgbe_free_all_rx_resources(adapter);
5202 err_setup_tx:
5203         ixgbe_free_all_tx_resources(adapter);
5204         ixgbe_reset(adapter);
5205
5206         return err;
5207 }
5208
5209 /**
5210  * ixgbe_close - Disables a network interface
5211  * @netdev: network interface device structure
5212  *
5213  * Returns 0, this is not allowed to fail
5214  *
5215  * The close entry point is called when an interface is de-activated
5216  * by the OS.  The hardware is still under the drivers control, but
5217  * needs to be disabled.  A global MAC reset is issued to stop the
5218  * hardware, and all transmit and receive resources are freed.
5219  **/
5220 static int ixgbe_close(struct net_device *netdev)
5221 {
5222         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5223
5224         ixgbe_down(adapter);
5225         ixgbe_free_irq(adapter);
5226
5227         ixgbe_fdir_filter_exit(adapter);
5228
5229         ixgbe_free_all_tx_resources(adapter);
5230         ixgbe_free_all_rx_resources(adapter);
5231
5232         ixgbe_release_hw_control(adapter);
5233
5234         return 0;
5235 }
5236
5237 #ifdef CONFIG_PM
5238 static int ixgbe_resume(struct pci_dev *pdev)
5239 {
5240         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5241         struct net_device *netdev = adapter->netdev;
5242         u32 err;
5243
5244         pci_set_power_state(pdev, PCI_D0);
5245         pci_restore_state(pdev);
5246         /*
5247          * pci_restore_state clears dev->state_saved so call
5248          * pci_save_state to restore it.
5249          */
5250         pci_save_state(pdev);
5251
5252         err = pci_enable_device_mem(pdev);
5253         if (err) {
5254                 e_dev_err("Cannot enable PCI device from suspend\n");
5255                 return err;
5256         }
5257         pci_set_master(pdev);
5258
5259         pci_wake_from_d3(pdev, false);
5260
5261         err = ixgbe_init_interrupt_scheme(adapter);
5262         if (err) {
5263                 e_dev_err("Cannot initialize interrupts for device\n");
5264                 return err;
5265         }
5266
5267         ixgbe_reset(adapter);
5268
5269         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5270
5271         if (netif_running(netdev)) {
5272                 err = ixgbe_open(netdev);
5273                 if (err)
5274                         return err;
5275         }
5276
5277         netif_device_attach(netdev);
5278
5279         return 0;
5280 }
5281 #endif /* CONFIG_PM */
5282
5283 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5284 {
5285         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5286         struct net_device *netdev = adapter->netdev;
5287         struct ixgbe_hw *hw = &adapter->hw;
5288         u32 ctrl, fctrl;
5289         u32 wufc = adapter->wol;
5290 #ifdef CONFIG_PM
5291         int retval = 0;
5292 #endif
5293
5294         netif_device_detach(netdev);
5295
5296         if (netif_running(netdev)) {
5297                 ixgbe_down(adapter);
5298                 ixgbe_free_irq(adapter);
5299                 ixgbe_free_all_tx_resources(adapter);
5300                 ixgbe_free_all_rx_resources(adapter);
5301         }
5302
5303         ixgbe_clear_interrupt_scheme(adapter);
5304 #ifdef CONFIG_DCB
5305         kfree(adapter->ixgbe_ieee_pfc);
5306         kfree(adapter->ixgbe_ieee_ets);
5307 #endif
5308
5309 #ifdef CONFIG_PM
5310         retval = pci_save_state(pdev);
5311         if (retval)
5312                 return retval;
5313
5314 #endif
5315         if (wufc) {
5316                 ixgbe_set_rx_mode(netdev);
5317
5318                 /* turn on all-multi mode if wake on multicast is enabled */
5319                 if (wufc & IXGBE_WUFC_MC) {
5320                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5321                         fctrl |= IXGBE_FCTRL_MPE;
5322                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5323                 }
5324
5325                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5326                 ctrl |= IXGBE_CTRL_GIO_DIS;
5327                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5328
5329                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5330         } else {
5331                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5332                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5333         }
5334
5335         switch (hw->mac.type) {
5336         case ixgbe_mac_82598EB:
5337                 pci_wake_from_d3(pdev, false);
5338                 break;
5339         case ixgbe_mac_82599EB:
5340         case ixgbe_mac_X540:
5341                 pci_wake_from_d3(pdev, !!wufc);
5342                 break;
5343         default:
5344                 break;
5345         }
5346
5347         *enable_wake = !!wufc;
5348
5349         ixgbe_release_hw_control(adapter);
5350
5351         pci_disable_device(pdev);
5352
5353         return 0;
5354 }
5355
5356 #ifdef CONFIG_PM
5357 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5358 {
5359         int retval;
5360         bool wake;
5361
5362         retval = __ixgbe_shutdown(pdev, &wake);
5363         if (retval)
5364                 return retval;
5365
5366         if (wake) {
5367                 pci_prepare_to_sleep(pdev);
5368         } else {
5369                 pci_wake_from_d3(pdev, false);
5370                 pci_set_power_state(pdev, PCI_D3hot);
5371         }
5372
5373         return 0;
5374 }
5375 #endif /* CONFIG_PM */
5376
5377 static void ixgbe_shutdown(struct pci_dev *pdev)
5378 {
5379         bool wake;
5380
5381         __ixgbe_shutdown(pdev, &wake);
5382
5383         if (system_state == SYSTEM_POWER_OFF) {
5384                 pci_wake_from_d3(pdev, wake);
5385                 pci_set_power_state(pdev, PCI_D3hot);
5386         }
5387 }
5388
5389 /**
5390  * ixgbe_update_stats - Update the board statistics counters.
5391  * @adapter: board private structure
5392  **/
5393 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5394 {
5395         struct net_device *netdev = adapter->netdev;
5396         struct ixgbe_hw *hw = &adapter->hw;
5397         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5398         u64 total_mpc = 0;
5399         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5400         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5401         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5402         u64 bytes = 0, packets = 0;
5403
5404         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5405             test_bit(__IXGBE_RESETTING, &adapter->state))
5406                 return;
5407
5408         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5409                 u64 rsc_count = 0;
5410                 u64 rsc_flush = 0;
5411                 for (i = 0; i < 16; i++)
5412                         adapter->hw_rx_no_dma_resources +=
5413                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5414                 for (i = 0; i < adapter->num_rx_queues; i++) {
5415                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5416                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5417                 }
5418                 adapter->rsc_total_count = rsc_count;
5419                 adapter->rsc_total_flush = rsc_flush;
5420         }
5421
5422         for (i = 0; i < adapter->num_rx_queues; i++) {
5423                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5424                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5425                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5426                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5427                 bytes += rx_ring->stats.bytes;
5428                 packets += rx_ring->stats.packets;
5429         }
5430         adapter->non_eop_descs = non_eop_descs;
5431         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5432         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5433         netdev->stats.rx_bytes = bytes;
5434         netdev->stats.rx_packets = packets;
5435
5436         bytes = 0;
5437         packets = 0;
5438         /* gather some stats to the adapter struct that are per queue */
5439         for (i = 0; i < adapter->num_tx_queues; i++) {
5440                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5441                 restart_queue += tx_ring->tx_stats.restart_queue;
5442                 tx_busy += tx_ring->tx_stats.tx_busy;
5443                 bytes += tx_ring->stats.bytes;
5444                 packets += tx_ring->stats.packets;
5445         }
5446         adapter->restart_queue = restart_queue;
5447         adapter->tx_busy = tx_busy;
5448         netdev->stats.tx_bytes = bytes;
5449         netdev->stats.tx_packets = packets;
5450
5451         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5452         for (i = 0; i < 8; i++) {
5453                 /* for packet buffers not used, the register should read 0 */
5454                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5455                 missed_rx += mpc;
5456                 hwstats->mpc[i] += mpc;
5457                 total_mpc += hwstats->mpc[i];
5458                 if (hw->mac.type == ixgbe_mac_82598EB)
5459                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5460                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5461                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5462                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5463                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5464                 switch (hw->mac.type) {
5465                 case ixgbe_mac_82598EB:
5466                         hwstats->pxonrxc[i] +=
5467                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5468                         break;
5469                 case ixgbe_mac_82599EB:
5470                 case ixgbe_mac_X540:
5471                         hwstats->pxonrxc[i] +=
5472                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5473                         break;
5474                 default:
5475                         break;
5476                 }
5477                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5478                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5479         }
5480         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5481         /* work around hardware counting issue */
5482         hwstats->gprc -= missed_rx;
5483
5484         ixgbe_update_xoff_received(adapter);
5485
5486         /* 82598 hardware only has a 32 bit counter in the high register */
5487         switch (hw->mac.type) {
5488         case ixgbe_mac_82598EB:
5489                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5490                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5491                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5492                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5493                 break;
5494         case ixgbe_mac_X540:
5495                 /* OS2BMC stats are X540 only*/
5496                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5497                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5498                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5499                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5500         case ixgbe_mac_82599EB:
5501                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5502                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5503                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5504                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5505                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5506                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5507                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5508                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5509                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5510 #ifdef IXGBE_FCOE
5511                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5512                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5513                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5514                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5515                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5516                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5517 #endif /* IXGBE_FCOE */
5518                 break;
5519         default:
5520                 break;
5521         }
5522         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5523         hwstats->bprc += bprc;
5524         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5525         if (hw->mac.type == ixgbe_mac_82598EB)
5526                 hwstats->mprc -= bprc;
5527         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5528         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5529         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5530         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5531         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5532         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5533         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5534         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5535         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5536         hwstats->lxontxc += lxon;
5537         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5538         hwstats->lxofftxc += lxoff;
5539         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5540         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5541         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5542         /*
5543          * 82598 errata - tx of flow control packets is included in tx counters
5544          */
5545         xon_off_tot = lxon + lxoff;
5546         hwstats->gptc -= xon_off_tot;
5547         hwstats->mptc -= xon_off_tot;
5548         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5549         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5550         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5551         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5552         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5553         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5554         hwstats->ptc64 -= xon_off_tot;
5555         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5556         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5557         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5558         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5559         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5560         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5561
5562         /* Fill out the OS statistics structure */
5563         netdev->stats.multicast = hwstats->mprc;
5564
5565         /* Rx Errors */
5566         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5567         netdev->stats.rx_dropped = 0;
5568         netdev->stats.rx_length_errors = hwstats->rlec;
5569         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5570         netdev->stats.rx_missed_errors = total_mpc;
5571 }
5572
5573 /**
5574  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5575  * @adapter - pointer to the device adapter structure
5576  **/
5577 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5578 {
5579         struct ixgbe_hw *hw = &adapter->hw;
5580         int i;
5581
5582         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5583                 return;
5584
5585         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5586
5587         /* if interface is down do nothing */
5588         if (test_bit(__IXGBE_DOWN, &adapter->state))
5589                 return;
5590
5591         /* do nothing if we are not using signature filters */
5592         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5593                 return;
5594
5595         adapter->fdir_overflow++;
5596
5597         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5598                 for (i = 0; i < adapter->num_tx_queues; i++)
5599                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5600                                 &(adapter->tx_ring[i]->state));
5601                 /* re-enable flow director interrupts */
5602                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5603         } else {
5604                 e_err(probe, "failed to finish FDIR re-initialization, "
5605                       "ignored adding FDIR ATR filters\n");
5606         }
5607 }
5608
5609 /**
5610  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5611  * @adapter - pointer to the device adapter structure
5612  *
5613  * This function serves two purposes.  First it strobes the interrupt lines
5614  * in order to make certain interrupts are occuring.  Secondly it sets the
5615  * bits needed to check for TX hangs.  As a result we should immediately
5616  * determine if a hang has occured.
5617  */
5618 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5619 {
5620         struct ixgbe_hw *hw = &adapter->hw;
5621         u64 eics = 0;
5622         int i;
5623
5624         /* If we're down or resetting, just bail */
5625         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5626             test_bit(__IXGBE_RESETTING, &adapter->state))
5627                 return;
5628
5629         /* Force detection of hung controller */
5630         if (netif_carrier_ok(adapter->netdev)) {
5631                 for (i = 0; i < adapter->num_tx_queues; i++)
5632                         set_check_for_tx_hang(adapter->tx_ring[i]);
5633         }
5634
5635         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5636                 /*
5637                  * for legacy and MSI interrupts don't set any bits
5638                  * that are enabled for EIAM, because this operation
5639                  * would set *both* EIMS and EICS for any bit in EIAM
5640                  */
5641                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5642                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5643         } else {
5644                 /* get one bit for every active tx/rx interrupt vector */
5645                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5646                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
5647                         if (qv->rx.ring || qv->tx.ring)
5648                                 eics |= ((u64)1 << i);
5649                 }
5650         }
5651
5652         /* Cause software interrupt to ensure rings are cleaned */
5653         ixgbe_irq_rearm_queues(adapter, eics);
5654
5655 }
5656
5657 /**
5658  * ixgbe_watchdog_update_link - update the link status
5659  * @adapter - pointer to the device adapter structure
5660  * @link_speed - pointer to a u32 to store the link_speed
5661  **/
5662 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5663 {
5664         struct ixgbe_hw *hw = &adapter->hw;
5665         u32 link_speed = adapter->link_speed;
5666         bool link_up = adapter->link_up;
5667         int i;
5668
5669         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5670                 return;
5671
5672         if (hw->mac.ops.check_link) {
5673                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5674         } else {
5675                 /* always assume link is up, if no check link function */
5676                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5677                 link_up = true;
5678         }
5679         if (link_up) {
5680                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5681                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5682                                 hw->mac.ops.fc_enable(hw, i);
5683                 } else {
5684                         hw->mac.ops.fc_enable(hw, 0);
5685                 }
5686         }
5687
5688         if (link_up ||
5689             time_after(jiffies, (adapter->link_check_timeout +
5690                                  IXGBE_TRY_LINK_TIMEOUT))) {
5691                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5692                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5693                 IXGBE_WRITE_FLUSH(hw);
5694         }
5695
5696         adapter->link_up = link_up;
5697         adapter->link_speed = link_speed;
5698 }
5699
5700 /**
5701  * ixgbe_watchdog_link_is_up - update netif_carrier status and
5702  *                             print link up message
5703  * @adapter - pointer to the device adapter structure
5704  **/
5705 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5706 {
5707         struct net_device *netdev = adapter->netdev;
5708         struct ixgbe_hw *hw = &adapter->hw;
5709         u32 link_speed = adapter->link_speed;
5710         bool flow_rx, flow_tx;
5711
5712         /* only continue if link was previously down */
5713         if (netif_carrier_ok(netdev))
5714                 return;
5715
5716         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5717
5718         switch (hw->mac.type) {
5719         case ixgbe_mac_82598EB: {
5720                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5721                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5722                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5723                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5724         }
5725                 break;
5726         case ixgbe_mac_X540:
5727         case ixgbe_mac_82599EB: {
5728                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5729                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5730                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5731                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5732         }
5733                 break;
5734         default:
5735                 flow_tx = false;
5736                 flow_rx = false;
5737                 break;
5738         }
5739         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5740                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5741                "10 Gbps" :
5742                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5743                "1 Gbps" :
5744                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5745                "100 Mbps" :
5746                "unknown speed"))),
5747                ((flow_rx && flow_tx) ? "RX/TX" :
5748                (flow_rx ? "RX" :
5749                (flow_tx ? "TX" : "None"))));
5750
5751         netif_carrier_on(netdev);
5752         ixgbe_check_vf_rate_limit(adapter);
5753 }
5754
5755 /**
5756  * ixgbe_watchdog_link_is_down - update netif_carrier status and
5757  *                               print link down message
5758  * @adapter - pointer to the adapter structure
5759  **/
5760 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5761 {
5762         struct net_device *netdev = adapter->netdev;
5763         struct ixgbe_hw *hw = &adapter->hw;
5764
5765         adapter->link_up = false;
5766         adapter->link_speed = 0;
5767
5768         /* only continue if link was up previously */
5769         if (!netif_carrier_ok(netdev))
5770                 return;
5771
5772         /* poll for SFP+ cable when link is down */
5773         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5774                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5775
5776         e_info(drv, "NIC Link is Down\n");
5777         netif_carrier_off(netdev);
5778 }
5779
5780 /**
5781  * ixgbe_watchdog_flush_tx - flush queues on link down
5782  * @adapter - pointer to the device adapter structure
5783  **/
5784 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5785 {
5786         int i;
5787         int some_tx_pending = 0;
5788
5789         if (!netif_carrier_ok(adapter->netdev)) {
5790                 for (i = 0; i < adapter->num_tx_queues; i++) {
5791                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5792                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5793                                 some_tx_pending = 1;
5794                                 break;
5795                         }
5796                 }
5797
5798                 if (some_tx_pending) {
5799                         /* We've lost link, so the controller stops DMA,
5800                          * but we've got queued Tx work that's never going
5801                          * to get done, so reset controller to flush Tx.
5802                          * (Do the reset outside of interrupt context).
5803                          */
5804                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5805                 }
5806         }
5807 }
5808
5809 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5810 {
5811         u32 ssvpc;
5812
5813         /* Do not perform spoof check for 82598 */
5814         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5815                 return;
5816
5817         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5818
5819         /*
5820          * ssvpc register is cleared on read, if zero then no
5821          * spoofed packets in the last interval.
5822          */
5823         if (!ssvpc)
5824                 return;
5825
5826         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5827 }
5828
5829 /**
5830  * ixgbe_watchdog_subtask - check and bring link up
5831  * @adapter - pointer to the device adapter structure
5832  **/
5833 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5834 {
5835         /* if interface is down do nothing */
5836         if (test_bit(__IXGBE_DOWN, &adapter->state))
5837                 return;
5838
5839         ixgbe_watchdog_update_link(adapter);
5840
5841         if (adapter->link_up)
5842                 ixgbe_watchdog_link_is_up(adapter);
5843         else
5844                 ixgbe_watchdog_link_is_down(adapter);
5845
5846         ixgbe_spoof_check(adapter);
5847         ixgbe_update_stats(adapter);
5848
5849         ixgbe_watchdog_flush_tx(adapter);
5850 }
5851
5852 /**
5853  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5854  * @adapter - the ixgbe adapter structure
5855  **/
5856 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5857 {
5858         struct ixgbe_hw *hw = &adapter->hw;
5859         s32 err;
5860
5861         /* not searching for SFP so there is nothing to do here */
5862         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5863             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5864                 return;
5865
5866         /* someone else is in init, wait until next service event */
5867         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5868                 return;
5869
5870         err = hw->phy.ops.identify_sfp(hw);
5871         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5872                 goto sfp_out;
5873
5874         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5875                 /* If no cable is present, then we need to reset
5876                  * the next time we find a good cable. */
5877                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5878         }
5879
5880         /* exit on error */
5881         if (err)
5882                 goto sfp_out;
5883
5884         /* exit if reset not needed */
5885         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5886                 goto sfp_out;
5887
5888         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5889
5890         /*
5891          * A module may be identified correctly, but the EEPROM may not have
5892          * support for that module.  setup_sfp() will fail in that case, so
5893          * we should not allow that module to load.
5894          */
5895         if (hw->mac.type == ixgbe_mac_82598EB)
5896                 err = hw->phy.ops.reset(hw);
5897         else
5898                 err = hw->mac.ops.setup_sfp(hw);
5899
5900         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5901                 goto sfp_out;
5902
5903         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5904         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5905
5906 sfp_out:
5907         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5908
5909         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5910             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5911                 e_dev_err("failed to initialize because an unsupported "
5912                           "SFP+ module type was detected.\n");
5913                 e_dev_err("Reload the driver after installing a "
5914                           "supported module.\n");
5915                 unregister_netdev(adapter->netdev);
5916         }
5917 }
5918
5919 /**
5920  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5921  * @adapter - the ixgbe adapter structure
5922  **/
5923 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5924 {
5925         struct ixgbe_hw *hw = &adapter->hw;
5926         u32 autoneg;
5927         bool negotiation;
5928
5929         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5930                 return;
5931
5932         /* someone else is in init, wait until next service event */
5933         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5934                 return;
5935
5936         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5937
5938         autoneg = hw->phy.autoneg_advertised;
5939         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5940                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5941         hw->mac.autotry_restart = false;
5942         if (hw->mac.ops.setup_link)
5943                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5944
5945         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5946         adapter->link_check_timeout = jiffies;
5947         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5948 }
5949
5950 /**
5951  * ixgbe_service_timer - Timer Call-back
5952  * @data: pointer to adapter cast into an unsigned long
5953  **/
5954 static void ixgbe_service_timer(unsigned long data)
5955 {
5956         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5957         unsigned long next_event_offset;
5958
5959         /* poll faster when waiting for link */
5960         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5961                 next_event_offset = HZ / 10;
5962         else
5963                 next_event_offset = HZ * 2;
5964
5965         /* Reset the timer */
5966         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5967
5968         ixgbe_service_event_schedule(adapter);
5969 }
5970
5971 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5972 {
5973         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5974                 return;
5975
5976         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5977
5978         /* If we're already down or resetting, just bail */
5979         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5980             test_bit(__IXGBE_RESETTING, &adapter->state))
5981                 return;
5982
5983         ixgbe_dump(adapter);
5984         netdev_err(adapter->netdev, "Reset adapter\n");
5985         adapter->tx_timeout_count++;
5986
5987         ixgbe_reinit_locked(adapter);
5988 }
5989
5990 /**
5991  * ixgbe_service_task - manages and runs subtasks
5992  * @work: pointer to work_struct containing our data
5993  **/
5994 static void ixgbe_service_task(struct work_struct *work)
5995 {
5996         struct ixgbe_adapter *adapter = container_of(work,
5997                                                      struct ixgbe_adapter,
5998                                                      service_task);
5999
6000         ixgbe_reset_subtask(adapter);
6001         ixgbe_sfp_detection_subtask(adapter);
6002         ixgbe_sfp_link_config_subtask(adapter);
6003         ixgbe_check_overtemp_subtask(adapter);
6004         ixgbe_watchdog_subtask(adapter);
6005         ixgbe_fdir_reinit_subtask(adapter);
6006         ixgbe_check_hang_subtask(adapter);
6007
6008         ixgbe_service_event_complete(adapter);
6009 }
6010
6011 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6012                        u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6013 {
6014         struct ixgbe_adv_tx_context_desc *context_desc;
6015         u16 i = tx_ring->next_to_use;
6016
6017         context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6018
6019         i++;
6020         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6021
6022         /* set bits to identify this as an advanced context descriptor */
6023         type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6024
6025         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
6026         context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
6027         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
6028         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
6029 }
6030
6031 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6032                      u32 tx_flags, __be16 protocol, u8 *hdr_len)
6033 {
6034         int err;
6035         u32 vlan_macip_lens, type_tucmd;
6036         u32 mss_l4len_idx, l4len;
6037
6038         if (!skb_is_gso(skb))
6039                 return 0;
6040
6041         if (skb_header_cloned(skb)) {
6042                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6043                 if (err)
6044                         return err;
6045         }
6046
6047         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6048         type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6049
6050         if (protocol == __constant_htons(ETH_P_IP)) {
6051                 struct iphdr *iph = ip_hdr(skb);
6052                 iph->tot_len = 0;
6053                 iph->check = 0;
6054                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6055                                                          iph->daddr, 0,
6056                                                          IPPROTO_TCP,
6057                                                          0);
6058                 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6059         } else if (skb_is_gso_v6(skb)) {
6060                 ipv6_hdr(skb)->payload_len = 0;
6061                 tcp_hdr(skb)->check =
6062                     ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6063                                      &ipv6_hdr(skb)->daddr,
6064                                      0, IPPROTO_TCP, 0);
6065         }
6066
6067         l4len = tcp_hdrlen(skb);
6068         *hdr_len = skb_transport_offset(skb) + l4len;
6069
6070         /* mss_l4len_id: use 1 as index for TSO */
6071         mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6072         mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6073         mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6074
6075         /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6076         vlan_macip_lens = skb_network_header_len(skb);
6077         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6078         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6079
6080         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6081                           mss_l4len_idx);
6082
6083         return 1;
6084 }
6085
6086 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6087                           struct sk_buff *skb, u32 tx_flags,
6088                           __be16 protocol)
6089 {
6090         u32 vlan_macip_lens = 0;
6091         u32 mss_l4len_idx = 0;
6092         u32 type_tucmd = 0;
6093
6094         if (skb->ip_summed != CHECKSUM_PARTIAL) {
6095             if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6096                 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6097                         return false;
6098         } else {
6099                 u8 l4_hdr = 0;
6100                 switch (protocol) {
6101                 case __constant_htons(ETH_P_IP):
6102                         vlan_macip_lens |= skb_network_header_len(skb);
6103                         type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6104                         l4_hdr = ip_hdr(skb)->protocol;
6105                         break;
6106                 case __constant_htons(ETH_P_IPV6):
6107                         vlan_macip_lens |= skb_network_header_len(skb);
6108                         l4_hdr = ipv6_hdr(skb)->nexthdr;
6109                         break;
6110                 default:
6111                         if (unlikely(net_ratelimit())) {
6112                                 dev_warn(tx_ring->dev,
6113                                  "partial checksum but proto=%x!\n",
6114                                  skb->protocol);
6115                         }
6116                         break;
6117                 }
6118
6119                 switch (l4_hdr) {
6120                 case IPPROTO_TCP:
6121                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6122                         mss_l4len_idx = tcp_hdrlen(skb) <<
6123                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6124                         break;
6125                 case IPPROTO_SCTP:
6126                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6127                         mss_l4len_idx = sizeof(struct sctphdr) <<
6128                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6129                         break;
6130                 case IPPROTO_UDP:
6131                         mss_l4len_idx = sizeof(struct udphdr) <<
6132                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6133                         break;
6134                 default:
6135                         if (unlikely(net_ratelimit())) {
6136                                 dev_warn(tx_ring->dev,
6137                                  "partial checksum but l4 proto=%x!\n",
6138                                  skb->protocol);
6139                         }
6140                         break;
6141                 }
6142         }
6143
6144         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6145         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6146
6147         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6148                           type_tucmd, mss_l4len_idx);
6149
6150         return (skb->ip_summed == CHECKSUM_PARTIAL);
6151 }
6152
6153 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6154 {
6155         /* set type for advanced descriptor with frame checksum insertion */
6156         __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6157                                       IXGBE_ADVTXD_DCMD_IFCS |
6158                                       IXGBE_ADVTXD_DCMD_DEXT);
6159
6160         /* set HW vlan bit if vlan is present */
6161         if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6162                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6163
6164         /* set segmentation enable bits for TSO/FSO */
6165 #ifdef IXGBE_FCOE
6166         if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6167 #else
6168         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6169 #endif
6170                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6171
6172         return cmd_type;
6173 }
6174
6175 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6176 {
6177         __le32 olinfo_status =
6178                 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6179
6180         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6181                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6182                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6183                 /* enble IPv4 checksum for TSO */
6184                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6185                         olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6186         }
6187
6188         /* enable L4 checksum for TSO and TX checksum offload */
6189         if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6190                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6191
6192 #ifdef IXGBE_FCOE
6193         /* use index 1 context for FCOE/FSO */
6194         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6195                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6196                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6197
6198 #endif
6199         /*
6200          * Check Context must be set if Tx switch is enabled, which it
6201          * always is for case where virtual functions are running
6202          */
6203         if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6204                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6205
6206         return olinfo_status;
6207 }
6208
6209 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6210                        IXGBE_TXD_CMD_RS)
6211
6212 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6213                          struct sk_buff *skb,
6214                          struct ixgbe_tx_buffer *first,
6215                          u32 tx_flags,
6216                          const u8 hdr_len)
6217 {
6218         struct device *dev = tx_ring->dev;
6219         struct ixgbe_tx_buffer *tx_buffer_info;
6220         union ixgbe_adv_tx_desc *tx_desc;
6221         dma_addr_t dma;
6222         __le32 cmd_type, olinfo_status;
6223         struct skb_frag_struct *frag;
6224         unsigned int f = 0;
6225         unsigned int data_len = skb->data_len;
6226         unsigned int size = skb_headlen(skb);
6227         u32 offset = 0;
6228         u32 paylen = skb->len - hdr_len;
6229         u16 i = tx_ring->next_to_use;
6230         u16 gso_segs;
6231
6232 #ifdef IXGBE_FCOE
6233         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6234                 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6235                         data_len -= sizeof(struct fcoe_crc_eof);
6236                 } else {
6237                         size -= sizeof(struct fcoe_crc_eof) - data_len;
6238                         data_len = 0;
6239                 }
6240         }
6241
6242 #endif
6243         dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6244         if (dma_mapping_error(dev, dma))
6245                 goto dma_error;
6246
6247         cmd_type = ixgbe_tx_cmd_type(tx_flags);
6248         olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6249
6250         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6251
6252         for (;;) {
6253                 while (size > IXGBE_MAX_DATA_PER_TXD) {
6254                         tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6255                         tx_desc->read.cmd_type_len =
6256                                 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6257                         tx_desc->read.olinfo_status = olinfo_status;
6258
6259                         offset += IXGBE_MAX_DATA_PER_TXD;
6260                         size -= IXGBE_MAX_DATA_PER_TXD;
6261
6262                         tx_desc++;
6263                         i++;
6264                         if (i == tx_ring->count) {
6265                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6266                                 i = 0;
6267                         }
6268                 }
6269
6270                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6271                 tx_buffer_info->length = offset + size;
6272                 tx_buffer_info->tx_flags = tx_flags;
6273                 tx_buffer_info->dma = dma;
6274
6275                 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6276                 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6277                 tx_desc->read.olinfo_status = olinfo_status;
6278
6279                 if (!data_len)
6280                         break;
6281
6282                 frag = &skb_shinfo(skb)->frags[f];
6283 #ifdef IXGBE_FCOE
6284                 size = min_t(unsigned int, data_len, frag->size);
6285 #else
6286                 size = frag->size;
6287 #endif
6288                 data_len -= size;
6289                 f++;
6290
6291                 offset = 0;
6292                 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6293
6294                 dma = dma_map_page(dev, frag->page, frag->page_offset,
6295                                    size, DMA_TO_DEVICE);
6296                 if (dma_mapping_error(dev, dma))
6297                         goto dma_error;
6298
6299                 tx_desc++;
6300                 i++;
6301                 if (i == tx_ring->count) {
6302                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6303                         i = 0;
6304                 }
6305         }
6306
6307         tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6308
6309         i++;
6310         if (i == tx_ring->count)
6311                 i = 0;
6312
6313         tx_ring->next_to_use = i;
6314
6315         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6316                 gso_segs = skb_shinfo(skb)->gso_segs;
6317 #ifdef IXGBE_FCOE
6318         /* adjust for FCoE Sequence Offload */
6319         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6320                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6321                                         skb_shinfo(skb)->gso_size);
6322 #endif /* IXGBE_FCOE */
6323         else
6324                 gso_segs = 1;
6325
6326         /* multiply data chunks by size of headers */
6327         tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6328         tx_buffer_info->gso_segs = gso_segs;
6329         tx_buffer_info->skb = skb;
6330
6331         /* set the timestamp */
6332         first->time_stamp = jiffies;
6333
6334         /*
6335          * Force memory writes to complete before letting h/w
6336          * know there are new descriptors to fetch.  (Only
6337          * applicable for weak-ordered memory model archs,
6338          * such as IA-64).
6339          */
6340         wmb();
6341
6342         /* set next_to_watch value indicating a packet is present */
6343         first->next_to_watch = tx_desc;
6344
6345         /* notify HW of packet */
6346         writel(i, tx_ring->tail);
6347
6348         return;
6349 dma_error:
6350         dev_err(dev, "TX DMA map failed\n");
6351
6352         /* clear dma mappings for failed tx_buffer_info map */
6353         for (;;) {
6354                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6355                 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6356                 if (tx_buffer_info == first)
6357                         break;
6358                 if (i == 0)
6359                         i = tx_ring->count;
6360                 i--;
6361         }
6362
6363         dev_kfree_skb_any(skb);
6364
6365         tx_ring->next_to_use = i;
6366 }
6367
6368 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6369                       u32 tx_flags, __be16 protocol)
6370 {
6371         struct ixgbe_q_vector *q_vector = ring->q_vector;
6372         union ixgbe_atr_hash_dword input = { .dword = 0 };
6373         union ixgbe_atr_hash_dword common = { .dword = 0 };
6374         union {
6375                 unsigned char *network;
6376                 struct iphdr *ipv4;
6377                 struct ipv6hdr *ipv6;
6378         } hdr;
6379         struct tcphdr *th;
6380         __be16 vlan_id;
6381
6382         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6383         if (!q_vector)
6384                 return;
6385
6386         /* do nothing if sampling is disabled */
6387         if (!ring->atr_sample_rate)
6388                 return;
6389
6390         ring->atr_count++;
6391
6392         /* snag network header to get L4 type and address */
6393         hdr.network = skb_network_header(skb);
6394
6395         /* Currently only IPv4/IPv6 with TCP is supported */
6396         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6397              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6398             (protocol != __constant_htons(ETH_P_IP) ||
6399              hdr.ipv4->protocol != IPPROTO_TCP))
6400                 return;
6401
6402         th = tcp_hdr(skb);
6403
6404         /* skip this packet since it is invalid or the socket is closing */
6405         if (!th || th->fin)
6406                 return;
6407
6408         /* sample on all syn packets or once every atr sample count */
6409         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6410                 return;
6411
6412         /* reset sample count */
6413         ring->atr_count = 0;
6414
6415         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6416
6417         /*
6418          * src and dst are inverted, think how the receiver sees them
6419          *
6420          * The input is broken into two sections, a non-compressed section
6421          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6422          * is XORed together and stored in the compressed dword.
6423          */
6424         input.formatted.vlan_id = vlan_id;
6425
6426         /*
6427          * since src port and flex bytes occupy the same word XOR them together
6428          * and write the value to source port portion of compressed dword
6429          */
6430         if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6431                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6432         else
6433                 common.port.src ^= th->dest ^ protocol;
6434         common.port.dst ^= th->source;
6435
6436         if (protocol == __constant_htons(ETH_P_IP)) {
6437                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6438                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6439         } else {
6440                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6441                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6442                              hdr.ipv6->saddr.s6_addr32[1] ^
6443                              hdr.ipv6->saddr.s6_addr32[2] ^
6444                              hdr.ipv6->saddr.s6_addr32[3] ^
6445                              hdr.ipv6->daddr.s6_addr32[0] ^
6446                              hdr.ipv6->daddr.s6_addr32[1] ^
6447                              hdr.ipv6->daddr.s6_addr32[2] ^
6448                              hdr.ipv6->daddr.s6_addr32[3];
6449         }
6450
6451         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6452         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6453                                               input, common, ring->queue_index);
6454 }
6455
6456 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6457 {
6458         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6459         /* Herbert's original patch had:
6460          *  smp_mb__after_netif_stop_queue();
6461          * but since that doesn't exist yet, just open code it. */
6462         smp_mb();
6463
6464         /* We need to check again in a case another CPU has just
6465          * made room available. */
6466         if (likely(ixgbe_desc_unused(tx_ring) < size))
6467                 return -EBUSY;
6468
6469         /* A reprieve! - use start_queue because it doesn't call schedule */
6470         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6471         ++tx_ring->tx_stats.restart_queue;
6472         return 0;
6473 }
6474
6475 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6476 {
6477         if (likely(ixgbe_desc_unused(tx_ring) >= size))
6478                 return 0;
6479         return __ixgbe_maybe_stop_tx(tx_ring, size);
6480 }
6481
6482 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6483 {
6484         struct ixgbe_adapter *adapter = netdev_priv(dev);
6485         int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6486                                                smp_processor_id();
6487 #ifdef IXGBE_FCOE
6488         __be16 protocol = vlan_get_protocol(skb);
6489
6490         if (((protocol == htons(ETH_P_FCOE)) ||
6491             (protocol == htons(ETH_P_FIP))) &&
6492             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6493                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6494                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6495                 return txq;
6496         }
6497 #endif
6498
6499         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6500                 while (unlikely(txq >= dev->real_num_tx_queues))
6501                         txq -= dev->real_num_tx_queues;
6502                 return txq;
6503         }
6504
6505         return skb_tx_hash(dev, skb);
6506 }
6507
6508 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6509                           struct ixgbe_adapter *adapter,
6510                           struct ixgbe_ring *tx_ring)
6511 {
6512         struct ixgbe_tx_buffer *first;
6513         int tso;
6514         u32 tx_flags = 0;
6515 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6516         unsigned short f;
6517 #endif
6518         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6519         __be16 protocol = skb->protocol;
6520         u8 hdr_len = 0;
6521
6522         /*
6523          * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6524          *       + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6525          *       + 2 desc gap to keep tail from touching head,
6526          *       + 1 desc for context descriptor,
6527          * otherwise try next time
6528          */
6529 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6530         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6531                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6532 #else
6533         count += skb_shinfo(skb)->nr_frags;
6534 #endif
6535         if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6536                 tx_ring->tx_stats.tx_busy++;
6537                 return NETDEV_TX_BUSY;
6538         }
6539
6540 #ifdef CONFIG_PCI_IOV
6541         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6542                 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6543
6544 #endif
6545         /* if we have a HW VLAN tag being added default to the HW one */
6546         if (vlan_tx_tag_present(skb)) {
6547                 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6548                 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6549         /* else if it is a SW VLAN check the next protocol and store the tag */
6550         } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6551                 struct vlan_hdr *vhdr, _vhdr;
6552                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6553                 if (!vhdr)
6554                         goto out_drop;
6555
6556                 protocol = vhdr->h_vlan_encapsulated_proto;
6557                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6558                 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6559         }
6560
6561         if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6562             ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6563              (skb->priority != TC_PRIO_CONTROL))) {
6564                 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6565                 tx_flags |= tx_ring->dcb_tc <<
6566                             IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6567                 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6568                         struct vlan_ethhdr *vhdr;
6569                         if (skb_header_cloned(skb) &&
6570                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6571                                 goto out_drop;
6572                         vhdr = (struct vlan_ethhdr *)skb->data;
6573                         vhdr->h_vlan_TCI = htons(tx_flags >>
6574                                                  IXGBE_TX_FLAGS_VLAN_SHIFT);
6575                 } else {
6576                         tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6577                 }
6578         }
6579
6580         /* record the location of the first descriptor for this packet */
6581         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6582
6583 #ifdef IXGBE_FCOE
6584         /* setup tx offload for FCoE */
6585         if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6586             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6587                 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6588                 if (tso < 0)
6589                         goto out_drop;
6590                 else if (tso)
6591                         tx_flags |= IXGBE_TX_FLAGS_FSO |
6592                                     IXGBE_TX_FLAGS_FCOE;
6593                 else
6594                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6595
6596                 goto xmit_fcoe;
6597         }
6598
6599 #endif /* IXGBE_FCOE */
6600         /* setup IPv4/IPv6 offloads */
6601         if (protocol == __constant_htons(ETH_P_IP))
6602                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6603
6604         tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6605         if (tso < 0)
6606                 goto out_drop;
6607         else if (tso)
6608                 tx_flags |= IXGBE_TX_FLAGS_TSO;
6609         else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6610                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6611
6612         /* add the ATR filter if ATR is on */
6613         if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6614                 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6615
6616 #ifdef IXGBE_FCOE
6617 xmit_fcoe:
6618 #endif /* IXGBE_FCOE */
6619         ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6620
6621         ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6622
6623         return NETDEV_TX_OK;
6624
6625 out_drop:
6626         dev_kfree_skb_any(skb);
6627         return NETDEV_TX_OK;
6628 }
6629
6630 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6631 {
6632         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6633         struct ixgbe_ring *tx_ring;
6634
6635         tx_ring = adapter->tx_ring[skb->queue_mapping];
6636         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6637 }
6638
6639 /**
6640  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6641  * @netdev: network interface device structure
6642  * @p: pointer to an address structure
6643  *
6644  * Returns 0 on success, negative on failure
6645  **/
6646 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6647 {
6648         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6649         struct ixgbe_hw *hw = &adapter->hw;
6650         struct sockaddr *addr = p;
6651
6652         if (!is_valid_ether_addr(addr->sa_data))
6653                 return -EADDRNOTAVAIL;
6654
6655         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6656         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6657
6658         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6659                             IXGBE_RAH_AV);
6660
6661         return 0;
6662 }
6663
6664 static int
6665 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6666 {
6667         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6668         struct ixgbe_hw *hw = &adapter->hw;
6669         u16 value;
6670         int rc;
6671
6672         if (prtad != hw->phy.mdio.prtad)
6673                 return -EINVAL;
6674         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6675         if (!rc)
6676                 rc = value;
6677         return rc;
6678 }
6679
6680 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6681                             u16 addr, u16 value)
6682 {
6683         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6684         struct ixgbe_hw *hw = &adapter->hw;
6685
6686         if (prtad != hw->phy.mdio.prtad)
6687                 return -EINVAL;
6688         return hw->phy.ops.write_reg(hw, addr, devad, value);
6689 }
6690
6691 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6692 {
6693         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6694
6695         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6696 }
6697
6698 /**
6699  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6700  * netdev->dev_addrs
6701  * @netdev: network interface device structure
6702  *
6703  * Returns non-zero on failure
6704  **/
6705 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6706 {
6707         int err = 0;
6708         struct ixgbe_adapter *adapter = netdev_priv(dev);
6709         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6710
6711         if (is_valid_ether_addr(mac->san_addr)) {
6712                 rtnl_lock();
6713                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6714                 rtnl_unlock();
6715         }
6716         return err;
6717 }
6718
6719 /**
6720  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6721  * netdev->dev_addrs
6722  * @netdev: network interface device structure
6723  *
6724  * Returns non-zero on failure
6725  **/
6726 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6727 {
6728         int err = 0;
6729         struct ixgbe_adapter *adapter = netdev_priv(dev);
6730         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6731
6732         if (is_valid_ether_addr(mac->san_addr)) {
6733                 rtnl_lock();
6734                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6735                 rtnl_unlock();
6736         }
6737         return err;
6738 }
6739
6740 #ifdef CONFIG_NET_POLL_CONTROLLER
6741 /*
6742  * Polling 'interrupt' - used by things like netconsole to send skbs
6743  * without having to re-enable interrupts. It's not called while
6744  * the interrupt routine is executing.
6745  */
6746 static void ixgbe_netpoll(struct net_device *netdev)
6747 {
6748         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6749         int i;
6750
6751         /* if interface is down do nothing */
6752         if (test_bit(__IXGBE_DOWN, &adapter->state))
6753                 return;
6754
6755         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6756         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6757                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6758                 for (i = 0; i < num_q_vectors; i++) {
6759                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6760                         ixgbe_msix_clean_rings(0, q_vector);
6761                 }
6762         } else {
6763                 ixgbe_intr(adapter->pdev->irq, netdev);
6764         }
6765         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6766 }
6767 #endif
6768
6769 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6770                                                    struct rtnl_link_stats64 *stats)
6771 {
6772         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6773         int i;
6774
6775         rcu_read_lock();
6776         for (i = 0; i < adapter->num_rx_queues; i++) {
6777                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6778                 u64 bytes, packets;
6779                 unsigned int start;
6780
6781                 if (ring) {
6782                         do {
6783                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6784                                 packets = ring->stats.packets;
6785                                 bytes   = ring->stats.bytes;
6786                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6787                         stats->rx_packets += packets;
6788                         stats->rx_bytes   += bytes;
6789                 }
6790         }
6791
6792         for (i = 0; i < adapter->num_tx_queues; i++) {
6793                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6794                 u64 bytes, packets;
6795                 unsigned int start;
6796
6797                 if (ring) {
6798                         do {
6799                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6800                                 packets = ring->stats.packets;
6801                                 bytes   = ring->stats.bytes;
6802                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6803                         stats->tx_packets += packets;
6804                         stats->tx_bytes   += bytes;
6805                 }
6806         }
6807         rcu_read_unlock();
6808         /* following stats updated by ixgbe_watchdog_task() */
6809         stats->multicast        = netdev->stats.multicast;
6810         stats->rx_errors        = netdev->stats.rx_errors;
6811         stats->rx_length_errors = netdev->stats.rx_length_errors;
6812         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6813         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6814         return stats;
6815 }
6816
6817 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6818  * #adapter: pointer to ixgbe_adapter
6819  * @tc: number of traffic classes currently enabled
6820  *
6821  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6822  * 802.1Q priority maps to a packet buffer that exists.
6823  */
6824 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6825 {
6826         struct ixgbe_hw *hw = &adapter->hw;
6827         u32 reg, rsave;
6828         int i;
6829
6830         /* 82598 have a static priority to TC mapping that can not
6831          * be changed so no validation is needed.
6832          */
6833         if (hw->mac.type == ixgbe_mac_82598EB)
6834                 return;
6835
6836         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6837         rsave = reg;
6838
6839         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6840                 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6841
6842                 /* If up2tc is out of bounds default to zero */
6843                 if (up2tc > tc)
6844                         reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6845         }
6846
6847         if (reg != rsave)
6848                 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6849
6850         return;
6851 }
6852
6853
6854 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6855  * classes.
6856  *
6857  * @netdev: net device to configure
6858  * @tc: number of traffic classes to enable
6859  */
6860 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6861 {
6862         struct ixgbe_adapter *adapter = netdev_priv(dev);
6863         struct ixgbe_hw *hw = &adapter->hw;
6864
6865         /* Multiple traffic classes requires multiple queues */
6866         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6867                 e_err(drv, "Enable failed, needs MSI-X\n");
6868                 return -EINVAL;
6869         }
6870
6871         /* Hardware supports up to 8 traffic classes */
6872         if (tc > MAX_TRAFFIC_CLASS ||
6873             (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
6874                 return -EINVAL;
6875
6876         /* Hardware has to reinitialize queues and interrupts to
6877          * match packet buffer alignment. Unfortunantly, the
6878          * hardware is not flexible enough to do this dynamically.
6879          */
6880         if (netif_running(dev))
6881                 ixgbe_close(dev);
6882         ixgbe_clear_interrupt_scheme(adapter);
6883
6884         if (tc) {
6885                 netdev_set_num_tc(dev, tc);
6886                 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6887
6888                 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6889                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6890
6891                 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6892                         adapter->hw.fc.requested_mode = ixgbe_fc_none;
6893         } else {
6894                 netdev_reset_tc(dev);
6895
6896                 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6897
6898                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6899                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6900
6901                 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6902                 adapter->dcb_cfg.pfc_mode_enable = false;
6903         }
6904
6905         ixgbe_init_interrupt_scheme(adapter);
6906         ixgbe_validate_rtr(adapter, tc);
6907         if (netif_running(dev))
6908                 ixgbe_open(dev);
6909
6910         return 0;
6911 }
6912
6913 void ixgbe_do_reset(struct net_device *netdev)
6914 {
6915         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6916
6917         if (netif_running(netdev))
6918                 ixgbe_reinit_locked(adapter);
6919         else
6920                 ixgbe_reset(adapter);
6921 }
6922
6923 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
6924 {
6925         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6926
6927 #ifdef CONFIG_DCB
6928         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6929                 data &= ~NETIF_F_HW_VLAN_RX;
6930 #endif
6931
6932         /* return error if RXHASH is being enabled when RSS is not supported */
6933         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6934                 data &= ~NETIF_F_RXHASH;
6935
6936         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6937         if (!(data & NETIF_F_RXCSUM))
6938                 data &= ~NETIF_F_LRO;
6939
6940         /* Turn off LRO if not RSC capable or invalid ITR settings */
6941         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
6942                 data &= ~NETIF_F_LRO;
6943         } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
6944                    (adapter->rx_itr_setting != 1 &&
6945                     adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
6946                 data &= ~NETIF_F_LRO;
6947                 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
6948         }
6949
6950         return data;
6951 }
6952
6953 static int ixgbe_set_features(struct net_device *netdev, u32 data)
6954 {
6955         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6956         bool need_reset = false;
6957
6958         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6959         if (!(data & NETIF_F_RXCSUM))
6960                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
6961         else
6962                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
6963
6964         /* Make sure RSC matches LRO, reset if change */
6965         if (!!(data & NETIF_F_LRO) !=
6966              !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6967                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
6968                 switch (adapter->hw.mac.type) {
6969                 case ixgbe_mac_X540:
6970                 case ixgbe_mac_82599EB:
6971                         need_reset = true;
6972                         break;
6973                 default:
6974                         break;
6975                 }
6976         }
6977
6978         /*
6979          * Check if Flow Director n-tuple support was enabled or disabled.  If
6980          * the state changed, we need to reset.
6981          */
6982         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6983                 /* turn off ATR, enable perfect filters and reset */
6984                 if (data & NETIF_F_NTUPLE) {
6985                         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6986                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6987                         need_reset = true;
6988                 }
6989         } else if (!(data & NETIF_F_NTUPLE)) {
6990                 /* turn off Flow Director, set ATR and reset */
6991                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6992                 if ((adapter->flags &  IXGBE_FLAG_RSS_ENABLED) &&
6993                     !(adapter->flags &  IXGBE_FLAG_DCB_ENABLED))
6994                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6995                 need_reset = true;
6996         }
6997
6998         if (need_reset)
6999                 ixgbe_do_reset(netdev);
7000
7001         return 0;
7002
7003 }
7004
7005 static const struct net_device_ops ixgbe_netdev_ops = {
7006         .ndo_open               = ixgbe_open,
7007         .ndo_stop               = ixgbe_close,
7008         .ndo_start_xmit         = ixgbe_xmit_frame,
7009         .ndo_select_queue       = ixgbe_select_queue,
7010         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7011         .ndo_validate_addr      = eth_validate_addr,
7012         .ndo_set_mac_address    = ixgbe_set_mac,
7013         .ndo_change_mtu         = ixgbe_change_mtu,
7014         .ndo_tx_timeout         = ixgbe_tx_timeout,
7015         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7016         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7017         .ndo_do_ioctl           = ixgbe_ioctl,
7018         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7019         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7020         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7021         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7022         .ndo_get_stats64        = ixgbe_get_stats64,
7023         .ndo_setup_tc           = ixgbe_setup_tc,
7024 #ifdef CONFIG_NET_POLL_CONTROLLER
7025         .ndo_poll_controller    = ixgbe_netpoll,
7026 #endif
7027 #ifdef IXGBE_FCOE
7028         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7029         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7030         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7031         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7032         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7033         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7034 #endif /* IXGBE_FCOE */
7035         .ndo_set_features = ixgbe_set_features,
7036         .ndo_fix_features = ixgbe_fix_features,
7037 };
7038
7039 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7040                            const struct ixgbe_info *ii)
7041 {
7042 #ifdef CONFIG_PCI_IOV
7043         struct ixgbe_hw *hw = &adapter->hw;
7044         int err;
7045         int num_vf_macvlans, i;
7046         struct vf_macvlans *mv_list;
7047
7048         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7049                 return;
7050
7051         /* The 82599 supports up to 64 VFs per physical function
7052          * but this implementation limits allocation to 63 so that
7053          * basic networking resources are still available to the
7054          * physical function
7055          */
7056         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7057         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7058         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7059         if (err) {
7060                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7061                 goto err_novfs;
7062         }
7063
7064         num_vf_macvlans = hw->mac.num_rar_entries -
7065                 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7066
7067         adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7068                                              sizeof(struct vf_macvlans),
7069                                              GFP_KERNEL);
7070         if (mv_list) {
7071                 /* Initialize list of VF macvlans */
7072                 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7073                 for (i = 0; i < num_vf_macvlans; i++) {
7074                         mv_list->vf = -1;
7075                         mv_list->free = true;
7076                         mv_list->rar_entry = hw->mac.num_rar_entries -
7077                                 (i + adapter->num_vfs + 1);
7078                         list_add(&mv_list->l, &adapter->vf_mvs.l);
7079                         mv_list++;
7080                 }
7081         }
7082
7083         /* If call to enable VFs succeeded then allocate memory
7084          * for per VF control structures.
7085          */
7086         adapter->vfinfo =
7087                 kcalloc(adapter->num_vfs,
7088                         sizeof(struct vf_data_storage), GFP_KERNEL);
7089         if (adapter->vfinfo) {
7090                 /* Now that we're sure SR-IOV is enabled
7091                  * and memory allocated set up the mailbox parameters
7092                  */
7093                 ixgbe_init_mbx_params_pf(hw);
7094                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7095                        sizeof(hw->mbx.ops));
7096
7097                 /* Disable RSC when in SR-IOV mode */
7098                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7099                                      IXGBE_FLAG2_RSC_ENABLED);
7100                 return;
7101         }
7102
7103         /* Oh oh */
7104         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7105               "SRIOV disabled\n");
7106         pci_disable_sriov(adapter->pdev);
7107
7108 err_novfs:
7109         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7110         adapter->num_vfs = 0;
7111 #endif /* CONFIG_PCI_IOV */
7112 }
7113
7114 /**
7115  * ixgbe_probe - Device Initialization Routine
7116  * @pdev: PCI device information struct
7117  * @ent: entry in ixgbe_pci_tbl
7118  *
7119  * Returns 0 on success, negative on failure
7120  *
7121  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7122  * The OS initialization, configuring of the adapter private structure,
7123  * and a hardware reset occur.
7124  **/
7125 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7126                                  const struct pci_device_id *ent)
7127 {
7128         struct net_device *netdev;
7129         struct ixgbe_adapter *adapter = NULL;
7130         struct ixgbe_hw *hw;
7131         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7132         static int cards_found;
7133         int i, err, pci_using_dac;
7134         u8 part_str[IXGBE_PBANUM_LENGTH];
7135         unsigned int indices = num_possible_cpus();
7136 #ifdef IXGBE_FCOE
7137         u16 device_caps;
7138 #endif
7139         u32 eec;
7140
7141         /* Catch broken hardware that put the wrong VF device ID in
7142          * the PCIe SR-IOV capability.
7143          */
7144         if (pdev->is_virtfn) {
7145                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7146                      pci_name(pdev), pdev->vendor, pdev->device);
7147                 return -EINVAL;
7148         }
7149
7150         err = pci_enable_device_mem(pdev);
7151         if (err)
7152                 return err;
7153
7154         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7155             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7156                 pci_using_dac = 1;
7157         } else {
7158                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7159                 if (err) {
7160                         err = dma_set_coherent_mask(&pdev->dev,
7161                                                     DMA_BIT_MASK(32));
7162                         if (err) {
7163                                 dev_err(&pdev->dev,
7164                                         "No usable DMA configuration, aborting\n");
7165                                 goto err_dma;
7166                         }
7167                 }
7168                 pci_using_dac = 0;
7169         }
7170
7171         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7172                                            IORESOURCE_MEM), ixgbe_driver_name);
7173         if (err) {
7174                 dev_err(&pdev->dev,
7175                         "pci_request_selected_regions failed 0x%x\n", err);
7176                 goto err_pci_reg;
7177         }
7178
7179         pci_enable_pcie_error_reporting(pdev);
7180
7181         pci_set_master(pdev);
7182         pci_save_state(pdev);
7183
7184 #ifdef CONFIG_IXGBE_DCB
7185         indices *= MAX_TRAFFIC_CLASS;
7186 #endif
7187
7188         if (ii->mac == ixgbe_mac_82598EB)
7189                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7190         else
7191                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7192
7193 #ifdef IXGBE_FCOE
7194         indices += min_t(unsigned int, num_possible_cpus(),
7195                          IXGBE_MAX_FCOE_INDICES);
7196 #endif
7197         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7198         if (!netdev) {
7199                 err = -ENOMEM;
7200                 goto err_alloc_etherdev;
7201         }
7202
7203         SET_NETDEV_DEV(netdev, &pdev->dev);
7204
7205         adapter = netdev_priv(netdev);
7206         pci_set_drvdata(pdev, adapter);
7207
7208         adapter->netdev = netdev;
7209         adapter->pdev = pdev;
7210         hw = &adapter->hw;
7211         hw->back = adapter;
7212         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7213
7214         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7215                               pci_resource_len(pdev, 0));
7216         if (!hw->hw_addr) {
7217                 err = -EIO;
7218                 goto err_ioremap;
7219         }
7220
7221         for (i = 1; i <= 5; i++) {
7222                 if (pci_resource_len(pdev, i) == 0)
7223                         continue;
7224         }
7225
7226         netdev->netdev_ops = &ixgbe_netdev_ops;
7227         ixgbe_set_ethtool_ops(netdev);
7228         netdev->watchdog_timeo = 5 * HZ;
7229         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7230
7231         adapter->bd_number = cards_found;
7232
7233         /* Setup hw api */
7234         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7235         hw->mac.type  = ii->mac;
7236
7237         /* EEPROM */
7238         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7239         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7240         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7241         if (!(eec & (1 << 8)))
7242                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7243
7244         /* PHY */
7245         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7246         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7247         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7248         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7249         hw->phy.mdio.mmds = 0;
7250         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7251         hw->phy.mdio.dev = netdev;
7252         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7253         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7254
7255         ii->get_invariants(hw);
7256
7257         /* setup the private structure */
7258         err = ixgbe_sw_init(adapter);
7259         if (err)
7260                 goto err_sw_init;
7261
7262         /* Make it possible the adapter to be woken up via WOL */
7263         switch (adapter->hw.mac.type) {
7264         case ixgbe_mac_82599EB:
7265         case ixgbe_mac_X540:
7266                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7267                 break;
7268         default:
7269                 break;
7270         }
7271
7272         /*
7273          * If there is a fan on this device and it has failed log the
7274          * failure.
7275          */
7276         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7277                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7278                 if (esdp & IXGBE_ESDP_SDP1)
7279                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7280         }
7281
7282         /* reset_hw fills in the perm_addr as well */
7283         hw->phy.reset_if_overtemp = true;
7284         err = hw->mac.ops.reset_hw(hw);
7285         hw->phy.reset_if_overtemp = false;
7286         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7287             hw->mac.type == ixgbe_mac_82598EB) {
7288                 err = 0;
7289         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7290                 e_dev_err("failed to load because an unsupported SFP+ "
7291                           "module type was detected.\n");
7292                 e_dev_err("Reload the driver after installing a supported "
7293                           "module.\n");
7294                 goto err_sw_init;
7295         } else if (err) {
7296                 e_dev_err("HW Init failed: %d\n", err);
7297                 goto err_sw_init;
7298         }
7299
7300         ixgbe_probe_vf(adapter, ii);
7301
7302         netdev->features = NETIF_F_SG |
7303                            NETIF_F_IP_CSUM |
7304                            NETIF_F_IPV6_CSUM |
7305                            NETIF_F_HW_VLAN_TX |
7306                            NETIF_F_HW_VLAN_RX |
7307                            NETIF_F_HW_VLAN_FILTER |
7308                            NETIF_F_TSO |
7309                            NETIF_F_TSO6 |
7310                            NETIF_F_RXHASH |
7311                            NETIF_F_RXCSUM;
7312
7313         netdev->hw_features = netdev->features;
7314
7315         switch (adapter->hw.mac.type) {
7316         case ixgbe_mac_82599EB:
7317         case ixgbe_mac_X540:
7318                 netdev->features |= NETIF_F_SCTP_CSUM;
7319                 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7320                                        NETIF_F_NTUPLE;
7321                 break;
7322         default:
7323                 break;
7324         }
7325
7326         netdev->vlan_features |= NETIF_F_TSO;
7327         netdev->vlan_features |= NETIF_F_TSO6;
7328         netdev->vlan_features |= NETIF_F_IP_CSUM;
7329         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7330         netdev->vlan_features |= NETIF_F_SG;
7331
7332         netdev->priv_flags |= IFF_UNICAST_FLT;
7333
7334         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7335                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7336                                     IXGBE_FLAG_DCB_ENABLED);
7337
7338 #ifdef CONFIG_IXGBE_DCB
7339         netdev->dcbnl_ops = &dcbnl_ops;
7340 #endif
7341
7342 #ifdef IXGBE_FCOE
7343         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7344                 if (hw->mac.ops.get_device_caps) {
7345                         hw->mac.ops.get_device_caps(hw, &device_caps);
7346                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7347                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7348                 }
7349         }
7350         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7351                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7352                 netdev->vlan_features |= NETIF_F_FSO;
7353                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7354         }
7355 #endif /* IXGBE_FCOE */
7356         if (pci_using_dac) {
7357                 netdev->features |= NETIF_F_HIGHDMA;
7358                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7359         }
7360
7361         if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7362                 netdev->hw_features |= NETIF_F_LRO;
7363         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7364                 netdev->features |= NETIF_F_LRO;
7365
7366         /* make sure the EEPROM is good */
7367         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7368                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7369                 err = -EIO;
7370                 goto err_eeprom;
7371         }
7372
7373         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7374         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7375
7376         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7377                 e_dev_err("invalid MAC address\n");
7378                 err = -EIO;
7379                 goto err_eeprom;
7380         }
7381
7382         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7383         if (hw->mac.ops.disable_tx_laser &&
7384             ((hw->phy.multispeed_fiber) ||
7385              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7386               (hw->mac.type == ixgbe_mac_82599EB))))
7387                 hw->mac.ops.disable_tx_laser(hw);
7388
7389         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7390                     (unsigned long) adapter);
7391
7392         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7393         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7394
7395         err = ixgbe_init_interrupt_scheme(adapter);
7396         if (err)
7397                 goto err_sw_init;
7398
7399         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7400                 netdev->hw_features &= ~NETIF_F_RXHASH;
7401                 netdev->features &= ~NETIF_F_RXHASH;
7402         }
7403
7404         switch (pdev->device) {
7405         case IXGBE_DEV_ID_82599_SFP:
7406                 /* Only this subdevice supports WOL */
7407                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7408                         adapter->wol = IXGBE_WUFC_MAG;
7409                 break;
7410         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7411                 /* All except this subdevice support WOL */
7412                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7413                         adapter->wol = IXGBE_WUFC_MAG;
7414                 break;
7415         case IXGBE_DEV_ID_82599_KX4:
7416                 adapter->wol = IXGBE_WUFC_MAG;
7417                 break;
7418         default:
7419                 adapter->wol = 0;
7420                 break;
7421         }
7422         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7423
7424         /* pick up the PCI bus settings for reporting later */
7425         hw->mac.ops.get_bus_info(hw);
7426
7427         /* print bus type/speed/width info */
7428         e_dev_info("(PCI Express:%s:%s) %pM\n",
7429                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7430                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7431                     "Unknown"),
7432                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7433                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7434                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7435                     "Unknown"),
7436                    netdev->dev_addr);
7437
7438         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7439         if (err)
7440                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7441         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7442                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7443                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7444                            part_str);
7445         else
7446                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7447                            hw->mac.type, hw->phy.type, part_str);
7448
7449         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7450                 e_dev_warn("PCI-Express bandwidth available for this card is "
7451                            "not sufficient for optimal performance.\n");
7452                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7453                            "is required.\n");
7454         }
7455
7456         /* save off EEPROM version number */
7457         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7458
7459         /* reset the hardware with the new settings */
7460         err = hw->mac.ops.start_hw(hw);
7461
7462         if (err == IXGBE_ERR_EEPROM_VERSION) {
7463                 /* We are running on a pre-production device, log a warning */
7464                 e_dev_warn("This device is a pre-production adapter/LOM. "
7465                            "Please be aware there may be issues associated "
7466                            "with your hardware.  If you are experiencing "
7467                            "problems please contact your Intel or hardware "
7468                            "representative who provided you with this "
7469                            "hardware.\n");
7470         }
7471         strcpy(netdev->name, "eth%d");
7472         err = register_netdev(netdev);
7473         if (err)
7474                 goto err_register;
7475
7476         /* carrier off reporting is important to ethtool even BEFORE open */
7477         netif_carrier_off(netdev);
7478
7479 #ifdef CONFIG_IXGBE_DCA
7480         if (dca_add_requester(&pdev->dev) == 0) {
7481                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7482                 ixgbe_setup_dca(adapter);
7483         }
7484 #endif
7485         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7486                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7487                 for (i = 0; i < adapter->num_vfs; i++)
7488                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7489         }
7490
7491         /* Inform firmware of driver version */
7492         if (hw->mac.ops.set_fw_drv_ver)
7493                 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7494                                            FW_CEM_UNUSED_VER);
7495
7496         /* add san mac addr to netdev */
7497         ixgbe_add_sanmac_netdev(netdev);
7498
7499         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7500         cards_found++;
7501         return 0;
7502
7503 err_register:
7504         ixgbe_release_hw_control(adapter);
7505         ixgbe_clear_interrupt_scheme(adapter);
7506 err_sw_init:
7507 err_eeprom:
7508         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7509                 ixgbe_disable_sriov(adapter);
7510         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7511         iounmap(hw->hw_addr);
7512 err_ioremap:
7513         free_netdev(netdev);
7514 err_alloc_etherdev:
7515         pci_release_selected_regions(pdev,
7516                                      pci_select_bars(pdev, IORESOURCE_MEM));
7517 err_pci_reg:
7518 err_dma:
7519         pci_disable_device(pdev);
7520         return err;
7521 }
7522
7523 /**
7524  * ixgbe_remove - Device Removal Routine
7525  * @pdev: PCI device information struct
7526  *
7527  * ixgbe_remove is called by the PCI subsystem to alert the driver
7528  * that it should release a PCI device.  The could be caused by a
7529  * Hot-Plug event, or because the driver is going to be removed from
7530  * memory.
7531  **/
7532 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7533 {
7534         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7535         struct net_device *netdev = adapter->netdev;
7536
7537         set_bit(__IXGBE_DOWN, &adapter->state);
7538         cancel_work_sync(&adapter->service_task);
7539
7540 #ifdef CONFIG_IXGBE_DCA
7541         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7542                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7543                 dca_remove_requester(&pdev->dev);
7544                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7545         }
7546
7547 #endif
7548 #ifdef IXGBE_FCOE
7549         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7550                 ixgbe_cleanup_fcoe(adapter);
7551
7552 #endif /* IXGBE_FCOE */
7553
7554         /* remove the added san mac */
7555         ixgbe_del_sanmac_netdev(netdev);
7556
7557         if (netdev->reg_state == NETREG_REGISTERED)
7558                 unregister_netdev(netdev);
7559
7560         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7561                 ixgbe_disable_sriov(adapter);
7562
7563         ixgbe_clear_interrupt_scheme(adapter);
7564
7565         ixgbe_release_hw_control(adapter);
7566
7567         iounmap(adapter->hw.hw_addr);
7568         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7569                                      IORESOURCE_MEM));
7570
7571         e_dev_info("complete\n");
7572
7573         free_netdev(netdev);
7574
7575         pci_disable_pcie_error_reporting(pdev);
7576
7577         pci_disable_device(pdev);
7578 }
7579
7580 /**
7581  * ixgbe_io_error_detected - called when PCI error is detected
7582  * @pdev: Pointer to PCI device
7583  * @state: The current pci connection state
7584  *
7585  * This function is called after a PCI bus error affecting
7586  * this device has been detected.
7587  */
7588 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7589                                                 pci_channel_state_t state)
7590 {
7591         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7592         struct net_device *netdev = adapter->netdev;
7593
7594         netif_device_detach(netdev);
7595
7596         if (state == pci_channel_io_perm_failure)
7597                 return PCI_ERS_RESULT_DISCONNECT;
7598
7599         if (netif_running(netdev))
7600                 ixgbe_down(adapter);
7601         pci_disable_device(pdev);
7602
7603         /* Request a slot reset. */
7604         return PCI_ERS_RESULT_NEED_RESET;
7605 }
7606
7607 /**
7608  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7609  * @pdev: Pointer to PCI device
7610  *
7611  * Restart the card from scratch, as if from a cold-boot.
7612  */
7613 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7614 {
7615         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7616         pci_ers_result_t result;
7617         int err;
7618
7619         if (pci_enable_device_mem(pdev)) {
7620                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7621                 result = PCI_ERS_RESULT_DISCONNECT;
7622         } else {
7623                 pci_set_master(pdev);
7624                 pci_restore_state(pdev);
7625                 pci_save_state(pdev);
7626
7627                 pci_wake_from_d3(pdev, false);
7628
7629                 ixgbe_reset(adapter);
7630                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7631                 result = PCI_ERS_RESULT_RECOVERED;
7632         }
7633
7634         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7635         if (err) {
7636                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7637                           "failed 0x%0x\n", err);
7638                 /* non-fatal, continue */
7639         }
7640
7641         return result;
7642 }
7643
7644 /**
7645  * ixgbe_io_resume - called when traffic can start flowing again.
7646  * @pdev: Pointer to PCI device
7647  *
7648  * This callback is called when the error recovery driver tells us that
7649  * its OK to resume normal operation.
7650  */
7651 static void ixgbe_io_resume(struct pci_dev *pdev)
7652 {
7653         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7654         struct net_device *netdev = adapter->netdev;
7655
7656         if (netif_running(netdev)) {
7657                 if (ixgbe_up(adapter)) {
7658                         e_info(probe, "ixgbe_up failed after reset\n");
7659                         return;
7660                 }
7661         }
7662
7663         netif_device_attach(netdev);
7664 }
7665
7666 static struct pci_error_handlers ixgbe_err_handler = {
7667         .error_detected = ixgbe_io_error_detected,
7668         .slot_reset = ixgbe_io_slot_reset,
7669         .resume = ixgbe_io_resume,
7670 };
7671
7672 static struct pci_driver ixgbe_driver = {
7673         .name     = ixgbe_driver_name,
7674         .id_table = ixgbe_pci_tbl,
7675         .probe    = ixgbe_probe,
7676         .remove   = __devexit_p(ixgbe_remove),
7677 #ifdef CONFIG_PM
7678         .suspend  = ixgbe_suspend,
7679         .resume   = ixgbe_resume,
7680 #endif
7681         .shutdown = ixgbe_shutdown,
7682         .err_handler = &ixgbe_err_handler
7683 };
7684
7685 /**
7686  * ixgbe_init_module - Driver Registration Routine
7687  *
7688  * ixgbe_init_module is the first routine called when the driver is
7689  * loaded. All it does is register with the PCI subsystem.
7690  **/
7691 static int __init ixgbe_init_module(void)
7692 {
7693         int ret;
7694         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7695         pr_info("%s\n", ixgbe_copyright);
7696
7697 #ifdef CONFIG_IXGBE_DCA
7698         dca_register_notify(&dca_notifier);
7699 #endif
7700
7701         ret = pci_register_driver(&ixgbe_driver);
7702         return ret;
7703 }
7704
7705 module_init(ixgbe_init_module);
7706
7707 /**
7708  * ixgbe_exit_module - Driver Exit Cleanup Routine
7709  *
7710  * ixgbe_exit_module is called just before the driver is removed
7711  * from memory.
7712  **/
7713 static void __exit ixgbe_exit_module(void)
7714 {
7715 #ifdef CONFIG_IXGBE_DCA
7716         dca_unregister_notify(&dca_notifier);
7717 #endif
7718         pci_unregister_driver(&ixgbe_driver);
7719         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7720 }
7721
7722 #ifdef CONFIG_IXGBE_DCA
7723 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7724                             void *p)
7725 {
7726         int ret_val;
7727
7728         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7729                                          __ixgbe_notify_dca);
7730
7731         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7732 }
7733
7734 #endif /* CONFIG_IXGBE_DCA */
7735
7736 module_exit(ixgbe_exit_module);
7737
7738 /* ixgbe_main.c */