drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/sctp.h>
  39 #include <linux/pkt_sched.h>
  40 #include <linux/ipv6.h>
  41 #include <linux/slab.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <linux/ethtool.h>
  45 #include <linux/if.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/prefetch.h>
  48 #include <scsi/fc/fc_fcoe.h>
  49
  50 #include "ixgbe.h"
  51 #include "ixgbe_common.h"
  52 #include "ixgbe_dcb_82599.h"
  53 #include "ixgbe_sriov.h"
  54
  55 char ixgbe_driver_name[] = "ixgbe";
  56 static const char ixgbe_driver_string[] =
  57                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  58 #define MAJ 3
  59 #define MIN 4
  60 #define BUILD 8
  61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  62         __stringify(BUILD) "-k"
  63 const char ixgbe_driver_version[] = DRV_VERSION;
  64 static const char ixgbe_copyright[] =
  65                                 "Copyright (c) 1999-2011 Intel Corporation.";
  66
  67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  68         [board_82598] = &ixgbe_82598_info,
  69         [board_82599] = &ixgbe_82599_info,
  70         [board_X540] = &ixgbe_X540_info,
  71 };
  72
  73 /* ixgbe_pci_tbl - PCI Device ID Table
  74  *
  75  * Wildcard entries (PCI_ANY_ID) should come last
  76  * Last entry must be all 0s
  77  *
  78  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  79  *   Class, Class Mask, private data (not used) }
  80  */
  81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  95          board_82598 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  97          board_82598 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  99          board_82598 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
 101          board_82598 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
 103          board_82598 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
 105          board_82598 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
 107          board_82599 },
 108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 109          board_82599 },
 110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 111          board_82599 },
 112         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 113          board_82599 },
 114         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 115          board_82599 },
 116         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 117          board_82599 },
 118         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 119          board_82599 },
 120         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 121          board_82599 },
 122         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 123          board_82599 },
 124         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 125          board_82599 },
 126         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 127          board_82599 },
 128         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 129          board_X540 },
 130         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
 131          board_82599 },
 132         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
 133          board_82599 },
 134
 135         /* required last entry */
 136         {0, }
 137 };
 138 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 139
 140 #ifdef CONFIG_IXGBE_DCA
 141 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 142                             void *p);
 143 static struct notifier_block dca_notifier = {
 144         .notifier_call = ixgbe_notify_dca,
 145         .next          = NULL,
 146         .priority      = 0
 147 };
 148 #endif
 149
 150 #ifdef CONFIG_PCI_IOV
 151 static unsigned int max_vfs;
 152 module_param(max_vfs, uint, 0);
 153 MODULE_PARM_DESC(max_vfs,
 154                  "Maximum number of virtual functions to allocate per physical function");
 155 #endif /* CONFIG_PCI_IOV */
 156
 157 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 158 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_VERSION);
 161
 162 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 163
 164 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 165 {
 166         struct ixgbe_hw *hw = &adapter->hw;
 167         u32 gcr;
 168         u32 gpie;
 169         u32 vmdctl;
 170
 171 #ifdef CONFIG_PCI_IOV
 172         /* disable iov and allow time for transactions to clear */
 173         pci_disable_sriov(adapter->pdev);
 174 #endif
 175
 176         /* turn off device IOV mode */
 177         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 178         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 179         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 180         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 181         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 182         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 183
 184         /* set default pool back to 0 */
 185         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 186         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 187         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 188         IXGBE_WRITE_FLUSH(hw);
 189
 190         /* take a breather then clean up driver data */
 191         msleep(100);
 192
 193         kfree(adapter->vfinfo);
 194         adapter->vfinfo = NULL;
 195
 196         adapter->num_vfs = 0;
 197         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 198 }
 199
 200 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 201 {
 202         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 203             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 204                 schedule_work(&adapter->service_task);
 205 }
 206
 207 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 208 {
 209         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 210
 211         /* flush memory to make sure state is correct before next watchog */
 212         smp_mb__before_clear_bit();
 213         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 214 }
 215
 216 struct ixgbe_reg_info {
 217         u32 ofs;
 218         char *name;
 219 };
 220
 221 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 222
 223         /* General Registers */
 224         {IXGBE_CTRL, "CTRL"},
 225         {IXGBE_STATUS, "STATUS"},
 226         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 227
 228         /* Interrupt Registers */
 229         {IXGBE_EICR, "EICR"},
 230
 231         /* RX Registers */
 232         {IXGBE_SRRCTL(0), "SRRCTL"},
 233         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 234         {IXGBE_RDLEN(0), "RDLEN"},
 235         {IXGBE_RDH(0), "RDH"},
 236         {IXGBE_RDT(0), "RDT"},
 237         {IXGBE_RXDCTL(0), "RXDCTL"},
 238         {IXGBE_RDBAL(0), "RDBAL"},
 239         {IXGBE_RDBAH(0), "RDBAH"},
 240
 241         /* TX Registers */
 242         {IXGBE_TDBAL(0), "TDBAL"},
 243         {IXGBE_TDBAH(0), "TDBAH"},
 244         {IXGBE_TDLEN(0), "TDLEN"},
 245         {IXGBE_TDH(0), "TDH"},
 246         {IXGBE_TDT(0), "TDT"},
 247         {IXGBE_TXDCTL(0), "TXDCTL"},
 248
 249         /* List Terminator */
 250         {}
 251 };
 252
 253
 254 /*
 255  * ixgbe_regdump - register printout routine
 256  */
 257 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 258 {
 259         int i = 0, j = 0;
 260         char rname[16];
 261         u32 regs[64];
 262
 263         switch (reginfo->ofs) {
 264         case IXGBE_SRRCTL(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 267                 break;
 268         case IXGBE_DCA_RXCTRL(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 271                 break;
 272         case IXGBE_RDLEN(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 275                 break;
 276         case IXGBE_RDH(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 279                 break;
 280         case IXGBE_RDT(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 283                 break;
 284         case IXGBE_RXDCTL(0):
 285                 for (i = 0; i < 64; i++)
 286                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 287                 break;
 288         case IXGBE_RDBAL(0):
 289                 for (i = 0; i < 64; i++)
 290                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 291                 break;
 292         case IXGBE_RDBAH(0):
 293                 for (i = 0; i < 64; i++)
 294                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 295                 break;
 296         case IXGBE_TDBAL(0):
 297                 for (i = 0; i < 64; i++)
 298                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 299                 break;
 300         case IXGBE_TDBAH(0):
 301                 for (i = 0; i < 64; i++)
 302                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 303                 break;
 304         case IXGBE_TDLEN(0):
 305                 for (i = 0; i < 64; i++)
 306                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 307                 break;
 308         case IXGBE_TDH(0):
 309                 for (i = 0; i < 64; i++)
 310                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 311                 break;
 312         case IXGBE_TDT(0):
 313                 for (i = 0; i < 64; i++)
 314                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 315                 break;
 316         case IXGBE_TXDCTL(0):
 317                 for (i = 0; i < 64; i++)
 318                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 319                 break;
 320         default:
 321                 pr_info("%-15s %08x\n", reginfo->name,
 322                         IXGBE_READ_REG(hw, reginfo->ofs));
 323                 return;
 324         }
 325
 326         for (i = 0; i < 8; i++) {
 327                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 328                 pr_err("%-15s", rname);
 329                 for (j = 0; j < 8; j++)
 330                         pr_cont(" %08x", regs[i*8+j]);
 331                 pr_cont("\n");
 332         }
 333
 334 }
 335
 336 /*
 337  * ixgbe_dump - Print registers, tx-rings and rx-rings
 338  */
 339 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 340 {
 341         struct net_device *netdev = adapter->netdev;
 342         struct ixgbe_hw *hw = &adapter->hw;
 343         struct ixgbe_reg_info *reginfo;
 344         int n = 0;
 345         struct ixgbe_ring *tx_ring;
 346         struct ixgbe_tx_buffer *tx_buffer_info;
 347         union ixgbe_adv_tx_desc *tx_desc;
 348         struct my_u0 { u64 a; u64 b; } *u0;
 349         struct ixgbe_ring *rx_ring;
 350         union ixgbe_adv_rx_desc *rx_desc;
 351         struct ixgbe_rx_buffer *rx_buffer_info;
 352         u32 staterr;
 353         int i = 0;
 354
 355         if (!netif_msg_hw(adapter))
 356                 return;
 357
 358         /* Print netdevice Info */
 359         if (netdev) {
 360                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 361                 pr_info("Device Name     state            "
 362                         "trans_start      last_rx\n");
 363                 pr_info("%-15s %016lX %016lX %016lX\n",
 364                         netdev->name,
 365                         netdev->state,
 366                         netdev->trans_start,
 367                         netdev->last_rx);
 368         }
 369
 370         /* Print Registers */
 371         dev_info(&adapter->pdev->dev, "Register Dump\n");
 372         pr_info(" Register Name   Value\n");
 373         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 374              reginfo->name; reginfo++) {
 375                 ixgbe_regdump(hw, reginfo);
 376         }
 377
 378         /* Print TX Ring Summary */
 379         if (!netdev || !netif_running(netdev))
 380                 goto exit;
 381
 382         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 383         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 384         for (n = 0; n < adapter->num_tx_queues; n++) {
 385                 tx_ring = adapter->tx_ring[n];
 386                 tx_buffer_info =
 387                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 388                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 389                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 390                            (u64)tx_buffer_info->dma,
 391                            tx_buffer_info->length,
 392                            tx_buffer_info->next_to_watch,
 393                            (u64)tx_buffer_info->time_stamp);
 394         }
 395
 396         /* Print TX Rings */
 397         if (!netif_msg_tx_done(adapter))
 398                 goto rx_ring_summary;
 399
 400         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 401
 402         /* Transmit Descriptor Formats
 403          *
 404          * Advanced Transmit Descriptor
 405          *   +--------------------------------------------------------------+
 406          * 0 |         Buffer Address [63:0]                                |
 407          *   +--------------------------------------------------------------+
 408          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 409          *   +--------------------------------------------------------------+
 410          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 411          */
 412
 413         for (n = 0; n < adapter->num_tx_queues; n++) {
 414                 tx_ring = adapter->tx_ring[n];
 415                 pr_info("------------------------------------\n");
 416                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 417                 pr_info("------------------------------------\n");
 418                 pr_info("T [desc]     [address 63:0  ] "
 419                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 420                         "leng  ntw timestamp        bi->skb\n");
 421
 422                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 423                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 424                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 425                         u0 = (struct my_u0 *)tx_desc;
 426                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 427                                 " %04X  %3X %016llX %p", i,
 428                                 le64_to_cpu(u0->a),
 429                                 le64_to_cpu(u0->b),
 430                                 (u64)tx_buffer_info->dma,
 431                                 tx_buffer_info->length,
 432                                 tx_buffer_info->next_to_watch,
 433                                 (u64)tx_buffer_info->time_stamp,
 434                                 tx_buffer_info->skb);
 435                         if (i == tx_ring->next_to_use &&
 436                                 i == tx_ring->next_to_clean)
 437                                 pr_cont(" NTC/U\n");
 438                         else if (i == tx_ring->next_to_use)
 439                                 pr_cont(" NTU\n");
 440                         else if (i == tx_ring->next_to_clean)
 441                                 pr_cont(" NTC\n");
 442                         else
 443                                 pr_cont("\n");
 444
 445                         if (netif_msg_pktdata(adapter) &&
 446                                 tx_buffer_info->dma != 0)
 447                                 print_hex_dump(KERN_INFO, "",
 448                                         DUMP_PREFIX_ADDRESS, 16, 1,
 449                                         phys_to_virt(tx_buffer_info->dma),
 450                                         tx_buffer_info->length, true);
 451                 }
 452         }
 453
 454         /* Print RX Rings Summary */
 455 rx_ring_summary:
 456         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 457         pr_info("Queue [NTU] [NTC]\n");
 458         for (n = 0; n < adapter->num_rx_queues; n++) {
 459                 rx_ring = adapter->rx_ring[n];
 460                 pr_info("%5d %5X %5X\n",
 461                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 462         }
 463
 464         /* Print RX Rings */
 465         if (!netif_msg_rx_status(adapter))
 466                 goto exit;
 467
 468         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 469
 470         /* Advanced Receive Descriptor (Read) Format
 471          *    63                                           1        0
 472          *    +-----------------------------------------------------+
 473          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 474          *    +----------------------------------------------+------+
 475          *  8 |       Header Buffer Address [63:1]           |  DD  |
 476          *    +-----------------------------------------------------+
 477          *
 478          *
 479          * Advanced Receive Descriptor (Write-Back) Format
 480          *
 481          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 482          *   +------------------------------------------------------+
 483          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 484          *   | Checksum   Ident  |   |           |    | Type | Type |
 485          *   +------------------------------------------------------+
 486          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 487          *   +------------------------------------------------------+
 488          *   63       48 47    32 31            20 19               0
 489          */
 490         for (n = 0; n < adapter->num_rx_queues; n++) {
 491                 rx_ring = adapter->rx_ring[n];
 492                 pr_info("------------------------------------\n");
 493                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 494                 pr_info("------------------------------------\n");
 495                 pr_info("R  [desc]      [ PktBuf     A0] "
 496                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 497                         "<-- Adv Rx Read format\n");
 498                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 499                         "[vl er S cks ln] ---------------- [bi->skb] "
 500                         "<-- Adv Rx Write-Back format\n");
 501
 502                 for (i = 0; i < rx_ring->count; i++) {
 503                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 504                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 505                         u0 = (struct my_u0 *)rx_desc;
 506                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 507                         if (staterr & IXGBE_RXD_STAT_DD) {
 508                                 /* Descriptor Done */
 509                                 pr_info("RWB[0x%03X]     %016llX "
 510                                         "%016llX ---------------- %p", i,
 511                                         le64_to_cpu(u0->a),
 512                                         le64_to_cpu(u0->b),
 513                                         rx_buffer_info->skb);
 514                         } else {
 515                                 pr_info("R  [0x%03X]     %016llX "
 516                                         "%016llX %016llX %p", i,
 517                                         le64_to_cpu(u0->a),
 518                                         le64_to_cpu(u0->b),
 519                                         (u64)rx_buffer_info->dma,
 520                                         rx_buffer_info->skb);
 521
 522                                 if (netif_msg_pktdata(adapter)) {
 523                                         print_hex_dump(KERN_INFO, "",
 524                                            DUMP_PREFIX_ADDRESS, 16, 1,
 525                                            phys_to_virt(rx_buffer_info->dma),
 526                                            rx_ring->rx_buf_len, true);
 527
 528                                         if (rx_ring->rx_buf_len
 529                                                 < IXGBE_RXBUFFER_2048)
 530                                                 print_hex_dump(KERN_INFO, "",
 531                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 532                                                   phys_to_virt(
 533                                                     rx_buffer_info->page_dma +
 534                                                     rx_buffer_info->page_offset
 535                                                   ),
 536                                                   PAGE_SIZE/2, true);
 537                                 }
 538                         }
 539
 540                         if (i == rx_ring->next_to_use)
 541                                 pr_cont(" NTU\n");
 542                         else if (i == rx_ring->next_to_clean)
 543                                 pr_cont(" NTC\n");
 544                         else
 545                                 pr_cont("\n");
 546
 547                 }
 548         }
 549
 550 exit:
 551         return;
 552 }
 553
 554 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 555 {
 556         u32 ctrl_ext;
 557
 558         /* Let firmware take over control of h/w */
 559         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 560         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 561                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 562 }
 563
 564 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 565 {
 566         u32 ctrl_ext;
 567
 568         /* Let firmware know the driver has taken over */
 569         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 570         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 571                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 572 }
 573
 574 /*
 575  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 576  * @adapter: pointer to adapter struct
 577  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 578  * @queue: queue to map the corresponding interrupt to
 579  * @msix_vector: the vector to map to the corresponding queue
 580  *
 581  */
 582 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 583                            u8 queue, u8 msix_vector)
 584 {
 585         u32 ivar, index;
 586         struct ixgbe_hw *hw = &adapter->hw;
 587         switch (hw->mac.type) {
 588         case ixgbe_mac_82598EB:
 589                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 590                 if (direction == -1)
 591                         direction = 0;
 592                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 593                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 594                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 595                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 596                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 597                 break;
 598         case ixgbe_mac_82599EB:
 599         case ixgbe_mac_X540:
 600                 if (direction == -1) {
 601                         /* other causes */
 602                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 603                         index = ((queue & 1) * 8);
 604                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 605                         ivar &= ~(0xFF << index);
 606                         ivar |= (msix_vector << index);
 607                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 608                         break;
 609                 } else {
 610                         /* tx or rx causes */
 611                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 612                         index = ((16 * (queue & 1)) + (8 * direction));
 613                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 614                         ivar &= ~(0xFF << index);
 615                         ivar |= (msix_vector << index);
 616                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 617                         break;
 618                 }
 619         default:
 620                 break;
 621         }
 622 }
 623
 624 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 625                                           u64 qmask)
 626 {
 627         u32 mask;
 628
 629         switch (adapter->hw.mac.type) {
 630         case ixgbe_mac_82598EB:
 631                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 632                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 633                 break;
 634         case ixgbe_mac_82599EB:
 635         case ixgbe_mac_X540:
 636                 mask = (qmask & 0xFFFFFFFF);
 637                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 638                 mask = (qmask >> 32);
 639                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 640                 break;
 641         default:
 642                 break;
 643         }
 644 }
 645
 646 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 647                                       struct ixgbe_tx_buffer *tx_buffer_info)
 648 {
 649         if (tx_buffer_info->dma) {
 650                 if (tx_buffer_info->mapped_as_page)
 651                         dma_unmap_page(tx_ring->dev,
 652                                        tx_buffer_info->dma,
 653                                        tx_buffer_info->length,
 654                                        DMA_TO_DEVICE);
 655                 else
 656                         dma_unmap_single(tx_ring->dev,
 657                                          tx_buffer_info->dma,
 658                                          tx_buffer_info->length,
 659                                          DMA_TO_DEVICE);
 660                 tx_buffer_info->dma = 0;
 661         }
 662         if (tx_buffer_info->skb) {
 663                 dev_kfree_skb_any(tx_buffer_info->skb);
 664                 tx_buffer_info->skb = NULL;
 665         }
 666         tx_buffer_info->time_stamp = 0;
 667         /* tx_buffer_info must be completely set up in the transmit path */
 668 }
 669
 670 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 671 {
 672         struct ixgbe_hw *hw = &adapter->hw;
 673         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 674         u32 data = 0;
 675         u32 xoff[8] = {0};
 676         int i;
 677
 678         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 679             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 680                 switch (hw->mac.type) {
 681                 case ixgbe_mac_82598EB:
 682                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 683                         break;
 684                 default:
 685                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 686                 }
 687                 hwstats->lxoffrxc += data;
 688
 689                 /* refill credits (no tx hang) if we received xoff */
 690                 if (!data)
 691                         return;
 692
 693                 for (i = 0; i < adapter->num_tx_queues; i++)
 694                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 695                                   &adapter->tx_ring[i]->state);
 696                 return;
 697         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 698                 return;
 699
 700         /* update stats for each tc, only valid with PFC enabled */
 701         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 702                 switch (hw->mac.type) {
 703                 case ixgbe_mac_82598EB:
 704                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 705                         break;
 706                 default:
 707                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 708                 }
 709                 hwstats->pxoffrxc[i] += xoff[i];
 710         }
 711
 712         /* disarm tx queues that have received xoff frames */
 713         for (i = 0; i < adapter->num_tx_queues; i++) {
 714                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 715                 u8 tc = tx_ring->dcb_tc;
 716
 717                 if (xoff[tc])
 718                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 719         }
 720 }
 721
 722 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 723 {
 724         return ring->tx_stats.completed;
 725 }
 726
 727 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 728 {
 729         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 730         struct ixgbe_hw *hw = &adapter->hw;
 731
 732         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 733         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 734
 735         if (head != tail)
 736                 return (head < tail) ?
 737                         tail - head : (tail + ring->count - head);
 738
 739         return 0;
 740 }
 741
 742 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 743 {
 744         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 745         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 746         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 747         bool ret = false;
 748
 749         clear_check_for_tx_hang(tx_ring);
 750
 751         /*
 752          * Check for a hung queue, but be thorough. This verifies
 753          * that a transmit has been completed since the previous
 754          * check AND there is at least one packet pending. The
 755          * ARMED bit is set to indicate a potential hang. The
 756          * bit is cleared if a pause frame is received to remove
 757          * false hang detection due to PFC or 802.3x frames. By
 758          * requiring this to fail twice we avoid races with
 759          * pfc clearing the ARMED bit and conditions where we
 760          * run the check_tx_hang logic with a transmit completion
 761          * pending but without time to complete it yet.
 762          */
 763         if ((tx_done_old == tx_done) && tx_pending) {
 764                 /* make sure it is true for two checks in a row */
 765                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 766                                        &tx_ring->state);
 767         } else {
 768                 /* update completed stats and continue */
 769                 tx_ring->tx_stats.tx_done_old = tx_done;
 770                 /* reset the countdown */
 771                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 772         }
 773
 774         return ret;
 775 }
 776
 777 /**
 778  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 779  * @adapter: driver private struct
 780  **/
 781 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 782 {
 783
 784         /* Do the reset outside of interrupt context */
 785         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 786                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 787                 ixgbe_service_event_schedule(adapter);
 788         }
 789 }
 790
 791 /**
 792  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 793  * @q_vector: structure containing interrupt and ring information
 794  * @tx_ring: tx ring to clean
 795  **/
 796 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 797                                struct ixgbe_ring *tx_ring)
 798 {
 799         struct ixgbe_adapter *adapter = q_vector->adapter;
 800         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 801         struct ixgbe_tx_buffer *tx_buffer_info;
 802         unsigned int total_bytes = 0, total_packets = 0;
 803         u16 i, eop, count = 0;
 804
 805         i = tx_ring->next_to_clean;
 806         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 807         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 808
 809         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 810                (count < q_vector->tx.work_limit)) {
 811                 bool cleaned = false;
 812                 rmb(); /* read buffer_info after eop_desc */
 813                 for ( ; !cleaned; count++) {
 814                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 815                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 816
 817                         tx_desc->wb.status = 0;
 818                         cleaned = (i == eop);
 819
 820                         i++;
 821                         if (i == tx_ring->count)
 822                                 i = 0;
 823
 824                         if (cleaned && tx_buffer_info->skb) {
 825                                 total_bytes += tx_buffer_info->bytecount;
 826                                 total_packets += tx_buffer_info->gso_segs;
 827                         }
 828
 829                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 830                                                          tx_buffer_info);
 831                 }
 832
 833                 tx_ring->tx_stats.completed++;
 834                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 835                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 836         }
 837
 838         tx_ring->next_to_clean = i;
 839         tx_ring->stats.bytes += total_bytes;
 840         tx_ring->stats.packets += total_packets;
 841         u64_stats_update_begin(&tx_ring->syncp);
 842         q_vector->tx.total_bytes += total_bytes;
 843         q_vector->tx.total_packets += total_packets;
 844         u64_stats_update_end(&tx_ring->syncp);
 845
 846         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 847                 /* schedule immediate reset if we believe we hung */
 848                 struct ixgbe_hw *hw = &adapter->hw;
 849                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 850                 e_err(drv, "Detected Tx Unit Hang\n"
 851                         "  Tx Queue             <%d>\n"
 852                         "  TDH, TDT             <%x>, <%x>\n"
 853                         "  next_to_use          <%x>\n"
 854                         "  next_to_clean        <%x>\n"
 855                         "tx_buffer_info[next_to_clean]\n"
 856                         "  time_stamp           <%lx>\n"
 857                         "  jiffies              <%lx>\n",
 858                         tx_ring->queue_index,
 859                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 860                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 861                         tx_ring->next_to_use, eop,
 862                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 863
 864                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 865
 866                 e_info(probe,
 867                        "tx hang %d detected on queue %d, resetting adapter\n",
 868                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 869
 870                 /* schedule immediate reset if we believe we hung */
 871                 ixgbe_tx_timeout_reset(adapter);
 872
 873                 /* the adapter is about to reset, no point in enabling stuff */
 874                 return true;
 875         }
 876
 877 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 878         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 879                      (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
 880                 /* Make sure that anybody stopping the queue after this
 881                  * sees the new next_to_clean.
 882                  */
 883                 smp_mb();
 884                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 885                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 886                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 887                         ++tx_ring->tx_stats.restart_queue;
 888                 }
 889         }
 890
 891         return count < q_vector->tx.work_limit;
 892 }
 893
 894 #ifdef CONFIG_IXGBE_DCA
 895 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 896                                 struct ixgbe_ring *rx_ring,
 897                                 int cpu)
 898 {
 899         struct ixgbe_hw *hw = &adapter->hw;
 900         u32 rxctrl;
 901         u8 reg_idx = rx_ring->reg_idx;
 902
 903         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 904         switch (hw->mac.type) {
 905         case ixgbe_mac_82598EB:
 906                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 907                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 908                 break;
 909         case ixgbe_mac_82599EB:
 910         case ixgbe_mac_X540:
 911                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 912                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 913                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 914                 break;
 915         default:
 916                 break;
 917         }
 918         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 919         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 920         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 921         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 922 }
 923
 924 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 925                                 struct ixgbe_ring *tx_ring,
 926                                 int cpu)
 927 {
 928         struct ixgbe_hw *hw = &adapter->hw;
 929         u32 txctrl;
 930         u8 reg_idx = tx_ring->reg_idx;
 931
 932         switch (hw->mac.type) {
 933         case ixgbe_mac_82598EB:
 934                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 935                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 936                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 937                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 938                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 939                 break;
 940         case ixgbe_mac_82599EB:
 941         case ixgbe_mac_X540:
 942                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 943                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 944                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 945                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 946                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 947                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 948                 break;
 949         default:
 950                 break;
 951         }
 952 }
 953
 954 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 955 {
 956         struct ixgbe_adapter *adapter = q_vector->adapter;
 957         int cpu = get_cpu();
 958         long r_idx;
 959         int i;
 960
 961         if (q_vector->cpu == cpu)
 962                 goto out_no_update;
 963
 964         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
 965         for (i = 0; i < q_vector->tx.count; i++) {
 966                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 967                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
 968                                       r_idx + 1);
 969         }
 970
 971         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
 972         for (i = 0; i < q_vector->rx.count; i++) {
 973                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 974                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
 975                                       r_idx + 1);
 976         }
 977
 978         q_vector->cpu = cpu;
 979 out_no_update:
 980         put_cpu();
 981 }
 982
 983 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 984 {
 985         int num_q_vectors;
 986         int i;
 987
 988         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 989                 return;
 990
 991         /* always use CB2 mode, difference is masked in the CB driver */
 992         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 993
 994         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 995                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 996         else
 997                 num_q_vectors = 1;
 998
 999         for (i = 0; i < num_q_vectors; i++) {
1000                 adapter->q_vector[i]->cpu = -1;
1001                 ixgbe_update_dca(adapter->q_vector[i]);
1002         }
1003 }
1004
1005 static int __ixgbe_notify_dca(struct device *dev, void *data)
1006 {
1007         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1008         unsigned long event = *(unsigned long *)data;
1009
1010         if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1011                 return 0;
1012
1013         switch (event) {
1014         case DCA_PROVIDER_ADD:
1015                 /* if we're already enabled, don't do it again */
1016                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1017                         break;
1018                 if (dca_add_requester(dev) == 0) {
1019                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1020                         ixgbe_setup_dca(adapter);
1021                         break;
1022                 }
1023                 /* Fall Through since DCA is disabled. */
1024         case DCA_PROVIDER_REMOVE:
1025                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1026                         dca_remove_requester(dev);
1027                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1028                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1029                 }
1030                 break;
1031         }
1032
1033         return 0;
1034 }
1035 #endif /* CONFIG_IXGBE_DCA */
1036
1037 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1038                                  struct sk_buff *skb)
1039 {
1040         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1041 }
1042
1043 /**
1044  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1045  * @adapter: address of board private structure
1046  * @rx_desc: advanced rx descriptor
1047  *
1048  * Returns : true if it is FCoE pkt
1049  */
1050 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1051                                     union ixgbe_adv_rx_desc *rx_desc)
1052 {
1053         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1054
1055         return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1056                ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1057                 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1058                              IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1059 }
1060
1061 /**
1062  * ixgbe_receive_skb - Send a completed packet up the stack
1063  * @adapter: board private structure
1064  * @skb: packet to send up
1065  * @status: hardware indication of status of receive
1066  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1067  * @rx_desc: rx descriptor
1068  **/
1069 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1070                               struct sk_buff *skb, u8 status,
1071                               struct ixgbe_ring *ring,
1072                               union ixgbe_adv_rx_desc *rx_desc)
1073 {
1074         struct ixgbe_adapter *adapter = q_vector->adapter;
1075         struct napi_struct *napi = &q_vector->napi;
1076         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1077         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1078
1079         if (is_vlan && (tag & VLAN_VID_MASK))
1080                 __vlan_hwaccel_put_tag(skb, tag);
1081
1082         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1083                 napi_gro_receive(napi, skb);
1084         else
1085                 netif_rx(skb);
1086 }
1087
1088 /**
1089  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1090  * @adapter: address of board private structure
1091  * @status_err: hardware indication of status of receive
1092  * @skb: skb currently being received and modified
1093  * @status_err: status error value of last descriptor in packet
1094  **/
1095 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1096                                      union ixgbe_adv_rx_desc *rx_desc,
1097                                      struct sk_buff *skb,
1098                                      u32 status_err)
1099 {
1100         skb->ip_summed = CHECKSUM_NONE;
1101
1102         /* Rx csum disabled */
1103         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1104                 return;
1105
1106         /* if IP and error */
1107         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1108             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1109                 adapter->hw_csum_rx_error++;
1110                 return;
1111         }
1112
1113         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1114                 return;
1115
1116         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1117                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1118
1119                 /*
1120                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1121                  * checksum errors.
1122                  */
1123                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1124                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1125                         return;
1126
1127                 adapter->hw_csum_rx_error++;
1128                 return;
1129         }
1130
1131         /* It must be a TCP or UDP packet with a valid checksum */
1132         skb->ip_summed = CHECKSUM_UNNECESSARY;
1133 }
1134
1135 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1136 {
1137         /*
1138          * Force memory writes to complete before letting h/w
1139          * know there are new descriptors to fetch.  (Only
1140          * applicable for weak-ordered memory model archs,
1141          * such as IA-64).
1142          */
1143         wmb();
1144         writel(val, rx_ring->tail);
1145 }
1146
1147 /**
1148  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1149  * @rx_ring: ring to place buffers on
1150  * @cleaned_count: number of buffers to replace
1151  **/
1152 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1153 {
1154         union ixgbe_adv_rx_desc *rx_desc;
1155         struct ixgbe_rx_buffer *bi;
1156         struct sk_buff *skb;
1157         u16 i = rx_ring->next_to_use;
1158
1159         /* do nothing if no valid netdev defined */
1160         if (!rx_ring->netdev)
1161                 return;
1162
1163         while (cleaned_count--) {
1164                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1165                 bi = &rx_ring->rx_buffer_info[i];
1166                 skb = bi->skb;
1167
1168                 if (!skb) {
1169                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1170                                                         rx_ring->rx_buf_len);
1171                         if (!skb) {
1172                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1173                                 goto no_buffers;
1174                         }
1175                         /* initialize queue mapping */
1176                         skb_record_rx_queue(skb, rx_ring->queue_index);
1177                         bi->skb = skb;
1178                 }
1179
1180                 if (!bi->dma) {
1181                         bi->dma = dma_map_single(rx_ring->dev,
1182                                                  skb->data,
1183                                                  rx_ring->rx_buf_len,
1184                                                  DMA_FROM_DEVICE);
1185                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1186                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1187                                 bi->dma = 0;
1188                                 goto no_buffers;
1189                         }
1190                 }
1191
1192                 if (ring_is_ps_enabled(rx_ring)) {
1193                         if (!bi->page) {
1194                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1195                                 if (!bi->page) {
1196                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1197                                         goto no_buffers;
1198                                 }
1199                         }
1200
1201                         if (!bi->page_dma) {
1202                                 /* use a half page if we're re-using */
1203                                 bi->page_offset ^= PAGE_SIZE / 2;
1204                                 bi->page_dma = dma_map_page(rx_ring->dev,
1205                                                             bi->page,
1206                                                             bi->page_offset,
1207                                                             PAGE_SIZE / 2,
1208                                                             DMA_FROM_DEVICE);
1209                                 if (dma_mapping_error(rx_ring->dev,
1210                                                       bi->page_dma)) {
1211                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1212                                         bi->page_dma = 0;
1213                                         goto no_buffers;
1214                                 }
1215                         }
1216
1217                         /* Refresh the desc even if buffer_addrs didn't change
1218                          * because each write-back erases this info. */
1219                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1220                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1221                 } else {
1222                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1223                         rx_desc->read.hdr_addr = 0;
1224                 }
1225
1226                 i++;
1227                 if (i == rx_ring->count)
1228                         i = 0;
1229         }
1230
1231 no_buffers:
1232         if (rx_ring->next_to_use != i) {
1233                 rx_ring->next_to_use = i;
1234                 ixgbe_release_rx_desc(rx_ring, i);
1235         }
1236 }
1237
1238 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1239 {
1240         /* HW will not DMA in data larger than the given buffer, even if it
1241          * parses the (NFS, of course) header to be larger.  In that case, it
1242          * fills the header buffer and spills the rest into the page.
1243          */
1244         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1245         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1246                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1247         if (hlen > IXGBE_RX_HDR_SIZE)
1248                 hlen = IXGBE_RX_HDR_SIZE;
1249         return hlen;
1250 }
1251
1252 /**
1253  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1254  * @skb: pointer to the last skb in the rsc queue
1255  *
1256  * This function changes a queue full of hw rsc buffers into a completed
1257  * packet.  It uses the ->prev pointers to find the first packet and then
1258  * turns it into the frag list owner.
1259  **/
1260 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1261 {
1262         unsigned int frag_list_size = 0;
1263         unsigned int skb_cnt = 1;
1264
1265         while (skb->prev) {
1266                 struct sk_buff *prev = skb->prev;
1267                 frag_list_size += skb->len;
1268                 skb->prev = NULL;
1269                 skb = prev;
1270                 skb_cnt++;
1271         }
1272
1273         skb_shinfo(skb)->frag_list = skb->next;
1274         skb->next = NULL;
1275         skb->len += frag_list_size;
1276         skb->data_len += frag_list_size;
1277         skb->truesize += frag_list_size;
1278         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1279
1280         return skb;
1281 }
1282
1283 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1284 {
1285         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1286                 IXGBE_RXDADV_RSCCNT_MASK);
1287 }
1288
1289 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1290                                struct ixgbe_ring *rx_ring,
1291                                int *work_done, int work_to_do)
1292 {
1293         struct ixgbe_adapter *adapter = q_vector->adapter;
1294         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1295         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1296         struct sk_buff *skb;
1297         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1298         const int current_node = numa_node_id();
1299 #ifdef IXGBE_FCOE
1300         int ddp_bytes = 0;
1301 #endif /* IXGBE_FCOE */
1302         u32 staterr;
1303         u16 i;
1304         u16 cleaned_count = 0;
1305         bool pkt_is_rsc = false;
1306
1307         i = rx_ring->next_to_clean;
1308         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1309         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1310
1311         while (staterr & IXGBE_RXD_STAT_DD) {
1312                 u32 upper_len = 0;
1313
1314                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1315
1316                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1317
1318                 skb = rx_buffer_info->skb;
1319                 rx_buffer_info->skb = NULL;
1320                 prefetch(skb->data);
1321
1322                 if (ring_is_rsc_enabled(rx_ring))
1323                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1324
1325                 /* if this is a skb from previous receive DMA will be 0 */
1326                 if (rx_buffer_info->dma) {
1327                         u16 hlen;
1328                         if (pkt_is_rsc &&
1329                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1330                             !skb->prev) {
1331                                 /*
1332                                  * When HWRSC is enabled, delay unmapping
1333                                  * of the first packet. It carries the
1334                                  * header information, HW may still
1335                                  * access the header after the writeback.
1336                                  * Only unmap it when EOP is reached
1337                                  */
1338                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1339                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1340                         } else {
1341                                 dma_unmap_single(rx_ring->dev,
1342                                                  rx_buffer_info->dma,
1343                                                  rx_ring->rx_buf_len,
1344                                                  DMA_FROM_DEVICE);
1345                         }
1346                         rx_buffer_info->dma = 0;
1347
1348                         if (ring_is_ps_enabled(rx_ring)) {
1349                                 hlen = ixgbe_get_hlen(rx_desc);
1350                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1351                         } else {
1352                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1353                         }
1354
1355                         skb_put(skb, hlen);
1356                 } else {
1357                         /* assume packet split since header is unmapped */
1358                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1359                 }
1360
1361                 if (upper_len) {
1362                         dma_unmap_page(rx_ring->dev,
1363                                        rx_buffer_info->page_dma,
1364                                        PAGE_SIZE / 2,
1365                                        DMA_FROM_DEVICE);
1366                         rx_buffer_info->page_dma = 0;
1367                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1368                                            rx_buffer_info->page,
1369                                            rx_buffer_info->page_offset,
1370                                            upper_len);
1371
1372                         if ((page_count(rx_buffer_info->page) == 1) &&
1373                             (page_to_nid(rx_buffer_info->page) == current_node))
1374                                 get_page(rx_buffer_info->page);
1375                         else
1376                                 rx_buffer_info->page = NULL;
1377
1378                         skb->len += upper_len;
1379                         skb->data_len += upper_len;
1380                         skb->truesize += upper_len;
1381                 }
1382
1383                 i++;
1384                 if (i == rx_ring->count)
1385                         i = 0;
1386
1387                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1388                 prefetch(next_rxd);
1389                 cleaned_count++;
1390
1391                 if (pkt_is_rsc) {
1392                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1393                                      IXGBE_RXDADV_NEXTP_SHIFT;
1394                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1395                 } else {
1396                         next_buffer = &rx_ring->rx_buffer_info[i];
1397                 }
1398
1399                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1400                         if (ring_is_ps_enabled(rx_ring)) {
1401                                 rx_buffer_info->skb = next_buffer->skb;
1402                                 rx_buffer_info->dma = next_buffer->dma;
1403                                 next_buffer->skb = skb;
1404                                 next_buffer->dma = 0;
1405                         } else {
1406                                 skb->next = next_buffer->skb;
1407                                 skb->next->prev = skb;
1408                         }
1409                         rx_ring->rx_stats.non_eop_descs++;
1410                         goto next_desc;
1411                 }
1412
1413                 if (skb->prev) {
1414                         skb = ixgbe_transform_rsc_queue(skb);
1415                         /* if we got here without RSC the packet is invalid */
1416                         if (!pkt_is_rsc) {
1417                                 __pskb_trim(skb, 0);
1418                                 rx_buffer_info->skb = skb;
1419                                 goto next_desc;
1420                         }
1421                 }
1422
1423                 if (ring_is_rsc_enabled(rx_ring)) {
1424                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1425                                 dma_unmap_single(rx_ring->dev,
1426                                                  IXGBE_RSC_CB(skb)->dma,
1427                                                  rx_ring->rx_buf_len,
1428                                                  DMA_FROM_DEVICE);
1429                                 IXGBE_RSC_CB(skb)->dma = 0;
1430                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1431                         }
1432                 }
1433                 if (pkt_is_rsc) {
1434                         if (ring_is_ps_enabled(rx_ring))
1435                                 rx_ring->rx_stats.rsc_count +=
1436                                         skb_shinfo(skb)->nr_frags;
1437                         else
1438                                 rx_ring->rx_stats.rsc_count +=
1439                                         IXGBE_RSC_CB(skb)->skb_cnt;
1440                         rx_ring->rx_stats.rsc_flush++;
1441                 }
1442
1443                 /* ERR_MASK will only have valid bits if EOP set */
1444                 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1445                         dev_kfree_skb_any(skb);
1446                         goto next_desc;
1447                 }
1448
1449                 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1450                 if (adapter->netdev->features & NETIF_F_RXHASH)
1451                         ixgbe_rx_hash(rx_desc, skb);
1452
1453                 /* probably a little skewed due to removing CRC */
1454                 total_rx_bytes += skb->len;
1455                 total_rx_packets++;
1456
1457                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1458 #ifdef IXGBE_FCOE
1459                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1460                 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1461                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1462                                                    staterr);
1463                         if (!ddp_bytes)
1464                                 goto next_desc;
1465                 }
1466 #endif /* IXGBE_FCOE */
1467                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1468
1469 next_desc:
1470                 rx_desc->wb.upper.status_error = 0;
1471
1472                 (*work_done)++;
1473                 if (*work_done >= work_to_do)
1474                         break;
1475
1476                 /* return some buffers to hardware, one at a time is too slow */
1477                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1478                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1479                         cleaned_count = 0;
1480                 }
1481
1482                 /* use prefetched values */
1483                 rx_desc = next_rxd;
1484                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1485         }
1486
1487         rx_ring->next_to_clean = i;
1488         cleaned_count = ixgbe_desc_unused(rx_ring);
1489
1490         if (cleaned_count)
1491                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1492
1493 #ifdef IXGBE_FCOE
1494         /* include DDPed FCoE data */
1495         if (ddp_bytes > 0) {
1496                 unsigned int mss;
1497
1498                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1499                         sizeof(struct fc_frame_header) -
1500                         sizeof(struct fcoe_crc_eof);
1501                 if (mss > 512)
1502                         mss &= ~511;
1503                 total_rx_bytes += ddp_bytes;
1504                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1505         }
1506 #endif /* IXGBE_FCOE */
1507
1508         u64_stats_update_begin(&rx_ring->syncp);
1509         rx_ring->stats.packets += total_rx_packets;
1510         rx_ring->stats.bytes += total_rx_bytes;
1511         u64_stats_update_end(&rx_ring->syncp);
1512         q_vector->rx.total_packets += total_rx_packets;
1513         q_vector->rx.total_bytes += total_rx_bytes;
1514 }
1515
1516 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1517 /**
1518  * ixgbe_configure_msix - Configure MSI-X hardware
1519  * @adapter: board private structure
1520  *
1521  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1522  * interrupts.
1523  **/
1524 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1525 {
1526         struct ixgbe_q_vector *q_vector;
1527         int i, q_vectors, v_idx, r_idx;
1528         u32 mask;
1529
1530         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1531
1532         /*
1533          * Populate the IVAR table and set the ITR values to the
1534          * corresponding register.
1535          */
1536         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1537                 q_vector = adapter->q_vector[v_idx];
1538                 /* XXX for_each_set_bit(...) */
1539                 r_idx = find_first_bit(q_vector->rx.idx,
1540                                        adapter->num_rx_queues);
1541
1542                 for (i = 0; i < q_vector->rx.count; i++) {
1543                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1544                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1545                         r_idx = find_next_bit(q_vector->rx.idx,
1546                                               adapter->num_rx_queues,
1547                                               r_idx + 1);
1548                 }
1549                 r_idx = find_first_bit(q_vector->tx.idx,
1550                                        adapter->num_tx_queues);
1551
1552                 for (i = 0; i < q_vector->tx.count; i++) {
1553                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1554                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1555                         r_idx = find_next_bit(q_vector->tx.idx,
1556                                               adapter->num_tx_queues,
1557                                               r_idx + 1);
1558                 }
1559
1560                 if (q_vector->tx.count && !q_vector->rx.count)
1561                         /* tx only */
1562                         q_vector->eitr = adapter->tx_eitr_param;
1563                 else if (q_vector->rx.count)
1564                         /* rx or mixed */
1565                         q_vector->eitr = adapter->rx_eitr_param;
1566
1567                 ixgbe_write_eitr(q_vector);
1568                 /* If ATR is enabled, set interrupt affinity */
1569                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
1570                         /*
1571                          * Allocate the affinity_hint cpumask, assign the mask
1572                          * for this vector, and set our affinity_hint for
1573                          * this irq.
1574                          */
1575                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1576                                                GFP_KERNEL))
1577                                 return;
1578                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1579                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1580                                               q_vector->affinity_mask);
1581                 }
1582         }
1583
1584         switch (adapter->hw.mac.type) {
1585         case ixgbe_mac_82598EB:
1586                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1587                                v_idx);
1588                 break;
1589         case ixgbe_mac_82599EB:
1590         case ixgbe_mac_X540:
1591                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1592                 break;
1593
1594         default:
1595                 break;
1596         }
1597         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1598
1599         /* set up to autoclear timer, and the vectors */
1600         mask = IXGBE_EIMS_ENABLE_MASK;
1601         if (adapter->num_vfs)
1602                 mask &= ~(IXGBE_EIMS_OTHER |
1603                           IXGBE_EIMS_MAILBOX |
1604                           IXGBE_EIMS_LSC);
1605         else
1606                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1607         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1608 }
1609
1610 enum latency_range {
1611         lowest_latency = 0,
1612         low_latency = 1,
1613         bulk_latency = 2,
1614         latency_invalid = 255
1615 };
1616
1617 /**
1618  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1619  * @q_vector: structure containing interrupt and ring information
1620  * @ring_container: structure containing ring performance data
1621  *
1622  *      Stores a new ITR value based on packets and byte
1623  *      counts during the last interrupt.  The advantage of per interrupt
1624  *      computation is faster updates and more accurate ITR for the current
1625  *      traffic pattern.  Constants in this function were computed
1626  *      based on theoretical maximum wire speed and thresholds were set based
1627  *      on testing data as well as attempting to minimize response time
1628  *      while increasing bulk throughput.
1629  *      this functionality is controlled by the InterruptThrottleRate module
1630  *      parameter (see ixgbe_param.c)
1631  **/
1632 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1633                              struct ixgbe_ring_container *ring_container)
1634 {
1635         u64 bytes_perint;
1636         struct ixgbe_adapter *adapter = q_vector->adapter;
1637         int bytes = ring_container->total_bytes;
1638         int packets = ring_container->total_packets;
1639         u32 timepassed_us;
1640         u8 itr_setting = ring_container->itr;
1641
1642         if (packets == 0)
1643                 return;
1644
1645         /* simple throttlerate management
1646          *    0-20MB/s lowest (100000 ints/s)
1647          *   20-100MB/s low   (20000 ints/s)
1648          *  100-1249MB/s bulk (8000 ints/s)
1649          */
1650         /* what was last interrupt timeslice? */
1651         timepassed_us = 1000000/q_vector->eitr;
1652         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1653
1654         switch (itr_setting) {
1655         case lowest_latency:
1656                 if (bytes_perint > adapter->eitr_low)
1657                         itr_setting = low_latency;
1658                 break;
1659         case low_latency:
1660                 if (bytes_perint > adapter->eitr_high)
1661                         itr_setting = bulk_latency;
1662                 else if (bytes_perint <= adapter->eitr_low)
1663                         itr_setting = lowest_latency;
1664                 break;
1665         case bulk_latency:
1666                 if (bytes_perint <= adapter->eitr_high)
1667                         itr_setting = low_latency;
1668                 break;
1669         }
1670
1671         /* clear work counters since we have the values we need */
1672         ring_container->total_bytes = 0;
1673         ring_container->total_packets = 0;
1674
1675         /* write updated itr to ring container */
1676         ring_container->itr = itr_setting;
1677 }
1678
1679 /**
1680  * ixgbe_write_eitr - write EITR register in hardware specific way
1681  * @q_vector: structure containing interrupt and ring information
1682  *
1683  * This function is made to be called by ethtool and by the driver
1684  * when it needs to update EITR registers at runtime.  Hardware
1685  * specific quirks/differences are taken care of here.
1686  */
1687 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1688 {
1689         struct ixgbe_adapter *adapter = q_vector->adapter;
1690         struct ixgbe_hw *hw = &adapter->hw;
1691         int v_idx = q_vector->v_idx;
1692         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1693
1694         switch (adapter->hw.mac.type) {
1695         case ixgbe_mac_82598EB:
1696                 /* must write high and low 16 bits to reset counter */
1697                 itr_reg |= (itr_reg << 16);
1698                 break;
1699         case ixgbe_mac_82599EB:
1700         case ixgbe_mac_X540:
1701                 /*
1702                  * 82599 and X540 can support a value of zero, so allow it for
1703                  * max interrupt rate, but there is an errata where it can
1704                  * not be zero with RSC
1705                  */
1706                 if (itr_reg == 8 &&
1707                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1708                         itr_reg = 0;
1709
1710                 /*
1711                  * set the WDIS bit to not clear the timer bits and cause an
1712                  * immediate assertion of the interrupt
1713                  */
1714                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1715                 break;
1716         default:
1717                 break;
1718         }
1719         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1720 }
1721
1722 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1723 {
1724         u32 new_itr = q_vector->eitr;
1725         u8 current_itr;
1726
1727         ixgbe_update_itr(q_vector, &q_vector->tx);
1728         ixgbe_update_itr(q_vector, &q_vector->rx);
1729
1730         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1731
1732         switch (current_itr) {
1733         /* counts and packets in update_itr are dependent on these numbers */
1734         case lowest_latency:
1735                 new_itr = 100000;
1736                 break;
1737         case low_latency:
1738                 new_itr = 20000; /* aka hwitr = ~200 */
1739                 break;
1740         case bulk_latency:
1741                 new_itr = 8000;
1742                 break;
1743         default:
1744                 break;
1745         }
1746
1747         if (new_itr != q_vector->eitr) {
1748                 /* do an exponential smoothing */
1749                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1750
1751                 /* save the algorithm value here */
1752                 q_vector->eitr = new_itr;
1753
1754                 ixgbe_write_eitr(q_vector);
1755         }
1756 }
1757
1758 /**
1759  * ixgbe_check_overtemp_subtask - check for over tempurature
1760  * @adapter: pointer to adapter
1761  **/
1762 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1763 {
1764         struct ixgbe_hw *hw = &adapter->hw;
1765         u32 eicr = adapter->interrupt_event;
1766
1767         if (test_bit(__IXGBE_DOWN, &adapter->state))
1768                 return;
1769
1770         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1771             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1772                 return;
1773
1774         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1775
1776         switch (hw->device_id) {
1777         case IXGBE_DEV_ID_82599_T3_LOM:
1778                 /*
1779                  * Since the warning interrupt is for both ports
1780                  * we don't have to check if:
1781                  *  - This interrupt wasn't for our port.
1782                  *  - We may have missed the interrupt so always have to
1783                  *    check if we  got a LSC
1784                  */
1785                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1786                     !(eicr & IXGBE_EICR_LSC))
1787                         return;
1788
1789                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1790                         u32 autoneg;
1791                         bool link_up = false;
1792
1793                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1794
1795                         if (link_up)
1796                                 return;
1797                 }
1798
1799                 /* Check if this is not due to overtemp */
1800                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1801                         return;
1802
1803                 break;
1804         default:
1805                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1806                         return;
1807                 break;
1808         }
1809         e_crit(drv,
1810                "Network adapter has been stopped because it has over heated. "
1811                "Restart the computer. If the problem persists, "
1812                "power off the system and replace the adapter\n");
1813
1814         adapter->interrupt_event = 0;
1815 }
1816
1817 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1818 {
1819         struct ixgbe_hw *hw = &adapter->hw;
1820
1821         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1822             (eicr & IXGBE_EICR_GPI_SDP1)) {
1823                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1824                 /* write to clear the interrupt */
1825                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1826         }
1827 }
1828
1829 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1830 {
1831         struct ixgbe_hw *hw = &adapter->hw;
1832
1833         if (eicr & IXGBE_EICR_GPI_SDP2) {
1834                 /* Clear the interrupt */
1835                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1836                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1837                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1838                         ixgbe_service_event_schedule(adapter);
1839                 }
1840         }
1841
1842         if (eicr & IXGBE_EICR_GPI_SDP1) {
1843                 /* Clear the interrupt */
1844                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1845                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1846                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1847                         ixgbe_service_event_schedule(adapter);
1848                 }
1849         }
1850 }
1851
1852 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1853 {
1854         struct ixgbe_hw *hw = &adapter->hw;
1855
1856         adapter->lsc_int++;
1857         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1858         adapter->link_check_timeout = jiffies;
1859         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1860                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1861                 IXGBE_WRITE_FLUSH(hw);
1862                 ixgbe_service_event_schedule(adapter);
1863         }
1864 }
1865
1866 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1867 {
1868         struct ixgbe_adapter *adapter = data;
1869         struct ixgbe_hw *hw = &adapter->hw;
1870         u32 eicr;
1871
1872         /*
1873          * Workaround for Silicon errata.  Use clear-by-write instead
1874          * of clear-by-read.  Reading with EICS will return the
1875          * interrupt causes without clearing, which later be done
1876          * with the write to EICR.
1877          */
1878         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1879         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1880
1881         if (eicr & IXGBE_EICR_LSC)
1882                 ixgbe_check_lsc(adapter);
1883
1884         if (eicr & IXGBE_EICR_MAILBOX)
1885                 ixgbe_msg_task(adapter);
1886
1887         switch (hw->mac.type) {
1888         case ixgbe_mac_82599EB:
1889         case ixgbe_mac_X540:
1890                 /* Handle Flow Director Full threshold interrupt */
1891                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1892                         int reinit_count = 0;
1893                         int i;
1894                         for (i = 0; i < adapter->num_tx_queues; i++) {
1895                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1896                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1897                                                        &ring->state))
1898                                         reinit_count++;
1899                         }
1900                         if (reinit_count) {
1901                                 /* no more flow director interrupts until after init */
1902                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1903                                 eicr &= ~IXGBE_EICR_FLOW_DIR;
1904                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1905                                 ixgbe_service_event_schedule(adapter);
1906                         }
1907                 }
1908                 ixgbe_check_sfp_event(adapter, eicr);
1909                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1910                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1911                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1912                                 adapter->interrupt_event = eicr;
1913                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1914                                 ixgbe_service_event_schedule(adapter);
1915                         }
1916                 }
1917                 break;
1918         default:
1919                 break;
1920         }
1921
1922         ixgbe_check_fan_failure(adapter, eicr);
1923
1924         /* re-enable the original interrupt state, no lsc, no queues */
1925         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1926                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1927                                 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1928
1929         return IRQ_HANDLED;
1930 }
1931
1932 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1933                                            u64 qmask)
1934 {
1935         u32 mask;
1936         struct ixgbe_hw *hw = &adapter->hw;
1937
1938         switch (hw->mac.type) {
1939         case ixgbe_mac_82598EB:
1940                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1941                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1942                 break;
1943         case ixgbe_mac_82599EB:
1944         case ixgbe_mac_X540:
1945                 mask = (qmask & 0xFFFFFFFF);
1946                 if (mask)
1947                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1948                 mask = (qmask >> 32);
1949                 if (mask)
1950                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1951                 break;
1952         default:
1953                 break;
1954         }
1955         /* skip the flush */
1956 }
1957
1958 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1959                                             u64 qmask)
1960 {
1961         u32 mask;
1962         struct ixgbe_hw *hw = &adapter->hw;
1963
1964         switch (hw->mac.type) {
1965         case ixgbe_mac_82598EB:
1966                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1967                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1968                 break;
1969         case ixgbe_mac_82599EB:
1970         case ixgbe_mac_X540:
1971                 mask = (qmask & 0xFFFFFFFF);
1972                 if (mask)
1973                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1974                 mask = (qmask >> 32);
1975                 if (mask)
1976                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1977                 break;
1978         default:
1979                 break;
1980         }
1981         /* skip the flush */
1982 }
1983
1984 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1985 {
1986         struct ixgbe_q_vector *q_vector = data;
1987         struct ixgbe_adapter  *adapter = q_vector->adapter;
1988         struct ixgbe_ring     *tx_ring;
1989         int i, r_idx;
1990
1991         if (!q_vector->tx.count)
1992                 return IRQ_HANDLED;
1993
1994         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
1995         for (i = 0; i < q_vector->tx.count; i++) {
1996                 tx_ring = adapter->tx_ring[r_idx];
1997                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
1998                                       r_idx + 1);
1999         }
2000
2001         /* EIAM disabled interrupts (on this vector) for us */
2002         napi_schedule(&q_vector->napi);
2003
2004         return IRQ_HANDLED;
2005 }
2006
2007 /**
2008  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2009  * @irq: unused
2010  * @data: pointer to our q_vector struct for this interrupt vector
2011  **/
2012 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2013 {
2014         struct ixgbe_q_vector *q_vector = data;
2015         struct ixgbe_adapter  *adapter = q_vector->adapter;
2016         struct ixgbe_ring  *rx_ring;
2017         int r_idx;
2018         int i;
2019
2020 #ifdef CONFIG_IXGBE_DCA
2021         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2022                 ixgbe_update_dca(q_vector);
2023 #endif
2024
2025         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2026         for (i = 0; i < q_vector->rx.count; i++) {
2027                 rx_ring = adapter->rx_ring[r_idx];
2028                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2029                                       r_idx + 1);
2030         }
2031
2032         if (!q_vector->rx.count)
2033                 return IRQ_HANDLED;
2034
2035         /* EIAM disabled interrupts (on this vector) for us */
2036         napi_schedule(&q_vector->napi);
2037
2038         return IRQ_HANDLED;
2039 }
2040
2041 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2042 {
2043         struct ixgbe_q_vector *q_vector = data;
2044         struct ixgbe_adapter  *adapter = q_vector->adapter;
2045         struct ixgbe_ring  *ring;
2046         int r_idx;
2047         int i;
2048
2049         if (!q_vector->tx.count && !q_vector->rx.count)
2050                 return IRQ_HANDLED;
2051
2052         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2053         for (i = 0; i < q_vector->tx.count; i++) {
2054                 ring = adapter->tx_ring[r_idx];
2055                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2056                                       r_idx + 1);
2057         }
2058
2059         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2060         for (i = 0; i < q_vector->rx.count; i++) {
2061                 ring = adapter->rx_ring[r_idx];
2062                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2063                                       r_idx + 1);
2064         }
2065
2066         /* EIAM disabled interrupts (on this vector) for us */
2067         napi_schedule(&q_vector->napi);
2068
2069         return IRQ_HANDLED;
2070 }
2071
2072 /**
2073  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2074  * @napi: napi struct with our devices info in it
2075  * @budget: amount of work driver is allowed to do this pass, in packets
2076  *
2077  * This function is optimized for cleaning one queue only on a single
2078  * q_vector!!!
2079  **/
2080 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2081 {
2082         struct ixgbe_q_vector *q_vector =
2083                                container_of(napi, struct ixgbe_q_vector, napi);
2084         struct ixgbe_adapter *adapter = q_vector->adapter;
2085         struct ixgbe_ring *rx_ring = NULL;
2086         int work_done = 0;
2087         long r_idx;
2088
2089 #ifdef CONFIG_IXGBE_DCA
2090         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2091                 ixgbe_update_dca(q_vector);
2092 #endif
2093
2094         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2095         rx_ring = adapter->rx_ring[r_idx];
2096
2097         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2098
2099         /* If all Rx work done, exit the polling mode */
2100         if (work_done < budget) {
2101                 napi_complete(napi);
2102                 if (adapter->rx_itr_setting & 1)
2103                         ixgbe_set_itr(q_vector);
2104                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2105                         ixgbe_irq_enable_queues(adapter,
2106                                                 ((u64)1 << q_vector->v_idx));
2107         }
2108
2109         return work_done;
2110 }
2111
2112 /**
2113  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2114  * @napi: napi struct with our devices info in it
2115  * @budget: amount of work driver is allowed to do this pass, in packets
2116  *
2117  * This function will clean more than one rx queue associated with a
2118  * q_vector.
2119  **/
2120 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2121 {
2122         struct ixgbe_q_vector *q_vector =
2123                                container_of(napi, struct ixgbe_q_vector, napi);
2124         struct ixgbe_adapter *adapter = q_vector->adapter;
2125         struct ixgbe_ring *ring = NULL;
2126         int work_done = 0, i;
2127         long r_idx;
2128         bool tx_clean_complete = true;
2129
2130 #ifdef CONFIG_IXGBE_DCA
2131         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2132                 ixgbe_update_dca(q_vector);
2133 #endif
2134
2135         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2136         for (i = 0; i < q_vector->tx.count; i++) {
2137                 ring = adapter->tx_ring[r_idx];
2138                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2139                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2140                                       r_idx + 1);
2141         }
2142
2143         /* attempt to distribute budget to each queue fairly, but don't allow
2144          * the budget to go below 1 because we'll exit polling */
2145         budget /= (q_vector->rx.count ?: 1);
2146         budget = max(budget, 1);
2147         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2148         for (i = 0; i < q_vector->rx.count; i++) {
2149                 ring = adapter->rx_ring[r_idx];
2150                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2151                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2152                                       r_idx + 1);
2153         }
2154
2155         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2156         ring = adapter->rx_ring[r_idx];
2157         /* If all Rx work done, exit the polling mode */
2158         if (work_done < budget) {
2159                 napi_complete(napi);
2160                 if (adapter->rx_itr_setting & 1)
2161                         ixgbe_set_itr(q_vector);
2162                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2163                         ixgbe_irq_enable_queues(adapter,
2164                                                 ((u64)1 << q_vector->v_idx));
2165                 return 0;
2166         }
2167
2168         return work_done;
2169 }
2170
2171 /**
2172  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2173  * @napi: napi struct with our devices info in it
2174  * @budget: amount of work driver is allowed to do this pass, in packets
2175  *
2176  * This function is optimized for cleaning one queue only on a single
2177  * q_vector!!!
2178  **/
2179 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2180 {
2181         struct ixgbe_q_vector *q_vector =
2182                                container_of(napi, struct ixgbe_q_vector, napi);
2183         struct ixgbe_adapter *adapter = q_vector->adapter;
2184         struct ixgbe_ring *tx_ring = NULL;
2185         int work_done = 0;
2186         long r_idx;
2187
2188 #ifdef CONFIG_IXGBE_DCA
2189         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2190                 ixgbe_update_dca(q_vector);
2191 #endif
2192
2193         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2194         tx_ring = adapter->tx_ring[r_idx];
2195
2196         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2197                 work_done = budget;
2198
2199         /* If all Tx work done, exit the polling mode */
2200         if (work_done < budget) {
2201                 napi_complete(napi);
2202                 if (adapter->tx_itr_setting & 1)
2203                         ixgbe_set_itr(q_vector);
2204                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2205                         ixgbe_irq_enable_queues(adapter,
2206                                                 ((u64)1 << q_vector->v_idx));
2207         }
2208
2209         return work_done;
2210 }
2211
2212 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2213                                      int r_idx)
2214 {
2215         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2216         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2217
2218         set_bit(r_idx, q_vector->rx.idx);
2219         q_vector->rx.count++;
2220         rx_ring->q_vector = q_vector;
2221 }
2222
2223 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2224                                      int t_idx)
2225 {
2226         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2227         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2228
2229         set_bit(t_idx, q_vector->tx.idx);
2230         q_vector->tx.count++;
2231         tx_ring->q_vector = q_vector;
2232         q_vector->tx.work_limit = a->tx_work_limit;
2233 }
2234
2235 /**
2236  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2237  * @adapter: board private structure to initialize
2238  *
2239  * This function maps descriptor rings to the queue-specific vectors
2240  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2241  * one vector per ring/queue, but on a constrained vector budget, we
2242  * group the rings as "efficiently" as possible.  You would add new
2243  * mapping configurations in here.
2244  **/
2245 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2246 {
2247         int q_vectors;
2248         int v_start = 0;
2249         int rxr_idx = 0, txr_idx = 0;
2250         int rxr_remaining = adapter->num_rx_queues;
2251         int txr_remaining = adapter->num_tx_queues;
2252         int i, j;
2253         int rqpv, tqpv;
2254         int err = 0;
2255
2256         /* No mapping required if MSI-X is disabled. */
2257         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2258                 goto out;
2259
2260         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2261
2262         /*
2263          * The ideal configuration...
2264          * We have enough vectors to map one per queue.
2265          */
2266         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2267                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2268                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2269
2270                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2271                         map_vector_to_txq(adapter, v_start, txr_idx);
2272
2273                 goto out;
2274         }
2275
2276         /*
2277          * If we don't have enough vectors for a 1-to-1
2278          * mapping, we'll have to group them so there are
2279          * multiple queues per vector.
2280          */
2281         /* Re-adjusting *qpv takes care of the remainder. */
2282         for (i = v_start; i < q_vectors; i++) {
2283                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2284                 for (j = 0; j < rqpv; j++) {
2285                         map_vector_to_rxq(adapter, i, rxr_idx);
2286                         rxr_idx++;
2287                         rxr_remaining--;
2288                 }
2289                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2290                 for (j = 0; j < tqpv; j++) {
2291                         map_vector_to_txq(adapter, i, txr_idx);
2292                         txr_idx++;
2293                         txr_remaining--;
2294                 }
2295         }
2296 out:
2297         return err;
2298 }
2299
2300 /**
2301  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2302  * @adapter: board private structure
2303  *
2304  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2305  * interrupts from the kernel.
2306  **/
2307 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2308 {
2309         struct net_device *netdev = adapter->netdev;
2310         irqreturn_t (*handler)(int, void *);
2311         int i, vector, q_vectors, err;
2312         int ri = 0, ti = 0;
2313
2314         /* Decrement for Other and TCP Timer vectors */
2315         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2316
2317         err = ixgbe_map_rings_to_vectors(adapter);
2318         if (err)
2319                 return err;
2320
2321 #define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count)        \
2322                                           ? &ixgbe_msix_clean_many : \
2323                           (_v)->rx.count ? &ixgbe_msix_clean_rx   : \
2324                           (_v)->tx.count ? &ixgbe_msix_clean_tx   : \
2325                           NULL)
2326         for (vector = 0; vector < q_vectors; vector++) {
2327                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2328                 handler = SET_HANDLER(q_vector);
2329
2330                 if (handler == &ixgbe_msix_clean_rx) {
2331                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2332                                  "%s-%s-%d", netdev->name, "rx", ri++);
2333                 } else if (handler == &ixgbe_msix_clean_tx) {
2334                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2335                                  "%s-%s-%d", netdev->name, "tx", ti++);
2336                 } else if (handler == &ixgbe_msix_clean_many) {
2337                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2338                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2339                         ti++;
2340                 } else {
2341                         /* skip this unused q_vector */
2342                         continue;
2343                 }
2344                 err = request_irq(adapter->msix_entries[vector].vector,
2345                                   handler, 0, q_vector->name,
2346                                   q_vector);
2347                 if (err) {
2348                         e_err(probe, "request_irq failed for MSIX interrupt "
2349                               "Error: %d\n", err);
2350                         goto free_queue_irqs;
2351                 }
2352         }
2353
2354         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2355         err = request_irq(adapter->msix_entries[vector].vector,
2356                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2357         if (err) {
2358                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2359                 goto free_queue_irqs;
2360         }
2361
2362         return 0;
2363
2364 free_queue_irqs:
2365         for (i = vector - 1; i >= 0; i--)
2366                 free_irq(adapter->msix_entries[--vector].vector,
2367                          adapter->q_vector[i]);
2368         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2369         pci_disable_msix(adapter->pdev);
2370         kfree(adapter->msix_entries);
2371         adapter->msix_entries = NULL;
2372         return err;
2373 }
2374
2375 /**
2376  * ixgbe_irq_enable - Enable default interrupt generation settings
2377  * @adapter: board private structure
2378  **/
2379 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2380                                     bool flush)
2381 {
2382         u32 mask;
2383
2384         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2385         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2386                 mask |= IXGBE_EIMS_GPI_SDP0;
2387         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2388                 mask |= IXGBE_EIMS_GPI_SDP1;
2389         switch (adapter->hw.mac.type) {
2390         case ixgbe_mac_82599EB:
2391         case ixgbe_mac_X540:
2392                 mask |= IXGBE_EIMS_ECC;
2393                 mask |= IXGBE_EIMS_GPI_SDP1;
2394                 mask |= IXGBE_EIMS_GPI_SDP2;
2395                 if (adapter->num_vfs)
2396                         mask |= IXGBE_EIMS_MAILBOX;
2397                 break;
2398         default:
2399                 break;
2400         }
2401         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2402                 mask |= IXGBE_EIMS_FLOW_DIR;
2403
2404         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2405         if (queues)
2406                 ixgbe_irq_enable_queues(adapter, ~0);
2407         if (flush)
2408                 IXGBE_WRITE_FLUSH(&adapter->hw);
2409
2410         if (adapter->num_vfs > 32) {
2411                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2412                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2413         }
2414 }
2415
2416 /**
2417  * ixgbe_intr - legacy mode Interrupt Handler
2418  * @irq: interrupt number
2419  * @data: pointer to a network interface device structure
2420  **/
2421 static irqreturn_t ixgbe_intr(int irq, void *data)
2422 {
2423         struct ixgbe_adapter *adapter = data;
2424         struct ixgbe_hw *hw = &adapter->hw;
2425         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2426         u32 eicr;
2427
2428         /*
2429          * Workaround for silicon errata on 82598.  Mask the interrupts
2430          * before the read of EICR.
2431          */
2432         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2433
2434         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2435          * therefore no explict interrupt disable is necessary */
2436         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2437         if (!eicr) {
2438                 /*
2439                  * shared interrupt alert!
2440                  * make sure interrupts are enabled because the read will
2441                  * have disabled interrupts due to EIAM
2442                  * finish the workaround of silicon errata on 82598.  Unmask
2443                  * the interrupt that we masked before the EICR read.
2444                  */
2445                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2446                         ixgbe_irq_enable(adapter, true, true);
2447                 return IRQ_NONE;        /* Not our interrupt */
2448         }
2449
2450         if (eicr & IXGBE_EICR_LSC)
2451                 ixgbe_check_lsc(adapter);
2452
2453         switch (hw->mac.type) {
2454         case ixgbe_mac_82599EB:
2455                 ixgbe_check_sfp_event(adapter, eicr);
2456                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2457                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2458                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2459                                 adapter->interrupt_event = eicr;
2460                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2461                                 ixgbe_service_event_schedule(adapter);
2462                         }
2463                 }
2464                 break;
2465         default:
2466                 break;
2467         }
2468
2469         ixgbe_check_fan_failure(adapter, eicr);
2470
2471         if (napi_schedule_prep(&(q_vector->napi))) {
2472                 /* would disable interrupts here but EIAM disabled it */
2473                 __napi_schedule(&(q_vector->napi));
2474         }
2475
2476         /*
2477          * re-enable link(maybe) and non-queue interrupts, no flush.
2478          * ixgbe_poll will re-enable the queue interrupts
2479          */
2480
2481         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2482                 ixgbe_irq_enable(adapter, false, false);
2483
2484         return IRQ_HANDLED;
2485 }
2486
2487 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2488 {
2489         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2490
2491         for (i = 0; i < q_vectors; i++) {
2492                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2493                 bitmap_zero(q_vector->rx.idx, MAX_RX_QUEUES);
2494                 bitmap_zero(q_vector->tx.idx, MAX_TX_QUEUES);
2495                 q_vector->rx.count = 0;
2496                 q_vector->tx.count = 0;
2497         }
2498 }
2499
2500 /**
2501  * ixgbe_request_irq - initialize interrupts
2502  * @adapter: board private structure
2503  *
2504  * Attempts to configure interrupts using the best available
2505  * capabilities of the hardware and kernel.
2506  **/
2507 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2508 {
2509         struct net_device *netdev = adapter->netdev;
2510         int err;
2511
2512         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2513                 err = ixgbe_request_msix_irqs(adapter);
2514         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2515                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2516                                   netdev->name, adapter);
2517         } else {
2518                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2519                                   netdev->name, adapter);
2520         }
2521
2522         if (err)
2523                 e_err(probe, "request_irq failed, Error %d\n", err);
2524
2525         return err;
2526 }
2527
2528 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2529 {
2530         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2531                 int i, q_vectors;
2532
2533                 q_vectors = adapter->num_msix_vectors;
2534
2535                 i = q_vectors - 1;
2536                 free_irq(adapter->msix_entries[i].vector, adapter);
2537
2538                 i--;
2539                 for (; i >= 0; i--) {
2540                         /* free only the irqs that were actually requested */
2541                         if (!adapter->q_vector[i]->rx.count &&
2542                             !adapter->q_vector[i]->tx.count)
2543                                 continue;
2544
2545                         free_irq(adapter->msix_entries[i].vector,
2546                                  adapter->q_vector[i]);
2547                 }
2548
2549                 ixgbe_reset_q_vectors(adapter);
2550         } else {
2551                 free_irq(adapter->pdev->irq, adapter);
2552         }
2553 }
2554
2555 /**
2556  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2557  * @adapter: board private structure
2558  **/
2559 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2560 {
2561         switch (adapter->hw.mac.type) {
2562         case ixgbe_mac_82598EB:
2563                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2564                 break;
2565         case ixgbe_mac_82599EB:
2566         case ixgbe_mac_X540:
2567                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2568                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2569                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2570                 if (adapter->num_vfs > 32)
2571                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2572                 break;
2573         default:
2574                 break;
2575         }
2576         IXGBE_WRITE_FLUSH(&adapter->hw);
2577         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2578                 int i;
2579                 for (i = 0; i < adapter->num_msix_vectors; i++)
2580                         synchronize_irq(adapter->msix_entries[i].vector);
2581         } else {
2582                 synchronize_irq(adapter->pdev->irq);
2583         }
2584 }
2585
2586 /**
2587  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2588  *
2589  **/
2590 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2591 {
2592         struct ixgbe_hw *hw = &adapter->hw;
2593
2594         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2595                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2596
2597         ixgbe_set_ivar(adapter, 0, 0, 0);
2598         ixgbe_set_ivar(adapter, 1, 0, 0);
2599
2600         map_vector_to_rxq(adapter, 0, 0);
2601         map_vector_to_txq(adapter, 0, 0);
2602
2603         e_info(hw, "Legacy interrupt IVAR setup done\n");
2604 }
2605
2606 /**
2607  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2608  * @adapter: board private structure
2609  * @ring: structure containing ring specific data
2610  *
2611  * Configure the Tx descriptor ring after a reset.
2612  **/
2613 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2614                              struct ixgbe_ring *ring)
2615 {
2616         struct ixgbe_hw *hw = &adapter->hw;
2617         u64 tdba = ring->dma;
2618         int wait_loop = 10;
2619         u32 txdctl;
2620         u8 reg_idx = ring->reg_idx;
2621
2622         /* disable queue to avoid issues while updating state */
2623         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2624         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2625                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2626         IXGBE_WRITE_FLUSH(hw);
2627
2628         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2629                         (tdba & DMA_BIT_MASK(32)));
2630         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2631         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2632                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2633         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2634         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2635         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2636
2637         /* configure fetching thresholds */
2638         if (adapter->rx_itr_setting == 0) {
2639                 /* cannot set wthresh when itr==0 */
2640                 txdctl &= ~0x007F0000;
2641         } else {
2642                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2643                 txdctl |= (8 << 16);
2644         }
2645         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2646                 /* PThresh workaround for Tx hang with DFP enabled. */
2647                 txdctl |= 32;
2648         }
2649
2650         /* reinitialize flowdirector state */
2651         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2652             adapter->atr_sample_rate) {
2653                 ring->atr_sample_rate = adapter->atr_sample_rate;
2654                 ring->atr_count = 0;
2655                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2656         } else {
2657                 ring->atr_sample_rate = 0;
2658         }
2659
2660         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2661
2662         /* enable queue */
2663         txdctl |= IXGBE_TXDCTL_ENABLE;
2664         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2665
2666         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2667         if (hw->mac.type == ixgbe_mac_82598EB &&
2668             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2669                 return;
2670
2671         /* poll to verify queue is enabled */
2672         do {
2673                 usleep_range(1000, 2000);
2674                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2675         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2676         if (!wait_loop)
2677                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2678 }
2679
2680 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2681 {
2682         struct ixgbe_hw *hw = &adapter->hw;
2683         u32 rttdcs;
2684         u32 reg;
2685         u8 tcs = netdev_get_num_tc(adapter->netdev);
2686
2687         if (hw->mac.type == ixgbe_mac_82598EB)
2688                 return;
2689
2690         /* disable the arbiter while setting MTQC */
2691         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2692         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2693         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2694
2695         /* set transmit pool layout */
2696         switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2697         case (IXGBE_FLAG_SRIOV_ENABLED):
2698                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2699                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2700                 break;
2701         default:
2702                 if (!tcs)
2703                         reg = IXGBE_MTQC_64Q_1PB;
2704                 else if (tcs <= 4)
2705                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2706                 else
2707                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2708
2709                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2710
2711                 /* Enable Security TX Buffer IFG for multiple pb */
2712                 if (tcs) {
2713                         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2714                         reg |= IXGBE_SECTX_DCB;
2715                         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2716                 }
2717                 break;
2718         }
2719
2720         /* re-enable the arbiter */
2721         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2722         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2723 }
2724
2725 /**
2726  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2727  * @adapter: board private structure
2728  *
2729  * Configure the Tx unit of the MAC after a reset.
2730  **/
2731 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2732 {
2733         struct ixgbe_hw *hw = &adapter->hw;
2734         u32 dmatxctl;
2735         u32 i;
2736
2737         ixgbe_setup_mtqc(adapter);
2738
2739         if (hw->mac.type != ixgbe_mac_82598EB) {
2740                 /* DMATXCTL.EN must be before Tx queues are enabled */
2741                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2742                 dmatxctl |= IXGBE_DMATXCTL_TE;
2743                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2744         }
2745
2746         /* Setup the HW Tx Head and Tail descriptor pointers */
2747         for (i = 0; i < adapter->num_tx_queues; i++)
2748                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2749 }
2750
2751 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2752
2753 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2754                                    struct ixgbe_ring *rx_ring)
2755 {
2756         u32 srrctl;
2757         u8 reg_idx = rx_ring->reg_idx;
2758
2759         switch (adapter->hw.mac.type) {
2760         case ixgbe_mac_82598EB: {
2761                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2762                 const int mask = feature[RING_F_RSS].mask;
2763                 reg_idx = reg_idx & mask;
2764         }
2765                 break;
2766         case ixgbe_mac_82599EB:
2767         case ixgbe_mac_X540:
2768         default:
2769                 break;
2770         }
2771
2772         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2773
2774         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2775         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2776         if (adapter->num_vfs)
2777                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2778
2779         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2780                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2781
2782         if (ring_is_ps_enabled(rx_ring)) {
2783 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2784                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2785 #else
2786                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2787 #endif
2788                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2789         } else {
2790                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2791                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2792                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2793         }
2794
2795         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2796 }
2797
2798 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2799 {
2800         struct ixgbe_hw *hw = &adapter->hw;
2801         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2802                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2803                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2804         u32 mrqc = 0, reta = 0;
2805         u32 rxcsum;
2806         int i, j;
2807         u8 tcs = netdev_get_num_tc(adapter->netdev);
2808         int maxq = adapter->ring_feature[RING_F_RSS].indices;
2809
2810         if (tcs)
2811                 maxq = min(maxq, adapter->num_tx_queues / tcs);
2812
2813         /* Fill out hash function seeds */
2814         for (i = 0; i < 10; i++)
2815                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2816
2817         /* Fill out redirection table */
2818         for (i = 0, j = 0; i < 128; i++, j++) {
2819                 if (j == maxq)
2820                         j = 0;
2821                 /* reta = 4-byte sliding window of
2822                  * 0x00..(indices-1)(indices-1)00..etc. */
2823                 reta = (reta << 8) | (j * 0x11);
2824                 if ((i & 3) == 3)
2825                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2826         }
2827
2828         /* Disable indicating checksum in descriptor, enables RSS hash */
2829         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2830         rxcsum |= IXGBE_RXCSUM_PCSD;
2831         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2832
2833         if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2834             (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2835                 mrqc = IXGBE_MRQC_RSSEN;
2836         } else {
2837                 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2838                                              | IXGBE_FLAG_SRIOV_ENABLED);
2839
2840                 switch (mask) {
2841                 case (IXGBE_FLAG_RSS_ENABLED):
2842                         if (!tcs)
2843                                 mrqc = IXGBE_MRQC_RSSEN;
2844                         else if (tcs <= 4)
2845                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2846                         else
2847                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2848                         break;
2849                 case (IXGBE_FLAG_SRIOV_ENABLED):
2850                         mrqc = IXGBE_MRQC_VMDQEN;
2851                         break;
2852                 default:
2853                         break;
2854                 }
2855         }
2856
2857         /* Perform hash on these packet types */
2858         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2859               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2860               | IXGBE_MRQC_RSS_FIELD_IPV6
2861               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2862
2863         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2864 }
2865
2866 /**
2867  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2868  * @adapter:    address of board private structure
2869  * @index:      index of ring to set
2870  **/
2871 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2872                                    struct ixgbe_ring *ring)
2873 {
2874         struct ixgbe_hw *hw = &adapter->hw;
2875         u32 rscctrl;
2876         int rx_buf_len;
2877         u8 reg_idx = ring->reg_idx;
2878
2879         if (!ring_is_rsc_enabled(ring))
2880                 return;
2881
2882         rx_buf_len = ring->rx_buf_len;
2883         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2884         rscctrl |= IXGBE_RSCCTL_RSCEN;
2885         /*
2886          * we must limit the number of descriptors so that the
2887          * total size of max desc * buf_len is not greater
2888          * than 65535
2889          */
2890         if (ring_is_ps_enabled(ring)) {
2891 #if (MAX_SKB_FRAGS > 16)
2892                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2893 #elif (MAX_SKB_FRAGS > 8)
2894                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2895 #elif (MAX_SKB_FRAGS > 4)
2896                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2897 #else
2898                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2899 #endif
2900         } else {
2901                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2902                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2903                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2904                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2905                 else
2906                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2907         }
2908         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2909 }
2910
2911 /**
2912  *  ixgbe_set_uta - Set unicast filter table address
2913  *  @adapter: board private structure
2914  *
2915  *  The unicast table address is a register array of 32-bit registers.
2916  *  The table is meant to be used in a way similar to how the MTA is used
2917  *  however due to certain limitations in the hardware it is necessary to
2918  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2919  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2920  **/
2921 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2922 {
2923         struct ixgbe_hw *hw = &adapter->hw;
2924         int i;
2925
2926         /* The UTA table only exists on 82599 hardware and newer */
2927         if (hw->mac.type < ixgbe_mac_82599EB)
2928                 return;
2929
2930         /* we only need to do this if VMDq is enabled */
2931         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2932                 return;
2933
2934         for (i = 0; i < 128; i++)
2935                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2936 }
2937
2938 #define IXGBE_MAX_RX_DESC_POLL 10
2939 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2940                                        struct ixgbe_ring *ring)
2941 {
2942         struct ixgbe_hw *hw = &adapter->hw;
2943         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2944         u32 rxdctl;
2945         u8 reg_idx = ring->reg_idx;
2946
2947         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2948         if (hw->mac.type == ixgbe_mac_82598EB &&
2949             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2950                 return;
2951
2952         do {
2953                 usleep_range(1000, 2000);
2954                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2955         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2956
2957         if (!wait_loop) {
2958                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2959                       "the polling period\n", reg_idx);
2960         }
2961 }
2962
2963 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2964                             struct ixgbe_ring *ring)
2965 {
2966         struct ixgbe_hw *hw = &adapter->hw;
2967         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2968         u32 rxdctl;
2969         u8 reg_idx = ring->reg_idx;
2970
2971         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2972         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2973
2974         /* write value back with RXDCTL.ENABLE bit cleared */
2975         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2976
2977         if (hw->mac.type == ixgbe_mac_82598EB &&
2978             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2979                 return;
2980
2981         /* the hardware may take up to 100us to really disable the rx queue */
2982         do {
2983                 udelay(10);
2984                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2985         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2986
2987         if (!wait_loop) {
2988                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2989                       "the polling period\n", reg_idx);
2990         }
2991 }
2992
2993 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2994                              struct ixgbe_ring *ring)
2995 {
2996         struct ixgbe_hw *hw = &adapter->hw;
2997         u64 rdba = ring->dma;
2998         u32 rxdctl;
2999         u8 reg_idx = ring->reg_idx;
3000
3001         /* disable queue to avoid issues while updating state */
3002         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3003         ixgbe_disable_rx_queue(adapter, ring);
3004
3005         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3006         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3007         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3008                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3009         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3010         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3011         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3012
3013         ixgbe_configure_srrctl(adapter, ring);
3014         ixgbe_configure_rscctl(adapter, ring);
3015
3016         /* If operating in IOV mode set RLPML for X540 */
3017         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3018             hw->mac.type == ixgbe_mac_X540) {
3019                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3020                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3021                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3022         }
3023
3024         if (hw->mac.type == ixgbe_mac_82598EB) {
3025                 /*
3026                  * enable cache line friendly hardware writes:
3027                  * PTHRESH=32 descriptors (half the internal cache),
3028                  * this also removes ugly rx_no_buffer_count increment
3029                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3030                  * WTHRESH=8 burst writeback up to two cache lines
3031                  */
3032                 rxdctl &= ~0x3FFFFF;
3033                 rxdctl |=  0x080420;
3034         }
3035
3036         /* enable receive descriptor ring */
3037         rxdctl |= IXGBE_RXDCTL_ENABLE;
3038         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3039
3040         ixgbe_rx_desc_queue_enable(adapter, ring);
3041         ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3042 }
3043
3044 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3045 {
3046         struct ixgbe_hw *hw = &adapter->hw;
3047         int p;
3048
3049         /* PSRTYPE must be initialized in non 82598 adapters */
3050         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3051                       IXGBE_PSRTYPE_UDPHDR |
3052                       IXGBE_PSRTYPE_IPV4HDR |
3053                       IXGBE_PSRTYPE_L2HDR |
3054                       IXGBE_PSRTYPE_IPV6HDR;
3055
3056         if (hw->mac.type == ixgbe_mac_82598EB)
3057                 return;
3058
3059         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3060                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3061
3062         for (p = 0; p < adapter->num_rx_pools; p++)
3063                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3064                                 psrtype);
3065 }
3066
3067 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3068 {
3069         struct ixgbe_hw *hw = &adapter->hw;
3070         u32 gcr_ext;
3071         u32 vt_reg_bits;
3072         u32 reg_offset, vf_shift;
3073         u32 vmdctl;
3074
3075         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3076                 return;
3077
3078         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3079         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3080         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3081         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3082
3083         vf_shift = adapter->num_vfs % 32;
3084         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3085
3086         /* Enable only the PF's pool for Tx/Rx */
3087         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3088         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3089         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3090         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3091         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3092
3093         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3094         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3095
3096         /*
3097          * Set up VF register offsets for selected VT Mode,
3098          * i.e. 32 or 64 VFs for SR-IOV
3099          */
3100         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3101         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3102         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3103         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3104
3105         /* enable Tx loopback for VF/PF communication */
3106         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3107         /* Enable MAC Anti-Spoofing */
3108         hw->mac.ops.set_mac_anti_spoofing(hw,
3109                                           (adapter->antispoofing_enabled =
3110                                            (adapter->num_vfs != 0)),
3111                                           adapter->num_vfs);
3112 }
3113
3114 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3115 {
3116         struct ixgbe_hw *hw = &adapter->hw;
3117         struct net_device *netdev = adapter->netdev;
3118         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3119         int rx_buf_len;
3120         struct ixgbe_ring *rx_ring;
3121         int i;
3122         u32 mhadd, hlreg0;
3123
3124         /* Decide whether to use packet split mode or not */
3125         /* On by default */
3126         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3127
3128         /* Do not use packet split if we're in SR-IOV Mode */
3129         if (adapter->num_vfs)
3130                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3131
3132         /* Disable packet split due to 82599 erratum #45 */
3133         if (hw->mac.type == ixgbe_mac_82599EB)
3134                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3135
3136         /* Set the RX buffer length according to the mode */
3137         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3138                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3139         } else {
3140                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3141                     (netdev->mtu <= ETH_DATA_LEN))
3142                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3143                 else
3144                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3145         }
3146
3147 #ifdef IXGBE_FCOE
3148         /* adjust max frame to be able to do baby jumbo for FCoE */
3149         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3150             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3151                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3152
3153 #endif /* IXGBE_FCOE */
3154         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3155         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3156                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3157                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3158
3159                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3160         }
3161
3162         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3163         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3164         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3165         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3166
3167         /*
3168          * Setup the HW Rx Head and Tail Descriptor Pointers and
3169          * the Base and Length of the Rx Descriptor Ring
3170          */
3171         for (i = 0; i < adapter->num_rx_queues; i++) {
3172                 rx_ring = adapter->rx_ring[i];
3173                 rx_ring->rx_buf_len = rx_buf_len;
3174
3175                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3176                         set_ring_ps_enabled(rx_ring);
3177                 else
3178                         clear_ring_ps_enabled(rx_ring);
3179
3180                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3181                         set_ring_rsc_enabled(rx_ring);
3182                 else
3183                         clear_ring_rsc_enabled(rx_ring);
3184
3185 #ifdef IXGBE_FCOE
3186                 if (netdev->features & NETIF_F_FCOE_MTU) {
3187                         struct ixgbe_ring_feature *f;
3188                         f = &adapter->ring_feature[RING_F_FCOE];
3189                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3190                                 clear_ring_ps_enabled(rx_ring);
3191                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3192                                         rx_ring->rx_buf_len =
3193                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3194                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3195                                    !ring_is_ps_enabled(rx_ring)) {
3196                                 rx_ring->rx_buf_len =
3197                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3198                         }
3199                 }
3200 #endif /* IXGBE_FCOE */
3201         }
3202 }
3203
3204 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3205 {
3206         struct ixgbe_hw *hw = &adapter->hw;
3207         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3208
3209         switch (hw->mac.type) {
3210         case ixgbe_mac_82598EB:
3211                 /*
3212                  * For VMDq support of different descriptor types or
3213                  * buffer sizes through the use of multiple SRRCTL
3214                  * registers, RDRXCTL.MVMEN must be set to 1
3215                  *
3216                  * also, the manual doesn't mention it clearly but DCA hints
3217                  * will only use queue 0's tags unless this bit is set.  Side
3218                  * effects of setting this bit are only that SRRCTL must be
3219                  * fully programmed [0..15]
3220                  */
3221                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3222                 break;
3223         case ixgbe_mac_82599EB:
3224         case ixgbe_mac_X540:
3225                 /* Disable RSC for ACK packets */
3226                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3227                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3228                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3229                 /* hardware requires some bits to be set by default */
3230                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3231                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3232                 break;
3233         default:
3234                 /* We should do nothing since we don't know this hardware */
3235                 return;
3236         }
3237
3238         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3239 }
3240
3241 /**
3242  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3243  * @adapter: board private structure
3244  *
3245  * Configure the Rx unit of the MAC after a reset.
3246  **/
3247 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3248 {
3249         struct ixgbe_hw *hw = &adapter->hw;
3250         int i;
3251         u32 rxctrl;
3252
3253         /* disable receives while setting up the descriptors */
3254         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3255         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3256
3257         ixgbe_setup_psrtype(adapter);
3258         ixgbe_setup_rdrxctl(adapter);
3259
3260         /* Program registers for the distribution of queues */
3261         ixgbe_setup_mrqc(adapter);
3262
3263         ixgbe_set_uta(adapter);
3264
3265         /* set_rx_buffer_len must be called before ring initialization */
3266         ixgbe_set_rx_buffer_len(adapter);
3267
3268         /*
3269          * Setup the HW Rx Head and Tail Descriptor Pointers and
3270          * the Base and Length of the Rx Descriptor Ring
3271          */
3272         for (i = 0; i < adapter->num_rx_queues; i++)
3273                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3274
3275         /* disable drop enable for 82598 parts */
3276         if (hw->mac.type == ixgbe_mac_82598EB)
3277                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3278
3279         /* enable all receives */
3280         rxctrl |= IXGBE_RXCTRL_RXEN;
3281         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3282 }
3283
3284 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3285 {
3286         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3287         struct ixgbe_hw *hw = &adapter->hw;
3288         int pool_ndx = adapter->num_vfs;
3289
3290         /* add VID to filter table */
3291         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3292         set_bit(vid, adapter->active_vlans);
3293 }
3294
3295 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3296 {
3297         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3298         struct ixgbe_hw *hw = &adapter->hw;
3299         int pool_ndx = adapter->num_vfs;
3300
3301         /* remove VID from filter table */
3302         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3303         clear_bit(vid, adapter->active_vlans);
3304 }
3305
3306 /**
3307  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3308  * @adapter: driver data
3309  */
3310 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3311 {
3312         struct ixgbe_hw *hw = &adapter->hw;
3313         u32 vlnctrl;
3314
3315         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3316         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3317         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3318 }
3319
3320 /**
3321  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3322  * @adapter: driver data
3323  */
3324 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3325 {
3326         struct ixgbe_hw *hw = &adapter->hw;
3327         u32 vlnctrl;
3328
3329         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3330         vlnctrl |= IXGBE_VLNCTRL_VFE;
3331         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3332         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3333 }
3334
3335 /**
3336  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3337  * @adapter: driver data
3338  */
3339 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3340 {
3341         struct ixgbe_hw *hw = &adapter->hw;
3342         u32 vlnctrl;
3343         int i, j;
3344
3345         switch (hw->mac.type) {
3346         case ixgbe_mac_82598EB:
3347                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3348                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3349                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3350                 break;
3351         case ixgbe_mac_82599EB:
3352         case ixgbe_mac_X540:
3353                 for (i = 0; i < adapter->num_rx_queues; i++) {
3354                         j = adapter->rx_ring[i]->reg_idx;
3355                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3356                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3357                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3358                 }
3359                 break;
3360         default:
3361                 break;
3362         }
3363 }
3364
3365 /**
3366  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3367  * @adapter: driver data
3368  */
3369 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3370 {
3371         struct ixgbe_hw *hw = &adapter->hw;
3372         u32 vlnctrl;
3373         int i, j;
3374
3375         switch (hw->mac.type) {
3376         case ixgbe_mac_82598EB:
3377                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3378                 vlnctrl |= IXGBE_VLNCTRL_VME;
3379                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3380                 break;
3381         case ixgbe_mac_82599EB:
3382         case ixgbe_mac_X540:
3383                 for (i = 0; i < adapter->num_rx_queues; i++) {
3384                         j = adapter->rx_ring[i]->reg_idx;
3385                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3386                         vlnctrl |= IXGBE_RXDCTL_VME;
3387                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3388                 }
3389                 break;
3390         default:
3391                 break;
3392         }
3393 }
3394
3395 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3396 {
3397         u16 vid;
3398
3399         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3400
3401         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3402                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3403 }
3404
3405 /**
3406  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3407  * @netdev: network interface device structure
3408  *
3409  * Writes unicast address list to the RAR table.
3410  * Returns: -ENOMEM on failure/insufficient address space
3411  *                0 on no addresses written
3412  *                X on writing X addresses to the RAR table
3413  **/
3414 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3415 {
3416         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3417         struct ixgbe_hw *hw = &adapter->hw;
3418         unsigned int vfn = adapter->num_vfs;
3419         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3420         int count = 0;
3421
3422         /* return ENOMEM indicating insufficient memory for addresses */
3423         if (netdev_uc_count(netdev) > rar_entries)
3424                 return -ENOMEM;
3425
3426         if (!netdev_uc_empty(netdev) && rar_entries) {
3427                 struct netdev_hw_addr *ha;
3428                 /* return error if we do not support writing to RAR table */
3429                 if (!hw->mac.ops.set_rar)
3430                         return -ENOMEM;
3431
3432                 netdev_for_each_uc_addr(ha, netdev) {
3433                         if (!rar_entries)
3434                                 break;
3435                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3436                                             vfn, IXGBE_RAH_AV);
3437                         count++;
3438                 }
3439         }
3440         /* write the addresses in reverse order to avoid write combining */
3441         for (; rar_entries > 0 ; rar_entries--)
3442                 hw->mac.ops.clear_rar(hw, rar_entries);
3443
3444         return count;
3445 }
3446
3447 /**
3448  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3449  * @netdev: network interface device structure
3450  *
3451  * The set_rx_method entry point is called whenever the unicast/multicast
3452  * address list or the network interface flags are updated.  This routine is
3453  * responsible for configuring the hardware for proper unicast, multicast and
3454  * promiscuous mode.
3455  **/
3456 void ixgbe_set_rx_mode(struct net_device *netdev)
3457 {
3458         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3459         struct ixgbe_hw *hw = &adapter->hw;
3460         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3461         int count;
3462
3463         /* Check for Promiscuous and All Multicast modes */
3464
3465         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3466
3467         /* set all bits that we expect to always be set */
3468         fctrl |= IXGBE_FCTRL_BAM;
3469         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3470         fctrl |= IXGBE_FCTRL_PMCF;
3471
3472         /* clear the bits we are changing the status of */
3473         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3474
3475         if (netdev->flags & IFF_PROMISC) {
3476                 hw->addr_ctrl.user_set_promisc = true;
3477                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3478                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3479                 /* don't hardware filter vlans in promisc mode */
3480                 ixgbe_vlan_filter_disable(adapter);
3481         } else {
3482                 if (netdev->flags & IFF_ALLMULTI) {
3483                         fctrl |= IXGBE_FCTRL_MPE;
3484                         vmolr |= IXGBE_VMOLR_MPE;
3485                 } else {
3486                         /*
3487                          * Write addresses to the MTA, if the attempt fails
3488                          * then we should just turn on promiscuous mode so
3489                          * that we can at least receive multicast traffic
3490                          */
3491                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3492                         vmolr |= IXGBE_VMOLR_ROMPE;
3493                 }
3494                 ixgbe_vlan_filter_enable(adapter);
3495                 hw->addr_ctrl.user_set_promisc = false;
3496                 /*
3497                  * Write addresses to available RAR registers, if there is not
3498                  * sufficient space to store all the addresses then enable
3499                  * unicast promiscuous mode
3500                  */
3501                 count = ixgbe_write_uc_addr_list(netdev);
3502                 if (count < 0) {
3503                         fctrl |= IXGBE_FCTRL_UPE;
3504                         vmolr |= IXGBE_VMOLR_ROPE;
3505                 }
3506         }
3507
3508         if (adapter->num_vfs) {
3509                 ixgbe_restore_vf_multicasts(adapter);
3510                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3511                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3512                            IXGBE_VMOLR_ROPE);
3513                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3514         }
3515
3516         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3517
3518         if (netdev->features & NETIF_F_HW_VLAN_RX)
3519                 ixgbe_vlan_strip_enable(adapter);
3520         else
3521                 ixgbe_vlan_strip_disable(adapter);
3522 }
3523
3524 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3525 {
3526         int q_idx;
3527         struct ixgbe_q_vector *q_vector;
3528         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3529
3530         /* legacy and MSI only use one vector */
3531         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3532                 q_vectors = 1;
3533
3534         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3535                 struct napi_struct *napi;
3536                 q_vector = adapter->q_vector[q_idx];
3537                 napi = &q_vector->napi;
3538                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3539                         if (!q_vector->rx.count || !q_vector->tx.count) {
3540                                 if (q_vector->tx.count == 1)
3541                                         napi->poll = &ixgbe_clean_txonly;
3542                                 else if (q_vector->rx.count == 1)
3543                                         napi->poll = &ixgbe_clean_rxonly;
3544                         }
3545                 }
3546
3547                 napi_enable(napi);
3548         }
3549 }
3550
3551 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3552 {
3553         int q_idx;
3554         struct ixgbe_q_vector *q_vector;
3555         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3556
3557         /* legacy and MSI only use one vector */
3558         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3559                 q_vectors = 1;
3560
3561         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3562                 q_vector = adapter->q_vector[q_idx];
3563                 napi_disable(&q_vector->napi);
3564         }
3565 }
3566
3567 #ifdef CONFIG_IXGBE_DCB
3568 /*
3569  * ixgbe_configure_dcb - Configure DCB hardware
3570  * @adapter: ixgbe adapter struct
3571  *
3572  * This is called by the driver on open to configure the DCB hardware.
3573  * This is also called by the gennetlink interface when reconfiguring
3574  * the DCB state.
3575  */
3576 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3577 {
3578         struct ixgbe_hw *hw = &adapter->hw;
3579         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3580
3581         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3582                 if (hw->mac.type == ixgbe_mac_82598EB)
3583                         netif_set_gso_max_size(adapter->netdev, 65536);
3584                 return;
3585         }
3586
3587         if (hw->mac.type == ixgbe_mac_82598EB)
3588                 netif_set_gso_max_size(adapter->netdev, 32768);
3589
3590
3591         /* Enable VLAN tag insert/strip */
3592         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3593
3594         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3595
3596         /* reconfigure the hardware */
3597         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3598 #ifdef CONFIG_FCOE
3599                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3600                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3601 #endif
3602                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3603                                                 DCB_TX_CONFIG);
3604                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3605                                                 DCB_RX_CONFIG);
3606                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3607         } else {
3608                 struct net_device *dev = adapter->netdev;
3609
3610                 if (adapter->ixgbe_ieee_ets)
3611                         dev->dcbnl_ops->ieee_setets(dev,
3612                                                     adapter->ixgbe_ieee_ets);
3613                 if (adapter->ixgbe_ieee_pfc)
3614                         dev->dcbnl_ops->ieee_setpfc(dev,
3615                                                     adapter->ixgbe_ieee_pfc);
3616         }
3617
3618         /* Enable RSS Hash per TC */
3619         if (hw->mac.type != ixgbe_mac_82598EB) {
3620                 int i;
3621                 u32 reg = 0;
3622
3623                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3624                         u8 msb = 0;
3625                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3626
3627                         while (cnt >>= 1)
3628                                 msb++;
3629
3630                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3631                 }
3632                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3633         }
3634 }
3635
3636 #endif
3637
3638 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3639 {
3640         int hdrm = 0;
3641         int num_tc = netdev_get_num_tc(adapter->netdev);
3642         struct ixgbe_hw *hw = &adapter->hw;
3643
3644         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3645             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3646                 hdrm = 64 << adapter->fdir_pballoc;
3647
3648         hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3649 }
3650
3651 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3652 {
3653         struct ixgbe_hw *hw = &adapter->hw;
3654         struct hlist_node *node, *node2;
3655         struct ixgbe_fdir_filter *filter;
3656
3657         spin_lock(&adapter->fdir_perfect_lock);
3658
3659         if (!hlist_empty(&adapter->fdir_filter_list))
3660                 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3661
3662         hlist_for_each_entry_safe(filter, node, node2,
3663                                   &adapter->fdir_filter_list, fdir_node) {
3664                 ixgbe_fdir_write_perfect_filter_82599(hw,
3665                                 &filter->filter,
3666                                 filter->sw_idx,
3667                                 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3668                                 IXGBE_FDIR_DROP_QUEUE :
3669                                 adapter->rx_ring[filter->action]->reg_idx);
3670         }
3671
3672         spin_unlock(&adapter->fdir_perfect_lock);
3673 }
3674
3675 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3676 {
3677         struct net_device *netdev = adapter->netdev;
3678         struct ixgbe_hw *hw = &adapter->hw;
3679         int i;
3680
3681         ixgbe_configure_pb(adapter);
3682 #ifdef CONFIG_IXGBE_DCB
3683         ixgbe_configure_dcb(adapter);
3684 #endif
3685
3686         ixgbe_set_rx_mode(netdev);
3687         ixgbe_restore_vlan(adapter);
3688
3689 #ifdef IXGBE_FCOE
3690         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3691                 ixgbe_configure_fcoe(adapter);
3692
3693 #endif /* IXGBE_FCOE */
3694         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3695                 for (i = 0; i < adapter->num_tx_queues; i++)
3696                         adapter->tx_ring[i]->atr_sample_rate =
3697                                                        adapter->atr_sample_rate;
3698                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3699         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3700                 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3701                                               adapter->fdir_pballoc);
3702                 ixgbe_fdir_filter_restore(adapter);
3703         }
3704         ixgbe_configure_virtualization(adapter);
3705
3706         ixgbe_configure_tx(adapter);
3707         ixgbe_configure_rx(adapter);
3708 }
3709
3710 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3711 {
3712         switch (hw->phy.type) {
3713         case ixgbe_phy_sfp_avago:
3714         case ixgbe_phy_sfp_ftl:
3715         case ixgbe_phy_sfp_intel:
3716         case ixgbe_phy_sfp_unknown:
3717         case ixgbe_phy_sfp_passive_tyco:
3718         case ixgbe_phy_sfp_passive_unknown:
3719         case ixgbe_phy_sfp_active_unknown:
3720         case ixgbe_phy_sfp_ftl_active:
3721                 return true;
3722         default:
3723                 return false;
3724         }
3725 }
3726
3727 /**
3728  * ixgbe_sfp_link_config - set up SFP+ link
3729  * @adapter: pointer to private adapter struct
3730  **/
3731 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3732 {
3733         /*
3734          * We are assuming the worst case scenerio here, and that
3735          * is that an SFP was inserted/removed after the reset
3736          * but before SFP detection was enabled.  As such the best
3737          * solution is to just start searching as soon as we start
3738          */
3739         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3740                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3741
3742         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3743 }
3744
3745 /**
3746  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3747  * @hw: pointer to private hardware struct
3748  *
3749  * Returns 0 on success, negative on failure
3750  **/
3751 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3752 {
3753         u32 autoneg;
3754         bool negotiation, link_up = false;
3755         u32 ret = IXGBE_ERR_LINK_SETUP;
3756
3757         if (hw->mac.ops.check_link)
3758                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3759
3760         if (ret)
3761                 goto link_cfg_out;
3762
3763         autoneg = hw->phy.autoneg_advertised;
3764         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3765                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3766                                                         &negotiation);
3767         if (ret)
3768                 goto link_cfg_out;
3769
3770         if (hw->mac.ops.setup_link)
3771                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3772 link_cfg_out:
3773         return ret;
3774 }
3775
3776 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3777 {
3778         struct ixgbe_hw *hw = &adapter->hw;
3779         u32 gpie = 0;
3780
3781         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3782                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3783                        IXGBE_GPIE_OCD;
3784                 gpie |= IXGBE_GPIE_EIAME;
3785                 /*
3786                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3787                  * this saves a register write for every interrupt
3788                  */
3789                 switch (hw->mac.type) {
3790                 case ixgbe_mac_82598EB:
3791                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3792                         break;
3793                 case ixgbe_mac_82599EB:
3794                 case ixgbe_mac_X540:
3795                 default:
3796                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3797                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3798                         break;
3799                 }
3800         } else {
3801                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3802                  * specifically only auto mask tx and rx interrupts */
3803                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3804         }
3805
3806         /* XXX: to interrupt immediately for EICS writes, enable this */
3807         /* gpie |= IXGBE_GPIE_EIMEN; */
3808
3809         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3810                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3811                 gpie |= IXGBE_GPIE_VTMODE_64;
3812         }
3813
3814         /* Enable fan failure interrupt */
3815         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3816                 gpie |= IXGBE_SDP1_GPIEN;
3817
3818         if (hw->mac.type == ixgbe_mac_82599EB) {
3819                 gpie |= IXGBE_SDP1_GPIEN;
3820                 gpie |= IXGBE_SDP2_GPIEN;
3821         }
3822
3823         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3824 }
3825
3826 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3827 {
3828         struct ixgbe_hw *hw = &adapter->hw;
3829         int err;
3830         u32 ctrl_ext;
3831
3832         ixgbe_get_hw_control(adapter);
3833         ixgbe_setup_gpie(adapter);
3834
3835         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3836                 ixgbe_configure_msix(adapter);
3837         else
3838                 ixgbe_configure_msi_and_legacy(adapter);
3839
3840         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3841         if (hw->mac.ops.enable_tx_laser &&
3842             ((hw->phy.multispeed_fiber) ||
3843              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3844               (hw->mac.type == ixgbe_mac_82599EB))))
3845                 hw->mac.ops.enable_tx_laser(hw);
3846
3847         clear_bit(__IXGBE_DOWN, &adapter->state);
3848         ixgbe_napi_enable_all(adapter);
3849
3850         if (ixgbe_is_sfp(hw)) {
3851                 ixgbe_sfp_link_config(adapter);
3852         } else {
3853                 err = ixgbe_non_sfp_link_config(hw);
3854                 if (err)
3855                         e_err(probe, "link_config FAILED %d\n", err);
3856         }
3857
3858         /* clear any pending interrupts, may auto mask */
3859         IXGBE_READ_REG(hw, IXGBE_EICR);
3860         ixgbe_irq_enable(adapter, true, true);
3861
3862         /*
3863          * If this adapter has a fan, check to see if we had a failure
3864          * before we enabled the interrupt.
3865          */
3866         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3867                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3868                 if (esdp & IXGBE_ESDP_SDP1)
3869                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3870         }
3871
3872         /* enable transmits */
3873         netif_tx_start_all_queues(adapter->netdev);
3874
3875         /* bring the link up in the watchdog, this could race with our first
3876          * link up interrupt but shouldn't be a problem */
3877         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3878         adapter->link_check_timeout = jiffies;
3879         mod_timer(&adapter->service_timer, jiffies);
3880
3881         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3882         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3883         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3884         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3885
3886         return 0;
3887 }
3888
3889 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3890 {
3891         WARN_ON(in_interrupt());
3892         /* put off any impending NetWatchDogTimeout */
3893         adapter->netdev->trans_start = jiffies;
3894
3895         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3896                 usleep_range(1000, 2000);
3897         ixgbe_down(adapter);
3898         /*
3899          * If SR-IOV enabled then wait a bit before bringing the adapter
3900          * back up to give the VFs time to respond to the reset.  The
3901          * two second wait is based upon the watchdog timer cycle in
3902          * the VF driver.
3903          */
3904         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3905                 msleep(2000);
3906         ixgbe_up(adapter);
3907         clear_bit(__IXGBE_RESETTING, &adapter->state);
3908 }
3909
3910 int ixgbe_up(struct ixgbe_adapter *adapter)
3911 {
3912         /* hardware has been reset, we need to reload some things */
3913         ixgbe_configure(adapter);
3914
3915         return ixgbe_up_complete(adapter);
3916 }
3917
3918 void ixgbe_reset(struct ixgbe_adapter *adapter)
3919 {
3920         struct ixgbe_hw *hw = &adapter->hw;
3921         int err;
3922
3923         /* lock SFP init bit to prevent race conditions with the watchdog */
3924         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3925                 usleep_range(1000, 2000);
3926
3927         /* clear all SFP and link config related flags while holding SFP_INIT */
3928         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3929                              IXGBE_FLAG2_SFP_NEEDS_RESET);
3930         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3931
3932         err = hw->mac.ops.init_hw(hw);
3933         switch (err) {
3934         case 0:
3935         case IXGBE_ERR_SFP_NOT_PRESENT:
3936         case IXGBE_ERR_SFP_NOT_SUPPORTED:
3937                 break;
3938         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3939                 e_dev_err("master disable timed out\n");
3940                 break;
3941         case IXGBE_ERR_EEPROM_VERSION:
3942                 /* We are running on a pre-production device, log a warning */
3943                 e_dev_warn("This device is a pre-production adapter/LOM. "
3944                            "Please be aware there may be issuesassociated with "
3945                            "your hardware.  If you are experiencing problems "
3946                            "please contact your Intel or hardware "
3947                            "representative who provided you with this "
3948                            "hardware.\n");
3949                 break;
3950         default:
3951                 e_dev_err("Hardware Error: %d\n", err);
3952         }
3953
3954         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3955
3956         /* reprogram the RAR[0] in case user changed it. */
3957         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3958                             IXGBE_RAH_AV);
3959 }
3960
3961 /**
3962  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3963  * @rx_ring: ring to free buffers from
3964  **/
3965 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3966 {
3967         struct device *dev = rx_ring->dev;
3968         unsigned long size;
3969         u16 i;
3970
3971         /* ring already cleared, nothing to do */
3972         if (!rx_ring->rx_buffer_info)
3973                 return;
3974
3975         /* Free all the Rx ring sk_buffs */
3976         for (i = 0; i < rx_ring->count; i++) {
3977                 struct ixgbe_rx_buffer *rx_buffer_info;
3978
3979                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3980                 if (rx_buffer_info->dma) {
3981                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3982                                          rx_ring->rx_buf_len,
3983                                          DMA_FROM_DEVICE);
3984                         rx_buffer_info->dma = 0;
3985                 }
3986                 if (rx_buffer_info->skb) {
3987                         struct sk_buff *skb = rx_buffer_info->skb;
3988                         rx_buffer_info->skb = NULL;
3989                         do {
3990                                 struct sk_buff *this = skb;
3991                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3992                                         dma_unmap_single(dev,
3993                                                          IXGBE_RSC_CB(this)->dma,
3994                                                          rx_ring->rx_buf_len,
3995                                                          DMA_FROM_DEVICE);
3996                                         IXGBE_RSC_CB(this)->dma = 0;
3997                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3998                                 }
3999                                 skb = skb->prev;
4000                                 dev_kfree_skb(this);
4001                         } while (skb);
4002                 }
4003                 if (!rx_buffer_info->page)
4004                         continue;
4005                 if (rx_buffer_info->page_dma) {
4006                         dma_unmap_page(dev, rx_buffer_info->page_dma,
4007                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
4008                         rx_buffer_info->page_dma = 0;
4009                 }
4010                 put_page(rx_buffer_info->page);
4011                 rx_buffer_info->page = NULL;
4012                 rx_buffer_info->page_offset = 0;
4013         }
4014
4015         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4016         memset(rx_ring->rx_buffer_info, 0, size);
4017
4018         /* Zero out the descriptor ring */
4019         memset(rx_ring->desc, 0, rx_ring->size);
4020
4021         rx_ring->next_to_clean = 0;
4022         rx_ring->next_to_use = 0;
4023 }
4024
4025 /**
4026  * ixgbe_clean_tx_ring - Free Tx Buffers
4027  * @tx_ring: ring to be cleaned
4028  **/
4029 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4030 {
4031         struct ixgbe_tx_buffer *tx_buffer_info;
4032         unsigned long size;
4033         u16 i;
4034
4035         /* ring already cleared, nothing to do */
4036         if (!tx_ring->tx_buffer_info)
4037                 return;
4038
4039         /* Free all the Tx ring sk_buffs */
4040         for (i = 0; i < tx_ring->count; i++) {
4041                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4042                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4043         }
4044
4045         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4046         memset(tx_ring->tx_buffer_info, 0, size);
4047
4048         /* Zero out the descriptor ring */
4049         memset(tx_ring->desc, 0, tx_ring->size);
4050
4051         tx_ring->next_to_use = 0;
4052         tx_ring->next_to_clean = 0;
4053 }
4054
4055 /**
4056  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4057  * @adapter: board private structure
4058  **/
4059 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4060 {
4061         int i;
4062
4063         for (i = 0; i < adapter->num_rx_queues; i++)
4064                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4065 }
4066
4067 /**
4068  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4069  * @adapter: board private structure
4070  **/
4071 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4072 {
4073         int i;
4074
4075         for (i = 0; i < adapter->num_tx_queues; i++)
4076                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4077 }
4078
4079 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4080 {
4081         struct hlist_node *node, *node2;
4082         struct ixgbe_fdir_filter *filter;
4083
4084         spin_lock(&adapter->fdir_perfect_lock);
4085
4086         hlist_for_each_entry_safe(filter, node, node2,
4087                                   &adapter->fdir_filter_list, fdir_node) {
4088                 hlist_del(&filter->fdir_node);
4089                 kfree(filter);
4090         }
4091         adapter->fdir_filter_count = 0;
4092
4093         spin_unlock(&adapter->fdir_perfect_lock);
4094 }
4095
4096 void ixgbe_down(struct ixgbe_adapter *adapter)
4097 {
4098         struct net_device *netdev = adapter->netdev;
4099         struct ixgbe_hw *hw = &adapter->hw;
4100         u32 rxctrl;
4101         int i;
4102         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4103
4104         /* signal that we are down to the interrupt handler */
4105         set_bit(__IXGBE_DOWN, &adapter->state);
4106
4107         /* disable receives */
4108         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4109         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4110
4111         /* disable all enabled rx queues */
4112         for (i = 0; i < adapter->num_rx_queues; i++)
4113                 /* this call also flushes the previous write */
4114                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4115
4116         usleep_range(10000, 20000);
4117
4118         netif_tx_stop_all_queues(netdev);
4119
4120         /* call carrier off first to avoid false dev_watchdog timeouts */
4121         netif_carrier_off(netdev);
4122         netif_tx_disable(netdev);
4123
4124         ixgbe_irq_disable(adapter);
4125
4126         ixgbe_napi_disable_all(adapter);
4127
4128         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4129                              IXGBE_FLAG2_RESET_REQUESTED);
4130         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4131
4132         del_timer_sync(&adapter->service_timer);
4133
4134         /* disable receive for all VFs and wait one second */
4135         if (adapter->num_vfs) {
4136                 /* ping all the active vfs to let them know we are going down */
4137                 ixgbe_ping_all_vfs(adapter);
4138
4139                 /* Disable all VFTE/VFRE TX/RX */
4140                 ixgbe_disable_tx_rx(adapter);
4141
4142                 /* Mark all the VFs as inactive */
4143                 for (i = 0 ; i < adapter->num_vfs; i++)
4144                         adapter->vfinfo[i].clear_to_send = 0;
4145         }
4146
4147         /* Cleanup the affinity_hint CPU mask memory and callback */
4148         for (i = 0; i < num_q_vectors; i++) {
4149                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4150                 /* clear the affinity_mask in the IRQ descriptor */
4151                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4152                 /* release the CPU mask memory */
4153                 free_cpumask_var(q_vector->affinity_mask);
4154         }
4155
4156         /* disable transmits in the hardware now that interrupts are off */
4157         for (i = 0; i < adapter->num_tx_queues; i++) {
4158                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4159                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4160         }
4161
4162         /* Disable the Tx DMA engine on 82599 and X540 */
4163         switch (hw->mac.type) {
4164         case ixgbe_mac_82599EB:
4165         case ixgbe_mac_X540:
4166                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4167                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4168                                  ~IXGBE_DMATXCTL_TE));
4169                 break;
4170         default:
4171                 break;
4172         }
4173
4174         if (!pci_channel_offline(adapter->pdev))
4175                 ixgbe_reset(adapter);
4176
4177         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4178         if (hw->mac.ops.disable_tx_laser &&
4179             ((hw->phy.multispeed_fiber) ||
4180              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4181               (hw->mac.type == ixgbe_mac_82599EB))))
4182                 hw->mac.ops.disable_tx_laser(hw);
4183
4184         ixgbe_clean_all_tx_rings(adapter);
4185         ixgbe_clean_all_rx_rings(adapter);
4186
4187 #ifdef CONFIG_IXGBE_DCA
4188         /* since we reset the hardware DCA settings were cleared */
4189         ixgbe_setup_dca(adapter);
4190 #endif
4191 }
4192
4193 /**
4194  * ixgbe_poll - NAPI Rx polling callback
4195  * @napi: structure for representing this polling device
4196  * @budget: how many packets driver is allowed to clean
4197  *
4198  * This function is used for legacy and MSI, NAPI mode
4199  **/
4200 static int ixgbe_poll(struct napi_struct *napi, int budget)
4201 {
4202         struct ixgbe_q_vector *q_vector =
4203                                 container_of(napi, struct ixgbe_q_vector, napi);
4204         struct ixgbe_adapter *adapter = q_vector->adapter;
4205         int tx_clean_complete, work_done = 0;
4206
4207 #ifdef CONFIG_IXGBE_DCA
4208         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4209                 ixgbe_update_dca(q_vector);
4210 #endif
4211
4212         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4213         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4214
4215         if (!tx_clean_complete)
4216                 work_done = budget;
4217
4218         /* If budget not fully consumed, exit the polling mode */
4219         if (work_done < budget) {
4220                 napi_complete(napi);
4221                 if (adapter->rx_itr_setting & 1)
4222                         ixgbe_set_itr(q_vector);
4223                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4224                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4225         }
4226         return work_done;
4227 }
4228
4229 /**
4230  * ixgbe_tx_timeout - Respond to a Tx Hang
4231  * @netdev: network interface device structure
4232  **/
4233 static void ixgbe_tx_timeout(struct net_device *netdev)
4234 {
4235         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4236
4237         /* Do the reset outside of interrupt context */
4238         ixgbe_tx_timeout_reset(adapter);
4239 }
4240
4241 /**
4242  * ixgbe_set_rss_queues: Allocate queues for RSS
4243  * @adapter: board private structure to initialize
4244  *
4245  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4246  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4247  *
4248  **/
4249 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4250 {
4251         bool ret = false;
4252         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4253
4254         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4255                 f->mask = 0xF;
4256                 adapter->num_rx_queues = f->indices;
4257                 adapter->num_tx_queues = f->indices;
4258                 ret = true;
4259         } else {
4260                 ret = false;
4261         }
4262
4263         return ret;
4264 }
4265
4266 /**
4267  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4268  * @adapter: board private structure to initialize
4269  *
4270  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4271  * to the original CPU that initiated the Tx session.  This runs in addition
4272  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4273  * Rx load across CPUs using RSS.
4274  *
4275  **/
4276 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4277 {
4278         bool ret = false;
4279         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4280
4281         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4282         f_fdir->mask = 0;
4283
4284         /* Flow Director must have RSS enabled */
4285         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4286             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4287                 adapter->num_tx_queues = f_fdir->indices;
4288                 adapter->num_rx_queues = f_fdir->indices;
4289                 ret = true;
4290         } else {
4291                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4292         }
4293         return ret;
4294 }
4295
4296 #ifdef IXGBE_FCOE
4297 /**
4298  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4299  * @adapter: board private structure to initialize
4300  *
4301  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4302  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4303  * rx queues out of the max number of rx queues, instead, it is used as the
4304  * index of the first rx queue used by FCoE.
4305  *
4306  **/
4307 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4308 {
4309         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4310
4311         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4312                 return false;
4313
4314         f->indices = min((int)num_online_cpus(), f->indices);
4315
4316         adapter->num_rx_queues = 1;
4317         adapter->num_tx_queues = 1;
4318
4319         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4320                 e_info(probe, "FCoE enabled with RSS\n");
4321                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4322                         ixgbe_set_fdir_queues(adapter);
4323                 else
4324                         ixgbe_set_rss_queues(adapter);
4325         }
4326
4327         /* adding FCoE rx rings to the end */
4328         f->mask = adapter->num_rx_queues;
4329         adapter->num_rx_queues += f->indices;
4330         adapter->num_tx_queues += f->indices;
4331
4332         return true;
4333 }
4334 #endif /* IXGBE_FCOE */
4335
4336 /* Artificial max queue cap per traffic class in DCB mode */
4337 #define DCB_QUEUE_CAP 8
4338
4339 #ifdef CONFIG_IXGBE_DCB
4340 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4341 {
4342         int per_tc_q, q, i, offset = 0;
4343         struct net_device *dev = adapter->netdev;
4344         int tcs = netdev_get_num_tc(dev);
4345
4346         if (!tcs)
4347                 return false;
4348
4349         /* Map queue offset and counts onto allocated tx queues */
4350         per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4351         q = min((int)num_online_cpus(), per_tc_q);
4352
4353         for (i = 0; i < tcs; i++) {
4354                 netdev_set_prio_tc_map(dev, i, i);
4355                 netdev_set_tc_queue(dev, i, q, offset);
4356                 offset += q;
4357         }
4358
4359         adapter->num_tx_queues = q * tcs;
4360         adapter->num_rx_queues = q * tcs;
4361
4362 #ifdef IXGBE_FCOE
4363         /* FCoE enabled queues require special configuration indexed
4364          * by feature specific indices and mask. Here we map FCoE
4365          * indices onto the DCB queue pairs allowing FCoE to own
4366          * configuration later.
4367          */
4368         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4369                 int tc;
4370                 struct ixgbe_ring_feature *f =
4371                                         &adapter->ring_feature[RING_F_FCOE];
4372
4373                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4374                 f->indices = dev->tc_to_txq[tc].count;
4375                 f->mask = dev->tc_to_txq[tc].offset;
4376         }
4377 #endif
4378
4379         return true;
4380 }
4381 #endif
4382
4383 /**
4384  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4385  * @adapter: board private structure to initialize
4386  *
4387  * IOV doesn't actually use anything, so just NAK the
4388  * request for now and let the other queue routines
4389  * figure out what to do.
4390  */
4391 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4392 {
4393         return false;
4394 }
4395
4396 /*
4397  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4398  * @adapter: board private structure to initialize
4399  *
4400  * This is the top level queue allocation routine.  The order here is very
4401  * important, starting with the "most" number of features turned on at once,
4402  * and ending with the smallest set of features.  This way large combinations
4403  * can be allocated if they're turned on, and smaller combinations are the
4404  * fallthrough conditions.
4405  *
4406  **/
4407 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4408 {
4409         /* Start with base case */
4410         adapter->num_rx_queues = 1;
4411         adapter->num_tx_queues = 1;
4412         adapter->num_rx_pools = adapter->num_rx_queues;
4413         adapter->num_rx_queues_per_pool = 1;
4414
4415         if (ixgbe_set_sriov_queues(adapter))
4416                 goto done;
4417
4418 #ifdef CONFIG_IXGBE_DCB
4419         if (ixgbe_set_dcb_queues(adapter))
4420                 goto done;
4421
4422 #endif
4423 #ifdef IXGBE_FCOE
4424         if (ixgbe_set_fcoe_queues(adapter))
4425                 goto done;
4426
4427 #endif /* IXGBE_FCOE */
4428         if (ixgbe_set_fdir_queues(adapter))
4429                 goto done;
4430
4431         if (ixgbe_set_rss_queues(adapter))
4432                 goto done;
4433
4434         /* fallback to base case */
4435         adapter->num_rx_queues = 1;
4436         adapter->num_tx_queues = 1;
4437
4438 done:
4439         /* Notify the stack of the (possibly) reduced queue counts. */
4440         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4441         return netif_set_real_num_rx_queues(adapter->netdev,
4442                                             adapter->num_rx_queues);
4443 }
4444
4445 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4446                                        int vectors)
4447 {
4448         int err, vector_threshold;
4449
4450         /* We'll want at least 3 (vector_threshold):
4451          * 1) TxQ[0] Cleanup
4452          * 2) RxQ[0] Cleanup
4453          * 3) Other (Link Status Change, etc.)
4454          * 4) TCP Timer (optional)
4455          */
4456         vector_threshold = MIN_MSIX_COUNT;
4457
4458         /* The more we get, the more we will assign to Tx/Rx Cleanup
4459          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4460          * Right now, we simply care about how many we'll get; we'll
4461          * set them up later while requesting irq's.
4462          */
4463         while (vectors >= vector_threshold) {
4464                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4465                                       vectors);
4466                 if (!err) /* Success in acquiring all requested vectors. */
4467                         break;
4468                 else if (err < 0)
4469                         vectors = 0; /* Nasty failure, quit now */
4470                 else /* err == number of vectors we should try again with */
4471                         vectors = err;
4472         }
4473
4474         if (vectors < vector_threshold) {
4475                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4476                  * This just means we'll go with either a single MSI
4477                  * vector or fall back to legacy interrupts.
4478                  */
4479                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4480                              "Unable to allocate MSI-X interrupts\n");
4481                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4482                 kfree(adapter->msix_entries);
4483                 adapter->msix_entries = NULL;
4484         } else {
4485                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4486                 /*
4487                  * Adjust for only the vectors we'll use, which is minimum
4488                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4489                  * vectors we were allocated.
4490                  */
4491                 adapter->num_msix_vectors = min(vectors,
4492                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4493         }
4494 }
4495
4496 /**
4497  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4498  * @adapter: board private structure to initialize
4499  *
4500  * Cache the descriptor ring offsets for RSS to the assigned rings.
4501  *
4502  **/
4503 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4504 {
4505         int i;
4506
4507         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4508                 return false;
4509
4510         for (i = 0; i < adapter->num_rx_queues; i++)
4511                 adapter->rx_ring[i]->reg_idx = i;
4512         for (i = 0; i < adapter->num_tx_queues; i++)
4513                 adapter->tx_ring[i]->reg_idx = i;
4514
4515         return true;
4516 }
4517
4518 #ifdef CONFIG_IXGBE_DCB
4519
4520 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4521 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4522                                     unsigned int *tx, unsigned int *rx)
4523 {
4524         struct net_device *dev = adapter->netdev;
4525         struct ixgbe_hw *hw = &adapter->hw;
4526         u8 num_tcs = netdev_get_num_tc(dev);
4527
4528         *tx = 0;
4529         *rx = 0;
4530
4531         switch (hw->mac.type) {
4532         case ixgbe_mac_82598EB:
4533                 *tx = tc << 2;
4534                 *rx = tc << 3;
4535                 break;
4536         case ixgbe_mac_82599EB:
4537         case ixgbe_mac_X540:
4538                 if (num_tcs == 8) {
4539                         if (tc < 3) {
4540                                 *tx = tc << 5;
4541                                 *rx = tc << 4;
4542                         } else if (tc <  5) {
4543                                 *tx = ((tc + 2) << 4);
4544                                 *rx = tc << 4;
4545                         } else if (tc < num_tcs) {
4546                                 *tx = ((tc + 8) << 3);
4547                                 *rx = tc << 4;
4548                         }
4549                 } else if (num_tcs == 4) {
4550                         *rx =  tc << 5;
4551                         switch (tc) {
4552                         case 0:
4553                                 *tx =  0;
4554                                 break;
4555                         case 1:
4556                                 *tx = 64;
4557                                 break;
4558                         case 2:
4559                                 *tx = 96;
4560                                 break;
4561                         case 3:
4562                                 *tx = 112;
4563                                 break;
4564                         default:
4565                                 break;
4566                         }
4567                 }
4568                 break;
4569         default:
4570                 break;
4571         }
4572 }
4573
4574 /**
4575  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4576  * @adapter: board private structure to initialize
4577  *
4578  * Cache the descriptor ring offsets for DCB to the assigned rings.
4579  *
4580  **/
4581 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4582 {
4583         struct net_device *dev = adapter->netdev;
4584         int i, j, k;
4585         u8 num_tcs = netdev_get_num_tc(dev);
4586
4587         if (!num_tcs)
4588                 return false;
4589
4590         for (i = 0, k = 0; i < num_tcs; i++) {
4591                 unsigned int tx_s, rx_s;
4592                 u16 count = dev->tc_to_txq[i].count;
4593
4594                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4595                 for (j = 0; j < count; j++, k++) {
4596                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4597                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4598                         adapter->tx_ring[k]->dcb_tc = i;
4599                         adapter->rx_ring[k]->dcb_tc = i;
4600                 }
4601         }
4602
4603         return true;
4604 }
4605 #endif
4606
4607 /**
4608  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4609  * @adapter: board private structure to initialize
4610  *
4611  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4612  *
4613  **/
4614 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4615 {
4616         int i;
4617         bool ret = false;
4618
4619         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4620             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4621                 for (i = 0; i < adapter->num_rx_queues; i++)
4622                         adapter->rx_ring[i]->reg_idx = i;
4623                 for (i = 0; i < adapter->num_tx_queues; i++)
4624                         adapter->tx_ring[i]->reg_idx = i;
4625                 ret = true;
4626         }
4627
4628         return ret;
4629 }
4630
4631 #ifdef IXGBE_FCOE
4632 /**
4633  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4634  * @adapter: board private structure to initialize
4635  *
4636  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4637  *
4638  */
4639 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4640 {
4641         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4642         int i;
4643         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4644
4645         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4646                 return false;
4647
4648         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4649                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4650                         ixgbe_cache_ring_fdir(adapter);
4651                 else
4652                         ixgbe_cache_ring_rss(adapter);
4653
4654                 fcoe_rx_i = f->mask;
4655                 fcoe_tx_i = f->mask;
4656         }
4657         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4658                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4659                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4660         }
4661         return true;
4662 }
4663
4664 #endif /* IXGBE_FCOE */
4665 /**
4666  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4667  * @adapter: board private structure to initialize
4668  *
4669  * SR-IOV doesn't use any descriptor rings but changes the default if
4670  * no other mapping is used.
4671  *
4672  */
4673 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4674 {
4675         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4676         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4677         if (adapter->num_vfs)
4678                 return true;
4679         else
4680                 return false;
4681 }
4682
4683 /**
4684  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4685  * @adapter: board private structure to initialize
4686  *
4687  * Once we know the feature-set enabled for the device, we'll cache
4688  * the register offset the descriptor ring is assigned to.
4689  *
4690  * Note, the order the various feature calls is important.  It must start with
4691  * the "most" features enabled at the same time, then trickle down to the
4692  * least amount of features turned on at once.
4693  **/
4694 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4695 {
4696         /* start with default case */
4697         adapter->rx_ring[0]->reg_idx = 0;
4698         adapter->tx_ring[0]->reg_idx = 0;
4699
4700         if (ixgbe_cache_ring_sriov(adapter))
4701                 return;
4702
4703 #ifdef CONFIG_IXGBE_DCB
4704         if (ixgbe_cache_ring_dcb(adapter))
4705                 return;
4706 #endif
4707
4708 #ifdef IXGBE_FCOE
4709         if (ixgbe_cache_ring_fcoe(adapter))
4710                 return;
4711 #endif /* IXGBE_FCOE */
4712
4713         if (ixgbe_cache_ring_fdir(adapter))
4714                 return;
4715
4716         if (ixgbe_cache_ring_rss(adapter))
4717                 return;
4718 }
4719
4720 /**
4721  * ixgbe_alloc_queues - Allocate memory for all rings
4722  * @adapter: board private structure to initialize
4723  *
4724  * We allocate one ring per queue at run-time since we don't know the
4725  * number of queues at compile-time.  The polling_netdev array is
4726  * intended for Multiqueue, but should work fine with a single queue.
4727  **/
4728 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4729 {
4730         int rx = 0, tx = 0, nid = adapter->node;
4731
4732         if (nid < 0 || !node_online(nid))
4733                 nid = first_online_node;
4734
4735         for (; tx < adapter->num_tx_queues; tx++) {
4736                 struct ixgbe_ring *ring;
4737
4738                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4739                 if (!ring)
4740                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4741                 if (!ring)
4742                         goto err_allocation;
4743                 ring->count = adapter->tx_ring_count;
4744                 ring->queue_index = tx;
4745                 ring->numa_node = nid;
4746                 ring->dev = &adapter->pdev->dev;
4747                 ring->netdev = adapter->netdev;
4748
4749                 adapter->tx_ring[tx] = ring;
4750         }
4751
4752         for (; rx < adapter->num_rx_queues; rx++) {
4753                 struct ixgbe_ring *ring;
4754
4755                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4756                 if (!ring)
4757                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4758                 if (!ring)
4759                         goto err_allocation;
4760                 ring->count = adapter->rx_ring_count;
4761                 ring->queue_index = rx;
4762                 ring->numa_node = nid;
4763                 ring->dev = &adapter->pdev->dev;
4764                 ring->netdev = adapter->netdev;
4765
4766                 adapter->rx_ring[rx] = ring;
4767         }
4768
4769         ixgbe_cache_ring_register(adapter);
4770
4771         return 0;
4772
4773 err_allocation:
4774         while (tx)
4775                 kfree(adapter->tx_ring[--tx]);
4776
4777         while (rx)
4778                 kfree(adapter->rx_ring[--rx]);
4779         return -ENOMEM;
4780 }
4781
4782 /**
4783  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4784  * @adapter: board private structure to initialize
4785  *
4786  * Attempt to configure the interrupts using the best available
4787  * capabilities of the hardware and the kernel.
4788  **/
4789 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4790 {
4791         struct ixgbe_hw *hw = &adapter->hw;
4792         int err = 0;
4793         int vector, v_budget;
4794
4795         /*
4796          * It's easy to be greedy for MSI-X vectors, but it really
4797          * doesn't do us much good if we have a lot more vectors
4798          * than CPU's.  So let's be conservative and only ask for
4799          * (roughly) the same number of vectors as there are CPU's.
4800          */
4801         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4802                        (int)num_online_cpus()) + NON_Q_VECTORS;
4803
4804         /*
4805          * At the same time, hardware can only support a maximum of
4806          * hw.mac->max_msix_vectors vectors.  With features
4807          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4808          * descriptor queues supported by our device.  Thus, we cap it off in
4809          * those rare cases where the cpu count also exceeds our vector limit.
4810          */
4811         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4812
4813         /* A failure in MSI-X entry allocation isn't fatal, but it does
4814          * mean we disable MSI-X capabilities of the adapter. */
4815         adapter->msix_entries = kcalloc(v_budget,
4816                                         sizeof(struct msix_entry), GFP_KERNEL);
4817         if (adapter->msix_entries) {
4818                 for (vector = 0; vector < v_budget; vector++)
4819                         adapter->msix_entries[vector].entry = vector;
4820
4821                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4822
4823                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4824                         goto out;
4825         }
4826
4827         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4828         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4829         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4830                 e_err(probe,
4831                       "ATR is not supported while multiple "
4832                       "queues are disabled.  Disabling Flow Director\n");
4833         }
4834         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4835         adapter->atr_sample_rate = 0;
4836         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4837                 ixgbe_disable_sriov(adapter);
4838
4839         err = ixgbe_set_num_queues(adapter);
4840         if (err)
4841                 return err;
4842
4843         err = pci_enable_msi(adapter->pdev);
4844         if (!err) {
4845                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4846         } else {
4847                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4848                              "Unable to allocate MSI interrupt, "
4849                              "falling back to legacy.  Error: %d\n", err);
4850                 /* reset err */
4851                 err = 0;
4852         }
4853
4854 out:
4855         return err;
4856 }
4857
4858 /**
4859  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4860  * @adapter: board private structure to initialize
4861  *
4862  * We allocate one q_vector per queue interrupt.  If allocation fails we
4863  * return -ENOMEM.
4864  **/
4865 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4866 {
4867         int q_idx, num_q_vectors;
4868         struct ixgbe_q_vector *q_vector;
4869         int (*poll)(struct napi_struct *, int);
4870
4871         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4872                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4873                 poll = &ixgbe_clean_rxtx_many;
4874         } else {
4875                 num_q_vectors = 1;
4876                 poll = &ixgbe_poll;
4877         }
4878
4879         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4880                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4881                                         GFP_KERNEL, adapter->node);
4882                 if (!q_vector)
4883                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4884                                            GFP_KERNEL);
4885                 if (!q_vector)
4886                         goto err_out;
4887                 q_vector->adapter = adapter;
4888                 if (q_vector->tx.count && !q_vector->rx.count)
4889                         q_vector->eitr = adapter->tx_eitr_param;
4890                 else
4891                         q_vector->eitr = adapter->rx_eitr_param;
4892                 q_vector->v_idx = q_idx;
4893                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4894                 adapter->q_vector[q_idx] = q_vector;
4895         }
4896
4897         return 0;
4898
4899 err_out:
4900         while (q_idx) {
4901                 q_idx--;
4902                 q_vector = adapter->q_vector[q_idx];
4903                 netif_napi_del(&q_vector->napi);
4904                 kfree(q_vector);
4905                 adapter->q_vector[q_idx] = NULL;
4906         }
4907         return -ENOMEM;
4908 }
4909
4910 /**
4911  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4912  * @adapter: board private structure to initialize
4913  *
4914  * This function frees the memory allocated to the q_vectors.  In addition if
4915  * NAPI is enabled it will delete any references to the NAPI struct prior
4916  * to freeing the q_vector.
4917  **/
4918 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4919 {
4920         int q_idx, num_q_vectors;
4921
4922         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4923                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4924         else
4925                 num_q_vectors = 1;
4926
4927         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4928                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4929                 adapter->q_vector[q_idx] = NULL;
4930                 netif_napi_del(&q_vector->napi);
4931                 kfree(q_vector);
4932         }
4933 }
4934
4935 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4936 {
4937         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4938                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4939                 pci_disable_msix(adapter->pdev);
4940                 kfree(adapter->msix_entries);
4941                 adapter->msix_entries = NULL;
4942         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4943                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4944                 pci_disable_msi(adapter->pdev);
4945         }
4946 }
4947
4948 /**
4949  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4950  * @adapter: board private structure to initialize
4951  *
4952  * We determine which interrupt scheme to use based on...
4953  * - Kernel support (MSI, MSI-X)
4954  *   - which can be user-defined (via MODULE_PARAM)
4955  * - Hardware queue count (num_*_queues)
4956  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4957  **/
4958 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4959 {
4960         int err;
4961
4962         /* Number of supported queues */
4963         err = ixgbe_set_num_queues(adapter);
4964         if (err)
4965                 return err;
4966
4967         err = ixgbe_set_interrupt_capability(adapter);
4968         if (err) {
4969                 e_dev_err("Unable to setup interrupt capabilities\n");
4970                 goto err_set_interrupt;
4971         }
4972
4973         err = ixgbe_alloc_q_vectors(adapter);
4974         if (err) {
4975                 e_dev_err("Unable to allocate memory for queue vectors\n");
4976                 goto err_alloc_q_vectors;
4977         }
4978
4979         err = ixgbe_alloc_queues(adapter);
4980         if (err) {
4981                 e_dev_err("Unable to allocate memory for queues\n");
4982                 goto err_alloc_queues;
4983         }
4984
4985         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4986                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4987                    adapter->num_rx_queues, adapter->num_tx_queues);
4988
4989         set_bit(__IXGBE_DOWN, &adapter->state);
4990
4991         return 0;
4992
4993 err_alloc_queues:
4994         ixgbe_free_q_vectors(adapter);
4995 err_alloc_q_vectors:
4996         ixgbe_reset_interrupt_capability(adapter);
4997 err_set_interrupt:
4998         return err;
4999 }
5000
5001 /**
5002  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5003  * @adapter: board private structure to clear interrupt scheme on
5004  *
5005  * We go through and clear interrupt specific resources and reset the structure
5006  * to pre-load conditions
5007  **/
5008 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5009 {
5010         int i;
5011
5012         for (i = 0; i < adapter->num_tx_queues; i++) {
5013                 kfree(adapter->tx_ring[i]);
5014                 adapter->tx_ring[i] = NULL;
5015         }
5016         for (i = 0; i < adapter->num_rx_queues; i++) {
5017                 struct ixgbe_ring *ring = adapter->rx_ring[i];
5018
5019                 /* ixgbe_get_stats64() might access this ring, we must wait
5020                  * a grace period before freeing it.
5021                  */
5022                 kfree_rcu(ring, rcu);
5023                 adapter->rx_ring[i] = NULL;
5024         }
5025
5026         adapter->num_tx_queues = 0;
5027         adapter->num_rx_queues = 0;
5028
5029         ixgbe_free_q_vectors(adapter);
5030         ixgbe_reset_interrupt_capability(adapter);
5031 }
5032
5033 /**
5034  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5035  * @adapter: board private structure to initialize
5036  *
5037  * ixgbe_sw_init initializes the Adapter private data structure.
5038  * Fields are initialized based on PCI device information and
5039  * OS network device settings (MTU size).
5040  **/
5041 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5042 {
5043         struct ixgbe_hw *hw = &adapter->hw;
5044         struct pci_dev *pdev = adapter->pdev;
5045         struct net_device *dev = adapter->netdev;
5046         unsigned int rss;
5047 #ifdef CONFIG_IXGBE_DCB
5048         int j;
5049         struct tc_configuration *tc;
5050 #endif
5051         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5052
5053         /* PCI config space info */
5054
5055         hw->vendor_id = pdev->vendor;
5056         hw->device_id = pdev->device;
5057         hw->revision_id = pdev->revision;
5058         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5059         hw->subsystem_device_id = pdev->subsystem_device;
5060
5061         /* Set capability flags */
5062         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5063         adapter->ring_feature[RING_F_RSS].indices = rss;
5064         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5065         switch (hw->mac.type) {
5066         case ixgbe_mac_82598EB:
5067                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5068                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5069                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5070                 break;
5071         case ixgbe_mac_82599EB:
5072         case ixgbe_mac_X540:
5073                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5074                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5075                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5076                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5077                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5078                 /* Flow Director hash filters enabled */
5079                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5080                 adapter->atr_sample_rate = 20;
5081                 adapter->ring_feature[RING_F_FDIR].indices =
5082                                                          IXGBE_MAX_FDIR_INDICES;
5083                 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5084 #ifdef IXGBE_FCOE
5085                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5086                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5087                 adapter->ring_feature[RING_F_FCOE].indices = 0;
5088 #ifdef CONFIG_IXGBE_DCB
5089                 /* Default traffic class to use for FCoE */
5090                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5091 #endif
5092 #endif /* IXGBE_FCOE */
5093                 break;
5094         default:
5095                 break;
5096         }
5097
5098         /* n-tuple support exists, always init our spinlock */
5099         spin_lock_init(&adapter->fdir_perfect_lock);
5100
5101 #ifdef CONFIG_IXGBE_DCB
5102         /* Configure DCB traffic classes */
5103         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5104                 tc = &adapter->dcb_cfg.tc_config[j];
5105                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5106                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5107                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5108                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5109                 tc->dcb_pfc = pfc_disabled;
5110         }
5111         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5112         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5113         adapter->dcb_cfg.pfc_mode_enable = false;
5114         adapter->dcb_set_bitmap = 0x00;
5115         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5116         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5117                            MAX_TRAFFIC_CLASS);
5118
5119 #endif
5120
5121         /* default flow control settings */
5122         hw->fc.requested_mode = ixgbe_fc_full;
5123         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5124 #ifdef CONFIG_DCB
5125         adapter->last_lfc_mode = hw->fc.current_mode;
5126 #endif
5127         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5128         hw->fc.low_water = FC_LOW_WATER(max_frame);
5129         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5130         hw->fc.send_xon = true;
5131         hw->fc.disable_fc_autoneg = false;
5132
5133         /* enable itr by default in dynamic mode */
5134         adapter->rx_itr_setting = 1;
5135         adapter->rx_eitr_param = 20000;
5136         adapter->tx_itr_setting = 1;
5137         adapter->tx_eitr_param = 10000;
5138
5139         /* set defaults for eitr in MegaBytes */
5140         adapter->eitr_low = 10;
5141         adapter->eitr_high = 20;
5142
5143         /* set default ring sizes */
5144         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5145         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5146
5147         /* set default work limits */
5148         adapter->tx_work_limit = adapter->tx_ring_count;
5149
5150         /* initialize eeprom parameters */
5151         if (ixgbe_init_eeprom_params_generic(hw)) {
5152                 e_dev_err("EEPROM initialization failed\n");
5153                 return -EIO;
5154         }
5155
5156         /* enable rx csum by default */
5157         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5158
5159         /* get assigned NUMA node */
5160         adapter->node = dev_to_node(&pdev->dev);
5161
5162         set_bit(__IXGBE_DOWN, &adapter->state);
5163
5164         return 0;
5165 }
5166
5167 /**
5168  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5169  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5170  *
5171  * Return 0 on success, negative on failure
5172  **/
5173 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5174 {
5175         struct device *dev = tx_ring->dev;
5176         int size;
5177
5178         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5179         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5180         if (!tx_ring->tx_buffer_info)
5181                 tx_ring->tx_buffer_info = vzalloc(size);
5182         if (!tx_ring->tx_buffer_info)
5183                 goto err;
5184
5185         /* round up to nearest 4K */
5186         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5187         tx_ring->size = ALIGN(tx_ring->size, 4096);
5188
5189         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5190                                            &tx_ring->dma, GFP_KERNEL);
5191         if (!tx_ring->desc)
5192                 goto err;
5193
5194         tx_ring->next_to_use = 0;
5195         tx_ring->next_to_clean = 0;
5196         return 0;
5197
5198 err:
5199         vfree(tx_ring->tx_buffer_info);
5200         tx_ring->tx_buffer_info = NULL;
5201         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5202         return -ENOMEM;
5203 }
5204
5205 /**
5206  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5207  * @adapter: board private structure
5208  *
5209  * If this function returns with an error, then it's possible one or
5210  * more of the rings is populated (while the rest are not).  It is the
5211  * callers duty to clean those orphaned rings.
5212  *
5213  * Return 0 on success, negative on failure
5214  **/
5215 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5216 {
5217         int i, err = 0;
5218
5219         for (i = 0; i < adapter->num_tx_queues; i++) {
5220                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5221                 if (!err)
5222                         continue;
5223                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5224                 break;
5225         }
5226
5227         return err;
5228 }
5229
5230 /**
5231  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5232  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5233  *
5234  * Returns 0 on success, negative on failure
5235  **/
5236 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5237 {
5238         struct device *dev = rx_ring->dev;
5239         int size;
5240
5241         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5242         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5243         if (!rx_ring->rx_buffer_info)
5244                 rx_ring->rx_buffer_info = vzalloc(size);
5245         if (!rx_ring->rx_buffer_info)
5246                 goto err;
5247
5248         /* Round up to nearest 4K */
5249         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5250         rx_ring->size = ALIGN(rx_ring->size, 4096);
5251
5252         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5253                                            &rx_ring->dma, GFP_KERNEL);
5254
5255         if (!rx_ring->desc)
5256                 goto err;
5257
5258         rx_ring->next_to_clean = 0;
5259         rx_ring->next_to_use = 0;
5260
5261         return 0;
5262 err:
5263         vfree(rx_ring->rx_buffer_info);
5264         rx_ring->rx_buffer_info = NULL;
5265         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5266         return -ENOMEM;
5267 }
5268
5269 /**
5270  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5271  * @adapter: board private structure
5272  *
5273  * If this function returns with an error, then it's possible one or
5274  * more of the rings is populated (while the rest are not).  It is the
5275  * callers duty to clean those orphaned rings.
5276  *
5277  * Return 0 on success, negative on failure
5278  **/
5279 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5280 {
5281         int i, err = 0;
5282
5283         for (i = 0; i < adapter->num_rx_queues; i++) {
5284                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5285                 if (!err)
5286                         continue;
5287                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5288                 break;
5289         }
5290
5291         return err;
5292 }
5293
5294 /**
5295  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5296  * @tx_ring: Tx descriptor ring for a specific queue
5297  *
5298  * Free all transmit software resources
5299  **/
5300 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5301 {
5302         ixgbe_clean_tx_ring(tx_ring);
5303
5304         vfree(tx_ring->tx_buffer_info);
5305         tx_ring->tx_buffer_info = NULL;
5306
5307         /* if not set, then don't free */
5308         if (!tx_ring->desc)
5309                 return;
5310
5311         dma_free_coherent(tx_ring->dev, tx_ring->size,
5312                           tx_ring->desc, tx_ring->dma);
5313
5314         tx_ring->desc = NULL;
5315 }
5316
5317 /**
5318  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5319  * @adapter: board private structure
5320  *
5321  * Free all transmit software resources
5322  **/
5323 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5324 {
5325         int i;
5326
5327         for (i = 0; i < adapter->num_tx_queues; i++)
5328                 if (adapter->tx_ring[i]->desc)
5329                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5330 }
5331
5332 /**
5333  * ixgbe_free_rx_resources - Free Rx Resources
5334  * @rx_ring: ring to clean the resources from
5335  *
5336  * Free all receive software resources
5337  **/
5338 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5339 {
5340         ixgbe_clean_rx_ring(rx_ring);
5341
5342         vfree(rx_ring->rx_buffer_info);
5343         rx_ring->rx_buffer_info = NULL;
5344
5345         /* if not set, then don't free */
5346         if (!rx_ring->desc)
5347                 return;
5348
5349         dma_free_coherent(rx_ring->dev, rx_ring->size,
5350                           rx_ring->desc, rx_ring->dma);
5351
5352         rx_ring->desc = NULL;
5353 }
5354
5355 /**
5356  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5357  * @adapter: board private structure
5358  *
5359  * Free all receive software resources
5360  **/
5361 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5362 {
5363         int i;
5364
5365         for (i = 0; i < adapter->num_rx_queues; i++)
5366                 if (adapter->rx_ring[i]->desc)
5367                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5368 }
5369
5370 /**
5371  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5372  * @netdev: network interface device structure
5373  * @new_mtu: new value for maximum frame size
5374  *
5375  * Returns 0 on success, negative on failure
5376  **/
5377 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5378 {
5379         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5380         struct ixgbe_hw *hw = &adapter->hw;
5381         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5382
5383         /* MTU < 68 is an error and causes problems on some kernels */
5384         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5385             hw->mac.type != ixgbe_mac_X540) {
5386                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5387                         return -EINVAL;
5388         } else {
5389                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5390                         return -EINVAL;
5391         }
5392
5393         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5394         /* must set new MTU before calling down or up */
5395         netdev->mtu = new_mtu;
5396
5397         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5398         hw->fc.low_water = FC_LOW_WATER(max_frame);
5399
5400         if (netif_running(netdev))
5401                 ixgbe_reinit_locked(adapter);
5402
5403         return 0;
5404 }
5405
5406 /**
5407  * ixgbe_open - Called when a network interface is made active
5408  * @netdev: network interface device structure
5409  *
5410  * Returns 0 on success, negative value on failure
5411  *
5412  * The open entry point is called when a network interface is made
5413  * active by the system (IFF_UP).  At this point all resources needed
5414  * for transmit and receive operations are allocated, the interrupt
5415  * handler is registered with the OS, the watchdog timer is started,
5416  * and the stack is notified that the interface is ready.
5417  **/
5418 static int ixgbe_open(struct net_device *netdev)
5419 {
5420         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5421         int err;
5422
5423         /* disallow open during test */
5424         if (test_bit(__IXGBE_TESTING, &adapter->state))
5425                 return -EBUSY;
5426
5427         netif_carrier_off(netdev);
5428
5429         /* allocate transmit descriptors */
5430         err = ixgbe_setup_all_tx_resources(adapter);
5431         if (err)
5432                 goto err_setup_tx;
5433
5434         /* allocate receive descriptors */
5435         err = ixgbe_setup_all_rx_resources(adapter);
5436         if (err)
5437                 goto err_setup_rx;
5438
5439         ixgbe_configure(adapter);
5440
5441         err = ixgbe_request_irq(adapter);
5442         if (err)
5443                 goto err_req_irq;
5444
5445         err = ixgbe_up_complete(adapter);
5446         if (err)
5447                 goto err_up;
5448
5449         netif_tx_start_all_queues(netdev);
5450
5451         return 0;
5452
5453 err_up:
5454         ixgbe_release_hw_control(adapter);
5455         ixgbe_free_irq(adapter);
5456 err_req_irq:
5457 err_setup_rx:
5458         ixgbe_free_all_rx_resources(adapter);
5459 err_setup_tx:
5460         ixgbe_free_all_tx_resources(adapter);
5461         ixgbe_reset(adapter);
5462
5463         return err;
5464 }
5465
5466 /**
5467  * ixgbe_close - Disables a network interface
5468  * @netdev: network interface device structure
5469  *
5470  * Returns 0, this is not allowed to fail
5471  *
5472  * The close entry point is called when an interface is de-activated
5473  * by the OS.  The hardware is still under the drivers control, but
5474  * needs to be disabled.  A global MAC reset is issued to stop the
5475  * hardware, and all transmit and receive resources are freed.
5476  **/
5477 static int ixgbe_close(struct net_device *netdev)
5478 {
5479         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5480
5481         ixgbe_down(adapter);
5482         ixgbe_free_irq(adapter);
5483
5484         ixgbe_fdir_filter_exit(adapter);
5485
5486         ixgbe_free_all_tx_resources(adapter);
5487         ixgbe_free_all_rx_resources(adapter);
5488
5489         ixgbe_release_hw_control(adapter);
5490
5491         return 0;
5492 }
5493
5494 #ifdef CONFIG_PM
5495 static int ixgbe_resume(struct pci_dev *pdev)
5496 {
5497         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5498         struct net_device *netdev = adapter->netdev;
5499         u32 err;
5500
5501         pci_set_power_state(pdev, PCI_D0);
5502         pci_restore_state(pdev);
5503         /*
5504          * pci_restore_state clears dev->state_saved so call
5505          * pci_save_state to restore it.
5506          */
5507         pci_save_state(pdev);
5508
5509         err = pci_enable_device_mem(pdev);
5510         if (err) {
5511                 e_dev_err("Cannot enable PCI device from suspend\n");
5512                 return err;
5513         }
5514         pci_set_master(pdev);
5515
5516         pci_wake_from_d3(pdev, false);
5517
5518         err = ixgbe_init_interrupt_scheme(adapter);
5519         if (err) {
5520                 e_dev_err("Cannot initialize interrupts for device\n");
5521                 return err;
5522         }
5523
5524         ixgbe_reset(adapter);
5525
5526         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5527
5528         if (netif_running(netdev)) {
5529                 err = ixgbe_open(netdev);
5530                 if (err)
5531                         return err;
5532         }
5533
5534         netif_device_attach(netdev);
5535
5536         return 0;
5537 }
5538 #endif /* CONFIG_PM */
5539
5540 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5541 {
5542         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5543         struct net_device *netdev = adapter->netdev;
5544         struct ixgbe_hw *hw = &adapter->hw;
5545         u32 ctrl, fctrl;
5546         u32 wufc = adapter->wol;
5547 #ifdef CONFIG_PM
5548         int retval = 0;
5549 #endif
5550
5551         netif_device_detach(netdev);
5552
5553         if (netif_running(netdev)) {
5554                 ixgbe_down(adapter);
5555                 ixgbe_free_irq(adapter);
5556                 ixgbe_free_all_tx_resources(adapter);
5557                 ixgbe_free_all_rx_resources(adapter);
5558         }
5559
5560         ixgbe_clear_interrupt_scheme(adapter);
5561 #ifdef CONFIG_DCB
5562         kfree(adapter->ixgbe_ieee_pfc);
5563         kfree(adapter->ixgbe_ieee_ets);
5564 #endif
5565
5566 #ifdef CONFIG_PM
5567         retval = pci_save_state(pdev);
5568         if (retval)
5569                 return retval;
5570
5571 #endif
5572         if (wufc) {
5573                 ixgbe_set_rx_mode(netdev);
5574
5575                 /* turn on all-multi mode if wake on multicast is enabled */
5576                 if (wufc & IXGBE_WUFC_MC) {
5577                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5578                         fctrl |= IXGBE_FCTRL_MPE;
5579                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5580                 }
5581
5582                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5583                 ctrl |= IXGBE_CTRL_GIO_DIS;
5584                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5585
5586                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5587         } else {
5588                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5589                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5590         }
5591
5592         switch (hw->mac.type) {
5593         case ixgbe_mac_82598EB:
5594                 pci_wake_from_d3(pdev, false);
5595                 break;
5596         case ixgbe_mac_82599EB:
5597         case ixgbe_mac_X540:
5598                 pci_wake_from_d3(pdev, !!wufc);
5599                 break;
5600         default:
5601                 break;
5602         }
5603
5604         *enable_wake = !!wufc;
5605
5606         ixgbe_release_hw_control(adapter);
5607
5608         pci_disable_device(pdev);
5609
5610         return 0;
5611 }
5612
5613 #ifdef CONFIG_PM
5614 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5615 {
5616         int retval;
5617         bool wake;
5618
5619         retval = __ixgbe_shutdown(pdev, &wake);
5620         if (retval)
5621                 return retval;
5622
5623         if (wake) {
5624                 pci_prepare_to_sleep(pdev);
5625         } else {
5626                 pci_wake_from_d3(pdev, false);
5627                 pci_set_power_state(pdev, PCI_D3hot);
5628         }
5629
5630         return 0;
5631 }
5632 #endif /* CONFIG_PM */
5633
5634 static void ixgbe_shutdown(struct pci_dev *pdev)
5635 {
5636         bool wake;
5637
5638         __ixgbe_shutdown(pdev, &wake);
5639
5640         if (system_state == SYSTEM_POWER_OFF) {
5641                 pci_wake_from_d3(pdev, wake);
5642                 pci_set_power_state(pdev, PCI_D3hot);
5643         }
5644 }
5645
5646 /**
5647  * ixgbe_update_stats - Update the board statistics counters.
5648  * @adapter: board private structure
5649  **/
5650 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5651 {
5652         struct net_device *netdev = adapter->netdev;
5653         struct ixgbe_hw *hw = &adapter->hw;
5654         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5655         u64 total_mpc = 0;
5656         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5657         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5658         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5659         u64 bytes = 0, packets = 0;
5660
5661         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5662             test_bit(__IXGBE_RESETTING, &adapter->state))
5663                 return;
5664
5665         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5666                 u64 rsc_count = 0;
5667                 u64 rsc_flush = 0;
5668                 for (i = 0; i < 16; i++)
5669                         adapter->hw_rx_no_dma_resources +=
5670                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5671                 for (i = 0; i < adapter->num_rx_queues; i++) {
5672                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5673                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5674                 }
5675                 adapter->rsc_total_count = rsc_count;
5676                 adapter->rsc_total_flush = rsc_flush;
5677         }
5678
5679         for (i = 0; i < adapter->num_rx_queues; i++) {
5680                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5681                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5682                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5683                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5684                 bytes += rx_ring->stats.bytes;
5685                 packets += rx_ring->stats.packets;
5686         }
5687         adapter->non_eop_descs = non_eop_descs;
5688         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5689         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5690         netdev->stats.rx_bytes = bytes;
5691         netdev->stats.rx_packets = packets;
5692
5693         bytes = 0;
5694         packets = 0;
5695         /* gather some stats to the adapter struct that are per queue */
5696         for (i = 0; i < adapter->num_tx_queues; i++) {
5697                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5698                 restart_queue += tx_ring->tx_stats.restart_queue;
5699                 tx_busy += tx_ring->tx_stats.tx_busy;
5700                 bytes += tx_ring->stats.bytes;
5701                 packets += tx_ring->stats.packets;
5702         }
5703         adapter->restart_queue = restart_queue;
5704         adapter->tx_busy = tx_busy;
5705         netdev->stats.tx_bytes = bytes;
5706         netdev->stats.tx_packets = packets;
5707
5708         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5709         for (i = 0; i < 8; i++) {
5710                 /* for packet buffers not used, the register should read 0 */
5711                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5712                 missed_rx += mpc;
5713                 hwstats->mpc[i] += mpc;
5714                 total_mpc += hwstats->mpc[i];
5715                 if (hw->mac.type == ixgbe_mac_82598EB)
5716                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5717                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5718                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5719                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5720                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5721                 switch (hw->mac.type) {
5722                 case ixgbe_mac_82598EB:
5723                         hwstats->pxonrxc[i] +=
5724                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5725                         break;
5726                 case ixgbe_mac_82599EB:
5727                 case ixgbe_mac_X540:
5728                         hwstats->pxonrxc[i] +=
5729                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5730                         break;
5731                 default:
5732                         break;
5733                 }
5734                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5735                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5736         }
5737         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5738         /* work around hardware counting issue */
5739         hwstats->gprc -= missed_rx;
5740
5741         ixgbe_update_xoff_received(adapter);
5742
5743         /* 82598 hardware only has a 32 bit counter in the high register */
5744         switch (hw->mac.type) {
5745         case ixgbe_mac_82598EB:
5746                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5747                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5748                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5749                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5750                 break;
5751         case ixgbe_mac_X540:
5752                 /* OS2BMC stats are X540 only*/
5753                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5754                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5755                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5756                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5757         case ixgbe_mac_82599EB:
5758                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5759                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5760                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5761                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5762                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5763                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5764                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5765                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5766                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5767 #ifdef IXGBE_FCOE
5768                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5769                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5770                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5771                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5772                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5773                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5774 #endif /* IXGBE_FCOE */
5775                 break;
5776         default:
5777                 break;
5778         }
5779         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5780         hwstats->bprc += bprc;
5781         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5782         if (hw->mac.type == ixgbe_mac_82598EB)
5783                 hwstats->mprc -= bprc;
5784         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5785         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5786         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5787         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5788         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5789         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5790         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5791         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5792         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5793         hwstats->lxontxc += lxon;
5794         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5795         hwstats->lxofftxc += lxoff;
5796         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5797         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5798         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5799         /*
5800          * 82598 errata - tx of flow control packets is included in tx counters
5801          */
5802         xon_off_tot = lxon + lxoff;
5803         hwstats->gptc -= xon_off_tot;
5804         hwstats->mptc -= xon_off_tot;
5805         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5806         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5807         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5808         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5809         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5810         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5811         hwstats->ptc64 -= xon_off_tot;
5812         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5813         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5814         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5815         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5816         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5817         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5818
5819         /* Fill out the OS statistics structure */
5820         netdev->stats.multicast = hwstats->mprc;
5821
5822         /* Rx Errors */
5823         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5824         netdev->stats.rx_dropped = 0;
5825         netdev->stats.rx_length_errors = hwstats->rlec;
5826         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5827         netdev->stats.rx_missed_errors = total_mpc;
5828 }
5829
5830 /**
5831  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5832  * @adapter - pointer to the device adapter structure
5833  **/
5834 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5835 {
5836         struct ixgbe_hw *hw = &adapter->hw;
5837         int i;
5838
5839         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5840                 return;
5841
5842         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5843
5844         /* if interface is down do nothing */
5845         if (test_bit(__IXGBE_DOWN, &adapter->state))
5846                 return;
5847
5848         /* do nothing if we are not using signature filters */
5849         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5850                 return;
5851
5852         adapter->fdir_overflow++;
5853
5854         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5855                 for (i = 0; i < adapter->num_tx_queues; i++)
5856                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5857                                 &(adapter->tx_ring[i]->state));
5858                 /* re-enable flow director interrupts */
5859                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5860         } else {
5861                 e_err(probe, "failed to finish FDIR re-initialization, "
5862                       "ignored adding FDIR ATR filters\n");
5863         }
5864 }
5865
5866 /**
5867  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5868  * @adapter - pointer to the device adapter structure
5869  *
5870  * This function serves two purposes.  First it strobes the interrupt lines
5871  * in order to make certain interrupts are occuring.  Secondly it sets the
5872  * bits needed to check for TX hangs.  As a result we should immediately
5873  * determine if a hang has occured.
5874  */
5875 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5876 {
5877         struct ixgbe_hw *hw = &adapter->hw;
5878         u64 eics = 0;
5879         int i;
5880
5881         /* If we're down or resetting, just bail */
5882         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5883             test_bit(__IXGBE_RESETTING, &adapter->state))
5884                 return;
5885
5886         /* Force detection of hung controller */
5887         if (netif_carrier_ok(adapter->netdev)) {
5888                 for (i = 0; i < adapter->num_tx_queues; i++)
5889                         set_check_for_tx_hang(adapter->tx_ring[i]);
5890         }
5891
5892         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5893                 /*
5894                  * for legacy and MSI interrupts don't set any bits
5895                  * that are enabled for EIAM, because this operation
5896                  * would set *both* EIMS and EICS for any bit in EIAM
5897                  */
5898                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5899                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5900         } else {
5901                 /* get one bit for every active tx/rx interrupt vector */
5902                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5903                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
5904                         if (qv->rx.count || qv->tx.count)
5905                                 eics |= ((u64)1 << i);
5906                 }
5907         }
5908
5909         /* Cause software interrupt to ensure rings are cleaned */
5910         ixgbe_irq_rearm_queues(adapter, eics);
5911
5912 }
5913
5914 /**
5915  * ixgbe_watchdog_update_link - update the link status
5916  * @adapter - pointer to the device adapter structure
5917  * @link_speed - pointer to a u32 to store the link_speed
5918  **/
5919 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5920 {
5921         struct ixgbe_hw *hw = &adapter->hw;
5922         u32 link_speed = adapter->link_speed;
5923         bool link_up = adapter->link_up;
5924         int i;
5925
5926         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5927                 return;
5928
5929         if (hw->mac.ops.check_link) {
5930                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5931         } else {
5932                 /* always assume link is up, if no check link function */
5933                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5934                 link_up = true;
5935         }
5936         if (link_up) {
5937                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5938                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5939                                 hw->mac.ops.fc_enable(hw, i);
5940                 } else {
5941                         hw->mac.ops.fc_enable(hw, 0);
5942                 }
5943         }
5944
5945         if (link_up ||
5946             time_after(jiffies, (adapter->link_check_timeout +
5947                                  IXGBE_TRY_LINK_TIMEOUT))) {
5948                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5949                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5950                 IXGBE_WRITE_FLUSH(hw);
5951         }
5952
5953         adapter->link_up = link_up;
5954         adapter->link_speed = link_speed;
5955 }
5956
5957 /**
5958  * ixgbe_watchdog_link_is_up - update netif_carrier status and
5959  *                             print link up message
5960  * @adapter - pointer to the device adapter structure
5961  **/
5962 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5963 {
5964         struct net_device *netdev = adapter->netdev;
5965         struct ixgbe_hw *hw = &adapter->hw;
5966         u32 link_speed = adapter->link_speed;
5967         bool flow_rx, flow_tx;
5968
5969         /* only continue if link was previously down */
5970         if (netif_carrier_ok(netdev))
5971                 return;
5972
5973         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5974
5975         switch (hw->mac.type) {
5976         case ixgbe_mac_82598EB: {
5977                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5978                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5979                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5980                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5981         }
5982                 break;
5983         case ixgbe_mac_X540:
5984         case ixgbe_mac_82599EB: {
5985                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5986                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5987                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5988                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5989         }
5990                 break;
5991         default:
5992                 flow_tx = false;
5993                 flow_rx = false;
5994                 break;
5995         }
5996         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5997                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5998                "10 Gbps" :
5999                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6000                "1 Gbps" :
6001                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6002                "100 Mbps" :
6003                "unknown speed"))),
6004                ((flow_rx && flow_tx) ? "RX/TX" :
6005                (flow_rx ? "RX" :
6006                (flow_tx ? "TX" : "None"))));
6007
6008         netif_carrier_on(netdev);
6009         ixgbe_check_vf_rate_limit(adapter);
6010 }
6011
6012 /**
6013  * ixgbe_watchdog_link_is_down - update netif_carrier status and
6014  *                               print link down message
6015  * @adapter - pointer to the adapter structure
6016  **/
6017 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6018 {
6019         struct net_device *netdev = adapter->netdev;
6020         struct ixgbe_hw *hw = &adapter->hw;
6021
6022         adapter->link_up = false;
6023         adapter->link_speed = 0;
6024
6025         /* only continue if link was up previously */
6026         if (!netif_carrier_ok(netdev))
6027                 return;
6028
6029         /* poll for SFP+ cable when link is down */
6030         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6031                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6032
6033         e_info(drv, "NIC Link is Down\n");
6034         netif_carrier_off(netdev);
6035 }
6036
6037 /**
6038  * ixgbe_watchdog_flush_tx - flush queues on link down
6039  * @adapter - pointer to the device adapter structure
6040  **/
6041 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6042 {
6043         int i;
6044         int some_tx_pending = 0;
6045
6046         if (!netif_carrier_ok(adapter->netdev)) {
6047                 for (i = 0; i < adapter->num_tx_queues; i++) {
6048                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6049                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6050                                 some_tx_pending = 1;
6051                                 break;
6052                         }
6053                 }
6054
6055                 if (some_tx_pending) {
6056                         /* We've lost link, so the controller stops DMA,
6057                          * but we've got queued Tx work that's never going
6058                          * to get done, so reset controller to flush Tx.
6059                          * (Do the reset outside of interrupt context).
6060                          */
6061                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6062                 }
6063         }
6064 }
6065
6066 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6067 {
6068         u32 ssvpc;
6069
6070         /* Do not perform spoof check for 82598 */
6071         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6072                 return;
6073
6074         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6075
6076         /*
6077          * ssvpc register is cleared on read, if zero then no
6078          * spoofed packets in the last interval.
6079          */
6080         if (!ssvpc)
6081                 return;
6082
6083         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6084 }
6085
6086 /**
6087  * ixgbe_watchdog_subtask - check and bring link up
6088  * @adapter - pointer to the device adapter structure
6089  **/
6090 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6091 {
6092         /* if interface is down do nothing */
6093         if (test_bit(__IXGBE_DOWN, &adapter->state))
6094                 return;
6095
6096         ixgbe_watchdog_update_link(adapter);
6097
6098         if (adapter->link_up)
6099                 ixgbe_watchdog_link_is_up(adapter);
6100         else
6101                 ixgbe_watchdog_link_is_down(adapter);
6102
6103         ixgbe_spoof_check(adapter);
6104         ixgbe_update_stats(adapter);
6105
6106         ixgbe_watchdog_flush_tx(adapter);
6107 }
6108
6109 /**
6110  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6111  * @adapter - the ixgbe adapter structure
6112  **/
6113 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6114 {
6115         struct ixgbe_hw *hw = &adapter->hw;
6116         s32 err;
6117
6118         /* not searching for SFP so there is nothing to do here */
6119         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6120             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6121                 return;
6122
6123         /* someone else is in init, wait until next service event */
6124         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6125                 return;
6126
6127         err = hw->phy.ops.identify_sfp(hw);
6128         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6129                 goto sfp_out;
6130
6131         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6132                 /* If no cable is present, then we need to reset
6133                  * the next time we find a good cable. */
6134                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6135         }
6136
6137         /* exit on error */
6138         if (err)
6139                 goto sfp_out;
6140
6141         /* exit if reset not needed */
6142         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6143                 goto sfp_out;
6144
6145         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6146
6147         /*
6148          * A module may be identified correctly, but the EEPROM may not have
6149          * support for that module.  setup_sfp() will fail in that case, so
6150          * we should not allow that module to load.
6151          */
6152         if (hw->mac.type == ixgbe_mac_82598EB)
6153                 err = hw->phy.ops.reset(hw);
6154         else
6155                 err = hw->mac.ops.setup_sfp(hw);
6156
6157         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6158                 goto sfp_out;
6159
6160         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6161         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6162
6163 sfp_out:
6164         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6165
6166         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6167             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6168                 e_dev_err("failed to initialize because an unsupported "
6169                           "SFP+ module type was detected.\n");
6170                 e_dev_err("Reload the driver after installing a "
6171                           "supported module.\n");
6172                 unregister_netdev(adapter->netdev);
6173         }
6174 }
6175
6176 /**
6177  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6178  * @adapter - the ixgbe adapter structure
6179  **/
6180 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6181 {
6182         struct ixgbe_hw *hw = &adapter->hw;
6183         u32 autoneg;
6184         bool negotiation;
6185
6186         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6187                 return;
6188
6189         /* someone else is in init, wait until next service event */
6190         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6191                 return;
6192
6193         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6194
6195         autoneg = hw->phy.autoneg_advertised;
6196         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6197                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6198         hw->mac.autotry_restart = false;
6199         if (hw->mac.ops.setup_link)
6200                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6201
6202         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6203         adapter->link_check_timeout = jiffies;
6204         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6205 }
6206
6207 /**
6208  * ixgbe_service_timer - Timer Call-back
6209  * @data: pointer to adapter cast into an unsigned long
6210  **/
6211 static void ixgbe_service_timer(unsigned long data)
6212 {
6213         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6214         unsigned long next_event_offset;
6215
6216         /* poll faster when waiting for link */
6217         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6218                 next_event_offset = HZ / 10;
6219         else
6220                 next_event_offset = HZ * 2;
6221
6222         /* Reset the timer */
6223         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6224
6225         ixgbe_service_event_schedule(adapter);
6226 }
6227
6228 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6229 {
6230         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6231                 return;
6232
6233         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6234
6235         /* If we're already down or resetting, just bail */
6236         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6237             test_bit(__IXGBE_RESETTING, &adapter->state))
6238                 return;
6239
6240         ixgbe_dump(adapter);
6241         netdev_err(adapter->netdev, "Reset adapter\n");
6242         adapter->tx_timeout_count++;
6243
6244         ixgbe_reinit_locked(adapter);
6245 }
6246
6247 /**
6248  * ixgbe_service_task - manages and runs subtasks
6249  * @work: pointer to work_struct containing our data
6250  **/
6251 static void ixgbe_service_task(struct work_struct *work)
6252 {
6253         struct ixgbe_adapter *adapter = container_of(work,
6254                                                      struct ixgbe_adapter,
6255                                                      service_task);
6256
6257         ixgbe_reset_subtask(adapter);
6258         ixgbe_sfp_detection_subtask(adapter);
6259         ixgbe_sfp_link_config_subtask(adapter);
6260         ixgbe_check_overtemp_subtask(adapter);
6261         ixgbe_watchdog_subtask(adapter);
6262         ixgbe_fdir_reinit_subtask(adapter);
6263         ixgbe_check_hang_subtask(adapter);
6264
6265         ixgbe_service_event_complete(adapter);
6266 }
6267
6268 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6269                        u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6270 {
6271         struct ixgbe_adv_tx_context_desc *context_desc;
6272         u16 i = tx_ring->next_to_use;
6273
6274         context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6275
6276         i++;
6277         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6278
6279         /* set bits to identify this as an advanced context descriptor */
6280         type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6281
6282         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
6283         context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
6284         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
6285         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
6286 }
6287
6288 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6289                      u32 tx_flags, __be16 protocol, u8 *hdr_len)
6290 {
6291         int err;
6292         u32 vlan_macip_lens, type_tucmd;
6293         u32 mss_l4len_idx, l4len;
6294
6295         if (!skb_is_gso(skb))
6296                 return 0;
6297
6298         if (skb_header_cloned(skb)) {
6299                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6300                 if (err)
6301                         return err;
6302         }
6303
6304         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6305         type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6306
6307         if (protocol == __constant_htons(ETH_P_IP)) {
6308                 struct iphdr *iph = ip_hdr(skb);
6309                 iph->tot_len = 0;
6310                 iph->check = 0;
6311                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6312                                                          iph->daddr, 0,
6313                                                          IPPROTO_TCP,
6314                                                          0);
6315                 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6316         } else if (skb_is_gso_v6(skb)) {
6317                 ipv6_hdr(skb)->payload_len = 0;
6318                 tcp_hdr(skb)->check =
6319                     ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6320                                      &ipv6_hdr(skb)->daddr,
6321                                      0, IPPROTO_TCP, 0);
6322         }
6323
6324         l4len = tcp_hdrlen(skb);
6325         *hdr_len = skb_transport_offset(skb) + l4len;
6326
6327         /* mss_l4len_id: use 1 as index for TSO */
6328         mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6329         mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6330         mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6331
6332         /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6333         vlan_macip_lens = skb_network_header_len(skb);
6334         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6335         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6336
6337         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6338                           mss_l4len_idx);
6339
6340         return 1;
6341 }
6342
6343 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6344                           struct sk_buff *skb, u32 tx_flags,
6345                           __be16 protocol)
6346 {
6347         u32 vlan_macip_lens = 0;
6348         u32 mss_l4len_idx = 0;
6349         u32 type_tucmd = 0;
6350
6351         if (skb->ip_summed != CHECKSUM_PARTIAL) {
6352             if (!(tx_flags & IXGBE_TX_FLAGS_VLAN))
6353                         return false;
6354         } else {
6355                 u8 l4_hdr = 0;
6356                 switch (protocol) {
6357                 case __constant_htons(ETH_P_IP):
6358                         vlan_macip_lens |= skb_network_header_len(skb);
6359                         type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6360                         l4_hdr = ip_hdr(skb)->protocol;
6361                         break;
6362                 case __constant_htons(ETH_P_IPV6):
6363                         vlan_macip_lens |= skb_network_header_len(skb);
6364                         l4_hdr = ipv6_hdr(skb)->nexthdr;
6365                         break;
6366                 default:
6367                         if (unlikely(net_ratelimit())) {
6368                                 dev_warn(tx_ring->dev,
6369                                  "partial checksum but proto=%x!\n",
6370                                  skb->protocol);
6371                         }
6372                         break;
6373                 }
6374
6375                 switch (l4_hdr) {
6376                 case IPPROTO_TCP:
6377                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6378                         mss_l4len_idx = tcp_hdrlen(skb) <<
6379                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6380                         break;
6381                 case IPPROTO_SCTP:
6382                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6383                         mss_l4len_idx = sizeof(struct sctphdr) <<
6384                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6385                         break;
6386                 case IPPROTO_UDP:
6387                         mss_l4len_idx = sizeof(struct udphdr) <<
6388                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6389                         break;
6390                 default:
6391                         if (unlikely(net_ratelimit())) {
6392                                 dev_warn(tx_ring->dev,
6393                                  "partial checksum but l4 proto=%x!\n",
6394                                  skb->protocol);
6395                         }
6396                         break;
6397                 }
6398         }
6399
6400         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6401         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6402
6403         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6404                           type_tucmd, mss_l4len_idx);
6405
6406         return (skb->ip_summed == CHECKSUM_PARTIAL);
6407 }
6408
6409 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6410                         struct ixgbe_ring *tx_ring,
6411                         struct sk_buff *skb, u32 tx_flags,
6412                         unsigned int first, const u8 hdr_len)
6413 {
6414         struct device *dev = tx_ring->dev;
6415         struct ixgbe_tx_buffer *tx_buffer_info;
6416         unsigned int len;
6417         unsigned int total = skb->len;
6418         unsigned int offset = 0, size, count = 0;
6419         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6420         unsigned int f;
6421         unsigned int bytecount = skb->len;
6422         u16 gso_segs = 1;
6423         u16 i;
6424
6425         i = tx_ring->next_to_use;
6426
6427         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6428                 /* excluding fcoe_crc_eof for FCoE */
6429                 total -= sizeof(struct fcoe_crc_eof);
6430
6431         len = min(skb_headlen(skb), total);
6432         while (len) {
6433                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6434                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6435
6436                 tx_buffer_info->length = size;
6437                 tx_buffer_info->mapped_as_page = false;
6438                 tx_buffer_info->dma = dma_map_single(dev,
6439                                                      skb->data + offset,
6440                                                      size, DMA_TO_DEVICE);
6441                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6442                         goto dma_error;
6443                 tx_buffer_info->time_stamp = jiffies;
6444                 tx_buffer_info->next_to_watch = i;
6445
6446                 len -= size;
6447                 total -= size;
6448                 offset += size;
6449                 count++;
6450
6451                 if (len) {
6452                         i++;
6453                         if (i == tx_ring->count)
6454                                 i = 0;
6455                 }
6456         }
6457
6458         for (f = 0; f < nr_frags; f++) {
6459                 struct skb_frag_struct *frag;
6460
6461                 frag = &skb_shinfo(skb)->frags[f];
6462                 len = min((unsigned int)frag->size, total);
6463                 offset = frag->page_offset;
6464
6465                 while (len) {
6466                         i++;
6467                         if (i == tx_ring->count)
6468                                 i = 0;
6469
6470                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6471                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6472
6473                         tx_buffer_info->length = size;
6474                         tx_buffer_info->dma = dma_map_page(dev,
6475                                                            frag->page,
6476                                                            offset, size,
6477                                                            DMA_TO_DEVICE);
6478                         tx_buffer_info->mapped_as_page = true;
6479                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6480                                 goto dma_error;
6481                         tx_buffer_info->time_stamp = jiffies;
6482                         tx_buffer_info->next_to_watch = i;
6483
6484                         len -= size;
6485                         total -= size;
6486                         offset += size;
6487                         count++;
6488                 }
6489                 if (total == 0)
6490                         break;
6491         }
6492
6493         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6494                 gso_segs = skb_shinfo(skb)->gso_segs;
6495 #ifdef IXGBE_FCOE
6496         /* adjust for FCoE Sequence Offload */
6497         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6498                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6499                                         skb_shinfo(skb)->gso_size);
6500 #endif /* IXGBE_FCOE */
6501         bytecount += (gso_segs - 1) * hdr_len;
6502
6503         /* multiply data chunks by size of headers */
6504         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6505         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6506         tx_ring->tx_buffer_info[i].skb = skb;
6507         tx_ring->tx_buffer_info[first].next_to_watch = i;
6508
6509         return count;
6510
6511 dma_error:
6512         e_dev_err("TX DMA map failed\n");
6513
6514         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6515         tx_buffer_info->dma = 0;
6516         tx_buffer_info->time_stamp = 0;
6517         tx_buffer_info->next_to_watch = 0;
6518         if (count)
6519                 count--;
6520
6521         /* clear timestamp and dma mappings for remaining portion of packet */
6522         while (count--) {
6523                 if (i == 0)
6524                         i += tx_ring->count;
6525                 i--;
6526                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6527                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6528         }
6529
6530         return 0;
6531 }
6532
6533 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6534                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6535 {
6536         union ixgbe_adv_tx_desc *tx_desc = NULL;
6537         struct ixgbe_tx_buffer *tx_buffer_info;
6538         u32 olinfo_status = 0, cmd_type_len = 0;
6539         unsigned int i;
6540         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6541
6542         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6543
6544         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6545
6546         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6547                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6548
6549         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6550                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6551
6552                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6553                                  IXGBE_ADVTXD_POPTS_SHIFT;
6554
6555                 /* use index 1 context for tso */
6556                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6557                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6558                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6559                                          IXGBE_ADVTXD_POPTS_SHIFT;
6560
6561         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6562                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6563                                  IXGBE_ADVTXD_POPTS_SHIFT;
6564
6565         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6566                 olinfo_status |= IXGBE_ADVTXD_CC;
6567                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6568                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6569                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6570         }
6571
6572         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6573
6574         i = tx_ring->next_to_use;
6575         while (count--) {
6576                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6577                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6578                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6579                 tx_desc->read.cmd_type_len =
6580                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6581                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6582                 i++;
6583                 if (i == tx_ring->count)
6584                         i = 0;
6585         }
6586
6587         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6588
6589         /*
6590          * Force memory writes to complete before letting h/w
6591          * know there are new descriptors to fetch.  (Only
6592          * applicable for weak-ordered memory model archs,
6593          * such as IA-64).
6594          */
6595         wmb();
6596
6597         tx_ring->next_to_use = i;
6598         writel(i, tx_ring->tail);
6599 }
6600
6601 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6602                       u32 tx_flags, __be16 protocol)
6603 {
6604         struct ixgbe_q_vector *q_vector = ring->q_vector;
6605         union ixgbe_atr_hash_dword input = { .dword = 0 };
6606         union ixgbe_atr_hash_dword common = { .dword = 0 };
6607         union {
6608                 unsigned char *network;
6609                 struct iphdr *ipv4;
6610                 struct ipv6hdr *ipv6;
6611         } hdr;
6612         struct tcphdr *th;
6613         __be16 vlan_id;
6614
6615         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6616         if (!q_vector)
6617                 return;
6618
6619         /* do nothing if sampling is disabled */
6620         if (!ring->atr_sample_rate)
6621                 return;
6622
6623         ring->atr_count++;
6624
6625         /* snag network header to get L4 type and address */
6626         hdr.network = skb_network_header(skb);
6627
6628         /* Currently only IPv4/IPv6 with TCP is supported */
6629         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6630              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6631             (protocol != __constant_htons(ETH_P_IP) ||
6632              hdr.ipv4->protocol != IPPROTO_TCP))
6633                 return;
6634
6635         th = tcp_hdr(skb);
6636
6637         /* skip this packet since the socket is closing */
6638         if (th->fin)
6639                 return;
6640
6641         /* sample on all syn packets or once every atr sample count */
6642         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6643                 return;
6644
6645         /* reset sample count */
6646         ring->atr_count = 0;
6647
6648         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6649
6650         /*
6651          * src and dst are inverted, think how the receiver sees them
6652          *
6653          * The input is broken into two sections, a non-compressed section
6654          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6655          * is XORed together and stored in the compressed dword.
6656          */
6657         input.formatted.vlan_id = vlan_id;
6658
6659         /*
6660          * since src port and flex bytes occupy the same word XOR them together
6661          * and write the value to source port portion of compressed dword
6662          */
6663         if (vlan_id)
6664                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6665         else
6666                 common.port.src ^= th->dest ^ protocol;
6667         common.port.dst ^= th->source;
6668
6669         if (protocol == __constant_htons(ETH_P_IP)) {
6670                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6671                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6672         } else {
6673                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6674                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6675                              hdr.ipv6->saddr.s6_addr32[1] ^
6676                              hdr.ipv6->saddr.s6_addr32[2] ^
6677                              hdr.ipv6->saddr.s6_addr32[3] ^
6678                              hdr.ipv6->daddr.s6_addr32[0] ^
6679                              hdr.ipv6->daddr.s6_addr32[1] ^
6680                              hdr.ipv6->daddr.s6_addr32[2] ^
6681                              hdr.ipv6->daddr.s6_addr32[3];
6682         }
6683
6684         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6685         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6686                                               input, common, ring->queue_index);
6687 }
6688
6689 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6690 {
6691         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6692         /* Herbert's original patch had:
6693          *  smp_mb__after_netif_stop_queue();
6694          * but since that doesn't exist yet, just open code it. */
6695         smp_mb();
6696
6697         /* We need to check again in a case another CPU has just
6698          * made room available. */
6699         if (likely(ixgbe_desc_unused(tx_ring) < size))
6700                 return -EBUSY;
6701
6702         /* A reprieve! - use start_queue because it doesn't call schedule */
6703         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6704         ++tx_ring->tx_stats.restart_queue;
6705         return 0;
6706 }
6707
6708 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6709 {
6710         if (likely(ixgbe_desc_unused(tx_ring) >= size))
6711                 return 0;
6712         return __ixgbe_maybe_stop_tx(tx_ring, size);
6713 }
6714
6715 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6716 {
6717         struct ixgbe_adapter *adapter = netdev_priv(dev);
6718         int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6719                                                smp_processor_id();
6720 #ifdef IXGBE_FCOE
6721         __be16 protocol = vlan_get_protocol(skb);
6722
6723         if (((protocol == htons(ETH_P_FCOE)) ||
6724             (protocol == htons(ETH_P_FIP))) &&
6725             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6726                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6727                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6728                 return txq;
6729         }
6730 #endif
6731
6732         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6733                 while (unlikely(txq >= dev->real_num_tx_queues))
6734                         txq -= dev->real_num_tx_queues;
6735                 return txq;
6736         }
6737
6738         return skb_tx_hash(dev, skb);
6739 }
6740
6741 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6742                           struct ixgbe_adapter *adapter,
6743                           struct ixgbe_ring *tx_ring)
6744 {
6745         int tso;
6746         u32  tx_flags = 0;
6747 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6748         unsigned short f;
6749 #endif
6750         u16 first;
6751         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6752         __be16 protocol;
6753         u8 hdr_len = 0;
6754
6755         /*
6756          * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6757          *       + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6758          *       + 2 desc gap to keep tail from touching head,
6759          *       + 1 desc for context descriptor,
6760          * otherwise try next time
6761          */
6762 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6763         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6764                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6765 #else
6766         count += skb_shinfo(skb)->nr_frags;
6767 #endif
6768         if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6769                 tx_ring->tx_stats.tx_busy++;
6770                 return NETDEV_TX_BUSY;
6771         }
6772
6773         protocol = vlan_get_protocol(skb);
6774
6775         if (vlan_tx_tag_present(skb)) {
6776                 tx_flags |= vlan_tx_tag_get(skb);
6777                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6778                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6779                         tx_flags |= tx_ring->dcb_tc << 13;
6780                 }
6781                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6782                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6783         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6784                    skb->priority != TC_PRIO_CONTROL) {
6785                 tx_flags |= tx_ring->dcb_tc << 13;
6786                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6787                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6788         }
6789
6790 #ifdef IXGBE_FCOE
6791         /* for FCoE with DCB, we force the priority to what
6792          * was specified by the switch */
6793         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6794             (protocol == htons(ETH_P_FCOE)))
6795                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6796
6797 #endif
6798         /* record the location of the first descriptor for this packet */
6799         first = tx_ring->next_to_use;
6800
6801         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6802 #ifdef IXGBE_FCOE
6803                 /* setup tx offload for FCoE */
6804                 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6805                 if (tso < 0)
6806                         goto out_drop;
6807                 else if (tso)
6808                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6809 #endif /* IXGBE_FCOE */
6810         } else {
6811                 if (protocol == htons(ETH_P_IP))
6812                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6813                 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6814                 if (tso < 0)
6815                         goto out_drop;
6816                 else if (tso)
6817                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6818                 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6819                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6820         }
6821
6822         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6823         if (count) {
6824                 /* add the ATR filter if ATR is on */
6825                 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6826                         ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6827                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6828                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6829
6830         } else {
6831                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6832                 tx_ring->next_to_use = first;
6833                 goto out_drop;
6834         }
6835
6836         return NETDEV_TX_OK;
6837
6838 out_drop:
6839         dev_kfree_skb_any(skb);
6840         return NETDEV_TX_OK;
6841 }
6842
6843 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6844 {
6845         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6846         struct ixgbe_ring *tx_ring;
6847
6848         tx_ring = adapter->tx_ring[skb->queue_mapping];
6849         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6850 }
6851
6852 /**
6853  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6854  * @netdev: network interface device structure
6855  * @p: pointer to an address structure
6856  *
6857  * Returns 0 on success, negative on failure
6858  **/
6859 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6860 {
6861         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6862         struct ixgbe_hw *hw = &adapter->hw;
6863         struct sockaddr *addr = p;
6864
6865         if (!is_valid_ether_addr(addr->sa_data))
6866                 return -EADDRNOTAVAIL;
6867
6868         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6869         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6870
6871         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6872                             IXGBE_RAH_AV);
6873
6874         return 0;
6875 }
6876
6877 static int
6878 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6879 {
6880         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6881         struct ixgbe_hw *hw = &adapter->hw;
6882         u16 value;
6883         int rc;
6884
6885         if (prtad != hw->phy.mdio.prtad)
6886                 return -EINVAL;
6887         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6888         if (!rc)
6889                 rc = value;
6890         return rc;
6891 }
6892
6893 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6894                             u16 addr, u16 value)
6895 {
6896         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6897         struct ixgbe_hw *hw = &adapter->hw;
6898
6899         if (prtad != hw->phy.mdio.prtad)
6900                 return -EINVAL;
6901         return hw->phy.ops.write_reg(hw, addr, devad, value);
6902 }
6903
6904 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6905 {
6906         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6907
6908         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6909 }
6910
6911 /**
6912  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6913  * netdev->dev_addrs
6914  * @netdev: network interface device structure
6915  *
6916  * Returns non-zero on failure
6917  **/
6918 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6919 {
6920         int err = 0;
6921         struct ixgbe_adapter *adapter = netdev_priv(dev);
6922         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6923
6924         if (is_valid_ether_addr(mac->san_addr)) {
6925                 rtnl_lock();
6926                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6927                 rtnl_unlock();
6928         }
6929         return err;
6930 }
6931
6932 /**
6933  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6934  * netdev->dev_addrs
6935  * @netdev: network interface device structure
6936  *
6937  * Returns non-zero on failure
6938  **/
6939 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6940 {
6941         int err = 0;
6942         struct ixgbe_adapter *adapter = netdev_priv(dev);
6943         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6944
6945         if (is_valid_ether_addr(mac->san_addr)) {
6946                 rtnl_lock();
6947                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6948                 rtnl_unlock();
6949         }
6950         return err;
6951 }
6952
6953 #ifdef CONFIG_NET_POLL_CONTROLLER
6954 /*
6955  * Polling 'interrupt' - used by things like netconsole to send skbs
6956  * without having to re-enable interrupts. It's not called while
6957  * the interrupt routine is executing.
6958  */
6959 static void ixgbe_netpoll(struct net_device *netdev)
6960 {
6961         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6962         int i;
6963
6964         /* if interface is down do nothing */
6965         if (test_bit(__IXGBE_DOWN, &adapter->state))
6966                 return;
6967
6968         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6969         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6970                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6971                 for (i = 0; i < num_q_vectors; i++) {
6972                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6973                         ixgbe_msix_clean_many(0, q_vector);
6974                 }
6975         } else {
6976                 ixgbe_intr(adapter->pdev->irq, netdev);
6977         }
6978         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6979 }
6980 #endif
6981
6982 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6983                                                    struct rtnl_link_stats64 *stats)
6984 {
6985         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6986         int i;
6987
6988         rcu_read_lock();
6989         for (i = 0; i < adapter->num_rx_queues; i++) {
6990                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6991                 u64 bytes, packets;
6992                 unsigned int start;
6993
6994                 if (ring) {
6995                         do {
6996                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6997                                 packets = ring->stats.packets;
6998                                 bytes   = ring->stats.bytes;
6999                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7000                         stats->rx_packets += packets;
7001                         stats->rx_bytes   += bytes;
7002                 }
7003         }
7004
7005         for (i = 0; i < adapter->num_tx_queues; i++) {
7006                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7007                 u64 bytes, packets;
7008                 unsigned int start;
7009
7010                 if (ring) {
7011                         do {
7012                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7013                                 packets = ring->stats.packets;
7014                                 bytes   = ring->stats.bytes;
7015                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7016                         stats->tx_packets += packets;
7017                         stats->tx_bytes   += bytes;
7018                 }
7019         }
7020         rcu_read_unlock();
7021         /* following stats updated by ixgbe_watchdog_task() */
7022         stats->multicast        = netdev->stats.multicast;
7023         stats->rx_errors        = netdev->stats.rx_errors;
7024         stats->rx_length_errors = netdev->stats.rx_length_errors;
7025         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
7026         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7027         return stats;
7028 }
7029
7030 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7031  * #adapter: pointer to ixgbe_adapter
7032  * @tc: number of traffic classes currently enabled
7033  *
7034  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7035  * 802.1Q priority maps to a packet buffer that exists.
7036  */
7037 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7038 {
7039         struct ixgbe_hw *hw = &adapter->hw;
7040         u32 reg, rsave;
7041         int i;
7042
7043         /* 82598 have a static priority to TC mapping that can not
7044          * be changed so no validation is needed.
7045          */
7046         if (hw->mac.type == ixgbe_mac_82598EB)
7047                 return;
7048
7049         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7050         rsave = reg;
7051
7052         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7053                 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7054
7055                 /* If up2tc is out of bounds default to zero */
7056                 if (up2tc > tc)
7057                         reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7058         }
7059
7060         if (reg != rsave)
7061                 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7062
7063         return;
7064 }
7065
7066
7067 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7068  * classes.
7069  *
7070  * @netdev: net device to configure
7071  * @tc: number of traffic classes to enable
7072  */
7073 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7074 {
7075         struct ixgbe_adapter *adapter = netdev_priv(dev);
7076         struct ixgbe_hw *hw = &adapter->hw;
7077
7078         /* If DCB is anabled do not remove traffic classes, multiple
7079          * traffic classes are required to implement DCB
7080          */
7081         if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7082                 return 0;
7083
7084         /* Hardware supports up to 8 traffic classes */
7085         if (tc > MAX_TRAFFIC_CLASS ||
7086             (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7087                 return -EINVAL;
7088
7089         /* Hardware has to reinitialize queues and interrupts to
7090          * match packet buffer alignment. Unfortunantly, the
7091          * hardware is not flexible enough to do this dynamically.
7092          */
7093         if (netif_running(dev))
7094                 ixgbe_close(dev);
7095         ixgbe_clear_interrupt_scheme(adapter);
7096
7097         if (tc)
7098                 netdev_set_num_tc(dev, tc);
7099         else
7100                 netdev_reset_tc(dev);
7101
7102         ixgbe_init_interrupt_scheme(adapter);
7103         ixgbe_validate_rtr(adapter, tc);
7104         if (netif_running(dev))
7105                 ixgbe_open(dev);
7106
7107         return 0;
7108 }
7109
7110 void ixgbe_do_reset(struct net_device *netdev)
7111 {
7112         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7113
7114         if (netif_running(netdev))
7115                 ixgbe_reinit_locked(adapter);
7116         else
7117                 ixgbe_reset(adapter);
7118 }
7119
7120 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7121 {
7122         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7123
7124 #ifdef CONFIG_DCB
7125         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7126                 data &= ~NETIF_F_HW_VLAN_RX;
7127 #endif
7128
7129         /* return error if RXHASH is being enabled when RSS is not supported */
7130         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7131                 data &= ~NETIF_F_RXHASH;
7132
7133         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7134         if (!(data & NETIF_F_RXCSUM))
7135                 data &= ~NETIF_F_LRO;
7136
7137         /* Turn off LRO if not RSC capable or invalid ITR settings */
7138         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7139                 data &= ~NETIF_F_LRO;
7140         } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7141                    (adapter->rx_itr_setting != 1 &&
7142                     adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7143                 data &= ~NETIF_F_LRO;
7144                 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7145         }
7146
7147         return data;
7148 }
7149
7150 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7151 {
7152         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7153         bool need_reset = false;
7154
7155         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7156         if (!(data & NETIF_F_RXCSUM))
7157                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7158         else
7159                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7160
7161         /* Make sure RSC matches LRO, reset if change */
7162         if (!!(data & NETIF_F_LRO) !=
7163              !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7164                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7165                 switch (adapter->hw.mac.type) {
7166                 case ixgbe_mac_X540:
7167                 case ixgbe_mac_82599EB:
7168                         need_reset = true;
7169                         break;
7170                 default:
7171                         break;
7172                 }
7173         }
7174
7175         /*
7176          * Check if Flow Director n-tuple support was enabled or disabled.  If
7177          * the state changed, we need to reset.
7178          */
7179         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7180                 /* turn off ATR, enable perfect filters and reset */
7181                 if (data & NETIF_F_NTUPLE) {
7182                         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7183                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7184                         need_reset = true;
7185                 }
7186         } else if (!(data & NETIF_F_NTUPLE)) {
7187                 /* turn off Flow Director, set ATR and reset */
7188                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7189                 if ((adapter->flags &  IXGBE_FLAG_RSS_ENABLED) &&
7190                     !(adapter->flags &  IXGBE_FLAG_DCB_ENABLED))
7191                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7192                 need_reset = true;
7193         }
7194
7195         if (need_reset)
7196                 ixgbe_do_reset(netdev);
7197
7198         return 0;
7199
7200 }
7201
7202 static const struct net_device_ops ixgbe_netdev_ops = {
7203         .ndo_open               = ixgbe_open,
7204         .ndo_stop               = ixgbe_close,
7205         .ndo_start_xmit         = ixgbe_xmit_frame,
7206         .ndo_select_queue       = ixgbe_select_queue,
7207         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7208         .ndo_validate_addr      = eth_validate_addr,
7209         .ndo_set_mac_address    = ixgbe_set_mac,
7210         .ndo_change_mtu         = ixgbe_change_mtu,
7211         .ndo_tx_timeout         = ixgbe_tx_timeout,
7212         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7213         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7214         .ndo_do_ioctl           = ixgbe_ioctl,
7215         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7216         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7217         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7218         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7219         .ndo_get_stats64        = ixgbe_get_stats64,
7220         .ndo_setup_tc           = ixgbe_setup_tc,
7221 #ifdef CONFIG_NET_POLL_CONTROLLER
7222         .ndo_poll_controller    = ixgbe_netpoll,
7223 #endif
7224 #ifdef IXGBE_FCOE
7225         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7226         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7227         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7228         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7229         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7230         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7231 #endif /* IXGBE_FCOE */
7232         .ndo_set_features = ixgbe_set_features,
7233         .ndo_fix_features = ixgbe_fix_features,
7234 };
7235
7236 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7237                            const struct ixgbe_info *ii)
7238 {
7239 #ifdef CONFIG_PCI_IOV
7240         struct ixgbe_hw *hw = &adapter->hw;
7241         int err;
7242         int num_vf_macvlans, i;
7243         struct vf_macvlans *mv_list;
7244
7245         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7246                 return;
7247
7248         /* The 82599 supports up to 64 VFs per physical function
7249          * but this implementation limits allocation to 63 so that
7250          * basic networking resources are still available to the
7251          * physical function
7252          */
7253         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7254         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7255         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7256         if (err) {
7257                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7258                 goto err_novfs;
7259         }
7260
7261         num_vf_macvlans = hw->mac.num_rar_entries -
7262                 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7263
7264         adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7265                                              sizeof(struct vf_macvlans),
7266                                              GFP_KERNEL);
7267         if (mv_list) {
7268                 /* Initialize list of VF macvlans */
7269                 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7270                 for (i = 0; i < num_vf_macvlans; i++) {
7271                         mv_list->vf = -1;
7272                         mv_list->free = true;
7273                         mv_list->rar_entry = hw->mac.num_rar_entries -
7274                                 (i + adapter->num_vfs + 1);
7275                         list_add(&mv_list->l, &adapter->vf_mvs.l);
7276                         mv_list++;
7277                 }
7278         }
7279
7280         /* If call to enable VFs succeeded then allocate memory
7281          * for per VF control structures.
7282          */
7283         adapter->vfinfo =
7284                 kcalloc(adapter->num_vfs,
7285                         sizeof(struct vf_data_storage), GFP_KERNEL);
7286         if (adapter->vfinfo) {
7287                 /* Now that we're sure SR-IOV is enabled
7288                  * and memory allocated set up the mailbox parameters
7289                  */
7290                 ixgbe_init_mbx_params_pf(hw);
7291                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7292                        sizeof(hw->mbx.ops));
7293
7294                 /* Disable RSC when in SR-IOV mode */
7295                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7296                                      IXGBE_FLAG2_RSC_ENABLED);
7297                 return;
7298         }
7299
7300         /* Oh oh */
7301         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7302               "SRIOV disabled\n");
7303         pci_disable_sriov(adapter->pdev);
7304
7305 err_novfs:
7306         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7307         adapter->num_vfs = 0;
7308 #endif /* CONFIG_PCI_IOV */
7309 }
7310
7311 /**
7312  * ixgbe_probe - Device Initialization Routine
7313  * @pdev: PCI device information struct
7314  * @ent: entry in ixgbe_pci_tbl
7315  *
7316  * Returns 0 on success, negative on failure
7317  *
7318  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7319  * The OS initialization, configuring of the adapter private structure,
7320  * and a hardware reset occur.
7321  **/
7322 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7323                                  const struct pci_device_id *ent)
7324 {
7325         struct net_device *netdev;
7326         struct ixgbe_adapter *adapter = NULL;
7327         struct ixgbe_hw *hw;
7328         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7329         static int cards_found;
7330         int i, err, pci_using_dac;
7331         u8 part_str[IXGBE_PBANUM_LENGTH];
7332         unsigned int indices = num_possible_cpus();
7333 #ifdef IXGBE_FCOE
7334         u16 device_caps;
7335 #endif
7336         u32 eec;
7337
7338         /* Catch broken hardware that put the wrong VF device ID in
7339          * the PCIe SR-IOV capability.
7340          */
7341         if (pdev->is_virtfn) {
7342                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7343                      pci_name(pdev), pdev->vendor, pdev->device);
7344                 return -EINVAL;
7345         }
7346
7347         err = pci_enable_device_mem(pdev);
7348         if (err)
7349                 return err;
7350
7351         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7352             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7353                 pci_using_dac = 1;
7354         } else {
7355                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7356                 if (err) {
7357                         err = dma_set_coherent_mask(&pdev->dev,
7358                                                     DMA_BIT_MASK(32));
7359                         if (err) {
7360                                 dev_err(&pdev->dev,
7361                                         "No usable DMA configuration, aborting\n");
7362                                 goto err_dma;
7363                         }
7364                 }
7365                 pci_using_dac = 0;
7366         }
7367
7368         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7369                                            IORESOURCE_MEM), ixgbe_driver_name);
7370         if (err) {
7371                 dev_err(&pdev->dev,
7372                         "pci_request_selected_regions failed 0x%x\n", err);
7373                 goto err_pci_reg;
7374         }
7375
7376         pci_enable_pcie_error_reporting(pdev);
7377
7378         pci_set_master(pdev);
7379         pci_save_state(pdev);
7380
7381 #ifdef CONFIG_IXGBE_DCB
7382         indices *= MAX_TRAFFIC_CLASS;
7383 #endif
7384
7385         if (ii->mac == ixgbe_mac_82598EB)
7386                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7387         else
7388                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7389
7390 #ifdef IXGBE_FCOE
7391         indices += min_t(unsigned int, num_possible_cpus(),
7392                          IXGBE_MAX_FCOE_INDICES);
7393 #endif
7394         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7395         if (!netdev) {
7396                 err = -ENOMEM;
7397                 goto err_alloc_etherdev;
7398         }
7399
7400         SET_NETDEV_DEV(netdev, &pdev->dev);
7401
7402         adapter = netdev_priv(netdev);
7403         pci_set_drvdata(pdev, adapter);
7404
7405         adapter->netdev = netdev;
7406         adapter->pdev = pdev;
7407         hw = &adapter->hw;
7408         hw->back = adapter;
7409         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7410
7411         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7412                               pci_resource_len(pdev, 0));
7413         if (!hw->hw_addr) {
7414                 err = -EIO;
7415                 goto err_ioremap;
7416         }
7417
7418         for (i = 1; i <= 5; i++) {
7419                 if (pci_resource_len(pdev, i) == 0)
7420                         continue;
7421         }
7422
7423         netdev->netdev_ops = &ixgbe_netdev_ops;
7424         ixgbe_set_ethtool_ops(netdev);
7425         netdev->watchdog_timeo = 5 * HZ;
7426         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7427
7428         adapter->bd_number = cards_found;
7429
7430         /* Setup hw api */
7431         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7432         hw->mac.type  = ii->mac;
7433
7434         /* EEPROM */
7435         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7436         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7437         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7438         if (!(eec & (1 << 8)))
7439                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7440
7441         /* PHY */
7442         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7443         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7444         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7445         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7446         hw->phy.mdio.mmds = 0;
7447         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7448         hw->phy.mdio.dev = netdev;
7449         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7450         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7451
7452         ii->get_invariants(hw);
7453
7454         /* setup the private structure */
7455         err = ixgbe_sw_init(adapter);
7456         if (err)
7457                 goto err_sw_init;
7458
7459         /* Make it possible the adapter to be woken up via WOL */
7460         switch (adapter->hw.mac.type) {
7461         case ixgbe_mac_82599EB:
7462         case ixgbe_mac_X540:
7463                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7464                 break;
7465         default:
7466                 break;
7467         }
7468
7469         /*
7470          * If there is a fan on this device and it has failed log the
7471          * failure.
7472          */
7473         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7474                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7475                 if (esdp & IXGBE_ESDP_SDP1)
7476                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7477         }
7478
7479         /* reset_hw fills in the perm_addr as well */
7480         hw->phy.reset_if_overtemp = true;
7481         err = hw->mac.ops.reset_hw(hw);
7482         hw->phy.reset_if_overtemp = false;
7483         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7484             hw->mac.type == ixgbe_mac_82598EB) {
7485                 err = 0;
7486         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7487                 e_dev_err("failed to load because an unsupported SFP+ "
7488                           "module type was detected.\n");
7489                 e_dev_err("Reload the driver after installing a supported "
7490                           "module.\n");
7491                 goto err_sw_init;
7492         } else if (err) {
7493                 e_dev_err("HW Init failed: %d\n", err);
7494                 goto err_sw_init;
7495         }
7496
7497         ixgbe_probe_vf(adapter, ii);
7498
7499         netdev->features = NETIF_F_SG |
7500                            NETIF_F_IP_CSUM |
7501                            NETIF_F_IPV6_CSUM |
7502                            NETIF_F_HW_VLAN_TX |
7503                            NETIF_F_HW_VLAN_RX |
7504                            NETIF_F_HW_VLAN_FILTER |
7505                            NETIF_F_TSO |
7506                            NETIF_F_TSO6 |
7507                            NETIF_F_GRO |
7508                            NETIF_F_RXHASH |
7509                            NETIF_F_RXCSUM;
7510
7511         netdev->hw_features = netdev->features;
7512
7513         switch (adapter->hw.mac.type) {
7514         case ixgbe_mac_82599EB:
7515         case ixgbe_mac_X540:
7516                 netdev->features |= NETIF_F_SCTP_CSUM;
7517                 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7518                                        NETIF_F_NTUPLE;
7519                 break;
7520         default:
7521                 break;
7522         }
7523
7524         netdev->vlan_features |= NETIF_F_TSO;
7525         netdev->vlan_features |= NETIF_F_TSO6;
7526         netdev->vlan_features |= NETIF_F_IP_CSUM;
7527         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7528         netdev->vlan_features |= NETIF_F_SG;
7529
7530         netdev->priv_flags |= IFF_UNICAST_FLT;
7531
7532         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7533                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7534                                     IXGBE_FLAG_DCB_ENABLED);
7535
7536 #ifdef CONFIG_IXGBE_DCB
7537         netdev->dcbnl_ops = &dcbnl_ops;
7538 #endif
7539
7540 #ifdef IXGBE_FCOE
7541         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7542                 if (hw->mac.ops.get_device_caps) {
7543                         hw->mac.ops.get_device_caps(hw, &device_caps);
7544                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7545                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7546                 }
7547         }
7548         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7549                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7550                 netdev->vlan_features |= NETIF_F_FSO;
7551                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7552         }
7553 #endif /* IXGBE_FCOE */
7554         if (pci_using_dac) {
7555                 netdev->features |= NETIF_F_HIGHDMA;
7556                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7557         }
7558
7559         if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7560                 netdev->hw_features |= NETIF_F_LRO;
7561         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7562                 netdev->features |= NETIF_F_LRO;
7563
7564         /* make sure the EEPROM is good */
7565         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7566                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7567                 err = -EIO;
7568                 goto err_eeprom;
7569         }
7570
7571         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7572         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7573
7574         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7575                 e_dev_err("invalid MAC address\n");
7576                 err = -EIO;
7577                 goto err_eeprom;
7578         }
7579
7580         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7581         if (hw->mac.ops.disable_tx_laser &&
7582             ((hw->phy.multispeed_fiber) ||
7583              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7584               (hw->mac.type == ixgbe_mac_82599EB))))
7585                 hw->mac.ops.disable_tx_laser(hw);
7586
7587         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7588                     (unsigned long) adapter);
7589
7590         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7591         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7592
7593         err = ixgbe_init_interrupt_scheme(adapter);
7594         if (err)
7595                 goto err_sw_init;
7596
7597         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7598                 netdev->hw_features &= ~NETIF_F_RXHASH;
7599                 netdev->features &= ~NETIF_F_RXHASH;
7600         }
7601
7602         switch (pdev->device) {
7603         case IXGBE_DEV_ID_82599_SFP:
7604                 /* Only this subdevice supports WOL */
7605                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7606                         adapter->wol = IXGBE_WUFC_MAG;
7607                 break;
7608         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7609                 /* All except this subdevice support WOL */
7610                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7611                         adapter->wol = IXGBE_WUFC_MAG;
7612                 break;
7613         case IXGBE_DEV_ID_82599_KX4:
7614                 adapter->wol = IXGBE_WUFC_MAG;
7615                 break;
7616         default:
7617                 adapter->wol = 0;
7618                 break;
7619         }
7620         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7621
7622         /* pick up the PCI bus settings for reporting later */
7623         hw->mac.ops.get_bus_info(hw);
7624
7625         /* print bus type/speed/width info */
7626         e_dev_info("(PCI Express:%s:%s) %pM\n",
7627                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7628                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7629                     "Unknown"),
7630                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7631                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7632                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7633                     "Unknown"),
7634                    netdev->dev_addr);
7635
7636         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7637         if (err)
7638                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7639         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7640                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7641                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7642                            part_str);
7643         else
7644                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7645                            hw->mac.type, hw->phy.type, part_str);
7646
7647         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7648                 e_dev_warn("PCI-Express bandwidth available for this card is "
7649                            "not sufficient for optimal performance.\n");
7650                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7651                            "is required.\n");
7652         }
7653
7654         /* save off EEPROM version number */
7655         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7656
7657         /* reset the hardware with the new settings */
7658         err = hw->mac.ops.start_hw(hw);
7659
7660         if (err == IXGBE_ERR_EEPROM_VERSION) {
7661                 /* We are running on a pre-production device, log a warning */
7662                 e_dev_warn("This device is a pre-production adapter/LOM. "
7663                            "Please be aware there may be issues associated "
7664                            "with your hardware.  If you are experiencing "
7665                            "problems please contact your Intel or hardware "
7666                            "representative who provided you with this "
7667                            "hardware.\n");
7668         }
7669         strcpy(netdev->name, "eth%d");
7670         err = register_netdev(netdev);
7671         if (err)
7672                 goto err_register;
7673
7674         /* carrier off reporting is important to ethtool even BEFORE open */
7675         netif_carrier_off(netdev);
7676
7677 #ifdef CONFIG_IXGBE_DCA
7678         if (dca_add_requester(&pdev->dev) == 0) {
7679                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7680                 ixgbe_setup_dca(adapter);
7681         }
7682 #endif
7683         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7684                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7685                 for (i = 0; i < adapter->num_vfs; i++)
7686                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7687         }
7688
7689         /* Inform firmware of driver version */
7690         if (hw->mac.ops.set_fw_drv_ver)
7691                 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7692                                            FW_CEM_UNUSED_VER);
7693
7694         /* add san mac addr to netdev */
7695         ixgbe_add_sanmac_netdev(netdev);
7696
7697         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7698         cards_found++;
7699         return 0;
7700
7701 err_register:
7702         ixgbe_release_hw_control(adapter);
7703         ixgbe_clear_interrupt_scheme(adapter);
7704 err_sw_init:
7705 err_eeprom:
7706         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7707                 ixgbe_disable_sriov(adapter);
7708         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7709         iounmap(hw->hw_addr);
7710 err_ioremap:
7711         free_netdev(netdev);
7712 err_alloc_etherdev:
7713         pci_release_selected_regions(pdev,
7714                                      pci_select_bars(pdev, IORESOURCE_MEM));
7715 err_pci_reg:
7716 err_dma:
7717         pci_disable_device(pdev);
7718         return err;
7719 }
7720
7721 /**
7722  * ixgbe_remove - Device Removal Routine
7723  * @pdev: PCI device information struct
7724  *
7725  * ixgbe_remove is called by the PCI subsystem to alert the driver
7726  * that it should release a PCI device.  The could be caused by a
7727  * Hot-Plug event, or because the driver is going to be removed from
7728  * memory.
7729  **/
7730 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7731 {
7732         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7733         struct net_device *netdev = adapter->netdev;
7734
7735         set_bit(__IXGBE_DOWN, &adapter->state);
7736         cancel_work_sync(&adapter->service_task);
7737
7738 #ifdef CONFIG_IXGBE_DCA
7739         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7740                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7741                 dca_remove_requester(&pdev->dev);
7742                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7743         }
7744
7745 #endif
7746 #ifdef IXGBE_FCOE
7747         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7748                 ixgbe_cleanup_fcoe(adapter);
7749
7750 #endif /* IXGBE_FCOE */
7751
7752         /* remove the added san mac */
7753         ixgbe_del_sanmac_netdev(netdev);
7754
7755         if (netdev->reg_state == NETREG_REGISTERED)
7756                 unregister_netdev(netdev);
7757
7758         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7759                 ixgbe_disable_sriov(adapter);
7760
7761         ixgbe_clear_interrupt_scheme(adapter);
7762
7763         ixgbe_release_hw_control(adapter);
7764
7765         iounmap(adapter->hw.hw_addr);
7766         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7767                                      IORESOURCE_MEM));
7768
7769         e_dev_info("complete\n");
7770
7771         free_netdev(netdev);
7772
7773         pci_disable_pcie_error_reporting(pdev);
7774
7775         pci_disable_device(pdev);
7776 }
7777
7778 /**
7779  * ixgbe_io_error_detected - called when PCI error is detected
7780  * @pdev: Pointer to PCI device
7781  * @state: The current pci connection state
7782  *
7783  * This function is called after a PCI bus error affecting
7784  * this device has been detected.
7785  */
7786 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7787                                                 pci_channel_state_t state)
7788 {
7789         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7790         struct net_device *netdev = adapter->netdev;
7791
7792         netif_device_detach(netdev);
7793
7794         if (state == pci_channel_io_perm_failure)
7795                 return PCI_ERS_RESULT_DISCONNECT;
7796
7797         if (netif_running(netdev))
7798                 ixgbe_down(adapter);
7799         pci_disable_device(pdev);
7800
7801         /* Request a slot reset. */
7802         return PCI_ERS_RESULT_NEED_RESET;
7803 }
7804
7805 /**
7806  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7807  * @pdev: Pointer to PCI device
7808  *
7809  * Restart the card from scratch, as if from a cold-boot.
7810  */
7811 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7812 {
7813         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7814         pci_ers_result_t result;
7815         int err;
7816
7817         if (pci_enable_device_mem(pdev)) {
7818                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7819                 result = PCI_ERS_RESULT_DISCONNECT;
7820         } else {
7821                 pci_set_master(pdev);
7822                 pci_restore_state(pdev);
7823                 pci_save_state(pdev);
7824
7825                 pci_wake_from_d3(pdev, false);
7826
7827                 ixgbe_reset(adapter);
7828                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7829                 result = PCI_ERS_RESULT_RECOVERED;
7830         }
7831
7832         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7833         if (err) {
7834                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7835                           "failed 0x%0x\n", err);
7836                 /* non-fatal, continue */
7837         }
7838
7839         return result;
7840 }
7841
7842 /**
7843  * ixgbe_io_resume - called when traffic can start flowing again.
7844  * @pdev: Pointer to PCI device
7845  *
7846  * This callback is called when the error recovery driver tells us that
7847  * its OK to resume normal operation.
7848  */
7849 static void ixgbe_io_resume(struct pci_dev *pdev)
7850 {
7851         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7852         struct net_device *netdev = adapter->netdev;
7853
7854         if (netif_running(netdev)) {
7855                 if (ixgbe_up(adapter)) {
7856                         e_info(probe, "ixgbe_up failed after reset\n");
7857                         return;
7858                 }
7859         }
7860
7861         netif_device_attach(netdev);
7862 }
7863
7864 static struct pci_error_handlers ixgbe_err_handler = {
7865         .error_detected = ixgbe_io_error_detected,
7866         .slot_reset = ixgbe_io_slot_reset,
7867         .resume = ixgbe_io_resume,
7868 };
7869
7870 static struct pci_driver ixgbe_driver = {
7871         .name     = ixgbe_driver_name,
7872         .id_table = ixgbe_pci_tbl,
7873         .probe    = ixgbe_probe,
7874         .remove   = __devexit_p(ixgbe_remove),
7875 #ifdef CONFIG_PM
7876         .suspend  = ixgbe_suspend,
7877         .resume   = ixgbe_resume,
7878 #endif
7879         .shutdown = ixgbe_shutdown,
7880         .err_handler = &ixgbe_err_handler
7881 };
7882
7883 /**
7884  * ixgbe_init_module - Driver Registration Routine
7885  *
7886  * ixgbe_init_module is the first routine called when the driver is
7887  * loaded. All it does is register with the PCI subsystem.
7888  **/
7889 static int __init ixgbe_init_module(void)
7890 {
7891         int ret;
7892         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7893         pr_info("%s\n", ixgbe_copyright);
7894
7895 #ifdef CONFIG_IXGBE_DCA
7896         dca_register_notify(&dca_notifier);
7897 #endif
7898
7899         ret = pci_register_driver(&ixgbe_driver);
7900         return ret;
7901 }
7902
7903 module_init(ixgbe_init_module);
7904
7905 /**
7906  * ixgbe_exit_module - Driver Exit Cleanup Routine
7907  *
7908  * ixgbe_exit_module is called just before the driver is removed
7909  * from memory.
7910  **/
7911 static void __exit ixgbe_exit_module(void)
7912 {
7913 #ifdef CONFIG_IXGBE_DCA
7914         dca_unregister_notify(&dca_notifier);
7915 #endif
7916         pci_unregister_driver(&ixgbe_driver);
7917         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7918 }
7919
7920 #ifdef CONFIG_IXGBE_DCA
7921 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7922                             void *p)
7923 {
7924         int ret_val;
7925
7926         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7927                                          __ixgbe_notify_dca);
7928
7929         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7930 }
7931
7932 #endif /* CONFIG_IXGBE_DCA */
7933
7934 module_exit(ixgbe_exit_module);
7935
7936 /* ixgbe_main.c */