drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/sctp.h>
  39 #include <linux/pkt_sched.h>
  40 #include <linux/ipv6.h>
  41 #include <linux/slab.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <linux/ethtool.h>
  45 #include <linux/if.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/prefetch.h>
  48 #include <scsi/fc/fc_fcoe.h>
  49
  50 #include "ixgbe.h"
  51 #include "ixgbe_common.h"
  52 #include "ixgbe_dcb_82599.h"
  53 #include "ixgbe_sriov.h"
  54
  55 char ixgbe_driver_name[] = "ixgbe";
  56 static const char ixgbe_driver_string[] =
  57                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  58 #define MAJ 3
  59 #define MIN 4
  60 #define BUILD 8
  61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  62         __stringify(BUILD) "-k"
  63 const char ixgbe_driver_version[] = DRV_VERSION;
  64 static const char ixgbe_copyright[] =
  65                                 "Copyright (c) 1999-2011 Intel Corporation.";
  66
  67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  68         [board_82598] = &ixgbe_82598_info,
  69         [board_82599] = &ixgbe_82599_info,
  70         [board_X540] = &ixgbe_X540_info,
  71 };
  72
  73 /* ixgbe_pci_tbl - PCI Device ID Table
  74  *
  75  * Wildcard entries (PCI_ANY_ID) should come last
  76  * Last entry must be all 0s
  77  *
  78  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  79  *   Class, Class Mask, private data (not used) }
  80  */
  81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  95          board_82598 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  97          board_82598 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  99          board_82598 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
 101          board_82598 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
 103          board_82598 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
 105          board_82598 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
 107          board_82599 },
 108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 109          board_82599 },
 110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 111          board_82599 },
 112         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 113          board_82599 },
 114         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 115          board_82599 },
 116         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 117          board_82599 },
 118         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 119          board_82599 },
 120         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 121          board_82599 },
 122         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 123          board_82599 },
 124         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 125          board_82599 },
 126         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 127          board_82599 },
 128         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 129          board_X540 },
 130         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
 131          board_82599 },
 132         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
 133          board_82599 },
 134
 135         /* required last entry */
 136         {0, }
 137 };
 138 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 139
 140 #ifdef CONFIG_IXGBE_DCA
 141 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 142                             void *p);
 143 static struct notifier_block dca_notifier = {
 144         .notifier_call = ixgbe_notify_dca,
 145         .next          = NULL,
 146         .priority      = 0
 147 };
 148 #endif
 149
 150 #ifdef CONFIG_PCI_IOV
 151 static unsigned int max_vfs;
 152 module_param(max_vfs, uint, 0);
 153 MODULE_PARM_DESC(max_vfs,
 154                  "Maximum number of virtual functions to allocate per physical function");
 155 #endif /* CONFIG_PCI_IOV */
 156
 157 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 158 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 159 MODULE_LICENSE("GPL");
 160 MODULE_VERSION(DRV_VERSION);
 161
 162 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 163
 164 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 165 {
 166         struct ixgbe_hw *hw = &adapter->hw;
 167         u32 gcr;
 168         u32 gpie;
 169         u32 vmdctl;
 170
 171 #ifdef CONFIG_PCI_IOV
 172         /* disable iov and allow time for transactions to clear */
 173         pci_disable_sriov(adapter->pdev);
 174 #endif
 175
 176         /* turn off device IOV mode */
 177         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 178         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 179         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 180         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 181         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 182         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 183
 184         /* set default pool back to 0 */
 185         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 186         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 187         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 188         IXGBE_WRITE_FLUSH(hw);
 189
 190         /* take a breather then clean up driver data */
 191         msleep(100);
 192
 193         kfree(adapter->vfinfo);
 194         adapter->vfinfo = NULL;
 195
 196         adapter->num_vfs = 0;
 197         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 198 }
 199
 200 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 201 {
 202         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 203             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 204                 schedule_work(&adapter->service_task);
 205 }
 206
 207 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 208 {
 209         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 210
 211         /* flush memory to make sure state is correct before next watchog */
 212         smp_mb__before_clear_bit();
 213         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 214 }
 215
 216 struct ixgbe_reg_info {
 217         u32 ofs;
 218         char *name;
 219 };
 220
 221 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 222
 223         /* General Registers */
 224         {IXGBE_CTRL, "CTRL"},
 225         {IXGBE_STATUS, "STATUS"},
 226         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 227
 228         /* Interrupt Registers */
 229         {IXGBE_EICR, "EICR"},
 230
 231         /* RX Registers */
 232         {IXGBE_SRRCTL(0), "SRRCTL"},
 233         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 234         {IXGBE_RDLEN(0), "RDLEN"},
 235         {IXGBE_RDH(0), "RDH"},
 236         {IXGBE_RDT(0), "RDT"},
 237         {IXGBE_RXDCTL(0), "RXDCTL"},
 238         {IXGBE_RDBAL(0), "RDBAL"},
 239         {IXGBE_RDBAH(0), "RDBAH"},
 240
 241         /* TX Registers */
 242         {IXGBE_TDBAL(0), "TDBAL"},
 243         {IXGBE_TDBAH(0), "TDBAH"},
 244         {IXGBE_TDLEN(0), "TDLEN"},
 245         {IXGBE_TDH(0), "TDH"},
 246         {IXGBE_TDT(0), "TDT"},
 247         {IXGBE_TXDCTL(0), "TXDCTL"},
 248
 249         /* List Terminator */
 250         {}
 251 };
 252
 253
 254 /*
 255  * ixgbe_regdump - register printout routine
 256  */
 257 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 258 {
 259         int i = 0, j = 0;
 260         char rname[16];
 261         u32 regs[64];
 262
 263         switch (reginfo->ofs) {
 264         case IXGBE_SRRCTL(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 267                 break;
 268         case IXGBE_DCA_RXCTRL(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 271                 break;
 272         case IXGBE_RDLEN(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 275                 break;
 276         case IXGBE_RDH(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 279                 break;
 280         case IXGBE_RDT(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 283                 break;
 284         case IXGBE_RXDCTL(0):
 285                 for (i = 0; i < 64; i++)
 286                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 287                 break;
 288         case IXGBE_RDBAL(0):
 289                 for (i = 0; i < 64; i++)
 290                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 291                 break;
 292         case IXGBE_RDBAH(0):
 293                 for (i = 0; i < 64; i++)
 294                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 295                 break;
 296         case IXGBE_TDBAL(0):
 297                 for (i = 0; i < 64; i++)
 298                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 299                 break;
 300         case IXGBE_TDBAH(0):
 301                 for (i = 0; i < 64; i++)
 302                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 303                 break;
 304         case IXGBE_TDLEN(0):
 305                 for (i = 0; i < 64; i++)
 306                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 307                 break;
 308         case IXGBE_TDH(0):
 309                 for (i = 0; i < 64; i++)
 310                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 311                 break;
 312         case IXGBE_TDT(0):
 313                 for (i = 0; i < 64; i++)
 314                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 315                 break;
 316         case IXGBE_TXDCTL(0):
 317                 for (i = 0; i < 64; i++)
 318                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 319                 break;
 320         default:
 321                 pr_info("%-15s %08x\n", reginfo->name,
 322                         IXGBE_READ_REG(hw, reginfo->ofs));
 323                 return;
 324         }
 325
 326         for (i = 0; i < 8; i++) {
 327                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 328                 pr_err("%-15s", rname);
 329                 for (j = 0; j < 8; j++)
 330                         pr_cont(" %08x", regs[i*8+j]);
 331                 pr_cont("\n");
 332         }
 333
 334 }
 335
 336 /*
 337  * ixgbe_dump - Print registers, tx-rings and rx-rings
 338  */
 339 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 340 {
 341         struct net_device *netdev = adapter->netdev;
 342         struct ixgbe_hw *hw = &adapter->hw;
 343         struct ixgbe_reg_info *reginfo;
 344         int n = 0;
 345         struct ixgbe_ring *tx_ring;
 346         struct ixgbe_tx_buffer *tx_buffer_info;
 347         union ixgbe_adv_tx_desc *tx_desc;
 348         struct my_u0 { u64 a; u64 b; } *u0;
 349         struct ixgbe_ring *rx_ring;
 350         union ixgbe_adv_rx_desc *rx_desc;
 351         struct ixgbe_rx_buffer *rx_buffer_info;
 352         u32 staterr;
 353         int i = 0;
 354
 355         if (!netif_msg_hw(adapter))
 356                 return;
 357
 358         /* Print netdevice Info */
 359         if (netdev) {
 360                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 361                 pr_info("Device Name     state            "
 362                         "trans_start      last_rx\n");
 363                 pr_info("%-15s %016lX %016lX %016lX\n",
 364                         netdev->name,
 365                         netdev->state,
 366                         netdev->trans_start,
 367                         netdev->last_rx);
 368         }
 369
 370         /* Print Registers */
 371         dev_info(&adapter->pdev->dev, "Register Dump\n");
 372         pr_info(" Register Name   Value\n");
 373         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 374              reginfo->name; reginfo++) {
 375                 ixgbe_regdump(hw, reginfo);
 376         }
 377
 378         /* Print TX Ring Summary */
 379         if (!netdev || !netif_running(netdev))
 380                 goto exit;
 381
 382         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 383         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 384         for (n = 0; n < adapter->num_tx_queues; n++) {
 385                 tx_ring = adapter->tx_ring[n];
 386                 tx_buffer_info =
 387                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 388                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 389                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 390                            (u64)tx_buffer_info->dma,
 391                            tx_buffer_info->length,
 392                            tx_buffer_info->next_to_watch,
 393                            (u64)tx_buffer_info->time_stamp);
 394         }
 395
 396         /* Print TX Rings */
 397         if (!netif_msg_tx_done(adapter))
 398                 goto rx_ring_summary;
 399
 400         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 401
 402         /* Transmit Descriptor Formats
 403          *
 404          * Advanced Transmit Descriptor
 405          *   +--------------------------------------------------------------+
 406          * 0 |         Buffer Address [63:0]                                |
 407          *   +--------------------------------------------------------------+
 408          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 409          *   +--------------------------------------------------------------+
 410          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 411          */
 412
 413         for (n = 0; n < adapter->num_tx_queues; n++) {
 414                 tx_ring = adapter->tx_ring[n];
 415                 pr_info("------------------------------------\n");
 416                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 417                 pr_info("------------------------------------\n");
 418                 pr_info("T [desc]     [address 63:0  ] "
 419                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 420                         "leng  ntw timestamp        bi->skb\n");
 421
 422                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 423                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 424                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 425                         u0 = (struct my_u0 *)tx_desc;
 426                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 427                                 " %04X  %p %016llX %p", i,
 428                                 le64_to_cpu(u0->a),
 429                                 le64_to_cpu(u0->b),
 430                                 (u64)tx_buffer_info->dma,
 431                                 tx_buffer_info->length,
 432                                 tx_buffer_info->next_to_watch,
 433                                 (u64)tx_buffer_info->time_stamp,
 434                                 tx_buffer_info->skb);
 435                         if (i == tx_ring->next_to_use &&
 436                                 i == tx_ring->next_to_clean)
 437                                 pr_cont(" NTC/U\n");
 438                         else if (i == tx_ring->next_to_use)
 439                                 pr_cont(" NTU\n");
 440                         else if (i == tx_ring->next_to_clean)
 441                                 pr_cont(" NTC\n");
 442                         else
 443                                 pr_cont("\n");
 444
 445                         if (netif_msg_pktdata(adapter) &&
 446                                 tx_buffer_info->dma != 0)
 447                                 print_hex_dump(KERN_INFO, "",
 448                                         DUMP_PREFIX_ADDRESS, 16, 1,
 449                                         phys_to_virt(tx_buffer_info->dma),
 450                                         tx_buffer_info->length, true);
 451                 }
 452         }
 453
 454         /* Print RX Rings Summary */
 455 rx_ring_summary:
 456         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 457         pr_info("Queue [NTU] [NTC]\n");
 458         for (n = 0; n < adapter->num_rx_queues; n++) {
 459                 rx_ring = adapter->rx_ring[n];
 460                 pr_info("%5d %5X %5X\n",
 461                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 462         }
 463
 464         /* Print RX Rings */
 465         if (!netif_msg_rx_status(adapter))
 466                 goto exit;
 467
 468         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 469
 470         /* Advanced Receive Descriptor (Read) Format
 471          *    63                                           1        0
 472          *    +-----------------------------------------------------+
 473          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 474          *    +----------------------------------------------+------+
 475          *  8 |       Header Buffer Address [63:1]           |  DD  |
 476          *    +-----------------------------------------------------+
 477          *
 478          *
 479          * Advanced Receive Descriptor (Write-Back) Format
 480          *
 481          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 482          *   +------------------------------------------------------+
 483          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 484          *   | Checksum   Ident  |   |           |    | Type | Type |
 485          *   +------------------------------------------------------+
 486          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 487          *   +------------------------------------------------------+
 488          *   63       48 47    32 31            20 19               0
 489          */
 490         for (n = 0; n < adapter->num_rx_queues; n++) {
 491                 rx_ring = adapter->rx_ring[n];
 492                 pr_info("------------------------------------\n");
 493                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 494                 pr_info("------------------------------------\n");
 495                 pr_info("R  [desc]      [ PktBuf     A0] "
 496                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 497                         "<-- Adv Rx Read format\n");
 498                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 499                         "[vl er S cks ln] ---------------- [bi->skb] "
 500                         "<-- Adv Rx Write-Back format\n");
 501
 502                 for (i = 0; i < rx_ring->count; i++) {
 503                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 504                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 505                         u0 = (struct my_u0 *)rx_desc;
 506                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 507                         if (staterr & IXGBE_RXD_STAT_DD) {
 508                                 /* Descriptor Done */
 509                                 pr_info("RWB[0x%03X]     %016llX "
 510                                         "%016llX ---------------- %p", i,
 511                                         le64_to_cpu(u0->a),
 512                                         le64_to_cpu(u0->b),
 513                                         rx_buffer_info->skb);
 514                         } else {
 515                                 pr_info("R  [0x%03X]     %016llX "
 516                                         "%016llX %016llX %p", i,
 517                                         le64_to_cpu(u0->a),
 518                                         le64_to_cpu(u0->b),
 519                                         (u64)rx_buffer_info->dma,
 520                                         rx_buffer_info->skb);
 521
 522                                 if (netif_msg_pktdata(adapter)) {
 523                                         print_hex_dump(KERN_INFO, "",
 524                                            DUMP_PREFIX_ADDRESS, 16, 1,
 525                                            phys_to_virt(rx_buffer_info->dma),
 526                                            rx_ring->rx_buf_len, true);
 527
 528                                         if (rx_ring->rx_buf_len
 529                                                 < IXGBE_RXBUFFER_2048)
 530                                                 print_hex_dump(KERN_INFO, "",
 531                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 532                                                   phys_to_virt(
 533                                                     rx_buffer_info->page_dma +
 534                                                     rx_buffer_info->page_offset
 535                                                   ),
 536                                                   PAGE_SIZE/2, true);
 537                                 }
 538                         }
 539
 540                         if (i == rx_ring->next_to_use)
 541                                 pr_cont(" NTU\n");
 542                         else if (i == rx_ring->next_to_clean)
 543                                 pr_cont(" NTC\n");
 544                         else
 545                                 pr_cont("\n");
 546
 547                 }
 548         }
 549
 550 exit:
 551         return;
 552 }
 553
 554 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 555 {
 556         u32 ctrl_ext;
 557
 558         /* Let firmware take over control of h/w */
 559         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 560         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 561                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 562 }
 563
 564 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 565 {
 566         u32 ctrl_ext;
 567
 568         /* Let firmware know the driver has taken over */
 569         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 570         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 571                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 572 }
 573
 574 /*
 575  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 576  * @adapter: pointer to adapter struct
 577  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 578  * @queue: queue to map the corresponding interrupt to
 579  * @msix_vector: the vector to map to the corresponding queue
 580  *
 581  */
 582 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 583                            u8 queue, u8 msix_vector)
 584 {
 585         u32 ivar, index;
 586         struct ixgbe_hw *hw = &adapter->hw;
 587         switch (hw->mac.type) {
 588         case ixgbe_mac_82598EB:
 589                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 590                 if (direction == -1)
 591                         direction = 0;
 592                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 593                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 594                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 595                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 596                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 597                 break;
 598         case ixgbe_mac_82599EB:
 599         case ixgbe_mac_X540:
 600                 if (direction == -1) {
 601                         /* other causes */
 602                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 603                         index = ((queue & 1) * 8);
 604                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 605                         ivar &= ~(0xFF << index);
 606                         ivar |= (msix_vector << index);
 607                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 608                         break;
 609                 } else {
 610                         /* tx or rx causes */
 611                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 612                         index = ((16 * (queue & 1)) + (8 * direction));
 613                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 614                         ivar &= ~(0xFF << index);
 615                         ivar |= (msix_vector << index);
 616                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 617                         break;
 618                 }
 619         default:
 620                 break;
 621         }
 622 }
 623
 624 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 625                                           u64 qmask)
 626 {
 627         u32 mask;
 628
 629         switch (adapter->hw.mac.type) {
 630         case ixgbe_mac_82598EB:
 631                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 632                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 633                 break;
 634         case ixgbe_mac_82599EB:
 635         case ixgbe_mac_X540:
 636                 mask = (qmask & 0xFFFFFFFF);
 637                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 638                 mask = (qmask >> 32);
 639                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 640                 break;
 641         default:
 642                 break;
 643         }
 644 }
 645
 646 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
 647                                            struct ixgbe_tx_buffer *tx_buffer)
 648 {
 649         if (tx_buffer->dma) {
 650                 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
 651                         dma_unmap_page(ring->dev,
 652                                        tx_buffer->dma,
 653                                        tx_buffer->length,
 654                                        DMA_TO_DEVICE);
 655                 else
 656                         dma_unmap_single(ring->dev,
 657                                          tx_buffer->dma,
 658                                          tx_buffer->length,
 659                                          DMA_TO_DEVICE);
 660         }
 661         tx_buffer->dma = 0;
 662 }
 663
 664 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 665                                       struct ixgbe_tx_buffer *tx_buffer_info)
 666 {
 667         ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
 668         if (tx_buffer_info->skb)
 669                 dev_kfree_skb_any(tx_buffer_info->skb);
 670         tx_buffer_info->skb = NULL;
 671         /* tx_buffer_info must be completely set up in the transmit path */
 672 }
 673
 674 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 675 {
 676         struct ixgbe_hw *hw = &adapter->hw;
 677         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 678         u32 data = 0;
 679         u32 xoff[8] = {0};
 680         int i;
 681
 682         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 683             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 684                 switch (hw->mac.type) {
 685                 case ixgbe_mac_82598EB:
 686                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 687                         break;
 688                 default:
 689                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 690                 }
 691                 hwstats->lxoffrxc += data;
 692
 693                 /* refill credits (no tx hang) if we received xoff */
 694                 if (!data)
 695                         return;
 696
 697                 for (i = 0; i < adapter->num_tx_queues; i++)
 698                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 699                                   &adapter->tx_ring[i]->state);
 700                 return;
 701         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 702                 return;
 703
 704         /* update stats for each tc, only valid with PFC enabled */
 705         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 706                 switch (hw->mac.type) {
 707                 case ixgbe_mac_82598EB:
 708                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 709                         break;
 710                 default:
 711                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 712                 }
 713                 hwstats->pxoffrxc[i] += xoff[i];
 714         }
 715
 716         /* disarm tx queues that have received xoff frames */
 717         for (i = 0; i < adapter->num_tx_queues; i++) {
 718                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 719                 u8 tc = tx_ring->dcb_tc;
 720
 721                 if (xoff[tc])
 722                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 723         }
 724 }
 725
 726 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 727 {
 728         return ring->tx_stats.completed;
 729 }
 730
 731 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 732 {
 733         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 734         struct ixgbe_hw *hw = &adapter->hw;
 735
 736         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 737         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 738
 739         if (head != tail)
 740                 return (head < tail) ?
 741                         tail - head : (tail + ring->count - head);
 742
 743         return 0;
 744 }
 745
 746 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 747 {
 748         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 749         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 750         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 751         bool ret = false;
 752
 753         clear_check_for_tx_hang(tx_ring);
 754
 755         /*
 756          * Check for a hung queue, but be thorough. This verifies
 757          * that a transmit has been completed since the previous
 758          * check AND there is at least one packet pending. The
 759          * ARMED bit is set to indicate a potential hang. The
 760          * bit is cleared if a pause frame is received to remove
 761          * false hang detection due to PFC or 802.3x frames. By
 762          * requiring this to fail twice we avoid races with
 763          * pfc clearing the ARMED bit and conditions where we
 764          * run the check_tx_hang logic with a transmit completion
 765          * pending but without time to complete it yet.
 766          */
 767         if ((tx_done_old == tx_done) && tx_pending) {
 768                 /* make sure it is true for two checks in a row */
 769                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 770                                        &tx_ring->state);
 771         } else {
 772                 /* update completed stats and continue */
 773                 tx_ring->tx_stats.tx_done_old = tx_done;
 774                 /* reset the countdown */
 775                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 776         }
 777
 778         return ret;
 779 }
 780
 781 /**
 782  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 783  * @adapter: driver private struct
 784  **/
 785 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 786 {
 787
 788         /* Do the reset outside of interrupt context */
 789         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 790                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 791                 ixgbe_service_event_schedule(adapter);
 792         }
 793 }
 794
 795 /**
 796  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 797  * @q_vector: structure containing interrupt and ring information
 798  * @tx_ring: tx ring to clean
 799  **/
 800 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 801                                struct ixgbe_ring *tx_ring)
 802 {
 803         struct ixgbe_adapter *adapter = q_vector->adapter;
 804         struct ixgbe_tx_buffer *tx_buffer;
 805         union ixgbe_adv_tx_desc *tx_desc;
 806         unsigned int total_bytes = 0, total_packets = 0;
 807         u16 budget = q_vector->tx.work_limit;
 808         u16 i = tx_ring->next_to_clean;
 809
 810         tx_buffer = &tx_ring->tx_buffer_info[i];
 811         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 812
 813         for (; budget; budget--) {
 814                 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
 815
 816                 /* if next_to_watch is not set then there is no work pending */
 817                 if (!eop_desc)
 818                         break;
 819
 820                 /* if DD is not set pending work has not been completed */
 821                 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
 822                         break;
 823
 824                 /* count the packet as being completed */
 825                 tx_ring->tx_stats.completed++;
 826
 827                 /* clear next_to_watch to prevent false hangs */
 828                 tx_buffer->next_to_watch = NULL;
 829
 830                 /* prevent any other reads prior to eop_desc being verified */
 831                 rmb();
 832
 833                 do {
 834                         ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
 835                         tx_desc->wb.status = 0;
 836                         if (likely(tx_desc == eop_desc)) {
 837                                 eop_desc = NULL;
 838                                 dev_kfree_skb_any(tx_buffer->skb);
 839                                 tx_buffer->skb = NULL;
 840
 841                                 total_bytes += tx_buffer->bytecount;
 842                                 total_packets += tx_buffer->gso_segs;
 843                         }
 844
 845                         tx_buffer++;
 846                         tx_desc++;
 847                         i++;
 848                         if (unlikely(i == tx_ring->count)) {
 849                                 i = 0;
 850
 851                                 tx_buffer = tx_ring->tx_buffer_info;
 852                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
 853                         }
 854
 855                 } while (eop_desc);
 856         }
 857
 858         tx_ring->next_to_clean = i;
 859         u64_stats_update_begin(&tx_ring->syncp);
 860         tx_ring->stats.bytes += total_bytes;
 861         tx_ring->stats.packets += total_packets;
 862         u64_stats_update_end(&tx_ring->syncp);
 863         q_vector->tx.total_bytes += total_bytes;
 864         q_vector->tx.total_packets += total_packets;
 865
 866         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 867                 /* schedule immediate reset if we believe we hung */
 868                 struct ixgbe_hw *hw = &adapter->hw;
 869                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 870                 e_err(drv, "Detected Tx Unit Hang\n"
 871                         "  Tx Queue             <%d>\n"
 872                         "  TDH, TDT             <%x>, <%x>\n"
 873                         "  next_to_use          <%x>\n"
 874                         "  next_to_clean        <%x>\n"
 875                         "tx_buffer_info[next_to_clean]\n"
 876                         "  time_stamp           <%lx>\n"
 877                         "  jiffies              <%lx>\n",
 878                         tx_ring->queue_index,
 879                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 880                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 881                         tx_ring->next_to_use, i,
 882                         tx_ring->tx_buffer_info[i].time_stamp, jiffies);
 883
 884                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 885
 886                 e_info(probe,
 887                        "tx hang %d detected on queue %d, resetting adapter\n",
 888                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 889
 890                 /* schedule immediate reset if we believe we hung */
 891                 ixgbe_tx_timeout_reset(adapter);
 892
 893                 /* the adapter is about to reset, no point in enabling stuff */
 894                 return budget;
 895         }
 896
 897 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 898         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 899                      (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
 900                 /* Make sure that anybody stopping the queue after this
 901                  * sees the new next_to_clean.
 902                  */
 903                 smp_mb();
 904                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 905                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 906                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 907                         ++tx_ring->tx_stats.restart_queue;
 908                 }
 909         }
 910
 911         return budget;
 912 }
 913
 914 #ifdef CONFIG_IXGBE_DCA
 915 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 916                                 struct ixgbe_ring *rx_ring,
 917                                 int cpu)
 918 {
 919         struct ixgbe_hw *hw = &adapter->hw;
 920         u32 rxctrl;
 921         u8 reg_idx = rx_ring->reg_idx;
 922
 923         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 924         switch (hw->mac.type) {
 925         case ixgbe_mac_82598EB:
 926                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 927                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 928                 break;
 929         case ixgbe_mac_82599EB:
 930         case ixgbe_mac_X540:
 931                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 932                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 933                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 934                 break;
 935         default:
 936                 break;
 937         }
 938         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 939         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 940         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 941         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 942 }
 943
 944 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 945                                 struct ixgbe_ring *tx_ring,
 946                                 int cpu)
 947 {
 948         struct ixgbe_hw *hw = &adapter->hw;
 949         u32 txctrl;
 950         u8 reg_idx = tx_ring->reg_idx;
 951
 952         switch (hw->mac.type) {
 953         case ixgbe_mac_82598EB:
 954                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 955                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 956                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 957                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 958                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 959                 break;
 960         case ixgbe_mac_82599EB:
 961         case ixgbe_mac_X540:
 962                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 963                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 964                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 965                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 966                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 967                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 968                 break;
 969         default:
 970                 break;
 971         }
 972 }
 973
 974 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 975 {
 976         struct ixgbe_adapter *adapter = q_vector->adapter;
 977         int cpu = get_cpu();
 978         long r_idx;
 979         int i;
 980
 981         if (q_vector->cpu == cpu)
 982                 goto out_no_update;
 983
 984         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
 985         for (i = 0; i < q_vector->tx.count; i++) {
 986                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 987                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
 988                                       r_idx + 1);
 989         }
 990
 991         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
 992         for (i = 0; i < q_vector->rx.count; i++) {
 993                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 994                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
 995                                       r_idx + 1);
 996         }
 997
 998         q_vector->cpu = cpu;
 999 out_no_update:
1000         put_cpu();
1001 }
1002
1003 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1004 {
1005         int num_q_vectors;
1006         int i;
1007
1008         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1009                 return;
1010
1011         /* always use CB2 mode, difference is masked in the CB driver */
1012         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1013
1014         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1015                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1016         else
1017                 num_q_vectors = 1;
1018
1019         for (i = 0; i < num_q_vectors; i++) {
1020                 adapter->q_vector[i]->cpu = -1;
1021                 ixgbe_update_dca(adapter->q_vector[i]);
1022         }
1023 }
1024
1025 static int __ixgbe_notify_dca(struct device *dev, void *data)
1026 {
1027         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1028         unsigned long event = *(unsigned long *)data;
1029
1030         if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1031                 return 0;
1032
1033         switch (event) {
1034         case DCA_PROVIDER_ADD:
1035                 /* if we're already enabled, don't do it again */
1036                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1037                         break;
1038                 if (dca_add_requester(dev) == 0) {
1039                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1040                         ixgbe_setup_dca(adapter);
1041                         break;
1042                 }
1043                 /* Fall Through since DCA is disabled. */
1044         case DCA_PROVIDER_REMOVE:
1045                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1046                         dca_remove_requester(dev);
1047                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1048                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1049                 }
1050                 break;
1051         }
1052
1053         return 0;
1054 }
1055 #endif /* CONFIG_IXGBE_DCA */
1056
1057 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1058                                  struct sk_buff *skb)
1059 {
1060         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1061 }
1062
1063 /**
1064  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1065  * @adapter: address of board private structure
1066  * @rx_desc: advanced rx descriptor
1067  *
1068  * Returns : true if it is FCoE pkt
1069  */
1070 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1071                                     union ixgbe_adv_rx_desc *rx_desc)
1072 {
1073         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1074
1075         return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1076                ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1077                 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1078                              IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1079 }
1080
1081 /**
1082  * ixgbe_receive_skb - Send a completed packet up the stack
1083  * @adapter: board private structure
1084  * @skb: packet to send up
1085  * @status: hardware indication of status of receive
1086  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1087  * @rx_desc: rx descriptor
1088  **/
1089 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1090                               struct sk_buff *skb, u8 status,
1091                               struct ixgbe_ring *ring,
1092                               union ixgbe_adv_rx_desc *rx_desc)
1093 {
1094         struct ixgbe_adapter *adapter = q_vector->adapter;
1095         struct napi_struct *napi = &q_vector->napi;
1096         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1097         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1098
1099         if (is_vlan && (tag & VLAN_VID_MASK))
1100                 __vlan_hwaccel_put_tag(skb, tag);
1101
1102         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1103                 napi_gro_receive(napi, skb);
1104         else
1105                 netif_rx(skb);
1106 }
1107
1108 /**
1109  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1110  * @adapter: address of board private structure
1111  * @status_err: hardware indication of status of receive
1112  * @skb: skb currently being received and modified
1113  * @status_err: status error value of last descriptor in packet
1114  **/
1115 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1116                                      union ixgbe_adv_rx_desc *rx_desc,
1117                                      struct sk_buff *skb,
1118                                      u32 status_err)
1119 {
1120         skb->ip_summed = CHECKSUM_NONE;
1121
1122         /* Rx csum disabled */
1123         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1124                 return;
1125
1126         /* if IP and error */
1127         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1128             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1129                 adapter->hw_csum_rx_error++;
1130                 return;
1131         }
1132
1133         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1134                 return;
1135
1136         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1137                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1138
1139                 /*
1140                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1141                  * checksum errors.
1142                  */
1143                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1144                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1145                         return;
1146
1147                 adapter->hw_csum_rx_error++;
1148                 return;
1149         }
1150
1151         /* It must be a TCP or UDP packet with a valid checksum */
1152         skb->ip_summed = CHECKSUM_UNNECESSARY;
1153 }
1154
1155 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1156 {
1157         /*
1158          * Force memory writes to complete before letting h/w
1159          * know there are new descriptors to fetch.  (Only
1160          * applicable for weak-ordered memory model archs,
1161          * such as IA-64).
1162          */
1163         wmb();
1164         writel(val, rx_ring->tail);
1165 }
1166
1167 /**
1168  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1169  * @rx_ring: ring to place buffers on
1170  * @cleaned_count: number of buffers to replace
1171  **/
1172 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1173 {
1174         union ixgbe_adv_rx_desc *rx_desc;
1175         struct ixgbe_rx_buffer *bi;
1176         struct sk_buff *skb;
1177         u16 i = rx_ring->next_to_use;
1178
1179         /* do nothing if no valid netdev defined */
1180         if (!rx_ring->netdev)
1181                 return;
1182
1183         while (cleaned_count--) {
1184                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1185                 bi = &rx_ring->rx_buffer_info[i];
1186                 skb = bi->skb;
1187
1188                 if (!skb) {
1189                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1190                                                         rx_ring->rx_buf_len);
1191                         if (!skb) {
1192                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1193                                 goto no_buffers;
1194                         }
1195                         /* initialize queue mapping */
1196                         skb_record_rx_queue(skb, rx_ring->queue_index);
1197                         bi->skb = skb;
1198                 }
1199
1200                 if (!bi->dma) {
1201                         bi->dma = dma_map_single(rx_ring->dev,
1202                                                  skb->data,
1203                                                  rx_ring->rx_buf_len,
1204                                                  DMA_FROM_DEVICE);
1205                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1206                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1207                                 bi->dma = 0;
1208                                 goto no_buffers;
1209                         }
1210                 }
1211
1212                 if (ring_is_ps_enabled(rx_ring)) {
1213                         if (!bi->page) {
1214                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1215                                 if (!bi->page) {
1216                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1217                                         goto no_buffers;
1218                                 }
1219                         }
1220
1221                         if (!bi->page_dma) {
1222                                 /* use a half page if we're re-using */
1223                                 bi->page_offset ^= PAGE_SIZE / 2;
1224                                 bi->page_dma = dma_map_page(rx_ring->dev,
1225                                                             bi->page,
1226                                                             bi->page_offset,
1227                                                             PAGE_SIZE / 2,
1228                                                             DMA_FROM_DEVICE);
1229                                 if (dma_mapping_error(rx_ring->dev,
1230                                                       bi->page_dma)) {
1231                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1232                                         bi->page_dma = 0;
1233                                         goto no_buffers;
1234                                 }
1235                         }
1236
1237                         /* Refresh the desc even if buffer_addrs didn't change
1238                          * because each write-back erases this info. */
1239                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1240                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1241                 } else {
1242                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1243                         rx_desc->read.hdr_addr = 0;
1244                 }
1245
1246                 i++;
1247                 if (i == rx_ring->count)
1248                         i = 0;
1249         }
1250
1251 no_buffers:
1252         if (rx_ring->next_to_use != i) {
1253                 rx_ring->next_to_use = i;
1254                 ixgbe_release_rx_desc(rx_ring, i);
1255         }
1256 }
1257
1258 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1259 {
1260         /* HW will not DMA in data larger than the given buffer, even if it
1261          * parses the (NFS, of course) header to be larger.  In that case, it
1262          * fills the header buffer and spills the rest into the page.
1263          */
1264         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1265         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1266                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1267         if (hlen > IXGBE_RX_HDR_SIZE)
1268                 hlen = IXGBE_RX_HDR_SIZE;
1269         return hlen;
1270 }
1271
1272 /**
1273  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1274  * @skb: pointer to the last skb in the rsc queue
1275  *
1276  * This function changes a queue full of hw rsc buffers into a completed
1277  * packet.  It uses the ->prev pointers to find the first packet and then
1278  * turns it into the frag list owner.
1279  **/
1280 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1281 {
1282         unsigned int frag_list_size = 0;
1283         unsigned int skb_cnt = 1;
1284
1285         while (skb->prev) {
1286                 struct sk_buff *prev = skb->prev;
1287                 frag_list_size += skb->len;
1288                 skb->prev = NULL;
1289                 skb = prev;
1290                 skb_cnt++;
1291         }
1292
1293         skb_shinfo(skb)->frag_list = skb->next;
1294         skb->next = NULL;
1295         skb->len += frag_list_size;
1296         skb->data_len += frag_list_size;
1297         skb->truesize += frag_list_size;
1298         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1299
1300         return skb;
1301 }
1302
1303 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1304 {
1305         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1306                 IXGBE_RXDADV_RSCCNT_MASK);
1307 }
1308
1309 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1310                                struct ixgbe_ring *rx_ring,
1311                                int *work_done, int work_to_do)
1312 {
1313         struct ixgbe_adapter *adapter = q_vector->adapter;
1314         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1315         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1316         struct sk_buff *skb;
1317         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1318         const int current_node = numa_node_id();
1319 #ifdef IXGBE_FCOE
1320         int ddp_bytes = 0;
1321 #endif /* IXGBE_FCOE */
1322         u32 staterr;
1323         u16 i;
1324         u16 cleaned_count = 0;
1325         bool pkt_is_rsc = false;
1326
1327         i = rx_ring->next_to_clean;
1328         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1329         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1330
1331         while (staterr & IXGBE_RXD_STAT_DD) {
1332                 u32 upper_len = 0;
1333
1334                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1335
1336                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1337
1338                 skb = rx_buffer_info->skb;
1339                 rx_buffer_info->skb = NULL;
1340                 prefetch(skb->data);
1341
1342                 if (ring_is_rsc_enabled(rx_ring))
1343                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1344
1345                 /* if this is a skb from previous receive DMA will be 0 */
1346                 if (rx_buffer_info->dma) {
1347                         u16 hlen;
1348                         if (pkt_is_rsc &&
1349                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1350                             !skb->prev) {
1351                                 /*
1352                                  * When HWRSC is enabled, delay unmapping
1353                                  * of the first packet. It carries the
1354                                  * header information, HW may still
1355                                  * access the header after the writeback.
1356                                  * Only unmap it when EOP is reached
1357                                  */
1358                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1359                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1360                         } else {
1361                                 dma_unmap_single(rx_ring->dev,
1362                                                  rx_buffer_info->dma,
1363                                                  rx_ring->rx_buf_len,
1364                                                  DMA_FROM_DEVICE);
1365                         }
1366                         rx_buffer_info->dma = 0;
1367
1368                         if (ring_is_ps_enabled(rx_ring)) {
1369                                 hlen = ixgbe_get_hlen(rx_desc);
1370                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1371                         } else {
1372                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1373                         }
1374
1375                         skb_put(skb, hlen);
1376                 } else {
1377                         /* assume packet split since header is unmapped */
1378                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1379                 }
1380
1381                 if (upper_len) {
1382                         dma_unmap_page(rx_ring->dev,
1383                                        rx_buffer_info->page_dma,
1384                                        PAGE_SIZE / 2,
1385                                        DMA_FROM_DEVICE);
1386                         rx_buffer_info->page_dma = 0;
1387                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1388                                            rx_buffer_info->page,
1389                                            rx_buffer_info->page_offset,
1390                                            upper_len);
1391
1392                         if ((page_count(rx_buffer_info->page) == 1) &&
1393                             (page_to_nid(rx_buffer_info->page) == current_node))
1394                                 get_page(rx_buffer_info->page);
1395                         else
1396                                 rx_buffer_info->page = NULL;
1397
1398                         skb->len += upper_len;
1399                         skb->data_len += upper_len;
1400                         skb->truesize += upper_len;
1401                 }
1402
1403                 i++;
1404                 if (i == rx_ring->count)
1405                         i = 0;
1406
1407                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1408                 prefetch(next_rxd);
1409                 cleaned_count++;
1410
1411                 if (pkt_is_rsc) {
1412                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1413                                      IXGBE_RXDADV_NEXTP_SHIFT;
1414                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1415                 } else {
1416                         next_buffer = &rx_ring->rx_buffer_info[i];
1417                 }
1418
1419                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1420                         if (ring_is_ps_enabled(rx_ring)) {
1421                                 rx_buffer_info->skb = next_buffer->skb;
1422                                 rx_buffer_info->dma = next_buffer->dma;
1423                                 next_buffer->skb = skb;
1424                                 next_buffer->dma = 0;
1425                         } else {
1426                                 skb->next = next_buffer->skb;
1427                                 skb->next->prev = skb;
1428                         }
1429                         rx_ring->rx_stats.non_eop_descs++;
1430                         goto next_desc;
1431                 }
1432
1433                 if (skb->prev) {
1434                         skb = ixgbe_transform_rsc_queue(skb);
1435                         /* if we got here without RSC the packet is invalid */
1436                         if (!pkt_is_rsc) {
1437                                 __pskb_trim(skb, 0);
1438                                 rx_buffer_info->skb = skb;
1439                                 goto next_desc;
1440                         }
1441                 }
1442
1443                 if (ring_is_rsc_enabled(rx_ring)) {
1444                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1445                                 dma_unmap_single(rx_ring->dev,
1446                                                  IXGBE_RSC_CB(skb)->dma,
1447                                                  rx_ring->rx_buf_len,
1448                                                  DMA_FROM_DEVICE);
1449                                 IXGBE_RSC_CB(skb)->dma = 0;
1450                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1451                         }
1452                 }
1453                 if (pkt_is_rsc) {
1454                         if (ring_is_ps_enabled(rx_ring))
1455                                 rx_ring->rx_stats.rsc_count +=
1456                                         skb_shinfo(skb)->nr_frags;
1457                         else
1458                                 rx_ring->rx_stats.rsc_count +=
1459                                         IXGBE_RSC_CB(skb)->skb_cnt;
1460                         rx_ring->rx_stats.rsc_flush++;
1461                 }
1462
1463                 /* ERR_MASK will only have valid bits if EOP set */
1464                 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1465                         dev_kfree_skb_any(skb);
1466                         goto next_desc;
1467                 }
1468
1469                 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1470                 if (adapter->netdev->features & NETIF_F_RXHASH)
1471                         ixgbe_rx_hash(rx_desc, skb);
1472
1473                 /* probably a little skewed due to removing CRC */
1474                 total_rx_bytes += skb->len;
1475                 total_rx_packets++;
1476
1477                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1478 #ifdef IXGBE_FCOE
1479                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1480                 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1481                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1482                                                    staterr);
1483                         if (!ddp_bytes) {
1484                                 dev_kfree_skb_any(skb);
1485                                 goto next_desc;
1486                         }
1487                 }
1488 #endif /* IXGBE_FCOE */
1489                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1490
1491 next_desc:
1492                 rx_desc->wb.upper.status_error = 0;
1493
1494                 (*work_done)++;
1495                 if (*work_done >= work_to_do)
1496                         break;
1497
1498                 /* return some buffers to hardware, one at a time is too slow */
1499                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1500                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1501                         cleaned_count = 0;
1502                 }
1503
1504                 /* use prefetched values */
1505                 rx_desc = next_rxd;
1506                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1507         }
1508
1509         rx_ring->next_to_clean = i;
1510         cleaned_count = ixgbe_desc_unused(rx_ring);
1511
1512         if (cleaned_count)
1513                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1514
1515 #ifdef IXGBE_FCOE
1516         /* include DDPed FCoE data */
1517         if (ddp_bytes > 0) {
1518                 unsigned int mss;
1519
1520                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1521                         sizeof(struct fc_frame_header) -
1522                         sizeof(struct fcoe_crc_eof);
1523                 if (mss > 512)
1524                         mss &= ~511;
1525                 total_rx_bytes += ddp_bytes;
1526                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1527         }
1528 #endif /* IXGBE_FCOE */
1529
1530         u64_stats_update_begin(&rx_ring->syncp);
1531         rx_ring->stats.packets += total_rx_packets;
1532         rx_ring->stats.bytes += total_rx_bytes;
1533         u64_stats_update_end(&rx_ring->syncp);
1534         q_vector->rx.total_packets += total_rx_packets;
1535         q_vector->rx.total_bytes += total_rx_bytes;
1536 }
1537
1538 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1539 /**
1540  * ixgbe_configure_msix - Configure MSI-X hardware
1541  * @adapter: board private structure
1542  *
1543  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1544  * interrupts.
1545  **/
1546 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1547 {
1548         struct ixgbe_q_vector *q_vector;
1549         int i, q_vectors, v_idx, r_idx;
1550         u32 mask;
1551
1552         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1553
1554         /*
1555          * Populate the IVAR table and set the ITR values to the
1556          * corresponding register.
1557          */
1558         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1559                 q_vector = adapter->q_vector[v_idx];
1560                 /* XXX for_each_set_bit(...) */
1561                 r_idx = find_first_bit(q_vector->rx.idx,
1562                                        adapter->num_rx_queues);
1563
1564                 for (i = 0; i < q_vector->rx.count; i++) {
1565                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1566                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1567                         r_idx = find_next_bit(q_vector->rx.idx,
1568                                               adapter->num_rx_queues,
1569                                               r_idx + 1);
1570                 }
1571                 r_idx = find_first_bit(q_vector->tx.idx,
1572                                        adapter->num_tx_queues);
1573
1574                 for (i = 0; i < q_vector->tx.count; i++) {
1575                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1576                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1577                         r_idx = find_next_bit(q_vector->tx.idx,
1578                                               adapter->num_tx_queues,
1579                                               r_idx + 1);
1580                 }
1581
1582                 if (q_vector->tx.count && !q_vector->rx.count)
1583                         /* tx only */
1584                         q_vector->eitr = adapter->tx_eitr_param;
1585                 else if (q_vector->rx.count)
1586                         /* rx or mixed */
1587                         q_vector->eitr = adapter->rx_eitr_param;
1588
1589                 ixgbe_write_eitr(q_vector);
1590                 /* If ATR is enabled, set interrupt affinity */
1591                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
1592                         /*
1593                          * Allocate the affinity_hint cpumask, assign the mask
1594                          * for this vector, and set our affinity_hint for
1595                          * this irq.
1596                          */
1597                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1598                                                GFP_KERNEL))
1599                                 return;
1600                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1601                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1602                                               q_vector->affinity_mask);
1603                 }
1604         }
1605
1606         switch (adapter->hw.mac.type) {
1607         case ixgbe_mac_82598EB:
1608                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1609                                v_idx);
1610                 break;
1611         case ixgbe_mac_82599EB:
1612         case ixgbe_mac_X540:
1613                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1614                 break;
1615
1616         default:
1617                 break;
1618         }
1619         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1620
1621         /* set up to autoclear timer, and the vectors */
1622         mask = IXGBE_EIMS_ENABLE_MASK;
1623         if (adapter->num_vfs)
1624                 mask &= ~(IXGBE_EIMS_OTHER |
1625                           IXGBE_EIMS_MAILBOX |
1626                           IXGBE_EIMS_LSC);
1627         else
1628                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1629         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1630 }
1631
1632 enum latency_range {
1633         lowest_latency = 0,
1634         low_latency = 1,
1635         bulk_latency = 2,
1636         latency_invalid = 255
1637 };
1638
1639 /**
1640  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1641  * @q_vector: structure containing interrupt and ring information
1642  * @ring_container: structure containing ring performance data
1643  *
1644  *      Stores a new ITR value based on packets and byte
1645  *      counts during the last interrupt.  The advantage of per interrupt
1646  *      computation is faster updates and more accurate ITR for the current
1647  *      traffic pattern.  Constants in this function were computed
1648  *      based on theoretical maximum wire speed and thresholds were set based
1649  *      on testing data as well as attempting to minimize response time
1650  *      while increasing bulk throughput.
1651  *      this functionality is controlled by the InterruptThrottleRate module
1652  *      parameter (see ixgbe_param.c)
1653  **/
1654 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1655                              struct ixgbe_ring_container *ring_container)
1656 {
1657         u64 bytes_perint;
1658         struct ixgbe_adapter *adapter = q_vector->adapter;
1659         int bytes = ring_container->total_bytes;
1660         int packets = ring_container->total_packets;
1661         u32 timepassed_us;
1662         u8 itr_setting = ring_container->itr;
1663
1664         if (packets == 0)
1665                 return;
1666
1667         /* simple throttlerate management
1668          *    0-20MB/s lowest (100000 ints/s)
1669          *   20-100MB/s low   (20000 ints/s)
1670          *  100-1249MB/s bulk (8000 ints/s)
1671          */
1672         /* what was last interrupt timeslice? */
1673         timepassed_us = 1000000/q_vector->eitr;
1674         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1675
1676         switch (itr_setting) {
1677         case lowest_latency:
1678                 if (bytes_perint > adapter->eitr_low)
1679                         itr_setting = low_latency;
1680                 break;
1681         case low_latency:
1682                 if (bytes_perint > adapter->eitr_high)
1683                         itr_setting = bulk_latency;
1684                 else if (bytes_perint <= adapter->eitr_low)
1685                         itr_setting = lowest_latency;
1686                 break;
1687         case bulk_latency:
1688                 if (bytes_perint <= adapter->eitr_high)
1689                         itr_setting = low_latency;
1690                 break;
1691         }
1692
1693         /* clear work counters since we have the values we need */
1694         ring_container->total_bytes = 0;
1695         ring_container->total_packets = 0;
1696
1697         /* write updated itr to ring container */
1698         ring_container->itr = itr_setting;
1699 }
1700
1701 /**
1702  * ixgbe_write_eitr - write EITR register in hardware specific way
1703  * @q_vector: structure containing interrupt and ring information
1704  *
1705  * This function is made to be called by ethtool and by the driver
1706  * when it needs to update EITR registers at runtime.  Hardware
1707  * specific quirks/differences are taken care of here.
1708  */
1709 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1710 {
1711         struct ixgbe_adapter *adapter = q_vector->adapter;
1712         struct ixgbe_hw *hw = &adapter->hw;
1713         int v_idx = q_vector->v_idx;
1714         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1715
1716         switch (adapter->hw.mac.type) {
1717         case ixgbe_mac_82598EB:
1718                 /* must write high and low 16 bits to reset counter */
1719                 itr_reg |= (itr_reg << 16);
1720                 break;
1721         case ixgbe_mac_82599EB:
1722         case ixgbe_mac_X540:
1723                 /*
1724                  * 82599 and X540 can support a value of zero, so allow it for
1725                  * max interrupt rate, but there is an errata where it can
1726                  * not be zero with RSC
1727                  */
1728                 if (itr_reg == 8 &&
1729                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1730                         itr_reg = 0;
1731
1732                 /*
1733                  * set the WDIS bit to not clear the timer bits and cause an
1734                  * immediate assertion of the interrupt
1735                  */
1736                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1737                 break;
1738         default:
1739                 break;
1740         }
1741         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1742 }
1743
1744 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1745 {
1746         u32 new_itr = q_vector->eitr;
1747         u8 current_itr;
1748
1749         ixgbe_update_itr(q_vector, &q_vector->tx);
1750         ixgbe_update_itr(q_vector, &q_vector->rx);
1751
1752         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1753
1754         switch (current_itr) {
1755         /* counts and packets in update_itr are dependent on these numbers */
1756         case lowest_latency:
1757                 new_itr = 100000;
1758                 break;
1759         case low_latency:
1760                 new_itr = 20000; /* aka hwitr = ~200 */
1761                 break;
1762         case bulk_latency:
1763                 new_itr = 8000;
1764                 break;
1765         default:
1766                 break;
1767         }
1768
1769         if (new_itr != q_vector->eitr) {
1770                 /* do an exponential smoothing */
1771                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1772
1773                 /* save the algorithm value here */
1774                 q_vector->eitr = new_itr;
1775
1776                 ixgbe_write_eitr(q_vector);
1777         }
1778 }
1779
1780 /**
1781  * ixgbe_check_overtemp_subtask - check for over tempurature
1782  * @adapter: pointer to adapter
1783  **/
1784 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1785 {
1786         struct ixgbe_hw *hw = &adapter->hw;
1787         u32 eicr = adapter->interrupt_event;
1788
1789         if (test_bit(__IXGBE_DOWN, &adapter->state))
1790                 return;
1791
1792         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1793             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1794                 return;
1795
1796         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1797
1798         switch (hw->device_id) {
1799         case IXGBE_DEV_ID_82599_T3_LOM:
1800                 /*
1801                  * Since the warning interrupt is for both ports
1802                  * we don't have to check if:
1803                  *  - This interrupt wasn't for our port.
1804                  *  - We may have missed the interrupt so always have to
1805                  *    check if we  got a LSC
1806                  */
1807                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1808                     !(eicr & IXGBE_EICR_LSC))
1809                         return;
1810
1811                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1812                         u32 autoneg;
1813                         bool link_up = false;
1814
1815                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1816
1817                         if (link_up)
1818                                 return;
1819                 }
1820
1821                 /* Check if this is not due to overtemp */
1822                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1823                         return;
1824
1825                 break;
1826         default:
1827                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1828                         return;
1829                 break;
1830         }
1831         e_crit(drv,
1832                "Network adapter has been stopped because it has over heated. "
1833                "Restart the computer. If the problem persists, "
1834                "power off the system and replace the adapter\n");
1835
1836         adapter->interrupt_event = 0;
1837 }
1838
1839 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1840 {
1841         struct ixgbe_hw *hw = &adapter->hw;
1842
1843         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1844             (eicr & IXGBE_EICR_GPI_SDP1)) {
1845                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1846                 /* write to clear the interrupt */
1847                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1848         }
1849 }
1850
1851 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1852 {
1853         struct ixgbe_hw *hw = &adapter->hw;
1854
1855         if (eicr & IXGBE_EICR_GPI_SDP2) {
1856                 /* Clear the interrupt */
1857                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1858                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1859                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1860                         ixgbe_service_event_schedule(adapter);
1861                 }
1862         }
1863
1864         if (eicr & IXGBE_EICR_GPI_SDP1) {
1865                 /* Clear the interrupt */
1866                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1867                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1868                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1869                         ixgbe_service_event_schedule(adapter);
1870                 }
1871         }
1872 }
1873
1874 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1875 {
1876         struct ixgbe_hw *hw = &adapter->hw;
1877
1878         adapter->lsc_int++;
1879         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1880         adapter->link_check_timeout = jiffies;
1881         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1882                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1883                 IXGBE_WRITE_FLUSH(hw);
1884                 ixgbe_service_event_schedule(adapter);
1885         }
1886 }
1887
1888 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1889 {
1890         struct ixgbe_adapter *adapter = data;
1891         struct ixgbe_hw *hw = &adapter->hw;
1892         u32 eicr;
1893
1894         /*
1895          * Workaround for Silicon errata.  Use clear-by-write instead
1896          * of clear-by-read.  Reading with EICS will return the
1897          * interrupt causes without clearing, which later be done
1898          * with the write to EICR.
1899          */
1900         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1901         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1902
1903         if (eicr & IXGBE_EICR_LSC)
1904                 ixgbe_check_lsc(adapter);
1905
1906         if (eicr & IXGBE_EICR_MAILBOX)
1907                 ixgbe_msg_task(adapter);
1908
1909         switch (hw->mac.type) {
1910         case ixgbe_mac_82599EB:
1911         case ixgbe_mac_X540:
1912                 /* Handle Flow Director Full threshold interrupt */
1913                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1914                         int reinit_count = 0;
1915                         int i;
1916                         for (i = 0; i < adapter->num_tx_queues; i++) {
1917                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1918                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1919                                                        &ring->state))
1920                                         reinit_count++;
1921                         }
1922                         if (reinit_count) {
1923                                 /* no more flow director interrupts until after init */
1924                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1925                                 eicr &= ~IXGBE_EICR_FLOW_DIR;
1926                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1927                                 ixgbe_service_event_schedule(adapter);
1928                         }
1929                 }
1930                 ixgbe_check_sfp_event(adapter, eicr);
1931                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1932                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1933                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1934                                 adapter->interrupt_event = eicr;
1935                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1936                                 ixgbe_service_event_schedule(adapter);
1937                         }
1938                 }
1939                 break;
1940         default:
1941                 break;
1942         }
1943
1944         ixgbe_check_fan_failure(adapter, eicr);
1945
1946         /* re-enable the original interrupt state, no lsc, no queues */
1947         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1948                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1949                                 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1950
1951         return IRQ_HANDLED;
1952 }
1953
1954 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1955                                            u64 qmask)
1956 {
1957         u32 mask;
1958         struct ixgbe_hw *hw = &adapter->hw;
1959
1960         switch (hw->mac.type) {
1961         case ixgbe_mac_82598EB:
1962                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1963                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1964                 break;
1965         case ixgbe_mac_82599EB:
1966         case ixgbe_mac_X540:
1967                 mask = (qmask & 0xFFFFFFFF);
1968                 if (mask)
1969                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1970                 mask = (qmask >> 32);
1971                 if (mask)
1972                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1973                 break;
1974         default:
1975                 break;
1976         }
1977         /* skip the flush */
1978 }
1979
1980 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1981                                             u64 qmask)
1982 {
1983         u32 mask;
1984         struct ixgbe_hw *hw = &adapter->hw;
1985
1986         switch (hw->mac.type) {
1987         case ixgbe_mac_82598EB:
1988                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1989                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1990                 break;
1991         case ixgbe_mac_82599EB:
1992         case ixgbe_mac_X540:
1993                 mask = (qmask & 0xFFFFFFFF);
1994                 if (mask)
1995                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1996                 mask = (qmask >> 32);
1997                 if (mask)
1998                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1999                 break;
2000         default:
2001                 break;
2002         }
2003         /* skip the flush */
2004 }
2005
2006 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2007 {
2008         struct ixgbe_q_vector *q_vector = data;
2009         struct ixgbe_adapter  *adapter = q_vector->adapter;
2010         struct ixgbe_ring     *tx_ring;
2011         int i, r_idx;
2012
2013         if (!q_vector->tx.count)
2014                 return IRQ_HANDLED;
2015
2016         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2017         for (i = 0; i < q_vector->tx.count; i++) {
2018                 tx_ring = adapter->tx_ring[r_idx];
2019                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2020                                       r_idx + 1);
2021         }
2022
2023         /* EIAM disabled interrupts (on this vector) for us */
2024         napi_schedule(&q_vector->napi);
2025
2026         return IRQ_HANDLED;
2027 }
2028
2029 /**
2030  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2031  * @irq: unused
2032  * @data: pointer to our q_vector struct for this interrupt vector
2033  **/
2034 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2035 {
2036         struct ixgbe_q_vector *q_vector = data;
2037         struct ixgbe_adapter  *adapter = q_vector->adapter;
2038         struct ixgbe_ring  *rx_ring;
2039         int r_idx;
2040         int i;
2041
2042 #ifdef CONFIG_IXGBE_DCA
2043         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2044                 ixgbe_update_dca(q_vector);
2045 #endif
2046
2047         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2048         for (i = 0; i < q_vector->rx.count; i++) {
2049                 rx_ring = adapter->rx_ring[r_idx];
2050                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2051                                       r_idx + 1);
2052         }
2053
2054         if (!q_vector->rx.count)
2055                 return IRQ_HANDLED;
2056
2057         /* EIAM disabled interrupts (on this vector) for us */
2058         napi_schedule(&q_vector->napi);
2059
2060         return IRQ_HANDLED;
2061 }
2062
2063 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2064 {
2065         struct ixgbe_q_vector *q_vector = data;
2066         struct ixgbe_adapter  *adapter = q_vector->adapter;
2067         struct ixgbe_ring  *ring;
2068         int r_idx;
2069         int i;
2070
2071         if (!q_vector->tx.count && !q_vector->rx.count)
2072                 return IRQ_HANDLED;
2073
2074         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2075         for (i = 0; i < q_vector->tx.count; i++) {
2076                 ring = adapter->tx_ring[r_idx];
2077                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2078                                       r_idx + 1);
2079         }
2080
2081         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2082         for (i = 0; i < q_vector->rx.count; i++) {
2083                 ring = adapter->rx_ring[r_idx];
2084                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2085                                       r_idx + 1);
2086         }
2087
2088         /* EIAM disabled interrupts (on this vector) for us */
2089         napi_schedule(&q_vector->napi);
2090
2091         return IRQ_HANDLED;
2092 }
2093
2094 /**
2095  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2096  * @napi: napi struct with our devices info in it
2097  * @budget: amount of work driver is allowed to do this pass, in packets
2098  *
2099  * This function is optimized for cleaning one queue only on a single
2100  * q_vector!!!
2101  **/
2102 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2103 {
2104         struct ixgbe_q_vector *q_vector =
2105                                container_of(napi, struct ixgbe_q_vector, napi);
2106         struct ixgbe_adapter *adapter = q_vector->adapter;
2107         struct ixgbe_ring *rx_ring = NULL;
2108         int work_done = 0;
2109         long r_idx;
2110
2111 #ifdef CONFIG_IXGBE_DCA
2112         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2113                 ixgbe_update_dca(q_vector);
2114 #endif
2115
2116         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2117         rx_ring = adapter->rx_ring[r_idx];
2118
2119         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2120
2121         /* If all Rx work done, exit the polling mode */
2122         if (work_done < budget) {
2123                 napi_complete(napi);
2124                 if (adapter->rx_itr_setting & 1)
2125                         ixgbe_set_itr(q_vector);
2126                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2127                         ixgbe_irq_enable_queues(adapter,
2128                                                 ((u64)1 << q_vector->v_idx));
2129         }
2130
2131         return work_done;
2132 }
2133
2134 /**
2135  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2136  * @napi: napi struct with our devices info in it
2137  * @budget: amount of work driver is allowed to do this pass, in packets
2138  *
2139  * This function will clean more than one rx queue associated with a
2140  * q_vector.
2141  **/
2142 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2143 {
2144         struct ixgbe_q_vector *q_vector =
2145                                container_of(napi, struct ixgbe_q_vector, napi);
2146         struct ixgbe_adapter *adapter = q_vector->adapter;
2147         struct ixgbe_ring *ring = NULL;
2148         int work_done = 0, i;
2149         long r_idx;
2150         bool tx_clean_complete = true;
2151
2152 #ifdef CONFIG_IXGBE_DCA
2153         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2154                 ixgbe_update_dca(q_vector);
2155 #endif
2156
2157         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2158         for (i = 0; i < q_vector->tx.count; i++) {
2159                 ring = adapter->tx_ring[r_idx];
2160                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2161                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2162                                       r_idx + 1);
2163         }
2164
2165         /* attempt to distribute budget to each queue fairly, but don't allow
2166          * the budget to go below 1 because we'll exit polling */
2167         budget /= (q_vector->rx.count ?: 1);
2168         budget = max(budget, 1);
2169         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2170         for (i = 0; i < q_vector->rx.count; i++) {
2171                 ring = adapter->rx_ring[r_idx];
2172                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2173                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2174                                       r_idx + 1);
2175         }
2176
2177         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2178         ring = adapter->rx_ring[r_idx];
2179         /* If all Rx work done, exit the polling mode */
2180         if (work_done < budget) {
2181                 napi_complete(napi);
2182                 if (adapter->rx_itr_setting & 1)
2183                         ixgbe_set_itr(q_vector);
2184                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2185                         ixgbe_irq_enable_queues(adapter,
2186                                                 ((u64)1 << q_vector->v_idx));
2187                 return 0;
2188         }
2189
2190         return work_done;
2191 }
2192
2193 /**
2194  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2195  * @napi: napi struct with our devices info in it
2196  * @budget: amount of work driver is allowed to do this pass, in packets
2197  *
2198  * This function is optimized for cleaning one queue only on a single
2199  * q_vector!!!
2200  **/
2201 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2202 {
2203         struct ixgbe_q_vector *q_vector =
2204                                container_of(napi, struct ixgbe_q_vector, napi);
2205         struct ixgbe_adapter *adapter = q_vector->adapter;
2206         struct ixgbe_ring *tx_ring = NULL;
2207         int work_done = 0;
2208         long r_idx;
2209
2210 #ifdef CONFIG_IXGBE_DCA
2211         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2212                 ixgbe_update_dca(q_vector);
2213 #endif
2214
2215         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2216         tx_ring = adapter->tx_ring[r_idx];
2217
2218         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2219                 work_done = budget;
2220
2221         /* If all Tx work done, exit the polling mode */
2222         if (work_done < budget) {
2223                 napi_complete(napi);
2224                 if (adapter->tx_itr_setting & 1)
2225                         ixgbe_set_itr(q_vector);
2226                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2227                         ixgbe_irq_enable_queues(adapter,
2228                                                 ((u64)1 << q_vector->v_idx));
2229         }
2230
2231         return work_done;
2232 }
2233
2234 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2235                                      int r_idx)
2236 {
2237         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2238         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2239
2240         set_bit(r_idx, q_vector->rx.idx);
2241         q_vector->rx.count++;
2242         rx_ring->q_vector = q_vector;
2243 }
2244
2245 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2246                                      int t_idx)
2247 {
2248         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2249         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2250
2251         set_bit(t_idx, q_vector->tx.idx);
2252         q_vector->tx.count++;
2253         tx_ring->q_vector = q_vector;
2254         q_vector->tx.work_limit = a->tx_work_limit;
2255 }
2256
2257 /**
2258  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2259  * @adapter: board private structure to initialize
2260  *
2261  * This function maps descriptor rings to the queue-specific vectors
2262  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2263  * one vector per ring/queue, but on a constrained vector budget, we
2264  * group the rings as "efficiently" as possible.  You would add new
2265  * mapping configurations in here.
2266  **/
2267 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2268 {
2269         int q_vectors;
2270         int v_start = 0;
2271         int rxr_idx = 0, txr_idx = 0;
2272         int rxr_remaining = adapter->num_rx_queues;
2273         int txr_remaining = adapter->num_tx_queues;
2274         int i, j;
2275         int rqpv, tqpv;
2276         int err = 0;
2277
2278         /* No mapping required if MSI-X is disabled. */
2279         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2280                 goto out;
2281
2282         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2283
2284         /*
2285          * The ideal configuration...
2286          * We have enough vectors to map one per queue.
2287          */
2288         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2289                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2290                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2291
2292                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2293                         map_vector_to_txq(adapter, v_start, txr_idx);
2294
2295                 goto out;
2296         }
2297
2298         /*
2299          * If we don't have enough vectors for a 1-to-1
2300          * mapping, we'll have to group them so there are
2301          * multiple queues per vector.
2302          */
2303         /* Re-adjusting *qpv takes care of the remainder. */
2304         for (i = v_start; i < q_vectors; i++) {
2305                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2306                 for (j = 0; j < rqpv; j++) {
2307                         map_vector_to_rxq(adapter, i, rxr_idx);
2308                         rxr_idx++;
2309                         rxr_remaining--;
2310                 }
2311                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2312                 for (j = 0; j < tqpv; j++) {
2313                         map_vector_to_txq(adapter, i, txr_idx);
2314                         txr_idx++;
2315                         txr_remaining--;
2316                 }
2317         }
2318 out:
2319         return err;
2320 }
2321
2322 /**
2323  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2324  * @adapter: board private structure
2325  *
2326  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2327  * interrupts from the kernel.
2328  **/
2329 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2330 {
2331         struct net_device *netdev = adapter->netdev;
2332         irqreturn_t (*handler)(int, void *);
2333         int i, vector, q_vectors, err;
2334         int ri = 0, ti = 0;
2335
2336         /* Decrement for Other and TCP Timer vectors */
2337         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2338
2339         err = ixgbe_map_rings_to_vectors(adapter);
2340         if (err)
2341                 return err;
2342
2343 #define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count)        \
2344                                           ? &ixgbe_msix_clean_many : \
2345                           (_v)->rx.count ? &ixgbe_msix_clean_rx   : \
2346                           (_v)->tx.count ? &ixgbe_msix_clean_tx   : \
2347                           NULL)
2348         for (vector = 0; vector < q_vectors; vector++) {
2349                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2350                 handler = SET_HANDLER(q_vector);
2351
2352                 if (handler == &ixgbe_msix_clean_rx) {
2353                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2354                                  "%s-%s-%d", netdev->name, "rx", ri++);
2355                 } else if (handler == &ixgbe_msix_clean_tx) {
2356                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2357                                  "%s-%s-%d", netdev->name, "tx", ti++);
2358                 } else if (handler == &ixgbe_msix_clean_many) {
2359                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2360                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2361                         ti++;
2362                 } else {
2363                         /* skip this unused q_vector */
2364                         continue;
2365                 }
2366                 err = request_irq(adapter->msix_entries[vector].vector,
2367                                   handler, 0, q_vector->name,
2368                                   q_vector);
2369                 if (err) {
2370                         e_err(probe, "request_irq failed for MSIX interrupt "
2371                               "Error: %d\n", err);
2372                         goto free_queue_irqs;
2373                 }
2374         }
2375
2376         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2377         err = request_irq(adapter->msix_entries[vector].vector,
2378                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2379         if (err) {
2380                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2381                 goto free_queue_irqs;
2382         }
2383
2384         return 0;
2385
2386 free_queue_irqs:
2387         for (i = vector - 1; i >= 0; i--)
2388                 free_irq(adapter->msix_entries[--vector].vector,
2389                          adapter->q_vector[i]);
2390         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2391         pci_disable_msix(adapter->pdev);
2392         kfree(adapter->msix_entries);
2393         adapter->msix_entries = NULL;
2394         return err;
2395 }
2396
2397 /**
2398  * ixgbe_irq_enable - Enable default interrupt generation settings
2399  * @adapter: board private structure
2400  **/
2401 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2402                                     bool flush)
2403 {
2404         u32 mask;
2405
2406         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2407         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2408                 mask |= IXGBE_EIMS_GPI_SDP0;
2409         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2410                 mask |= IXGBE_EIMS_GPI_SDP1;
2411         switch (adapter->hw.mac.type) {
2412         case ixgbe_mac_82599EB:
2413         case ixgbe_mac_X540:
2414                 mask |= IXGBE_EIMS_ECC;
2415                 mask |= IXGBE_EIMS_GPI_SDP1;
2416                 mask |= IXGBE_EIMS_GPI_SDP2;
2417                 if (adapter->num_vfs)
2418                         mask |= IXGBE_EIMS_MAILBOX;
2419                 break;
2420         default:
2421                 break;
2422         }
2423         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2424                 mask |= IXGBE_EIMS_FLOW_DIR;
2425
2426         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2427         if (queues)
2428                 ixgbe_irq_enable_queues(adapter, ~0);
2429         if (flush)
2430                 IXGBE_WRITE_FLUSH(&adapter->hw);
2431
2432         if (adapter->num_vfs > 32) {
2433                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2434                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2435         }
2436 }
2437
2438 /**
2439  * ixgbe_intr - legacy mode Interrupt Handler
2440  * @irq: interrupt number
2441  * @data: pointer to a network interface device structure
2442  **/
2443 static irqreturn_t ixgbe_intr(int irq, void *data)
2444 {
2445         struct ixgbe_adapter *adapter = data;
2446         struct ixgbe_hw *hw = &adapter->hw;
2447         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2448         u32 eicr;
2449
2450         /*
2451          * Workaround for silicon errata on 82598.  Mask the interrupts
2452          * before the read of EICR.
2453          */
2454         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2455
2456         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2457          * therefore no explict interrupt disable is necessary */
2458         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2459         if (!eicr) {
2460                 /*
2461                  * shared interrupt alert!
2462                  * make sure interrupts are enabled because the read will
2463                  * have disabled interrupts due to EIAM
2464                  * finish the workaround of silicon errata on 82598.  Unmask
2465                  * the interrupt that we masked before the EICR read.
2466                  */
2467                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2468                         ixgbe_irq_enable(adapter, true, true);
2469                 return IRQ_NONE;        /* Not our interrupt */
2470         }
2471
2472         if (eicr & IXGBE_EICR_LSC)
2473                 ixgbe_check_lsc(adapter);
2474
2475         switch (hw->mac.type) {
2476         case ixgbe_mac_82599EB:
2477                 ixgbe_check_sfp_event(adapter, eicr);
2478                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2479                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2480                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2481                                 adapter->interrupt_event = eicr;
2482                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2483                                 ixgbe_service_event_schedule(adapter);
2484                         }
2485                 }
2486                 break;
2487         default:
2488                 break;
2489         }
2490
2491         ixgbe_check_fan_failure(adapter, eicr);
2492
2493         if (napi_schedule_prep(&(q_vector->napi))) {
2494                 /* would disable interrupts here but EIAM disabled it */
2495                 __napi_schedule(&(q_vector->napi));
2496         }
2497
2498         /*
2499          * re-enable link(maybe) and non-queue interrupts, no flush.
2500          * ixgbe_poll will re-enable the queue interrupts
2501          */
2502
2503         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2504                 ixgbe_irq_enable(adapter, false, false);
2505
2506         return IRQ_HANDLED;
2507 }
2508
2509 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2510 {
2511         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2512
2513         for (i = 0; i < q_vectors; i++) {
2514                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2515                 bitmap_zero(q_vector->rx.idx, MAX_RX_QUEUES);
2516                 bitmap_zero(q_vector->tx.idx, MAX_TX_QUEUES);
2517                 q_vector->rx.count = 0;
2518                 q_vector->tx.count = 0;
2519         }
2520 }
2521
2522 /**
2523  * ixgbe_request_irq - initialize interrupts
2524  * @adapter: board private structure
2525  *
2526  * Attempts to configure interrupts using the best available
2527  * capabilities of the hardware and kernel.
2528  **/
2529 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2530 {
2531         struct net_device *netdev = adapter->netdev;
2532         int err;
2533
2534         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2535                 err = ixgbe_request_msix_irqs(adapter);
2536         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2537                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2538                                   netdev->name, adapter);
2539         } else {
2540                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2541                                   netdev->name, adapter);
2542         }
2543
2544         if (err)
2545                 e_err(probe, "request_irq failed, Error %d\n", err);
2546
2547         return err;
2548 }
2549
2550 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2551 {
2552         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2553                 int i, q_vectors;
2554
2555                 q_vectors = adapter->num_msix_vectors;
2556
2557                 i = q_vectors - 1;
2558                 free_irq(adapter->msix_entries[i].vector, adapter);
2559
2560                 i--;
2561                 for (; i >= 0; i--) {
2562                         /* free only the irqs that were actually requested */
2563                         if (!adapter->q_vector[i]->rx.count &&
2564                             !adapter->q_vector[i]->tx.count)
2565                                 continue;
2566
2567                         free_irq(adapter->msix_entries[i].vector,
2568                                  adapter->q_vector[i]);
2569                 }
2570
2571                 ixgbe_reset_q_vectors(adapter);
2572         } else {
2573                 free_irq(adapter->pdev->irq, adapter);
2574         }
2575 }
2576
2577 /**
2578  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2579  * @adapter: board private structure
2580  **/
2581 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2582 {
2583         switch (adapter->hw.mac.type) {
2584         case ixgbe_mac_82598EB:
2585                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2586                 break;
2587         case ixgbe_mac_82599EB:
2588         case ixgbe_mac_X540:
2589                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2590                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2591                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2592                 if (adapter->num_vfs > 32)
2593                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2594                 break;
2595         default:
2596                 break;
2597         }
2598         IXGBE_WRITE_FLUSH(&adapter->hw);
2599         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2600                 int i;
2601                 for (i = 0; i < adapter->num_msix_vectors; i++)
2602                         synchronize_irq(adapter->msix_entries[i].vector);
2603         } else {
2604                 synchronize_irq(adapter->pdev->irq);
2605         }
2606 }
2607
2608 /**
2609  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2610  *
2611  **/
2612 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2613 {
2614         struct ixgbe_hw *hw = &adapter->hw;
2615
2616         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2617                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2618
2619         ixgbe_set_ivar(adapter, 0, 0, 0);
2620         ixgbe_set_ivar(adapter, 1, 0, 0);
2621
2622         map_vector_to_rxq(adapter, 0, 0);
2623         map_vector_to_txq(adapter, 0, 0);
2624
2625         e_info(hw, "Legacy interrupt IVAR setup done\n");
2626 }
2627
2628 /**
2629  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2630  * @adapter: board private structure
2631  * @ring: structure containing ring specific data
2632  *
2633  * Configure the Tx descriptor ring after a reset.
2634  **/
2635 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2636                              struct ixgbe_ring *ring)
2637 {
2638         struct ixgbe_hw *hw = &adapter->hw;
2639         u64 tdba = ring->dma;
2640         int wait_loop = 10;
2641         u32 txdctl;
2642         u8 reg_idx = ring->reg_idx;
2643
2644         /* disable queue to avoid issues while updating state */
2645         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2646         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2647                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2648         IXGBE_WRITE_FLUSH(hw);
2649
2650         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2651                         (tdba & DMA_BIT_MASK(32)));
2652         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2653         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2654                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2655         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2656         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2657         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2658
2659         /* configure fetching thresholds */
2660         if (adapter->rx_itr_setting == 0) {
2661                 /* cannot set wthresh when itr==0 */
2662                 txdctl &= ~0x007F0000;
2663         } else {
2664                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2665                 txdctl |= (8 << 16);
2666         }
2667         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2668                 /* PThresh workaround for Tx hang with DFP enabled. */
2669                 txdctl |= 32;
2670         }
2671
2672         /* reinitialize flowdirector state */
2673         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2674             adapter->atr_sample_rate) {
2675                 ring->atr_sample_rate = adapter->atr_sample_rate;
2676                 ring->atr_count = 0;
2677                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2678         } else {
2679                 ring->atr_sample_rate = 0;
2680         }
2681
2682         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2683
2684         /* enable queue */
2685         txdctl |= IXGBE_TXDCTL_ENABLE;
2686         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2687
2688         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2689         if (hw->mac.type == ixgbe_mac_82598EB &&
2690             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2691                 return;
2692
2693         /* poll to verify queue is enabled */
2694         do {
2695                 usleep_range(1000, 2000);
2696                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2697         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2698         if (!wait_loop)
2699                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2700 }
2701
2702 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2703 {
2704         struct ixgbe_hw *hw = &adapter->hw;
2705         u32 rttdcs;
2706         u32 reg;
2707         u8 tcs = netdev_get_num_tc(adapter->netdev);
2708
2709         if (hw->mac.type == ixgbe_mac_82598EB)
2710                 return;
2711
2712         /* disable the arbiter while setting MTQC */
2713         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2714         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2715         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2716
2717         /* set transmit pool layout */
2718         switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2719         case (IXGBE_FLAG_SRIOV_ENABLED):
2720                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2721                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2722                 break;
2723         default:
2724                 if (!tcs)
2725                         reg = IXGBE_MTQC_64Q_1PB;
2726                 else if (tcs <= 4)
2727                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2728                 else
2729                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2730
2731                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2732
2733                 /* Enable Security TX Buffer IFG for multiple pb */
2734                 if (tcs) {
2735                         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2736                         reg |= IXGBE_SECTX_DCB;
2737                         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2738                 }
2739                 break;
2740         }
2741
2742         /* re-enable the arbiter */
2743         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2744         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2745 }
2746
2747 /**
2748  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2749  * @adapter: board private structure
2750  *
2751  * Configure the Tx unit of the MAC after a reset.
2752  **/
2753 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2754 {
2755         struct ixgbe_hw *hw = &adapter->hw;
2756         u32 dmatxctl;
2757         u32 i;
2758
2759         ixgbe_setup_mtqc(adapter);
2760
2761         if (hw->mac.type != ixgbe_mac_82598EB) {
2762                 /* DMATXCTL.EN must be before Tx queues are enabled */
2763                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2764                 dmatxctl |= IXGBE_DMATXCTL_TE;
2765                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2766         }
2767
2768         /* Setup the HW Tx Head and Tail descriptor pointers */
2769         for (i = 0; i < adapter->num_tx_queues; i++)
2770                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2771 }
2772
2773 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2774
2775 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2776                                    struct ixgbe_ring *rx_ring)
2777 {
2778         u32 srrctl;
2779         u8 reg_idx = rx_ring->reg_idx;
2780
2781         switch (adapter->hw.mac.type) {
2782         case ixgbe_mac_82598EB: {
2783                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2784                 const int mask = feature[RING_F_RSS].mask;
2785                 reg_idx = reg_idx & mask;
2786         }
2787                 break;
2788         case ixgbe_mac_82599EB:
2789         case ixgbe_mac_X540:
2790         default:
2791                 break;
2792         }
2793
2794         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2795
2796         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2797         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2798         if (adapter->num_vfs)
2799                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2800
2801         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2802                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2803
2804         if (ring_is_ps_enabled(rx_ring)) {
2805 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2806                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2807 #else
2808                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2809 #endif
2810                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2811         } else {
2812                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2813                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2814                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2815         }
2816
2817         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2818 }
2819
2820 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2821 {
2822         struct ixgbe_hw *hw = &adapter->hw;
2823         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2824                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2825                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2826         u32 mrqc = 0, reta = 0;
2827         u32 rxcsum;
2828         int i, j;
2829         u8 tcs = netdev_get_num_tc(adapter->netdev);
2830         int maxq = adapter->ring_feature[RING_F_RSS].indices;
2831
2832         if (tcs)
2833                 maxq = min(maxq, adapter->num_tx_queues / tcs);
2834
2835         /* Fill out hash function seeds */
2836         for (i = 0; i < 10; i++)
2837                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2838
2839         /* Fill out redirection table */
2840         for (i = 0, j = 0; i < 128; i++, j++) {
2841                 if (j == maxq)
2842                         j = 0;
2843                 /* reta = 4-byte sliding window of
2844                  * 0x00..(indices-1)(indices-1)00..etc. */
2845                 reta = (reta << 8) | (j * 0x11);
2846                 if ((i & 3) == 3)
2847                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2848         }
2849
2850         /* Disable indicating checksum in descriptor, enables RSS hash */
2851         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2852         rxcsum |= IXGBE_RXCSUM_PCSD;
2853         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2854
2855         if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2856             (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2857                 mrqc = IXGBE_MRQC_RSSEN;
2858         } else {
2859                 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2860                                              | IXGBE_FLAG_SRIOV_ENABLED);
2861
2862                 switch (mask) {
2863                 case (IXGBE_FLAG_RSS_ENABLED):
2864                         if (!tcs)
2865                                 mrqc = IXGBE_MRQC_RSSEN;
2866                         else if (tcs <= 4)
2867                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2868                         else
2869                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2870                         break;
2871                 case (IXGBE_FLAG_SRIOV_ENABLED):
2872                         mrqc = IXGBE_MRQC_VMDQEN;
2873                         break;
2874                 default:
2875                         break;
2876                 }
2877         }
2878
2879         /* Perform hash on these packet types */
2880         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2881               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2882               | IXGBE_MRQC_RSS_FIELD_IPV6
2883               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2884
2885         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2886 }
2887
2888 /**
2889  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2890  * @adapter:    address of board private structure
2891  * @index:      index of ring to set
2892  **/
2893 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2894                                    struct ixgbe_ring *ring)
2895 {
2896         struct ixgbe_hw *hw = &adapter->hw;
2897         u32 rscctrl;
2898         int rx_buf_len;
2899         u8 reg_idx = ring->reg_idx;
2900
2901         if (!ring_is_rsc_enabled(ring))
2902                 return;
2903
2904         rx_buf_len = ring->rx_buf_len;
2905         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2906         rscctrl |= IXGBE_RSCCTL_RSCEN;
2907         /*
2908          * we must limit the number of descriptors so that the
2909          * total size of max desc * buf_len is not greater
2910          * than 65535
2911          */
2912         if (ring_is_ps_enabled(ring)) {
2913 #if (MAX_SKB_FRAGS > 16)
2914                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2915 #elif (MAX_SKB_FRAGS > 8)
2916                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2917 #elif (MAX_SKB_FRAGS > 4)
2918                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2919 #else
2920                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2921 #endif
2922         } else {
2923                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2924                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2925                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2926                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2927                 else
2928                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2929         }
2930         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2931 }
2932
2933 /**
2934  *  ixgbe_set_uta - Set unicast filter table address
2935  *  @adapter: board private structure
2936  *
2937  *  The unicast table address is a register array of 32-bit registers.
2938  *  The table is meant to be used in a way similar to how the MTA is used
2939  *  however due to certain limitations in the hardware it is necessary to
2940  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2941  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2942  **/
2943 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2944 {
2945         struct ixgbe_hw *hw = &adapter->hw;
2946         int i;
2947
2948         /* The UTA table only exists on 82599 hardware and newer */
2949         if (hw->mac.type < ixgbe_mac_82599EB)
2950                 return;
2951
2952         /* we only need to do this if VMDq is enabled */
2953         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2954                 return;
2955
2956         for (i = 0; i < 128; i++)
2957                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2958 }
2959
2960 #define IXGBE_MAX_RX_DESC_POLL 10
2961 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2962                                        struct ixgbe_ring *ring)
2963 {
2964         struct ixgbe_hw *hw = &adapter->hw;
2965         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2966         u32 rxdctl;
2967         u8 reg_idx = ring->reg_idx;
2968
2969         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2970         if (hw->mac.type == ixgbe_mac_82598EB &&
2971             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2972                 return;
2973
2974         do {
2975                 usleep_range(1000, 2000);
2976                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2977         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2978
2979         if (!wait_loop) {
2980                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2981                       "the polling period\n", reg_idx);
2982         }
2983 }
2984
2985 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2986                             struct ixgbe_ring *ring)
2987 {
2988         struct ixgbe_hw *hw = &adapter->hw;
2989         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2990         u32 rxdctl;
2991         u8 reg_idx = ring->reg_idx;
2992
2993         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2994         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2995
2996         /* write value back with RXDCTL.ENABLE bit cleared */
2997         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2998
2999         if (hw->mac.type == ixgbe_mac_82598EB &&
3000             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3001                 return;
3002
3003         /* the hardware may take up to 100us to really disable the rx queue */
3004         do {
3005                 udelay(10);
3006                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3007         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3008
3009         if (!wait_loop) {
3010                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3011                       "the polling period\n", reg_idx);
3012         }
3013 }
3014
3015 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3016                              struct ixgbe_ring *ring)
3017 {
3018         struct ixgbe_hw *hw = &adapter->hw;
3019         u64 rdba = ring->dma;
3020         u32 rxdctl;
3021         u8 reg_idx = ring->reg_idx;
3022
3023         /* disable queue to avoid issues while updating state */
3024         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3025         ixgbe_disable_rx_queue(adapter, ring);
3026
3027         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3028         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3029         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3030                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3031         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3032         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3033         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3034
3035         ixgbe_configure_srrctl(adapter, ring);
3036         ixgbe_configure_rscctl(adapter, ring);
3037
3038         /* If operating in IOV mode set RLPML for X540 */
3039         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3040             hw->mac.type == ixgbe_mac_X540) {
3041                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3042                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3043                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3044         }
3045
3046         if (hw->mac.type == ixgbe_mac_82598EB) {
3047                 /*
3048                  * enable cache line friendly hardware writes:
3049                  * PTHRESH=32 descriptors (half the internal cache),
3050                  * this also removes ugly rx_no_buffer_count increment
3051                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3052                  * WTHRESH=8 burst writeback up to two cache lines
3053                  */
3054                 rxdctl &= ~0x3FFFFF;
3055                 rxdctl |=  0x080420;
3056         }
3057
3058         /* enable receive descriptor ring */
3059         rxdctl |= IXGBE_RXDCTL_ENABLE;
3060         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3061
3062         ixgbe_rx_desc_queue_enable(adapter, ring);
3063         ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3064 }
3065
3066 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3067 {
3068         struct ixgbe_hw *hw = &adapter->hw;
3069         int p;
3070
3071         /* PSRTYPE must be initialized in non 82598 adapters */
3072         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3073                       IXGBE_PSRTYPE_UDPHDR |
3074                       IXGBE_PSRTYPE_IPV4HDR |
3075                       IXGBE_PSRTYPE_L2HDR |
3076                       IXGBE_PSRTYPE_IPV6HDR;
3077
3078         if (hw->mac.type == ixgbe_mac_82598EB)
3079                 return;
3080
3081         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3082                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3083
3084         for (p = 0; p < adapter->num_rx_pools; p++)
3085                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3086                                 psrtype);
3087 }
3088
3089 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3090 {
3091         struct ixgbe_hw *hw = &adapter->hw;
3092         u32 gcr_ext;
3093         u32 vt_reg_bits;
3094         u32 reg_offset, vf_shift;
3095         u32 vmdctl;
3096
3097         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3098                 return;
3099
3100         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3101         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3102         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3103         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3104
3105         vf_shift = adapter->num_vfs % 32;
3106         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3107
3108         /* Enable only the PF's pool for Tx/Rx */
3109         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3110         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3111         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3112         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3113         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3114
3115         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3116         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3117
3118         /*
3119          * Set up VF register offsets for selected VT Mode,
3120          * i.e. 32 or 64 VFs for SR-IOV
3121          */
3122         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3123         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3124         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3125         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3126
3127         /* enable Tx loopback for VF/PF communication */
3128         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3129         /* Enable MAC Anti-Spoofing */
3130         hw->mac.ops.set_mac_anti_spoofing(hw,
3131                                           (adapter->antispoofing_enabled =
3132                                            (adapter->num_vfs != 0)),
3133                                           adapter->num_vfs);
3134 }
3135
3136 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3137 {
3138         struct ixgbe_hw *hw = &adapter->hw;
3139         struct net_device *netdev = adapter->netdev;
3140         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3141         int rx_buf_len;
3142         struct ixgbe_ring *rx_ring;
3143         int i;
3144         u32 mhadd, hlreg0;
3145
3146         /* Decide whether to use packet split mode or not */
3147         /* On by default */
3148         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3149
3150         /* Do not use packet split if we're in SR-IOV Mode */
3151         if (adapter->num_vfs)
3152                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3153
3154         /* Disable packet split due to 82599 erratum #45 */
3155         if (hw->mac.type == ixgbe_mac_82599EB)
3156                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3157
3158         /* Set the RX buffer length according to the mode */
3159         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3160                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3161         } else {
3162                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3163                     (netdev->mtu <= ETH_DATA_LEN))
3164                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3165                 else
3166                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3167         }
3168
3169 #ifdef IXGBE_FCOE
3170         /* adjust max frame to be able to do baby jumbo for FCoE */
3171         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3172             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3173                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3174
3175 #endif /* IXGBE_FCOE */
3176         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3177         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3178                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3179                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3180
3181                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3182         }
3183
3184         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3185         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3186         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3187         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3188
3189         /*
3190          * Setup the HW Rx Head and Tail Descriptor Pointers and
3191          * the Base and Length of the Rx Descriptor Ring
3192          */
3193         for (i = 0; i < adapter->num_rx_queues; i++) {
3194                 rx_ring = adapter->rx_ring[i];
3195                 rx_ring->rx_buf_len = rx_buf_len;
3196
3197                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3198                         set_ring_ps_enabled(rx_ring);
3199                 else
3200                         clear_ring_ps_enabled(rx_ring);
3201
3202                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3203                         set_ring_rsc_enabled(rx_ring);
3204                 else
3205                         clear_ring_rsc_enabled(rx_ring);
3206
3207 #ifdef IXGBE_FCOE
3208                 if (netdev->features & NETIF_F_FCOE_MTU) {
3209                         struct ixgbe_ring_feature *f;
3210                         f = &adapter->ring_feature[RING_F_FCOE];
3211                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3212                                 clear_ring_ps_enabled(rx_ring);
3213                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3214                                         rx_ring->rx_buf_len =
3215                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3216                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3217                                    !ring_is_ps_enabled(rx_ring)) {
3218                                 rx_ring->rx_buf_len =
3219                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3220                         }
3221                 }
3222 #endif /* IXGBE_FCOE */
3223         }
3224 }
3225
3226 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3227 {
3228         struct ixgbe_hw *hw = &adapter->hw;
3229         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3230
3231         switch (hw->mac.type) {
3232         case ixgbe_mac_82598EB:
3233                 /*
3234                  * For VMDq support of different descriptor types or
3235                  * buffer sizes through the use of multiple SRRCTL
3236                  * registers, RDRXCTL.MVMEN must be set to 1
3237                  *
3238                  * also, the manual doesn't mention it clearly but DCA hints
3239                  * will only use queue 0's tags unless this bit is set.  Side
3240                  * effects of setting this bit are only that SRRCTL must be
3241                  * fully programmed [0..15]
3242                  */
3243                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3244                 break;
3245         case ixgbe_mac_82599EB:
3246         case ixgbe_mac_X540:
3247                 /* Disable RSC for ACK packets */
3248                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3249                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3250                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3251                 /* hardware requires some bits to be set by default */
3252                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3253                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3254                 break;
3255         default:
3256                 /* We should do nothing since we don't know this hardware */
3257                 return;
3258         }
3259
3260         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3261 }
3262
3263 /**
3264  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3265  * @adapter: board private structure
3266  *
3267  * Configure the Rx unit of the MAC after a reset.
3268  **/
3269 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3270 {
3271         struct ixgbe_hw *hw = &adapter->hw;
3272         int i;
3273         u32 rxctrl;
3274
3275         /* disable receives while setting up the descriptors */
3276         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3277         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3278
3279         ixgbe_setup_psrtype(adapter);
3280         ixgbe_setup_rdrxctl(adapter);
3281
3282         /* Program registers for the distribution of queues */
3283         ixgbe_setup_mrqc(adapter);
3284
3285         ixgbe_set_uta(adapter);
3286
3287         /* set_rx_buffer_len must be called before ring initialization */
3288         ixgbe_set_rx_buffer_len(adapter);
3289
3290         /*
3291          * Setup the HW Rx Head and Tail Descriptor Pointers and
3292          * the Base and Length of the Rx Descriptor Ring
3293          */
3294         for (i = 0; i < adapter->num_rx_queues; i++)
3295                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3296
3297         /* disable drop enable for 82598 parts */
3298         if (hw->mac.type == ixgbe_mac_82598EB)
3299                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3300
3301         /* enable all receives */
3302         rxctrl |= IXGBE_RXCTRL_RXEN;
3303         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3304 }
3305
3306 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3307 {
3308         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3309         struct ixgbe_hw *hw = &adapter->hw;
3310         int pool_ndx = adapter->num_vfs;
3311
3312         /* add VID to filter table */
3313         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3314         set_bit(vid, adapter->active_vlans);
3315 }
3316
3317 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3318 {
3319         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3320         struct ixgbe_hw *hw = &adapter->hw;
3321         int pool_ndx = adapter->num_vfs;
3322
3323         /* remove VID from filter table */
3324         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3325         clear_bit(vid, adapter->active_vlans);
3326 }
3327
3328 /**
3329  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3330  * @adapter: driver data
3331  */
3332 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3333 {
3334         struct ixgbe_hw *hw = &adapter->hw;
3335         u32 vlnctrl;
3336
3337         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3338         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3339         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3340 }
3341
3342 /**
3343  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3344  * @adapter: driver data
3345  */
3346 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3347 {
3348         struct ixgbe_hw *hw = &adapter->hw;
3349         u32 vlnctrl;
3350
3351         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3352         vlnctrl |= IXGBE_VLNCTRL_VFE;
3353         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3354         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3355 }
3356
3357 /**
3358  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3359  * @adapter: driver data
3360  */
3361 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3362 {
3363         struct ixgbe_hw *hw = &adapter->hw;
3364         u32 vlnctrl;
3365         int i, j;
3366
3367         switch (hw->mac.type) {
3368         case ixgbe_mac_82598EB:
3369                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3370                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3371                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3372                 break;
3373         case ixgbe_mac_82599EB:
3374         case ixgbe_mac_X540:
3375                 for (i = 0; i < adapter->num_rx_queues; i++) {
3376                         j = adapter->rx_ring[i]->reg_idx;
3377                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3378                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3379                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3380                 }
3381                 break;
3382         default:
3383                 break;
3384         }
3385 }
3386
3387 /**
3388  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3389  * @adapter: driver data
3390  */
3391 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3392 {
3393         struct ixgbe_hw *hw = &adapter->hw;
3394         u32 vlnctrl;
3395         int i, j;
3396
3397         switch (hw->mac.type) {
3398         case ixgbe_mac_82598EB:
3399                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3400                 vlnctrl |= IXGBE_VLNCTRL_VME;
3401                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3402                 break;
3403         case ixgbe_mac_82599EB:
3404         case ixgbe_mac_X540:
3405                 for (i = 0; i < adapter->num_rx_queues; i++) {
3406                         j = adapter->rx_ring[i]->reg_idx;
3407                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3408                         vlnctrl |= IXGBE_RXDCTL_VME;
3409                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3410                 }
3411                 break;
3412         default:
3413                 break;
3414         }
3415 }
3416
3417 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3418 {
3419         u16 vid;
3420
3421         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3422
3423         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3424                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3425 }
3426
3427 /**
3428  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3429  * @netdev: network interface device structure
3430  *
3431  * Writes unicast address list to the RAR table.
3432  * Returns: -ENOMEM on failure/insufficient address space
3433  *                0 on no addresses written
3434  *                X on writing X addresses to the RAR table
3435  **/
3436 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3437 {
3438         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3439         struct ixgbe_hw *hw = &adapter->hw;
3440         unsigned int vfn = adapter->num_vfs;
3441         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3442         int count = 0;
3443
3444         /* return ENOMEM indicating insufficient memory for addresses */
3445         if (netdev_uc_count(netdev) > rar_entries)
3446                 return -ENOMEM;
3447
3448         if (!netdev_uc_empty(netdev) && rar_entries) {
3449                 struct netdev_hw_addr *ha;
3450                 /* return error if we do not support writing to RAR table */
3451                 if (!hw->mac.ops.set_rar)
3452                         return -ENOMEM;
3453
3454                 netdev_for_each_uc_addr(ha, netdev) {
3455                         if (!rar_entries)
3456                                 break;
3457                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3458                                             vfn, IXGBE_RAH_AV);
3459                         count++;
3460                 }
3461         }
3462         /* write the addresses in reverse order to avoid write combining */
3463         for (; rar_entries > 0 ; rar_entries--)
3464                 hw->mac.ops.clear_rar(hw, rar_entries);
3465
3466         return count;
3467 }
3468
3469 /**
3470  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3471  * @netdev: network interface device structure
3472  *
3473  * The set_rx_method entry point is called whenever the unicast/multicast
3474  * address list or the network interface flags are updated.  This routine is
3475  * responsible for configuring the hardware for proper unicast, multicast and
3476  * promiscuous mode.
3477  **/
3478 void ixgbe_set_rx_mode(struct net_device *netdev)
3479 {
3480         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3481         struct ixgbe_hw *hw = &adapter->hw;
3482         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3483         int count;
3484
3485         /* Check for Promiscuous and All Multicast modes */
3486
3487         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3488
3489         /* set all bits that we expect to always be set */
3490         fctrl |= IXGBE_FCTRL_BAM;
3491         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3492         fctrl |= IXGBE_FCTRL_PMCF;
3493
3494         /* clear the bits we are changing the status of */
3495         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3496
3497         if (netdev->flags & IFF_PROMISC) {
3498                 hw->addr_ctrl.user_set_promisc = true;
3499                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3500                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3501                 /* don't hardware filter vlans in promisc mode */
3502                 ixgbe_vlan_filter_disable(adapter);
3503         } else {
3504                 if (netdev->flags & IFF_ALLMULTI) {
3505                         fctrl |= IXGBE_FCTRL_MPE;
3506                         vmolr |= IXGBE_VMOLR_MPE;
3507                 } else {
3508                         /*
3509                          * Write addresses to the MTA, if the attempt fails
3510                          * then we should just turn on promiscuous mode so
3511                          * that we can at least receive multicast traffic
3512                          */
3513                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3514                         vmolr |= IXGBE_VMOLR_ROMPE;
3515                 }
3516                 ixgbe_vlan_filter_enable(adapter);
3517                 hw->addr_ctrl.user_set_promisc = false;
3518                 /*
3519                  * Write addresses to available RAR registers, if there is not
3520                  * sufficient space to store all the addresses then enable
3521                  * unicast promiscuous mode
3522                  */
3523                 count = ixgbe_write_uc_addr_list(netdev);
3524                 if (count < 0) {
3525                         fctrl |= IXGBE_FCTRL_UPE;
3526                         vmolr |= IXGBE_VMOLR_ROPE;
3527                 }
3528         }
3529
3530         if (adapter->num_vfs) {
3531                 ixgbe_restore_vf_multicasts(adapter);
3532                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3533                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3534                            IXGBE_VMOLR_ROPE);
3535                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3536         }
3537
3538         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3539
3540         if (netdev->features & NETIF_F_HW_VLAN_RX)
3541                 ixgbe_vlan_strip_enable(adapter);
3542         else
3543                 ixgbe_vlan_strip_disable(adapter);
3544 }
3545
3546 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3547 {
3548         int q_idx;
3549         struct ixgbe_q_vector *q_vector;
3550         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3551
3552         /* legacy and MSI only use one vector */
3553         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3554                 q_vectors = 1;
3555
3556         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3557                 struct napi_struct *napi;
3558                 q_vector = adapter->q_vector[q_idx];
3559                 napi = &q_vector->napi;
3560                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3561                         if (!q_vector->rx.count || !q_vector->tx.count) {
3562                                 if (q_vector->tx.count == 1)
3563                                         napi->poll = &ixgbe_clean_txonly;
3564                                 else if (q_vector->rx.count == 1)
3565                                         napi->poll = &ixgbe_clean_rxonly;
3566                         }
3567                 }
3568
3569                 napi_enable(napi);
3570         }
3571 }
3572
3573 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3574 {
3575         int q_idx;
3576         struct ixgbe_q_vector *q_vector;
3577         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3578
3579         /* legacy and MSI only use one vector */
3580         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3581                 q_vectors = 1;
3582
3583         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3584                 q_vector = adapter->q_vector[q_idx];
3585                 napi_disable(&q_vector->napi);
3586         }
3587 }
3588
3589 #ifdef CONFIG_IXGBE_DCB
3590 /*
3591  * ixgbe_configure_dcb - Configure DCB hardware
3592  * @adapter: ixgbe adapter struct
3593  *
3594  * This is called by the driver on open to configure the DCB hardware.
3595  * This is also called by the gennetlink interface when reconfiguring
3596  * the DCB state.
3597  */
3598 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3599 {
3600         struct ixgbe_hw *hw = &adapter->hw;
3601         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3602
3603         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3604                 if (hw->mac.type == ixgbe_mac_82598EB)
3605                         netif_set_gso_max_size(adapter->netdev, 65536);
3606                 return;
3607         }
3608
3609         if (hw->mac.type == ixgbe_mac_82598EB)
3610                 netif_set_gso_max_size(adapter->netdev, 32768);
3611
3612
3613         /* Enable VLAN tag insert/strip */
3614         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3615
3616         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3617
3618         /* reconfigure the hardware */
3619         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3620 #ifdef IXGBE_FCOE
3621                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3622                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3623 #endif
3624                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3625                                                 DCB_TX_CONFIG);
3626                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3627                                                 DCB_RX_CONFIG);
3628                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3629         } else {
3630                 struct net_device *dev = adapter->netdev;
3631
3632                 if (adapter->ixgbe_ieee_ets)
3633                         dev->dcbnl_ops->ieee_setets(dev,
3634                                                     adapter->ixgbe_ieee_ets);
3635                 if (adapter->ixgbe_ieee_pfc)
3636                         dev->dcbnl_ops->ieee_setpfc(dev,
3637                                                     adapter->ixgbe_ieee_pfc);
3638         }
3639
3640         /* Enable RSS Hash per TC */
3641         if (hw->mac.type != ixgbe_mac_82598EB) {
3642                 int i;
3643                 u32 reg = 0;
3644
3645                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3646                         u8 msb = 0;
3647                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3648
3649                         while (cnt >>= 1)
3650                                 msb++;
3651
3652                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3653                 }
3654                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3655         }
3656 }
3657
3658 #endif
3659
3660 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3661 {
3662         int hdrm = 0;
3663         int num_tc = netdev_get_num_tc(adapter->netdev);
3664         struct ixgbe_hw *hw = &adapter->hw;
3665
3666         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3667             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3668                 hdrm = 64 << adapter->fdir_pballoc;
3669
3670         hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3671 }
3672
3673 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3674 {
3675         struct ixgbe_hw *hw = &adapter->hw;
3676         struct hlist_node *node, *node2;
3677         struct ixgbe_fdir_filter *filter;
3678
3679         spin_lock(&adapter->fdir_perfect_lock);
3680
3681         if (!hlist_empty(&adapter->fdir_filter_list))
3682                 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3683
3684         hlist_for_each_entry_safe(filter, node, node2,
3685                                   &adapter->fdir_filter_list, fdir_node) {
3686                 ixgbe_fdir_write_perfect_filter_82599(hw,
3687                                 &filter->filter,
3688                                 filter->sw_idx,
3689                                 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3690                                 IXGBE_FDIR_DROP_QUEUE :
3691                                 adapter->rx_ring[filter->action]->reg_idx);
3692         }
3693
3694         spin_unlock(&adapter->fdir_perfect_lock);
3695 }
3696
3697 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3698 {
3699         struct net_device *netdev = adapter->netdev;
3700         struct ixgbe_hw *hw = &adapter->hw;
3701         int i;
3702
3703         ixgbe_configure_pb(adapter);
3704 #ifdef CONFIG_IXGBE_DCB
3705         ixgbe_configure_dcb(adapter);
3706 #endif
3707
3708         ixgbe_set_rx_mode(netdev);
3709         ixgbe_restore_vlan(adapter);
3710
3711 #ifdef IXGBE_FCOE
3712         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3713                 ixgbe_configure_fcoe(adapter);
3714
3715 #endif /* IXGBE_FCOE */
3716         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3717                 for (i = 0; i < adapter->num_tx_queues; i++)
3718                         adapter->tx_ring[i]->atr_sample_rate =
3719                                                        adapter->atr_sample_rate;
3720                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3721         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3722                 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3723                                               adapter->fdir_pballoc);
3724                 ixgbe_fdir_filter_restore(adapter);
3725         }
3726         ixgbe_configure_virtualization(adapter);
3727
3728         ixgbe_configure_tx(adapter);
3729         ixgbe_configure_rx(adapter);
3730 }
3731
3732 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3733 {
3734         switch (hw->phy.type) {
3735         case ixgbe_phy_sfp_avago:
3736         case ixgbe_phy_sfp_ftl:
3737         case ixgbe_phy_sfp_intel:
3738         case ixgbe_phy_sfp_unknown:
3739         case ixgbe_phy_sfp_passive_tyco:
3740         case ixgbe_phy_sfp_passive_unknown:
3741         case ixgbe_phy_sfp_active_unknown:
3742         case ixgbe_phy_sfp_ftl_active:
3743                 return true;
3744         default:
3745                 return false;
3746         }
3747 }
3748
3749 /**
3750  * ixgbe_sfp_link_config - set up SFP+ link
3751  * @adapter: pointer to private adapter struct
3752  **/
3753 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3754 {
3755         /*
3756          * We are assuming the worst case scenerio here, and that
3757          * is that an SFP was inserted/removed after the reset
3758          * but before SFP detection was enabled.  As such the best
3759          * solution is to just start searching as soon as we start
3760          */
3761         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3762                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3763
3764         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3765 }
3766
3767 /**
3768  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3769  * @hw: pointer to private hardware struct
3770  *
3771  * Returns 0 on success, negative on failure
3772  **/
3773 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3774 {
3775         u32 autoneg;
3776         bool negotiation, link_up = false;
3777         u32 ret = IXGBE_ERR_LINK_SETUP;
3778
3779         if (hw->mac.ops.check_link)
3780                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3781
3782         if (ret)
3783                 goto link_cfg_out;
3784
3785         autoneg = hw->phy.autoneg_advertised;
3786         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3787                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3788                                                         &negotiation);
3789         if (ret)
3790                 goto link_cfg_out;
3791
3792         if (hw->mac.ops.setup_link)
3793                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3794 link_cfg_out:
3795         return ret;
3796 }
3797
3798 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3799 {
3800         struct ixgbe_hw *hw = &adapter->hw;
3801         u32 gpie = 0;
3802
3803         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3804                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3805                        IXGBE_GPIE_OCD;
3806                 gpie |= IXGBE_GPIE_EIAME;
3807                 /*
3808                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3809                  * this saves a register write for every interrupt
3810                  */
3811                 switch (hw->mac.type) {
3812                 case ixgbe_mac_82598EB:
3813                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3814                         break;
3815                 case ixgbe_mac_82599EB:
3816                 case ixgbe_mac_X540:
3817                 default:
3818                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3819                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3820                         break;
3821                 }
3822         } else {
3823                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3824                  * specifically only auto mask tx and rx interrupts */
3825                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3826         }
3827
3828         /* XXX: to interrupt immediately for EICS writes, enable this */
3829         /* gpie |= IXGBE_GPIE_EIMEN; */
3830
3831         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3832                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3833                 gpie |= IXGBE_GPIE_VTMODE_64;
3834         }
3835
3836         /* Enable fan failure interrupt */
3837         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3838                 gpie |= IXGBE_SDP1_GPIEN;
3839
3840         if (hw->mac.type == ixgbe_mac_82599EB) {
3841                 gpie |= IXGBE_SDP1_GPIEN;
3842                 gpie |= IXGBE_SDP2_GPIEN;
3843         }
3844
3845         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3846 }
3847
3848 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3849 {
3850         struct ixgbe_hw *hw = &adapter->hw;
3851         int err;
3852         u32 ctrl_ext;
3853
3854         ixgbe_get_hw_control(adapter);
3855         ixgbe_setup_gpie(adapter);
3856
3857         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3858                 ixgbe_configure_msix(adapter);
3859         else
3860                 ixgbe_configure_msi_and_legacy(adapter);
3861
3862         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3863         if (hw->mac.ops.enable_tx_laser &&
3864             ((hw->phy.multispeed_fiber) ||
3865              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3866               (hw->mac.type == ixgbe_mac_82599EB))))
3867                 hw->mac.ops.enable_tx_laser(hw);
3868
3869         clear_bit(__IXGBE_DOWN, &adapter->state);
3870         ixgbe_napi_enable_all(adapter);
3871
3872         if (ixgbe_is_sfp(hw)) {
3873                 ixgbe_sfp_link_config(adapter);
3874         } else {
3875                 err = ixgbe_non_sfp_link_config(hw);
3876                 if (err)
3877                         e_err(probe, "link_config FAILED %d\n", err);
3878         }
3879
3880         /* clear any pending interrupts, may auto mask */
3881         IXGBE_READ_REG(hw, IXGBE_EICR);
3882         ixgbe_irq_enable(adapter, true, true);
3883
3884         /*
3885          * If this adapter has a fan, check to see if we had a failure
3886          * before we enabled the interrupt.
3887          */
3888         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3889                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3890                 if (esdp & IXGBE_ESDP_SDP1)
3891                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3892         }
3893
3894         /* enable transmits */
3895         netif_tx_start_all_queues(adapter->netdev);
3896
3897         /* bring the link up in the watchdog, this could race with our first
3898          * link up interrupt but shouldn't be a problem */
3899         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3900         adapter->link_check_timeout = jiffies;
3901         mod_timer(&adapter->service_timer, jiffies);
3902
3903         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3904         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3905         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3906         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3907
3908         return 0;
3909 }
3910
3911 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3912 {
3913         WARN_ON(in_interrupt());
3914         /* put off any impending NetWatchDogTimeout */
3915         adapter->netdev->trans_start = jiffies;
3916
3917         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3918                 usleep_range(1000, 2000);
3919         ixgbe_down(adapter);
3920         /*
3921          * If SR-IOV enabled then wait a bit before bringing the adapter
3922          * back up to give the VFs time to respond to the reset.  The
3923          * two second wait is based upon the watchdog timer cycle in
3924          * the VF driver.
3925          */
3926         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3927                 msleep(2000);
3928         ixgbe_up(adapter);
3929         clear_bit(__IXGBE_RESETTING, &adapter->state);
3930 }
3931
3932 int ixgbe_up(struct ixgbe_adapter *adapter)
3933 {
3934         /* hardware has been reset, we need to reload some things */
3935         ixgbe_configure(adapter);
3936
3937         return ixgbe_up_complete(adapter);
3938 }
3939
3940 void ixgbe_reset(struct ixgbe_adapter *adapter)
3941 {
3942         struct ixgbe_hw *hw = &adapter->hw;
3943         int err;
3944
3945         /* lock SFP init bit to prevent race conditions with the watchdog */
3946         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3947                 usleep_range(1000, 2000);
3948
3949         /* clear all SFP and link config related flags while holding SFP_INIT */
3950         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3951                              IXGBE_FLAG2_SFP_NEEDS_RESET);
3952         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3953
3954         err = hw->mac.ops.init_hw(hw);
3955         switch (err) {
3956         case 0:
3957         case IXGBE_ERR_SFP_NOT_PRESENT:
3958         case IXGBE_ERR_SFP_NOT_SUPPORTED:
3959                 break;
3960         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3961                 e_dev_err("master disable timed out\n");
3962                 break;
3963         case IXGBE_ERR_EEPROM_VERSION:
3964                 /* We are running on a pre-production device, log a warning */
3965                 e_dev_warn("This device is a pre-production adapter/LOM. "
3966                            "Please be aware there may be issuesassociated with "
3967                            "your hardware.  If you are experiencing problems "
3968                            "please contact your Intel or hardware "
3969                            "representative who provided you with this "
3970                            "hardware.\n");
3971                 break;
3972         default:
3973                 e_dev_err("Hardware Error: %d\n", err);
3974         }
3975
3976         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3977
3978         /* reprogram the RAR[0] in case user changed it. */
3979         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3980                             IXGBE_RAH_AV);
3981 }
3982
3983 /**
3984  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3985  * @rx_ring: ring to free buffers from
3986  **/
3987 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3988 {
3989         struct device *dev = rx_ring->dev;
3990         unsigned long size;
3991         u16 i;
3992
3993         /* ring already cleared, nothing to do */
3994         if (!rx_ring->rx_buffer_info)
3995                 return;
3996
3997         /* Free all the Rx ring sk_buffs */
3998         for (i = 0; i < rx_ring->count; i++) {
3999                 struct ixgbe_rx_buffer *rx_buffer_info;
4000
4001                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4002                 if (rx_buffer_info->dma) {
4003                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4004                                          rx_ring->rx_buf_len,
4005                                          DMA_FROM_DEVICE);
4006                         rx_buffer_info->dma = 0;
4007                 }
4008                 if (rx_buffer_info->skb) {
4009                         struct sk_buff *skb = rx_buffer_info->skb;
4010                         rx_buffer_info->skb = NULL;
4011                         do {
4012                                 struct sk_buff *this = skb;
4013                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
4014                                         dma_unmap_single(dev,
4015                                                          IXGBE_RSC_CB(this)->dma,
4016                                                          rx_ring->rx_buf_len,
4017                                                          DMA_FROM_DEVICE);
4018                                         IXGBE_RSC_CB(this)->dma = 0;
4019                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
4020                                 }
4021                                 skb = skb->prev;
4022                                 dev_kfree_skb(this);
4023                         } while (skb);
4024                 }
4025                 if (!rx_buffer_info->page)
4026                         continue;
4027                 if (rx_buffer_info->page_dma) {
4028                         dma_unmap_page(dev, rx_buffer_info->page_dma,
4029                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
4030                         rx_buffer_info->page_dma = 0;
4031                 }
4032                 put_page(rx_buffer_info->page);
4033                 rx_buffer_info->page = NULL;
4034                 rx_buffer_info->page_offset = 0;
4035         }
4036
4037         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4038         memset(rx_ring->rx_buffer_info, 0, size);
4039
4040         /* Zero out the descriptor ring */
4041         memset(rx_ring->desc, 0, rx_ring->size);
4042
4043         rx_ring->next_to_clean = 0;
4044         rx_ring->next_to_use = 0;
4045 }
4046
4047 /**
4048  * ixgbe_clean_tx_ring - Free Tx Buffers
4049  * @tx_ring: ring to be cleaned
4050  **/
4051 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4052 {
4053         struct ixgbe_tx_buffer *tx_buffer_info;
4054         unsigned long size;
4055         u16 i;
4056
4057         /* ring already cleared, nothing to do */
4058         if (!tx_ring->tx_buffer_info)
4059                 return;
4060
4061         /* Free all the Tx ring sk_buffs */
4062         for (i = 0; i < tx_ring->count; i++) {
4063                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4064                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4065         }
4066
4067         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4068         memset(tx_ring->tx_buffer_info, 0, size);
4069
4070         /* Zero out the descriptor ring */
4071         memset(tx_ring->desc, 0, tx_ring->size);
4072
4073         tx_ring->next_to_use = 0;
4074         tx_ring->next_to_clean = 0;
4075 }
4076
4077 /**
4078  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4079  * @adapter: board private structure
4080  **/
4081 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4082 {
4083         int i;
4084
4085         for (i = 0; i < adapter->num_rx_queues; i++)
4086                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4087 }
4088
4089 /**
4090  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4091  * @adapter: board private structure
4092  **/
4093 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4094 {
4095         int i;
4096
4097         for (i = 0; i < adapter->num_tx_queues; i++)
4098                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4099 }
4100
4101 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4102 {
4103         struct hlist_node *node, *node2;
4104         struct ixgbe_fdir_filter *filter;
4105
4106         spin_lock(&adapter->fdir_perfect_lock);
4107
4108         hlist_for_each_entry_safe(filter, node, node2,
4109                                   &adapter->fdir_filter_list, fdir_node) {
4110                 hlist_del(&filter->fdir_node);
4111                 kfree(filter);
4112         }
4113         adapter->fdir_filter_count = 0;
4114
4115         spin_unlock(&adapter->fdir_perfect_lock);
4116 }
4117
4118 void ixgbe_down(struct ixgbe_adapter *adapter)
4119 {
4120         struct net_device *netdev = adapter->netdev;
4121         struct ixgbe_hw *hw = &adapter->hw;
4122         u32 rxctrl;
4123         int i;
4124         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4125
4126         /* signal that we are down to the interrupt handler */
4127         set_bit(__IXGBE_DOWN, &adapter->state);
4128
4129         /* disable receives */
4130         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4131         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4132
4133         /* disable all enabled rx queues */
4134         for (i = 0; i < adapter->num_rx_queues; i++)
4135                 /* this call also flushes the previous write */
4136                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4137
4138         usleep_range(10000, 20000);
4139
4140         netif_tx_stop_all_queues(netdev);
4141
4142         /* call carrier off first to avoid false dev_watchdog timeouts */
4143         netif_carrier_off(netdev);
4144         netif_tx_disable(netdev);
4145
4146         ixgbe_irq_disable(adapter);
4147
4148         ixgbe_napi_disable_all(adapter);
4149
4150         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4151                              IXGBE_FLAG2_RESET_REQUESTED);
4152         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4153
4154         del_timer_sync(&adapter->service_timer);
4155
4156         /* disable receive for all VFs and wait one second */
4157         if (adapter->num_vfs) {
4158                 /* ping all the active vfs to let them know we are going down */
4159                 ixgbe_ping_all_vfs(adapter);
4160
4161                 /* Disable all VFTE/VFRE TX/RX */
4162                 ixgbe_disable_tx_rx(adapter);
4163
4164                 /* Mark all the VFs as inactive */
4165                 for (i = 0 ; i < adapter->num_vfs; i++)
4166                         adapter->vfinfo[i].clear_to_send = 0;
4167         }
4168
4169         /* Cleanup the affinity_hint CPU mask memory and callback */
4170         for (i = 0; i < num_q_vectors; i++) {
4171                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4172                 /* clear the affinity_mask in the IRQ descriptor */
4173                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4174                 /* release the CPU mask memory */
4175                 free_cpumask_var(q_vector->affinity_mask);
4176         }
4177
4178         /* disable transmits in the hardware now that interrupts are off */
4179         for (i = 0; i < adapter->num_tx_queues; i++) {
4180                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4181                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4182         }
4183
4184         /* Disable the Tx DMA engine on 82599 and X540 */
4185         switch (hw->mac.type) {
4186         case ixgbe_mac_82599EB:
4187         case ixgbe_mac_X540:
4188                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4189                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4190                                  ~IXGBE_DMATXCTL_TE));
4191                 break;
4192         default:
4193                 break;
4194         }
4195
4196         if (!pci_channel_offline(adapter->pdev))
4197                 ixgbe_reset(adapter);
4198
4199         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4200         if (hw->mac.ops.disable_tx_laser &&
4201             ((hw->phy.multispeed_fiber) ||
4202              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4203               (hw->mac.type == ixgbe_mac_82599EB))))
4204                 hw->mac.ops.disable_tx_laser(hw);
4205
4206         ixgbe_clean_all_tx_rings(adapter);
4207         ixgbe_clean_all_rx_rings(adapter);
4208
4209 #ifdef CONFIG_IXGBE_DCA
4210         /* since we reset the hardware DCA settings were cleared */
4211         ixgbe_setup_dca(adapter);
4212 #endif
4213 }
4214
4215 /**
4216  * ixgbe_poll - NAPI Rx polling callback
4217  * @napi: structure for representing this polling device
4218  * @budget: how many packets driver is allowed to clean
4219  *
4220  * This function is used for legacy and MSI, NAPI mode
4221  **/
4222 static int ixgbe_poll(struct napi_struct *napi, int budget)
4223 {
4224         struct ixgbe_q_vector *q_vector =
4225                                 container_of(napi, struct ixgbe_q_vector, napi);
4226         struct ixgbe_adapter *adapter = q_vector->adapter;
4227         int tx_clean_complete, work_done = 0;
4228
4229 #ifdef CONFIG_IXGBE_DCA
4230         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4231                 ixgbe_update_dca(q_vector);
4232 #endif
4233
4234         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4235         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4236
4237         if (!tx_clean_complete)
4238                 work_done = budget;
4239
4240         /* If budget not fully consumed, exit the polling mode */
4241         if (work_done < budget) {
4242                 napi_complete(napi);
4243                 if (adapter->rx_itr_setting & 1)
4244                         ixgbe_set_itr(q_vector);
4245                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4246                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4247         }
4248         return work_done;
4249 }
4250
4251 /**
4252  * ixgbe_tx_timeout - Respond to a Tx Hang
4253  * @netdev: network interface device structure
4254  **/
4255 static void ixgbe_tx_timeout(struct net_device *netdev)
4256 {
4257         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4258
4259         /* Do the reset outside of interrupt context */
4260         ixgbe_tx_timeout_reset(adapter);
4261 }
4262
4263 /**
4264  * ixgbe_set_rss_queues: Allocate queues for RSS
4265  * @adapter: board private structure to initialize
4266  *
4267  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4268  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4269  *
4270  **/
4271 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4272 {
4273         bool ret = false;
4274         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4275
4276         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4277                 f->mask = 0xF;
4278                 adapter->num_rx_queues = f->indices;
4279                 adapter->num_tx_queues = f->indices;
4280                 ret = true;
4281         } else {
4282                 ret = false;
4283         }
4284
4285         return ret;
4286 }
4287
4288 /**
4289  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4290  * @adapter: board private structure to initialize
4291  *
4292  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4293  * to the original CPU that initiated the Tx session.  This runs in addition
4294  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4295  * Rx load across CPUs using RSS.
4296  *
4297  **/
4298 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4299 {
4300         bool ret = false;
4301         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4302
4303         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4304         f_fdir->mask = 0;
4305
4306         /* Flow Director must have RSS enabled */
4307         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4308             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4309                 adapter->num_tx_queues = f_fdir->indices;
4310                 adapter->num_rx_queues = f_fdir->indices;
4311                 ret = true;
4312         } else {
4313                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4314         }
4315         return ret;
4316 }
4317
4318 #ifdef IXGBE_FCOE
4319 /**
4320  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4321  * @adapter: board private structure to initialize
4322  *
4323  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4324  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4325  * rx queues out of the max number of rx queues, instead, it is used as the
4326  * index of the first rx queue used by FCoE.
4327  *
4328  **/
4329 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4330 {
4331         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4332
4333         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4334                 return false;
4335
4336         f->indices = min((int)num_online_cpus(), f->indices);
4337
4338         adapter->num_rx_queues = 1;
4339         adapter->num_tx_queues = 1;
4340
4341         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4342                 e_info(probe, "FCoE enabled with RSS\n");
4343                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4344                         ixgbe_set_fdir_queues(adapter);
4345                 else
4346                         ixgbe_set_rss_queues(adapter);
4347         }
4348
4349         /* adding FCoE rx rings to the end */
4350         f->mask = adapter->num_rx_queues;
4351         adapter->num_rx_queues += f->indices;
4352         adapter->num_tx_queues += f->indices;
4353
4354         return true;
4355 }
4356 #endif /* IXGBE_FCOE */
4357
4358 /* Artificial max queue cap per traffic class in DCB mode */
4359 #define DCB_QUEUE_CAP 8
4360
4361 #ifdef CONFIG_IXGBE_DCB
4362 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4363 {
4364         int per_tc_q, q, i, offset = 0;
4365         struct net_device *dev = adapter->netdev;
4366         int tcs = netdev_get_num_tc(dev);
4367
4368         if (!tcs)
4369                 return false;
4370
4371         /* Map queue offset and counts onto allocated tx queues */
4372         per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4373         q = min((int)num_online_cpus(), per_tc_q);
4374
4375         for (i = 0; i < tcs; i++) {
4376                 netdev_set_prio_tc_map(dev, i, i);
4377                 netdev_set_tc_queue(dev, i, q, offset);
4378                 offset += q;
4379         }
4380
4381         adapter->num_tx_queues = q * tcs;
4382         adapter->num_rx_queues = q * tcs;
4383
4384 #ifdef IXGBE_FCOE
4385         /* FCoE enabled queues require special configuration indexed
4386          * by feature specific indices and mask. Here we map FCoE
4387          * indices onto the DCB queue pairs allowing FCoE to own
4388          * configuration later.
4389          */
4390         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4391                 int tc;
4392                 struct ixgbe_ring_feature *f =
4393                                         &adapter->ring_feature[RING_F_FCOE];
4394
4395                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4396                 f->indices = dev->tc_to_txq[tc].count;
4397                 f->mask = dev->tc_to_txq[tc].offset;
4398         }
4399 #endif
4400
4401         return true;
4402 }
4403 #endif
4404
4405 /**
4406  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4407  * @adapter: board private structure to initialize
4408  *
4409  * IOV doesn't actually use anything, so just NAK the
4410  * request for now and let the other queue routines
4411  * figure out what to do.
4412  */
4413 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4414 {
4415         return false;
4416 }
4417
4418 /*
4419  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4420  * @adapter: board private structure to initialize
4421  *
4422  * This is the top level queue allocation routine.  The order here is very
4423  * important, starting with the "most" number of features turned on at once,
4424  * and ending with the smallest set of features.  This way large combinations
4425  * can be allocated if they're turned on, and smaller combinations are the
4426  * fallthrough conditions.
4427  *
4428  **/
4429 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4430 {
4431         /* Start with base case */
4432         adapter->num_rx_queues = 1;
4433         adapter->num_tx_queues = 1;
4434         adapter->num_rx_pools = adapter->num_rx_queues;
4435         adapter->num_rx_queues_per_pool = 1;
4436
4437         if (ixgbe_set_sriov_queues(adapter))
4438                 goto done;
4439
4440 #ifdef CONFIG_IXGBE_DCB
4441         if (ixgbe_set_dcb_queues(adapter))
4442                 goto done;
4443
4444 #endif
4445 #ifdef IXGBE_FCOE
4446         if (ixgbe_set_fcoe_queues(adapter))
4447                 goto done;
4448
4449 #endif /* IXGBE_FCOE */
4450         if (ixgbe_set_fdir_queues(adapter))
4451                 goto done;
4452
4453         if (ixgbe_set_rss_queues(adapter))
4454                 goto done;
4455
4456         /* fallback to base case */
4457         adapter->num_rx_queues = 1;
4458         adapter->num_tx_queues = 1;
4459
4460 done:
4461         /* Notify the stack of the (possibly) reduced queue counts. */
4462         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4463         return netif_set_real_num_rx_queues(adapter->netdev,
4464                                             adapter->num_rx_queues);
4465 }
4466
4467 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4468                                        int vectors)
4469 {
4470         int err, vector_threshold;
4471
4472         /* We'll want at least 3 (vector_threshold):
4473          * 1) TxQ[0] Cleanup
4474          * 2) RxQ[0] Cleanup
4475          * 3) Other (Link Status Change, etc.)
4476          * 4) TCP Timer (optional)
4477          */
4478         vector_threshold = MIN_MSIX_COUNT;
4479
4480         /* The more we get, the more we will assign to Tx/Rx Cleanup
4481          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4482          * Right now, we simply care about how many we'll get; we'll
4483          * set them up later while requesting irq's.
4484          */
4485         while (vectors >= vector_threshold) {
4486                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4487                                       vectors);
4488                 if (!err) /* Success in acquiring all requested vectors. */
4489                         break;
4490                 else if (err < 0)
4491                         vectors = 0; /* Nasty failure, quit now */
4492                 else /* err == number of vectors we should try again with */
4493                         vectors = err;
4494         }
4495
4496         if (vectors < vector_threshold) {
4497                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4498                  * This just means we'll go with either a single MSI
4499                  * vector or fall back to legacy interrupts.
4500                  */
4501                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4502                              "Unable to allocate MSI-X interrupts\n");
4503                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4504                 kfree(adapter->msix_entries);
4505                 adapter->msix_entries = NULL;
4506         } else {
4507                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4508                 /*
4509                  * Adjust for only the vectors we'll use, which is minimum
4510                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4511                  * vectors we were allocated.
4512                  */
4513                 adapter->num_msix_vectors = min(vectors,
4514                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4515         }
4516 }
4517
4518 /**
4519  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4520  * @adapter: board private structure to initialize
4521  *
4522  * Cache the descriptor ring offsets for RSS to the assigned rings.
4523  *
4524  **/
4525 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4526 {
4527         int i;
4528
4529         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4530                 return false;
4531
4532         for (i = 0; i < adapter->num_rx_queues; i++)
4533                 adapter->rx_ring[i]->reg_idx = i;
4534         for (i = 0; i < adapter->num_tx_queues; i++)
4535                 adapter->tx_ring[i]->reg_idx = i;
4536
4537         return true;
4538 }
4539
4540 #ifdef CONFIG_IXGBE_DCB
4541
4542 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4543 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4544                                     unsigned int *tx, unsigned int *rx)
4545 {
4546         struct net_device *dev = adapter->netdev;
4547         struct ixgbe_hw *hw = &adapter->hw;
4548         u8 num_tcs = netdev_get_num_tc(dev);
4549
4550         *tx = 0;
4551         *rx = 0;
4552
4553         switch (hw->mac.type) {
4554         case ixgbe_mac_82598EB:
4555                 *tx = tc << 2;
4556                 *rx = tc << 3;
4557                 break;
4558         case ixgbe_mac_82599EB:
4559         case ixgbe_mac_X540:
4560                 if (num_tcs == 8) {
4561                         if (tc < 3) {
4562                                 *tx = tc << 5;
4563                                 *rx = tc << 4;
4564                         } else if (tc <  5) {
4565                                 *tx = ((tc + 2) << 4);
4566                                 *rx = tc << 4;
4567                         } else if (tc < num_tcs) {
4568                                 *tx = ((tc + 8) << 3);
4569                                 *rx = tc << 4;
4570                         }
4571                 } else if (num_tcs == 4) {
4572                         *rx =  tc << 5;
4573                         switch (tc) {
4574                         case 0:
4575                                 *tx =  0;
4576                                 break;
4577                         case 1:
4578                                 *tx = 64;
4579                                 break;
4580                         case 2:
4581                                 *tx = 96;
4582                                 break;
4583                         case 3:
4584                                 *tx = 112;
4585                                 break;
4586                         default:
4587                                 break;
4588                         }
4589                 }
4590                 break;
4591         default:
4592                 break;
4593         }
4594 }
4595
4596 /**
4597  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4598  * @adapter: board private structure to initialize
4599  *
4600  * Cache the descriptor ring offsets for DCB to the assigned rings.
4601  *
4602  **/
4603 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4604 {
4605         struct net_device *dev = adapter->netdev;
4606         int i, j, k;
4607         u8 num_tcs = netdev_get_num_tc(dev);
4608
4609         if (!num_tcs)
4610                 return false;
4611
4612         for (i = 0, k = 0; i < num_tcs; i++) {
4613                 unsigned int tx_s, rx_s;
4614                 u16 count = dev->tc_to_txq[i].count;
4615
4616                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4617                 for (j = 0; j < count; j++, k++) {
4618                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4619                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4620                         adapter->tx_ring[k]->dcb_tc = i;
4621                         adapter->rx_ring[k]->dcb_tc = i;
4622                 }
4623         }
4624
4625         return true;
4626 }
4627 #endif
4628
4629 /**
4630  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4631  * @adapter: board private structure to initialize
4632  *
4633  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4634  *
4635  **/
4636 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4637 {
4638         int i;
4639         bool ret = false;
4640
4641         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4642             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4643                 for (i = 0; i < adapter->num_rx_queues; i++)
4644                         adapter->rx_ring[i]->reg_idx = i;
4645                 for (i = 0; i < adapter->num_tx_queues; i++)
4646                         adapter->tx_ring[i]->reg_idx = i;
4647                 ret = true;
4648         }
4649
4650         return ret;
4651 }
4652
4653 #ifdef IXGBE_FCOE
4654 /**
4655  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4656  * @adapter: board private structure to initialize
4657  *
4658  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4659  *
4660  */
4661 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4662 {
4663         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4664         int i;
4665         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4666
4667         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4668                 return false;
4669
4670         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4671                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4672                         ixgbe_cache_ring_fdir(adapter);
4673                 else
4674                         ixgbe_cache_ring_rss(adapter);
4675
4676                 fcoe_rx_i = f->mask;
4677                 fcoe_tx_i = f->mask;
4678         }
4679         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4680                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4681                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4682         }
4683         return true;
4684 }
4685
4686 #endif /* IXGBE_FCOE */
4687 /**
4688  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4689  * @adapter: board private structure to initialize
4690  *
4691  * SR-IOV doesn't use any descriptor rings but changes the default if
4692  * no other mapping is used.
4693  *
4694  */
4695 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4696 {
4697         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4698         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4699         if (adapter->num_vfs)
4700                 return true;
4701         else
4702                 return false;
4703 }
4704
4705 /**
4706  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4707  * @adapter: board private structure to initialize
4708  *
4709  * Once we know the feature-set enabled for the device, we'll cache
4710  * the register offset the descriptor ring is assigned to.
4711  *
4712  * Note, the order the various feature calls is important.  It must start with
4713  * the "most" features enabled at the same time, then trickle down to the
4714  * least amount of features turned on at once.
4715  **/
4716 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4717 {
4718         /* start with default case */
4719         adapter->rx_ring[0]->reg_idx = 0;
4720         adapter->tx_ring[0]->reg_idx = 0;
4721
4722         if (ixgbe_cache_ring_sriov(adapter))
4723                 return;
4724
4725 #ifdef CONFIG_IXGBE_DCB
4726         if (ixgbe_cache_ring_dcb(adapter))
4727                 return;
4728 #endif
4729
4730 #ifdef IXGBE_FCOE
4731         if (ixgbe_cache_ring_fcoe(adapter))
4732                 return;
4733 #endif /* IXGBE_FCOE */
4734
4735         if (ixgbe_cache_ring_fdir(adapter))
4736                 return;
4737
4738         if (ixgbe_cache_ring_rss(adapter))
4739                 return;
4740 }
4741
4742 /**
4743  * ixgbe_alloc_queues - Allocate memory for all rings
4744  * @adapter: board private structure to initialize
4745  *
4746  * We allocate one ring per queue at run-time since we don't know the
4747  * number of queues at compile-time.  The polling_netdev array is
4748  * intended for Multiqueue, but should work fine with a single queue.
4749  **/
4750 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4751 {
4752         int rx = 0, tx = 0, nid = adapter->node;
4753
4754         if (nid < 0 || !node_online(nid))
4755                 nid = first_online_node;
4756
4757         for (; tx < adapter->num_tx_queues; tx++) {
4758                 struct ixgbe_ring *ring;
4759
4760                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4761                 if (!ring)
4762                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4763                 if (!ring)
4764                         goto err_allocation;
4765                 ring->count = adapter->tx_ring_count;
4766                 ring->queue_index = tx;
4767                 ring->numa_node = nid;
4768                 ring->dev = &adapter->pdev->dev;
4769                 ring->netdev = adapter->netdev;
4770
4771                 adapter->tx_ring[tx] = ring;
4772         }
4773
4774         for (; rx < adapter->num_rx_queues; rx++) {
4775                 struct ixgbe_ring *ring;
4776
4777                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4778                 if (!ring)
4779                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4780                 if (!ring)
4781                         goto err_allocation;
4782                 ring->count = adapter->rx_ring_count;
4783                 ring->queue_index = rx;
4784                 ring->numa_node = nid;
4785                 ring->dev = &adapter->pdev->dev;
4786                 ring->netdev = adapter->netdev;
4787
4788                 adapter->rx_ring[rx] = ring;
4789         }
4790
4791         ixgbe_cache_ring_register(adapter);
4792
4793         return 0;
4794
4795 err_allocation:
4796         while (tx)
4797                 kfree(adapter->tx_ring[--tx]);
4798
4799         while (rx)
4800                 kfree(adapter->rx_ring[--rx]);
4801         return -ENOMEM;
4802 }
4803
4804 /**
4805  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4806  * @adapter: board private structure to initialize
4807  *
4808  * Attempt to configure the interrupts using the best available
4809  * capabilities of the hardware and the kernel.
4810  **/
4811 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4812 {
4813         struct ixgbe_hw *hw = &adapter->hw;
4814         int err = 0;
4815         int vector, v_budget;
4816
4817         /*
4818          * It's easy to be greedy for MSI-X vectors, but it really
4819          * doesn't do us much good if we have a lot more vectors
4820          * than CPU's.  So let's be conservative and only ask for
4821          * (roughly) the same number of vectors as there are CPU's.
4822          */
4823         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4824                        (int)num_online_cpus()) + NON_Q_VECTORS;
4825
4826         /*
4827          * At the same time, hardware can only support a maximum of
4828          * hw.mac->max_msix_vectors vectors.  With features
4829          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4830          * descriptor queues supported by our device.  Thus, we cap it off in
4831          * those rare cases where the cpu count also exceeds our vector limit.
4832          */
4833         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4834
4835         /* A failure in MSI-X entry allocation isn't fatal, but it does
4836          * mean we disable MSI-X capabilities of the adapter. */
4837         adapter->msix_entries = kcalloc(v_budget,
4838                                         sizeof(struct msix_entry), GFP_KERNEL);
4839         if (adapter->msix_entries) {
4840                 for (vector = 0; vector < v_budget; vector++)
4841                         adapter->msix_entries[vector].entry = vector;
4842
4843                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4844
4845                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4846                         goto out;
4847         }
4848
4849         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4850         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4851         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4852                 e_err(probe,
4853                       "ATR is not supported while multiple "
4854                       "queues are disabled.  Disabling Flow Director\n");
4855         }
4856         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4857         adapter->atr_sample_rate = 0;
4858         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4859                 ixgbe_disable_sriov(adapter);
4860
4861         err = ixgbe_set_num_queues(adapter);
4862         if (err)
4863                 return err;
4864
4865         err = pci_enable_msi(adapter->pdev);
4866         if (!err) {
4867                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4868         } else {
4869                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4870                              "Unable to allocate MSI interrupt, "
4871                              "falling back to legacy.  Error: %d\n", err);
4872                 /* reset err */
4873                 err = 0;
4874         }
4875
4876 out:
4877         return err;
4878 }
4879
4880 /**
4881  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4882  * @adapter: board private structure to initialize
4883  *
4884  * We allocate one q_vector per queue interrupt.  If allocation fails we
4885  * return -ENOMEM.
4886  **/
4887 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4888 {
4889         int q_idx, num_q_vectors;
4890         struct ixgbe_q_vector *q_vector;
4891         int (*poll)(struct napi_struct *, int);
4892
4893         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4894                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4895                 poll = &ixgbe_clean_rxtx_many;
4896         } else {
4897                 num_q_vectors = 1;
4898                 poll = &ixgbe_poll;
4899         }
4900
4901         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4902                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4903                                         GFP_KERNEL, adapter->node);
4904                 if (!q_vector)
4905                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4906                                            GFP_KERNEL);
4907                 if (!q_vector)
4908                         goto err_out;
4909                 q_vector->adapter = adapter;
4910                 if (q_vector->tx.count && !q_vector->rx.count)
4911                         q_vector->eitr = adapter->tx_eitr_param;
4912                 else
4913                         q_vector->eitr = adapter->rx_eitr_param;
4914                 q_vector->v_idx = q_idx;
4915                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4916                 adapter->q_vector[q_idx] = q_vector;
4917         }
4918
4919         return 0;
4920
4921 err_out:
4922         while (q_idx) {
4923                 q_idx--;
4924                 q_vector = adapter->q_vector[q_idx];
4925                 netif_napi_del(&q_vector->napi);
4926                 kfree(q_vector);
4927                 adapter->q_vector[q_idx] = NULL;
4928         }
4929         return -ENOMEM;
4930 }
4931
4932 /**
4933  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4934  * @adapter: board private structure to initialize
4935  *
4936  * This function frees the memory allocated to the q_vectors.  In addition if
4937  * NAPI is enabled it will delete any references to the NAPI struct prior
4938  * to freeing the q_vector.
4939  **/
4940 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4941 {
4942         int q_idx, num_q_vectors;
4943
4944         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4945                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4946         else
4947                 num_q_vectors = 1;
4948
4949         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4950                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4951                 adapter->q_vector[q_idx] = NULL;
4952                 netif_napi_del(&q_vector->napi);
4953                 kfree(q_vector);
4954         }
4955 }
4956
4957 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4958 {
4959         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4960                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4961                 pci_disable_msix(adapter->pdev);
4962                 kfree(adapter->msix_entries);
4963                 adapter->msix_entries = NULL;
4964         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4965                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4966                 pci_disable_msi(adapter->pdev);
4967         }
4968 }
4969
4970 /**
4971  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4972  * @adapter: board private structure to initialize
4973  *
4974  * We determine which interrupt scheme to use based on...
4975  * - Kernel support (MSI, MSI-X)
4976  *   - which can be user-defined (via MODULE_PARAM)
4977  * - Hardware queue count (num_*_queues)
4978  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4979  **/
4980 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4981 {
4982         int err;
4983
4984         /* Number of supported queues */
4985         err = ixgbe_set_num_queues(adapter);
4986         if (err)
4987                 return err;
4988
4989         err = ixgbe_set_interrupt_capability(adapter);
4990         if (err) {
4991                 e_dev_err("Unable to setup interrupt capabilities\n");
4992                 goto err_set_interrupt;
4993         }
4994
4995         err = ixgbe_alloc_q_vectors(adapter);
4996         if (err) {
4997                 e_dev_err("Unable to allocate memory for queue vectors\n");
4998                 goto err_alloc_q_vectors;
4999         }
5000
5001         err = ixgbe_alloc_queues(adapter);
5002         if (err) {
5003                 e_dev_err("Unable to allocate memory for queues\n");
5004                 goto err_alloc_queues;
5005         }
5006
5007         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5008                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5009                    adapter->num_rx_queues, adapter->num_tx_queues);
5010
5011         set_bit(__IXGBE_DOWN, &adapter->state);
5012
5013         return 0;
5014
5015 err_alloc_queues:
5016         ixgbe_free_q_vectors(adapter);
5017 err_alloc_q_vectors:
5018         ixgbe_reset_interrupt_capability(adapter);
5019 err_set_interrupt:
5020         return err;
5021 }
5022
5023 /**
5024  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5025  * @adapter: board private structure to clear interrupt scheme on
5026  *
5027  * We go through and clear interrupt specific resources and reset the structure
5028  * to pre-load conditions
5029  **/
5030 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5031 {
5032         int i;
5033
5034         for (i = 0; i < adapter->num_tx_queues; i++) {
5035                 kfree(adapter->tx_ring[i]);
5036                 adapter->tx_ring[i] = NULL;
5037         }
5038         for (i = 0; i < adapter->num_rx_queues; i++) {
5039                 struct ixgbe_ring *ring = adapter->rx_ring[i];
5040
5041                 /* ixgbe_get_stats64() might access this ring, we must wait
5042                  * a grace period before freeing it.
5043                  */
5044                 kfree_rcu(ring, rcu);
5045                 adapter->rx_ring[i] = NULL;
5046         }
5047
5048         adapter->num_tx_queues = 0;
5049         adapter->num_rx_queues = 0;
5050
5051         ixgbe_free_q_vectors(adapter);
5052         ixgbe_reset_interrupt_capability(adapter);
5053 }
5054
5055 /**
5056  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5057  * @adapter: board private structure to initialize
5058  *
5059  * ixgbe_sw_init initializes the Adapter private data structure.
5060  * Fields are initialized based on PCI device information and
5061  * OS network device settings (MTU size).
5062  **/
5063 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5064 {
5065         struct ixgbe_hw *hw = &adapter->hw;
5066         struct pci_dev *pdev = adapter->pdev;
5067         struct net_device *dev = adapter->netdev;
5068         unsigned int rss;
5069 #ifdef CONFIG_IXGBE_DCB
5070         int j;
5071         struct tc_configuration *tc;
5072 #endif
5073         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5074
5075         /* PCI config space info */
5076
5077         hw->vendor_id = pdev->vendor;
5078         hw->device_id = pdev->device;
5079         hw->revision_id = pdev->revision;
5080         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5081         hw->subsystem_device_id = pdev->subsystem_device;
5082
5083         /* Set capability flags */
5084         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5085         adapter->ring_feature[RING_F_RSS].indices = rss;
5086         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5087         switch (hw->mac.type) {
5088         case ixgbe_mac_82598EB:
5089                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5090                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5091                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5092                 break;
5093         case ixgbe_mac_82599EB:
5094         case ixgbe_mac_X540:
5095                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5096                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5097                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5098                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5099                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5100                 /* Flow Director hash filters enabled */
5101                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5102                 adapter->atr_sample_rate = 20;
5103                 adapter->ring_feature[RING_F_FDIR].indices =
5104                                                          IXGBE_MAX_FDIR_INDICES;
5105                 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5106 #ifdef IXGBE_FCOE
5107                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5108                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5109                 adapter->ring_feature[RING_F_FCOE].indices = 0;
5110 #ifdef CONFIG_IXGBE_DCB
5111                 /* Default traffic class to use for FCoE */
5112                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5113 #endif
5114 #endif /* IXGBE_FCOE */
5115                 break;
5116         default:
5117                 break;
5118         }
5119
5120         /* n-tuple support exists, always init our spinlock */
5121         spin_lock_init(&adapter->fdir_perfect_lock);
5122
5123 #ifdef CONFIG_IXGBE_DCB
5124         /* Configure DCB traffic classes */
5125         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5126                 tc = &adapter->dcb_cfg.tc_config[j];
5127                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5128                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5129                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5130                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5131                 tc->dcb_pfc = pfc_disabled;
5132         }
5133         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5134         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5135         adapter->dcb_cfg.pfc_mode_enable = false;
5136         adapter->dcb_set_bitmap = 0x00;
5137         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5138         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5139                            MAX_TRAFFIC_CLASS);
5140
5141 #endif
5142
5143         /* default flow control settings */
5144         hw->fc.requested_mode = ixgbe_fc_full;
5145         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5146 #ifdef CONFIG_DCB
5147         adapter->last_lfc_mode = hw->fc.current_mode;
5148 #endif
5149         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5150         hw->fc.low_water = FC_LOW_WATER(max_frame);
5151         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5152         hw->fc.send_xon = true;
5153         hw->fc.disable_fc_autoneg = false;
5154
5155         /* enable itr by default in dynamic mode */
5156         adapter->rx_itr_setting = 1;
5157         adapter->rx_eitr_param = 20000;
5158         adapter->tx_itr_setting = 1;
5159         adapter->tx_eitr_param = 10000;
5160
5161         /* set defaults for eitr in MegaBytes */
5162         adapter->eitr_low = 10;
5163         adapter->eitr_high = 20;
5164
5165         /* set default ring sizes */
5166         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5167         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5168
5169         /* set default work limits */
5170         adapter->tx_work_limit = adapter->tx_ring_count;
5171
5172         /* initialize eeprom parameters */
5173         if (ixgbe_init_eeprom_params_generic(hw)) {
5174                 e_dev_err("EEPROM initialization failed\n");
5175                 return -EIO;
5176         }
5177
5178         /* enable rx csum by default */
5179         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5180
5181         /* get assigned NUMA node */
5182         adapter->node = dev_to_node(&pdev->dev);
5183
5184         set_bit(__IXGBE_DOWN, &adapter->state);
5185
5186         return 0;
5187 }
5188
5189 /**
5190  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5191  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5192  *
5193  * Return 0 on success, negative on failure
5194  **/
5195 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5196 {
5197         struct device *dev = tx_ring->dev;
5198         int size;
5199
5200         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5201         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5202         if (!tx_ring->tx_buffer_info)
5203                 tx_ring->tx_buffer_info = vzalloc(size);
5204         if (!tx_ring->tx_buffer_info)
5205                 goto err;
5206
5207         /* round up to nearest 4K */
5208         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5209         tx_ring->size = ALIGN(tx_ring->size, 4096);
5210
5211         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5212                                            &tx_ring->dma, GFP_KERNEL);
5213         if (!tx_ring->desc)
5214                 goto err;
5215
5216         tx_ring->next_to_use = 0;
5217         tx_ring->next_to_clean = 0;
5218         return 0;
5219
5220 err:
5221         vfree(tx_ring->tx_buffer_info);
5222         tx_ring->tx_buffer_info = NULL;
5223         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5224         return -ENOMEM;
5225 }
5226
5227 /**
5228  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5229  * @adapter: board private structure
5230  *
5231  * If this function returns with an error, then it's possible one or
5232  * more of the rings is populated (while the rest are not).  It is the
5233  * callers duty to clean those orphaned rings.
5234  *
5235  * Return 0 on success, negative on failure
5236  **/
5237 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5238 {
5239         int i, err = 0;
5240
5241         for (i = 0; i < adapter->num_tx_queues; i++) {
5242                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5243                 if (!err)
5244                         continue;
5245                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5246                 break;
5247         }
5248
5249         return err;
5250 }
5251
5252 /**
5253  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5254  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5255  *
5256  * Returns 0 on success, negative on failure
5257  **/
5258 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5259 {
5260         struct device *dev = rx_ring->dev;
5261         int size;
5262
5263         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5264         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5265         if (!rx_ring->rx_buffer_info)
5266                 rx_ring->rx_buffer_info = vzalloc(size);
5267         if (!rx_ring->rx_buffer_info)
5268                 goto err;
5269
5270         /* Round up to nearest 4K */
5271         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5272         rx_ring->size = ALIGN(rx_ring->size, 4096);
5273
5274         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5275                                            &rx_ring->dma, GFP_KERNEL);
5276
5277         if (!rx_ring->desc)
5278                 goto err;
5279
5280         rx_ring->next_to_clean = 0;
5281         rx_ring->next_to_use = 0;
5282
5283         return 0;
5284 err:
5285         vfree(rx_ring->rx_buffer_info);
5286         rx_ring->rx_buffer_info = NULL;
5287         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5288         return -ENOMEM;
5289 }
5290
5291 /**
5292  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5293  * @adapter: board private structure
5294  *
5295  * If this function returns with an error, then it's possible one or
5296  * more of the rings is populated (while the rest are not).  It is the
5297  * callers duty to clean those orphaned rings.
5298  *
5299  * Return 0 on success, negative on failure
5300  **/
5301 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5302 {
5303         int i, err = 0;
5304
5305         for (i = 0; i < adapter->num_rx_queues; i++) {
5306                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5307                 if (!err)
5308                         continue;
5309                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5310                 break;
5311         }
5312
5313         return err;
5314 }
5315
5316 /**
5317  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5318  * @tx_ring: Tx descriptor ring for a specific queue
5319  *
5320  * Free all transmit software resources
5321  **/
5322 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5323 {
5324         ixgbe_clean_tx_ring(tx_ring);
5325
5326         vfree(tx_ring->tx_buffer_info);
5327         tx_ring->tx_buffer_info = NULL;
5328
5329         /* if not set, then don't free */
5330         if (!tx_ring->desc)
5331                 return;
5332
5333         dma_free_coherent(tx_ring->dev, tx_ring->size,
5334                           tx_ring->desc, tx_ring->dma);
5335
5336         tx_ring->desc = NULL;
5337 }
5338
5339 /**
5340  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5341  * @adapter: board private structure
5342  *
5343  * Free all transmit software resources
5344  **/
5345 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5346 {
5347         int i;
5348
5349         for (i = 0; i < adapter->num_tx_queues; i++)
5350                 if (adapter->tx_ring[i]->desc)
5351                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5352 }
5353
5354 /**
5355  * ixgbe_free_rx_resources - Free Rx Resources
5356  * @rx_ring: ring to clean the resources from
5357  *
5358  * Free all receive software resources
5359  **/
5360 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5361 {
5362         ixgbe_clean_rx_ring(rx_ring);
5363
5364         vfree(rx_ring->rx_buffer_info);
5365         rx_ring->rx_buffer_info = NULL;
5366
5367         /* if not set, then don't free */
5368         if (!rx_ring->desc)
5369                 return;
5370
5371         dma_free_coherent(rx_ring->dev, rx_ring->size,
5372                           rx_ring->desc, rx_ring->dma);
5373
5374         rx_ring->desc = NULL;
5375 }
5376
5377 /**
5378  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5379  * @adapter: board private structure
5380  *
5381  * Free all receive software resources
5382  **/
5383 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5384 {
5385         int i;
5386
5387         for (i = 0; i < adapter->num_rx_queues; i++)
5388                 if (adapter->rx_ring[i]->desc)
5389                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5390 }
5391
5392 /**
5393  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5394  * @netdev: network interface device structure
5395  * @new_mtu: new value for maximum frame size
5396  *
5397  * Returns 0 on success, negative on failure
5398  **/
5399 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5400 {
5401         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5402         struct ixgbe_hw *hw = &adapter->hw;
5403         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5404
5405         /* MTU < 68 is an error and causes problems on some kernels */
5406         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5407             hw->mac.type != ixgbe_mac_X540) {
5408                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5409                         return -EINVAL;
5410         } else {
5411                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5412                         return -EINVAL;
5413         }
5414
5415         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5416         /* must set new MTU before calling down or up */
5417         netdev->mtu = new_mtu;
5418
5419         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5420         hw->fc.low_water = FC_LOW_WATER(max_frame);
5421
5422         if (netif_running(netdev))
5423                 ixgbe_reinit_locked(adapter);
5424
5425         return 0;
5426 }
5427
5428 /**
5429  * ixgbe_open - Called when a network interface is made active
5430  * @netdev: network interface device structure
5431  *
5432  * Returns 0 on success, negative value on failure
5433  *
5434  * The open entry point is called when a network interface is made
5435  * active by the system (IFF_UP).  At this point all resources needed
5436  * for transmit and receive operations are allocated, the interrupt
5437  * handler is registered with the OS, the watchdog timer is started,
5438  * and the stack is notified that the interface is ready.
5439  **/
5440 static int ixgbe_open(struct net_device *netdev)
5441 {
5442         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5443         int err;
5444
5445         /* disallow open during test */
5446         if (test_bit(__IXGBE_TESTING, &adapter->state))
5447                 return -EBUSY;
5448
5449         netif_carrier_off(netdev);
5450
5451         /* allocate transmit descriptors */
5452         err = ixgbe_setup_all_tx_resources(adapter);
5453         if (err)
5454                 goto err_setup_tx;
5455
5456         /* allocate receive descriptors */
5457         err = ixgbe_setup_all_rx_resources(adapter);
5458         if (err)
5459                 goto err_setup_rx;
5460
5461         ixgbe_configure(adapter);
5462
5463         err = ixgbe_request_irq(adapter);
5464         if (err)
5465                 goto err_req_irq;
5466
5467         err = ixgbe_up_complete(adapter);
5468         if (err)
5469                 goto err_up;
5470
5471         netif_tx_start_all_queues(netdev);
5472
5473         return 0;
5474
5475 err_up:
5476         ixgbe_release_hw_control(adapter);
5477         ixgbe_free_irq(adapter);
5478 err_req_irq:
5479 err_setup_rx:
5480         ixgbe_free_all_rx_resources(adapter);
5481 err_setup_tx:
5482         ixgbe_free_all_tx_resources(adapter);
5483         ixgbe_reset(adapter);
5484
5485         return err;
5486 }
5487
5488 /**
5489  * ixgbe_close - Disables a network interface
5490  * @netdev: network interface device structure
5491  *
5492  * Returns 0, this is not allowed to fail
5493  *
5494  * The close entry point is called when an interface is de-activated
5495  * by the OS.  The hardware is still under the drivers control, but
5496  * needs to be disabled.  A global MAC reset is issued to stop the
5497  * hardware, and all transmit and receive resources are freed.
5498  **/
5499 static int ixgbe_close(struct net_device *netdev)
5500 {
5501         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5502
5503         ixgbe_down(adapter);
5504         ixgbe_free_irq(adapter);
5505
5506         ixgbe_fdir_filter_exit(adapter);
5507
5508         ixgbe_free_all_tx_resources(adapter);
5509         ixgbe_free_all_rx_resources(adapter);
5510
5511         ixgbe_release_hw_control(adapter);
5512
5513         return 0;
5514 }
5515
5516 #ifdef CONFIG_PM
5517 static int ixgbe_resume(struct pci_dev *pdev)
5518 {
5519         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5520         struct net_device *netdev = adapter->netdev;
5521         u32 err;
5522
5523         pci_set_power_state(pdev, PCI_D0);
5524         pci_restore_state(pdev);
5525         /*
5526          * pci_restore_state clears dev->state_saved so call
5527          * pci_save_state to restore it.
5528          */
5529         pci_save_state(pdev);
5530
5531         err = pci_enable_device_mem(pdev);
5532         if (err) {
5533                 e_dev_err("Cannot enable PCI device from suspend\n");
5534                 return err;
5535         }
5536         pci_set_master(pdev);
5537
5538         pci_wake_from_d3(pdev, false);
5539
5540         err = ixgbe_init_interrupt_scheme(adapter);
5541         if (err) {
5542                 e_dev_err("Cannot initialize interrupts for device\n");
5543                 return err;
5544         }
5545
5546         ixgbe_reset(adapter);
5547
5548         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5549
5550         if (netif_running(netdev)) {
5551                 err = ixgbe_open(netdev);
5552                 if (err)
5553                         return err;
5554         }
5555
5556         netif_device_attach(netdev);
5557
5558         return 0;
5559 }
5560 #endif /* CONFIG_PM */
5561
5562 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5563 {
5564         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5565         struct net_device *netdev = adapter->netdev;
5566         struct ixgbe_hw *hw = &adapter->hw;
5567         u32 ctrl, fctrl;
5568         u32 wufc = adapter->wol;
5569 #ifdef CONFIG_PM
5570         int retval = 0;
5571 #endif
5572
5573         netif_device_detach(netdev);
5574
5575         if (netif_running(netdev)) {
5576                 ixgbe_down(adapter);
5577                 ixgbe_free_irq(adapter);
5578                 ixgbe_free_all_tx_resources(adapter);
5579                 ixgbe_free_all_rx_resources(adapter);
5580         }
5581
5582         ixgbe_clear_interrupt_scheme(adapter);
5583 #ifdef CONFIG_DCB
5584         kfree(adapter->ixgbe_ieee_pfc);
5585         kfree(adapter->ixgbe_ieee_ets);
5586 #endif
5587
5588 #ifdef CONFIG_PM
5589         retval = pci_save_state(pdev);
5590         if (retval)
5591                 return retval;
5592
5593 #endif
5594         if (wufc) {
5595                 ixgbe_set_rx_mode(netdev);
5596
5597                 /* turn on all-multi mode if wake on multicast is enabled */
5598                 if (wufc & IXGBE_WUFC_MC) {
5599                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5600                         fctrl |= IXGBE_FCTRL_MPE;
5601                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5602                 }
5603
5604                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5605                 ctrl |= IXGBE_CTRL_GIO_DIS;
5606                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5607
5608                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5609         } else {
5610                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5611                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5612         }
5613
5614         switch (hw->mac.type) {
5615         case ixgbe_mac_82598EB:
5616                 pci_wake_from_d3(pdev, false);
5617                 break;
5618         case ixgbe_mac_82599EB:
5619         case ixgbe_mac_X540:
5620                 pci_wake_from_d3(pdev, !!wufc);
5621                 break;
5622         default:
5623                 break;
5624         }
5625
5626         *enable_wake = !!wufc;
5627
5628         ixgbe_release_hw_control(adapter);
5629
5630         pci_disable_device(pdev);
5631
5632         return 0;
5633 }
5634
5635 #ifdef CONFIG_PM
5636 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5637 {
5638         int retval;
5639         bool wake;
5640
5641         retval = __ixgbe_shutdown(pdev, &wake);
5642         if (retval)
5643                 return retval;
5644
5645         if (wake) {
5646                 pci_prepare_to_sleep(pdev);
5647         } else {
5648                 pci_wake_from_d3(pdev, false);
5649                 pci_set_power_state(pdev, PCI_D3hot);
5650         }
5651
5652         return 0;
5653 }
5654 #endif /* CONFIG_PM */
5655
5656 static void ixgbe_shutdown(struct pci_dev *pdev)
5657 {
5658         bool wake;
5659
5660         __ixgbe_shutdown(pdev, &wake);
5661
5662         if (system_state == SYSTEM_POWER_OFF) {
5663                 pci_wake_from_d3(pdev, wake);
5664                 pci_set_power_state(pdev, PCI_D3hot);
5665         }
5666 }
5667
5668 /**
5669  * ixgbe_update_stats - Update the board statistics counters.
5670  * @adapter: board private structure
5671  **/
5672 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5673 {
5674         struct net_device *netdev = adapter->netdev;
5675         struct ixgbe_hw *hw = &adapter->hw;
5676         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5677         u64 total_mpc = 0;
5678         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5679         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5680         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5681         u64 bytes = 0, packets = 0;
5682
5683         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5684             test_bit(__IXGBE_RESETTING, &adapter->state))
5685                 return;
5686
5687         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5688                 u64 rsc_count = 0;
5689                 u64 rsc_flush = 0;
5690                 for (i = 0; i < 16; i++)
5691                         adapter->hw_rx_no_dma_resources +=
5692                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5693                 for (i = 0; i < adapter->num_rx_queues; i++) {
5694                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5695                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5696                 }
5697                 adapter->rsc_total_count = rsc_count;
5698                 adapter->rsc_total_flush = rsc_flush;
5699         }
5700
5701         for (i = 0; i < adapter->num_rx_queues; i++) {
5702                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5703                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5704                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5705                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5706                 bytes += rx_ring->stats.bytes;
5707                 packets += rx_ring->stats.packets;
5708         }
5709         adapter->non_eop_descs = non_eop_descs;
5710         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5711         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5712         netdev->stats.rx_bytes = bytes;
5713         netdev->stats.rx_packets = packets;
5714
5715         bytes = 0;
5716         packets = 0;
5717         /* gather some stats to the adapter struct that are per queue */
5718         for (i = 0; i < adapter->num_tx_queues; i++) {
5719                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5720                 restart_queue += tx_ring->tx_stats.restart_queue;
5721                 tx_busy += tx_ring->tx_stats.tx_busy;
5722                 bytes += tx_ring->stats.bytes;
5723                 packets += tx_ring->stats.packets;
5724         }
5725         adapter->restart_queue = restart_queue;
5726         adapter->tx_busy = tx_busy;
5727         netdev->stats.tx_bytes = bytes;
5728         netdev->stats.tx_packets = packets;
5729
5730         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5731         for (i = 0; i < 8; i++) {
5732                 /* for packet buffers not used, the register should read 0 */
5733                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5734                 missed_rx += mpc;
5735                 hwstats->mpc[i] += mpc;
5736                 total_mpc += hwstats->mpc[i];
5737                 if (hw->mac.type == ixgbe_mac_82598EB)
5738                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5739                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5740                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5741                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5742                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5743                 switch (hw->mac.type) {
5744                 case ixgbe_mac_82598EB:
5745                         hwstats->pxonrxc[i] +=
5746                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5747                         break;
5748                 case ixgbe_mac_82599EB:
5749                 case ixgbe_mac_X540:
5750                         hwstats->pxonrxc[i] +=
5751                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5752                         break;
5753                 default:
5754                         break;
5755                 }
5756                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5757                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5758         }
5759         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5760         /* work around hardware counting issue */
5761         hwstats->gprc -= missed_rx;
5762
5763         ixgbe_update_xoff_received(adapter);
5764
5765         /* 82598 hardware only has a 32 bit counter in the high register */
5766         switch (hw->mac.type) {
5767         case ixgbe_mac_82598EB:
5768                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5769                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5770                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5771                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5772                 break;
5773         case ixgbe_mac_X540:
5774                 /* OS2BMC stats are X540 only*/
5775                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5776                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5777                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5778                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5779         case ixgbe_mac_82599EB:
5780                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5781                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5782                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5783                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5784                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5785                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5786                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5787                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5788                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5789 #ifdef IXGBE_FCOE
5790                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5791                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5792                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5793                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5794                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5795                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5796 #endif /* IXGBE_FCOE */
5797                 break;
5798         default:
5799                 break;
5800         }
5801         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5802         hwstats->bprc += bprc;
5803         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5804         if (hw->mac.type == ixgbe_mac_82598EB)
5805                 hwstats->mprc -= bprc;
5806         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5807         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5808         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5809         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5810         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5811         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5812         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5813         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5814         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5815         hwstats->lxontxc += lxon;
5816         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5817         hwstats->lxofftxc += lxoff;
5818         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5819         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5820         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5821         /*
5822          * 82598 errata - tx of flow control packets is included in tx counters
5823          */
5824         xon_off_tot = lxon + lxoff;
5825         hwstats->gptc -= xon_off_tot;
5826         hwstats->mptc -= xon_off_tot;
5827         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5828         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5829         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5830         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5831         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5832         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5833         hwstats->ptc64 -= xon_off_tot;
5834         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5835         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5836         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5837         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5838         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5839         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5840
5841         /* Fill out the OS statistics structure */
5842         netdev->stats.multicast = hwstats->mprc;
5843
5844         /* Rx Errors */
5845         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5846         netdev->stats.rx_dropped = 0;
5847         netdev->stats.rx_length_errors = hwstats->rlec;
5848         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5849         netdev->stats.rx_missed_errors = total_mpc;
5850 }
5851
5852 /**
5853  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5854  * @adapter - pointer to the device adapter structure
5855  **/
5856 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5857 {
5858         struct ixgbe_hw *hw = &adapter->hw;
5859         int i;
5860
5861         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5862                 return;
5863
5864         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5865
5866         /* if interface is down do nothing */
5867         if (test_bit(__IXGBE_DOWN, &adapter->state))
5868                 return;
5869
5870         /* do nothing if we are not using signature filters */
5871         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5872                 return;
5873
5874         adapter->fdir_overflow++;
5875
5876         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5877                 for (i = 0; i < adapter->num_tx_queues; i++)
5878                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5879                                 &(adapter->tx_ring[i]->state));
5880                 /* re-enable flow director interrupts */
5881                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5882         } else {
5883                 e_err(probe, "failed to finish FDIR re-initialization, "
5884                       "ignored adding FDIR ATR filters\n");
5885         }
5886 }
5887
5888 /**
5889  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5890  * @adapter - pointer to the device adapter structure
5891  *
5892  * This function serves two purposes.  First it strobes the interrupt lines
5893  * in order to make certain interrupts are occuring.  Secondly it sets the
5894  * bits needed to check for TX hangs.  As a result we should immediately
5895  * determine if a hang has occured.
5896  */
5897 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5898 {
5899         struct ixgbe_hw *hw = &adapter->hw;
5900         u64 eics = 0;
5901         int i;
5902
5903         /* If we're down or resetting, just bail */
5904         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5905             test_bit(__IXGBE_RESETTING, &adapter->state))
5906                 return;
5907
5908         /* Force detection of hung controller */
5909         if (netif_carrier_ok(adapter->netdev)) {
5910                 for (i = 0; i < adapter->num_tx_queues; i++)
5911                         set_check_for_tx_hang(adapter->tx_ring[i]);
5912         }
5913
5914         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5915                 /*
5916                  * for legacy and MSI interrupts don't set any bits
5917                  * that are enabled for EIAM, because this operation
5918                  * would set *both* EIMS and EICS for any bit in EIAM
5919                  */
5920                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5921                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5922         } else {
5923                 /* get one bit for every active tx/rx interrupt vector */
5924                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5925                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
5926                         if (qv->rx.count || qv->tx.count)
5927                                 eics |= ((u64)1 << i);
5928                 }
5929         }
5930
5931         /* Cause software interrupt to ensure rings are cleaned */
5932         ixgbe_irq_rearm_queues(adapter, eics);
5933
5934 }
5935
5936 /**
5937  * ixgbe_watchdog_update_link - update the link status
5938  * @adapter - pointer to the device adapter structure
5939  * @link_speed - pointer to a u32 to store the link_speed
5940  **/
5941 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5942 {
5943         struct ixgbe_hw *hw = &adapter->hw;
5944         u32 link_speed = adapter->link_speed;
5945         bool link_up = adapter->link_up;
5946         int i;
5947
5948         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5949                 return;
5950
5951         if (hw->mac.ops.check_link) {
5952                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5953         } else {
5954                 /* always assume link is up, if no check link function */
5955                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5956                 link_up = true;
5957         }
5958         if (link_up) {
5959                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5960                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5961                                 hw->mac.ops.fc_enable(hw, i);
5962                 } else {
5963                         hw->mac.ops.fc_enable(hw, 0);
5964                 }
5965         }
5966
5967         if (link_up ||
5968             time_after(jiffies, (adapter->link_check_timeout +
5969                                  IXGBE_TRY_LINK_TIMEOUT))) {
5970                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5971                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5972                 IXGBE_WRITE_FLUSH(hw);
5973         }
5974
5975         adapter->link_up = link_up;
5976         adapter->link_speed = link_speed;
5977 }
5978
5979 /**
5980  * ixgbe_watchdog_link_is_up - update netif_carrier status and
5981  *                             print link up message
5982  * @adapter - pointer to the device adapter structure
5983  **/
5984 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5985 {
5986         struct net_device *netdev = adapter->netdev;
5987         struct ixgbe_hw *hw = &adapter->hw;
5988         u32 link_speed = adapter->link_speed;
5989         bool flow_rx, flow_tx;
5990
5991         /* only continue if link was previously down */
5992         if (netif_carrier_ok(netdev))
5993                 return;
5994
5995         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5996
5997         switch (hw->mac.type) {
5998         case ixgbe_mac_82598EB: {
5999                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6000                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6001                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6002                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6003         }
6004                 break;
6005         case ixgbe_mac_X540:
6006         case ixgbe_mac_82599EB: {
6007                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6008                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6009                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6010                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6011         }
6012                 break;
6013         default:
6014                 flow_tx = false;
6015                 flow_rx = false;
6016                 break;
6017         }
6018         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6019                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6020                "10 Gbps" :
6021                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6022                "1 Gbps" :
6023                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6024                "100 Mbps" :
6025                "unknown speed"))),
6026                ((flow_rx && flow_tx) ? "RX/TX" :
6027                (flow_rx ? "RX" :
6028                (flow_tx ? "TX" : "None"))));
6029
6030         netif_carrier_on(netdev);
6031         ixgbe_check_vf_rate_limit(adapter);
6032 }
6033
6034 /**
6035  * ixgbe_watchdog_link_is_down - update netif_carrier status and
6036  *                               print link down message
6037  * @adapter - pointer to the adapter structure
6038  **/
6039 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6040 {
6041         struct net_device *netdev = adapter->netdev;
6042         struct ixgbe_hw *hw = &adapter->hw;
6043
6044         adapter->link_up = false;
6045         adapter->link_speed = 0;
6046
6047         /* only continue if link was up previously */
6048         if (!netif_carrier_ok(netdev))
6049                 return;
6050
6051         /* poll for SFP+ cable when link is down */
6052         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6053                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6054
6055         e_info(drv, "NIC Link is Down\n");
6056         netif_carrier_off(netdev);
6057 }
6058
6059 /**
6060  * ixgbe_watchdog_flush_tx - flush queues on link down
6061  * @adapter - pointer to the device adapter structure
6062  **/
6063 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6064 {
6065         int i;
6066         int some_tx_pending = 0;
6067
6068         if (!netif_carrier_ok(adapter->netdev)) {
6069                 for (i = 0; i < adapter->num_tx_queues; i++) {
6070                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6071                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6072                                 some_tx_pending = 1;
6073                                 break;
6074                         }
6075                 }
6076
6077                 if (some_tx_pending) {
6078                         /* We've lost link, so the controller stops DMA,
6079                          * but we've got queued Tx work that's never going
6080                          * to get done, so reset controller to flush Tx.
6081                          * (Do the reset outside of interrupt context).
6082                          */
6083                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6084                 }
6085         }
6086 }
6087
6088 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6089 {
6090         u32 ssvpc;
6091
6092         /* Do not perform spoof check for 82598 */
6093         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6094                 return;
6095
6096         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6097
6098         /*
6099          * ssvpc register is cleared on read, if zero then no
6100          * spoofed packets in the last interval.
6101          */
6102         if (!ssvpc)
6103                 return;
6104
6105         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6106 }
6107
6108 /**
6109  * ixgbe_watchdog_subtask - check and bring link up
6110  * @adapter - pointer to the device adapter structure
6111  **/
6112 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6113 {
6114         /* if interface is down do nothing */
6115         if (test_bit(__IXGBE_DOWN, &adapter->state))
6116                 return;
6117
6118         ixgbe_watchdog_update_link(adapter);
6119
6120         if (adapter->link_up)
6121                 ixgbe_watchdog_link_is_up(adapter);
6122         else
6123                 ixgbe_watchdog_link_is_down(adapter);
6124
6125         ixgbe_spoof_check(adapter);
6126         ixgbe_update_stats(adapter);
6127
6128         ixgbe_watchdog_flush_tx(adapter);
6129 }
6130
6131 /**
6132  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6133  * @adapter - the ixgbe adapter structure
6134  **/
6135 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6136 {
6137         struct ixgbe_hw *hw = &adapter->hw;
6138         s32 err;
6139
6140         /* not searching for SFP so there is nothing to do here */
6141         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6142             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6143                 return;
6144
6145         /* someone else is in init, wait until next service event */
6146         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6147                 return;
6148
6149         err = hw->phy.ops.identify_sfp(hw);
6150         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6151                 goto sfp_out;
6152
6153         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6154                 /* If no cable is present, then we need to reset
6155                  * the next time we find a good cable. */
6156                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6157         }
6158
6159         /* exit on error */
6160         if (err)
6161                 goto sfp_out;
6162
6163         /* exit if reset not needed */
6164         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6165                 goto sfp_out;
6166
6167         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6168
6169         /*
6170          * A module may be identified correctly, but the EEPROM may not have
6171          * support for that module.  setup_sfp() will fail in that case, so
6172          * we should not allow that module to load.
6173          */
6174         if (hw->mac.type == ixgbe_mac_82598EB)
6175                 err = hw->phy.ops.reset(hw);
6176         else
6177                 err = hw->mac.ops.setup_sfp(hw);
6178
6179         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6180                 goto sfp_out;
6181
6182         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6183         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6184
6185 sfp_out:
6186         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6187
6188         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6189             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6190                 e_dev_err("failed to initialize because an unsupported "
6191                           "SFP+ module type was detected.\n");
6192                 e_dev_err("Reload the driver after installing a "
6193                           "supported module.\n");
6194                 unregister_netdev(adapter->netdev);
6195         }
6196 }
6197
6198 /**
6199  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6200  * @adapter - the ixgbe adapter structure
6201  **/
6202 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6203 {
6204         struct ixgbe_hw *hw = &adapter->hw;
6205         u32 autoneg;
6206         bool negotiation;
6207
6208         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6209                 return;
6210
6211         /* someone else is in init, wait until next service event */
6212         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6213                 return;
6214
6215         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6216
6217         autoneg = hw->phy.autoneg_advertised;
6218         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6219                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6220         hw->mac.autotry_restart = false;
6221         if (hw->mac.ops.setup_link)
6222                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6223
6224         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6225         adapter->link_check_timeout = jiffies;
6226         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6227 }
6228
6229 /**
6230  * ixgbe_service_timer - Timer Call-back
6231  * @data: pointer to adapter cast into an unsigned long
6232  **/
6233 static void ixgbe_service_timer(unsigned long data)
6234 {
6235         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6236         unsigned long next_event_offset;
6237
6238         /* poll faster when waiting for link */
6239         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6240                 next_event_offset = HZ / 10;
6241         else
6242                 next_event_offset = HZ * 2;
6243
6244         /* Reset the timer */
6245         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6246
6247         ixgbe_service_event_schedule(adapter);
6248 }
6249
6250 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6251 {
6252         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6253                 return;
6254
6255         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6256
6257         /* If we're already down or resetting, just bail */
6258         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6259             test_bit(__IXGBE_RESETTING, &adapter->state))
6260                 return;
6261
6262         ixgbe_dump(adapter);
6263         netdev_err(adapter->netdev, "Reset adapter\n");
6264         adapter->tx_timeout_count++;
6265
6266         ixgbe_reinit_locked(adapter);
6267 }
6268
6269 /**
6270  * ixgbe_service_task - manages and runs subtasks
6271  * @work: pointer to work_struct containing our data
6272  **/
6273 static void ixgbe_service_task(struct work_struct *work)
6274 {
6275         struct ixgbe_adapter *adapter = container_of(work,
6276                                                      struct ixgbe_adapter,
6277                                                      service_task);
6278
6279         ixgbe_reset_subtask(adapter);
6280         ixgbe_sfp_detection_subtask(adapter);
6281         ixgbe_sfp_link_config_subtask(adapter);
6282         ixgbe_check_overtemp_subtask(adapter);
6283         ixgbe_watchdog_subtask(adapter);
6284         ixgbe_fdir_reinit_subtask(adapter);
6285         ixgbe_check_hang_subtask(adapter);
6286
6287         ixgbe_service_event_complete(adapter);
6288 }
6289
6290 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6291                        u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6292 {
6293         struct ixgbe_adv_tx_context_desc *context_desc;
6294         u16 i = tx_ring->next_to_use;
6295
6296         context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6297
6298         i++;
6299         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6300
6301         /* set bits to identify this as an advanced context descriptor */
6302         type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6303
6304         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
6305         context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
6306         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
6307         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
6308 }
6309
6310 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6311                      u32 tx_flags, __be16 protocol, u8 *hdr_len)
6312 {
6313         int err;
6314         u32 vlan_macip_lens, type_tucmd;
6315         u32 mss_l4len_idx, l4len;
6316
6317         if (!skb_is_gso(skb))
6318                 return 0;
6319
6320         if (skb_header_cloned(skb)) {
6321                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6322                 if (err)
6323                         return err;
6324         }
6325
6326         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6327         type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6328
6329         if (protocol == __constant_htons(ETH_P_IP)) {
6330                 struct iphdr *iph = ip_hdr(skb);
6331                 iph->tot_len = 0;
6332                 iph->check = 0;
6333                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6334                                                          iph->daddr, 0,
6335                                                          IPPROTO_TCP,
6336                                                          0);
6337                 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6338         } else if (skb_is_gso_v6(skb)) {
6339                 ipv6_hdr(skb)->payload_len = 0;
6340                 tcp_hdr(skb)->check =
6341                     ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6342                                      &ipv6_hdr(skb)->daddr,
6343                                      0, IPPROTO_TCP, 0);
6344         }
6345
6346         l4len = tcp_hdrlen(skb);
6347         *hdr_len = skb_transport_offset(skb) + l4len;
6348
6349         /* mss_l4len_id: use 1 as index for TSO */
6350         mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6351         mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6352         mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6353
6354         /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6355         vlan_macip_lens = skb_network_header_len(skb);
6356         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6357         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6358
6359         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6360                           mss_l4len_idx);
6361
6362         return 1;
6363 }
6364
6365 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6366                           struct sk_buff *skb, u32 tx_flags,
6367                           __be16 protocol)
6368 {
6369         u32 vlan_macip_lens = 0;
6370         u32 mss_l4len_idx = 0;
6371         u32 type_tucmd = 0;
6372
6373         if (skb->ip_summed != CHECKSUM_PARTIAL) {
6374             if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN))
6375                         return false;
6376         } else {
6377                 u8 l4_hdr = 0;
6378                 switch (protocol) {
6379                 case __constant_htons(ETH_P_IP):
6380                         vlan_macip_lens |= skb_network_header_len(skb);
6381                         type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6382                         l4_hdr = ip_hdr(skb)->protocol;
6383                         break;
6384                 case __constant_htons(ETH_P_IPV6):
6385                         vlan_macip_lens |= skb_network_header_len(skb);
6386                         l4_hdr = ipv6_hdr(skb)->nexthdr;
6387                         break;
6388                 default:
6389                         if (unlikely(net_ratelimit())) {
6390                                 dev_warn(tx_ring->dev,
6391                                  "partial checksum but proto=%x!\n",
6392                                  skb->protocol);
6393                         }
6394                         break;
6395                 }
6396
6397                 switch (l4_hdr) {
6398                 case IPPROTO_TCP:
6399                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6400                         mss_l4len_idx = tcp_hdrlen(skb) <<
6401                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6402                         break;
6403                 case IPPROTO_SCTP:
6404                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6405                         mss_l4len_idx = sizeof(struct sctphdr) <<
6406                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6407                         break;
6408                 case IPPROTO_UDP:
6409                         mss_l4len_idx = sizeof(struct udphdr) <<
6410                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6411                         break;
6412                 default:
6413                         if (unlikely(net_ratelimit())) {
6414                                 dev_warn(tx_ring->dev,
6415                                  "partial checksum but l4 proto=%x!\n",
6416                                  skb->protocol);
6417                         }
6418                         break;
6419                 }
6420         }
6421
6422         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6423         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6424
6425         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6426                           type_tucmd, mss_l4len_idx);
6427
6428         return (skb->ip_summed == CHECKSUM_PARTIAL);
6429 }
6430
6431 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6432 {
6433         /* set type for advanced descriptor with frame checksum insertion */
6434         __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6435                                       IXGBE_ADVTXD_DCMD_IFCS |
6436                                       IXGBE_ADVTXD_DCMD_DEXT);
6437
6438         /* set HW vlan bit if vlan is present */
6439         if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6440                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6441
6442         /* set segmentation enable bits for TSO/FSO */
6443 #ifdef IXGBE_FCOE
6444         if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6445 #else
6446         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6447 #endif
6448                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6449
6450         return cmd_type;
6451 }
6452
6453 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6454 {
6455         __le32 olinfo_status =
6456                 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6457
6458         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6459                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6460                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6461                 /* enble IPv4 checksum for TSO */
6462                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6463                         olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6464         }
6465
6466         /* enable L4 checksum for TSO and TX checksum offload */
6467         if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6468                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6469
6470 #ifdef IXGBE_FCOE
6471         /* use index 1 context for FCOE/FSO */
6472         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6473                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6474                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6475
6476 #endif
6477         return olinfo_status;
6478 }
6479
6480 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6481                        IXGBE_TXD_CMD_RS)
6482
6483 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6484                          struct sk_buff *skb,
6485                          struct ixgbe_tx_buffer *first,
6486                          u32 tx_flags,
6487                          const u8 hdr_len)
6488 {
6489         struct device *dev = tx_ring->dev;
6490         struct ixgbe_tx_buffer *tx_buffer_info;
6491         union ixgbe_adv_tx_desc *tx_desc;
6492         dma_addr_t dma;
6493         __le32 cmd_type, olinfo_status;
6494         struct skb_frag_struct *frag;
6495         unsigned int f = 0;
6496         unsigned int data_len = skb->data_len;
6497         unsigned int size = skb_headlen(skb);
6498         u32 offset = 0;
6499         u32 paylen = skb->len - hdr_len;
6500         u16 i = tx_ring->next_to_use;
6501         u16 gso_segs;
6502
6503 #ifdef IXGBE_FCOE
6504         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6505                 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6506                         data_len -= sizeof(struct fcoe_crc_eof);
6507                 } else {
6508                         size -= sizeof(struct fcoe_crc_eof) - data_len;
6509                         data_len = 0;
6510                 }
6511         }
6512
6513 #endif
6514         dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6515         if (dma_mapping_error(dev, dma))
6516                 goto dma_error;
6517
6518         cmd_type = ixgbe_tx_cmd_type(tx_flags);
6519         olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6520
6521         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6522
6523         for (;;) {
6524                 while (size > IXGBE_MAX_DATA_PER_TXD) {
6525                         tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6526                         tx_desc->read.cmd_type_len =
6527                                 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6528                         tx_desc->read.olinfo_status = olinfo_status;
6529
6530                         offset += IXGBE_MAX_DATA_PER_TXD;
6531                         size -= IXGBE_MAX_DATA_PER_TXD;
6532
6533                         tx_desc++;
6534                         i++;
6535                         if (i == tx_ring->count) {
6536                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6537                                 i = 0;
6538                         }
6539                 }
6540
6541                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6542                 tx_buffer_info->length = offset + size;
6543                 tx_buffer_info->tx_flags = tx_flags;
6544                 tx_buffer_info->dma = dma;
6545
6546                 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6547                 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6548                 tx_desc->read.olinfo_status = olinfo_status;
6549
6550                 if (!data_len)
6551                         break;
6552
6553                 frag = &skb_shinfo(skb)->frags[f];
6554 #ifdef IXGBE_FCOE
6555                 size = min_t(unsigned int, data_len, frag->size);
6556 #else
6557                 size = frag->size;
6558 #endif
6559                 data_len -= size;
6560                 f++;
6561
6562                 offset = 0;
6563                 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6564
6565                 dma = dma_map_page(dev, frag->page, frag->page_offset,
6566                                    size, DMA_TO_DEVICE);
6567                 if (dma_mapping_error(dev, dma))
6568                         goto dma_error;
6569
6570                 tx_desc++;
6571                 i++;
6572                 if (i == tx_ring->count) {
6573                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6574                         i = 0;
6575                 }
6576         }
6577
6578         tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6579
6580         i++;
6581         if (i == tx_ring->count)
6582                 i = 0;
6583
6584         tx_ring->next_to_use = i;
6585
6586         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6587                 gso_segs = skb_shinfo(skb)->gso_segs;
6588 #ifdef IXGBE_FCOE
6589         /* adjust for FCoE Sequence Offload */
6590         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6591                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6592                                         skb_shinfo(skb)->gso_size);
6593 #endif /* IXGBE_FCOE */
6594         else
6595                 gso_segs = 1;
6596
6597         /* multiply data chunks by size of headers */
6598         tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6599         tx_buffer_info->gso_segs = gso_segs;
6600         tx_buffer_info->skb = skb;
6601
6602         /* set the timestamp */
6603         first->time_stamp = jiffies;
6604
6605         /*
6606          * Force memory writes to complete before letting h/w
6607          * know there are new descriptors to fetch.  (Only
6608          * applicable for weak-ordered memory model archs,
6609          * such as IA-64).
6610          */
6611         wmb();
6612
6613         /* set next_to_watch value indicating a packet is present */
6614         first->next_to_watch = tx_desc;
6615
6616         /* notify HW of packet */
6617         writel(i, tx_ring->tail);
6618
6619         return;
6620 dma_error:
6621         dev_err(dev, "TX DMA map failed\n");
6622
6623         /* clear dma mappings for failed tx_buffer_info map */
6624         for (;;) {
6625                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6626                 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6627                 if (tx_buffer_info == first)
6628                         break;
6629                 if (i == 0)
6630                         i = tx_ring->count;
6631                 i--;
6632         }
6633
6634         dev_kfree_skb_any(skb);
6635
6636         tx_ring->next_to_use = i;
6637 }
6638
6639 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6640                       u32 tx_flags, __be16 protocol)
6641 {
6642         struct ixgbe_q_vector *q_vector = ring->q_vector;
6643         union ixgbe_atr_hash_dword input = { .dword = 0 };
6644         union ixgbe_atr_hash_dword common = { .dword = 0 };
6645         union {
6646                 unsigned char *network;
6647                 struct iphdr *ipv4;
6648                 struct ipv6hdr *ipv6;
6649         } hdr;
6650         struct tcphdr *th;
6651         __be16 vlan_id;
6652
6653         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6654         if (!q_vector)
6655                 return;
6656
6657         /* do nothing if sampling is disabled */
6658         if (!ring->atr_sample_rate)
6659                 return;
6660
6661         ring->atr_count++;
6662
6663         /* snag network header to get L4 type and address */
6664         hdr.network = skb_network_header(skb);
6665
6666         /* Currently only IPv4/IPv6 with TCP is supported */
6667         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6668              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6669             (protocol != __constant_htons(ETH_P_IP) ||
6670              hdr.ipv4->protocol != IPPROTO_TCP))
6671                 return;
6672
6673         th = tcp_hdr(skb);
6674
6675         /* skip this packet since it is invalid or the socket is closing */
6676         if (!th || th->fin)
6677                 return;
6678
6679         /* sample on all syn packets or once every atr sample count */
6680         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6681                 return;
6682
6683         /* reset sample count */
6684         ring->atr_count = 0;
6685
6686         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6687
6688         /*
6689          * src and dst are inverted, think how the receiver sees them
6690          *
6691          * The input is broken into two sections, a non-compressed section
6692          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6693          * is XORed together and stored in the compressed dword.
6694          */
6695         input.formatted.vlan_id = vlan_id;
6696
6697         /*
6698          * since src port and flex bytes occupy the same word XOR them together
6699          * and write the value to source port portion of compressed dword
6700          */
6701         if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6702                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6703         else
6704                 common.port.src ^= th->dest ^ protocol;
6705         common.port.dst ^= th->source;
6706
6707         if (protocol == __constant_htons(ETH_P_IP)) {
6708                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6709                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6710         } else {
6711                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6712                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6713                              hdr.ipv6->saddr.s6_addr32[1] ^
6714                              hdr.ipv6->saddr.s6_addr32[2] ^
6715                              hdr.ipv6->saddr.s6_addr32[3] ^
6716                              hdr.ipv6->daddr.s6_addr32[0] ^
6717                              hdr.ipv6->daddr.s6_addr32[1] ^
6718                              hdr.ipv6->daddr.s6_addr32[2] ^
6719                              hdr.ipv6->daddr.s6_addr32[3];
6720         }
6721
6722         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6723         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6724                                               input, common, ring->queue_index);
6725 }
6726
6727 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6728 {
6729         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6730         /* Herbert's original patch had:
6731          *  smp_mb__after_netif_stop_queue();
6732          * but since that doesn't exist yet, just open code it. */
6733         smp_mb();
6734
6735         /* We need to check again in a case another CPU has just
6736          * made room available. */
6737         if (likely(ixgbe_desc_unused(tx_ring) < size))
6738                 return -EBUSY;
6739
6740         /* A reprieve! - use start_queue because it doesn't call schedule */
6741         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6742         ++tx_ring->tx_stats.restart_queue;
6743         return 0;
6744 }
6745
6746 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6747 {
6748         if (likely(ixgbe_desc_unused(tx_ring) >= size))
6749                 return 0;
6750         return __ixgbe_maybe_stop_tx(tx_ring, size);
6751 }
6752
6753 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6754 {
6755         struct ixgbe_adapter *adapter = netdev_priv(dev);
6756         int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6757                                                smp_processor_id();
6758 #ifdef IXGBE_FCOE
6759         __be16 protocol = vlan_get_protocol(skb);
6760
6761         if (((protocol == htons(ETH_P_FCOE)) ||
6762             (protocol == htons(ETH_P_FIP))) &&
6763             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6764                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6765                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6766                 return txq;
6767         }
6768 #endif
6769
6770         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6771                 while (unlikely(txq >= dev->real_num_tx_queues))
6772                         txq -= dev->real_num_tx_queues;
6773                 return txq;
6774         }
6775
6776         return skb_tx_hash(dev, skb);
6777 }
6778
6779 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6780                           struct ixgbe_adapter *adapter,
6781                           struct ixgbe_ring *tx_ring)
6782 {
6783         struct ixgbe_tx_buffer *first;
6784         int tso;
6785         u32 tx_flags = 0;
6786 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6787         unsigned short f;
6788 #endif
6789         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6790         __be16 protocol = skb->protocol;
6791         u8 hdr_len = 0;
6792
6793         /*
6794          * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6795          *       + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6796          *       + 2 desc gap to keep tail from touching head,
6797          *       + 1 desc for context descriptor,
6798          * otherwise try next time
6799          */
6800 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6801         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6802                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6803 #else
6804         count += skb_shinfo(skb)->nr_frags;
6805 #endif
6806         if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6807                 tx_ring->tx_stats.tx_busy++;
6808                 return NETDEV_TX_BUSY;
6809         }
6810
6811         /* if we have a HW VLAN tag being added default to the HW one */
6812         if (vlan_tx_tag_present(skb)) {
6813                 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6814                 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6815         /* else if it is a SW VLAN check the next protocol and store the tag */
6816         } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6817                 struct vlan_hdr *vhdr, _vhdr;
6818                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6819                 if (!vhdr)
6820                         goto out_drop;
6821
6822                 protocol = vhdr->h_vlan_encapsulated_proto;
6823                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6824                 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6825         }
6826
6827         if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6828             skb->priority != TC_PRIO_CONTROL) {
6829                 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6830                 tx_flags |= tx_ring->dcb_tc <<
6831                             IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6832                 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6833                         struct vlan_ethhdr *vhdr;
6834                         if (skb_header_cloned(skb) &&
6835                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6836                                 goto out_drop;
6837                         vhdr = (struct vlan_ethhdr *)skb->data;
6838                         vhdr->h_vlan_TCI = htons(tx_flags >>
6839                                                  IXGBE_TX_FLAGS_VLAN_SHIFT);
6840                 } else {
6841                         tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6842                 }
6843         }
6844
6845         /* record the location of the first descriptor for this packet */
6846         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6847
6848 #ifdef IXGBE_FCOE
6849         /* setup tx offload for FCoE */
6850         if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6851             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6852                 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6853                 if (tso < 0)
6854                         goto out_drop;
6855                 else if (tso)
6856                         tx_flags |= IXGBE_TX_FLAGS_FSO |
6857                                     IXGBE_TX_FLAGS_FCOE;
6858                 else
6859                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6860
6861                 goto xmit_fcoe;
6862         }
6863
6864 #endif /* IXGBE_FCOE */
6865         /* setup IPv4/IPv6 offloads */
6866         if (protocol == __constant_htons(ETH_P_IP))
6867                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6868
6869         tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6870         if (tso < 0)
6871                 goto out_drop;
6872         else if (tso)
6873                 tx_flags |= IXGBE_TX_FLAGS_TSO;
6874         else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6875                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6876
6877         /* add the ATR filter if ATR is on */
6878         if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6879                 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6880
6881 #ifdef IXGBE_FCOE
6882 xmit_fcoe:
6883 #endif /* IXGBE_FCOE */
6884         ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6885
6886         ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6887
6888         return NETDEV_TX_OK;
6889
6890 out_drop:
6891         dev_kfree_skb_any(skb);
6892         return NETDEV_TX_OK;
6893 }
6894
6895 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6896 {
6897         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6898         struct ixgbe_ring *tx_ring;
6899
6900         tx_ring = adapter->tx_ring[skb->queue_mapping];
6901         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6902 }
6903
6904 /**
6905  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6906  * @netdev: network interface device structure
6907  * @p: pointer to an address structure
6908  *
6909  * Returns 0 on success, negative on failure
6910  **/
6911 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6912 {
6913         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6914         struct ixgbe_hw *hw = &adapter->hw;
6915         struct sockaddr *addr = p;
6916
6917         if (!is_valid_ether_addr(addr->sa_data))
6918                 return -EADDRNOTAVAIL;
6919
6920         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6921         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6922
6923         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6924                             IXGBE_RAH_AV);
6925
6926         return 0;
6927 }
6928
6929 static int
6930 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6931 {
6932         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6933         struct ixgbe_hw *hw = &adapter->hw;
6934         u16 value;
6935         int rc;
6936
6937         if (prtad != hw->phy.mdio.prtad)
6938                 return -EINVAL;
6939         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6940         if (!rc)
6941                 rc = value;
6942         return rc;
6943 }
6944
6945 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6946                             u16 addr, u16 value)
6947 {
6948         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6949         struct ixgbe_hw *hw = &adapter->hw;
6950
6951         if (prtad != hw->phy.mdio.prtad)
6952                 return -EINVAL;
6953         return hw->phy.ops.write_reg(hw, addr, devad, value);
6954 }
6955
6956 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6957 {
6958         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6959
6960         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6961 }
6962
6963 /**
6964  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6965  * netdev->dev_addrs
6966  * @netdev: network interface device structure
6967  *
6968  * Returns non-zero on failure
6969  **/
6970 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6971 {
6972         int err = 0;
6973         struct ixgbe_adapter *adapter = netdev_priv(dev);
6974         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6975
6976         if (is_valid_ether_addr(mac->san_addr)) {
6977                 rtnl_lock();
6978                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6979                 rtnl_unlock();
6980         }
6981         return err;
6982 }
6983
6984 /**
6985  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6986  * netdev->dev_addrs
6987  * @netdev: network interface device structure
6988  *
6989  * Returns non-zero on failure
6990  **/
6991 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6992 {
6993         int err = 0;
6994         struct ixgbe_adapter *adapter = netdev_priv(dev);
6995         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6996
6997         if (is_valid_ether_addr(mac->san_addr)) {
6998                 rtnl_lock();
6999                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7000                 rtnl_unlock();
7001         }
7002         return err;
7003 }
7004
7005 #ifdef CONFIG_NET_POLL_CONTROLLER
7006 /*
7007  * Polling 'interrupt' - used by things like netconsole to send skbs
7008  * without having to re-enable interrupts. It's not called while
7009  * the interrupt routine is executing.
7010  */
7011 static void ixgbe_netpoll(struct net_device *netdev)
7012 {
7013         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7014         int i;
7015
7016         /* if interface is down do nothing */
7017         if (test_bit(__IXGBE_DOWN, &adapter->state))
7018                 return;
7019
7020         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7021         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7022                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7023                 for (i = 0; i < num_q_vectors; i++) {
7024                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7025                         ixgbe_msix_clean_many(0, q_vector);
7026                 }
7027         } else {
7028                 ixgbe_intr(adapter->pdev->irq, netdev);
7029         }
7030         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7031 }
7032 #endif
7033
7034 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7035                                                    struct rtnl_link_stats64 *stats)
7036 {
7037         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7038         int i;
7039
7040         rcu_read_lock();
7041         for (i = 0; i < adapter->num_rx_queues; i++) {
7042                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7043                 u64 bytes, packets;
7044                 unsigned int start;
7045
7046                 if (ring) {
7047                         do {
7048                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7049                                 packets = ring->stats.packets;
7050                                 bytes   = ring->stats.bytes;
7051                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7052                         stats->rx_packets += packets;
7053                         stats->rx_bytes   += bytes;
7054                 }
7055         }
7056
7057         for (i = 0; i < adapter->num_tx_queues; i++) {
7058                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7059                 u64 bytes, packets;
7060                 unsigned int start;
7061
7062                 if (ring) {
7063                         do {
7064                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7065                                 packets = ring->stats.packets;
7066                                 bytes   = ring->stats.bytes;
7067                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7068                         stats->tx_packets += packets;
7069                         stats->tx_bytes   += bytes;
7070                 }
7071         }
7072         rcu_read_unlock();
7073         /* following stats updated by ixgbe_watchdog_task() */
7074         stats->multicast        = netdev->stats.multicast;
7075         stats->rx_errors        = netdev->stats.rx_errors;
7076         stats->rx_length_errors = netdev->stats.rx_length_errors;
7077         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
7078         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7079         return stats;
7080 }
7081
7082 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7083  * #adapter: pointer to ixgbe_adapter
7084  * @tc: number of traffic classes currently enabled
7085  *
7086  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7087  * 802.1Q priority maps to a packet buffer that exists.
7088  */
7089 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7090 {
7091         struct ixgbe_hw *hw = &adapter->hw;
7092         u32 reg, rsave;
7093         int i;
7094
7095         /* 82598 have a static priority to TC mapping that can not
7096          * be changed so no validation is needed.
7097          */
7098         if (hw->mac.type == ixgbe_mac_82598EB)
7099                 return;
7100
7101         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7102         rsave = reg;
7103
7104         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7105                 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7106
7107                 /* If up2tc is out of bounds default to zero */
7108                 if (up2tc > tc)
7109                         reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7110         }
7111
7112         if (reg != rsave)
7113                 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7114
7115         return;
7116 }
7117
7118
7119 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7120  * classes.
7121  *
7122  * @netdev: net device to configure
7123  * @tc: number of traffic classes to enable
7124  */
7125 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7126 {
7127         struct ixgbe_adapter *adapter = netdev_priv(dev);
7128         struct ixgbe_hw *hw = &adapter->hw;
7129
7130         /* If DCB is anabled do not remove traffic classes, multiple
7131          * traffic classes are required to implement DCB
7132          */
7133         if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7134                 return 0;
7135
7136         /* Hardware supports up to 8 traffic classes */
7137         if (tc > MAX_TRAFFIC_CLASS ||
7138             (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7139                 return -EINVAL;
7140
7141         /* Hardware has to reinitialize queues and interrupts to
7142          * match packet buffer alignment. Unfortunantly, the
7143          * hardware is not flexible enough to do this dynamically.
7144          */
7145         if (netif_running(dev))
7146                 ixgbe_close(dev);
7147         ixgbe_clear_interrupt_scheme(adapter);
7148
7149         if (tc)
7150                 netdev_set_num_tc(dev, tc);
7151         else
7152                 netdev_reset_tc(dev);
7153
7154         ixgbe_init_interrupt_scheme(adapter);
7155         ixgbe_validate_rtr(adapter, tc);
7156         if (netif_running(dev))
7157                 ixgbe_open(dev);
7158
7159         return 0;
7160 }
7161
7162 void ixgbe_do_reset(struct net_device *netdev)
7163 {
7164         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7165
7166         if (netif_running(netdev))
7167                 ixgbe_reinit_locked(adapter);
7168         else
7169                 ixgbe_reset(adapter);
7170 }
7171
7172 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7173 {
7174         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7175
7176 #ifdef CONFIG_DCB
7177         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7178                 data &= ~NETIF_F_HW_VLAN_RX;
7179 #endif
7180
7181         /* return error if RXHASH is being enabled when RSS is not supported */
7182         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7183                 data &= ~NETIF_F_RXHASH;
7184
7185         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7186         if (!(data & NETIF_F_RXCSUM))
7187                 data &= ~NETIF_F_LRO;
7188
7189         /* Turn off LRO if not RSC capable or invalid ITR settings */
7190         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7191                 data &= ~NETIF_F_LRO;
7192         } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7193                    (adapter->rx_itr_setting != 1 &&
7194                     adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7195                 data &= ~NETIF_F_LRO;
7196                 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7197         }
7198
7199         return data;
7200 }
7201
7202 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7203 {
7204         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7205         bool need_reset = false;
7206
7207         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7208         if (!(data & NETIF_F_RXCSUM))
7209                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7210         else
7211                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7212
7213         /* Make sure RSC matches LRO, reset if change */
7214         if (!!(data & NETIF_F_LRO) !=
7215              !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7216                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7217                 switch (adapter->hw.mac.type) {
7218                 case ixgbe_mac_X540:
7219                 case ixgbe_mac_82599EB:
7220                         need_reset = true;
7221                         break;
7222                 default:
7223                         break;
7224                 }
7225         }
7226
7227         /*
7228          * Check if Flow Director n-tuple support was enabled or disabled.  If
7229          * the state changed, we need to reset.
7230          */
7231         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7232                 /* turn off ATR, enable perfect filters and reset */
7233                 if (data & NETIF_F_NTUPLE) {
7234                         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7235                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7236                         need_reset = true;
7237                 }
7238         } else if (!(data & NETIF_F_NTUPLE)) {
7239                 /* turn off Flow Director, set ATR and reset */
7240                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7241                 if ((adapter->flags &  IXGBE_FLAG_RSS_ENABLED) &&
7242                     !(adapter->flags &  IXGBE_FLAG_DCB_ENABLED))
7243                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7244                 need_reset = true;
7245         }
7246
7247         if (need_reset)
7248                 ixgbe_do_reset(netdev);
7249
7250         return 0;
7251
7252 }
7253
7254 static const struct net_device_ops ixgbe_netdev_ops = {
7255         .ndo_open               = ixgbe_open,
7256         .ndo_stop               = ixgbe_close,
7257         .ndo_start_xmit         = ixgbe_xmit_frame,
7258         .ndo_select_queue       = ixgbe_select_queue,
7259         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7260         .ndo_validate_addr      = eth_validate_addr,
7261         .ndo_set_mac_address    = ixgbe_set_mac,
7262         .ndo_change_mtu         = ixgbe_change_mtu,
7263         .ndo_tx_timeout         = ixgbe_tx_timeout,
7264         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7265         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7266         .ndo_do_ioctl           = ixgbe_ioctl,
7267         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7268         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7269         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7270         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7271         .ndo_get_stats64        = ixgbe_get_stats64,
7272         .ndo_setup_tc           = ixgbe_setup_tc,
7273 #ifdef CONFIG_NET_POLL_CONTROLLER
7274         .ndo_poll_controller    = ixgbe_netpoll,
7275 #endif
7276 #ifdef IXGBE_FCOE
7277         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7278         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7279         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7280         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7281         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7282         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7283 #endif /* IXGBE_FCOE */
7284         .ndo_set_features = ixgbe_set_features,
7285         .ndo_fix_features = ixgbe_fix_features,
7286 };
7287
7288 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7289                            const struct ixgbe_info *ii)
7290 {
7291 #ifdef CONFIG_PCI_IOV
7292         struct ixgbe_hw *hw = &adapter->hw;
7293         int err;
7294         int num_vf_macvlans, i;
7295         struct vf_macvlans *mv_list;
7296
7297         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7298                 return;
7299
7300         /* The 82599 supports up to 64 VFs per physical function
7301          * but this implementation limits allocation to 63 so that
7302          * basic networking resources are still available to the
7303          * physical function
7304          */
7305         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7306         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7307         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7308         if (err) {
7309                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7310                 goto err_novfs;
7311         }
7312
7313         num_vf_macvlans = hw->mac.num_rar_entries -
7314                 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7315
7316         adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7317                                              sizeof(struct vf_macvlans),
7318                                              GFP_KERNEL);
7319         if (mv_list) {
7320                 /* Initialize list of VF macvlans */
7321                 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7322                 for (i = 0; i < num_vf_macvlans; i++) {
7323                         mv_list->vf = -1;
7324                         mv_list->free = true;
7325                         mv_list->rar_entry = hw->mac.num_rar_entries -
7326                                 (i + adapter->num_vfs + 1);
7327                         list_add(&mv_list->l, &adapter->vf_mvs.l);
7328                         mv_list++;
7329                 }
7330         }
7331
7332         /* If call to enable VFs succeeded then allocate memory
7333          * for per VF control structures.
7334          */
7335         adapter->vfinfo =
7336                 kcalloc(adapter->num_vfs,
7337                         sizeof(struct vf_data_storage), GFP_KERNEL);
7338         if (adapter->vfinfo) {
7339                 /* Now that we're sure SR-IOV is enabled
7340                  * and memory allocated set up the mailbox parameters
7341                  */
7342                 ixgbe_init_mbx_params_pf(hw);
7343                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7344                        sizeof(hw->mbx.ops));
7345
7346                 /* Disable RSC when in SR-IOV mode */
7347                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7348                                      IXGBE_FLAG2_RSC_ENABLED);
7349                 return;
7350         }
7351
7352         /* Oh oh */
7353         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7354               "SRIOV disabled\n");
7355         pci_disable_sriov(adapter->pdev);
7356
7357 err_novfs:
7358         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7359         adapter->num_vfs = 0;
7360 #endif /* CONFIG_PCI_IOV */
7361 }
7362
7363 /**
7364  * ixgbe_probe - Device Initialization Routine
7365  * @pdev: PCI device information struct
7366  * @ent: entry in ixgbe_pci_tbl
7367  *
7368  * Returns 0 on success, negative on failure
7369  *
7370  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7371  * The OS initialization, configuring of the adapter private structure,
7372  * and a hardware reset occur.
7373  **/
7374 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7375                                  const struct pci_device_id *ent)
7376 {
7377         struct net_device *netdev;
7378         struct ixgbe_adapter *adapter = NULL;
7379         struct ixgbe_hw *hw;
7380         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7381         static int cards_found;
7382         int i, err, pci_using_dac;
7383         u8 part_str[IXGBE_PBANUM_LENGTH];
7384         unsigned int indices = num_possible_cpus();
7385 #ifdef IXGBE_FCOE
7386         u16 device_caps;
7387 #endif
7388         u32 eec;
7389
7390         /* Catch broken hardware that put the wrong VF device ID in
7391          * the PCIe SR-IOV capability.
7392          */
7393         if (pdev->is_virtfn) {
7394                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7395                      pci_name(pdev), pdev->vendor, pdev->device);
7396                 return -EINVAL;
7397         }
7398
7399         err = pci_enable_device_mem(pdev);
7400         if (err)
7401                 return err;
7402
7403         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7404             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7405                 pci_using_dac = 1;
7406         } else {
7407                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7408                 if (err) {
7409                         err = dma_set_coherent_mask(&pdev->dev,
7410                                                     DMA_BIT_MASK(32));
7411                         if (err) {
7412                                 dev_err(&pdev->dev,
7413                                         "No usable DMA configuration, aborting\n");
7414                                 goto err_dma;
7415                         }
7416                 }
7417                 pci_using_dac = 0;
7418         }
7419
7420         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7421                                            IORESOURCE_MEM), ixgbe_driver_name);
7422         if (err) {
7423                 dev_err(&pdev->dev,
7424                         "pci_request_selected_regions failed 0x%x\n", err);
7425                 goto err_pci_reg;
7426         }
7427
7428         pci_enable_pcie_error_reporting(pdev);
7429
7430         pci_set_master(pdev);
7431         pci_save_state(pdev);
7432
7433 #ifdef CONFIG_IXGBE_DCB
7434         indices *= MAX_TRAFFIC_CLASS;
7435 #endif
7436
7437         if (ii->mac == ixgbe_mac_82598EB)
7438                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7439         else
7440                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7441
7442 #ifdef IXGBE_FCOE
7443         indices += min_t(unsigned int, num_possible_cpus(),
7444                          IXGBE_MAX_FCOE_INDICES);
7445 #endif
7446         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7447         if (!netdev) {
7448                 err = -ENOMEM;
7449                 goto err_alloc_etherdev;
7450         }
7451
7452         SET_NETDEV_DEV(netdev, &pdev->dev);
7453
7454         adapter = netdev_priv(netdev);
7455         pci_set_drvdata(pdev, adapter);
7456
7457         adapter->netdev = netdev;
7458         adapter->pdev = pdev;
7459         hw = &adapter->hw;
7460         hw->back = adapter;
7461         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7462
7463         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7464                               pci_resource_len(pdev, 0));
7465         if (!hw->hw_addr) {
7466                 err = -EIO;
7467                 goto err_ioremap;
7468         }
7469
7470         for (i = 1; i <= 5; i++) {
7471                 if (pci_resource_len(pdev, i) == 0)
7472                         continue;
7473         }
7474
7475         netdev->netdev_ops = &ixgbe_netdev_ops;
7476         ixgbe_set_ethtool_ops(netdev);
7477         netdev->watchdog_timeo = 5 * HZ;
7478         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7479
7480         adapter->bd_number = cards_found;
7481
7482         /* Setup hw api */
7483         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7484         hw->mac.type  = ii->mac;
7485
7486         /* EEPROM */
7487         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7488         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7489         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7490         if (!(eec & (1 << 8)))
7491                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7492
7493         /* PHY */
7494         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7495         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7496         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7497         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7498         hw->phy.mdio.mmds = 0;
7499         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7500         hw->phy.mdio.dev = netdev;
7501         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7502         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7503
7504         ii->get_invariants(hw);
7505
7506         /* setup the private structure */
7507         err = ixgbe_sw_init(adapter);
7508         if (err)
7509                 goto err_sw_init;
7510
7511         /* Make it possible the adapter to be woken up via WOL */
7512         switch (adapter->hw.mac.type) {
7513         case ixgbe_mac_82599EB:
7514         case ixgbe_mac_X540:
7515                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7516                 break;
7517         default:
7518                 break;
7519         }
7520
7521         /*
7522          * If there is a fan on this device and it has failed log the
7523          * failure.
7524          */
7525         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7526                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7527                 if (esdp & IXGBE_ESDP_SDP1)
7528                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7529         }
7530
7531         /* reset_hw fills in the perm_addr as well */
7532         hw->phy.reset_if_overtemp = true;
7533         err = hw->mac.ops.reset_hw(hw);
7534         hw->phy.reset_if_overtemp = false;
7535         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7536             hw->mac.type == ixgbe_mac_82598EB) {
7537                 err = 0;
7538         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7539                 e_dev_err("failed to load because an unsupported SFP+ "
7540                           "module type was detected.\n");
7541                 e_dev_err("Reload the driver after installing a supported "
7542                           "module.\n");
7543                 goto err_sw_init;
7544         } else if (err) {
7545                 e_dev_err("HW Init failed: %d\n", err);
7546                 goto err_sw_init;
7547         }
7548
7549         ixgbe_probe_vf(adapter, ii);
7550
7551         netdev->features = NETIF_F_SG |
7552                            NETIF_F_IP_CSUM |
7553                            NETIF_F_IPV6_CSUM |
7554                            NETIF_F_HW_VLAN_TX |
7555                            NETIF_F_HW_VLAN_RX |
7556                            NETIF_F_HW_VLAN_FILTER |
7557                            NETIF_F_TSO |
7558                            NETIF_F_TSO6 |
7559                            NETIF_F_GRO |
7560                            NETIF_F_RXHASH |
7561                            NETIF_F_RXCSUM;
7562
7563         netdev->hw_features = netdev->features;
7564
7565         switch (adapter->hw.mac.type) {
7566         case ixgbe_mac_82599EB:
7567         case ixgbe_mac_X540:
7568                 netdev->features |= NETIF_F_SCTP_CSUM;
7569                 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7570                                        NETIF_F_NTUPLE;
7571                 break;
7572         default:
7573                 break;
7574         }
7575
7576         netdev->vlan_features |= NETIF_F_TSO;
7577         netdev->vlan_features |= NETIF_F_TSO6;
7578         netdev->vlan_features |= NETIF_F_IP_CSUM;
7579         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7580         netdev->vlan_features |= NETIF_F_SG;
7581
7582         netdev->priv_flags |= IFF_UNICAST_FLT;
7583
7584         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7585                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7586                                     IXGBE_FLAG_DCB_ENABLED);
7587
7588 #ifdef CONFIG_IXGBE_DCB
7589         netdev->dcbnl_ops = &dcbnl_ops;
7590 #endif
7591
7592 #ifdef IXGBE_FCOE
7593         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7594                 if (hw->mac.ops.get_device_caps) {
7595                         hw->mac.ops.get_device_caps(hw, &device_caps);
7596                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7597                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7598                 }
7599         }
7600         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7601                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7602                 netdev->vlan_features |= NETIF_F_FSO;
7603                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7604         }
7605 #endif /* IXGBE_FCOE */
7606         if (pci_using_dac) {
7607                 netdev->features |= NETIF_F_HIGHDMA;
7608                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7609         }
7610
7611         if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7612                 netdev->hw_features |= NETIF_F_LRO;
7613         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7614                 netdev->features |= NETIF_F_LRO;
7615
7616         /* make sure the EEPROM is good */
7617         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7618                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7619                 err = -EIO;
7620                 goto err_eeprom;
7621         }
7622
7623         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7624         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7625
7626         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7627                 e_dev_err("invalid MAC address\n");
7628                 err = -EIO;
7629                 goto err_eeprom;
7630         }
7631
7632         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7633         if (hw->mac.ops.disable_tx_laser &&
7634             ((hw->phy.multispeed_fiber) ||
7635              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7636               (hw->mac.type == ixgbe_mac_82599EB))))
7637                 hw->mac.ops.disable_tx_laser(hw);
7638
7639         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7640                     (unsigned long) adapter);
7641
7642         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7643         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7644
7645         err = ixgbe_init_interrupt_scheme(adapter);
7646         if (err)
7647                 goto err_sw_init;
7648
7649         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7650                 netdev->hw_features &= ~NETIF_F_RXHASH;
7651                 netdev->features &= ~NETIF_F_RXHASH;
7652         }
7653
7654         switch (pdev->device) {
7655         case IXGBE_DEV_ID_82599_SFP:
7656                 /* Only this subdevice supports WOL */
7657                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7658                         adapter->wol = IXGBE_WUFC_MAG;
7659                 break;
7660         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7661                 /* All except this subdevice support WOL */
7662                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7663                         adapter->wol = IXGBE_WUFC_MAG;
7664                 break;
7665         case IXGBE_DEV_ID_82599_KX4:
7666                 adapter->wol = IXGBE_WUFC_MAG;
7667                 break;
7668         default:
7669                 adapter->wol = 0;
7670                 break;
7671         }
7672         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7673
7674         /* pick up the PCI bus settings for reporting later */
7675         hw->mac.ops.get_bus_info(hw);
7676
7677         /* print bus type/speed/width info */
7678         e_dev_info("(PCI Express:%s:%s) %pM\n",
7679                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7680                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7681                     "Unknown"),
7682                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7683                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7684                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7685                     "Unknown"),
7686                    netdev->dev_addr);
7687
7688         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7689         if (err)
7690                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7691         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7692                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7693                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7694                            part_str);
7695         else
7696                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7697                            hw->mac.type, hw->phy.type, part_str);
7698
7699         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7700                 e_dev_warn("PCI-Express bandwidth available for this card is "
7701                            "not sufficient for optimal performance.\n");
7702                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7703                            "is required.\n");
7704         }
7705
7706         /* save off EEPROM version number */
7707         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7708
7709         /* reset the hardware with the new settings */
7710         err = hw->mac.ops.start_hw(hw);
7711
7712         if (err == IXGBE_ERR_EEPROM_VERSION) {
7713                 /* We are running on a pre-production device, log a warning */
7714                 e_dev_warn("This device is a pre-production adapter/LOM. "
7715                            "Please be aware there may be issues associated "
7716                            "with your hardware.  If you are experiencing "
7717                            "problems please contact your Intel or hardware "
7718                            "representative who provided you with this "
7719                            "hardware.\n");
7720         }
7721         strcpy(netdev->name, "eth%d");
7722         err = register_netdev(netdev);
7723         if (err)
7724                 goto err_register;
7725
7726         /* carrier off reporting is important to ethtool even BEFORE open */
7727         netif_carrier_off(netdev);
7728
7729 #ifdef CONFIG_IXGBE_DCA
7730         if (dca_add_requester(&pdev->dev) == 0) {
7731                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7732                 ixgbe_setup_dca(adapter);
7733         }
7734 #endif
7735         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7736                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7737                 for (i = 0; i < adapter->num_vfs; i++)
7738                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7739         }
7740
7741         /* Inform firmware of driver version */
7742         if (hw->mac.ops.set_fw_drv_ver)
7743                 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7744                                            FW_CEM_UNUSED_VER);
7745
7746         /* add san mac addr to netdev */
7747         ixgbe_add_sanmac_netdev(netdev);
7748
7749         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7750         cards_found++;
7751         return 0;
7752
7753 err_register:
7754         ixgbe_release_hw_control(adapter);
7755         ixgbe_clear_interrupt_scheme(adapter);
7756 err_sw_init:
7757 err_eeprom:
7758         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7759                 ixgbe_disable_sriov(adapter);
7760         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7761         iounmap(hw->hw_addr);
7762 err_ioremap:
7763         free_netdev(netdev);
7764 err_alloc_etherdev:
7765         pci_release_selected_regions(pdev,
7766                                      pci_select_bars(pdev, IORESOURCE_MEM));
7767 err_pci_reg:
7768 err_dma:
7769         pci_disable_device(pdev);
7770         return err;
7771 }
7772
7773 /**
7774  * ixgbe_remove - Device Removal Routine
7775  * @pdev: PCI device information struct
7776  *
7777  * ixgbe_remove is called by the PCI subsystem to alert the driver
7778  * that it should release a PCI device.  The could be caused by a
7779  * Hot-Plug event, or because the driver is going to be removed from
7780  * memory.
7781  **/
7782 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7783 {
7784         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7785         struct net_device *netdev = adapter->netdev;
7786
7787         set_bit(__IXGBE_DOWN, &adapter->state);
7788         cancel_work_sync(&adapter->service_task);
7789
7790 #ifdef CONFIG_IXGBE_DCA
7791         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7792                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7793                 dca_remove_requester(&pdev->dev);
7794                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7795         }
7796
7797 #endif
7798 #ifdef IXGBE_FCOE
7799         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7800                 ixgbe_cleanup_fcoe(adapter);
7801
7802 #endif /* IXGBE_FCOE */
7803
7804         /* remove the added san mac */
7805         ixgbe_del_sanmac_netdev(netdev);
7806
7807         if (netdev->reg_state == NETREG_REGISTERED)
7808                 unregister_netdev(netdev);
7809
7810         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7811                 ixgbe_disable_sriov(adapter);
7812
7813         ixgbe_clear_interrupt_scheme(adapter);
7814
7815         ixgbe_release_hw_control(adapter);
7816
7817         iounmap(adapter->hw.hw_addr);
7818         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7819                                      IORESOURCE_MEM));
7820
7821         e_dev_info("complete\n");
7822
7823         free_netdev(netdev);
7824
7825         pci_disable_pcie_error_reporting(pdev);
7826
7827         pci_disable_device(pdev);
7828 }
7829
7830 /**
7831  * ixgbe_io_error_detected - called when PCI error is detected
7832  * @pdev: Pointer to PCI device
7833  * @state: The current pci connection state
7834  *
7835  * This function is called after a PCI bus error affecting
7836  * this device has been detected.
7837  */
7838 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7839                                                 pci_channel_state_t state)
7840 {
7841         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7842         struct net_device *netdev = adapter->netdev;
7843
7844         netif_device_detach(netdev);
7845
7846         if (state == pci_channel_io_perm_failure)
7847                 return PCI_ERS_RESULT_DISCONNECT;
7848
7849         if (netif_running(netdev))
7850                 ixgbe_down(adapter);
7851         pci_disable_device(pdev);
7852
7853         /* Request a slot reset. */
7854         return PCI_ERS_RESULT_NEED_RESET;
7855 }
7856
7857 /**
7858  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7859  * @pdev: Pointer to PCI device
7860  *
7861  * Restart the card from scratch, as if from a cold-boot.
7862  */
7863 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7864 {
7865         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7866         pci_ers_result_t result;
7867         int err;
7868
7869         if (pci_enable_device_mem(pdev)) {
7870                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7871                 result = PCI_ERS_RESULT_DISCONNECT;
7872         } else {
7873                 pci_set_master(pdev);
7874                 pci_restore_state(pdev);
7875                 pci_save_state(pdev);
7876
7877                 pci_wake_from_d3(pdev, false);
7878
7879                 ixgbe_reset(adapter);
7880                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7881                 result = PCI_ERS_RESULT_RECOVERED;
7882         }
7883
7884         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7885         if (err) {
7886                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7887                           "failed 0x%0x\n", err);
7888                 /* non-fatal, continue */
7889         }
7890
7891         return result;
7892 }
7893
7894 /**
7895  * ixgbe_io_resume - called when traffic can start flowing again.
7896  * @pdev: Pointer to PCI device
7897  *
7898  * This callback is called when the error recovery driver tells us that
7899  * its OK to resume normal operation.
7900  */
7901 static void ixgbe_io_resume(struct pci_dev *pdev)
7902 {
7903         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7904         struct net_device *netdev = adapter->netdev;
7905
7906         if (netif_running(netdev)) {
7907                 if (ixgbe_up(adapter)) {
7908                         e_info(probe, "ixgbe_up failed after reset\n");
7909                         return;
7910                 }
7911         }
7912
7913         netif_device_attach(netdev);
7914 }
7915
7916 static struct pci_error_handlers ixgbe_err_handler = {
7917         .error_detected = ixgbe_io_error_detected,
7918         .slot_reset = ixgbe_io_slot_reset,
7919         .resume = ixgbe_io_resume,
7920 };
7921
7922 static struct pci_driver ixgbe_driver = {
7923         .name     = ixgbe_driver_name,
7924         .id_table = ixgbe_pci_tbl,
7925         .probe    = ixgbe_probe,
7926         .remove   = __devexit_p(ixgbe_remove),
7927 #ifdef CONFIG_PM
7928         .suspend  = ixgbe_suspend,
7929         .resume   = ixgbe_resume,
7930 #endif
7931         .shutdown = ixgbe_shutdown,
7932         .err_handler = &ixgbe_err_handler
7933 };
7934
7935 /**
7936  * ixgbe_init_module - Driver Registration Routine
7937  *
7938  * ixgbe_init_module is the first routine called when the driver is
7939  * loaded. All it does is register with the PCI subsystem.
7940  **/
7941 static int __init ixgbe_init_module(void)
7942 {
7943         int ret;
7944         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7945         pr_info("%s\n", ixgbe_copyright);
7946
7947 #ifdef CONFIG_IXGBE_DCA
7948         dca_register_notify(&dca_notifier);
7949 #endif
7950
7951         ret = pci_register_driver(&ixgbe_driver);
7952         return ret;
7953 }
7954
7955 module_init(ixgbe_init_module);
7956
7957 /**
7958  * ixgbe_exit_module - Driver Exit Cleanup Routine
7959  *
7960  * ixgbe_exit_module is called just before the driver is removed
7961  * from memory.
7962  **/
7963 static void __exit ixgbe_exit_module(void)
7964 {
7965 #ifdef CONFIG_IXGBE_DCA
7966         dca_unregister_notify(&dca_notifier);
7967 #endif
7968         pci_unregister_driver(&ixgbe_driver);
7969         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7970 }
7971
7972 #ifdef CONFIG_IXGBE_DCA
7973 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7974                             void *p)
7975 {
7976         int ret_val;
7977
7978         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7979                                          __ixgbe_notify_dca);
7980
7981         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7982 }
7983
7984 #endif /* CONFIG_IXGBE_DCA */
7985
7986 module_exit(ixgbe_exit_module);
7987
7988 /* ixgbe_main.c */