drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/sctp.h>
  39 #include <linux/pkt_sched.h>
  40 #include <linux/ipv6.h>
  41 #include <linux/slab.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <linux/ethtool.h>
  45 #include <linux/if.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/prefetch.h>
  48 #include <scsi/fc/fc_fcoe.h>
  49
  50 #include "ixgbe.h"
  51 #include "ixgbe_common.h"
  52 #include "ixgbe_dcb_82599.h"
  53 #include "ixgbe_sriov.h"
  54
  55 char ixgbe_driver_name[] = "ixgbe";
  56 static const char ixgbe_driver_string[] =
  57                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  58 #define MAJ 3
  59 #define MIN 6
  60 #define BUILD 7
  61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  62         __stringify(BUILD) "-k"
  63 const char ixgbe_driver_version[] = DRV_VERSION;
  64 static const char ixgbe_copyright[] =
  65                                 "Copyright (c) 1999-2011 Intel Corporation.";
  66
  67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  68         [board_82598] = &ixgbe_82598_info,
  69         [board_82599] = &ixgbe_82599_info,
  70         [board_X540] = &ixgbe_X540_info,
  71 };
  72
  73 /* ixgbe_pci_tbl - PCI Device ID Table
  74  *
  75  * Wildcard entries (PCI_ANY_ID) should come last
  76  * Last entry must be all 0s
  77  *
  78  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  79  *   Class, Class Mask, private data (not used) }
  80  */
  81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
 108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
 110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
 111         /* required last entry */
 112         {0, }
 113 };
 114 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 115
 116 #ifdef CONFIG_IXGBE_DCA
 117 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 118                             void *p);
 119 static struct notifier_block dca_notifier = {
 120         .notifier_call = ixgbe_notify_dca,
 121         .next          = NULL,
 122         .priority      = 0
 123 };
 124 #endif
 125
 126 #ifdef CONFIG_PCI_IOV
 127 static unsigned int max_vfs;
 128 module_param(max_vfs, uint, 0);
 129 MODULE_PARM_DESC(max_vfs,
 130                  "Maximum number of virtual functions to allocate per physical function");
 131 #endif /* CONFIG_PCI_IOV */
 132
 133 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 134 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 135 MODULE_LICENSE("GPL");
 136 MODULE_VERSION(DRV_VERSION);
 137
 138 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 139
 140 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 141 {
 142         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 143             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 144                 schedule_work(&adapter->service_task);
 145 }
 146
 147 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 148 {
 149         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 150
 151         /* flush memory to make sure state is correct before next watchog */
 152         smp_mb__before_clear_bit();
 153         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 154 }
 155
 156 struct ixgbe_reg_info {
 157         u32 ofs;
 158         char *name;
 159 };
 160
 161 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 162
 163         /* General Registers */
 164         {IXGBE_CTRL, "CTRL"},
 165         {IXGBE_STATUS, "STATUS"},
 166         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 167
 168         /* Interrupt Registers */
 169         {IXGBE_EICR, "EICR"},
 170
 171         /* RX Registers */
 172         {IXGBE_SRRCTL(0), "SRRCTL"},
 173         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 174         {IXGBE_RDLEN(0), "RDLEN"},
 175         {IXGBE_RDH(0), "RDH"},
 176         {IXGBE_RDT(0), "RDT"},
 177         {IXGBE_RXDCTL(0), "RXDCTL"},
 178         {IXGBE_RDBAL(0), "RDBAL"},
 179         {IXGBE_RDBAH(0), "RDBAH"},
 180
 181         /* TX Registers */
 182         {IXGBE_TDBAL(0), "TDBAL"},
 183         {IXGBE_TDBAH(0), "TDBAH"},
 184         {IXGBE_TDLEN(0), "TDLEN"},
 185         {IXGBE_TDH(0), "TDH"},
 186         {IXGBE_TDT(0), "TDT"},
 187         {IXGBE_TXDCTL(0), "TXDCTL"},
 188
 189         /* List Terminator */
 190         {}
 191 };
 192
 193
 194 /*
 195  * ixgbe_regdump - register printout routine
 196  */
 197 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 198 {
 199         int i = 0, j = 0;
 200         char rname[16];
 201         u32 regs[64];
 202
 203         switch (reginfo->ofs) {
 204         case IXGBE_SRRCTL(0):
 205                 for (i = 0; i < 64; i++)
 206                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 207                 break;
 208         case IXGBE_DCA_RXCTRL(0):
 209                 for (i = 0; i < 64; i++)
 210                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 211                 break;
 212         case IXGBE_RDLEN(0):
 213                 for (i = 0; i < 64; i++)
 214                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 215                 break;
 216         case IXGBE_RDH(0):
 217                 for (i = 0; i < 64; i++)
 218                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 219                 break;
 220         case IXGBE_RDT(0):
 221                 for (i = 0; i < 64; i++)
 222                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 223                 break;
 224         case IXGBE_RXDCTL(0):
 225                 for (i = 0; i < 64; i++)
 226                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 227                 break;
 228         case IXGBE_RDBAL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 231                 break;
 232         case IXGBE_RDBAH(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 235                 break;
 236         case IXGBE_TDBAL(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 239                 break;
 240         case IXGBE_TDBAH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 243                 break;
 244         case IXGBE_TDLEN(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 247                 break;
 248         case IXGBE_TDH(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 251                 break;
 252         case IXGBE_TDT(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 255                 break;
 256         case IXGBE_TXDCTL(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 259                 break;
 260         default:
 261                 pr_info("%-15s %08x\n", reginfo->name,
 262                         IXGBE_READ_REG(hw, reginfo->ofs));
 263                 return;
 264         }
 265
 266         for (i = 0; i < 8; i++) {
 267                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 268                 pr_err("%-15s", rname);
 269                 for (j = 0; j < 8; j++)
 270                         pr_cont(" %08x", regs[i*8+j]);
 271                 pr_cont("\n");
 272         }
 273
 274 }
 275
 276 /*
 277  * ixgbe_dump - Print registers, tx-rings and rx-rings
 278  */
 279 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 280 {
 281         struct net_device *netdev = adapter->netdev;
 282         struct ixgbe_hw *hw = &adapter->hw;
 283         struct ixgbe_reg_info *reginfo;
 284         int n = 0;
 285         struct ixgbe_ring *tx_ring;
 286         struct ixgbe_tx_buffer *tx_buffer_info;
 287         union ixgbe_adv_tx_desc *tx_desc;
 288         struct my_u0 { u64 a; u64 b; } *u0;
 289         struct ixgbe_ring *rx_ring;
 290         union ixgbe_adv_rx_desc *rx_desc;
 291         struct ixgbe_rx_buffer *rx_buffer_info;
 292         u32 staterr;
 293         int i = 0;
 294
 295         if (!netif_msg_hw(adapter))
 296                 return;
 297
 298         /* Print netdevice Info */
 299         if (netdev) {
 300                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 301                 pr_info("Device Name     state            "
 302                         "trans_start      last_rx\n");
 303                 pr_info("%-15s %016lX %016lX %016lX\n",
 304                         netdev->name,
 305                         netdev->state,
 306                         netdev->trans_start,
 307                         netdev->last_rx);
 308         }
 309
 310         /* Print Registers */
 311         dev_info(&adapter->pdev->dev, "Register Dump\n");
 312         pr_info(" Register Name   Value\n");
 313         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 314              reginfo->name; reginfo++) {
 315                 ixgbe_regdump(hw, reginfo);
 316         }
 317
 318         /* Print TX Ring Summary */
 319         if (!netdev || !netif_running(netdev))
 320                 goto exit;
 321
 322         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 323         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 324         for (n = 0; n < adapter->num_tx_queues; n++) {
 325                 tx_ring = adapter->tx_ring[n];
 326                 tx_buffer_info =
 327                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 328                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 329                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 330                            (u64)tx_buffer_info->dma,
 331                            tx_buffer_info->length,
 332                            tx_buffer_info->next_to_watch,
 333                            (u64)tx_buffer_info->time_stamp);
 334         }
 335
 336         /* Print TX Rings */
 337         if (!netif_msg_tx_done(adapter))
 338                 goto rx_ring_summary;
 339
 340         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 341
 342         /* Transmit Descriptor Formats
 343          *
 344          * Advanced Transmit Descriptor
 345          *   +--------------------------------------------------------------+
 346          * 0 |         Buffer Address [63:0]                                |
 347          *   +--------------------------------------------------------------+
 348          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 349          *   +--------------------------------------------------------------+
 350          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 351          */
 352
 353         for (n = 0; n < adapter->num_tx_queues; n++) {
 354                 tx_ring = adapter->tx_ring[n];
 355                 pr_info("------------------------------------\n");
 356                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 357                 pr_info("------------------------------------\n");
 358                 pr_info("T [desc]     [address 63:0  ] "
 359                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 360                         "leng  ntw timestamp        bi->skb\n");
 361
 362                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 363                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 364                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 365                         u0 = (struct my_u0 *)tx_desc;
 366                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 367                                 " %04X  %p %016llX %p", i,
 368                                 le64_to_cpu(u0->a),
 369                                 le64_to_cpu(u0->b),
 370                                 (u64)tx_buffer_info->dma,
 371                                 tx_buffer_info->length,
 372                                 tx_buffer_info->next_to_watch,
 373                                 (u64)tx_buffer_info->time_stamp,
 374                                 tx_buffer_info->skb);
 375                         if (i == tx_ring->next_to_use &&
 376                                 i == tx_ring->next_to_clean)
 377                                 pr_cont(" NTC/U\n");
 378                         else if (i == tx_ring->next_to_use)
 379                                 pr_cont(" NTU\n");
 380                         else if (i == tx_ring->next_to_clean)
 381                                 pr_cont(" NTC\n");
 382                         else
 383                                 pr_cont("\n");
 384
 385                         if (netif_msg_pktdata(adapter) &&
 386                                 tx_buffer_info->dma != 0)
 387                                 print_hex_dump(KERN_INFO, "",
 388                                         DUMP_PREFIX_ADDRESS, 16, 1,
 389                                         phys_to_virt(tx_buffer_info->dma),
 390                                         tx_buffer_info->length, true);
 391                 }
 392         }
 393
 394         /* Print RX Rings Summary */
 395 rx_ring_summary:
 396         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 397         pr_info("Queue [NTU] [NTC]\n");
 398         for (n = 0; n < adapter->num_rx_queues; n++) {
 399                 rx_ring = adapter->rx_ring[n];
 400                 pr_info("%5d %5X %5X\n",
 401                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 402         }
 403
 404         /* Print RX Rings */
 405         if (!netif_msg_rx_status(adapter))
 406                 goto exit;
 407
 408         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 409
 410         /* Advanced Receive Descriptor (Read) Format
 411          *    63                                           1        0
 412          *    +-----------------------------------------------------+
 413          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 414          *    +----------------------------------------------+------+
 415          *  8 |       Header Buffer Address [63:1]           |  DD  |
 416          *    +-----------------------------------------------------+
 417          *
 418          *
 419          * Advanced Receive Descriptor (Write-Back) Format
 420          *
 421          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 422          *   +------------------------------------------------------+
 423          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 424          *   | Checksum   Ident  |   |           |    | Type | Type |
 425          *   +------------------------------------------------------+
 426          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 427          *   +------------------------------------------------------+
 428          *   63       48 47    32 31            20 19               0
 429          */
 430         for (n = 0; n < adapter->num_rx_queues; n++) {
 431                 rx_ring = adapter->rx_ring[n];
 432                 pr_info("------------------------------------\n");
 433                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 434                 pr_info("------------------------------------\n");
 435                 pr_info("R  [desc]      [ PktBuf     A0] "
 436                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 437                         "<-- Adv Rx Read format\n");
 438                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 439                         "[vl er S cks ln] ---------------- [bi->skb] "
 440                         "<-- Adv Rx Write-Back format\n");
 441
 442                 for (i = 0; i < rx_ring->count; i++) {
 443                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 444                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 445                         u0 = (struct my_u0 *)rx_desc;
 446                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 447                         if (staterr & IXGBE_RXD_STAT_DD) {
 448                                 /* Descriptor Done */
 449                                 pr_info("RWB[0x%03X]     %016llX "
 450                                         "%016llX ---------------- %p", i,
 451                                         le64_to_cpu(u0->a),
 452                                         le64_to_cpu(u0->b),
 453                                         rx_buffer_info->skb);
 454                         } else {
 455                                 pr_info("R  [0x%03X]     %016llX "
 456                                         "%016llX %016llX %p", i,
 457                                         le64_to_cpu(u0->a),
 458                                         le64_to_cpu(u0->b),
 459                                         (u64)rx_buffer_info->dma,
 460                                         rx_buffer_info->skb);
 461
 462                                 if (netif_msg_pktdata(adapter)) {
 463                                         print_hex_dump(KERN_INFO, "",
 464                                            DUMP_PREFIX_ADDRESS, 16, 1,
 465                                            phys_to_virt(rx_buffer_info->dma),
 466                                            rx_ring->rx_buf_len, true);
 467
 468                                         if (rx_ring->rx_buf_len
 469                                                 < IXGBE_RXBUFFER_2K)
 470                                                 print_hex_dump(KERN_INFO, "",
 471                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 472                                                   phys_to_virt(
 473                                                     rx_buffer_info->page_dma +
 474                                                     rx_buffer_info->page_offset
 475                                                   ),
 476                                                   PAGE_SIZE/2, true);
 477                                 }
 478                         }
 479
 480                         if (i == rx_ring->next_to_use)
 481                                 pr_cont(" NTU\n");
 482                         else if (i == rx_ring->next_to_clean)
 483                                 pr_cont(" NTC\n");
 484                         else
 485                                 pr_cont("\n");
 486
 487                 }
 488         }
 489
 490 exit:
 491         return;
 492 }
 493
 494 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 495 {
 496         u32 ctrl_ext;
 497
 498         /* Let firmware take over control of h/w */
 499         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 500         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 501                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 502 }
 503
 504 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 505 {
 506         u32 ctrl_ext;
 507
 508         /* Let firmware know the driver has taken over */
 509         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 510         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 511                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 512 }
 513
 514 /*
 515  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 516  * @adapter: pointer to adapter struct
 517  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 518  * @queue: queue to map the corresponding interrupt to
 519  * @msix_vector: the vector to map to the corresponding queue
 520  *
 521  */
 522 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 523                            u8 queue, u8 msix_vector)
 524 {
 525         u32 ivar, index;
 526         struct ixgbe_hw *hw = &adapter->hw;
 527         switch (hw->mac.type) {
 528         case ixgbe_mac_82598EB:
 529                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 530                 if (direction == -1)
 531                         direction = 0;
 532                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 533                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 534                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 535                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 536                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 537                 break;
 538         case ixgbe_mac_82599EB:
 539         case ixgbe_mac_X540:
 540                 if (direction == -1) {
 541                         /* other causes */
 542                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 543                         index = ((queue & 1) * 8);
 544                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 545                         ivar &= ~(0xFF << index);
 546                         ivar |= (msix_vector << index);
 547                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 548                         break;
 549                 } else {
 550                         /* tx or rx causes */
 551                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 552                         index = ((16 * (queue & 1)) + (8 * direction));
 553                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 554                         ivar &= ~(0xFF << index);
 555                         ivar |= (msix_vector << index);
 556                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 557                         break;
 558                 }
 559         default:
 560                 break;
 561         }
 562 }
 563
 564 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 565                                           u64 qmask)
 566 {
 567         u32 mask;
 568
 569         switch (adapter->hw.mac.type) {
 570         case ixgbe_mac_82598EB:
 571                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 572                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 573                 break;
 574         case ixgbe_mac_82599EB:
 575         case ixgbe_mac_X540:
 576                 mask = (qmask & 0xFFFFFFFF);
 577                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 578                 mask = (qmask >> 32);
 579                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 580                 break;
 581         default:
 582                 break;
 583         }
 584 }
 585
 586 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
 587                                            struct ixgbe_tx_buffer *tx_buffer)
 588 {
 589         if (tx_buffer->dma) {
 590                 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
 591                         dma_unmap_page(ring->dev,
 592                                        tx_buffer->dma,
 593                                        tx_buffer->length,
 594                                        DMA_TO_DEVICE);
 595                 else
 596                         dma_unmap_single(ring->dev,
 597                                          tx_buffer->dma,
 598                                          tx_buffer->length,
 599                                          DMA_TO_DEVICE);
 600         }
 601         tx_buffer->dma = 0;
 602 }
 603
 604 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 605                                       struct ixgbe_tx_buffer *tx_buffer_info)
 606 {
 607         ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
 608         if (tx_buffer_info->skb)
 609                 dev_kfree_skb_any(tx_buffer_info->skb);
 610         tx_buffer_info->skb = NULL;
 611         /* tx_buffer_info must be completely set up in the transmit path */
 612 }
 613
 614 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 615 {
 616         struct ixgbe_hw *hw = &adapter->hw;
 617         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 618         u32 data = 0;
 619         u32 xoff[8] = {0};
 620         int i;
 621
 622         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 623             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 624                 switch (hw->mac.type) {
 625                 case ixgbe_mac_82598EB:
 626                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 627                         break;
 628                 default:
 629                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 630                 }
 631                 hwstats->lxoffrxc += data;
 632
 633                 /* refill credits (no tx hang) if we received xoff */
 634                 if (!data)
 635                         return;
 636
 637                 for (i = 0; i < adapter->num_tx_queues; i++)
 638                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 639                                   &adapter->tx_ring[i]->state);
 640                 return;
 641         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 642                 return;
 643
 644         /* update stats for each tc, only valid with PFC enabled */
 645         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 646                 switch (hw->mac.type) {
 647                 case ixgbe_mac_82598EB:
 648                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 649                         break;
 650                 default:
 651                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 652                 }
 653                 hwstats->pxoffrxc[i] += xoff[i];
 654         }
 655
 656         /* disarm tx queues that have received xoff frames */
 657         for (i = 0; i < adapter->num_tx_queues; i++) {
 658                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 659                 u8 tc = tx_ring->dcb_tc;
 660
 661                 if (xoff[tc])
 662                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 663         }
 664 }
 665
 666 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 667 {
 668         return ring->tx_stats.completed;
 669 }
 670
 671 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 672 {
 673         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 674         struct ixgbe_hw *hw = &adapter->hw;
 675
 676         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 677         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 678
 679         if (head != tail)
 680                 return (head < tail) ?
 681                         tail - head : (tail + ring->count - head);
 682
 683         return 0;
 684 }
 685
 686 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 687 {
 688         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 689         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 690         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 691         bool ret = false;
 692
 693         clear_check_for_tx_hang(tx_ring);
 694
 695         /*
 696          * Check for a hung queue, but be thorough. This verifies
 697          * that a transmit has been completed since the previous
 698          * check AND there is at least one packet pending. The
 699          * ARMED bit is set to indicate a potential hang. The
 700          * bit is cleared if a pause frame is received to remove
 701          * false hang detection due to PFC or 802.3x frames. By
 702          * requiring this to fail twice we avoid races with
 703          * pfc clearing the ARMED bit and conditions where we
 704          * run the check_tx_hang logic with a transmit completion
 705          * pending but without time to complete it yet.
 706          */
 707         if ((tx_done_old == tx_done) && tx_pending) {
 708                 /* make sure it is true for two checks in a row */
 709                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 710                                        &tx_ring->state);
 711         } else {
 712                 /* update completed stats and continue */
 713                 tx_ring->tx_stats.tx_done_old = tx_done;
 714                 /* reset the countdown */
 715                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 716         }
 717
 718         return ret;
 719 }
 720
 721 /**
 722  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 723  * @adapter: driver private struct
 724  **/
 725 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 726 {
 727
 728         /* Do the reset outside of interrupt context */
 729         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 730                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 731                 ixgbe_service_event_schedule(adapter);
 732         }
 733 }
 734
 735 /**
 736  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 737  * @q_vector: structure containing interrupt and ring information
 738  * @tx_ring: tx ring to clean
 739  **/
 740 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 741                                struct ixgbe_ring *tx_ring)
 742 {
 743         struct ixgbe_adapter *adapter = q_vector->adapter;
 744         struct ixgbe_tx_buffer *tx_buffer;
 745         union ixgbe_adv_tx_desc *tx_desc;
 746         unsigned int total_bytes = 0, total_packets = 0;
 747         unsigned int budget = q_vector->tx.work_limit;
 748         u16 i = tx_ring->next_to_clean;
 749
 750         tx_buffer = &tx_ring->tx_buffer_info[i];
 751         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 752
 753         for (; budget; budget--) {
 754                 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
 755
 756                 /* if next_to_watch is not set then there is no work pending */
 757                 if (!eop_desc)
 758                         break;
 759
 760                 /* if DD is not set pending work has not been completed */
 761                 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
 762                         break;
 763
 764                 /* count the packet as being completed */
 765                 tx_ring->tx_stats.completed++;
 766
 767                 /* clear next_to_watch to prevent false hangs */
 768                 tx_buffer->next_to_watch = NULL;
 769
 770                 /* prevent any other reads prior to eop_desc being verified */
 771                 rmb();
 772
 773                 do {
 774                         ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
 775                         tx_desc->wb.status = 0;
 776                         if (likely(tx_desc == eop_desc)) {
 777                                 eop_desc = NULL;
 778                                 dev_kfree_skb_any(tx_buffer->skb);
 779                                 tx_buffer->skb = NULL;
 780
 781                                 total_bytes += tx_buffer->bytecount;
 782                                 total_packets += tx_buffer->gso_segs;
 783                         }
 784
 785                         tx_buffer++;
 786                         tx_desc++;
 787                         i++;
 788                         if (unlikely(i == tx_ring->count)) {
 789                                 i = 0;
 790
 791                                 tx_buffer = tx_ring->tx_buffer_info;
 792                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
 793                         }
 794
 795                 } while (eop_desc);
 796         }
 797
 798         tx_ring->next_to_clean = i;
 799         u64_stats_update_begin(&tx_ring->syncp);
 800         tx_ring->stats.bytes += total_bytes;
 801         tx_ring->stats.packets += total_packets;
 802         u64_stats_update_end(&tx_ring->syncp);
 803         q_vector->tx.total_bytes += total_bytes;
 804         q_vector->tx.total_packets += total_packets;
 805
 806         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 807                 /* schedule immediate reset if we believe we hung */
 808                 struct ixgbe_hw *hw = &adapter->hw;
 809                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 810                 e_err(drv, "Detected Tx Unit Hang\n"
 811                         "  Tx Queue             <%d>\n"
 812                         "  TDH, TDT             <%x>, <%x>\n"
 813                         "  next_to_use          <%x>\n"
 814                         "  next_to_clean        <%x>\n"
 815                         "tx_buffer_info[next_to_clean]\n"
 816                         "  time_stamp           <%lx>\n"
 817                         "  jiffies              <%lx>\n",
 818                         tx_ring->queue_index,
 819                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 820                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 821                         tx_ring->next_to_use, i,
 822                         tx_ring->tx_buffer_info[i].time_stamp, jiffies);
 823
 824                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 825
 826                 e_info(probe,
 827                        "tx hang %d detected on queue %d, resetting adapter\n",
 828                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 829
 830                 /* schedule immediate reset if we believe we hung */
 831                 ixgbe_tx_timeout_reset(adapter);
 832
 833                 /* the adapter is about to reset, no point in enabling stuff */
 834                 return true;
 835         }
 836
 837 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 838         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 839                      (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
 840                 /* Make sure that anybody stopping the queue after this
 841                  * sees the new next_to_clean.
 842                  */
 843                 smp_mb();
 844                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 845                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 846                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 847                         ++tx_ring->tx_stats.restart_queue;
 848                 }
 849         }
 850
 851         return !!budget;
 852 }
 853
 854 #ifdef CONFIG_IXGBE_DCA
 855 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 856                                 struct ixgbe_ring *rx_ring,
 857                                 int cpu)
 858 {
 859         struct ixgbe_hw *hw = &adapter->hw;
 860         u32 rxctrl;
 861         u8 reg_idx = rx_ring->reg_idx;
 862
 863         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 864         switch (hw->mac.type) {
 865         case ixgbe_mac_82598EB:
 866                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 867                 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
 868                 break;
 869         case ixgbe_mac_82599EB:
 870         case ixgbe_mac_X540:
 871                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 872                 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
 873                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 874                 break;
 875         default:
 876                 break;
 877         }
 878         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 879         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 880         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 881         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 882 }
 883
 884 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 885                                 struct ixgbe_ring *tx_ring,
 886                                 int cpu)
 887 {
 888         struct ixgbe_hw *hw = &adapter->hw;
 889         u32 txctrl;
 890         u8 reg_idx = tx_ring->reg_idx;
 891
 892         switch (hw->mac.type) {
 893         case ixgbe_mac_82598EB:
 894                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 895                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 896                 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
 897                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 898                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 899                 break;
 900         case ixgbe_mac_82599EB:
 901         case ixgbe_mac_X540:
 902                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 903                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 904                 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
 905                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 906                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 907                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 908                 break;
 909         default:
 910                 break;
 911         }
 912 }
 913
 914 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 915 {
 916         struct ixgbe_adapter *adapter = q_vector->adapter;
 917         struct ixgbe_ring *ring;
 918         int cpu = get_cpu();
 919
 920         if (q_vector->cpu == cpu)
 921                 goto out_no_update;
 922
 923         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
 924                 ixgbe_update_tx_dca(adapter, ring, cpu);
 925
 926         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
 927                 ixgbe_update_rx_dca(adapter, ring, cpu);
 928
 929         q_vector->cpu = cpu;
 930 out_no_update:
 931         put_cpu();
 932 }
 933
 934 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 935 {
 936         int num_q_vectors;
 937         int i;
 938
 939         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 940                 return;
 941
 942         /* always use CB2 mode, difference is masked in the CB driver */
 943         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 944
 945         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 946                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 947         else
 948                 num_q_vectors = 1;
 949
 950         for (i = 0; i < num_q_vectors; i++) {
 951                 adapter->q_vector[i]->cpu = -1;
 952                 ixgbe_update_dca(adapter->q_vector[i]);
 953         }
 954 }
 955
 956 static int __ixgbe_notify_dca(struct device *dev, void *data)
 957 {
 958         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 959         unsigned long event = *(unsigned long *)data;
 960
 961         if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
 962                 return 0;
 963
 964         switch (event) {
 965         case DCA_PROVIDER_ADD:
 966                 /* if we're already enabled, don't do it again */
 967                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 968                         break;
 969                 if (dca_add_requester(dev) == 0) {
 970                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 971                         ixgbe_setup_dca(adapter);
 972                         break;
 973                 }
 974                 /* Fall Through since DCA is disabled. */
 975         case DCA_PROVIDER_REMOVE:
 976                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 977                         dca_remove_requester(dev);
 978                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 979                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 980                 }
 981                 break;
 982         }
 983
 984         return 0;
 985 }
 986 #endif /* CONFIG_IXGBE_DCA */
 987
 988 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
 989                                  struct sk_buff *skb)
 990 {
 991         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
 992 }
 993
 994 /**
 995  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
 996  * @adapter: address of board private structure
 997  * @rx_desc: advanced rx descriptor
 998  *
 999  * Returns : true if it is FCoE pkt
1000  */
1001 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1002                                     union ixgbe_adv_rx_desc *rx_desc)
1003 {
1004         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1005
1006         return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1007                ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1008                 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1009                              IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1010 }
1011
1012 /**
1013  * ixgbe_receive_skb - Send a completed packet up the stack
1014  * @adapter: board private structure
1015  * @skb: packet to send up
1016  * @status: hardware indication of status of receive
1017  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1018  * @rx_desc: rx descriptor
1019  **/
1020 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1021                               struct sk_buff *skb, u8 status,
1022                               struct ixgbe_ring *ring,
1023                               union ixgbe_adv_rx_desc *rx_desc)
1024 {
1025         struct ixgbe_adapter *adapter = q_vector->adapter;
1026         struct napi_struct *napi = &q_vector->napi;
1027         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1028         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1029
1030         if (is_vlan && (tag & VLAN_VID_MASK))
1031                 __vlan_hwaccel_put_tag(skb, tag);
1032
1033         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1034                 napi_gro_receive(napi, skb);
1035         else
1036                 netif_rx(skb);
1037 }
1038
1039 /**
1040  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1041  * @adapter: address of board private structure
1042  * @status_err: hardware indication of status of receive
1043  * @skb: skb currently being received and modified
1044  * @status_err: status error value of last descriptor in packet
1045  **/
1046 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1047                                      union ixgbe_adv_rx_desc *rx_desc,
1048                                      struct sk_buff *skb,
1049                                      u32 status_err)
1050 {
1051         skb->ip_summed = CHECKSUM_NONE;
1052
1053         /* Rx csum disabled */
1054         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1055                 return;
1056
1057         /* if IP and error */
1058         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1059             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1060                 adapter->hw_csum_rx_error++;
1061                 return;
1062         }
1063
1064         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1065                 return;
1066
1067         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1068                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1069
1070                 /*
1071                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1072                  * checksum errors.
1073                  */
1074                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1075                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1076                         return;
1077
1078                 adapter->hw_csum_rx_error++;
1079                 return;
1080         }
1081
1082         /* It must be a TCP or UDP packet with a valid checksum */
1083         skb->ip_summed = CHECKSUM_UNNECESSARY;
1084 }
1085
1086 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1087 {
1088         /*
1089          * Force memory writes to complete before letting h/w
1090          * know there are new descriptors to fetch.  (Only
1091          * applicable for weak-ordered memory model archs,
1092          * such as IA-64).
1093          */
1094         wmb();
1095         writel(val, rx_ring->tail);
1096 }
1097
1098 /**
1099  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1100  * @rx_ring: ring to place buffers on
1101  * @cleaned_count: number of buffers to replace
1102  **/
1103 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1104 {
1105         union ixgbe_adv_rx_desc *rx_desc;
1106         struct ixgbe_rx_buffer *bi;
1107         struct sk_buff *skb;
1108         u16 i = rx_ring->next_to_use;
1109
1110         /* do nothing if no valid netdev defined */
1111         if (!rx_ring->netdev)
1112                 return;
1113
1114         while (cleaned_count--) {
1115                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1116                 bi = &rx_ring->rx_buffer_info[i];
1117                 skb = bi->skb;
1118
1119                 if (!skb) {
1120                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1121                                                         rx_ring->rx_buf_len);
1122                         if (!skb) {
1123                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1124                                 goto no_buffers;
1125                         }
1126                         /* initialize queue mapping */
1127                         skb_record_rx_queue(skb, rx_ring->queue_index);
1128                         bi->skb = skb;
1129                 }
1130
1131                 if (!bi->dma) {
1132                         bi->dma = dma_map_single(rx_ring->dev,
1133                                                  skb->data,
1134                                                  rx_ring->rx_buf_len,
1135                                                  DMA_FROM_DEVICE);
1136                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1137                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1138                                 bi->dma = 0;
1139                                 goto no_buffers;
1140                         }
1141                 }
1142
1143                 if (ring_is_ps_enabled(rx_ring)) {
1144                         if (!bi->page) {
1145                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1146                                 if (!bi->page) {
1147                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1148                                         goto no_buffers;
1149                                 }
1150                         }
1151
1152                         if (!bi->page_dma) {
1153                                 /* use a half page if we're re-using */
1154                                 bi->page_offset ^= PAGE_SIZE / 2;
1155                                 bi->page_dma = dma_map_page(rx_ring->dev,
1156                                                             bi->page,
1157                                                             bi->page_offset,
1158                                                             PAGE_SIZE / 2,
1159                                                             DMA_FROM_DEVICE);
1160                                 if (dma_mapping_error(rx_ring->dev,
1161                                                       bi->page_dma)) {
1162                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1163                                         bi->page_dma = 0;
1164                                         goto no_buffers;
1165                                 }
1166                         }
1167
1168                         /* Refresh the desc even if buffer_addrs didn't change
1169                          * because each write-back erases this info. */
1170                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1171                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1172                 } else {
1173                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1174                         rx_desc->read.hdr_addr = 0;
1175                 }
1176
1177                 i++;
1178                 if (i == rx_ring->count)
1179                         i = 0;
1180         }
1181
1182 no_buffers:
1183         if (rx_ring->next_to_use != i) {
1184                 rx_ring->next_to_use = i;
1185                 ixgbe_release_rx_desc(rx_ring, i);
1186         }
1187 }
1188
1189 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1190 {
1191         /* HW will not DMA in data larger than the given buffer, even if it
1192          * parses the (NFS, of course) header to be larger.  In that case, it
1193          * fills the header buffer and spills the rest into the page.
1194          */
1195         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1196         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1197                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1198         if (hlen > IXGBE_RX_HDR_SIZE)
1199                 hlen = IXGBE_RX_HDR_SIZE;
1200         return hlen;
1201 }
1202
1203 /**
1204  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1205  * @skb: pointer to the last skb in the rsc queue
1206  *
1207  * This function changes a queue full of hw rsc buffers into a completed
1208  * packet.  It uses the ->prev pointers to find the first packet and then
1209  * turns it into the frag list owner.
1210  **/
1211 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1212 {
1213         unsigned int frag_list_size = 0;
1214         unsigned int skb_cnt = 1;
1215
1216         while (skb->prev) {
1217                 struct sk_buff *prev = skb->prev;
1218                 frag_list_size += skb->len;
1219                 skb->prev = NULL;
1220                 skb = prev;
1221                 skb_cnt++;
1222         }
1223
1224         skb_shinfo(skb)->frag_list = skb->next;
1225         skb->next = NULL;
1226         skb->len += frag_list_size;
1227         skb->data_len += frag_list_size;
1228         skb->truesize += frag_list_size;
1229         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1230
1231         return skb;
1232 }
1233
1234 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1235 {
1236         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1237                 IXGBE_RXDADV_RSCCNT_MASK);
1238 }
1239
1240 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1241                                struct ixgbe_ring *rx_ring,
1242                                int budget)
1243 {
1244         struct ixgbe_adapter *adapter = q_vector->adapter;
1245         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1246         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1247         struct sk_buff *skb;
1248         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1249         const int current_node = numa_node_id();
1250 #ifdef IXGBE_FCOE
1251         int ddp_bytes = 0;
1252 #endif /* IXGBE_FCOE */
1253         u32 staterr;
1254         u16 i;
1255         u16 cleaned_count = 0;
1256         bool pkt_is_rsc = false;
1257
1258         i = rx_ring->next_to_clean;
1259         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1260         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1261
1262         while (staterr & IXGBE_RXD_STAT_DD) {
1263                 u32 upper_len = 0;
1264
1265                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1266
1267                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1268
1269                 skb = rx_buffer_info->skb;
1270                 rx_buffer_info->skb = NULL;
1271                 prefetch(skb->data);
1272
1273                 if (ring_is_rsc_enabled(rx_ring))
1274                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1275
1276                 /* linear means we are building an skb from multiple pages */
1277                 if (!skb_is_nonlinear(skb)) {
1278                         u16 hlen;
1279                         if (pkt_is_rsc &&
1280                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1281                             !skb->prev) {
1282                                 /*
1283                                  * When HWRSC is enabled, delay unmapping
1284                                  * of the first packet. It carries the
1285                                  * header information, HW may still
1286                                  * access the header after the writeback.
1287                                  * Only unmap it when EOP is reached
1288                                  */
1289                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1290                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1291                         } else {
1292                                 dma_unmap_single(rx_ring->dev,
1293                                                  rx_buffer_info->dma,
1294                                                  rx_ring->rx_buf_len,
1295                                                  DMA_FROM_DEVICE);
1296                         }
1297                         rx_buffer_info->dma = 0;
1298
1299                         if (ring_is_ps_enabled(rx_ring)) {
1300                                 hlen = ixgbe_get_hlen(rx_desc);
1301                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1302                         } else {
1303                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1304                         }
1305
1306                         skb_put(skb, hlen);
1307                 } else {
1308                         /* assume packet split since header is unmapped */
1309                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1310                 }
1311
1312                 if (upper_len) {
1313                         dma_unmap_page(rx_ring->dev,
1314                                        rx_buffer_info->page_dma,
1315                                        PAGE_SIZE / 2,
1316                                        DMA_FROM_DEVICE);
1317                         rx_buffer_info->page_dma = 0;
1318                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1319                                            rx_buffer_info->page,
1320                                            rx_buffer_info->page_offset,
1321                                            upper_len);
1322
1323                         if ((page_count(rx_buffer_info->page) == 1) &&
1324                             (page_to_nid(rx_buffer_info->page) == current_node))
1325                                 get_page(rx_buffer_info->page);
1326                         else
1327                                 rx_buffer_info->page = NULL;
1328
1329                         skb->len += upper_len;
1330                         skb->data_len += upper_len;
1331                         skb->truesize += PAGE_SIZE / 2;
1332                 }
1333
1334                 i++;
1335                 if (i == rx_ring->count)
1336                         i = 0;
1337
1338                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1339                 prefetch(next_rxd);
1340                 cleaned_count++;
1341
1342                 if (pkt_is_rsc) {
1343                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1344                                      IXGBE_RXDADV_NEXTP_SHIFT;
1345                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1346                 } else {
1347                         next_buffer = &rx_ring->rx_buffer_info[i];
1348                 }
1349
1350                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1351                         if (ring_is_ps_enabled(rx_ring)) {
1352                                 rx_buffer_info->skb = next_buffer->skb;
1353                                 rx_buffer_info->dma = next_buffer->dma;
1354                                 next_buffer->skb = skb;
1355                                 next_buffer->dma = 0;
1356                         } else {
1357                                 skb->next = next_buffer->skb;
1358                                 skb->next->prev = skb;
1359                         }
1360                         rx_ring->rx_stats.non_eop_descs++;
1361                         goto next_desc;
1362                 }
1363
1364                 if (skb->prev) {
1365                         skb = ixgbe_transform_rsc_queue(skb);
1366                         /* if we got here without RSC the packet is invalid */
1367                         if (!pkt_is_rsc) {
1368                                 __pskb_trim(skb, 0);
1369                                 rx_buffer_info->skb = skb;
1370                                 goto next_desc;
1371                         }
1372                 }
1373
1374                 if (ring_is_rsc_enabled(rx_ring)) {
1375                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1376                                 dma_unmap_single(rx_ring->dev,
1377                                                  IXGBE_RSC_CB(skb)->dma,
1378                                                  rx_ring->rx_buf_len,
1379                                                  DMA_FROM_DEVICE);
1380                                 IXGBE_RSC_CB(skb)->dma = 0;
1381                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1382                         }
1383                 }
1384                 if (pkt_is_rsc) {
1385                         if (ring_is_ps_enabled(rx_ring))
1386                                 rx_ring->rx_stats.rsc_count +=
1387                                         skb_shinfo(skb)->nr_frags;
1388                         else
1389                                 rx_ring->rx_stats.rsc_count +=
1390                                         IXGBE_RSC_CB(skb)->skb_cnt;
1391                         rx_ring->rx_stats.rsc_flush++;
1392                 }
1393
1394                 /* ERR_MASK will only have valid bits if EOP set */
1395                 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1396                         dev_kfree_skb_any(skb);
1397                         goto next_desc;
1398                 }
1399
1400                 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1401                 if (adapter->netdev->features & NETIF_F_RXHASH)
1402                         ixgbe_rx_hash(rx_desc, skb);
1403
1404                 /* probably a little skewed due to removing CRC */
1405                 total_rx_bytes += skb->len;
1406                 total_rx_packets++;
1407
1408                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1409 #ifdef IXGBE_FCOE
1410                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1411                 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1412                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1413                                                    staterr);
1414                         if (!ddp_bytes) {
1415                                 dev_kfree_skb_any(skb);
1416                                 goto next_desc;
1417                         }
1418                 }
1419 #endif /* IXGBE_FCOE */
1420                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1421
1422                 budget--;
1423 next_desc:
1424                 rx_desc->wb.upper.status_error = 0;
1425
1426                 if (!budget)
1427                         break;
1428
1429                 /* return some buffers to hardware, one at a time is too slow */
1430                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1431                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1432                         cleaned_count = 0;
1433                 }
1434
1435                 /* use prefetched values */
1436                 rx_desc = next_rxd;
1437                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1438         }
1439
1440         rx_ring->next_to_clean = i;
1441         cleaned_count = ixgbe_desc_unused(rx_ring);
1442
1443         if (cleaned_count)
1444                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1445
1446 #ifdef IXGBE_FCOE
1447         /* include DDPed FCoE data */
1448         if (ddp_bytes > 0) {
1449                 unsigned int mss;
1450
1451                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1452                         sizeof(struct fc_frame_header) -
1453                         sizeof(struct fcoe_crc_eof);
1454                 if (mss > 512)
1455                         mss &= ~511;
1456                 total_rx_bytes += ddp_bytes;
1457                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1458         }
1459 #endif /* IXGBE_FCOE */
1460
1461         u64_stats_update_begin(&rx_ring->syncp);
1462         rx_ring->stats.packets += total_rx_packets;
1463         rx_ring->stats.bytes += total_rx_bytes;
1464         u64_stats_update_end(&rx_ring->syncp);
1465         q_vector->rx.total_packets += total_rx_packets;
1466         q_vector->rx.total_bytes += total_rx_bytes;
1467
1468         return !!budget;
1469 }
1470
1471 /**
1472  * ixgbe_configure_msix - Configure MSI-X hardware
1473  * @adapter: board private structure
1474  *
1475  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1476  * interrupts.
1477  **/
1478 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1479 {
1480         struct ixgbe_q_vector *q_vector;
1481         int q_vectors, v_idx;
1482         u32 mask;
1483
1484         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1485
1486         /* Populate MSIX to EITR Select */
1487         if (adapter->num_vfs > 32) {
1488                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1489                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1490         }
1491
1492         /*
1493          * Populate the IVAR table and set the ITR values to the
1494          * corresponding register.
1495          */
1496         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1497                 struct ixgbe_ring *ring;
1498                 q_vector = adapter->q_vector[v_idx];
1499
1500                 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1501                         ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1502
1503                 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1504                         ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1505
1506                 if (q_vector->tx.ring && !q_vector->rx.ring) {
1507                         /* tx only vector */
1508                         if (adapter->tx_itr_setting == 1)
1509                                 q_vector->itr = IXGBE_10K_ITR;
1510                         else
1511                                 q_vector->itr = adapter->tx_itr_setting;
1512                 } else {
1513                         /* rx or rx/tx vector */
1514                         if (adapter->rx_itr_setting == 1)
1515                                 q_vector->itr = IXGBE_20K_ITR;
1516                         else
1517                                 q_vector->itr = adapter->rx_itr_setting;
1518                 }
1519
1520                 ixgbe_write_eitr(q_vector);
1521         }
1522
1523         switch (adapter->hw.mac.type) {
1524         case ixgbe_mac_82598EB:
1525                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1526                                v_idx);
1527                 break;
1528         case ixgbe_mac_82599EB:
1529         case ixgbe_mac_X540:
1530                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1531                 break;
1532         default:
1533                 break;
1534         }
1535         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1536
1537         /* set up to autoclear timer, and the vectors */
1538         mask = IXGBE_EIMS_ENABLE_MASK;
1539         mask &= ~(IXGBE_EIMS_OTHER |
1540                   IXGBE_EIMS_MAILBOX |
1541                   IXGBE_EIMS_LSC);
1542
1543         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1544 }
1545
1546 enum latency_range {
1547         lowest_latency = 0,
1548         low_latency = 1,
1549         bulk_latency = 2,
1550         latency_invalid = 255
1551 };
1552
1553 /**
1554  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1555  * @q_vector: structure containing interrupt and ring information
1556  * @ring_container: structure containing ring performance data
1557  *
1558  *      Stores a new ITR value based on packets and byte
1559  *      counts during the last interrupt.  The advantage of per interrupt
1560  *      computation is faster updates and more accurate ITR for the current
1561  *      traffic pattern.  Constants in this function were computed
1562  *      based on theoretical maximum wire speed and thresholds were set based
1563  *      on testing data as well as attempting to minimize response time
1564  *      while increasing bulk throughput.
1565  *      this functionality is controlled by the InterruptThrottleRate module
1566  *      parameter (see ixgbe_param.c)
1567  **/
1568 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1569                              struct ixgbe_ring_container *ring_container)
1570 {
1571         u64 bytes_perint;
1572         struct ixgbe_adapter *adapter = q_vector->adapter;
1573         int bytes = ring_container->total_bytes;
1574         int packets = ring_container->total_packets;
1575         u32 timepassed_us;
1576         u8 itr_setting = ring_container->itr;
1577
1578         if (packets == 0)
1579                 return;
1580
1581         /* simple throttlerate management
1582          *    0-20MB/s lowest (100000 ints/s)
1583          *   20-100MB/s low   (20000 ints/s)
1584          *  100-1249MB/s bulk (8000 ints/s)
1585          */
1586         /* what was last interrupt timeslice? */
1587         timepassed_us = q_vector->itr >> 2;
1588         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1589
1590         switch (itr_setting) {
1591         case lowest_latency:
1592                 if (bytes_perint > adapter->eitr_low)
1593                         itr_setting = low_latency;
1594                 break;
1595         case low_latency:
1596                 if (bytes_perint > adapter->eitr_high)
1597                         itr_setting = bulk_latency;
1598                 else if (bytes_perint <= adapter->eitr_low)
1599                         itr_setting = lowest_latency;
1600                 break;
1601         case bulk_latency:
1602                 if (bytes_perint <= adapter->eitr_high)
1603                         itr_setting = low_latency;
1604                 break;
1605         }
1606
1607         /* clear work counters since we have the values we need */
1608         ring_container->total_bytes = 0;
1609         ring_container->total_packets = 0;
1610
1611         /* write updated itr to ring container */
1612         ring_container->itr = itr_setting;
1613 }
1614
1615 /**
1616  * ixgbe_write_eitr - write EITR register in hardware specific way
1617  * @q_vector: structure containing interrupt and ring information
1618  *
1619  * This function is made to be called by ethtool and by the driver
1620  * when it needs to update EITR registers at runtime.  Hardware
1621  * specific quirks/differences are taken care of here.
1622  */
1623 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1624 {
1625         struct ixgbe_adapter *adapter = q_vector->adapter;
1626         struct ixgbe_hw *hw = &adapter->hw;
1627         int v_idx = q_vector->v_idx;
1628         u32 itr_reg = q_vector->itr;
1629
1630         switch (adapter->hw.mac.type) {
1631         case ixgbe_mac_82598EB:
1632                 /* must write high and low 16 bits to reset counter */
1633                 itr_reg |= (itr_reg << 16);
1634                 break;
1635         case ixgbe_mac_82599EB:
1636         case ixgbe_mac_X540:
1637                 /*
1638                  * set the WDIS bit to not clear the timer bits and cause an
1639                  * immediate assertion of the interrupt
1640                  */
1641                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1642                 break;
1643         default:
1644                 break;
1645         }
1646         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1647 }
1648
1649 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1650 {
1651         u32 new_itr = q_vector->itr;
1652         u8 current_itr;
1653
1654         ixgbe_update_itr(q_vector, &q_vector->tx);
1655         ixgbe_update_itr(q_vector, &q_vector->rx);
1656
1657         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1658
1659         switch (current_itr) {
1660         /* counts and packets in update_itr are dependent on these numbers */
1661         case lowest_latency:
1662                 new_itr = IXGBE_100K_ITR;
1663                 break;
1664         case low_latency:
1665                 new_itr = IXGBE_20K_ITR;
1666                 break;
1667         case bulk_latency:
1668                 new_itr = IXGBE_8K_ITR;
1669                 break;
1670         default:
1671                 break;
1672         }
1673
1674         if (new_itr != q_vector->itr) {
1675                 /* do an exponential smoothing */
1676                 new_itr = (10 * new_itr * q_vector->itr) /
1677                           ((9 * new_itr) + q_vector->itr);
1678
1679                 /* save the algorithm value here */
1680                 q_vector->itr = new_itr & IXGBE_MAX_EITR;
1681
1682                 ixgbe_write_eitr(q_vector);
1683         }
1684 }
1685
1686 /**
1687  * ixgbe_check_overtemp_subtask - check for over tempurature
1688  * @adapter: pointer to adapter
1689  **/
1690 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1691 {
1692         struct ixgbe_hw *hw = &adapter->hw;
1693         u32 eicr = adapter->interrupt_event;
1694
1695         if (test_bit(__IXGBE_DOWN, &adapter->state))
1696                 return;
1697
1698         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1699             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1700                 return;
1701
1702         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1703
1704         switch (hw->device_id) {
1705         case IXGBE_DEV_ID_82599_T3_LOM:
1706                 /*
1707                  * Since the warning interrupt is for both ports
1708                  * we don't have to check if:
1709                  *  - This interrupt wasn't for our port.
1710                  *  - We may have missed the interrupt so always have to
1711                  *    check if we  got a LSC
1712                  */
1713                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1714                     !(eicr & IXGBE_EICR_LSC))
1715                         return;
1716
1717                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1718                         u32 autoneg;
1719                         bool link_up = false;
1720
1721                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1722
1723                         if (link_up)
1724                                 return;
1725                 }
1726
1727                 /* Check if this is not due to overtemp */
1728                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1729                         return;
1730
1731                 break;
1732         default:
1733                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1734                         return;
1735                 break;
1736         }
1737         e_crit(drv,
1738                "Network adapter has been stopped because it has over heated. "
1739                "Restart the computer. If the problem persists, "
1740                "power off the system and replace the adapter\n");
1741
1742         adapter->interrupt_event = 0;
1743 }
1744
1745 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1746 {
1747         struct ixgbe_hw *hw = &adapter->hw;
1748
1749         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1750             (eicr & IXGBE_EICR_GPI_SDP1)) {
1751                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1752                 /* write to clear the interrupt */
1753                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1754         }
1755 }
1756
1757 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1758 {
1759         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1760                 return;
1761
1762         switch (adapter->hw.mac.type) {
1763         case ixgbe_mac_82599EB:
1764                 /*
1765                  * Need to check link state so complete overtemp check
1766                  * on service task
1767                  */
1768                 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1769                     (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1770                         adapter->interrupt_event = eicr;
1771                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1772                         ixgbe_service_event_schedule(adapter);
1773                         return;
1774                 }
1775                 return;
1776         case ixgbe_mac_X540:
1777                 if (!(eicr & IXGBE_EICR_TS))
1778                         return;
1779                 break;
1780         default:
1781                 return;
1782         }
1783
1784         e_crit(drv,
1785                "Network adapter has been stopped because it has over heated. "
1786                "Restart the computer. If the problem persists, "
1787                "power off the system and replace the adapter\n");
1788 }
1789
1790 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1791 {
1792         struct ixgbe_hw *hw = &adapter->hw;
1793
1794         if (eicr & IXGBE_EICR_GPI_SDP2) {
1795                 /* Clear the interrupt */
1796                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1797                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1798                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1799                         ixgbe_service_event_schedule(adapter);
1800                 }
1801         }
1802
1803         if (eicr & IXGBE_EICR_GPI_SDP1) {
1804                 /* Clear the interrupt */
1805                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1806                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1807                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1808                         ixgbe_service_event_schedule(adapter);
1809                 }
1810         }
1811 }
1812
1813 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1814 {
1815         struct ixgbe_hw *hw = &adapter->hw;
1816
1817         adapter->lsc_int++;
1818         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1819         adapter->link_check_timeout = jiffies;
1820         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1821                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1822                 IXGBE_WRITE_FLUSH(hw);
1823                 ixgbe_service_event_schedule(adapter);
1824         }
1825 }
1826
1827 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1828                                            u64 qmask)
1829 {
1830         u32 mask;
1831         struct ixgbe_hw *hw = &adapter->hw;
1832
1833         switch (hw->mac.type) {
1834         case ixgbe_mac_82598EB:
1835                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1836                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1837                 break;
1838         case ixgbe_mac_82599EB:
1839         case ixgbe_mac_X540:
1840                 mask = (qmask & 0xFFFFFFFF);
1841                 if (mask)
1842                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1843                 mask = (qmask >> 32);
1844                 if (mask)
1845                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1846                 break;
1847         default:
1848                 break;
1849         }
1850         /* skip the flush */
1851 }
1852
1853 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1854                                             u64 qmask)
1855 {
1856         u32 mask;
1857         struct ixgbe_hw *hw = &adapter->hw;
1858
1859         switch (hw->mac.type) {
1860         case ixgbe_mac_82598EB:
1861                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1862                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1863                 break;
1864         case ixgbe_mac_82599EB:
1865         case ixgbe_mac_X540:
1866                 mask = (qmask & 0xFFFFFFFF);
1867                 if (mask)
1868                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1869                 mask = (qmask >> 32);
1870                 if (mask)
1871                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1872                 break;
1873         default:
1874                 break;
1875         }
1876         /* skip the flush */
1877 }
1878
1879 /**
1880  * ixgbe_irq_enable - Enable default interrupt generation settings
1881  * @adapter: board private structure
1882  **/
1883 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1884                                     bool flush)
1885 {
1886         u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1887
1888         /* don't reenable LSC while waiting for link */
1889         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1890                 mask &= ~IXGBE_EIMS_LSC;
1891
1892         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
1893                 switch (adapter->hw.mac.type) {
1894                 case ixgbe_mac_82599EB:
1895                         mask |= IXGBE_EIMS_GPI_SDP0;
1896                         break;
1897                 case ixgbe_mac_X540:
1898                         mask |= IXGBE_EIMS_TS;
1899                         break;
1900                 default:
1901                         break;
1902                 }
1903         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1904                 mask |= IXGBE_EIMS_GPI_SDP1;
1905         switch (adapter->hw.mac.type) {
1906         case ixgbe_mac_82599EB:
1907                 mask |= IXGBE_EIMS_GPI_SDP1;
1908                 mask |= IXGBE_EIMS_GPI_SDP2;
1909         case ixgbe_mac_X540:
1910                 mask |= IXGBE_EIMS_ECC;
1911                 mask |= IXGBE_EIMS_MAILBOX;
1912                 break;
1913         default:
1914                 break;
1915         }
1916         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1917             !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1918                 mask |= IXGBE_EIMS_FLOW_DIR;
1919
1920         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1921         if (queues)
1922                 ixgbe_irq_enable_queues(adapter, ~0);
1923         if (flush)
1924                 IXGBE_WRITE_FLUSH(&adapter->hw);
1925 }
1926
1927 static irqreturn_t ixgbe_msix_other(int irq, void *data)
1928 {
1929         struct ixgbe_adapter *adapter = data;
1930         struct ixgbe_hw *hw = &adapter->hw;
1931         u32 eicr;
1932
1933         /*
1934          * Workaround for Silicon errata.  Use clear-by-write instead
1935          * of clear-by-read.  Reading with EICS will return the
1936          * interrupt causes without clearing, which later be done
1937          * with the write to EICR.
1938          */
1939         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1940
1941         /* The lower 16bits of the EICR register are for the queue interrupts
1942          * which should be masked here in order to not accidently clear them if
1943          * the bits are high when ixgbe_msix_other is called. There is a race
1944          * condition otherwise which results in possible performance loss
1945          * especially if the ixgbe_msix_other interrupt is triggering
1946          * consistently (as it would when PPS is turned on for the X540 device)
1947          */
1948         eicr &= 0xFFFF0000;
1949
1950         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1951
1952         if (eicr & IXGBE_EICR_LSC)
1953                 ixgbe_check_lsc(adapter);
1954
1955         if (eicr & IXGBE_EICR_MAILBOX)
1956                 ixgbe_msg_task(adapter);
1957
1958         switch (hw->mac.type) {
1959         case ixgbe_mac_82599EB:
1960         case ixgbe_mac_X540:
1961                 if (eicr & IXGBE_EICR_ECC)
1962                         e_info(link, "Received unrecoverable ECC Err, please "
1963                                "reboot\n");
1964                 /* Handle Flow Director Full threshold interrupt */
1965                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1966                         int reinit_count = 0;
1967                         int i;
1968                         for (i = 0; i < adapter->num_tx_queues; i++) {
1969                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1970                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1971                                                        &ring->state))
1972                                         reinit_count++;
1973                         }
1974                         if (reinit_count) {
1975                                 /* no more flow director interrupts until after init */
1976                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1977                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1978                                 ixgbe_service_event_schedule(adapter);
1979                         }
1980                 }
1981                 ixgbe_check_sfp_event(adapter, eicr);
1982                 ixgbe_check_overtemp_event(adapter, eicr);
1983                 break;
1984         default:
1985                 break;
1986         }
1987
1988         ixgbe_check_fan_failure(adapter, eicr);
1989
1990         /* re-enable the original interrupt state, no lsc, no queues */
1991         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1992                 ixgbe_irq_enable(adapter, false, false);
1993
1994         return IRQ_HANDLED;
1995 }
1996
1997 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1998 {
1999         struct ixgbe_q_vector *q_vector = data;
2000
2001         /* EIAM disabled interrupts (on this vector) for us */
2002
2003         if (q_vector->rx.ring || q_vector->tx.ring)
2004                 napi_schedule(&q_vector->napi);
2005
2006         return IRQ_HANDLED;
2007 }
2008
2009 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2010                                      int r_idx)
2011 {
2012         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2013         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2014
2015         rx_ring->q_vector = q_vector;
2016         rx_ring->next = q_vector->rx.ring;
2017         q_vector->rx.ring = rx_ring;
2018         q_vector->rx.count++;
2019 }
2020
2021 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2022                                      int t_idx)
2023 {
2024         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2025         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2026
2027         tx_ring->q_vector = q_vector;
2028         tx_ring->next = q_vector->tx.ring;
2029         q_vector->tx.ring = tx_ring;
2030         q_vector->tx.count++;
2031         q_vector->tx.work_limit = a->tx_work_limit;
2032 }
2033
2034 /**
2035  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2036  * @adapter: board private structure to initialize
2037  *
2038  * This function maps descriptor rings to the queue-specific vectors
2039  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2040  * one vector per ring/queue, but on a constrained vector budget, we
2041  * group the rings as "efficiently" as possible.  You would add new
2042  * mapping configurations in here.
2043  **/
2044 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2045 {
2046         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2047         int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2048         int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
2049         int v_start = 0;
2050
2051         /* only one q_vector if MSI-X is disabled. */
2052         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2053                 q_vectors = 1;
2054
2055         /*
2056          * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2057          * group them so there are multiple queues per vector.
2058          *
2059          * Re-adjusting *qpv takes care of the remainder.
2060          */
2061         for (; v_start < q_vectors && rxr_remaining; v_start++) {
2062                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2063                 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2064                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2065         }
2066
2067         /*
2068          * If there are not enough q_vectors for each ring to have it's own
2069          * vector then we must pair up Rx/Tx on a each vector
2070          */
2071         if ((v_start + txr_remaining) > q_vectors)
2072                 v_start = 0;
2073
2074         for (; v_start < q_vectors && txr_remaining; v_start++) {
2075                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2076                 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2077                         map_vector_to_txq(adapter, v_start, txr_idx);
2078         }
2079 }
2080
2081 /**
2082  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2083  * @adapter: board private structure
2084  *
2085  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2086  * interrupts from the kernel.
2087  **/
2088 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2089 {
2090         struct net_device *netdev = adapter->netdev;
2091         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2092         int vector, err;
2093         int ri = 0, ti = 0;
2094
2095         for (vector = 0; vector < q_vectors; vector++) {
2096                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2097                 struct msix_entry *entry = &adapter->msix_entries[vector];
2098
2099                 if (q_vector->tx.ring && q_vector->rx.ring) {
2100                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2101                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2102                         ti++;
2103                 } else if (q_vector->rx.ring) {
2104                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2105                                  "%s-%s-%d", netdev->name, "rx", ri++);
2106                 } else if (q_vector->tx.ring) {
2107                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2108                                  "%s-%s-%d", netdev->name, "tx", ti++);
2109                 } else {
2110                         /* skip this unused q_vector */
2111                         continue;
2112                 }
2113                 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2114                                   q_vector->name, q_vector);
2115                 if (err) {
2116                         e_err(probe, "request_irq failed for MSIX interrupt "
2117                               "Error: %d\n", err);
2118                         goto free_queue_irqs;
2119                 }
2120                 /* If Flow Director is enabled, set interrupt affinity */
2121                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2122                         /* assign the mask for this irq */
2123                         irq_set_affinity_hint(entry->vector,
2124                                               q_vector->affinity_mask);
2125                 }
2126         }
2127
2128         err = request_irq(adapter->msix_entries[vector].vector,
2129                           ixgbe_msix_other, 0, netdev->name, adapter);
2130         if (err) {
2131                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2132                 goto free_queue_irqs;
2133         }
2134
2135         return 0;
2136
2137 free_queue_irqs:
2138         while (vector) {
2139                 vector--;
2140                 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2141                                       NULL);
2142                 free_irq(adapter->msix_entries[vector].vector,
2143                          adapter->q_vector[vector]);
2144         }
2145         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2146         pci_disable_msix(adapter->pdev);
2147         kfree(adapter->msix_entries);
2148         adapter->msix_entries = NULL;
2149         return err;
2150 }
2151
2152 /**
2153  * ixgbe_intr - legacy mode Interrupt Handler
2154  * @irq: interrupt number
2155  * @data: pointer to a network interface device structure
2156  **/
2157 static irqreturn_t ixgbe_intr(int irq, void *data)
2158 {
2159         struct ixgbe_adapter *adapter = data;
2160         struct ixgbe_hw *hw = &adapter->hw;
2161         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2162         u32 eicr;
2163
2164         /*
2165          * Workaround for silicon errata on 82598.  Mask the interrupts
2166          * before the read of EICR.
2167          */
2168         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2169
2170         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2171          * therefore no explict interrupt disable is necessary */
2172         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2173         if (!eicr) {
2174                 /*
2175                  * shared interrupt alert!
2176                  * make sure interrupts are enabled because the read will
2177                  * have disabled interrupts due to EIAM
2178                  * finish the workaround of silicon errata on 82598.  Unmask
2179                  * the interrupt that we masked before the EICR read.
2180                  */
2181                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2182                         ixgbe_irq_enable(adapter, true, true);
2183                 return IRQ_NONE;        /* Not our interrupt */
2184         }
2185
2186         if (eicr & IXGBE_EICR_LSC)
2187                 ixgbe_check_lsc(adapter);
2188
2189         switch (hw->mac.type) {
2190         case ixgbe_mac_82599EB:
2191                 ixgbe_check_sfp_event(adapter, eicr);
2192                 /* Fall through */
2193         case ixgbe_mac_X540:
2194                 if (eicr & IXGBE_EICR_ECC)
2195                         e_info(link, "Received unrecoverable ECC err, please "
2196                                      "reboot\n");
2197                 ixgbe_check_overtemp_event(adapter, eicr);
2198                 break;
2199         default:
2200                 break;
2201         }
2202
2203         ixgbe_check_fan_failure(adapter, eicr);
2204
2205         if (napi_schedule_prep(&(q_vector->napi))) {
2206                 /* would disable interrupts here but EIAM disabled it */
2207                 __napi_schedule(&(q_vector->napi));
2208         }
2209
2210         /*
2211          * re-enable link(maybe) and non-queue interrupts, no flush.
2212          * ixgbe_poll will re-enable the queue interrupts
2213          */
2214
2215         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2216                 ixgbe_irq_enable(adapter, false, false);
2217
2218         return IRQ_HANDLED;
2219 }
2220
2221 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2222 {
2223         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2224         int i;
2225
2226         /* legacy and MSI only use one vector */
2227         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2228                 q_vectors = 1;
2229
2230         for (i = 0; i < adapter->num_rx_queues; i++) {
2231                 adapter->rx_ring[i]->q_vector = NULL;
2232                 adapter->rx_ring[i]->next = NULL;
2233         }
2234         for (i = 0; i < adapter->num_tx_queues; i++) {
2235                 adapter->tx_ring[i]->q_vector = NULL;
2236                 adapter->tx_ring[i]->next = NULL;
2237         }
2238
2239         for (i = 0; i < q_vectors; i++) {
2240                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2241                 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2242                 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2243         }
2244 }
2245
2246 /**
2247  * ixgbe_request_irq - initialize interrupts
2248  * @adapter: board private structure
2249  *
2250  * Attempts to configure interrupts using the best available
2251  * capabilities of the hardware and kernel.
2252  **/
2253 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2254 {
2255         struct net_device *netdev = adapter->netdev;
2256         int err;
2257
2258         /* map all of the rings to the q_vectors */
2259         ixgbe_map_rings_to_vectors(adapter);
2260
2261         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2262                 err = ixgbe_request_msix_irqs(adapter);
2263         else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2264                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2265                                   netdev->name, adapter);
2266         else
2267                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2268                                   netdev->name, adapter);
2269
2270         if (err) {
2271                 e_err(probe, "request_irq failed, Error %d\n", err);
2272
2273                 /* place q_vectors and rings back into a known good state */
2274                 ixgbe_reset_q_vectors(adapter);
2275         }
2276
2277         return err;
2278 }
2279
2280 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2281 {
2282         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2283                 int i, q_vectors;
2284
2285                 q_vectors = adapter->num_msix_vectors;
2286                 i = q_vectors - 1;
2287                 free_irq(adapter->msix_entries[i].vector, adapter);
2288                 i--;
2289
2290                 for (; i >= 0; i--) {
2291                         /* free only the irqs that were actually requested */
2292                         if (!adapter->q_vector[i]->rx.ring &&
2293                             !adapter->q_vector[i]->tx.ring)
2294                                 continue;
2295
2296                         /* clear the affinity_mask in the IRQ descriptor */
2297                         irq_set_affinity_hint(adapter->msix_entries[i].vector,
2298                                               NULL);
2299
2300                         free_irq(adapter->msix_entries[i].vector,
2301                                  adapter->q_vector[i]);
2302                 }
2303         } else {
2304                 free_irq(adapter->pdev->irq, adapter);
2305         }
2306
2307         /* clear q_vector state information */
2308         ixgbe_reset_q_vectors(adapter);
2309 }
2310
2311 /**
2312  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2313  * @adapter: board private structure
2314  **/
2315 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2316 {
2317         switch (adapter->hw.mac.type) {
2318         case ixgbe_mac_82598EB:
2319                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2320                 break;
2321         case ixgbe_mac_82599EB:
2322         case ixgbe_mac_X540:
2323                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2324                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2325                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2326                 break;
2327         default:
2328                 break;
2329         }
2330         IXGBE_WRITE_FLUSH(&adapter->hw);
2331         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2332                 int i;
2333                 for (i = 0; i < adapter->num_msix_vectors; i++)
2334                         synchronize_irq(adapter->msix_entries[i].vector);
2335         } else {
2336                 synchronize_irq(adapter->pdev->irq);
2337         }
2338 }
2339
2340 /**
2341  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2342  *
2343  **/
2344 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2345 {
2346         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2347
2348         /* rx/tx vector */
2349         if (adapter->rx_itr_setting == 1)
2350                 q_vector->itr = IXGBE_20K_ITR;
2351         else
2352                 q_vector->itr = adapter->rx_itr_setting;
2353
2354         ixgbe_write_eitr(q_vector);
2355
2356         ixgbe_set_ivar(adapter, 0, 0, 0);
2357         ixgbe_set_ivar(adapter, 1, 0, 0);
2358
2359         e_info(hw, "Legacy interrupt IVAR setup done\n");
2360 }
2361
2362 /**
2363  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2364  * @adapter: board private structure
2365  * @ring: structure containing ring specific data
2366  *
2367  * Configure the Tx descriptor ring after a reset.
2368  **/
2369 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2370                              struct ixgbe_ring *ring)
2371 {
2372         struct ixgbe_hw *hw = &adapter->hw;
2373         u64 tdba = ring->dma;
2374         int wait_loop = 10;
2375         u32 txdctl = IXGBE_TXDCTL_ENABLE;
2376         u8 reg_idx = ring->reg_idx;
2377
2378         /* disable queue to avoid issues while updating state */
2379         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2380         IXGBE_WRITE_FLUSH(hw);
2381
2382         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2383                         (tdba & DMA_BIT_MASK(32)));
2384         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2385         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2386                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2387         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2388         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2389         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2390
2391         /*
2392          * set WTHRESH to encourage burst writeback, it should not be set
2393          * higher than 1 when ITR is 0 as it could cause false TX hangs
2394          *
2395          * In order to avoid issues WTHRESH + PTHRESH should always be equal
2396          * to or less than the number of on chip descriptors, which is
2397          * currently 40.
2398          */
2399         if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2400                 txdctl |= (1 << 16);    /* WTHRESH = 1 */
2401         else
2402                 txdctl |= (8 << 16);    /* WTHRESH = 8 */
2403
2404         /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2405         txdctl |= (1 << 8) |    /* HTHRESH = 1 */
2406                    32;          /* PTHRESH = 32 */
2407
2408         /* reinitialize flowdirector state */
2409         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2410             adapter->atr_sample_rate) {
2411                 ring->atr_sample_rate = adapter->atr_sample_rate;
2412                 ring->atr_count = 0;
2413                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2414         } else {
2415                 ring->atr_sample_rate = 0;
2416         }
2417
2418         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2419
2420         /* enable queue */
2421         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2422
2423         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2424         if (hw->mac.type == ixgbe_mac_82598EB &&
2425             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2426                 return;
2427
2428         /* poll to verify queue is enabled */
2429         do {
2430                 usleep_range(1000, 2000);
2431                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2432         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2433         if (!wait_loop)
2434                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2435 }
2436
2437 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2438 {
2439         struct ixgbe_hw *hw = &adapter->hw;
2440         u32 rttdcs;
2441         u32 reg;
2442         u8 tcs = netdev_get_num_tc(adapter->netdev);
2443
2444         if (hw->mac.type == ixgbe_mac_82598EB)
2445                 return;
2446
2447         /* disable the arbiter while setting MTQC */
2448         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2449         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2450         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2451
2452         /* set transmit pool layout */
2453         switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2454         case (IXGBE_FLAG_SRIOV_ENABLED):
2455                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2456                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2457                 break;
2458         default:
2459                 if (!tcs)
2460                         reg = IXGBE_MTQC_64Q_1PB;
2461                 else if (tcs <= 4)
2462                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2463                 else
2464                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2465
2466                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2467
2468                 /* Enable Security TX Buffer IFG for multiple pb */
2469                 if (tcs) {
2470                         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2471                         reg |= IXGBE_SECTX_DCB;
2472                         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2473                 }
2474                 break;
2475         }
2476
2477         /* re-enable the arbiter */
2478         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2479         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2480 }
2481
2482 /**
2483  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2484  * @adapter: board private structure
2485  *
2486  * Configure the Tx unit of the MAC after a reset.
2487  **/
2488 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2489 {
2490         struct ixgbe_hw *hw = &adapter->hw;
2491         u32 dmatxctl;
2492         u32 i;
2493
2494         ixgbe_setup_mtqc(adapter);
2495
2496         if (hw->mac.type != ixgbe_mac_82598EB) {
2497                 /* DMATXCTL.EN must be before Tx queues are enabled */
2498                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2499                 dmatxctl |= IXGBE_DMATXCTL_TE;
2500                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2501         }
2502
2503         /* Setup the HW Tx Head and Tail descriptor pointers */
2504         for (i = 0; i < adapter->num_tx_queues; i++)
2505                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2506 }
2507
2508 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2509
2510 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2511                                    struct ixgbe_ring *rx_ring)
2512 {
2513         u32 srrctl;
2514         u8 reg_idx = rx_ring->reg_idx;
2515
2516         switch (adapter->hw.mac.type) {
2517         case ixgbe_mac_82598EB: {
2518                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2519                 const int mask = feature[RING_F_RSS].mask;
2520                 reg_idx = reg_idx & mask;
2521         }
2522                 break;
2523         case ixgbe_mac_82599EB:
2524         case ixgbe_mac_X540:
2525         default:
2526                 break;
2527         }
2528
2529         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2530
2531         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2532         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2533         if (adapter->num_vfs)
2534                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2535
2536         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2537                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2538
2539         if (ring_is_ps_enabled(rx_ring)) {
2540 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2541                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2542 #else
2543                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2544 #endif
2545                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2546         } else {
2547                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2548                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2549                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2550         }
2551
2552         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2553 }
2554
2555 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2556 {
2557         struct ixgbe_hw *hw = &adapter->hw;
2558         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2559                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2560                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2561         u32 mrqc = 0, reta = 0;
2562         u32 rxcsum;
2563         int i, j;
2564         u8 tcs = netdev_get_num_tc(adapter->netdev);
2565         int maxq = adapter->ring_feature[RING_F_RSS].indices;
2566
2567         if (tcs)
2568                 maxq = min(maxq, adapter->num_tx_queues / tcs);
2569
2570         /* Fill out hash function seeds */
2571         for (i = 0; i < 10; i++)
2572                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2573
2574         /* Fill out redirection table */
2575         for (i = 0, j = 0; i < 128; i++, j++) {
2576                 if (j == maxq)
2577                         j = 0;
2578                 /* reta = 4-byte sliding window of
2579                  * 0x00..(indices-1)(indices-1)00..etc. */
2580                 reta = (reta << 8) | (j * 0x11);
2581                 if ((i & 3) == 3)
2582                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2583         }
2584
2585         /* Disable indicating checksum in descriptor, enables RSS hash */
2586         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2587         rxcsum |= IXGBE_RXCSUM_PCSD;
2588         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2589
2590         if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2591             (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2592                 mrqc = IXGBE_MRQC_RSSEN;
2593         } else {
2594                 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2595                                              | IXGBE_FLAG_SRIOV_ENABLED);
2596
2597                 switch (mask) {
2598                 case (IXGBE_FLAG_RSS_ENABLED):
2599                         if (!tcs)
2600                                 mrqc = IXGBE_MRQC_RSSEN;
2601                         else if (tcs <= 4)
2602                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2603                         else
2604                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2605                         break;
2606                 case (IXGBE_FLAG_SRIOV_ENABLED):
2607                         mrqc = IXGBE_MRQC_VMDQEN;
2608                         break;
2609                 default:
2610                         break;
2611                 }
2612         }
2613
2614         /* Perform hash on these packet types */
2615         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2616               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2617               | IXGBE_MRQC_RSS_FIELD_IPV6
2618               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2619
2620         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2621 }
2622
2623 /**
2624  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2625  * @adapter:    address of board private structure
2626  * @index:      index of ring to set
2627  **/
2628 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2629                                    struct ixgbe_ring *ring)
2630 {
2631         struct ixgbe_hw *hw = &adapter->hw;
2632         u32 rscctrl;
2633         int rx_buf_len;
2634         u8 reg_idx = ring->reg_idx;
2635
2636         if (!ring_is_rsc_enabled(ring))
2637                 return;
2638
2639         rx_buf_len = ring->rx_buf_len;
2640         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2641         rscctrl |= IXGBE_RSCCTL_RSCEN;
2642         /*
2643          * we must limit the number of descriptors so that the
2644          * total size of max desc * buf_len is not greater
2645          * than 65535
2646          */
2647         if (ring_is_ps_enabled(ring)) {
2648 #if (MAX_SKB_FRAGS > 16)
2649                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2650 #elif (MAX_SKB_FRAGS > 8)
2651                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2652 #elif (MAX_SKB_FRAGS > 4)
2653                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2654 #else
2655                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2656 #endif
2657         } else {
2658                 if (rx_buf_len < IXGBE_RXBUFFER_4K)
2659                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2660                 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
2661                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2662                 else
2663                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2664         }
2665         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2666 }
2667
2668 /**
2669  *  ixgbe_set_uta - Set unicast filter table address
2670  *  @adapter: board private structure
2671  *
2672  *  The unicast table address is a register array of 32-bit registers.
2673  *  The table is meant to be used in a way similar to how the MTA is used
2674  *  however due to certain limitations in the hardware it is necessary to
2675  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2676  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2677  **/
2678 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2679 {
2680         struct ixgbe_hw *hw = &adapter->hw;
2681         int i;
2682
2683         /* The UTA table only exists on 82599 hardware and newer */
2684         if (hw->mac.type < ixgbe_mac_82599EB)
2685                 return;
2686
2687         /* we only need to do this if VMDq is enabled */
2688         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2689                 return;
2690
2691         for (i = 0; i < 128; i++)
2692                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2693 }
2694
2695 #define IXGBE_MAX_RX_DESC_POLL 10
2696 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2697                                        struct ixgbe_ring *ring)
2698 {
2699         struct ixgbe_hw *hw = &adapter->hw;
2700         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2701         u32 rxdctl;
2702         u8 reg_idx = ring->reg_idx;
2703
2704         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2705         if (hw->mac.type == ixgbe_mac_82598EB &&
2706             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2707                 return;
2708
2709         do {
2710                 usleep_range(1000, 2000);
2711                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2712         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2713
2714         if (!wait_loop) {
2715                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2716                       "the polling period\n", reg_idx);
2717         }
2718 }
2719
2720 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2721                             struct ixgbe_ring *ring)
2722 {
2723         struct ixgbe_hw *hw = &adapter->hw;
2724         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2725         u32 rxdctl;
2726         u8 reg_idx = ring->reg_idx;
2727
2728         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2729         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2730
2731         /* write value back with RXDCTL.ENABLE bit cleared */
2732         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2733
2734         if (hw->mac.type == ixgbe_mac_82598EB &&
2735             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2736                 return;
2737
2738         /* the hardware may take up to 100us to really disable the rx queue */
2739         do {
2740                 udelay(10);
2741                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2742         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2743
2744         if (!wait_loop) {
2745                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2746                       "the polling period\n", reg_idx);
2747         }
2748 }
2749
2750 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2751                              struct ixgbe_ring *ring)
2752 {
2753         struct ixgbe_hw *hw = &adapter->hw;
2754         u64 rdba = ring->dma;
2755         u32 rxdctl;
2756         u8 reg_idx = ring->reg_idx;
2757
2758         /* disable queue to avoid issues while updating state */
2759         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2760         ixgbe_disable_rx_queue(adapter, ring);
2761
2762         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2763         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2764         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2765                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2766         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2767         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2768         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2769
2770         ixgbe_configure_srrctl(adapter, ring);
2771         ixgbe_configure_rscctl(adapter, ring);
2772
2773         /* If operating in IOV mode set RLPML for X540 */
2774         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2775             hw->mac.type == ixgbe_mac_X540) {
2776                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2777                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2778                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2779         }
2780
2781         if (hw->mac.type == ixgbe_mac_82598EB) {
2782                 /*
2783                  * enable cache line friendly hardware writes:
2784                  * PTHRESH=32 descriptors (half the internal cache),
2785                  * this also removes ugly rx_no_buffer_count increment
2786                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2787                  * WTHRESH=8 burst writeback up to two cache lines
2788                  */
2789                 rxdctl &= ~0x3FFFFF;
2790                 rxdctl |=  0x080420;
2791         }
2792
2793         /* enable receive descriptor ring */
2794         rxdctl |= IXGBE_RXDCTL_ENABLE;
2795         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2796
2797         ixgbe_rx_desc_queue_enable(adapter, ring);
2798         ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2799 }
2800
2801 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2802 {
2803         struct ixgbe_hw *hw = &adapter->hw;
2804         int p;
2805
2806         /* PSRTYPE must be initialized in non 82598 adapters */
2807         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2808                       IXGBE_PSRTYPE_UDPHDR |
2809                       IXGBE_PSRTYPE_IPV4HDR |
2810                       IXGBE_PSRTYPE_L2HDR |
2811                       IXGBE_PSRTYPE_IPV6HDR;
2812
2813         if (hw->mac.type == ixgbe_mac_82598EB)
2814                 return;
2815
2816         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2817                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2818
2819         for (p = 0; p < adapter->num_rx_pools; p++)
2820                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2821                                 psrtype);
2822 }
2823
2824 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2825 {
2826         struct ixgbe_hw *hw = &adapter->hw;
2827         u32 gcr_ext;
2828         u32 vt_reg_bits;
2829         u32 reg_offset, vf_shift;
2830         u32 vmdctl;
2831         int i;
2832
2833         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2834                 return;
2835
2836         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2837         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2838         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2839         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2840
2841         vf_shift = adapter->num_vfs % 32;
2842         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2843
2844         /* Enable only the PF's pool for Tx/Rx */
2845         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2846         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2847         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2848         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2849         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2850
2851         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2852         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2853
2854         /*
2855          * Set up VF register offsets for selected VT Mode,
2856          * i.e. 32 or 64 VFs for SR-IOV
2857          */
2858         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2859         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2860         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2861         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2862
2863         /* enable Tx loopback for VF/PF communication */
2864         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2865         /* Enable MAC Anti-Spoofing */
2866         hw->mac.ops.set_mac_anti_spoofing(hw,
2867                                            (adapter->num_vfs != 0),
2868                                           adapter->num_vfs);
2869         /* For VFs that have spoof checking turned off */
2870         for (i = 0; i < adapter->num_vfs; i++) {
2871                 if (!adapter->vfinfo[i].spoofchk_enabled)
2872                         ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
2873         }
2874 }
2875
2876 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2877 {
2878         struct ixgbe_hw *hw = &adapter->hw;
2879         struct net_device *netdev = adapter->netdev;
2880         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2881         int rx_buf_len;
2882         struct ixgbe_ring *rx_ring;
2883         int i;
2884         u32 mhadd, hlreg0;
2885
2886         /* Decide whether to use packet split mode or not */
2887         /* On by default */
2888         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2889
2890         /* Do not use packet split if we're in SR-IOV Mode */
2891         if (adapter->num_vfs)
2892                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2893
2894         /* Disable packet split due to 82599 erratum #45 */
2895         if (hw->mac.type == ixgbe_mac_82599EB)
2896                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2897
2898 #ifdef IXGBE_FCOE
2899         /* adjust max frame to be able to do baby jumbo for FCoE */
2900         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2901             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2902                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2903
2904 #endif /* IXGBE_FCOE */
2905         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2906         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2907                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2908                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2909
2910                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2911         }
2912
2913         /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2914         max_frame += VLAN_HLEN;
2915
2916         /* Set the RX buffer length according to the mode */
2917         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2918                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2919         } else {
2920                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2921                     (netdev->mtu <= ETH_DATA_LEN))
2922                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2923                 /*
2924                  * Make best use of allocation by using all but 1K of a
2925                  * power of 2 allocation that will be used for skb->head.
2926                  */
2927                 else if (max_frame <= IXGBE_RXBUFFER_3K)
2928                         rx_buf_len = IXGBE_RXBUFFER_3K;
2929                 else if (max_frame <= IXGBE_RXBUFFER_7K)
2930                         rx_buf_len = IXGBE_RXBUFFER_7K;
2931                 else if (max_frame <= IXGBE_RXBUFFER_15K)
2932                         rx_buf_len = IXGBE_RXBUFFER_15K;
2933                 else
2934                         rx_buf_len = IXGBE_MAX_RXBUFFER;
2935         }
2936
2937         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2938         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2939         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2940         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2941
2942         /*
2943          * Setup the HW Rx Head and Tail Descriptor Pointers and
2944          * the Base and Length of the Rx Descriptor Ring
2945          */
2946         for (i = 0; i < adapter->num_rx_queues; i++) {
2947                 rx_ring = adapter->rx_ring[i];
2948                 rx_ring->rx_buf_len = rx_buf_len;
2949
2950                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2951                         set_ring_ps_enabled(rx_ring);
2952                 else
2953                         clear_ring_ps_enabled(rx_ring);
2954
2955                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2956                         set_ring_rsc_enabled(rx_ring);
2957                 else
2958                         clear_ring_rsc_enabled(rx_ring);
2959
2960 #ifdef IXGBE_FCOE
2961                 if (netdev->features & NETIF_F_FCOE_MTU) {
2962                         struct ixgbe_ring_feature *f;
2963                         f = &adapter->ring_feature[RING_F_FCOE];
2964                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2965                                 clear_ring_ps_enabled(rx_ring);
2966                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2967                                         rx_ring->rx_buf_len =
2968                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2969                         } else if (!ring_is_rsc_enabled(rx_ring) &&
2970                                    !ring_is_ps_enabled(rx_ring)) {
2971                                 rx_ring->rx_buf_len =
2972                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2973                         }
2974                 }
2975 #endif /* IXGBE_FCOE */
2976         }
2977 }
2978
2979 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2980 {
2981         struct ixgbe_hw *hw = &adapter->hw;
2982         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2983
2984         switch (hw->mac.type) {
2985         case ixgbe_mac_82598EB:
2986                 /*
2987                  * For VMDq support of different descriptor types or
2988                  * buffer sizes through the use of multiple SRRCTL
2989                  * registers, RDRXCTL.MVMEN must be set to 1
2990                  *
2991                  * also, the manual doesn't mention it clearly but DCA hints
2992                  * will only use queue 0's tags unless this bit is set.  Side
2993                  * effects of setting this bit are only that SRRCTL must be
2994                  * fully programmed [0..15]
2995                  */
2996                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2997                 break;
2998         case ixgbe_mac_82599EB:
2999         case ixgbe_mac_X540:
3000                 /* Disable RSC for ACK packets */
3001                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3002                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3003                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3004                 /* hardware requires some bits to be set by default */
3005                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3006                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3007                 break;
3008         default:
3009                 /* We should do nothing since we don't know this hardware */
3010                 return;
3011         }
3012
3013         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3014 }
3015
3016 /**
3017  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3018  * @adapter: board private structure
3019  *
3020  * Configure the Rx unit of the MAC after a reset.
3021  **/
3022 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3023 {
3024         struct ixgbe_hw *hw = &adapter->hw;
3025         int i;
3026         u32 rxctrl;
3027
3028         /* disable receives while setting up the descriptors */
3029         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3030         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3031
3032         ixgbe_setup_psrtype(adapter);
3033         ixgbe_setup_rdrxctl(adapter);
3034
3035         /* Program registers for the distribution of queues */
3036         ixgbe_setup_mrqc(adapter);
3037
3038         ixgbe_set_uta(adapter);
3039
3040         /* set_rx_buffer_len must be called before ring initialization */
3041         ixgbe_set_rx_buffer_len(adapter);
3042
3043         /*
3044          * Setup the HW Rx Head and Tail Descriptor Pointers and
3045          * the Base and Length of the Rx Descriptor Ring
3046          */
3047         for (i = 0; i < adapter->num_rx_queues; i++)
3048                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3049
3050         /* disable drop enable for 82598 parts */
3051         if (hw->mac.type == ixgbe_mac_82598EB)
3052                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3053
3054         /* enable all receives */
3055         rxctrl |= IXGBE_RXCTRL_RXEN;
3056         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3057 }
3058
3059 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3060 {
3061         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3062         struct ixgbe_hw *hw = &adapter->hw;
3063         int pool_ndx = adapter->num_vfs;
3064
3065         /* add VID to filter table */
3066         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3067         set_bit(vid, adapter->active_vlans);
3068 }
3069
3070 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3071 {
3072         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3073         struct ixgbe_hw *hw = &adapter->hw;
3074         int pool_ndx = adapter->num_vfs;
3075
3076         /* remove VID from filter table */
3077         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3078         clear_bit(vid, adapter->active_vlans);
3079 }
3080
3081 /**
3082  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3083  * @adapter: driver data
3084  */
3085 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3086 {
3087         struct ixgbe_hw *hw = &adapter->hw;
3088         u32 vlnctrl;
3089
3090         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3091         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3092         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3093 }
3094
3095 /**
3096  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3097  * @adapter: driver data
3098  */
3099 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3100 {
3101         struct ixgbe_hw *hw = &adapter->hw;
3102         u32 vlnctrl;
3103
3104         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3105         vlnctrl |= IXGBE_VLNCTRL_VFE;
3106         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3107         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3108 }
3109
3110 /**
3111  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3112  * @adapter: driver data
3113  */
3114 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3115 {
3116         struct ixgbe_hw *hw = &adapter->hw;
3117         u32 vlnctrl;
3118         int i, j;
3119
3120         switch (hw->mac.type) {
3121         case ixgbe_mac_82598EB:
3122                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3123                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3124                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3125                 break;
3126         case ixgbe_mac_82599EB:
3127         case ixgbe_mac_X540:
3128                 for (i = 0; i < adapter->num_rx_queues; i++) {
3129                         j = adapter->rx_ring[i]->reg_idx;
3130                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3131                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3132                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3133                 }
3134                 break;
3135         default:
3136                 break;
3137         }
3138 }
3139
3140 /**
3141  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3142  * @adapter: driver data
3143  */
3144 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3145 {
3146         struct ixgbe_hw *hw = &adapter->hw;
3147         u32 vlnctrl;
3148         int i, j;
3149
3150         switch (hw->mac.type) {
3151         case ixgbe_mac_82598EB:
3152                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3153                 vlnctrl |= IXGBE_VLNCTRL_VME;
3154                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3155                 break;
3156         case ixgbe_mac_82599EB:
3157         case ixgbe_mac_X540:
3158                 for (i = 0; i < adapter->num_rx_queues; i++) {
3159                         j = adapter->rx_ring[i]->reg_idx;
3160                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3161                         vlnctrl |= IXGBE_RXDCTL_VME;
3162                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3163                 }
3164                 break;
3165         default:
3166                 break;
3167         }
3168 }
3169
3170 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3171 {
3172         u16 vid;
3173
3174         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3175
3176         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3177                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3178 }
3179
3180 /**
3181  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3182  * @netdev: network interface device structure
3183  *
3184  * Writes unicast address list to the RAR table.
3185  * Returns: -ENOMEM on failure/insufficient address space
3186  *                0 on no addresses written
3187  *                X on writing X addresses to the RAR table
3188  **/
3189 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3190 {
3191         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3192         struct ixgbe_hw *hw = &adapter->hw;
3193         unsigned int vfn = adapter->num_vfs;
3194         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3195         int count = 0;
3196
3197         /* return ENOMEM indicating insufficient memory for addresses */
3198         if (netdev_uc_count(netdev) > rar_entries)
3199                 return -ENOMEM;
3200
3201         if (!netdev_uc_empty(netdev) && rar_entries) {
3202                 struct netdev_hw_addr *ha;
3203                 /* return error if we do not support writing to RAR table */
3204                 if (!hw->mac.ops.set_rar)
3205                         return -ENOMEM;
3206
3207                 netdev_for_each_uc_addr(ha, netdev) {
3208                         if (!rar_entries)
3209                                 break;
3210                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3211                                             vfn, IXGBE_RAH_AV);
3212                         count++;
3213                 }
3214         }
3215         /* write the addresses in reverse order to avoid write combining */
3216         for (; rar_entries > 0 ; rar_entries--)
3217                 hw->mac.ops.clear_rar(hw, rar_entries);
3218
3219         return count;
3220 }
3221
3222 /**
3223  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3224  * @netdev: network interface device structure
3225  *
3226  * The set_rx_method entry point is called whenever the unicast/multicast
3227  * address list or the network interface flags are updated.  This routine is
3228  * responsible for configuring the hardware for proper unicast, multicast and
3229  * promiscuous mode.
3230  **/
3231 void ixgbe_set_rx_mode(struct net_device *netdev)
3232 {
3233         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3234         struct ixgbe_hw *hw = &adapter->hw;
3235         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3236         int count;
3237
3238         /* Check for Promiscuous and All Multicast modes */
3239
3240         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3241
3242         /* set all bits that we expect to always be set */
3243         fctrl |= IXGBE_FCTRL_BAM;
3244         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3245         fctrl |= IXGBE_FCTRL_PMCF;
3246
3247         /* clear the bits we are changing the status of */
3248         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3249
3250         if (netdev->flags & IFF_PROMISC) {
3251                 hw->addr_ctrl.user_set_promisc = true;
3252                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3253                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3254                 /* don't hardware filter vlans in promisc mode */
3255                 ixgbe_vlan_filter_disable(adapter);
3256         } else {
3257                 if (netdev->flags & IFF_ALLMULTI) {
3258                         fctrl |= IXGBE_FCTRL_MPE;
3259                         vmolr |= IXGBE_VMOLR_MPE;
3260                 } else {
3261                         /*
3262                          * Write addresses to the MTA, if the attempt fails
3263                          * then we should just turn on promiscuous mode so
3264                          * that we can at least receive multicast traffic
3265                          */
3266                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3267                         vmolr |= IXGBE_VMOLR_ROMPE;
3268                 }
3269                 ixgbe_vlan_filter_enable(adapter);
3270                 hw->addr_ctrl.user_set_promisc = false;
3271                 /*
3272                  * Write addresses to available RAR registers, if there is not
3273                  * sufficient space to store all the addresses then enable
3274                  * unicast promiscuous mode
3275                  */
3276                 count = ixgbe_write_uc_addr_list(netdev);
3277                 if (count < 0) {
3278                         fctrl |= IXGBE_FCTRL_UPE;
3279                         vmolr |= IXGBE_VMOLR_ROPE;
3280                 }
3281         }
3282
3283         if (adapter->num_vfs) {
3284                 ixgbe_restore_vf_multicasts(adapter);
3285                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3286                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3287                            IXGBE_VMOLR_ROPE);
3288                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3289         }
3290
3291         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3292
3293         if (netdev->features & NETIF_F_HW_VLAN_RX)
3294                 ixgbe_vlan_strip_enable(adapter);
3295         else
3296                 ixgbe_vlan_strip_disable(adapter);
3297 }
3298
3299 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3300 {
3301         int q_idx;
3302         struct ixgbe_q_vector *q_vector;
3303         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3304
3305         /* legacy and MSI only use one vector */
3306         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3307                 q_vectors = 1;
3308
3309         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3310                 q_vector = adapter->q_vector[q_idx];
3311                 napi_enable(&q_vector->napi);
3312         }
3313 }
3314
3315 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3316 {
3317         int q_idx;
3318         struct ixgbe_q_vector *q_vector;
3319         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3320
3321         /* legacy and MSI only use one vector */
3322         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3323                 q_vectors = 1;
3324
3325         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3326                 q_vector = adapter->q_vector[q_idx];
3327                 napi_disable(&q_vector->napi);
3328         }
3329 }
3330
3331 #ifdef CONFIG_IXGBE_DCB
3332 /*
3333  * ixgbe_configure_dcb - Configure DCB hardware
3334  * @adapter: ixgbe adapter struct
3335  *
3336  * This is called by the driver on open to configure the DCB hardware.
3337  * This is also called by the gennetlink interface when reconfiguring
3338  * the DCB state.
3339  */
3340 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3341 {
3342         struct ixgbe_hw *hw = &adapter->hw;
3343         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3344
3345         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3346                 if (hw->mac.type == ixgbe_mac_82598EB)
3347                         netif_set_gso_max_size(adapter->netdev, 65536);
3348                 return;
3349         }
3350
3351         if (hw->mac.type == ixgbe_mac_82598EB)
3352                 netif_set_gso_max_size(adapter->netdev, 32768);
3353
3354
3355         /* Enable VLAN tag insert/strip */
3356         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3357
3358         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3359
3360 #ifdef IXGBE_FCOE
3361         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3362                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3363 #endif
3364
3365         /* reconfigure the hardware */
3366         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3367                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3368                                                 DCB_TX_CONFIG);
3369                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3370                                                 DCB_RX_CONFIG);
3371                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3372         } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3373                 ixgbe_dcb_hw_ets(&adapter->hw,
3374                                  adapter->ixgbe_ieee_ets,
3375                                  max_frame);
3376                 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3377                                         adapter->ixgbe_ieee_pfc->pfc_en,
3378                                         adapter->ixgbe_ieee_ets->prio_tc);
3379         }
3380
3381         /* Enable RSS Hash per TC */
3382         if (hw->mac.type != ixgbe_mac_82598EB) {
3383                 int i;
3384                 u32 reg = 0;
3385
3386                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3387                         u8 msb = 0;
3388                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3389
3390                         while (cnt >>= 1)
3391                                 msb++;
3392
3393                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3394                 }
3395                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3396         }
3397 }
3398 #endif
3399
3400 /* Additional bittime to account for IXGBE framing */
3401 #define IXGBE_ETH_FRAMING 20
3402
3403 /*
3404  * ixgbe_hpbthresh - calculate high water mark for flow control
3405  *
3406  * @adapter: board private structure to calculate for
3407  * @pb - packet buffer to calculate
3408  */
3409 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3410 {
3411         struct ixgbe_hw *hw = &adapter->hw;
3412         struct net_device *dev = adapter->netdev;
3413         int link, tc, kb, marker;
3414         u32 dv_id, rx_pba;
3415
3416         /* Calculate max LAN frame size */
3417         tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3418
3419 #ifdef IXGBE_FCOE
3420         /* FCoE traffic class uses FCOE jumbo frames */
3421         if (dev->features & NETIF_F_FCOE_MTU) {
3422                 int fcoe_pb = 0;
3423
3424 #ifdef CONFIG_IXGBE_DCB
3425                 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3426
3427 #endif
3428                 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3429                         tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3430         }
3431 #endif
3432
3433         /* Calculate delay value for device */
3434         switch (hw->mac.type) {
3435         case ixgbe_mac_X540:
3436                 dv_id = IXGBE_DV_X540(link, tc);
3437                 break;
3438         default:
3439                 dv_id = IXGBE_DV(link, tc);
3440                 break;
3441         }
3442
3443         /* Loopback switch introduces additional latency */
3444         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3445                 dv_id += IXGBE_B2BT(tc);
3446
3447         /* Delay value is calculated in bit times convert to KB */
3448         kb = IXGBE_BT2KB(dv_id);
3449         rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3450
3451         marker = rx_pba - kb;
3452
3453         /* It is possible that the packet buffer is not large enough
3454          * to provide required headroom. In this case throw an error
3455          * to user and a do the best we can.
3456          */
3457         if (marker < 0) {
3458                 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3459                             "headroom to support flow control."
3460                             "Decrease MTU or number of traffic classes\n", pb);
3461                 marker = tc + 1;
3462         }
3463
3464         return marker;
3465 }
3466
3467 /*
3468  * ixgbe_lpbthresh - calculate low water mark for for flow control
3469  *
3470  * @adapter: board private structure to calculate for
3471  * @pb - packet buffer to calculate
3472  */
3473 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3474 {
3475         struct ixgbe_hw *hw = &adapter->hw;
3476         struct net_device *dev = adapter->netdev;
3477         int tc;
3478         u32 dv_id;
3479
3480         /* Calculate max LAN frame size */
3481         tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3482
3483         /* Calculate delay value for device */
3484         switch (hw->mac.type) {
3485         case ixgbe_mac_X540:
3486                 dv_id = IXGBE_LOW_DV_X540(tc);
3487                 break;
3488         default:
3489                 dv_id = IXGBE_LOW_DV(tc);
3490                 break;
3491         }
3492
3493         /* Delay value is calculated in bit times convert to KB */
3494         return IXGBE_BT2KB(dv_id);
3495 }
3496
3497 /*
3498  * ixgbe_pbthresh_setup - calculate and setup high low water marks
3499  */
3500 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3501 {
3502         struct ixgbe_hw *hw = &adapter->hw;
3503         int num_tc = netdev_get_num_tc(adapter->netdev);
3504         int i;
3505
3506         if (!num_tc)
3507                 num_tc = 1;
3508
3509         hw->fc.low_water = ixgbe_lpbthresh(adapter);
3510
3511         for (i = 0; i < num_tc; i++) {
3512                 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3513
3514                 /* Low water marks must not be larger than high water marks */
3515                 if (hw->fc.low_water > hw->fc.high_water[i])
3516                         hw->fc.low_water = 0;
3517         }
3518 }
3519
3520 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3521 {
3522         struct ixgbe_hw *hw = &adapter->hw;
3523         int hdrm;
3524         u8 tc = netdev_get_num_tc(adapter->netdev);
3525
3526         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3527             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3528                 hdrm = 32 << adapter->fdir_pballoc;
3529         else
3530                 hdrm = 0;
3531
3532         hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3533         ixgbe_pbthresh_setup(adapter);
3534 }
3535
3536 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3537 {
3538         struct ixgbe_hw *hw = &adapter->hw;
3539         struct hlist_node *node, *node2;
3540         struct ixgbe_fdir_filter *filter;
3541
3542         spin_lock(&adapter->fdir_perfect_lock);
3543
3544         if (!hlist_empty(&adapter->fdir_filter_list))
3545                 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3546
3547         hlist_for_each_entry_safe(filter, node, node2,
3548                                   &adapter->fdir_filter_list, fdir_node) {
3549                 ixgbe_fdir_write_perfect_filter_82599(hw,
3550                                 &filter->filter,
3551                                 filter->sw_idx,
3552                                 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3553                                 IXGBE_FDIR_DROP_QUEUE :
3554                                 adapter->rx_ring[filter->action]->reg_idx);
3555         }
3556
3557         spin_unlock(&adapter->fdir_perfect_lock);
3558 }
3559
3560 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3561 {
3562         ixgbe_configure_pb(adapter);
3563 #ifdef CONFIG_IXGBE_DCB
3564         ixgbe_configure_dcb(adapter);
3565 #endif
3566
3567         ixgbe_set_rx_mode(adapter->netdev);
3568         ixgbe_restore_vlan(adapter);
3569
3570 #ifdef IXGBE_FCOE
3571         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3572                 ixgbe_configure_fcoe(adapter);
3573
3574 #endif /* IXGBE_FCOE */
3575         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3576                 ixgbe_init_fdir_signature_82599(&adapter->hw,
3577                                                 adapter->fdir_pballoc);
3578         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3579                 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3580                                               adapter->fdir_pballoc);
3581                 ixgbe_fdir_filter_restore(adapter);
3582         }
3583
3584         ixgbe_configure_virtualization(adapter);
3585
3586         ixgbe_configure_tx(adapter);
3587         ixgbe_configure_rx(adapter);
3588 }
3589
3590 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3591 {
3592         switch (hw->phy.type) {
3593         case ixgbe_phy_sfp_avago:
3594         case ixgbe_phy_sfp_ftl:
3595         case ixgbe_phy_sfp_intel:
3596         case ixgbe_phy_sfp_unknown:
3597         case ixgbe_phy_sfp_passive_tyco:
3598         case ixgbe_phy_sfp_passive_unknown:
3599         case ixgbe_phy_sfp_active_unknown:
3600         case ixgbe_phy_sfp_ftl_active:
3601                 return true;
3602         case ixgbe_phy_nl:
3603                 if (hw->mac.type == ixgbe_mac_82598EB)
3604                         return true;
3605         default:
3606                 return false;
3607         }
3608 }
3609
3610 /**
3611  * ixgbe_sfp_link_config - set up SFP+ link
3612  * @adapter: pointer to private adapter struct
3613  **/
3614 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3615 {
3616         /*
3617          * We are assuming the worst case scenerio here, and that
3618          * is that an SFP was inserted/removed after the reset
3619          * but before SFP detection was enabled.  As such the best
3620          * solution is to just start searching as soon as we start
3621          */
3622         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3623                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3624
3625         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3626 }
3627
3628 /**
3629  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3630  * @hw: pointer to private hardware struct
3631  *
3632  * Returns 0 on success, negative on failure
3633  **/
3634 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3635 {
3636         u32 autoneg;
3637         bool negotiation, link_up = false;
3638         u32 ret = IXGBE_ERR_LINK_SETUP;
3639
3640         if (hw->mac.ops.check_link)
3641                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3642
3643         if (ret)
3644                 goto link_cfg_out;
3645
3646         autoneg = hw->phy.autoneg_advertised;
3647         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3648                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3649                                                         &negotiation);
3650         if (ret)
3651                 goto link_cfg_out;
3652
3653         if (hw->mac.ops.setup_link)
3654                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3655 link_cfg_out:
3656         return ret;
3657 }
3658
3659 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3660 {
3661         struct ixgbe_hw *hw = &adapter->hw;
3662         u32 gpie = 0;
3663
3664         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3665                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3666                        IXGBE_GPIE_OCD;
3667                 gpie |= IXGBE_GPIE_EIAME;
3668                 /*
3669                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3670                  * this saves a register write for every interrupt
3671                  */
3672                 switch (hw->mac.type) {
3673                 case ixgbe_mac_82598EB:
3674                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3675                         break;
3676                 case ixgbe_mac_82599EB:
3677                 case ixgbe_mac_X540:
3678                 default:
3679                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3680                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3681                         break;
3682                 }
3683         } else {
3684                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3685                  * specifically only auto mask tx and rx interrupts */
3686                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3687         }
3688
3689         /* XXX: to interrupt immediately for EICS writes, enable this */
3690         /* gpie |= IXGBE_GPIE_EIMEN; */
3691
3692         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3693                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3694                 gpie |= IXGBE_GPIE_VTMODE_64;
3695         }
3696
3697         /* Enable Thermal over heat sensor interrupt */
3698         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3699                 switch (adapter->hw.mac.type) {
3700                 case ixgbe_mac_82599EB:
3701                         gpie |= IXGBE_SDP0_GPIEN;
3702                         break;
3703                 case ixgbe_mac_X540:
3704                         gpie |= IXGBE_EIMS_TS;
3705                         break;
3706                 default:
3707                         break;
3708                 }
3709         }
3710
3711         /* Enable fan failure interrupt */
3712         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3713                 gpie |= IXGBE_SDP1_GPIEN;
3714
3715         if (hw->mac.type == ixgbe_mac_82599EB) {
3716                 gpie |= IXGBE_SDP1_GPIEN;
3717                 gpie |= IXGBE_SDP2_GPIEN;
3718         }
3719
3720         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3721 }
3722
3723 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3724 {
3725         struct ixgbe_hw *hw = &adapter->hw;
3726         int err;
3727         u32 ctrl_ext;
3728
3729         ixgbe_get_hw_control(adapter);
3730         ixgbe_setup_gpie(adapter);
3731
3732         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3733                 ixgbe_configure_msix(adapter);
3734         else
3735                 ixgbe_configure_msi_and_legacy(adapter);
3736
3737         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3738         if (hw->mac.ops.enable_tx_laser &&
3739             ((hw->phy.multispeed_fiber) ||
3740              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3741               (hw->mac.type == ixgbe_mac_82599EB))))
3742                 hw->mac.ops.enable_tx_laser(hw);
3743
3744         clear_bit(__IXGBE_DOWN, &adapter->state);
3745         ixgbe_napi_enable_all(adapter);
3746
3747         if (ixgbe_is_sfp(hw)) {
3748                 ixgbe_sfp_link_config(adapter);
3749         } else {
3750                 err = ixgbe_non_sfp_link_config(hw);
3751                 if (err)
3752                         e_err(probe, "link_config FAILED %d\n", err);
3753         }
3754
3755         /* clear any pending interrupts, may auto mask */
3756         IXGBE_READ_REG(hw, IXGBE_EICR);
3757         ixgbe_irq_enable(adapter, true, true);
3758
3759         /*
3760          * If this adapter has a fan, check to see if we had a failure
3761          * before we enabled the interrupt.
3762          */
3763         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3764                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3765                 if (esdp & IXGBE_ESDP_SDP1)
3766                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3767         }
3768
3769         /* enable transmits */
3770         netif_tx_start_all_queues(adapter->netdev);
3771
3772         /* bring the link up in the watchdog, this could race with our first
3773          * link up interrupt but shouldn't be a problem */
3774         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3775         adapter->link_check_timeout = jiffies;
3776         mod_timer(&adapter->service_timer, jiffies);
3777
3778         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3779         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3780         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3781         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3782 }
3783
3784 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3785 {
3786         WARN_ON(in_interrupt());
3787         /* put off any impending NetWatchDogTimeout */
3788         adapter->netdev->trans_start = jiffies;
3789
3790         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3791                 usleep_range(1000, 2000);
3792         ixgbe_down(adapter);
3793         /*
3794          * If SR-IOV enabled then wait a bit before bringing the adapter
3795          * back up to give the VFs time to respond to the reset.  The
3796          * two second wait is based upon the watchdog timer cycle in
3797          * the VF driver.
3798          */
3799         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3800                 msleep(2000);
3801         ixgbe_up(adapter);
3802         clear_bit(__IXGBE_RESETTING, &adapter->state);
3803 }
3804
3805 void ixgbe_up(struct ixgbe_adapter *adapter)
3806 {
3807         /* hardware has been reset, we need to reload some things */
3808         ixgbe_configure(adapter);
3809
3810         ixgbe_up_complete(adapter);
3811 }
3812
3813 void ixgbe_reset(struct ixgbe_adapter *adapter)
3814 {
3815         struct ixgbe_hw *hw = &adapter->hw;
3816         int err;
3817
3818         /* lock SFP init bit to prevent race conditions with the watchdog */
3819         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3820                 usleep_range(1000, 2000);
3821
3822         /* clear all SFP and link config related flags while holding SFP_INIT */
3823         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3824                              IXGBE_FLAG2_SFP_NEEDS_RESET);
3825         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3826
3827         err = hw->mac.ops.init_hw(hw);
3828         switch (err) {
3829         case 0:
3830         case IXGBE_ERR_SFP_NOT_PRESENT:
3831         case IXGBE_ERR_SFP_NOT_SUPPORTED:
3832                 break;
3833         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3834                 e_dev_err("master disable timed out\n");
3835                 break;
3836         case IXGBE_ERR_EEPROM_VERSION:
3837                 /* We are running on a pre-production device, log a warning */
3838                 e_dev_warn("This device is a pre-production adapter/LOM. "
3839                            "Please be aware there may be issuesassociated with "
3840                            "your hardware.  If you are experiencing problems "
3841                            "please contact your Intel or hardware "
3842                            "representative who provided you with this "
3843                            "hardware.\n");
3844                 break;
3845         default:
3846                 e_dev_err("Hardware Error: %d\n", err);
3847         }
3848
3849         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3850
3851         /* reprogram the RAR[0] in case user changed it. */
3852         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3853                             IXGBE_RAH_AV);
3854 }
3855
3856 /**
3857  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3858  * @rx_ring: ring to free buffers from
3859  **/
3860 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3861 {
3862         struct device *dev = rx_ring->dev;
3863         unsigned long size;
3864         u16 i;
3865
3866         /* ring already cleared, nothing to do */
3867         if (!rx_ring->rx_buffer_info)
3868                 return;
3869
3870         /* Free all the Rx ring sk_buffs */
3871         for (i = 0; i < rx_ring->count; i++) {
3872                 struct ixgbe_rx_buffer *rx_buffer_info;
3873
3874                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3875                 if (rx_buffer_info->dma) {
3876                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3877                                          rx_ring->rx_buf_len,
3878                                          DMA_FROM_DEVICE);
3879                         rx_buffer_info->dma = 0;
3880                 }
3881                 if (rx_buffer_info->skb) {
3882                         struct sk_buff *skb = rx_buffer_info->skb;
3883                         rx_buffer_info->skb = NULL;
3884                         do {
3885                                 struct sk_buff *this = skb;
3886                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3887                                         dma_unmap_single(dev,
3888                                                          IXGBE_RSC_CB(this)->dma,
3889                                                          rx_ring->rx_buf_len,
3890                                                          DMA_FROM_DEVICE);
3891                                         IXGBE_RSC_CB(this)->dma = 0;
3892                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3893                                 }
3894                                 skb = skb->prev;
3895                                 dev_kfree_skb(this);
3896                         } while (skb);
3897                 }
3898                 if (!rx_buffer_info->page)
3899                         continue;
3900                 if (rx_buffer_info->page_dma) {
3901                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3902                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3903                         rx_buffer_info->page_dma = 0;
3904                 }
3905                 put_page(rx_buffer_info->page);
3906                 rx_buffer_info->page = NULL;
3907                 rx_buffer_info->page_offset = 0;
3908         }
3909
3910         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3911         memset(rx_ring->rx_buffer_info, 0, size);
3912
3913         /* Zero out the descriptor ring */
3914         memset(rx_ring->desc, 0, rx_ring->size);
3915
3916         rx_ring->next_to_clean = 0;
3917         rx_ring->next_to_use = 0;
3918 }
3919
3920 /**
3921  * ixgbe_clean_tx_ring - Free Tx Buffers
3922  * @tx_ring: ring to be cleaned
3923  **/
3924 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3925 {
3926         struct ixgbe_tx_buffer *tx_buffer_info;
3927         unsigned long size;
3928         u16 i;
3929
3930         /* ring already cleared, nothing to do */
3931         if (!tx_ring->tx_buffer_info)
3932                 return;
3933
3934         /* Free all the Tx ring sk_buffs */
3935         for (i = 0; i < tx_ring->count; i++) {
3936                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3937                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3938         }
3939
3940         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3941         memset(tx_ring->tx_buffer_info, 0, size);
3942
3943         /* Zero out the descriptor ring */
3944         memset(tx_ring->desc, 0, tx_ring->size);
3945
3946         tx_ring->next_to_use = 0;
3947         tx_ring->next_to_clean = 0;
3948 }
3949
3950 /**
3951  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3952  * @adapter: board private structure
3953  **/
3954 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3955 {
3956         int i;
3957
3958         for (i = 0; i < adapter->num_rx_queues; i++)
3959                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3960 }
3961
3962 /**
3963  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3964  * @adapter: board private structure
3965  **/
3966 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3967 {
3968         int i;
3969
3970         for (i = 0; i < adapter->num_tx_queues; i++)
3971                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3972 }
3973
3974 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3975 {
3976         struct hlist_node *node, *node2;
3977         struct ixgbe_fdir_filter *filter;
3978
3979         spin_lock(&adapter->fdir_perfect_lock);
3980
3981         hlist_for_each_entry_safe(filter, node, node2,
3982                                   &adapter->fdir_filter_list, fdir_node) {
3983                 hlist_del(&filter->fdir_node);
3984                 kfree(filter);
3985         }
3986         adapter->fdir_filter_count = 0;
3987
3988         spin_unlock(&adapter->fdir_perfect_lock);
3989 }
3990
3991 void ixgbe_down(struct ixgbe_adapter *adapter)
3992 {
3993         struct net_device *netdev = adapter->netdev;
3994         struct ixgbe_hw *hw = &adapter->hw;
3995         u32 rxctrl;
3996         int i;
3997
3998         /* signal that we are down to the interrupt handler */
3999         set_bit(__IXGBE_DOWN, &adapter->state);
4000
4001         /* disable receives */
4002         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4003         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4004
4005         /* disable all enabled rx queues */
4006         for (i = 0; i < adapter->num_rx_queues; i++)
4007                 /* this call also flushes the previous write */
4008                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4009
4010         usleep_range(10000, 20000);
4011
4012         netif_tx_stop_all_queues(netdev);
4013
4014         /* call carrier off first to avoid false dev_watchdog timeouts */
4015         netif_carrier_off(netdev);
4016         netif_tx_disable(netdev);
4017
4018         ixgbe_irq_disable(adapter);
4019
4020         ixgbe_napi_disable_all(adapter);
4021
4022         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4023                              IXGBE_FLAG2_RESET_REQUESTED);
4024         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4025
4026         del_timer_sync(&adapter->service_timer);
4027
4028         if (adapter->num_vfs) {
4029                 /* Clear EITR Select mapping */
4030                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4031
4032                 /* Mark all the VFs as inactive */
4033                 for (i = 0 ; i < adapter->num_vfs; i++)
4034                         adapter->vfinfo[i].clear_to_send = 0;
4035
4036                 /* ping all the active vfs to let them know we are going down */
4037                 ixgbe_ping_all_vfs(adapter);
4038
4039                 /* Disable all VFTE/VFRE TX/RX */
4040                 ixgbe_disable_tx_rx(adapter);
4041         }
4042
4043         /* disable transmits in the hardware now that interrupts are off */
4044         for (i = 0; i < adapter->num_tx_queues; i++) {
4045                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4046                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4047         }
4048
4049         /* Disable the Tx DMA engine on 82599 and X540 */
4050         switch (hw->mac.type) {
4051         case ixgbe_mac_82599EB:
4052         case ixgbe_mac_X540:
4053                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4054                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4055                                  ~IXGBE_DMATXCTL_TE));
4056                 break;
4057         default:
4058                 break;
4059         }
4060
4061         if (!pci_channel_offline(adapter->pdev))
4062                 ixgbe_reset(adapter);
4063
4064         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4065         if (hw->mac.ops.disable_tx_laser &&
4066             ((hw->phy.multispeed_fiber) ||
4067              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4068               (hw->mac.type == ixgbe_mac_82599EB))))
4069                 hw->mac.ops.disable_tx_laser(hw);
4070
4071         ixgbe_clean_all_tx_rings(adapter);
4072         ixgbe_clean_all_rx_rings(adapter);
4073
4074 #ifdef CONFIG_IXGBE_DCA
4075         /* since we reset the hardware DCA settings were cleared */
4076         ixgbe_setup_dca(adapter);
4077 #endif
4078 }
4079
4080 /**
4081  * ixgbe_poll - NAPI Rx polling callback
4082  * @napi: structure for representing this polling device
4083  * @budget: how many packets driver is allowed to clean
4084  *
4085  * This function is used for legacy and MSI, NAPI mode
4086  **/
4087 static int ixgbe_poll(struct napi_struct *napi, int budget)
4088 {
4089         struct ixgbe_q_vector *q_vector =
4090                                 container_of(napi, struct ixgbe_q_vector, napi);
4091         struct ixgbe_adapter *adapter = q_vector->adapter;
4092         struct ixgbe_ring *ring;
4093         int per_ring_budget;
4094         bool clean_complete = true;
4095
4096 #ifdef CONFIG_IXGBE_DCA
4097         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4098                 ixgbe_update_dca(q_vector);
4099 #endif
4100
4101         for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4102                 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
4103
4104         /* attempt to distribute budget to each queue fairly, but don't allow
4105          * the budget to go below 1 because we'll exit polling */
4106         if (q_vector->rx.count > 1)
4107                 per_ring_budget = max(budget/q_vector->rx.count, 1);
4108         else
4109                 per_ring_budget = budget;
4110
4111         for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4112                 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4113                                                      per_ring_budget);
4114
4115         /* If all work not completed, return budget and keep polling */
4116         if (!clean_complete)
4117                 return budget;
4118
4119         /* all work done, exit the polling mode */
4120         napi_complete(napi);
4121         if (adapter->rx_itr_setting & 1)
4122                 ixgbe_set_itr(q_vector);
4123         if (!test_bit(__IXGBE_DOWN, &adapter->state))
4124                 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4125
4126         return 0;
4127 }
4128
4129 /**
4130  * ixgbe_tx_timeout - Respond to a Tx Hang
4131  * @netdev: network interface device structure
4132  **/
4133 static void ixgbe_tx_timeout(struct net_device *netdev)
4134 {
4135         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4136
4137         /* Do the reset outside of interrupt context */
4138         ixgbe_tx_timeout_reset(adapter);
4139 }
4140
4141 /**
4142  * ixgbe_set_rss_queues: Allocate queues for RSS
4143  * @adapter: board private structure to initialize
4144  *
4145  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4146  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4147  *
4148  **/
4149 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4150 {
4151         bool ret = false;
4152         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4153
4154         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4155                 f->mask = 0xF;
4156                 adapter->num_rx_queues = f->indices;
4157                 adapter->num_tx_queues = f->indices;
4158                 ret = true;
4159         } else {
4160                 ret = false;
4161         }
4162
4163         return ret;
4164 }
4165
4166 /**
4167  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4168  * @adapter: board private structure to initialize
4169  *
4170  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4171  * to the original CPU that initiated the Tx session.  This runs in addition
4172  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4173  * Rx load across CPUs using RSS.
4174  *
4175  **/
4176 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4177 {
4178         bool ret = false;
4179         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4180
4181         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4182         f_fdir->mask = 0;
4183
4184         /* Flow Director must have RSS enabled */
4185         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4186             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4187                 adapter->num_tx_queues = f_fdir->indices;
4188                 adapter->num_rx_queues = f_fdir->indices;
4189                 ret = true;
4190         } else {
4191                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4192         }
4193         return ret;
4194 }
4195
4196 #ifdef IXGBE_FCOE
4197 /**
4198  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4199  * @adapter: board private structure to initialize
4200  *
4201  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4202  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4203  * rx queues out of the max number of rx queues, instead, it is used as the
4204  * index of the first rx queue used by FCoE.
4205  *
4206  **/
4207 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4208 {
4209         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4210
4211         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4212                 return false;
4213
4214         f->indices = min((int)num_online_cpus(), f->indices);
4215
4216         adapter->num_rx_queues = 1;
4217         adapter->num_tx_queues = 1;
4218
4219         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4220                 e_info(probe, "FCoE enabled with RSS\n");
4221                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4222                         ixgbe_set_fdir_queues(adapter);
4223                 else
4224                         ixgbe_set_rss_queues(adapter);
4225         }
4226
4227         /* adding FCoE rx rings to the end */
4228         f->mask = adapter->num_rx_queues;
4229         adapter->num_rx_queues += f->indices;
4230         adapter->num_tx_queues += f->indices;
4231
4232         return true;
4233 }
4234 #endif /* IXGBE_FCOE */
4235
4236 /* Artificial max queue cap per traffic class in DCB mode */
4237 #define DCB_QUEUE_CAP 8
4238
4239 #ifdef CONFIG_IXGBE_DCB
4240 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4241 {
4242         int per_tc_q, q, i, offset = 0;
4243         struct net_device *dev = adapter->netdev;
4244         int tcs = netdev_get_num_tc(dev);
4245
4246         if (!tcs)
4247                 return false;
4248
4249         /* Map queue offset and counts onto allocated tx queues */
4250         per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4251         q = min((int)num_online_cpus(), per_tc_q);
4252
4253         for (i = 0; i < tcs; i++) {
4254                 netdev_set_tc_queue(dev, i, q, offset);
4255                 offset += q;
4256         }
4257
4258         adapter->num_tx_queues = q * tcs;
4259         adapter->num_rx_queues = q * tcs;
4260
4261 #ifdef IXGBE_FCOE
4262         /* FCoE enabled queues require special configuration indexed
4263          * by feature specific indices and mask. Here we map FCoE
4264          * indices onto the DCB queue pairs allowing FCoE to own
4265          * configuration later.
4266          */
4267         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4268                 int tc;
4269                 struct ixgbe_ring_feature *f =
4270                                         &adapter->ring_feature[RING_F_FCOE];
4271
4272                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4273                 f->indices = dev->tc_to_txq[tc].count;
4274                 f->mask = dev->tc_to_txq[tc].offset;
4275         }
4276 #endif
4277
4278         return true;
4279 }
4280 #endif
4281
4282 /**
4283  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4284  * @adapter: board private structure to initialize
4285  *
4286  * IOV doesn't actually use anything, so just NAK the
4287  * request for now and let the other queue routines
4288  * figure out what to do.
4289  */
4290 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4291 {
4292         return false;
4293 }
4294
4295 /*
4296  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4297  * @adapter: board private structure to initialize
4298  *
4299  * This is the top level queue allocation routine.  The order here is very
4300  * important, starting with the "most" number of features turned on at once,
4301  * and ending with the smallest set of features.  This way large combinations
4302  * can be allocated if they're turned on, and smaller combinations are the
4303  * fallthrough conditions.
4304  *
4305  **/
4306 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4307 {
4308         /* Start with base case */
4309         adapter->num_rx_queues = 1;
4310         adapter->num_tx_queues = 1;
4311         adapter->num_rx_pools = adapter->num_rx_queues;
4312         adapter->num_rx_queues_per_pool = 1;
4313
4314         if (ixgbe_set_sriov_queues(adapter))
4315                 goto done;
4316
4317 #ifdef CONFIG_IXGBE_DCB
4318         if (ixgbe_set_dcb_queues(adapter))
4319                 goto done;
4320
4321 #endif
4322 #ifdef IXGBE_FCOE
4323         if (ixgbe_set_fcoe_queues(adapter))
4324                 goto done;
4325
4326 #endif /* IXGBE_FCOE */
4327         if (ixgbe_set_fdir_queues(adapter))
4328                 goto done;
4329
4330         if (ixgbe_set_rss_queues(adapter))
4331                 goto done;
4332
4333         /* fallback to base case */
4334         adapter->num_rx_queues = 1;
4335         adapter->num_tx_queues = 1;
4336
4337 done:
4338         /* Notify the stack of the (possibly) reduced queue counts. */
4339         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4340         return netif_set_real_num_rx_queues(adapter->netdev,
4341                                             adapter->num_rx_queues);
4342 }
4343
4344 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4345                                        int vectors)
4346 {
4347         int err, vector_threshold;
4348
4349         /* We'll want at least 3 (vector_threshold):
4350          * 1) TxQ[0] Cleanup
4351          * 2) RxQ[0] Cleanup
4352          * 3) Other (Link Status Change, etc.)
4353          * 4) TCP Timer (optional)
4354          */
4355         vector_threshold = MIN_MSIX_COUNT;
4356
4357         /* The more we get, the more we will assign to Tx/Rx Cleanup
4358          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4359          * Right now, we simply care about how many we'll get; we'll
4360          * set them up later while requesting irq's.
4361          */
4362         while (vectors >= vector_threshold) {
4363                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4364                                       vectors);
4365                 if (!err) /* Success in acquiring all requested vectors. */
4366                         break;
4367                 else if (err < 0)
4368                         vectors = 0; /* Nasty failure, quit now */
4369                 else /* err == number of vectors we should try again with */
4370                         vectors = err;
4371         }
4372
4373         if (vectors < vector_threshold) {
4374                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4375                  * This just means we'll go with either a single MSI
4376                  * vector or fall back to legacy interrupts.
4377                  */
4378                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4379                              "Unable to allocate MSI-X interrupts\n");
4380                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4381                 kfree(adapter->msix_entries);
4382                 adapter->msix_entries = NULL;
4383         } else {
4384                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4385                 /*
4386                  * Adjust for only the vectors we'll use, which is minimum
4387                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4388                  * vectors we were allocated.
4389                  */
4390                 adapter->num_msix_vectors = min(vectors,
4391                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4392         }
4393 }
4394
4395 /**
4396  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4397  * @adapter: board private structure to initialize
4398  *
4399  * Cache the descriptor ring offsets for RSS to the assigned rings.
4400  *
4401  **/
4402 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4403 {
4404         int i;
4405
4406         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4407                 return false;
4408
4409         for (i = 0; i < adapter->num_rx_queues; i++)
4410                 adapter->rx_ring[i]->reg_idx = i;
4411         for (i = 0; i < adapter->num_tx_queues; i++)
4412                 adapter->tx_ring[i]->reg_idx = i;
4413
4414         return true;
4415 }
4416
4417 #ifdef CONFIG_IXGBE_DCB
4418
4419 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4420 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4421                                     unsigned int *tx, unsigned int *rx)
4422 {
4423         struct net_device *dev = adapter->netdev;
4424         struct ixgbe_hw *hw = &adapter->hw;
4425         u8 num_tcs = netdev_get_num_tc(dev);
4426
4427         *tx = 0;
4428         *rx = 0;
4429
4430         switch (hw->mac.type) {
4431         case ixgbe_mac_82598EB:
4432                 *tx = tc << 2;
4433                 *rx = tc << 3;
4434                 break;
4435         case ixgbe_mac_82599EB:
4436         case ixgbe_mac_X540:
4437                 if (num_tcs > 4) {
4438                         if (tc < 3) {
4439                                 *tx = tc << 5;
4440                                 *rx = tc << 4;
4441                         } else if (tc <  5) {
4442                                 *tx = ((tc + 2) << 4);
4443                                 *rx = tc << 4;
4444                         } else if (tc < num_tcs) {
4445                                 *tx = ((tc + 8) << 3);
4446                                 *rx = tc << 4;
4447                         }
4448                 } else {
4449                         *rx =  tc << 5;
4450                         switch (tc) {
4451                         case 0:
4452                                 *tx =  0;
4453                                 break;
4454                         case 1:
4455                                 *tx = 64;
4456                                 break;
4457                         case 2:
4458                                 *tx = 96;
4459                                 break;
4460                         case 3:
4461                                 *tx = 112;
4462                                 break;
4463                         default:
4464                                 break;
4465                         }
4466                 }
4467                 break;
4468         default:
4469                 break;
4470         }
4471 }
4472
4473 /**
4474  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4475  * @adapter: board private structure to initialize
4476  *
4477  * Cache the descriptor ring offsets for DCB to the assigned rings.
4478  *
4479  **/
4480 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4481 {
4482         struct net_device *dev = adapter->netdev;
4483         int i, j, k;
4484         u8 num_tcs = netdev_get_num_tc(dev);
4485
4486         if (!num_tcs)
4487                 return false;
4488
4489         for (i = 0, k = 0; i < num_tcs; i++) {
4490                 unsigned int tx_s, rx_s;
4491                 u16 count = dev->tc_to_txq[i].count;
4492
4493                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4494                 for (j = 0; j < count; j++, k++) {
4495                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4496                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4497                         adapter->tx_ring[k]->dcb_tc = i;
4498                         adapter->rx_ring[k]->dcb_tc = i;
4499                 }
4500         }
4501
4502         return true;
4503 }
4504 #endif
4505
4506 /**
4507  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4508  * @adapter: board private structure to initialize
4509  *
4510  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4511  *
4512  **/
4513 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4514 {
4515         int i;
4516         bool ret = false;
4517
4518         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4519             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4520                 for (i = 0; i < adapter->num_rx_queues; i++)
4521                         adapter->rx_ring[i]->reg_idx = i;
4522                 for (i = 0; i < adapter->num_tx_queues; i++)
4523                         adapter->tx_ring[i]->reg_idx = i;
4524                 ret = true;
4525         }
4526
4527         return ret;
4528 }
4529
4530 #ifdef IXGBE_FCOE
4531 /**
4532  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4533  * @adapter: board private structure to initialize
4534  *
4535  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4536  *
4537  */
4538 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4539 {
4540         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4541         int i;
4542         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4543
4544         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4545                 return false;
4546
4547         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4548                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4549                         ixgbe_cache_ring_fdir(adapter);
4550                 else
4551                         ixgbe_cache_ring_rss(adapter);
4552
4553                 fcoe_rx_i = f->mask;
4554                 fcoe_tx_i = f->mask;
4555         }
4556         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4557                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4558                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4559         }
4560         return true;
4561 }
4562
4563 #endif /* IXGBE_FCOE */
4564 /**
4565  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4566  * @adapter: board private structure to initialize
4567  *
4568  * SR-IOV doesn't use any descriptor rings but changes the default if
4569  * no other mapping is used.
4570  *
4571  */
4572 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4573 {
4574         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4575         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4576         if (adapter->num_vfs)
4577                 return true;
4578         else
4579                 return false;
4580 }
4581
4582 /**
4583  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4584  * @adapter: board private structure to initialize
4585  *
4586  * Once we know the feature-set enabled for the device, we'll cache
4587  * the register offset the descriptor ring is assigned to.
4588  *
4589  * Note, the order the various feature calls is important.  It must start with
4590  * the "most" features enabled at the same time, then trickle down to the
4591  * least amount of features turned on at once.
4592  **/
4593 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4594 {
4595         /* start with default case */
4596         adapter->rx_ring[0]->reg_idx = 0;
4597         adapter->tx_ring[0]->reg_idx = 0;
4598
4599         if (ixgbe_cache_ring_sriov(adapter))
4600                 return;
4601
4602 #ifdef CONFIG_IXGBE_DCB
4603         if (ixgbe_cache_ring_dcb(adapter))
4604                 return;
4605 #endif
4606
4607 #ifdef IXGBE_FCOE
4608         if (ixgbe_cache_ring_fcoe(adapter))
4609                 return;
4610 #endif /* IXGBE_FCOE */
4611
4612         if (ixgbe_cache_ring_fdir(adapter))
4613                 return;
4614
4615         if (ixgbe_cache_ring_rss(adapter))
4616                 return;
4617 }
4618
4619 /**
4620  * ixgbe_alloc_queues - Allocate memory for all rings
4621  * @adapter: board private structure to initialize
4622  *
4623  * We allocate one ring per queue at run-time since we don't know the
4624  * number of queues at compile-time.  The polling_netdev array is
4625  * intended for Multiqueue, but should work fine with a single queue.
4626  **/
4627 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4628 {
4629         int rx = 0, tx = 0, nid = adapter->node;
4630
4631         if (nid < 0 || !node_online(nid))
4632                 nid = first_online_node;
4633
4634         for (; tx < adapter->num_tx_queues; tx++) {
4635                 struct ixgbe_ring *ring;
4636
4637                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4638                 if (!ring)
4639                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4640                 if (!ring)
4641                         goto err_allocation;
4642                 ring->count = adapter->tx_ring_count;
4643                 ring->queue_index = tx;
4644                 ring->numa_node = nid;
4645                 ring->dev = &adapter->pdev->dev;
4646                 ring->netdev = adapter->netdev;
4647
4648                 adapter->tx_ring[tx] = ring;
4649         }
4650
4651         for (; rx < adapter->num_rx_queues; rx++) {
4652                 struct ixgbe_ring *ring;
4653
4654                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4655                 if (!ring)
4656                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4657                 if (!ring)
4658                         goto err_allocation;
4659                 ring->count = adapter->rx_ring_count;
4660                 ring->queue_index = rx;
4661                 ring->numa_node = nid;
4662                 ring->dev = &adapter->pdev->dev;
4663                 ring->netdev = adapter->netdev;
4664
4665                 adapter->rx_ring[rx] = ring;
4666         }
4667
4668         ixgbe_cache_ring_register(adapter);
4669
4670         return 0;
4671
4672 err_allocation:
4673         while (tx)
4674                 kfree(adapter->tx_ring[--tx]);
4675
4676         while (rx)
4677                 kfree(adapter->rx_ring[--rx]);
4678         return -ENOMEM;
4679 }
4680
4681 /**
4682  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4683  * @adapter: board private structure to initialize
4684  *
4685  * Attempt to configure the interrupts using the best available
4686  * capabilities of the hardware and the kernel.
4687  **/
4688 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4689 {
4690         struct ixgbe_hw *hw = &adapter->hw;
4691         int err = 0;
4692         int vector, v_budget;
4693
4694         /*
4695          * It's easy to be greedy for MSI-X vectors, but it really
4696          * doesn't do us much good if we have a lot more vectors
4697          * than CPU's.  So let's be conservative and only ask for
4698          * (roughly) the same number of vectors as there are CPU's.
4699          */
4700         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4701                        (int)num_online_cpus()) + NON_Q_VECTORS;
4702
4703         /*
4704          * At the same time, hardware can only support a maximum of
4705          * hw.mac->max_msix_vectors vectors.  With features
4706          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4707          * descriptor queues supported by our device.  Thus, we cap it off in
4708          * those rare cases where the cpu count also exceeds our vector limit.
4709          */
4710         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4711
4712         /* A failure in MSI-X entry allocation isn't fatal, but it does
4713          * mean we disable MSI-X capabilities of the adapter. */
4714         adapter->msix_entries = kcalloc(v_budget,
4715                                         sizeof(struct msix_entry), GFP_KERNEL);
4716         if (adapter->msix_entries) {
4717                 for (vector = 0; vector < v_budget; vector++)
4718                         adapter->msix_entries[vector].entry = vector;
4719
4720                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4721
4722                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4723                         goto out;
4724         }
4725
4726         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4727         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4728         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4729                 e_err(probe,
4730                       "ATR is not supported while multiple "
4731                       "queues are disabled.  Disabling Flow Director\n");
4732         }
4733         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4734         adapter->atr_sample_rate = 0;
4735         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4736                 ixgbe_disable_sriov(adapter);
4737
4738         err = ixgbe_set_num_queues(adapter);
4739         if (err)
4740                 return err;
4741
4742         err = pci_enable_msi(adapter->pdev);
4743         if (!err) {
4744                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4745         } else {
4746                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4747                              "Unable to allocate MSI interrupt, "
4748                              "falling back to legacy.  Error: %d\n", err);
4749                 /* reset err */
4750                 err = 0;
4751         }
4752
4753 out:
4754         return err;
4755 }
4756
4757 /**
4758  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4759  * @adapter: board private structure to initialize
4760  *
4761  * We allocate one q_vector per queue interrupt.  If allocation fails we
4762  * return -ENOMEM.
4763  **/
4764 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4765 {
4766         int v_idx, num_q_vectors;
4767         struct ixgbe_q_vector *q_vector;
4768
4769         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4770                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4771         else
4772                 num_q_vectors = 1;
4773
4774         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4775                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4776                                         GFP_KERNEL, adapter->node);
4777                 if (!q_vector)
4778                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4779                                            GFP_KERNEL);
4780                 if (!q_vector)
4781                         goto err_out;
4782
4783                 q_vector->adapter = adapter;
4784                 q_vector->v_idx = v_idx;
4785
4786                 /* Allocate the affinity_hint cpumask, configure the mask */
4787                 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4788                         goto err_out;
4789                 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4790                 netif_napi_add(adapter->netdev, &q_vector->napi,
4791                                ixgbe_poll, 64);
4792                 adapter->q_vector[v_idx] = q_vector;
4793         }
4794
4795         return 0;
4796
4797 err_out:
4798         while (v_idx) {
4799                 v_idx--;
4800                 q_vector = adapter->q_vector[v_idx];
4801                 netif_napi_del(&q_vector->napi);
4802                 free_cpumask_var(q_vector->affinity_mask);
4803                 kfree(q_vector);
4804                 adapter->q_vector[v_idx] = NULL;
4805         }
4806         return -ENOMEM;
4807 }
4808
4809 /**
4810  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4811  * @adapter: board private structure to initialize
4812  *
4813  * This function frees the memory allocated to the q_vectors.  In addition if
4814  * NAPI is enabled it will delete any references to the NAPI struct prior
4815  * to freeing the q_vector.
4816  **/
4817 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4818 {
4819         int v_idx, num_q_vectors;
4820
4821         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4822                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4823         else
4824                 num_q_vectors = 1;
4825
4826         for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4827                 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4828                 adapter->q_vector[v_idx] = NULL;
4829                 netif_napi_del(&q_vector->napi);
4830                 free_cpumask_var(q_vector->affinity_mask);
4831                 kfree(q_vector);
4832         }
4833 }
4834
4835 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4836 {
4837         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4838                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4839                 pci_disable_msix(adapter->pdev);
4840                 kfree(adapter->msix_entries);
4841                 adapter->msix_entries = NULL;
4842         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4843                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4844                 pci_disable_msi(adapter->pdev);
4845         }
4846 }
4847
4848 /**
4849  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4850  * @adapter: board private structure to initialize
4851  *
4852  * We determine which interrupt scheme to use based on...
4853  * - Kernel support (MSI, MSI-X)
4854  *   - which can be user-defined (via MODULE_PARAM)
4855  * - Hardware queue count (num_*_queues)
4856  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4857  **/
4858 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4859 {
4860         int err;
4861
4862         /* Number of supported queues */
4863         err = ixgbe_set_num_queues(adapter);
4864         if (err)
4865                 return err;
4866
4867         err = ixgbe_set_interrupt_capability(adapter);
4868         if (err) {
4869                 e_dev_err("Unable to setup interrupt capabilities\n");
4870                 goto err_set_interrupt;
4871         }
4872
4873         err = ixgbe_alloc_q_vectors(adapter);
4874         if (err) {
4875                 e_dev_err("Unable to allocate memory for queue vectors\n");
4876                 goto err_alloc_q_vectors;
4877         }
4878
4879         err = ixgbe_alloc_queues(adapter);
4880         if (err) {
4881                 e_dev_err("Unable to allocate memory for queues\n");
4882                 goto err_alloc_queues;
4883         }
4884
4885         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4886                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4887                    adapter->num_rx_queues, adapter->num_tx_queues);
4888
4889         set_bit(__IXGBE_DOWN, &adapter->state);
4890
4891         return 0;
4892
4893 err_alloc_queues:
4894         ixgbe_free_q_vectors(adapter);
4895 err_alloc_q_vectors:
4896         ixgbe_reset_interrupt_capability(adapter);
4897 err_set_interrupt:
4898         return err;
4899 }
4900
4901 /**
4902  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4903  * @adapter: board private structure to clear interrupt scheme on
4904  *
4905  * We go through and clear interrupt specific resources and reset the structure
4906  * to pre-load conditions
4907  **/
4908 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4909 {
4910         int i;
4911
4912         for (i = 0; i < adapter->num_tx_queues; i++) {
4913                 kfree(adapter->tx_ring[i]);
4914                 adapter->tx_ring[i] = NULL;
4915         }
4916         for (i = 0; i < adapter->num_rx_queues; i++) {
4917                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4918
4919                 /* ixgbe_get_stats64() might access this ring, we must wait
4920                  * a grace period before freeing it.
4921                  */
4922                 kfree_rcu(ring, rcu);
4923                 adapter->rx_ring[i] = NULL;
4924         }
4925
4926         adapter->num_tx_queues = 0;
4927         adapter->num_rx_queues = 0;
4928
4929         ixgbe_free_q_vectors(adapter);
4930         ixgbe_reset_interrupt_capability(adapter);
4931 }
4932
4933 /**
4934  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4935  * @adapter: board private structure to initialize
4936  *
4937  * ixgbe_sw_init initializes the Adapter private data structure.
4938  * Fields are initialized based on PCI device information and
4939  * OS network device settings (MTU size).
4940  **/
4941 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4942 {
4943         struct ixgbe_hw *hw = &adapter->hw;
4944         struct pci_dev *pdev = adapter->pdev;
4945         unsigned int rss;
4946 #ifdef CONFIG_IXGBE_DCB
4947         int j;
4948         struct tc_configuration *tc;
4949 #endif
4950
4951         /* PCI config space info */
4952
4953         hw->vendor_id = pdev->vendor;
4954         hw->device_id = pdev->device;
4955         hw->revision_id = pdev->revision;
4956         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4957         hw->subsystem_device_id = pdev->subsystem_device;
4958
4959         /* Set capability flags */
4960         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4961         adapter->ring_feature[RING_F_RSS].indices = rss;
4962         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4963         switch (hw->mac.type) {
4964         case ixgbe_mac_82598EB:
4965                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4966                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4967                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4968                 break;
4969         case ixgbe_mac_X540:
4970                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4971         case ixgbe_mac_82599EB:
4972                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4973                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4974                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4975                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4976                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4977                 /* Flow Director hash filters enabled */
4978                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4979                 adapter->atr_sample_rate = 20;
4980                 adapter->ring_feature[RING_F_FDIR].indices =
4981                                                          IXGBE_MAX_FDIR_INDICES;
4982                 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4983 #ifdef IXGBE_FCOE
4984                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4985                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4986                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4987 #ifdef CONFIG_IXGBE_DCB
4988                 /* Default traffic class to use for FCoE */
4989                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4990 #endif
4991 #endif /* IXGBE_FCOE */
4992                 break;
4993         default:
4994                 break;
4995         }
4996
4997         /* n-tuple support exists, always init our spinlock */
4998         spin_lock_init(&adapter->fdir_perfect_lock);
4999
5000 #ifdef CONFIG_IXGBE_DCB
5001         switch (hw->mac.type) {
5002         case ixgbe_mac_X540:
5003                 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5004                 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5005                 break;
5006         default:
5007                 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5008                 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5009                 break;
5010         }
5011
5012         /* Configure DCB traffic classes */
5013         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5014                 tc = &adapter->dcb_cfg.tc_config[j];
5015                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5016                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5017                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5018                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5019                 tc->dcb_pfc = pfc_disabled;
5020         }
5021
5022         /* Initialize default user to priority mapping, UPx->TC0 */
5023         tc = &adapter->dcb_cfg.tc_config[0];
5024         tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5025         tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5026
5027         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5028         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5029         adapter->dcb_cfg.pfc_mode_enable = false;
5030         adapter->dcb_set_bitmap = 0x00;
5031         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5032         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5033                            MAX_TRAFFIC_CLASS);
5034
5035 #endif
5036
5037         /* default flow control settings */
5038         hw->fc.requested_mode = ixgbe_fc_full;
5039         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5040 #ifdef CONFIG_DCB
5041         adapter->last_lfc_mode = hw->fc.current_mode;
5042 #endif
5043         ixgbe_pbthresh_setup(adapter);
5044         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5045         hw->fc.send_xon = true;
5046         hw->fc.disable_fc_autoneg = false;
5047
5048         /* enable itr by default in dynamic mode */
5049         adapter->rx_itr_setting = 1;
5050         adapter->tx_itr_setting = 1;
5051
5052         /* set defaults for eitr in MegaBytes */
5053         adapter->eitr_low = 10;
5054         adapter->eitr_high = 20;
5055
5056         /* set default ring sizes */
5057         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5058         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5059
5060         /* set default work limits */
5061         adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5062
5063         /* initialize eeprom parameters */
5064         if (ixgbe_init_eeprom_params_generic(hw)) {
5065                 e_dev_err("EEPROM initialization failed\n");
5066                 return -EIO;
5067         }
5068
5069         /* enable rx csum by default */
5070         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5071
5072         /* get assigned NUMA node */
5073         adapter->node = dev_to_node(&pdev->dev);
5074
5075         set_bit(__IXGBE_DOWN, &adapter->state);
5076
5077         return 0;
5078 }
5079
5080 /**
5081  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5082  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5083  *
5084  * Return 0 on success, negative on failure
5085  **/
5086 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5087 {
5088         struct device *dev = tx_ring->dev;
5089         int size;
5090
5091         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5092         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5093         if (!tx_ring->tx_buffer_info)
5094                 tx_ring->tx_buffer_info = vzalloc(size);
5095         if (!tx_ring->tx_buffer_info)
5096                 goto err;
5097
5098         /* round up to nearest 4K */
5099         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5100         tx_ring->size = ALIGN(tx_ring->size, 4096);
5101
5102         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5103                                            &tx_ring->dma, GFP_KERNEL);
5104         if (!tx_ring->desc)
5105                 goto err;
5106
5107         tx_ring->next_to_use = 0;
5108         tx_ring->next_to_clean = 0;
5109         return 0;
5110
5111 err:
5112         vfree(tx_ring->tx_buffer_info);
5113         tx_ring->tx_buffer_info = NULL;
5114         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5115         return -ENOMEM;
5116 }
5117
5118 /**
5119  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5120  * @adapter: board private structure
5121  *
5122  * If this function returns with an error, then it's possible one or
5123  * more of the rings is populated (while the rest are not).  It is the
5124  * callers duty to clean those orphaned rings.
5125  *
5126  * Return 0 on success, negative on failure
5127  **/
5128 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5129 {
5130         int i, err = 0;
5131
5132         for (i = 0; i < adapter->num_tx_queues; i++) {
5133                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5134                 if (!err)
5135                         continue;
5136                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5137                 break;
5138         }
5139
5140         return err;
5141 }
5142
5143 /**
5144  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5145  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5146  *
5147  * Returns 0 on success, negative on failure
5148  **/
5149 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5150 {
5151         struct device *dev = rx_ring->dev;
5152         int size;
5153
5154         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5155         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5156         if (!rx_ring->rx_buffer_info)
5157                 rx_ring->rx_buffer_info = vzalloc(size);
5158         if (!rx_ring->rx_buffer_info)
5159                 goto err;
5160
5161         /* Round up to nearest 4K */
5162         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5163         rx_ring->size = ALIGN(rx_ring->size, 4096);
5164
5165         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5166                                            &rx_ring->dma, GFP_KERNEL);
5167
5168         if (!rx_ring->desc)
5169                 goto err;
5170
5171         rx_ring->next_to_clean = 0;
5172         rx_ring->next_to_use = 0;
5173
5174         return 0;
5175 err:
5176         vfree(rx_ring->rx_buffer_info);
5177         rx_ring->rx_buffer_info = NULL;
5178         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5179         return -ENOMEM;
5180 }
5181
5182 /**
5183  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5184  * @adapter: board private structure
5185  *
5186  * If this function returns with an error, then it's possible one or
5187  * more of the rings is populated (while the rest are not).  It is the
5188  * callers duty to clean those orphaned rings.
5189  *
5190  * Return 0 on success, negative on failure
5191  **/
5192 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5193 {
5194         int i, err = 0;
5195
5196         for (i = 0; i < adapter->num_rx_queues; i++) {
5197                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5198                 if (!err)
5199                         continue;
5200                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5201                 break;
5202         }
5203
5204         return err;
5205 }
5206
5207 /**
5208  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5209  * @tx_ring: Tx descriptor ring for a specific queue
5210  *
5211  * Free all transmit software resources
5212  **/
5213 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5214 {
5215         ixgbe_clean_tx_ring(tx_ring);
5216
5217         vfree(tx_ring->tx_buffer_info);
5218         tx_ring->tx_buffer_info = NULL;
5219
5220         /* if not set, then don't free */
5221         if (!tx_ring->desc)
5222                 return;
5223
5224         dma_free_coherent(tx_ring->dev, tx_ring->size,
5225                           tx_ring->desc, tx_ring->dma);
5226
5227         tx_ring->desc = NULL;
5228 }
5229
5230 /**
5231  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5232  * @adapter: board private structure
5233  *
5234  * Free all transmit software resources
5235  **/
5236 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5237 {
5238         int i;
5239
5240         for (i = 0; i < adapter->num_tx_queues; i++)
5241                 if (adapter->tx_ring[i]->desc)
5242                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5243 }
5244
5245 /**
5246  * ixgbe_free_rx_resources - Free Rx Resources
5247  * @rx_ring: ring to clean the resources from
5248  *
5249  * Free all receive software resources
5250  **/
5251 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5252 {
5253         ixgbe_clean_rx_ring(rx_ring);
5254
5255         vfree(rx_ring->rx_buffer_info);
5256         rx_ring->rx_buffer_info = NULL;
5257
5258         /* if not set, then don't free */
5259         if (!rx_ring->desc)
5260                 return;
5261
5262         dma_free_coherent(rx_ring->dev, rx_ring->size,
5263                           rx_ring->desc, rx_ring->dma);
5264
5265         rx_ring->desc = NULL;
5266 }
5267
5268 /**
5269  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5270  * @adapter: board private structure
5271  *
5272  * Free all receive software resources
5273  **/
5274 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5275 {
5276         int i;
5277
5278         for (i = 0; i < adapter->num_rx_queues; i++)
5279                 if (adapter->rx_ring[i]->desc)
5280                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5281 }
5282
5283 /**
5284  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5285  * @netdev: network interface device structure
5286  * @new_mtu: new value for maximum frame size
5287  *
5288  * Returns 0 on success, negative on failure
5289  **/
5290 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5291 {
5292         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5293         struct ixgbe_hw *hw = &adapter->hw;
5294         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5295
5296         /* MTU < 68 is an error and causes problems on some kernels */
5297         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5298             hw->mac.type != ixgbe_mac_X540) {
5299                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5300                         return -EINVAL;
5301         } else {
5302                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5303                         return -EINVAL;
5304         }
5305
5306         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5307         /* must set new MTU before calling down or up */
5308         netdev->mtu = new_mtu;
5309
5310         if (netif_running(netdev))
5311                 ixgbe_reinit_locked(adapter);
5312
5313         return 0;
5314 }
5315
5316 /**
5317  * ixgbe_open - Called when a network interface is made active
5318  * @netdev: network interface device structure
5319  *
5320  * Returns 0 on success, negative value on failure
5321  *
5322  * The open entry point is called when a network interface is made
5323  * active by the system (IFF_UP).  At this point all resources needed
5324  * for transmit and receive operations are allocated, the interrupt
5325  * handler is registered with the OS, the watchdog timer is started,
5326  * and the stack is notified that the interface is ready.
5327  **/
5328 static int ixgbe_open(struct net_device *netdev)
5329 {
5330         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5331         int err;
5332
5333         /* disallow open during test */
5334         if (test_bit(__IXGBE_TESTING, &adapter->state))
5335                 return -EBUSY;
5336
5337         netif_carrier_off(netdev);
5338
5339         /* allocate transmit descriptors */
5340         err = ixgbe_setup_all_tx_resources(adapter);
5341         if (err)
5342                 goto err_setup_tx;
5343
5344         /* allocate receive descriptors */
5345         err = ixgbe_setup_all_rx_resources(adapter);
5346         if (err)
5347                 goto err_setup_rx;
5348
5349         ixgbe_configure(adapter);
5350
5351         err = ixgbe_request_irq(adapter);
5352         if (err)
5353                 goto err_req_irq;
5354
5355         ixgbe_up_complete(adapter);
5356
5357         return 0;
5358
5359 err_req_irq:
5360 err_setup_rx:
5361         ixgbe_free_all_rx_resources(adapter);
5362 err_setup_tx:
5363         ixgbe_free_all_tx_resources(adapter);
5364         ixgbe_reset(adapter);
5365
5366         return err;
5367 }
5368
5369 /**
5370  * ixgbe_close - Disables a network interface
5371  * @netdev: network interface device structure
5372  *
5373  * Returns 0, this is not allowed to fail
5374  *
5375  * The close entry point is called when an interface is de-activated
5376  * by the OS.  The hardware is still under the drivers control, but
5377  * needs to be disabled.  A global MAC reset is issued to stop the
5378  * hardware, and all transmit and receive resources are freed.
5379  **/
5380 static int ixgbe_close(struct net_device *netdev)
5381 {
5382         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5383
5384         ixgbe_down(adapter);
5385         ixgbe_free_irq(adapter);
5386
5387         ixgbe_fdir_filter_exit(adapter);
5388
5389         ixgbe_free_all_tx_resources(adapter);
5390         ixgbe_free_all_rx_resources(adapter);
5391
5392         ixgbe_release_hw_control(adapter);
5393
5394         return 0;
5395 }
5396
5397 #ifdef CONFIG_PM
5398 static int ixgbe_resume(struct pci_dev *pdev)
5399 {
5400         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5401         struct net_device *netdev = adapter->netdev;
5402         u32 err;
5403
5404         pci_set_power_state(pdev, PCI_D0);
5405         pci_restore_state(pdev);
5406         /*
5407          * pci_restore_state clears dev->state_saved so call
5408          * pci_save_state to restore it.
5409          */
5410         pci_save_state(pdev);
5411
5412         err = pci_enable_device_mem(pdev);
5413         if (err) {
5414                 e_dev_err("Cannot enable PCI device from suspend\n");
5415                 return err;
5416         }
5417         pci_set_master(pdev);
5418
5419         pci_wake_from_d3(pdev, false);
5420
5421         rtnl_lock();
5422         err = ixgbe_init_interrupt_scheme(adapter);
5423         rtnl_unlock();
5424         if (err) {
5425                 e_dev_err("Cannot initialize interrupts for device\n");
5426                 return err;
5427         }
5428
5429         ixgbe_reset(adapter);
5430
5431         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5432
5433         if (netif_running(netdev)) {
5434                 err = ixgbe_open(netdev);
5435                 if (err)
5436                         return err;
5437         }
5438
5439         netif_device_attach(netdev);
5440
5441         return 0;
5442 }
5443 #endif /* CONFIG_PM */
5444
5445 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5446 {
5447         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5448         struct net_device *netdev = adapter->netdev;
5449         struct ixgbe_hw *hw = &adapter->hw;
5450         u32 ctrl, fctrl;
5451         u32 wufc = adapter->wol;
5452 #ifdef CONFIG_PM
5453         int retval = 0;
5454 #endif
5455
5456         netif_device_detach(netdev);
5457
5458         if (netif_running(netdev)) {
5459                 ixgbe_down(adapter);
5460                 ixgbe_free_irq(adapter);
5461                 ixgbe_free_all_tx_resources(adapter);
5462                 ixgbe_free_all_rx_resources(adapter);
5463         }
5464
5465         ixgbe_clear_interrupt_scheme(adapter);
5466 #ifdef CONFIG_DCB
5467         kfree(adapter->ixgbe_ieee_pfc);
5468         kfree(adapter->ixgbe_ieee_ets);
5469 #endif
5470
5471 #ifdef CONFIG_PM
5472         retval = pci_save_state(pdev);
5473         if (retval)
5474                 return retval;
5475
5476 #endif
5477         if (wufc) {
5478                 ixgbe_set_rx_mode(netdev);
5479
5480                 /* turn on all-multi mode if wake on multicast is enabled */
5481                 if (wufc & IXGBE_WUFC_MC) {
5482                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5483                         fctrl |= IXGBE_FCTRL_MPE;
5484                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5485                 }
5486
5487                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5488                 ctrl |= IXGBE_CTRL_GIO_DIS;
5489                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5490
5491                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5492         } else {
5493                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5494                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5495         }
5496
5497         switch (hw->mac.type) {
5498         case ixgbe_mac_82598EB:
5499                 pci_wake_from_d3(pdev, false);
5500                 break;
5501         case ixgbe_mac_82599EB:
5502         case ixgbe_mac_X540:
5503                 pci_wake_from_d3(pdev, !!wufc);
5504                 break;
5505         default:
5506                 break;
5507         }
5508
5509         *enable_wake = !!wufc;
5510
5511         ixgbe_release_hw_control(adapter);
5512
5513         pci_disable_device(pdev);
5514
5515         return 0;
5516 }
5517
5518 #ifdef CONFIG_PM
5519 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5520 {
5521         int retval;
5522         bool wake;
5523
5524         retval = __ixgbe_shutdown(pdev, &wake);
5525         if (retval)
5526                 return retval;
5527
5528         if (wake) {
5529                 pci_prepare_to_sleep(pdev);
5530         } else {
5531                 pci_wake_from_d3(pdev, false);
5532                 pci_set_power_state(pdev, PCI_D3hot);
5533         }
5534
5535         return 0;
5536 }
5537 #endif /* CONFIG_PM */
5538
5539 static void ixgbe_shutdown(struct pci_dev *pdev)
5540 {
5541         bool wake;
5542
5543         __ixgbe_shutdown(pdev, &wake);
5544
5545         if (system_state == SYSTEM_POWER_OFF) {
5546                 pci_wake_from_d3(pdev, wake);
5547                 pci_set_power_state(pdev, PCI_D3hot);
5548         }
5549 }
5550
5551 /**
5552  * ixgbe_update_stats - Update the board statistics counters.
5553  * @adapter: board private structure
5554  **/
5555 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5556 {
5557         struct net_device *netdev = adapter->netdev;
5558         struct ixgbe_hw *hw = &adapter->hw;
5559         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5560         u64 total_mpc = 0;
5561         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5562         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5563         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5564         u64 bytes = 0, packets = 0;
5565 #ifdef IXGBE_FCOE
5566         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5567         unsigned int cpu;
5568         u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5569 #endif /* IXGBE_FCOE */
5570
5571         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5572             test_bit(__IXGBE_RESETTING, &adapter->state))
5573                 return;
5574
5575         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5576                 u64 rsc_count = 0;
5577                 u64 rsc_flush = 0;
5578                 for (i = 0; i < 16; i++)
5579                         adapter->hw_rx_no_dma_resources +=
5580                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5581                 for (i = 0; i < adapter->num_rx_queues; i++) {
5582                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5583                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5584                 }
5585                 adapter->rsc_total_count = rsc_count;
5586                 adapter->rsc_total_flush = rsc_flush;
5587         }
5588
5589         for (i = 0; i < adapter->num_rx_queues; i++) {
5590                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5591                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5592                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5593                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5594                 bytes += rx_ring->stats.bytes;
5595                 packets += rx_ring->stats.packets;
5596         }
5597         adapter->non_eop_descs = non_eop_descs;
5598         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5599         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5600         netdev->stats.rx_bytes = bytes;
5601         netdev->stats.rx_packets = packets;
5602
5603         bytes = 0;
5604         packets = 0;
5605         /* gather some stats to the adapter struct that are per queue */
5606         for (i = 0; i < adapter->num_tx_queues; i++) {
5607                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5608                 restart_queue += tx_ring->tx_stats.restart_queue;
5609                 tx_busy += tx_ring->tx_stats.tx_busy;
5610                 bytes += tx_ring->stats.bytes;
5611                 packets += tx_ring->stats.packets;
5612         }
5613         adapter->restart_queue = restart_queue;
5614         adapter->tx_busy = tx_busy;
5615         netdev->stats.tx_bytes = bytes;
5616         netdev->stats.tx_packets = packets;
5617
5618         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5619
5620         /* 8 register reads */
5621         for (i = 0; i < 8; i++) {
5622                 /* for packet buffers not used, the register should read 0 */
5623                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5624                 missed_rx += mpc;
5625                 hwstats->mpc[i] += mpc;
5626                 total_mpc += hwstats->mpc[i];
5627                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5628                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5629                 switch (hw->mac.type) {
5630                 case ixgbe_mac_82598EB:
5631                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5632                         hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5633                         hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5634                         hwstats->pxonrxc[i] +=
5635                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5636                         break;
5637                 case ixgbe_mac_82599EB:
5638                 case ixgbe_mac_X540:
5639                         hwstats->pxonrxc[i] +=
5640                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5641                         break;
5642                 default:
5643                         break;
5644                 }
5645         }
5646
5647         /*16 register reads */
5648         for (i = 0; i < 16; i++) {
5649                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5650                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5651                 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5652                     (hw->mac.type == ixgbe_mac_X540)) {
5653                         hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5654                         IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5655                         hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5656                         IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5657                 }
5658         }
5659
5660         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5661         /* work around hardware counting issue */
5662         hwstats->gprc -= missed_rx;
5663
5664         ixgbe_update_xoff_received(adapter);
5665
5666         /* 82598 hardware only has a 32 bit counter in the high register */
5667         switch (hw->mac.type) {
5668         case ixgbe_mac_82598EB:
5669                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5670                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5671                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5672                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5673                 break;
5674         case ixgbe_mac_X540:
5675                 /* OS2BMC stats are X540 only*/
5676                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5677                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5678                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5679                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5680         case ixgbe_mac_82599EB:
5681                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5682                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5683                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5684                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5685                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5686                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5687                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5688                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5689                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5690 #ifdef IXGBE_FCOE
5691                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5692                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5693                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5694                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5695                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5696                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5697                 /* Add up per cpu counters for total ddp aloc fail */
5698                 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5699                         for_each_possible_cpu(cpu) {
5700                                 fcoe_noddp_counts_sum +=
5701                                         *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5702                                 fcoe_noddp_ext_buff_counts_sum +=
5703                                         *per_cpu_ptr(fcoe->
5704                                                 pcpu_noddp_ext_buff, cpu);
5705                         }
5706                 }
5707                 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5708                 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5709 #endif /* IXGBE_FCOE */
5710                 break;
5711         default:
5712                 break;
5713         }
5714         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5715         hwstats->bprc += bprc;
5716         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5717         if (hw->mac.type == ixgbe_mac_82598EB)
5718                 hwstats->mprc -= bprc;
5719         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5720         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5721         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5722         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5723         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5724         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5725         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5726         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5727         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5728         hwstats->lxontxc += lxon;
5729         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5730         hwstats->lxofftxc += lxoff;
5731         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5732         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5733         /*
5734          * 82598 errata - tx of flow control packets is included in tx counters
5735          */
5736         xon_off_tot = lxon + lxoff;
5737         hwstats->gptc -= xon_off_tot;
5738         hwstats->mptc -= xon_off_tot;
5739         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5740         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5741         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5742         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5743         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5744         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5745         hwstats->ptc64 -= xon_off_tot;
5746         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5747         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5748         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5749         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5750         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5751         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5752
5753         /* Fill out the OS statistics structure */
5754         netdev->stats.multicast = hwstats->mprc;
5755
5756         /* Rx Errors */
5757         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5758         netdev->stats.rx_dropped = 0;
5759         netdev->stats.rx_length_errors = hwstats->rlec;
5760         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5761         netdev->stats.rx_missed_errors = total_mpc;
5762 }
5763
5764 /**
5765  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5766  * @adapter - pointer to the device adapter structure
5767  **/
5768 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5769 {
5770         struct ixgbe_hw *hw = &adapter->hw;
5771         int i;
5772
5773         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5774                 return;
5775
5776         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5777
5778         /* if interface is down do nothing */
5779         if (test_bit(__IXGBE_DOWN, &adapter->state))
5780                 return;
5781
5782         /* do nothing if we are not using signature filters */
5783         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5784                 return;
5785
5786         adapter->fdir_overflow++;
5787
5788         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5789                 for (i = 0; i < adapter->num_tx_queues; i++)
5790                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5791                                 &(adapter->tx_ring[i]->state));
5792                 /* re-enable flow director interrupts */
5793                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5794         } else {
5795                 e_err(probe, "failed to finish FDIR re-initialization, "
5796                       "ignored adding FDIR ATR filters\n");
5797         }
5798 }
5799
5800 /**
5801  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5802  * @adapter - pointer to the device adapter structure
5803  *
5804  * This function serves two purposes.  First it strobes the interrupt lines
5805  * in order to make certain interrupts are occuring.  Secondly it sets the
5806  * bits needed to check for TX hangs.  As a result we should immediately
5807  * determine if a hang has occured.
5808  */
5809 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5810 {
5811         struct ixgbe_hw *hw = &adapter->hw;
5812         u64 eics = 0;
5813         int i;
5814
5815         /* If we're down or resetting, just bail */
5816         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5817             test_bit(__IXGBE_RESETTING, &adapter->state))
5818                 return;
5819
5820         /* Force detection of hung controller */
5821         if (netif_carrier_ok(adapter->netdev)) {
5822                 for (i = 0; i < adapter->num_tx_queues; i++)
5823                         set_check_for_tx_hang(adapter->tx_ring[i]);
5824         }
5825
5826         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5827                 /*
5828                  * for legacy and MSI interrupts don't set any bits
5829                  * that are enabled for EIAM, because this operation
5830                  * would set *both* EIMS and EICS for any bit in EIAM
5831                  */
5832                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5833                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5834         } else {
5835                 /* get one bit for every active tx/rx interrupt vector */
5836                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5837                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
5838                         if (qv->rx.ring || qv->tx.ring)
5839                                 eics |= ((u64)1 << i);
5840                 }
5841         }
5842
5843         /* Cause software interrupt to ensure rings are cleaned */
5844         ixgbe_irq_rearm_queues(adapter, eics);
5845
5846 }
5847
5848 /**
5849  * ixgbe_watchdog_update_link - update the link status
5850  * @adapter - pointer to the device adapter structure
5851  * @link_speed - pointer to a u32 to store the link_speed
5852  **/
5853 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5854 {
5855         struct ixgbe_hw *hw = &adapter->hw;
5856         u32 link_speed = adapter->link_speed;
5857         bool link_up = adapter->link_up;
5858         int i;
5859
5860         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5861                 return;
5862
5863         if (hw->mac.ops.check_link) {
5864                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5865         } else {
5866                 /* always assume link is up, if no check link function */
5867                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5868                 link_up = true;
5869         }
5870         if (link_up) {
5871                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5872                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5873                                 hw->mac.ops.fc_enable(hw, i);
5874                 } else {
5875                         hw->mac.ops.fc_enable(hw, 0);
5876                 }
5877         }
5878
5879         if (link_up ||
5880             time_after(jiffies, (adapter->link_check_timeout +
5881                                  IXGBE_TRY_LINK_TIMEOUT))) {
5882                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5883                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5884                 IXGBE_WRITE_FLUSH(hw);
5885         }
5886
5887         adapter->link_up = link_up;
5888         adapter->link_speed = link_speed;
5889 }
5890
5891 /**
5892  * ixgbe_watchdog_link_is_up - update netif_carrier status and
5893  *                             print link up message
5894  * @adapter - pointer to the device adapter structure
5895  **/
5896 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5897 {
5898         struct net_device *netdev = adapter->netdev;
5899         struct ixgbe_hw *hw = &adapter->hw;
5900         u32 link_speed = adapter->link_speed;
5901         bool flow_rx, flow_tx;
5902
5903         /* only continue if link was previously down */
5904         if (netif_carrier_ok(netdev))
5905                 return;
5906
5907         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5908
5909         switch (hw->mac.type) {
5910         case ixgbe_mac_82598EB: {
5911                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5912                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5913                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5914                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5915         }
5916                 break;
5917         case ixgbe_mac_X540:
5918         case ixgbe_mac_82599EB: {
5919                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5920                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5921                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5922                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5923         }
5924                 break;
5925         default:
5926                 flow_tx = false;
5927                 flow_rx = false;
5928                 break;
5929         }
5930         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5931                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5932                "10 Gbps" :
5933                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5934                "1 Gbps" :
5935                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5936                "100 Mbps" :
5937                "unknown speed"))),
5938                ((flow_rx && flow_tx) ? "RX/TX" :
5939                (flow_rx ? "RX" :
5940                (flow_tx ? "TX" : "None"))));
5941
5942         netif_carrier_on(netdev);
5943         ixgbe_check_vf_rate_limit(adapter);
5944 }
5945
5946 /**
5947  * ixgbe_watchdog_link_is_down - update netif_carrier status and
5948  *                               print link down message
5949  * @adapter - pointer to the adapter structure
5950  **/
5951 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5952 {
5953         struct net_device *netdev = adapter->netdev;
5954         struct ixgbe_hw *hw = &adapter->hw;
5955
5956         adapter->link_up = false;
5957         adapter->link_speed = 0;
5958
5959         /* only continue if link was up previously */
5960         if (!netif_carrier_ok(netdev))
5961                 return;
5962
5963         /* poll for SFP+ cable when link is down */
5964         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5965                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5966
5967         e_info(drv, "NIC Link is Down\n");
5968         netif_carrier_off(netdev);
5969 }
5970
5971 /**
5972  * ixgbe_watchdog_flush_tx - flush queues on link down
5973  * @adapter - pointer to the device adapter structure
5974  **/
5975 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5976 {
5977         int i;
5978         int some_tx_pending = 0;
5979
5980         if (!netif_carrier_ok(adapter->netdev)) {
5981                 for (i = 0; i < adapter->num_tx_queues; i++) {
5982                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5983                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5984                                 some_tx_pending = 1;
5985                                 break;
5986                         }
5987                 }
5988
5989                 if (some_tx_pending) {
5990                         /* We've lost link, so the controller stops DMA,
5991                          * but we've got queued Tx work that's never going
5992                          * to get done, so reset controller to flush Tx.
5993                          * (Do the reset outside of interrupt context).
5994                          */
5995                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5996                 }
5997         }
5998 }
5999
6000 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6001 {
6002         u32 ssvpc;
6003
6004         /* Do not perform spoof check for 82598 */
6005         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6006                 return;
6007
6008         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6009
6010         /*
6011          * ssvpc register is cleared on read, if zero then no
6012          * spoofed packets in the last interval.
6013          */
6014         if (!ssvpc)
6015                 return;
6016
6017         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6018 }
6019
6020 /**
6021  * ixgbe_watchdog_subtask - check and bring link up
6022  * @adapter - pointer to the device adapter structure
6023  **/
6024 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6025 {
6026         /* if interface is down do nothing */
6027         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6028             test_bit(__IXGBE_RESETTING, &adapter->state))
6029                 return;
6030
6031         ixgbe_watchdog_update_link(adapter);
6032
6033         if (adapter->link_up)
6034                 ixgbe_watchdog_link_is_up(adapter);
6035         else
6036                 ixgbe_watchdog_link_is_down(adapter);
6037
6038         ixgbe_spoof_check(adapter);
6039         ixgbe_update_stats(adapter);
6040
6041         ixgbe_watchdog_flush_tx(adapter);
6042 }
6043
6044 /**
6045  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6046  * @adapter - the ixgbe adapter structure
6047  **/
6048 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6049 {
6050         struct ixgbe_hw *hw = &adapter->hw;
6051         s32 err;
6052
6053         /* not searching for SFP so there is nothing to do here */
6054         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6055             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6056                 return;
6057
6058         /* someone else is in init, wait until next service event */
6059         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6060                 return;
6061
6062         err = hw->phy.ops.identify_sfp(hw);
6063         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6064                 goto sfp_out;
6065
6066         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6067                 /* If no cable is present, then we need to reset
6068                  * the next time we find a good cable. */
6069                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6070         }
6071
6072         /* exit on error */
6073         if (err)
6074                 goto sfp_out;
6075
6076         /* exit if reset not needed */
6077         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6078                 goto sfp_out;
6079
6080         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6081
6082         /*
6083          * A module may be identified correctly, but the EEPROM may not have
6084          * support for that module.  setup_sfp() will fail in that case, so
6085          * we should not allow that module to load.
6086          */
6087         if (hw->mac.type == ixgbe_mac_82598EB)
6088                 err = hw->phy.ops.reset(hw);
6089         else
6090                 err = hw->mac.ops.setup_sfp(hw);
6091
6092         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6093                 goto sfp_out;
6094
6095         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6096         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6097
6098 sfp_out:
6099         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6100
6101         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6102             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6103                 e_dev_err("failed to initialize because an unsupported "
6104                           "SFP+ module type was detected.\n");
6105                 e_dev_err("Reload the driver after installing a "
6106                           "supported module.\n");
6107                 unregister_netdev(adapter->netdev);
6108         }
6109 }
6110
6111 /**
6112  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6113  * @adapter - the ixgbe adapter structure
6114  **/
6115 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6116 {
6117         struct ixgbe_hw *hw = &adapter->hw;
6118         u32 autoneg;
6119         bool negotiation;
6120
6121         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6122                 return;
6123
6124         /* someone else is in init, wait until next service event */
6125         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6126                 return;
6127
6128         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6129
6130         autoneg = hw->phy.autoneg_advertised;
6131         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6132                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6133         if (hw->mac.ops.setup_link)
6134                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6135
6136         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6137         adapter->link_check_timeout = jiffies;
6138         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6139 }
6140
6141 #ifdef CONFIG_PCI_IOV
6142 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6143 {
6144         int vf;
6145         struct ixgbe_hw *hw = &adapter->hw;
6146         struct net_device *netdev = adapter->netdev;
6147         u32 gpc;
6148         u32 ciaa, ciad;
6149
6150         gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6151         if (gpc) /* If incrementing then no need for the check below */
6152                 return;
6153         /*
6154          * Check to see if a bad DMA write target from an errant or
6155          * malicious VF has caused a PCIe error.  If so then we can
6156          * issue a VFLR to the offending VF(s) and then resume without
6157          * requesting a full slot reset.
6158          */
6159
6160         for (vf = 0; vf < adapter->num_vfs; vf++) {
6161                 ciaa = (vf << 16) | 0x80000000;
6162                 /* 32 bit read so align, we really want status at offset 6 */
6163                 ciaa |= PCI_COMMAND;
6164                 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6165                 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6166                 ciaa &= 0x7FFFFFFF;
6167                 /* disable debug mode asap after reading data */
6168                 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6169                 /* Get the upper 16 bits which will be the PCI status reg */
6170                 ciad >>= 16;
6171                 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6172                         netdev_err(netdev, "VF %d Hung DMA\n", vf);
6173                         /* Issue VFLR */
6174                         ciaa = (vf << 16) | 0x80000000;
6175                         ciaa |= 0xA8;
6176                         IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6177                         ciad = 0x00008000;  /* VFLR */
6178                         IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6179                         ciaa &= 0x7FFFFFFF;
6180                         IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6181                 }
6182         }
6183 }
6184
6185 #endif
6186 /**
6187  * ixgbe_service_timer - Timer Call-back
6188  * @data: pointer to adapter cast into an unsigned long
6189  **/
6190 static void ixgbe_service_timer(unsigned long data)
6191 {
6192         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6193         unsigned long next_event_offset;
6194         bool ready = true;
6195
6196 #ifdef CONFIG_PCI_IOV
6197         ready = false;
6198
6199         /*
6200          * don't bother with SR-IOV VF DMA hang check if there are
6201          * no VFs or the link is down
6202          */
6203         if (!adapter->num_vfs ||
6204             (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6205                 ready = true;
6206                 goto normal_timer_service;
6207         }
6208
6209         /* If we have VFs allocated then we must check for DMA hangs */
6210         ixgbe_check_for_bad_vf(adapter);
6211         next_event_offset = HZ / 50;
6212         adapter->timer_event_accumulator++;
6213
6214         if (adapter->timer_event_accumulator >= 100) {
6215                 ready = true;
6216                 adapter->timer_event_accumulator = 0;
6217         }
6218
6219         goto schedule_event;
6220
6221 normal_timer_service:
6222 #endif
6223         /* poll faster when waiting for link */
6224         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6225                 next_event_offset = HZ / 10;
6226         else
6227                 next_event_offset = HZ * 2;
6228
6229 #ifdef CONFIG_PCI_IOV
6230 schedule_event:
6231 #endif
6232         /* Reset the timer */
6233         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6234
6235         if (ready)
6236                 ixgbe_service_event_schedule(adapter);
6237 }
6238
6239 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6240 {
6241         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6242                 return;
6243
6244         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6245
6246         /* If we're already down or resetting, just bail */
6247         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6248             test_bit(__IXGBE_RESETTING, &adapter->state))
6249                 return;
6250
6251         ixgbe_dump(adapter);
6252         netdev_err(adapter->netdev, "Reset adapter\n");
6253         adapter->tx_timeout_count++;
6254
6255         ixgbe_reinit_locked(adapter);
6256 }
6257
6258 /**
6259  * ixgbe_service_task - manages and runs subtasks
6260  * @work: pointer to work_struct containing our data
6261  **/
6262 static void ixgbe_service_task(struct work_struct *work)
6263 {
6264         struct ixgbe_adapter *adapter = container_of(work,
6265                                                      struct ixgbe_adapter,
6266                                                      service_task);
6267
6268         ixgbe_reset_subtask(adapter);
6269         ixgbe_sfp_detection_subtask(adapter);
6270         ixgbe_sfp_link_config_subtask(adapter);
6271         ixgbe_check_overtemp_subtask(adapter);
6272         ixgbe_watchdog_subtask(adapter);
6273         ixgbe_fdir_reinit_subtask(adapter);
6274         ixgbe_check_hang_subtask(adapter);
6275
6276         ixgbe_service_event_complete(adapter);
6277 }
6278
6279 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6280                        u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6281 {
6282         struct ixgbe_adv_tx_context_desc *context_desc;
6283         u16 i = tx_ring->next_to_use;
6284
6285         context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6286
6287         i++;
6288         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6289
6290         /* set bits to identify this as an advanced context descriptor */
6291         type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6292
6293         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
6294         context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
6295         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
6296         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
6297 }
6298
6299 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6300                      u32 tx_flags, __be16 protocol, u8 *hdr_len)
6301 {
6302         int err;
6303         u32 vlan_macip_lens, type_tucmd;
6304         u32 mss_l4len_idx, l4len;
6305
6306         if (!skb_is_gso(skb))
6307                 return 0;
6308
6309         if (skb_header_cloned(skb)) {
6310                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6311                 if (err)
6312                         return err;
6313         }
6314
6315         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6316         type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6317
6318         if (protocol == __constant_htons(ETH_P_IP)) {
6319                 struct iphdr *iph = ip_hdr(skb);
6320                 iph->tot_len = 0;
6321                 iph->check = 0;
6322                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6323                                                          iph->daddr, 0,
6324                                                          IPPROTO_TCP,
6325                                                          0);
6326                 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6327         } else if (skb_is_gso_v6(skb)) {
6328                 ipv6_hdr(skb)->payload_len = 0;
6329                 tcp_hdr(skb)->check =
6330                     ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6331                                      &ipv6_hdr(skb)->daddr,
6332                                      0, IPPROTO_TCP, 0);
6333         }
6334
6335         l4len = tcp_hdrlen(skb);
6336         *hdr_len = skb_transport_offset(skb) + l4len;
6337
6338         /* mss_l4len_id: use 1 as index for TSO */
6339         mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6340         mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6341         mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6342
6343         /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6344         vlan_macip_lens = skb_network_header_len(skb);
6345         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6346         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6347
6348         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6349                           mss_l4len_idx);
6350
6351         return 1;
6352 }
6353
6354 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6355                           struct sk_buff *skb, u32 tx_flags,
6356                           __be16 protocol)
6357 {
6358         u32 vlan_macip_lens = 0;
6359         u32 mss_l4len_idx = 0;
6360         u32 type_tucmd = 0;
6361
6362         if (skb->ip_summed != CHECKSUM_PARTIAL) {
6363             if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6364                 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6365                         return false;
6366         } else {
6367                 u8 l4_hdr = 0;
6368                 switch (protocol) {
6369                 case __constant_htons(ETH_P_IP):
6370                         vlan_macip_lens |= skb_network_header_len(skb);
6371                         type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6372                         l4_hdr = ip_hdr(skb)->protocol;
6373                         break;
6374                 case __constant_htons(ETH_P_IPV6):
6375                         vlan_macip_lens |= skb_network_header_len(skb);
6376                         l4_hdr = ipv6_hdr(skb)->nexthdr;
6377                         break;
6378                 default:
6379                         if (unlikely(net_ratelimit())) {
6380                                 dev_warn(tx_ring->dev,
6381                                  "partial checksum but proto=%x!\n",
6382                                  skb->protocol);
6383                         }
6384                         break;
6385                 }
6386
6387                 switch (l4_hdr) {
6388                 case IPPROTO_TCP:
6389                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6390                         mss_l4len_idx = tcp_hdrlen(skb) <<
6391                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6392                         break;
6393                 case IPPROTO_SCTP:
6394                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6395                         mss_l4len_idx = sizeof(struct sctphdr) <<
6396                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6397                         break;
6398                 case IPPROTO_UDP:
6399                         mss_l4len_idx = sizeof(struct udphdr) <<
6400                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6401                         break;
6402                 default:
6403                         if (unlikely(net_ratelimit())) {
6404                                 dev_warn(tx_ring->dev,
6405                                  "partial checksum but l4 proto=%x!\n",
6406                                  skb->protocol);
6407                         }
6408                         break;
6409                 }
6410         }
6411
6412         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6413         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6414
6415         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6416                           type_tucmd, mss_l4len_idx);
6417
6418         return (skb->ip_summed == CHECKSUM_PARTIAL);
6419 }
6420
6421 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6422 {
6423         /* set type for advanced descriptor with frame checksum insertion */
6424         __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6425                                       IXGBE_ADVTXD_DCMD_IFCS |
6426                                       IXGBE_ADVTXD_DCMD_DEXT);
6427
6428         /* set HW vlan bit if vlan is present */
6429         if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6430                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6431
6432         /* set segmentation enable bits for TSO/FSO */
6433 #ifdef IXGBE_FCOE
6434         if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6435 #else
6436         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6437 #endif
6438                 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6439
6440         return cmd_type;
6441 }
6442
6443 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6444 {
6445         __le32 olinfo_status =
6446                 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6447
6448         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6449                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6450                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6451                 /* enble IPv4 checksum for TSO */
6452                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6453                         olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6454         }
6455
6456         /* enable L4 checksum for TSO and TX checksum offload */
6457         if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6458                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6459
6460 #ifdef IXGBE_FCOE
6461         /* use index 1 context for FCOE/FSO */
6462         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6463                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6464                                             (1 << IXGBE_ADVTXD_IDX_SHIFT));
6465
6466 #endif
6467         /*
6468          * Check Context must be set if Tx switch is enabled, which it
6469          * always is for case where virtual functions are running
6470          */
6471         if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6472                 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6473
6474         return olinfo_status;
6475 }
6476
6477 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6478                        IXGBE_TXD_CMD_RS)
6479
6480 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6481                          struct sk_buff *skb,
6482                          struct ixgbe_tx_buffer *first,
6483                          u32 tx_flags,
6484                          const u8 hdr_len)
6485 {
6486         struct device *dev = tx_ring->dev;
6487         struct ixgbe_tx_buffer *tx_buffer_info;
6488         union ixgbe_adv_tx_desc *tx_desc;
6489         dma_addr_t dma;
6490         __le32 cmd_type, olinfo_status;
6491         struct skb_frag_struct *frag;
6492         unsigned int f = 0;
6493         unsigned int data_len = skb->data_len;
6494         unsigned int size = skb_headlen(skb);
6495         u32 offset = 0;
6496         u32 paylen = skb->len - hdr_len;
6497         u16 i = tx_ring->next_to_use;
6498         u16 gso_segs;
6499
6500 #ifdef IXGBE_FCOE
6501         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6502                 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6503                         data_len -= sizeof(struct fcoe_crc_eof);
6504                 } else {
6505                         size -= sizeof(struct fcoe_crc_eof) - data_len;
6506                         data_len = 0;
6507                 }
6508         }
6509
6510 #endif
6511         dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6512         if (dma_mapping_error(dev, dma))
6513                 goto dma_error;
6514
6515         cmd_type = ixgbe_tx_cmd_type(tx_flags);
6516         olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6517
6518         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6519
6520         for (;;) {
6521                 while (size > IXGBE_MAX_DATA_PER_TXD) {
6522                         tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6523                         tx_desc->read.cmd_type_len =
6524                                 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6525                         tx_desc->read.olinfo_status = olinfo_status;
6526
6527                         offset += IXGBE_MAX_DATA_PER_TXD;
6528                         size -= IXGBE_MAX_DATA_PER_TXD;
6529
6530                         tx_desc++;
6531                         i++;
6532                         if (i == tx_ring->count) {
6533                                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6534                                 i = 0;
6535                         }
6536                 }
6537
6538                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6539                 tx_buffer_info->length = offset + size;
6540                 tx_buffer_info->tx_flags = tx_flags;
6541                 tx_buffer_info->dma = dma;
6542
6543                 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6544                 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6545                 tx_desc->read.olinfo_status = olinfo_status;
6546
6547                 if (!data_len)
6548                         break;
6549
6550                 frag = &skb_shinfo(skb)->frags[f];
6551 #ifdef IXGBE_FCOE
6552                 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6553 #else
6554                 size = skb_frag_size(frag);
6555 #endif
6556                 data_len -= size;
6557                 f++;
6558
6559                 offset = 0;
6560                 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6561
6562                 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
6563                 if (dma_mapping_error(dev, dma))
6564                         goto dma_error;
6565
6566                 tx_desc++;
6567                 i++;
6568                 if (i == tx_ring->count) {
6569                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6570                         i = 0;
6571                 }
6572         }
6573
6574         tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6575
6576         i++;
6577         if (i == tx_ring->count)
6578                 i = 0;
6579
6580         tx_ring->next_to_use = i;
6581
6582         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6583                 gso_segs = skb_shinfo(skb)->gso_segs;
6584 #ifdef IXGBE_FCOE
6585         /* adjust for FCoE Sequence Offload */
6586         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6587                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6588                                         skb_shinfo(skb)->gso_size);
6589 #endif /* IXGBE_FCOE */
6590         else
6591                 gso_segs = 1;
6592
6593         /* multiply data chunks by size of headers */
6594         tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6595         tx_buffer_info->gso_segs = gso_segs;
6596         tx_buffer_info->skb = skb;
6597
6598         /* set the timestamp */
6599         first->time_stamp = jiffies;
6600
6601         /*
6602          * Force memory writes to complete before letting h/w
6603          * know there are new descriptors to fetch.  (Only
6604          * applicable for weak-ordered memory model archs,
6605          * such as IA-64).
6606          */
6607         wmb();
6608
6609         /* set next_to_watch value indicating a packet is present */
6610         first->next_to_watch = tx_desc;
6611
6612         /* notify HW of packet */
6613         writel(i, tx_ring->tail);
6614
6615         return;
6616 dma_error:
6617         dev_err(dev, "TX DMA map failed\n");
6618
6619         /* clear dma mappings for failed tx_buffer_info map */
6620         for (;;) {
6621                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6622                 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6623                 if (tx_buffer_info == first)
6624                         break;
6625                 if (i == 0)
6626                         i = tx_ring->count;
6627                 i--;
6628         }
6629
6630         dev_kfree_skb_any(skb);
6631
6632         tx_ring->next_to_use = i;
6633 }
6634
6635 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6636                       u32 tx_flags, __be16 protocol)
6637 {
6638         struct ixgbe_q_vector *q_vector = ring->q_vector;
6639         union ixgbe_atr_hash_dword input = { .dword = 0 };
6640         union ixgbe_atr_hash_dword common = { .dword = 0 };
6641         union {
6642                 unsigned char *network;
6643                 struct iphdr *ipv4;
6644                 struct ipv6hdr *ipv6;
6645         } hdr;
6646         struct tcphdr *th;
6647         __be16 vlan_id;
6648
6649         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6650         if (!q_vector)
6651                 return;
6652
6653         /* do nothing if sampling is disabled */
6654         if (!ring->atr_sample_rate)
6655                 return;
6656
6657         ring->atr_count++;
6658
6659         /* snag network header to get L4 type and address */
6660         hdr.network = skb_network_header(skb);
6661
6662         /* Currently only IPv4/IPv6 with TCP is supported */
6663         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6664              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6665             (protocol != __constant_htons(ETH_P_IP) ||
6666              hdr.ipv4->protocol != IPPROTO_TCP))
6667                 return;
6668
6669         th = tcp_hdr(skb);
6670
6671         /* skip this packet since it is invalid or the socket is closing */
6672         if (!th || th->fin)
6673                 return;
6674
6675         /* sample on all syn packets or once every atr sample count */
6676         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6677                 return;
6678
6679         /* reset sample count */
6680         ring->atr_count = 0;
6681
6682         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6683
6684         /*
6685          * src and dst are inverted, think how the receiver sees them
6686          *
6687          * The input is broken into two sections, a non-compressed section
6688          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6689          * is XORed together and stored in the compressed dword.
6690          */
6691         input.formatted.vlan_id = vlan_id;
6692
6693         /*
6694          * since src port and flex bytes occupy the same word XOR them together
6695          * and write the value to source port portion of compressed dword
6696          */
6697         if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6698                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6699         else
6700                 common.port.src ^= th->dest ^ protocol;
6701         common.port.dst ^= th->source;
6702
6703         if (protocol == __constant_htons(ETH_P_IP)) {
6704                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6705                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6706         } else {
6707                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6708                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6709                              hdr.ipv6->saddr.s6_addr32[1] ^
6710                              hdr.ipv6->saddr.s6_addr32[2] ^
6711                              hdr.ipv6->saddr.s6_addr32[3] ^
6712                              hdr.ipv6->daddr.s6_addr32[0] ^
6713                              hdr.ipv6->daddr.s6_addr32[1] ^
6714                              hdr.ipv6->daddr.s6_addr32[2] ^
6715                              hdr.ipv6->daddr.s6_addr32[3];
6716         }
6717
6718         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6719         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6720                                               input, common, ring->queue_index);
6721 }
6722
6723 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6724 {
6725         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6726         /* Herbert's original patch had:
6727          *  smp_mb__after_netif_stop_queue();
6728          * but since that doesn't exist yet, just open code it. */
6729         smp_mb();
6730
6731         /* We need to check again in a case another CPU has just
6732          * made room available. */
6733         if (likely(ixgbe_desc_unused(tx_ring) < size))
6734                 return -EBUSY;
6735
6736         /* A reprieve! - use start_queue because it doesn't call schedule */
6737         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6738         ++tx_ring->tx_stats.restart_queue;
6739         return 0;
6740 }
6741
6742 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6743 {
6744         if (likely(ixgbe_desc_unused(tx_ring) >= size))
6745                 return 0;
6746         return __ixgbe_maybe_stop_tx(tx_ring, size);
6747 }
6748
6749 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6750 {
6751         struct ixgbe_adapter *adapter = netdev_priv(dev);
6752         int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6753                                                smp_processor_id();
6754 #ifdef IXGBE_FCOE
6755         __be16 protocol = vlan_get_protocol(skb);
6756
6757         if (((protocol == htons(ETH_P_FCOE)) ||
6758             (protocol == htons(ETH_P_FIP))) &&
6759             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6760                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6761                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6762                 return txq;
6763         }
6764 #endif
6765
6766         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6767                 while (unlikely(txq >= dev->real_num_tx_queues))
6768                         txq -= dev->real_num_tx_queues;
6769                 return txq;
6770         }
6771
6772         return skb_tx_hash(dev, skb);
6773 }
6774
6775 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6776                           struct ixgbe_adapter *adapter,
6777                           struct ixgbe_ring *tx_ring)
6778 {
6779         struct ixgbe_tx_buffer *first;
6780         int tso;
6781         u32 tx_flags = 0;
6782 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6783         unsigned short f;
6784 #endif
6785         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6786         __be16 protocol = skb->protocol;
6787         u8 hdr_len = 0;
6788
6789         /*
6790          * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6791          *       + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6792          *       + 2 desc gap to keep tail from touching head,
6793          *       + 1 desc for context descriptor,
6794          * otherwise try next time
6795          */
6796 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6797         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6798                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6799 #else
6800         count += skb_shinfo(skb)->nr_frags;
6801 #endif
6802         if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6803                 tx_ring->tx_stats.tx_busy++;
6804                 return NETDEV_TX_BUSY;
6805         }
6806
6807 #ifdef CONFIG_PCI_IOV
6808         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6809                 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6810
6811 #endif
6812         /* if we have a HW VLAN tag being added default to the HW one */
6813         if (vlan_tx_tag_present(skb)) {
6814                 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6815                 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6816         /* else if it is a SW VLAN check the next protocol and store the tag */
6817         } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6818                 struct vlan_hdr *vhdr, _vhdr;
6819                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6820                 if (!vhdr)
6821                         goto out_drop;
6822
6823                 protocol = vhdr->h_vlan_encapsulated_proto;
6824                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6825                 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6826         }
6827
6828         /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6829         if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6830             ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6831              (skb->priority != TC_PRIO_CONTROL))) {
6832                 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6833                 tx_flags |= (skb->priority & 0x7) <<
6834                                         IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6835                 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6836                         struct vlan_ethhdr *vhdr;
6837                         if (skb_header_cloned(skb) &&
6838                             pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6839                                 goto out_drop;
6840                         vhdr = (struct vlan_ethhdr *)skb->data;
6841                         vhdr->h_vlan_TCI = htons(tx_flags >>
6842                                                  IXGBE_TX_FLAGS_VLAN_SHIFT);
6843                 } else {
6844                         tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6845                 }
6846         }
6847
6848         /* record the location of the first descriptor for this packet */
6849         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6850
6851 #ifdef IXGBE_FCOE
6852         /* setup tx offload for FCoE */
6853         if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6854             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6855                 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6856                 if (tso < 0)
6857                         goto out_drop;
6858                 else if (tso)
6859                         tx_flags |= IXGBE_TX_FLAGS_FSO |
6860                                     IXGBE_TX_FLAGS_FCOE;
6861                 else
6862                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6863
6864                 goto xmit_fcoe;
6865         }
6866
6867 #endif /* IXGBE_FCOE */
6868         /* setup IPv4/IPv6 offloads */
6869         if (protocol == __constant_htons(ETH_P_IP))
6870                 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6871
6872         tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6873         if (tso < 0)
6874                 goto out_drop;
6875         else if (tso)
6876                 tx_flags |= IXGBE_TX_FLAGS_TSO;
6877         else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6878                 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6879
6880         /* add the ATR filter if ATR is on */
6881         if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6882                 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6883
6884 #ifdef IXGBE_FCOE
6885 xmit_fcoe:
6886 #endif /* IXGBE_FCOE */
6887         ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6888
6889         ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6890
6891         return NETDEV_TX_OK;
6892
6893 out_drop:
6894         dev_kfree_skb_any(skb);
6895         return NETDEV_TX_OK;
6896 }
6897
6898 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6899 {
6900         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6901         struct ixgbe_ring *tx_ring;
6902
6903         tx_ring = adapter->tx_ring[skb->queue_mapping];
6904         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6905 }
6906
6907 /**
6908  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6909  * @netdev: network interface device structure
6910  * @p: pointer to an address structure
6911  *
6912  * Returns 0 on success, negative on failure
6913  **/
6914 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6915 {
6916         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6917         struct ixgbe_hw *hw = &adapter->hw;
6918         struct sockaddr *addr = p;
6919
6920         if (!is_valid_ether_addr(addr->sa_data))
6921                 return -EADDRNOTAVAIL;
6922
6923         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6924         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6925
6926         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6927                             IXGBE_RAH_AV);
6928
6929         return 0;
6930 }
6931
6932 static int
6933 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6934 {
6935         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6936         struct ixgbe_hw *hw = &adapter->hw;
6937         u16 value;
6938         int rc;
6939
6940         if (prtad != hw->phy.mdio.prtad)
6941                 return -EINVAL;
6942         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6943         if (!rc)
6944                 rc = value;
6945         return rc;
6946 }
6947
6948 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6949                             u16 addr, u16 value)
6950 {
6951         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6952         struct ixgbe_hw *hw = &adapter->hw;
6953
6954         if (prtad != hw->phy.mdio.prtad)
6955                 return -EINVAL;
6956         return hw->phy.ops.write_reg(hw, addr, devad, value);
6957 }
6958
6959 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6960 {
6961         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6962
6963         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6964 }
6965
6966 /**
6967  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6968  * netdev->dev_addrs
6969  * @netdev: network interface device structure
6970  *
6971  * Returns non-zero on failure
6972  **/
6973 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6974 {
6975         int err = 0;
6976         struct ixgbe_adapter *adapter = netdev_priv(dev);
6977         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6978
6979         if (is_valid_ether_addr(mac->san_addr)) {
6980                 rtnl_lock();
6981                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6982                 rtnl_unlock();
6983         }
6984         return err;
6985 }
6986
6987 /**
6988  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6989  * netdev->dev_addrs
6990  * @netdev: network interface device structure
6991  *
6992  * Returns non-zero on failure
6993  **/
6994 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6995 {
6996         int err = 0;
6997         struct ixgbe_adapter *adapter = netdev_priv(dev);
6998         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6999
7000         if (is_valid_ether_addr(mac->san_addr)) {
7001                 rtnl_lock();
7002                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7003                 rtnl_unlock();
7004         }
7005         return err;
7006 }
7007
7008 #ifdef CONFIG_NET_POLL_CONTROLLER
7009 /*
7010  * Polling 'interrupt' - used by things like netconsole to send skbs
7011  * without having to re-enable interrupts. It's not called while
7012  * the interrupt routine is executing.
7013  */
7014 static void ixgbe_netpoll(struct net_device *netdev)
7015 {
7016         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7017         int i;
7018
7019         /* if interface is down do nothing */
7020         if (test_bit(__IXGBE_DOWN, &adapter->state))
7021                 return;
7022
7023         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7024         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7025                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7026                 for (i = 0; i < num_q_vectors; i++) {
7027                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7028                         ixgbe_msix_clean_rings(0, q_vector);
7029                 }
7030         } else {
7031                 ixgbe_intr(adapter->pdev->irq, netdev);
7032         }
7033         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7034 }
7035 #endif
7036
7037 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7038                                                    struct rtnl_link_stats64 *stats)
7039 {
7040         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7041         int i;
7042
7043         rcu_read_lock();
7044         for (i = 0; i < adapter->num_rx_queues; i++) {
7045                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7046                 u64 bytes, packets;
7047                 unsigned int start;
7048
7049                 if (ring) {
7050                         do {
7051                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7052                                 packets = ring->stats.packets;
7053                                 bytes   = ring->stats.bytes;
7054                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7055                         stats->rx_packets += packets;
7056                         stats->rx_bytes   += bytes;
7057                 }
7058         }
7059
7060         for (i = 0; i < adapter->num_tx_queues; i++) {
7061                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7062                 u64 bytes, packets;
7063                 unsigned int start;
7064
7065                 if (ring) {
7066                         do {
7067                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7068                                 packets = ring->stats.packets;
7069                                 bytes   = ring->stats.bytes;
7070                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7071                         stats->tx_packets += packets;
7072                         stats->tx_bytes   += bytes;
7073                 }
7074         }
7075         rcu_read_unlock();
7076         /* following stats updated by ixgbe_watchdog_task() */
7077         stats->multicast        = netdev->stats.multicast;
7078         stats->rx_errors        = netdev->stats.rx_errors;
7079         stats->rx_length_errors = netdev->stats.rx_length_errors;
7080         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
7081         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7082         return stats;
7083 }
7084
7085 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7086  * #adapter: pointer to ixgbe_adapter
7087  * @tc: number of traffic classes currently enabled
7088  *
7089  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7090  * 802.1Q priority maps to a packet buffer that exists.
7091  */
7092 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7093 {
7094         struct ixgbe_hw *hw = &adapter->hw;
7095         u32 reg, rsave;
7096         int i;
7097
7098         /* 82598 have a static priority to TC mapping that can not
7099          * be changed so no validation is needed.
7100          */
7101         if (hw->mac.type == ixgbe_mac_82598EB)
7102                 return;
7103
7104         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7105         rsave = reg;
7106
7107         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7108                 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7109
7110                 /* If up2tc is out of bounds default to zero */
7111                 if (up2tc > tc)
7112                         reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7113         }
7114
7115         if (reg != rsave)
7116                 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7117
7118         return;
7119 }
7120
7121
7122 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7123  * classes.
7124  *
7125  * @netdev: net device to configure
7126  * @tc: number of traffic classes to enable
7127  */
7128 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7129 {
7130         struct ixgbe_adapter *adapter = netdev_priv(dev);
7131         struct ixgbe_hw *hw = &adapter->hw;
7132
7133         /* Multiple traffic classes requires multiple queues */
7134         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7135                 e_err(drv, "Enable failed, needs MSI-X\n");
7136                 return -EINVAL;
7137         }
7138
7139         /* Hardware supports up to 8 traffic classes */
7140         if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7141             (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7142                 return -EINVAL;
7143
7144         /* Hardware has to reinitialize queues and interrupts to
7145          * match packet buffer alignment. Unfortunantly, the
7146          * hardware is not flexible enough to do this dynamically.
7147          */
7148         if (netif_running(dev))
7149                 ixgbe_close(dev);
7150         ixgbe_clear_interrupt_scheme(adapter);
7151
7152         if (tc) {
7153                 netdev_set_num_tc(dev, tc);
7154                 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7155
7156                 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7157                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7158
7159                 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7160                         adapter->hw.fc.requested_mode = ixgbe_fc_none;
7161         } else {
7162                 netdev_reset_tc(dev);
7163
7164                 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7165
7166                 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7167                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7168
7169                 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7170                 adapter->dcb_cfg.pfc_mode_enable = false;
7171         }
7172
7173         ixgbe_init_interrupt_scheme(adapter);
7174         ixgbe_validate_rtr(adapter, tc);
7175         if (netif_running(dev))
7176                 ixgbe_open(dev);
7177
7178         return 0;
7179 }
7180
7181 void ixgbe_do_reset(struct net_device *netdev)
7182 {
7183         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7184
7185         if (netif_running(netdev))
7186                 ixgbe_reinit_locked(adapter);
7187         else
7188                 ixgbe_reset(adapter);
7189 }
7190
7191 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7192 {
7193         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7194
7195 #ifdef CONFIG_DCB
7196         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7197                 data &= ~NETIF_F_HW_VLAN_RX;
7198 #endif
7199
7200         /* return error if RXHASH is being enabled when RSS is not supported */
7201         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7202                 data &= ~NETIF_F_RXHASH;
7203
7204         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7205         if (!(data & NETIF_F_RXCSUM))
7206                 data &= ~NETIF_F_LRO;
7207
7208         /* Turn off LRO if not RSC capable or invalid ITR settings */
7209         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7210                 data &= ~NETIF_F_LRO;
7211         } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7212                    (adapter->rx_itr_setting != 1 &&
7213                     adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7214                 data &= ~NETIF_F_LRO;
7215                 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7216         }
7217
7218         return data;
7219 }
7220
7221 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7222 {
7223         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7224         bool need_reset = false;
7225
7226         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7227         if (!(data & NETIF_F_RXCSUM))
7228                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7229         else
7230                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7231
7232         /* Make sure RSC matches LRO, reset if change */
7233         if (!!(data & NETIF_F_LRO) !=
7234              !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7235                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7236                 switch (adapter->hw.mac.type) {
7237                 case ixgbe_mac_X540:
7238                 case ixgbe_mac_82599EB:
7239                         need_reset = true;
7240                         break;
7241                 default:
7242                         break;
7243                 }
7244         }
7245
7246         /*
7247          * Check if Flow Director n-tuple support was enabled or disabled.  If
7248          * the state changed, we need to reset.
7249          */
7250         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7251                 /* turn off ATR, enable perfect filters and reset */
7252                 if (data & NETIF_F_NTUPLE) {
7253                         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7254                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7255                         need_reset = true;
7256                 }
7257         } else if (!(data & NETIF_F_NTUPLE)) {
7258                 /* turn off Flow Director, set ATR and reset */
7259                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7260                 if ((adapter->flags &  IXGBE_FLAG_RSS_ENABLED) &&
7261                     !(adapter->flags &  IXGBE_FLAG_DCB_ENABLED))
7262                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7263                 need_reset = true;
7264         }
7265
7266         if (need_reset)
7267                 ixgbe_do_reset(netdev);
7268
7269         return 0;
7270
7271 }
7272
7273 static const struct net_device_ops ixgbe_netdev_ops = {
7274         .ndo_open               = ixgbe_open,
7275         .ndo_stop               = ixgbe_close,
7276         .ndo_start_xmit         = ixgbe_xmit_frame,
7277         .ndo_select_queue       = ixgbe_select_queue,
7278         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7279         .ndo_validate_addr      = eth_validate_addr,
7280         .ndo_set_mac_address    = ixgbe_set_mac,
7281         .ndo_change_mtu         = ixgbe_change_mtu,
7282         .ndo_tx_timeout         = ixgbe_tx_timeout,
7283         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7284         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7285         .ndo_do_ioctl           = ixgbe_ioctl,
7286         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7287         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7288         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7289         .ndo_set_vf_spoofchk    = ixgbe_ndo_set_vf_spoofchk,
7290         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7291         .ndo_get_stats64        = ixgbe_get_stats64,
7292         .ndo_setup_tc           = ixgbe_setup_tc,
7293 #ifdef CONFIG_NET_POLL_CONTROLLER
7294         .ndo_poll_controller    = ixgbe_netpoll,
7295 #endif
7296 #ifdef IXGBE_FCOE
7297         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7298         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7299         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7300         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7301         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7302         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7303 #endif /* IXGBE_FCOE */
7304         .ndo_set_features = ixgbe_set_features,
7305         .ndo_fix_features = ixgbe_fix_features,
7306 };
7307
7308 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7309                            const struct ixgbe_info *ii)
7310 {
7311 #ifdef CONFIG_PCI_IOV
7312         struct ixgbe_hw *hw = &adapter->hw;
7313
7314         if (hw->mac.type == ixgbe_mac_82598EB)
7315                 return;
7316
7317         /* The 82599 supports up to 64 VFs per physical function
7318          * but this implementation limits allocation to 63 so that
7319          * basic networking resources are still available to the
7320          * physical function
7321          */
7322         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7323         ixgbe_enable_sriov(adapter, ii);
7324 #endif /* CONFIG_PCI_IOV */
7325 }
7326
7327 /**
7328  * ixgbe_probe - Device Initialization Routine
7329  * @pdev: PCI device information struct
7330  * @ent: entry in ixgbe_pci_tbl
7331  *
7332  * Returns 0 on success, negative on failure
7333  *
7334  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7335  * The OS initialization, configuring of the adapter private structure,
7336  * and a hardware reset occur.
7337  **/
7338 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7339                                  const struct pci_device_id *ent)
7340 {
7341         struct net_device *netdev;
7342         struct ixgbe_adapter *adapter = NULL;
7343         struct ixgbe_hw *hw;
7344         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7345         static int cards_found;
7346         int i, err, pci_using_dac;
7347         u8 part_str[IXGBE_PBANUM_LENGTH];
7348         unsigned int indices = num_possible_cpus();
7349 #ifdef IXGBE_FCOE
7350         u16 device_caps;
7351 #endif
7352         u32 eec;
7353         u16 wol_cap;
7354
7355         /* Catch broken hardware that put the wrong VF device ID in
7356          * the PCIe SR-IOV capability.
7357          */
7358         if (pdev->is_virtfn) {
7359                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7360                      pci_name(pdev), pdev->vendor, pdev->device);
7361                 return -EINVAL;
7362         }
7363
7364         err = pci_enable_device_mem(pdev);
7365         if (err)
7366                 return err;
7367
7368         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7369             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7370                 pci_using_dac = 1;
7371         } else {
7372                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7373                 if (err) {
7374                         err = dma_set_coherent_mask(&pdev->dev,
7375                                                     DMA_BIT_MASK(32));
7376                         if (err) {
7377                                 dev_err(&pdev->dev,
7378                                         "No usable DMA configuration, aborting\n");
7379                                 goto err_dma;
7380                         }
7381                 }
7382                 pci_using_dac = 0;
7383         }
7384
7385         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7386                                            IORESOURCE_MEM), ixgbe_driver_name);
7387         if (err) {
7388                 dev_err(&pdev->dev,
7389                         "pci_request_selected_regions failed 0x%x\n", err);
7390                 goto err_pci_reg;
7391         }
7392
7393         pci_enable_pcie_error_reporting(pdev);
7394
7395         pci_set_master(pdev);
7396         pci_save_state(pdev);
7397
7398 #ifdef CONFIG_IXGBE_DCB
7399         indices *= MAX_TRAFFIC_CLASS;
7400 #endif
7401
7402         if (ii->mac == ixgbe_mac_82598EB)
7403                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7404         else
7405                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7406
7407 #ifdef IXGBE_FCOE
7408         indices += min_t(unsigned int, num_possible_cpus(),
7409                          IXGBE_MAX_FCOE_INDICES);
7410 #endif
7411         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7412         if (!netdev) {
7413                 err = -ENOMEM;
7414                 goto err_alloc_etherdev;
7415         }
7416
7417         SET_NETDEV_DEV(netdev, &pdev->dev);
7418
7419         adapter = netdev_priv(netdev);
7420         pci_set_drvdata(pdev, adapter);
7421
7422         adapter->netdev = netdev;
7423         adapter->pdev = pdev;
7424         hw = &adapter->hw;
7425         hw->back = adapter;
7426         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7427
7428         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7429                               pci_resource_len(pdev, 0));
7430         if (!hw->hw_addr) {
7431                 err = -EIO;
7432                 goto err_ioremap;
7433         }
7434
7435         for (i = 1; i <= 5; i++) {
7436                 if (pci_resource_len(pdev, i) == 0)
7437                         continue;
7438         }
7439
7440         netdev->netdev_ops = &ixgbe_netdev_ops;
7441         ixgbe_set_ethtool_ops(netdev);
7442         netdev->watchdog_timeo = 5 * HZ;
7443         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7444
7445         adapter->bd_number = cards_found;
7446
7447         /* Setup hw api */
7448         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7449         hw->mac.type  = ii->mac;
7450
7451         /* EEPROM */
7452         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7453         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7454         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7455         if (!(eec & (1 << 8)))
7456                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7457
7458         /* PHY */
7459         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7460         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7461         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7462         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7463         hw->phy.mdio.mmds = 0;
7464         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7465         hw->phy.mdio.dev = netdev;
7466         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7467         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7468
7469         ii->get_invariants(hw);
7470
7471         /* setup the private structure */
7472         err = ixgbe_sw_init(adapter);
7473         if (err)
7474                 goto err_sw_init;
7475
7476         /* Make it possible the adapter to be woken up via WOL */
7477         switch (adapter->hw.mac.type) {
7478         case ixgbe_mac_82599EB:
7479         case ixgbe_mac_X540:
7480                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7481                 break;
7482         default:
7483                 break;
7484         }
7485
7486         /*
7487          * If there is a fan on this device and it has failed log the
7488          * failure.
7489          */
7490         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7491                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7492                 if (esdp & IXGBE_ESDP_SDP1)
7493                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7494         }
7495
7496         /* reset_hw fills in the perm_addr as well */
7497         hw->phy.reset_if_overtemp = true;
7498         err = hw->mac.ops.reset_hw(hw);
7499         hw->phy.reset_if_overtemp = false;
7500         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7501             hw->mac.type == ixgbe_mac_82598EB) {
7502                 err = 0;
7503         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7504                 e_dev_err("failed to load because an unsupported SFP+ "
7505                           "module type was detected.\n");
7506                 e_dev_err("Reload the driver after installing a supported "
7507                           "module.\n");
7508                 goto err_sw_init;
7509         } else if (err) {
7510                 e_dev_err("HW Init failed: %d\n", err);
7511                 goto err_sw_init;
7512         }
7513
7514         ixgbe_probe_vf(adapter, ii);
7515
7516         netdev->features = NETIF_F_SG |
7517                            NETIF_F_IP_CSUM |
7518                            NETIF_F_IPV6_CSUM |
7519                            NETIF_F_HW_VLAN_TX |
7520                            NETIF_F_HW_VLAN_RX |
7521                            NETIF_F_HW_VLAN_FILTER |
7522                            NETIF_F_TSO |
7523                            NETIF_F_TSO6 |
7524                            NETIF_F_RXHASH |
7525                            NETIF_F_RXCSUM;
7526
7527         netdev->hw_features = netdev->features;
7528
7529         switch (adapter->hw.mac.type) {
7530         case ixgbe_mac_82599EB:
7531         case ixgbe_mac_X540:
7532                 netdev->features |= NETIF_F_SCTP_CSUM;
7533                 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7534                                        NETIF_F_NTUPLE;
7535                 break;
7536         default:
7537                 break;
7538         }
7539
7540         netdev->vlan_features |= NETIF_F_TSO;
7541         netdev->vlan_features |= NETIF_F_TSO6;
7542         netdev->vlan_features |= NETIF_F_IP_CSUM;
7543         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7544         netdev->vlan_features |= NETIF_F_SG;
7545
7546         netdev->priv_flags |= IFF_UNICAST_FLT;
7547
7548         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7549                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7550                                     IXGBE_FLAG_DCB_ENABLED);
7551
7552 #ifdef CONFIG_IXGBE_DCB
7553         netdev->dcbnl_ops = &dcbnl_ops;
7554 #endif
7555
7556 #ifdef IXGBE_FCOE
7557         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7558                 if (hw->mac.ops.get_device_caps) {
7559                         hw->mac.ops.get_device_caps(hw, &device_caps);
7560                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7561                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7562                 }
7563         }
7564         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7565                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7566                 netdev->vlan_features |= NETIF_F_FSO;
7567                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7568         }
7569 #endif /* IXGBE_FCOE */
7570         if (pci_using_dac) {
7571                 netdev->features |= NETIF_F_HIGHDMA;
7572                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7573         }
7574
7575         if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7576                 netdev->hw_features |= NETIF_F_LRO;
7577         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7578                 netdev->features |= NETIF_F_LRO;
7579
7580         /* make sure the EEPROM is good */
7581         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7582                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7583                 err = -EIO;
7584                 goto err_eeprom;
7585         }
7586
7587         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7588         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7589
7590         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7591                 e_dev_err("invalid MAC address\n");
7592                 err = -EIO;
7593                 goto err_eeprom;
7594         }
7595
7596         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7597                     (unsigned long) adapter);
7598
7599         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7600         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7601
7602         err = ixgbe_init_interrupt_scheme(adapter);
7603         if (err)
7604                 goto err_sw_init;
7605
7606         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7607                 netdev->hw_features &= ~NETIF_F_RXHASH;
7608                 netdev->features &= ~NETIF_F_RXHASH;
7609         }
7610
7611         /* WOL not supported for all but the following */
7612         adapter->wol = 0;
7613         switch (pdev->device) {
7614         case IXGBE_DEV_ID_82599_SFP:
7615                 /* Only this subdevice supports WOL */
7616                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7617                         adapter->wol = IXGBE_WUFC_MAG;
7618                 break;
7619         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7620                 /* All except this subdevice support WOL */
7621                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7622                         adapter->wol = IXGBE_WUFC_MAG;
7623                 break;
7624         case IXGBE_DEV_ID_82599_KX4:
7625                 adapter->wol = IXGBE_WUFC_MAG;
7626                 break;
7627         case IXGBE_DEV_ID_X540T:
7628         case IXGBE_DEV_ID_X540T1:
7629                 /* Check eeprom to see if it is enabled */
7630                 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7631                 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7632
7633                 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7634                     ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7635                      (hw->bus.func == 0)))
7636                         adapter->wol = IXGBE_WUFC_MAG;
7637                 break;
7638         }
7639         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7640
7641         /* save off EEPROM version number */
7642         hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7643         hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7644
7645         /* pick up the PCI bus settings for reporting later */
7646         hw->mac.ops.get_bus_info(hw);
7647
7648         /* print bus type/speed/width info */
7649         e_dev_info("(PCI Express:%s:%s) %pM\n",
7650                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7651                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7652                     "Unknown"),
7653                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7654                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7655                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7656                     "Unknown"),
7657                    netdev->dev_addr);
7658
7659         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7660         if (err)
7661                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7662         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7663                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7664                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7665                            part_str);
7666         else
7667                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7668                            hw->mac.type, hw->phy.type, part_str);
7669
7670         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7671                 e_dev_warn("PCI-Express bandwidth available for this card is "
7672                            "not sufficient for optimal performance.\n");
7673                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7674                            "is required.\n");
7675         }
7676
7677         /* reset the hardware with the new settings */
7678         err = hw->mac.ops.start_hw(hw);
7679
7680         if (err == IXGBE_ERR_EEPROM_VERSION) {
7681                 /* We are running on a pre-production device, log a warning */
7682                 e_dev_warn("This device is a pre-production adapter/LOM. "
7683                            "Please be aware there may be issues associated "
7684                            "with your hardware.  If you are experiencing "
7685                            "problems please contact your Intel or hardware "
7686                            "representative who provided you with this "
7687                            "hardware.\n");
7688         }
7689         strcpy(netdev->name, "eth%d");
7690         err = register_netdev(netdev);
7691         if (err)
7692                 goto err_register;
7693
7694         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7695         if (hw->mac.ops.disable_tx_laser &&
7696             ((hw->phy.multispeed_fiber) ||
7697              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7698               (hw->mac.type == ixgbe_mac_82599EB))))
7699                 hw->mac.ops.disable_tx_laser(hw);
7700
7701         /* carrier off reporting is important to ethtool even BEFORE open */
7702         netif_carrier_off(netdev);
7703
7704 #ifdef CONFIG_IXGBE_DCA
7705         if (dca_add_requester(&pdev->dev) == 0) {
7706                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7707                 ixgbe_setup_dca(adapter);
7708         }
7709 #endif
7710         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7711                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7712                 for (i = 0; i < adapter->num_vfs; i++)
7713                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7714         }
7715
7716         /* firmware requires driver version to be 0xFFFFFFFF
7717          * since os does not support feature
7718          */
7719         if (hw->mac.ops.set_fw_drv_ver)
7720                 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7721                                            0xFF);
7722
7723         /* add san mac addr to netdev */
7724         ixgbe_add_sanmac_netdev(netdev);
7725
7726         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7727         cards_found++;
7728         return 0;
7729
7730 err_register:
7731         ixgbe_release_hw_control(adapter);
7732         ixgbe_clear_interrupt_scheme(adapter);
7733 err_sw_init:
7734 err_eeprom:
7735         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7736                 ixgbe_disable_sriov(adapter);
7737         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7738         iounmap(hw->hw_addr);
7739 err_ioremap:
7740         free_netdev(netdev);
7741 err_alloc_etherdev:
7742         pci_release_selected_regions(pdev,
7743                                      pci_select_bars(pdev, IORESOURCE_MEM));
7744 err_pci_reg:
7745 err_dma:
7746         pci_disable_device(pdev);
7747         return err;
7748 }
7749
7750 /**
7751  * ixgbe_remove - Device Removal Routine
7752  * @pdev: PCI device information struct
7753  *
7754  * ixgbe_remove is called by the PCI subsystem to alert the driver
7755  * that it should release a PCI device.  The could be caused by a
7756  * Hot-Plug event, or because the driver is going to be removed from
7757  * memory.
7758  **/
7759 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7760 {
7761         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7762         struct net_device *netdev = adapter->netdev;
7763
7764         set_bit(__IXGBE_DOWN, &adapter->state);
7765         cancel_work_sync(&adapter->service_task);
7766
7767 #ifdef CONFIG_IXGBE_DCA
7768         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7769                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7770                 dca_remove_requester(&pdev->dev);
7771                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7772         }
7773
7774 #endif
7775 #ifdef IXGBE_FCOE
7776         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7777                 ixgbe_cleanup_fcoe(adapter);
7778
7779 #endif /* IXGBE_FCOE */
7780
7781         /* remove the added san mac */
7782         ixgbe_del_sanmac_netdev(netdev);
7783
7784         if (netdev->reg_state == NETREG_REGISTERED)
7785                 unregister_netdev(netdev);
7786
7787         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7788                 if (!(ixgbe_check_vf_assignment(adapter)))
7789                         ixgbe_disable_sriov(adapter);
7790                 else
7791                         e_dev_warn("Unloading driver while VFs are assigned "
7792                                    "- VFs will not be deallocated\n");
7793         }
7794
7795         ixgbe_clear_interrupt_scheme(adapter);
7796
7797         ixgbe_release_hw_control(adapter);
7798
7799         iounmap(adapter->hw.hw_addr);
7800         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7801                                      IORESOURCE_MEM));
7802
7803         e_dev_info("complete\n");
7804
7805         free_netdev(netdev);
7806
7807         pci_disable_pcie_error_reporting(pdev);
7808
7809         pci_disable_device(pdev);
7810 }
7811
7812 /**
7813  * ixgbe_io_error_detected - called when PCI error is detected
7814  * @pdev: Pointer to PCI device
7815  * @state: The current pci connection state
7816  *
7817  * This function is called after a PCI bus error affecting
7818  * this device has been detected.
7819  */
7820 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7821                                                 pci_channel_state_t state)
7822 {
7823         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7824         struct net_device *netdev = adapter->netdev;
7825
7826 #ifdef CONFIG_PCI_IOV
7827         struct pci_dev *bdev, *vfdev;
7828         u32 dw0, dw1, dw2, dw3;
7829         int vf, pos;
7830         u16 req_id, pf_func;
7831
7832         if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7833             adapter->num_vfs == 0)
7834                 goto skip_bad_vf_detection;
7835
7836         bdev = pdev->bus->self;
7837         while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7838                 bdev = bdev->bus->self;
7839
7840         if (!bdev)
7841                 goto skip_bad_vf_detection;
7842
7843         pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7844         if (!pos)
7845                 goto skip_bad_vf_detection;
7846
7847         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7848         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7849         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7850         pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7851
7852         req_id = dw1 >> 16;
7853         /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7854         if (!(req_id & 0x0080))
7855                 goto skip_bad_vf_detection;
7856
7857         pf_func = req_id & 0x01;
7858         if ((pf_func & 1) == (pdev->devfn & 1)) {
7859                 unsigned int device_id;
7860
7861                 vf = (req_id & 0x7F) >> 1;
7862                 e_dev_err("VF %d has caused a PCIe error\n", vf);
7863                 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7864                                 "%8.8x\tdw3: %8.8x\n",
7865                 dw0, dw1, dw2, dw3);
7866                 switch (adapter->hw.mac.type) {
7867                 case ixgbe_mac_82599EB:
7868                         device_id = IXGBE_82599_VF_DEVICE_ID;
7869                         break;
7870                 case ixgbe_mac_X540:
7871                         device_id = IXGBE_X540_VF_DEVICE_ID;
7872                         break;
7873                 default:
7874                         device_id = 0;
7875                         break;
7876                 }
7877
7878                 /* Find the pci device of the offending VF */
7879                 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7880                 while (vfdev) {
7881                         if (vfdev->devfn == (req_id & 0xFF))
7882                                 break;
7883                         vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7884                                                device_id, vfdev);
7885                 }
7886                 /*
7887                  * There's a slim chance the VF could have been hot plugged,
7888                  * so if it is no longer present we don't need to issue the
7889                  * VFLR.  Just clean up the AER in that case.
7890                  */
7891                 if (vfdev) {
7892                         e_dev_err("Issuing VFLR to VF %d\n", vf);
7893                         pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7894                 }
7895
7896                 pci_cleanup_aer_uncorrect_error_status(pdev);
7897         }
7898
7899         /*
7900          * Even though the error may have occurred on the other port
7901          * we still need to increment the vf error reference count for
7902          * both ports because the I/O resume function will be called
7903          * for both of them.
7904          */
7905         adapter->vferr_refcount++;
7906
7907         return PCI_ERS_RESULT_RECOVERED;
7908
7909 skip_bad_vf_detection:
7910 #endif /* CONFIG_PCI_IOV */
7911         netif_device_detach(netdev);
7912
7913         if (state == pci_channel_io_perm_failure)
7914                 return PCI_ERS_RESULT_DISCONNECT;
7915
7916         if (netif_running(netdev))
7917                 ixgbe_down(adapter);
7918         pci_disable_device(pdev);
7919
7920         /* Request a slot reset. */
7921         return PCI_ERS_RESULT_NEED_RESET;
7922 }
7923
7924 /**
7925  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7926  * @pdev: Pointer to PCI device
7927  *
7928  * Restart the card from scratch, as if from a cold-boot.
7929  */
7930 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7931 {
7932         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7933         pci_ers_result_t result;
7934         int err;
7935
7936         if (pci_enable_device_mem(pdev)) {
7937                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7938                 result = PCI_ERS_RESULT_DISCONNECT;
7939         } else {
7940                 pci_set_master(pdev);
7941                 pci_restore_state(pdev);
7942                 pci_save_state(pdev);
7943
7944                 pci_wake_from_d3(pdev, false);
7945
7946                 ixgbe_reset(adapter);
7947                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7948                 result = PCI_ERS_RESULT_RECOVERED;
7949         }
7950
7951         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7952         if (err) {
7953                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7954                           "failed 0x%0x\n", err);
7955                 /* non-fatal, continue */
7956         }
7957
7958         return result;
7959 }
7960
7961 /**
7962  * ixgbe_io_resume - called when traffic can start flowing again.
7963  * @pdev: Pointer to PCI device
7964  *
7965  * This callback is called when the error recovery driver tells us that
7966  * its OK to resume normal operation.
7967  */
7968 static void ixgbe_io_resume(struct pci_dev *pdev)
7969 {
7970         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7971         struct net_device *netdev = adapter->netdev;
7972
7973 #ifdef CONFIG_PCI_IOV
7974         if (adapter->vferr_refcount) {
7975                 e_info(drv, "Resuming after VF err\n");
7976                 adapter->vferr_refcount--;
7977                 return;
7978         }
7979
7980 #endif
7981         if (netif_running(netdev))
7982                 ixgbe_up(adapter);
7983
7984         netif_device_attach(netdev);
7985 }
7986
7987 static struct pci_error_handlers ixgbe_err_handler = {
7988         .error_detected = ixgbe_io_error_detected,
7989         .slot_reset = ixgbe_io_slot_reset,
7990         .resume = ixgbe_io_resume,
7991 };
7992
7993 static struct pci_driver ixgbe_driver = {
7994         .name     = ixgbe_driver_name,
7995         .id_table = ixgbe_pci_tbl,
7996         .probe    = ixgbe_probe,
7997         .remove   = __devexit_p(ixgbe_remove),
7998 #ifdef CONFIG_PM
7999         .suspend  = ixgbe_suspend,
8000         .resume   = ixgbe_resume,
8001 #endif
8002         .shutdown = ixgbe_shutdown,
8003         .err_handler = &ixgbe_err_handler
8004 };
8005
8006 /**
8007  * ixgbe_init_module - Driver Registration Routine
8008  *
8009  * ixgbe_init_module is the first routine called when the driver is
8010  * loaded. All it does is register with the PCI subsystem.
8011  **/
8012 static int __init ixgbe_init_module(void)
8013 {
8014         int ret;
8015         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8016         pr_info("%s\n", ixgbe_copyright);
8017
8018         ret = pci_register_driver(&ixgbe_driver);
8019         if (ret)
8020                 return ret;
8021
8022 #ifdef CONFIG_IXGBE_DCA
8023         dca_register_notify(&dca_notifier);
8024 #endif
8025
8026         return 0;
8027 }
8028
8029 module_init(ixgbe_init_module);
8030
8031 /**
8032  * ixgbe_exit_module - Driver Exit Cleanup Routine
8033  *
8034  * ixgbe_exit_module is called just before the driver is removed
8035  * from memory.
8036  **/
8037 static void __exit ixgbe_exit_module(void)
8038 {
8039 #ifdef CONFIG_IXGBE_DCA
8040         dca_unregister_notify(&dca_notifier);
8041 #endif
8042         pci_unregister_driver(&ixgbe_driver);
8043         rcu_barrier(); /* Wait for completion of call_rcu()'s */
8044 }
8045
8046 #ifdef CONFIG_IXGBE_DCA
8047 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8048                             void *p)
8049 {
8050         int ret_val;
8051
8052         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8053                                          __ixgbe_notify_dca);
8054
8055         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8056 }
8057
8058 #endif /* CONFIG_IXGBE_DCA */
8059
8060 module_exit(ixgbe_exit_module);
8061
8062 /* ixgbe_main.c */