1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41 #define IXGBE_82599_RX_PB_SIZE 512
43 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed,
49 bool autoneg_wait_to_complete);
50 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
53 bool autoneg_wait_to_complete);
54 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
63 bool autoneg_wait_to_complete);
64 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
65 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
67 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
69 struct ixgbe_mac_info *mac = &hw->mac;
71 /* enable the laser control functions for SFP+ fiber */
72 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
73 mac->ops.disable_tx_laser =
74 &ixgbe_disable_tx_laser_multispeed_fiber;
75 mac->ops.enable_tx_laser =
76 &ixgbe_enable_tx_laser_multispeed_fiber;
77 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
79 mac->ops.disable_tx_laser = NULL;
80 mac->ops.enable_tx_laser = NULL;
81 mac->ops.flap_tx_laser = NULL;
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
88 if ((mac->ops.get_media_type(hw) ==
89 ixgbe_media_type_backplane) &&
90 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
91 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw))
93 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
95 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
99 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
104 u16 list_offset, data_offset, data_value;
106 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
107 ixgbe_init_mac_link_ops_82599(hw);
109 hw->phy.ops.reset = NULL;
111 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
116 /* PHY config will finish before releasing the semaphore */
117 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
118 IXGBE_GSSR_MAC_CSR_SM);
120 ret_val = IXGBE_ERR_SWFW_SYNC;
124 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
125 while (data_value != 0xffff) {
126 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
127 IXGBE_WRITE_FLUSH(hw);
128 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
131 /* Release the semaphore */
132 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
137 usleep_range(hw->eeprom.semaphore_delay * 1000,
138 hw->eeprom.semaphore_delay * 2000);
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
142 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
143 IXGBE_AUTOC_AN_RESTART));
145 /* Wait for AN to leave state 0 */
146 for (i = 0; i < 10; i++) {
147 usleep_range(4000, 8000);
148 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
149 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
152 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
153 hw_dbg(hw, "sfp module setup not complete\n");
154 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
160 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
161 IXGBE_AUTOC_AN_RESTART));
168 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
170 struct ixgbe_mac_info *mac = &hw->mac;
172 ixgbe_init_mac_link_ops_82599(hw);
174 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
175 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
176 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
177 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
178 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
179 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
186 * @hw: pointer to hardware structure
188 * Initialize any function pointers that were not able to be
189 * set during get_invariants because the PHY/SFP type was
190 * not known. Perform the SFP init if necessary.
193 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
195 struct ixgbe_mac_info *mac = &hw->mac;
196 struct ixgbe_phy_info *phy = &hw->phy;
199 /* Identify the PHY or SFP module */
200 ret_val = phy->ops.identify(hw);
202 /* Setup function pointers based on detected SFP module and speeds */
203 ixgbe_init_mac_link_ops_82599(hw);
205 /* If copper media, overwrite with copper function pointers */
206 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
207 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
208 mac->ops.get_link_capabilities =
209 &ixgbe_get_copper_link_capabilities_generic;
212 /* Set necessary function pointers based on phy type */
213 switch (hw->phy.type) {
215 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
216 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
217 phy->ops.get_firmware_version =
218 &ixgbe_get_phy_firmware_version_tnx;
221 phy->ops.get_firmware_version =
222 &ixgbe_get_phy_firmware_version_generic;
232 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
233 * @hw: pointer to hardware structure
234 * @speed: pointer to link speed
235 * @negotiation: true when autoneg or autotry is enabled
237 * Determines the link capabilities by reading the AUTOC register.
239 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
240 ixgbe_link_speed *speed,
246 /* Determine 1G link capabilities off of SFP+ type */
247 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
248 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
249 *speed = IXGBE_LINK_SPEED_1GB_FULL;
255 * Determine link capabilities based on the stored value of AUTOC,
256 * which represents EEPROM defaults. If AUTOC value has not been
257 * stored, use the current register value.
259 if (hw->mac.orig_link_settings_stored)
260 autoc = hw->mac.orig_autoc;
262 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
264 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
265 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
266 *speed = IXGBE_LINK_SPEED_1GB_FULL;
267 *negotiation = false;
270 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
271 *speed = IXGBE_LINK_SPEED_10GB_FULL;
272 *negotiation = false;
275 case IXGBE_AUTOC_LMS_1G_AN:
276 *speed = IXGBE_LINK_SPEED_1GB_FULL;
280 case IXGBE_AUTOC_LMS_10G_SERIAL:
281 *speed = IXGBE_LINK_SPEED_10GB_FULL;
282 *negotiation = false;
285 case IXGBE_AUTOC_LMS_KX4_KX_KR:
286 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
287 *speed = IXGBE_LINK_SPEED_UNKNOWN;
288 if (autoc & IXGBE_AUTOC_KR_SUPP)
289 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
290 if (autoc & IXGBE_AUTOC_KX4_SUPP)
291 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
292 if (autoc & IXGBE_AUTOC_KX_SUPP)
293 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
297 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
298 *speed = IXGBE_LINK_SPEED_100_FULL;
299 if (autoc & IXGBE_AUTOC_KR_SUPP)
300 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
301 if (autoc & IXGBE_AUTOC_KX4_SUPP)
302 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
303 if (autoc & IXGBE_AUTOC_KX_SUPP)
304 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
308 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
309 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
310 *negotiation = false;
314 status = IXGBE_ERR_LINK_SETUP;
319 if (hw->phy.multispeed_fiber) {
320 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
321 IXGBE_LINK_SPEED_1GB_FULL;
330 * ixgbe_get_media_type_82599 - Get media type
331 * @hw: pointer to hardware structure
333 * Returns the media type (fiber, copper, backplane)
335 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
337 enum ixgbe_media_type media_type;
339 /* Detect if there is a copper PHY attached. */
340 switch (hw->phy.type) {
341 case ixgbe_phy_cu_unknown:
344 media_type = ixgbe_media_type_copper;
350 switch (hw->device_id) {
351 case IXGBE_DEV_ID_82599_KX4:
352 case IXGBE_DEV_ID_82599_KX4_MEZZ:
353 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
354 case IXGBE_DEV_ID_82599_KR:
355 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
356 case IXGBE_DEV_ID_82599_XAUI_LOM:
357 /* Default device ID is mezzanine card KX/KX4 */
358 media_type = ixgbe_media_type_backplane;
360 case IXGBE_DEV_ID_82599_SFP:
361 case IXGBE_DEV_ID_82599_SFP_FCOE:
362 case IXGBE_DEV_ID_82599_SFP_EM:
363 case IXGBE_DEV_ID_82599_SFP_SF2:
364 media_type = ixgbe_media_type_fiber;
366 case IXGBE_DEV_ID_82599_CX4:
367 media_type = ixgbe_media_type_cx4;
369 case IXGBE_DEV_ID_82599_T3_LOM:
370 media_type = ixgbe_media_type_copper;
372 case IXGBE_DEV_ID_82599_LS:
373 media_type = ixgbe_media_type_fiber_lco;
376 media_type = ixgbe_media_type_unknown;
384 * ixgbe_start_mac_link_82599 - Setup MAC link settings
385 * @hw: pointer to hardware structure
386 * @autoneg_wait_to_complete: true when waiting for completion is needed
388 * Configures link settings based on values in the ixgbe_hw struct.
389 * Restarts the link. Performs autonegotiation if needed.
391 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
392 bool autoneg_wait_to_complete)
400 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
401 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
402 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
404 /* Only poll for autoneg to complete if specified to do so */
405 if (autoneg_wait_to_complete) {
406 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
407 IXGBE_AUTOC_LMS_KX4_KX_KR ||
408 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
409 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
410 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
411 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
412 links_reg = 0; /* Just in case Autoneg time = 0 */
413 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
414 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
415 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
419 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
420 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
421 hw_dbg(hw, "Autoneg did not complete.\n");
426 /* Add delay to filter out noises during initial link setup */
433 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
434 * @hw: pointer to hardware structure
436 * The base drivers may require better control over SFP+ module
437 * PHY states. This includes selectively shutting down the Tx
438 * laser on the PHY, effectively halting physical link.
440 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
442 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
444 /* Disable tx laser; allow 100us to go dark per spec */
445 esdp_reg |= IXGBE_ESDP_SDP3;
446 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
447 IXGBE_WRITE_FLUSH(hw);
452 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
453 * @hw: pointer to hardware structure
455 * The base drivers may require better control over SFP+ module
456 * PHY states. This includes selectively turning on the Tx
457 * laser on the PHY, effectively starting physical link.
459 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
461 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
463 /* Enable tx laser; allow 100ms to light up */
464 esdp_reg &= ~IXGBE_ESDP_SDP3;
465 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
466 IXGBE_WRITE_FLUSH(hw);
471 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
472 * @hw: pointer to hardware structure
474 * When the driver changes the link speeds that it can support,
475 * it sets autotry_restart to true to indicate that we need to
476 * initiate a new autotry session with the link partner. To do
477 * so, we set the speed then disable and re-enable the tx laser, to
478 * alert the link partner that it also needs to restart autotry on its
479 * end. This is consistent with true clause 37 autoneg, which also
480 * involves a loss of signal.
482 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
484 if (hw->mac.autotry_restart) {
485 ixgbe_disable_tx_laser_multispeed_fiber(hw);
486 ixgbe_enable_tx_laser_multispeed_fiber(hw);
487 hw->mac.autotry_restart = false;
492 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
493 * @hw: pointer to hardware structure
494 * @speed: new link speed
495 * @autoneg: true if autonegotiation enabled
496 * @autoneg_wait_to_complete: true when waiting for completion is needed
498 * Set the link speed in the AUTOC register and restarts link.
500 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
501 ixgbe_link_speed speed,
503 bool autoneg_wait_to_complete)
506 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
507 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
509 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
511 bool link_up = false;
514 /* Mask off requested but non-supported speeds */
515 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
523 * Try each speed one by one, highest priority first. We do this in
524 * software because 10gb fiber doesn't support speed autonegotiation.
526 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
528 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
530 /* If we already have link at this speed, just jump out */
531 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
536 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
539 /* Set the module link speed */
540 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
541 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
542 IXGBE_WRITE_FLUSH(hw);
544 /* Allow module to change analog characteristics (1G->10G) */
547 status = ixgbe_setup_mac_link_82599(hw,
548 IXGBE_LINK_SPEED_10GB_FULL,
550 autoneg_wait_to_complete);
554 /* Flap the tx laser if it has not already been done */
555 hw->mac.ops.flap_tx_laser(hw);
558 * Wait for the controller to acquire link. Per IEEE 802.3ap,
559 * Section 73.10.2, we may have to wait up to 500ms if KR is
560 * attempted. 82599 uses the same timing for 10g SFI.
562 for (i = 0; i < 5; i++) {
563 /* Wait for the link partner to also set speed */
566 /* If we have link, just jump out */
567 status = hw->mac.ops.check_link(hw, &link_speed,
577 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
579 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
580 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
582 /* If we already have link at this speed, just jump out */
583 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
588 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
591 /* Set the module link speed */
592 esdp_reg &= ~IXGBE_ESDP_SDP5;
593 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
594 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
595 IXGBE_WRITE_FLUSH(hw);
597 /* Allow module to change analog characteristics (10G->1G) */
600 status = ixgbe_setup_mac_link_82599(hw,
601 IXGBE_LINK_SPEED_1GB_FULL,
603 autoneg_wait_to_complete);
607 /* Flap the tx laser if it has not already been done */
608 hw->mac.ops.flap_tx_laser(hw);
610 /* Wait for the link partner to also set speed */
613 /* If we have link, just jump out */
614 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
624 * We didn't get link. Configure back to the highest speed we tried,
625 * (if there was more than one). We call ourselves back with just the
626 * single highest speed that the user requested.
629 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
632 autoneg_wait_to_complete);
635 /* Set autoneg_advertised value based on input link speed */
636 hw->phy.autoneg_advertised = 0;
638 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
639 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
641 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
642 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
648 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
649 * @hw: pointer to hardware structure
650 * @speed: new link speed
651 * @autoneg: true if autonegotiation enabled
652 * @autoneg_wait_to_complete: true when waiting for completion is needed
654 * Implements the Intel SmartSpeed algorithm.
656 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
657 ixgbe_link_speed speed, bool autoneg,
658 bool autoneg_wait_to_complete)
661 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
663 bool link_up = false;
664 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
666 /* Set autoneg_advertised value based on input link speed */
667 hw->phy.autoneg_advertised = 0;
669 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
670 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
672 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
673 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
675 if (speed & IXGBE_LINK_SPEED_100_FULL)
676 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
679 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
680 * autoneg advertisement if link is unable to be established at the
681 * highest negotiated rate. This can sometimes happen due to integrity
682 * issues with the physical media connection.
685 /* First, try to get link with full advertisement */
686 hw->phy.smart_speed_active = false;
687 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
688 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
689 autoneg_wait_to_complete);
694 * Wait for the controller to acquire link. Per IEEE 802.3ap,
695 * Section 73.10.2, we may have to wait up to 500ms if KR is
696 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
697 * Table 9 in the AN MAS.
699 for (i = 0; i < 5; i++) {
702 /* If we have link, just jump out */
703 status = hw->mac.ops.check_link(hw, &link_speed,
714 * We didn't get link. If we advertised KR plus one of KX4/KX
715 * (or BX4/BX), then disable KR and try again.
717 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
718 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
721 /* Turn SmartSpeed on to disable KR support */
722 hw->phy.smart_speed_active = true;
723 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
724 autoneg_wait_to_complete);
729 * Wait for the controller to acquire link. 600ms will allow for
730 * the AN link_fail_inhibit_timer as well for multiple cycles of
731 * parallel detect, both 10g and 1g. This allows for the maximum
732 * connect attempts as defined in the AN MAS table 73-7.
734 for (i = 0; i < 6; i++) {
737 /* If we have link, just jump out */
738 status = hw->mac.ops.check_link(hw, &link_speed,
747 /* We didn't get link. Turn SmartSpeed back off. */
748 hw->phy.smart_speed_active = false;
749 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
750 autoneg_wait_to_complete);
753 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
754 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
755 "the maximum advertised\n");
760 * ixgbe_setup_mac_link_82599 - Set MAC link speed
761 * @hw: pointer to hardware structure
762 * @speed: new link speed
763 * @autoneg: true if autonegotiation enabled
764 * @autoneg_wait_to_complete: true when waiting for completion is needed
766 * Set the link speed in the AUTOC register and restarts link.
768 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
769 ixgbe_link_speed speed, bool autoneg,
770 bool autoneg_wait_to_complete)
773 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
774 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
775 u32 start_autoc = autoc;
777 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
778 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
779 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
782 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
784 /* Check to see if speed passed in is supported. */
785 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
789 speed &= link_capabilities;
791 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
792 status = IXGBE_ERR_LINK_SETUP;
796 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
797 if (hw->mac.orig_link_settings_stored)
798 orig_autoc = hw->mac.orig_autoc;
802 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
803 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
804 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
805 /* Set KX4/KX/KR support according to speed requested */
806 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
807 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
808 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
809 autoc |= IXGBE_AUTOC_KX4_SUPP;
810 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
811 (hw->phy.smart_speed_active == false))
812 autoc |= IXGBE_AUTOC_KR_SUPP;
813 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
814 autoc |= IXGBE_AUTOC_KX_SUPP;
815 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
816 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
817 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
818 /* Switch from 1G SFI to 10G SFI if requested */
819 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
820 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
821 autoc &= ~IXGBE_AUTOC_LMS_MASK;
822 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
824 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
825 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
826 /* Switch from 10G SFI to 1G SFI if requested */
827 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
828 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
829 autoc &= ~IXGBE_AUTOC_LMS_MASK;
831 autoc |= IXGBE_AUTOC_LMS_1G_AN;
833 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
837 if (autoc != start_autoc) {
839 autoc |= IXGBE_AUTOC_AN_RESTART;
840 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
842 /* Only poll for autoneg to complete if specified to do so */
843 if (autoneg_wait_to_complete) {
844 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
845 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
846 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
847 links_reg = 0; /*Just in case Autoneg time=0*/
848 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
850 IXGBE_READ_REG(hw, IXGBE_LINKS);
851 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
855 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
857 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
858 hw_dbg(hw, "Autoneg did not "
864 /* Add delay to filter out noises during initial link setup */
873 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
874 * @hw: pointer to hardware structure
875 * @speed: new link speed
876 * @autoneg: true if autonegotiation enabled
877 * @autoneg_wait_to_complete: true if waiting is needed to complete
879 * Restarts link on PHY and MAC based on settings passed in.
881 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
882 ixgbe_link_speed speed,
884 bool autoneg_wait_to_complete)
888 /* Setup the PHY according to input speed */
889 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
890 autoneg_wait_to_complete);
892 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
898 * ixgbe_reset_hw_82599 - Perform hardware reset
899 * @hw: pointer to hardware structure
901 * Resets the hardware by resetting the transmit and receive units, masks
902 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
905 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
907 ixgbe_link_speed link_speed;
909 u32 ctrl, i, autoc, autoc2;
910 bool link_up = false;
912 /* Call adapter stop to disable tx/rx and clear interrupts */
913 hw->mac.ops.stop_adapter(hw);
915 /* PHY ops must be identified and initialized prior to reset */
917 /* Identify PHY and related function pointers */
918 status = hw->phy.ops.init(hw);
920 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
923 /* Setup SFP module if there is one present. */
924 if (hw->phy.sfp_setup_needed) {
925 status = hw->mac.ops.setup_sfp(hw);
926 hw->phy.sfp_setup_needed = false;
929 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
933 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
934 hw->phy.ops.reset(hw);
937 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
938 * access and verify no pending requests before reset
940 ixgbe_disable_pcie_master(hw);
944 * Issue global reset to the MAC. Needs to be SW reset if link is up.
945 * If link reset is used when link is up, it might reset the PHY when
946 * mng is using it. If link is down or the flag to force full link
947 * reset is set, then perform link reset.
949 ctrl = IXGBE_CTRL_LNK_RST;
950 if (!hw->force_full_reset) {
951 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
953 ctrl = IXGBE_CTRL_RST;
956 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
957 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
958 IXGBE_WRITE_FLUSH(hw);
960 /* Poll for reset bit to self-clear indicating reset is complete */
961 for (i = 0; i < 10; i++) {
963 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
964 if (!(ctrl & IXGBE_CTRL_RST_MASK))
968 if (ctrl & IXGBE_CTRL_RST_MASK) {
969 status = IXGBE_ERR_RESET_FAILED;
970 hw_dbg(hw, "Reset polling failed to complete.\n");
976 * Double resets are required for recovery from certain error
977 * conditions. Between resets, it is necessary to stall to allow time
978 * for any pending HW events to complete.
980 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
981 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
986 * Store the original AUTOC/AUTOC2 values if they have not been
987 * stored off yet. Otherwise restore the stored original
988 * values since the reset operation sets back to defaults.
990 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
991 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
992 if (hw->mac.orig_link_settings_stored == false) {
993 hw->mac.orig_autoc = autoc;
994 hw->mac.orig_autoc2 = autoc2;
995 hw->mac.orig_link_settings_stored = true;
997 if (autoc != hw->mac.orig_autoc)
998 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
999 IXGBE_AUTOC_AN_RESTART));
1001 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1002 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1003 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1004 autoc2 |= (hw->mac.orig_autoc2 &
1005 IXGBE_AUTOC2_UPPER_MASK);
1006 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1010 /* Store the permanent mac address */
1011 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1014 * Store MAC address from RAR0, clear receive address registers, and
1015 * clear the multicast table. Also reset num_rar_entries to 128,
1016 * since we modify this value when programming the SAN MAC address.
1018 hw->mac.num_rar_entries = 128;
1019 hw->mac.ops.init_rx_addrs(hw);
1021 /* Store the permanent SAN mac address */
1022 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1024 /* Add the SAN MAC address to the RAR only if it's a valid address */
1025 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1026 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1027 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1029 /* Reserve the last RAR for the SAN MAC address */
1030 hw->mac.num_rar_entries--;
1033 /* Store the alternative WWNN/WWPN prefix */
1034 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1035 &hw->mac.wwpn_prefix);
1042 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1043 * @hw: pointer to hardware structure
1045 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1048 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1049 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1052 * Before starting reinitialization process,
1053 * FDIRCMD.CMD must be zero.
1055 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1056 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1057 IXGBE_FDIRCMD_CMD_MASK))
1061 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1062 hw_dbg(hw, "Flow Director previous command isn't complete, "
1063 "aborting table re-initialization.\n");
1064 return IXGBE_ERR_FDIR_REINIT_FAILED;
1067 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1068 IXGBE_WRITE_FLUSH(hw);
1070 * 82599 adapters flow director init flow cannot be restarted,
1071 * Workaround 82599 silicon errata by performing the following steps
1072 * before re-writing the FDIRCTRL control register with the same value.
1073 * - write 1 to bit 8 of FDIRCMD register &
1074 * - write 0 to bit 8 of FDIRCMD register
1076 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1077 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1078 IXGBE_FDIRCMD_CLEARHT));
1079 IXGBE_WRITE_FLUSH(hw);
1080 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1081 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1082 ~IXGBE_FDIRCMD_CLEARHT));
1083 IXGBE_WRITE_FLUSH(hw);
1085 * Clear FDIR Hash register to clear any leftover hashes
1086 * waiting to be programmed.
1088 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1089 IXGBE_WRITE_FLUSH(hw);
1091 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1092 IXGBE_WRITE_FLUSH(hw);
1094 /* Poll init-done after we write FDIRCTRL register */
1095 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1096 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1097 IXGBE_FDIRCTRL_INIT_DONE)
1101 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1102 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1103 return IXGBE_ERR_FDIR_REINIT_FAILED;
1106 /* Clear FDIR statistics registers (read to clear) */
1107 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1108 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1109 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1110 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1111 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1117 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1118 * @hw: pointer to hardware structure
1119 * @fdirctrl: value to write to flow director control register
1121 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1125 /* Prime the keys for hashing */
1126 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1127 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1130 * Poll init-done after we write the register. Estimated times:
1131 * 10G: PBALLOC = 11b, timing is 60us
1132 * 1G: PBALLOC = 11b, timing is 600us
1133 * 100M: PBALLOC = 11b, timing is 6ms
1135 * Multiple these timings by 4 if under full Rx load
1137 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1138 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1139 * this might not finish in our poll time, but we can live with that
1142 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1143 IXGBE_WRITE_FLUSH(hw);
1144 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1145 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1146 IXGBE_FDIRCTRL_INIT_DONE)
1148 usleep_range(1000, 2000);
1151 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1152 hw_dbg(hw, "Flow Director poll time exceeded!\n");
1156 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1157 * @hw: pointer to hardware structure
1158 * @fdirctrl: value to write to flow director control register, initially
1159 * contains just the value of the Rx packet buffer allocation
1161 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1164 * Continue setup of fdirctrl register bits:
1165 * Move the flexible bytes to use the ethertype - shift 6 words
1166 * Set the maximum length per hash bucket to 0xA filters
1167 * Send interrupt when 64 filters are left
1169 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1170 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1171 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1173 /* write hashes and fdirctrl register, poll for completion */
1174 ixgbe_fdir_enable_82599(hw, fdirctrl);
1180 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1181 * @hw: pointer to hardware structure
1182 * @fdirctrl: value to write to flow director control register, initially
1183 * contains just the value of the Rx packet buffer allocation
1185 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1188 * Continue setup of fdirctrl register bits:
1189 * Turn perfect match filtering on
1190 * Report hash in RSS field of Rx wb descriptor
1191 * Initialize the drop queue
1192 * Move the flexible bytes to use the ethertype - shift 6 words
1193 * Set the maximum length per hash bucket to 0xA filters
1194 * Send interrupt when 64 (0x4 * 16) filters are left
1196 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1197 IXGBE_FDIRCTRL_REPORT_STATUS |
1198 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1199 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1200 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1201 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1203 /* write hashes and fdirctrl register, poll for completion */
1204 ixgbe_fdir_enable_82599(hw, fdirctrl);
1210 * These defines allow us to quickly generate all of the necessary instructions
1211 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1212 * for values 0 through 15
1214 #define IXGBE_ATR_COMMON_HASH_KEY \
1215 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1216 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1219 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1220 common_hash ^= lo_hash_dword >> n; \
1221 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1222 bucket_hash ^= lo_hash_dword >> n; \
1223 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1224 sig_hash ^= lo_hash_dword << (16 - n); \
1225 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1226 common_hash ^= hi_hash_dword >> n; \
1227 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1228 bucket_hash ^= hi_hash_dword >> n; \
1229 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1230 sig_hash ^= hi_hash_dword << (16 - n); \
1234 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1235 * @stream: input bitstream to compute the hash on
1237 * This function is almost identical to the function above but contains
1238 * several optomizations such as unwinding all of the loops, letting the
1239 * compiler work out all of the conditional ifs since the keys are static
1240 * defines, and computing two keys at once since the hashed dword stream
1241 * will be the same for both keys.
1243 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1244 union ixgbe_atr_hash_dword common)
1246 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1247 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1249 /* record the flow_vm_vlan bits as they are a key part to the hash */
1250 flow_vm_vlan = ntohl(input.dword);
1252 /* generate common hash dword */
1253 hi_hash_dword = ntohl(common.dword);
1255 /* low dword is word swapped version of common */
1256 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1258 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1259 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1261 /* Process bits 0 and 16 */
1262 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1265 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1266 * delay this because bit 0 of the stream should not be processed
1267 * so we do not add the vlan until after bit 0 was processed
1269 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1271 /* Process remaining 30 bit of the key */
1272 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1273 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1274 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1275 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1276 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1277 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1278 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1279 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1280 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1281 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1282 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1283 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1284 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1285 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1286 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1288 /* combine common_hash result with signature and bucket hashes */
1289 bucket_hash ^= common_hash;
1290 bucket_hash &= IXGBE_ATR_HASH_MASK;
1292 sig_hash ^= common_hash << 16;
1293 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1295 /* return completed signature hash */
1296 return sig_hash ^ bucket_hash;
1300 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1301 * @hw: pointer to hardware structure
1302 * @input: unique input dword
1303 * @common: compressed common input dword
1304 * @queue: queue index to direct traffic to
1306 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1307 union ixgbe_atr_hash_dword input,
1308 union ixgbe_atr_hash_dword common,
1315 * Get the flow_type in order to program FDIRCMD properly
1316 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1318 switch (input.formatted.flow_type) {
1319 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1320 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1321 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1322 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1323 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1324 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1327 hw_dbg(hw, " Error on flow type input\n");
1328 return IXGBE_ERR_CONFIG;
1331 /* configure FDIRCMD register */
1332 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1333 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1334 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1335 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1338 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1339 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1341 fdirhashcmd = (u64)fdircmd << 32;
1342 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1343 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1345 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1350 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1353 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1354 bucket_hash ^= lo_hash_dword >> n; \
1355 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1356 bucket_hash ^= hi_hash_dword >> n; \
1360 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1361 * @atr_input: input bitstream to compute the hash on
1362 * @input_mask: mask for the input bitstream
1364 * This function serves two main purposes. First it applys the input_mask
1365 * to the atr_input resulting in a cleaned up atr_input data stream.
1366 * Secondly it computes the hash and stores it in the bkt_hash field at
1367 * the end of the input byte stream. This way it will be available for
1368 * future use without needing to recompute the hash.
1370 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1371 union ixgbe_atr_input *input_mask)
1374 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1375 u32 bucket_hash = 0;
1377 /* Apply masks to input data */
1378 input->dword_stream[0] &= input_mask->dword_stream[0];
1379 input->dword_stream[1] &= input_mask->dword_stream[1];
1380 input->dword_stream[2] &= input_mask->dword_stream[2];
1381 input->dword_stream[3] &= input_mask->dword_stream[3];
1382 input->dword_stream[4] &= input_mask->dword_stream[4];
1383 input->dword_stream[5] &= input_mask->dword_stream[5];
1384 input->dword_stream[6] &= input_mask->dword_stream[6];
1385 input->dword_stream[7] &= input_mask->dword_stream[7];
1386 input->dword_stream[8] &= input_mask->dword_stream[8];
1387 input->dword_stream[9] &= input_mask->dword_stream[9];
1388 input->dword_stream[10] &= input_mask->dword_stream[10];
1390 /* record the flow_vm_vlan bits as they are a key part to the hash */
1391 flow_vm_vlan = ntohl(input->dword_stream[0]);
1393 /* generate common hash dword */
1394 hi_hash_dword = ntohl(input->dword_stream[1] ^
1395 input->dword_stream[2] ^
1396 input->dword_stream[3] ^
1397 input->dword_stream[4] ^
1398 input->dword_stream[5] ^
1399 input->dword_stream[6] ^
1400 input->dword_stream[7] ^
1401 input->dword_stream[8] ^
1402 input->dword_stream[9] ^
1403 input->dword_stream[10]);
1405 /* low dword is word swapped version of common */
1406 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1408 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1409 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1411 /* Process bits 0 and 16 */
1412 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1415 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1416 * delay this because bit 0 of the stream should not be processed
1417 * so we do not add the vlan until after bit 0 was processed
1419 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1421 /* Process remaining 30 bit of the key */
1422 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1423 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1424 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1425 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1426 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1427 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1428 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1429 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1430 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1431 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1432 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1433 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1434 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1435 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1436 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1439 * Limit hash to 13 bits since max bucket count is 8K.
1440 * Store result at the end of the input stream.
1442 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1446 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1447 * @input_mask: mask to be bit swapped
1449 * The source and destination port masks for flow director are bit swapped
1450 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1451 * generate a correctly swapped value we need to bit swap the mask and that
1452 * is what is accomplished by this function.
1454 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1456 u32 mask = ntohs(input_mask->formatted.dst_port);
1457 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1458 mask |= ntohs(input_mask->formatted.src_port);
1459 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1460 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1461 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1462 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1466 * These two macros are meant to address the fact that we have registers
1467 * that are either all or in part big-endian. As a result on big-endian
1468 * systems we will end up byte swapping the value to little-endian before
1469 * it is byte swapped again and written to the hardware in the original
1470 * big-endian format.
1472 #define IXGBE_STORE_AS_BE32(_value) \
1473 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1474 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1476 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1477 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1479 #define IXGBE_STORE_AS_BE16(_value) \
1480 ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1482 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1483 union ixgbe_atr_input *input_mask)
1485 /* mask IPv6 since it is currently not supported */
1486 u32 fdirm = IXGBE_FDIRM_DIPv6;
1490 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1491 * are zero, then assume a full mask for that field. Also assume that
1492 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1493 * cannot be masked out in this implementation.
1495 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1499 /* verify bucket hash is cleared on hash generation */
1500 if (input_mask->formatted.bkt_hash)
1501 hw_dbg(hw, " bucket hash should always be 0 in mask\n");
1503 /* Program FDIRM and verify partial masks */
1504 switch (input_mask->formatted.vm_pool & 0x7F) {
1506 fdirm |= IXGBE_FDIRM_POOL;
1510 hw_dbg(hw, " Error on vm pool mask\n");
1511 return IXGBE_ERR_CONFIG;
1514 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1516 fdirm |= IXGBE_FDIRM_L4P;
1517 if (input_mask->formatted.dst_port ||
1518 input_mask->formatted.src_port) {
1519 hw_dbg(hw, " Error on src/dst port mask\n");
1520 return IXGBE_ERR_CONFIG;
1522 case IXGBE_ATR_L4TYPE_MASK:
1525 hw_dbg(hw, " Error on flow type mask\n");
1526 return IXGBE_ERR_CONFIG;
1529 switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
1531 /* mask VLAN ID, fall through to mask VLAN priority */
1532 fdirm |= IXGBE_FDIRM_VLANID;
1534 /* mask VLAN priority */
1535 fdirm |= IXGBE_FDIRM_VLANP;
1538 /* mask VLAN ID only, fall through */
1539 fdirm |= IXGBE_FDIRM_VLANID;
1541 /* no VLAN fields masked */
1544 hw_dbg(hw, " Error on VLAN mask\n");
1545 return IXGBE_ERR_CONFIG;
1548 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1550 /* Mask Flex Bytes, fall through */
1551 fdirm |= IXGBE_FDIRM_FLEX;
1555 hw_dbg(hw, " Error on flexible byte mask\n");
1556 return IXGBE_ERR_CONFIG;
1559 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1560 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1562 /* store the TCP/UDP port masks, bit reversed from port layout */
1563 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1565 /* write both the same so that UDP and TCP use the same mask */
1566 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1567 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1569 /* store source and destination IP masks (big-enian) */
1570 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1571 ~input_mask->formatted.src_ip[0]);
1572 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1573 ~input_mask->formatted.dst_ip[0]);
1578 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1579 union ixgbe_atr_input *input,
1580 u16 soft_id, u8 queue)
1582 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1584 /* currently IPv6 is not supported, must be programmed with 0 */
1585 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1586 input->formatted.src_ip[0]);
1587 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1588 input->formatted.src_ip[1]);
1589 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1590 input->formatted.src_ip[2]);
1592 /* record the source address (big-endian) */
1593 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1595 /* record the first 32 bits of the destination address (big-endian) */
1596 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1598 /* record source and destination port (little-endian)*/
1599 fdirport = ntohs(input->formatted.dst_port);
1600 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1601 fdirport |= ntohs(input->formatted.src_port);
1602 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1604 /* record vlan (little-endian) and flex_bytes(big-endian) */
1605 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1606 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1607 fdirvlan |= ntohs(input->formatted.vlan_id);
1608 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1610 /* configure FDIRHASH register */
1611 fdirhash = input->formatted.bkt_hash;
1612 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1613 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1616 * flush all previous writes to make certain registers are
1617 * programmed prior to issuing the command
1619 IXGBE_WRITE_FLUSH(hw);
1621 /* configure FDIRCMD register */
1622 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1623 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1624 if (queue == IXGBE_FDIR_DROP_QUEUE)
1625 fdircmd |= IXGBE_FDIRCMD_DROP;
1626 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1627 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1628 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1630 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1635 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1636 union ixgbe_atr_input *input,
1644 /* configure FDIRHASH register */
1645 fdirhash = input->formatted.bkt_hash;
1646 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1647 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1649 /* flush hash to HW */
1650 IXGBE_WRITE_FLUSH(hw);
1652 /* Query if filter is present */
1653 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1655 for (retry_count = 10; retry_count; retry_count--) {
1656 /* allow 10us for query to process */
1658 /* verify query completed successfully */
1659 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1660 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1665 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1667 /* if filter exists in hardware then remove it */
1668 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1669 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1670 IXGBE_WRITE_FLUSH(hw);
1671 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1672 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1679 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1680 * @hw: pointer to hardware structure
1681 * @reg: analog register to read
1684 * Performs read operation to Omer analog register specified.
1686 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1690 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1692 IXGBE_WRITE_FLUSH(hw);
1694 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1695 *val = (u8)core_ctl;
1701 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1702 * @hw: pointer to hardware structure
1703 * @reg: atlas register to write
1704 * @val: value to write
1706 * Performs write operation to Omer analog register specified.
1708 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1712 core_ctl = (reg << 8) | val;
1713 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1714 IXGBE_WRITE_FLUSH(hw);
1721 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1722 * @hw: pointer to hardware structure
1724 * Starts the hardware using the generic start_hw function
1725 * and the generation start_hw function.
1726 * Then performs revision-specific operations, if any.
1728 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1732 ret_val = ixgbe_start_hw_generic(hw);
1736 ret_val = ixgbe_start_hw_gen2(hw);
1740 /* We need to run link autotry after the driver loads */
1741 hw->mac.autotry_restart = true;
1742 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
1745 ret_val = ixgbe_verify_fw_version_82599(hw);
1751 * ixgbe_identify_phy_82599 - Get physical layer module
1752 * @hw: pointer to hardware structure
1754 * Determines the physical layer module found on the current adapter.
1755 * If PHY already detected, maintains current PHY type in hw struct,
1756 * otherwise executes the PHY detection routine.
1758 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1760 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1762 /* Detect PHY if not unknown - returns success if already detected. */
1763 status = ixgbe_identify_phy_generic(hw);
1765 /* 82599 10GBASE-T requires an external PHY */
1766 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1769 status = ixgbe_identify_sfp_module_generic(hw);
1772 /* Set PHY type none if no PHY detected */
1773 if (hw->phy.type == ixgbe_phy_unknown) {
1774 hw->phy.type = ixgbe_phy_none;
1778 /* Return error if SFP module has been detected but is not supported */
1779 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1780 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1787 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1788 * @hw: pointer to hardware structure
1790 * Determines physical layer capabilities of the current configuration.
1792 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1794 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1795 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1796 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1797 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1798 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1799 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1800 u16 ext_ability = 0;
1801 u8 comp_codes_10g = 0;
1802 u8 comp_codes_1g = 0;
1804 hw->phy.ops.identify(hw);
1806 switch (hw->phy.type) {
1809 case ixgbe_phy_cu_unknown:
1810 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1812 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1813 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1814 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1815 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1816 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1817 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1823 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1824 case IXGBE_AUTOC_LMS_1G_AN:
1825 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1826 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1827 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1828 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1831 /* SFI mode so read SFP module */
1834 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1835 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1836 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1837 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1838 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1839 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1840 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1843 case IXGBE_AUTOC_LMS_10G_SERIAL:
1844 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1845 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1847 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1850 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1851 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1852 if (autoc & IXGBE_AUTOC_KX_SUPP)
1853 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1854 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1855 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1856 if (autoc & IXGBE_AUTOC_KR_SUPP)
1857 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1866 /* SFP check must be done last since DA modules are sometimes used to
1867 * test KR mode - we need to id KR mode correctly before SFP module.
1868 * Call identify_sfp because the pluggable module may have changed */
1869 hw->phy.ops.identify_sfp(hw);
1870 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1873 switch (hw->phy.type) {
1874 case ixgbe_phy_sfp_passive_tyco:
1875 case ixgbe_phy_sfp_passive_unknown:
1876 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1878 case ixgbe_phy_sfp_ftl_active:
1879 case ixgbe_phy_sfp_active_unknown:
1880 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1882 case ixgbe_phy_sfp_avago:
1883 case ixgbe_phy_sfp_ftl:
1884 case ixgbe_phy_sfp_intel:
1885 case ixgbe_phy_sfp_unknown:
1886 hw->phy.ops.read_i2c_eeprom(hw,
1887 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1888 hw->phy.ops.read_i2c_eeprom(hw,
1889 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1890 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1891 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1892 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1893 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1894 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1895 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1902 return physical_layer;
1906 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1907 * @hw: pointer to hardware structure
1908 * @regval: register value to write to RXCTRL
1910 * Enables the Rx DMA unit for 82599
1912 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1914 #define IXGBE_MAX_SECRX_POLL 30
1919 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1920 * If traffic is incoming before we enable the Rx unit, it could hang
1921 * the Rx DMA unit. Therefore, make sure the security engine is
1922 * completely disabled prior to enabling the Rx unit.
1924 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1925 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1926 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1927 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1928 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1929 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1932 /* Use interrupt-safe sleep just in case */
1936 /* For informational purposes only */
1937 if (i >= IXGBE_MAX_SECRX_POLL)
1938 hw_dbg(hw, "Rx unit being enabled before security "
1939 "path fully disabled. Continuing with init.\n");
1941 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1942 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1943 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1944 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1945 IXGBE_WRITE_FLUSH(hw);
1951 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1952 * @hw: pointer to hardware structure
1954 * Verifies that installed the firmware version is 0.6 or higher
1955 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1957 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1958 * if the FW version is not supported.
1960 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1962 s32 status = IXGBE_ERR_EEPROM_VERSION;
1963 u16 fw_offset, fw_ptp_cfg_offset;
1966 /* firmware check is only necessary for SFI devices */
1967 if (hw->phy.media_type != ixgbe_media_type_fiber) {
1969 goto fw_version_out;
1972 /* get the offset to the Firmware Module block */
1973 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
1975 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
1976 goto fw_version_out;
1978 /* get the offset to the Pass Through Patch Configuration block */
1979 hw->eeprom.ops.read(hw, (fw_offset +
1980 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
1981 &fw_ptp_cfg_offset);
1983 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
1984 goto fw_version_out;
1986 /* get the firmware version */
1987 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
1988 IXGBE_FW_PATCH_VERSION_4),
1991 if (fw_version > 0x5)
1999 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2000 * @hw: pointer to hardware structure
2002 * Returns true if the LESM FW module is present and enabled. Otherwise
2003 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2005 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2007 bool lesm_enabled = false;
2008 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2011 /* get the offset to the Firmware Module block */
2012 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2014 if ((status != 0) ||
2015 (fw_offset == 0) || (fw_offset == 0xFFFF))
2018 /* get the offset to the LESM Parameters block */
2019 status = hw->eeprom.ops.read(hw, (fw_offset +
2020 IXGBE_FW_LESM_PARAMETERS_PTR),
2021 &fw_lesm_param_offset);
2023 if ((status != 0) ||
2024 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2027 /* get the lesm state word */
2028 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2029 IXGBE_FW_LESM_STATE_1),
2032 if ((status == 0) &&
2033 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2034 lesm_enabled = true;
2037 return lesm_enabled;
2041 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2042 * fastest available method
2044 * @hw: pointer to hardware structure
2045 * @offset: offset of word in EEPROM to read
2046 * @words: number of words
2047 * @data: word(s) read from the EEPROM
2049 * Retrieves 16 bit word(s) read from EEPROM
2051 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2052 u16 words, u16 *data)
2054 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2055 s32 ret_val = IXGBE_ERR_CONFIG;
2058 * If EEPROM is detected and can be addressed using 14 bits,
2059 * use EERD otherwise use bit bang
2061 if ((eeprom->type == ixgbe_eeprom_spi) &&
2062 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2063 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2066 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2074 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2075 * fastest available method
2077 * @hw: pointer to hardware structure
2078 * @offset: offset of word in the EEPROM to read
2079 * @data: word read from the EEPROM
2081 * Reads a 16 bit word from the EEPROM
2083 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2084 u16 offset, u16 *data)
2086 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2087 s32 ret_val = IXGBE_ERR_CONFIG;
2090 * If EEPROM is detected and can be addressed using 14 bits,
2091 * use EERD otherwise use bit bang
2093 if ((eeprom->type == ixgbe_eeprom_spi) &&
2094 (offset <= IXGBE_EERD_MAX_ADDR))
2095 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2097 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2102 static struct ixgbe_mac_operations mac_ops_82599 = {
2103 .init_hw = &ixgbe_init_hw_generic,
2104 .reset_hw = &ixgbe_reset_hw_82599,
2105 .start_hw = &ixgbe_start_hw_82599,
2106 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2107 .get_media_type = &ixgbe_get_media_type_82599,
2108 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2109 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2110 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2111 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2112 .get_device_caps = &ixgbe_get_device_caps_generic,
2113 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2114 .stop_adapter = &ixgbe_stop_adapter_generic,
2115 .get_bus_info = &ixgbe_get_bus_info_generic,
2116 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2117 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2118 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2119 .setup_link = &ixgbe_setup_mac_link_82599,
2120 .set_rxpba = &ixgbe_set_rxpba_generic,
2121 .check_link = &ixgbe_check_mac_link_generic,
2122 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2123 .led_on = &ixgbe_led_on_generic,
2124 .led_off = &ixgbe_led_off_generic,
2125 .blink_led_start = &ixgbe_blink_led_start_generic,
2126 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2127 .set_rar = &ixgbe_set_rar_generic,
2128 .clear_rar = &ixgbe_clear_rar_generic,
2129 .set_vmdq = &ixgbe_set_vmdq_generic,
2130 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2131 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2132 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2133 .enable_mc = &ixgbe_enable_mc_generic,
2134 .disable_mc = &ixgbe_disable_mc_generic,
2135 .clear_vfta = &ixgbe_clear_vfta_generic,
2136 .set_vfta = &ixgbe_set_vfta_generic,
2137 .fc_enable = &ixgbe_fc_enable_generic,
2138 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
2139 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2140 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2141 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2142 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2143 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2144 .release_swfw_sync = &ixgbe_release_swfw_sync,
2148 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2149 .init_params = &ixgbe_init_eeprom_params_generic,
2150 .read = &ixgbe_read_eeprom_82599,
2151 .read_buffer = &ixgbe_read_eeprom_buffer_82599,
2152 .write = &ixgbe_write_eeprom_generic,
2153 .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
2154 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2155 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2156 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2159 static struct ixgbe_phy_operations phy_ops_82599 = {
2160 .identify = &ixgbe_identify_phy_82599,
2161 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2162 .init = &ixgbe_init_phy_ops_82599,
2163 .reset = &ixgbe_reset_phy_generic,
2164 .read_reg = &ixgbe_read_phy_reg_generic,
2165 .write_reg = &ixgbe_write_phy_reg_generic,
2166 .setup_link = &ixgbe_setup_phy_link_generic,
2167 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2168 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2169 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2170 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2171 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2172 .check_overtemp = &ixgbe_tn_check_overtemp,
2175 struct ixgbe_info ixgbe_82599_info = {
2176 .mac = ixgbe_mac_82599EB,
2177 .get_invariants = &ixgbe_get_invariants_82599,
2178 .mac_ops = &mac_ops_82599,
2179 .eeprom_ops = &eeprom_ops_82599,
2180 .phy_ops = &phy_ops_82599,
2181 .mbx_ops = &mbx_ops_generic,