1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 e1000_mng_mode_none = 0,
36 e1000_mng_mode_host_if_only
39 #define E1000_FACTPS_MNGCG 0x20000000
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
54 struct e1000_mac_info *mac = &hw->mac;
55 struct e1000_bus_info *bus = &hw->bus;
56 struct e1000_adapter *adapter = hw->adapter;
57 u16 pcie_link_status, cap_offset;
59 cap_offset = adapter->pdev->pcie_cap;
61 bus->width = e1000_bus_width_unknown;
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
71 mac->ops.set_lan_id(hw);
77 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
79 * @hw: pointer to the HW structure
81 * Determines the LAN function id by reading memory-mapped registers
82 * and swaps the port value if requested.
84 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
86 struct e1000_bus_info *bus = &hw->bus;
90 * The status register reports the correct function number
91 * for the device regardless of function swap state.
94 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
98 * e1000_set_lan_id_single_port - Set LAN id for a single port device
99 * @hw: pointer to the HW structure
101 * Sets the LAN function id to zero for a single port device.
103 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
105 struct e1000_bus_info *bus = &hw->bus;
111 * e1000_clear_vfta_generic - Clear VLAN filter table
112 * @hw: pointer to the HW structure
114 * Clears the register array which contains the VLAN filter table by
115 * setting all the values to 0.
117 void e1000_clear_vfta_generic(struct e1000_hw *hw)
121 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
122 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
128 * e1000_write_vfta_generic - Write value to VLAN filter table
129 * @hw: pointer to the HW structure
130 * @offset: register offset in VLAN filter table
131 * @value: register value written to VLAN filter table
133 * Writes value at the given offset in the register array which stores
134 * the VLAN filter table.
136 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
138 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
143 * e1000e_init_rx_addrs - Initialize receive address's
144 * @hw: pointer to the HW structure
145 * @rar_count: receive address registers
147 * Setup the receive address registers by setting the base receive address
148 * register to the devices MAC address and clearing all the other receive
149 * address registers to 0.
151 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
154 u8 mac_addr[ETH_ALEN] = {0};
156 /* Setup the receive address */
157 e_dbg("Programming MAC Address into RAR[0]\n");
159 e1000e_rar_set(hw, hw->mac.addr, 0);
161 /* Zero out the other (rar_entry_count - 1) receive addresses */
162 e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
163 for (i = 1; i < rar_count; i++)
164 e1000e_rar_set(hw, mac_addr, i);
168 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
169 * @hw: pointer to the HW structure
171 * Checks the nvm for an alternate MAC address. An alternate MAC address
172 * can be setup by pre-boot software and must be treated like a permanent
173 * address and must override the actual permanent MAC address. If an
174 * alternate MAC address is found it is programmed into RAR0, replacing
175 * the permanent address that was installed into RAR0 by the Si on reset.
176 * This function will return SUCCESS unless it encounters an error while
177 * reading the EEPROM.
179 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
183 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
184 u8 alt_mac_addr[ETH_ALEN];
186 ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data);
190 /* Check for LOM (vs. NIC) or one of two valid mezzanine cards */
191 if (!((nvm_data & NVM_COMPAT_LOM) ||
192 (hw->adapter->pdev->device == E1000_DEV_ID_82571EB_SERDES_DUAL) ||
193 (hw->adapter->pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) ||
194 (hw->adapter->pdev->device == E1000_DEV_ID_82571EB_SERDES)))
197 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
198 &nvm_alt_mac_addr_offset);
200 e_dbg("NVM Read Error\n");
204 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
205 (nvm_alt_mac_addr_offset == 0x0000))
206 /* There is no Alternate MAC Address */
209 if (hw->bus.func == E1000_FUNC_1)
210 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
211 for (i = 0; i < ETH_ALEN; i += 2) {
212 offset = nvm_alt_mac_addr_offset + (i >> 1);
213 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
215 e_dbg("NVM Read Error\n");
219 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
220 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
223 /* if multicast bit is set, the alternate address will not be used */
224 if (is_multicast_ether_addr(alt_mac_addr)) {
225 e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
230 * We have a valid alternate MAC address, and we want to treat it the
231 * same as the normal permanent MAC address stored by the HW into the
232 * RAR. Do this by mapping this address into RAR0.
234 e1000e_rar_set(hw, alt_mac_addr, 0);
241 * e1000e_rar_set - Set receive address register
242 * @hw: pointer to the HW structure
243 * @addr: pointer to the receive address
244 * @index: receive address array register
246 * Sets the receive address array register at index to the address passed
249 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
251 u32 rar_low, rar_high;
254 * HW expects these in little endian so we reverse the byte order
255 * from network order (big endian) to little endian
257 rar_low = ((u32) addr[0] |
258 ((u32) addr[1] << 8) |
259 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
261 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
263 /* If MAC address zero, no need to set the AV bit */
264 if (rar_low || rar_high)
265 rar_high |= E1000_RAH_AV;
268 * Some bridges will combine consecutive 32-bit writes into
269 * a single burst write, which will malfunction on some parts.
270 * The flushes avoid this.
272 ew32(RAL(index), rar_low);
274 ew32(RAH(index), rar_high);
279 * e1000_hash_mc_addr - Generate a multicast hash value
280 * @hw: pointer to the HW structure
281 * @mc_addr: pointer to a multicast address
283 * Generates a multicast address hash value which is used to determine
284 * the multicast filter table array address and new table value. See
285 * e1000_mta_set_generic()
287 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
289 u32 hash_value, hash_mask;
292 /* Register count multiplied by bits per register */
293 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
296 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
297 * where 0xFF would still fall within the hash mask.
299 while (hash_mask >> bit_shift != 0xFF)
303 * The portion of the address that is used for the hash table
304 * is determined by the mc_filter_type setting.
305 * The algorithm is such that there is a total of 8 bits of shifting.
306 * The bit_shift for a mc_filter_type of 0 represents the number of
307 * left-shifts where the MSB of mc_addr[5] would still fall within
308 * the hash_mask. Case 0 does this exactly. Since there are a total
309 * of 8 bits of shifting, then mc_addr[4] will shift right the
310 * remaining number of bits. Thus 8 - bit_shift. The rest of the
311 * cases are a variation of this algorithm...essentially raising the
312 * number of bits to shift mc_addr[5] left, while still keeping the
313 * 8-bit shifting total.
315 * For example, given the following Destination MAC Address and an
316 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
317 * we can see that the bit_shift for case 0 is 4. These are the hash
318 * values resulting from each mc_filter_type...
319 * [0] [1] [2] [3] [4] [5]
323 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
324 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
325 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
326 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
328 switch (hw->mac.mc_filter_type) {
343 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
344 (((u16) mc_addr[5]) << bit_shift)));
350 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
351 * @hw: pointer to the HW structure
352 * @mc_addr_list: array of multicast addresses to program
353 * @mc_addr_count: number of multicast addresses to program
355 * Updates entire Multicast Table Array.
356 * The caller must have a packed mc_addr_list of multicast addresses.
358 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
359 u8 *mc_addr_list, u32 mc_addr_count)
361 u32 hash_value, hash_bit, hash_reg;
364 /* clear mta_shadow */
365 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
367 /* update mta_shadow from mc_addr_list */
368 for (i = 0; (u32) i < mc_addr_count; i++) {
369 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
371 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
372 hash_bit = hash_value & 0x1F;
374 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
375 mc_addr_list += (ETH_ALEN);
378 /* replace the entire MTA table */
379 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
380 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
385 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
386 * @hw: pointer to the HW structure
388 * Clears the base hardware counters by reading the counter registers.
390 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
432 * e1000e_check_for_copper_link - Check for link (Copper)
433 * @hw: pointer to the HW structure
435 * Checks to see of the link status of the hardware has changed. If a
436 * change in link status has been detected, then we read the PHY registers
437 * to get the current speed/duplex if link exists.
439 * Returns a negative error code (-E1000_ERR_*) or 0 (link down) or 1 (link
442 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
444 struct e1000_mac_info *mac = &hw->mac;
449 * We only want to go out to the PHY registers to see if Auto-Neg
450 * has completed and/or if our link status has changed. The
451 * get_link_status flag is set upon receiving a Link Status
452 * Change or Rx Sequence Error interrupt.
454 if (!mac->get_link_status)
458 * First we want to see if the MII Status Register reports
459 * link. If so, then we want to get the current speed/duplex
462 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
467 return ret_val; /* No link detected */
469 mac->get_link_status = false;
472 * Check if there was DownShift, must be checked
473 * immediately after link-up
475 e1000e_check_downshift(hw);
478 * If we are forcing speed/duplex, then we simply return since
479 * we have already determined whether we have link or not.
482 ret_val = -E1000_ERR_CONFIG;
487 * Auto-Neg is enabled. Auto Speed Detection takes care
488 * of MAC speed/duplex configuration. So we only need to
489 * configure Collision Distance in the MAC.
491 e1000e_config_collision_dist(hw);
494 * Configure Flow Control now that Auto-Neg has completed.
495 * First, we need to restore the desired flow control
496 * settings because we may have had to re-autoneg with a
497 * different link partner.
499 ret_val = e1000e_config_fc_after_link_up(hw);
501 e_dbg("Error configuring flow control\n");
509 * e1000e_check_for_fiber_link - Check for link (Fiber)
510 * @hw: pointer to the HW structure
512 * Checks for link up on the hardware. If link is not up and we have
513 * a signal, then we need to force link up.
515 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
517 struct e1000_mac_info *mac = &hw->mac;
524 status = er32(STATUS);
528 * If we don't have link (auto-negotiation failed or link partner
529 * cannot auto-negotiate), the cable is plugged in (we have signal),
530 * and our link partner is not trying to auto-negotiate with us (we
531 * are receiving idles or data), we need to force link up. We also
532 * need to give auto-negotiation time to complete, in case the cable
533 * was just plugged in. The autoneg_failed flag does this.
535 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
536 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
537 (!(rxcw & E1000_RXCW_C))) {
538 if (mac->autoneg_failed == 0) {
539 mac->autoneg_failed = 1;
542 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
544 /* Disable auto-negotiation in the TXCW register */
545 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
547 /* Force link-up and also force full-duplex. */
549 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
552 /* Configure Flow Control after forcing link up. */
553 ret_val = e1000e_config_fc_after_link_up(hw);
555 e_dbg("Error configuring flow control\n");
558 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
560 * If we are forcing link and we are receiving /C/ ordered
561 * sets, re-enable auto-negotiation in the TXCW register
562 * and disable forced link in the Device Control register
563 * in an attempt to auto-negotiate with our link partner.
565 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
566 ew32(TXCW, mac->txcw);
567 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
569 mac->serdes_has_link = true;
576 * e1000e_check_for_serdes_link - Check for link (Serdes)
577 * @hw: pointer to the HW structure
579 * Checks for link up on the hardware. If link is not up and we have
580 * a signal, then we need to force link up.
582 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
584 struct e1000_mac_info *mac = &hw->mac;
591 status = er32(STATUS);
595 * If we don't have link (auto-negotiation failed or link partner
596 * cannot auto-negotiate), and our link partner is not trying to
597 * auto-negotiate with us (we are receiving idles or data),
598 * we need to force link up. We also need to give auto-negotiation
601 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
602 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
603 if (mac->autoneg_failed == 0) {
604 mac->autoneg_failed = 1;
607 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
609 /* Disable auto-negotiation in the TXCW register */
610 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
612 /* Force link-up and also force full-duplex. */
614 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
617 /* Configure Flow Control after forcing link up. */
618 ret_val = e1000e_config_fc_after_link_up(hw);
620 e_dbg("Error configuring flow control\n");
623 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
625 * If we are forcing link and we are receiving /C/ ordered
626 * sets, re-enable auto-negotiation in the TXCW register
627 * and disable forced link in the Device Control register
628 * in an attempt to auto-negotiate with our link partner.
630 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
631 ew32(TXCW, mac->txcw);
632 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
634 mac->serdes_has_link = true;
635 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
637 * If we force link for non-auto-negotiation switch, check
638 * link status based on MAC synchronization for internal
641 /* SYNCH bit and IV bit are sticky. */
644 if (rxcw & E1000_RXCW_SYNCH) {
645 if (!(rxcw & E1000_RXCW_IV)) {
646 mac->serdes_has_link = true;
647 e_dbg("SERDES: Link up - forced.\n");
650 mac->serdes_has_link = false;
651 e_dbg("SERDES: Link down - force failed.\n");
655 if (E1000_TXCW_ANE & er32(TXCW)) {
656 status = er32(STATUS);
657 if (status & E1000_STATUS_LU) {
658 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
661 if (rxcw & E1000_RXCW_SYNCH) {
662 if (!(rxcw & E1000_RXCW_IV)) {
663 mac->serdes_has_link = true;
664 e_dbg("SERDES: Link up - autoneg "
665 "completed successfully.\n");
667 mac->serdes_has_link = false;
668 e_dbg("SERDES: Link down - invalid"
669 "codewords detected in autoneg.\n");
672 mac->serdes_has_link = false;
673 e_dbg("SERDES: Link down - no sync.\n");
676 mac->serdes_has_link = false;
677 e_dbg("SERDES: Link down - autoneg failed\n");
685 * e1000_set_default_fc_generic - Set flow control default values
686 * @hw: pointer to the HW structure
688 * Read the EEPROM for the default values for flow control and store the
691 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
697 * Read and store word 0x0F of the EEPROM. This word contains bits
698 * that determine the hardware's default PAUSE (flow control) mode,
699 * a bit that determines whether the HW defaults to enabling or
700 * disabling auto-negotiation, and the direction of the
701 * SW defined pins. If there is no SW over-ride of the flow
702 * control setting, then the variable hw->fc will
703 * be initialized based on a value in the EEPROM.
705 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
708 e_dbg("NVM Read Error\n");
712 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
713 hw->fc.requested_mode = e1000_fc_none;
714 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
716 hw->fc.requested_mode = e1000_fc_tx_pause;
718 hw->fc.requested_mode = e1000_fc_full;
724 * e1000e_setup_link - Setup flow control and link settings
725 * @hw: pointer to the HW structure
727 * Determines which flow control settings to use, then configures flow
728 * control. Calls the appropriate media-specific link configuration
729 * function. Assuming the adapter has a valid link partner, a valid link
730 * should be established. Assumes the hardware has previously been reset
731 * and the transmitter and receiver are not enabled.
733 s32 e1000e_setup_link(struct e1000_hw *hw)
735 struct e1000_mac_info *mac = &hw->mac;
739 * In the case of the phy reset being blocked, we already have a link.
740 * We do not need to set it up again.
742 if (e1000_check_reset_block(hw))
746 * If requested flow control is set to default, set flow control
747 * based on the EEPROM flow control settings.
749 if (hw->fc.requested_mode == e1000_fc_default) {
750 ret_val = e1000_set_default_fc_generic(hw);
756 * Save off the requested flow control mode for use later. Depending
757 * on the link partner's capabilities, we may or may not use this mode.
759 hw->fc.current_mode = hw->fc.requested_mode;
761 e_dbg("After fix-ups FlowControl is now = %x\n",
762 hw->fc.current_mode);
764 /* Call the necessary media_type subroutine to configure the link. */
765 ret_val = mac->ops.setup_physical_interface(hw);
770 * Initialize the flow control address, type, and PAUSE timer
771 * registers to their default values. This is done even if flow
772 * control is disabled, because it does not hurt anything to
773 * initialize these registers.
775 e_dbg("Initializing the Flow Control address, type and timer regs\n");
776 ew32(FCT, FLOW_CONTROL_TYPE);
777 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
778 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
780 ew32(FCTTV, hw->fc.pause_time);
782 return e1000e_set_fc_watermarks(hw);
786 * e1000_commit_fc_settings_generic - Configure flow control
787 * @hw: pointer to the HW structure
789 * Write the flow control settings to the Transmit Config Word Register (TXCW)
790 * base on the flow control settings in e1000_mac_info.
792 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
794 struct e1000_mac_info *mac = &hw->mac;
798 * Check for a software override of the flow control settings, and
799 * setup the device accordingly. If auto-negotiation is enabled, then
800 * software will have to set the "PAUSE" bits to the correct value in
801 * the Transmit Config Word Register (TXCW) and re-start auto-
802 * negotiation. However, if auto-negotiation is disabled, then
803 * software will have to manually configure the two flow control enable
804 * bits in the CTRL register.
806 * The possible values of the "fc" parameter are:
807 * 0: Flow control is completely disabled
808 * 1: Rx flow control is enabled (we can receive pause frames,
809 * but not send pause frames).
810 * 2: Tx flow control is enabled (we can send pause frames but we
811 * do not support receiving pause frames).
812 * 3: Both Rx and Tx flow control (symmetric) are enabled.
814 switch (hw->fc.current_mode) {
816 /* Flow control completely disabled by a software over-ride. */
817 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
819 case e1000_fc_rx_pause:
821 * Rx Flow control is enabled and Tx Flow control is disabled
822 * by a software over-ride. Since there really isn't a way to
823 * advertise that we are capable of Rx Pause ONLY, we will
824 * advertise that we support both symmetric and asymmetric Rx
825 * PAUSE. Later, we will disable the adapter's ability to send
828 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
830 case e1000_fc_tx_pause:
832 * Tx Flow control is enabled, and Rx Flow control is disabled,
833 * by a software over-ride.
835 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
839 * Flow control (both Rx and Tx) is enabled by a software
842 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
845 e_dbg("Flow control param set incorrectly\n");
846 return -E1000_ERR_CONFIG;
857 * e1000_poll_fiber_serdes_link_generic - Poll for link up
858 * @hw: pointer to the HW structure
860 * Polls for link up by reading the status register, if link fails to come
861 * up with auto-negotiation, then the link is forced if a signal is detected.
863 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
865 struct e1000_mac_info *mac = &hw->mac;
870 * If we have a signal (the cable is plugged in, or assumed true for
871 * serdes media) then poll for a "Link-Up" indication in the Device
872 * Status Register. Time-out if a link isn't seen in 500 milliseconds
873 * seconds (Auto-negotiation should complete in less than 500
874 * milliseconds even if the other end is doing it in SW).
876 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
877 usleep_range(10000, 20000);
878 status = er32(STATUS);
879 if (status & E1000_STATUS_LU)
882 if (i == FIBER_LINK_UP_LIMIT) {
883 e_dbg("Never got a valid link from auto-neg!!!\n");
884 mac->autoneg_failed = 1;
886 * AutoNeg failed to achieve a link, so we'll call
887 * mac->check_for_link. This routine will force the
888 * link up if we detect a signal. This will allow us to
889 * communicate with non-autonegotiating link partners.
891 ret_val = mac->ops.check_for_link(hw);
893 e_dbg("Error while checking for link\n");
896 mac->autoneg_failed = 0;
898 mac->autoneg_failed = 0;
899 e_dbg("Valid Link Found\n");
906 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
907 * @hw: pointer to the HW structure
909 * Configures collision distance and flow control for fiber and serdes
910 * links. Upon successful setup, poll for link.
912 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
919 /* Take the link out of reset */
920 ctrl &= ~E1000_CTRL_LRST;
922 e1000e_config_collision_dist(hw);
924 ret_val = e1000_commit_fc_settings_generic(hw);
929 * Since auto-negotiation is enabled, take the link out of reset (the
930 * link will be in reset, because we previously reset the chip). This
931 * will restart auto-negotiation. If auto-negotiation is successful
932 * then the link-up status bit will be set and the flow control enable
933 * bits (RFCE and TFCE) will be set according to their negotiated value.
935 e_dbg("Auto-negotiation enabled\n");
939 usleep_range(1000, 2000);
942 * For these adapters, the SW definable pin 1 is set when the optics
943 * detect a signal. If we have a signal, then poll for a "Link-Up"
946 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
947 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
948 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
950 e_dbg("No signal detected\n");
957 * e1000e_config_collision_dist - Configure collision distance
958 * @hw: pointer to the HW structure
960 * Configures the collision distance to the default value and is used
961 * during link setup. Currently no func pointer exists and all
962 * implementations are handled in the generic version of this function.
964 void e1000e_config_collision_dist(struct e1000_hw *hw)
970 tctl &= ~E1000_TCTL_COLD;
971 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
978 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
979 * @hw: pointer to the HW structure
981 * Sets the flow control high/low threshold (watermark) registers. If
982 * flow control XON frame transmission is enabled, then set XON frame
983 * transmission as well.
985 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
987 u32 fcrtl = 0, fcrth = 0;
990 * Set the flow control receive threshold registers. Normally,
991 * these registers will be set to a default threshold that may be
992 * adjusted later by the driver's runtime code. However, if the
993 * ability to transmit pause frames is not enabled, then these
994 * registers will be set to 0.
996 if (hw->fc.current_mode & e1000_fc_tx_pause) {
998 * We need to set up the Receive Threshold high and low water
999 * marks as well as (optionally) enabling the transmission of
1002 fcrtl = hw->fc.low_water;
1003 fcrtl |= E1000_FCRTL_XONE;
1004 fcrth = hw->fc.high_water;
1013 * e1000e_force_mac_fc - Force the MAC's flow control settings
1014 * @hw: pointer to the HW structure
1016 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1017 * device control register to reflect the adapter settings. TFCE and RFCE
1018 * need to be explicitly set by software when a copper PHY is used because
1019 * autonegotiation is managed by the PHY rather than the MAC. Software must
1020 * also configure these bits when link is forced on a fiber connection.
1022 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
1029 * Because we didn't get link via the internal auto-negotiation
1030 * mechanism (we either forced link or we got link via PHY
1031 * auto-neg), we have to manually enable/disable transmit an
1032 * receive flow control.
1034 * The "Case" statement below enables/disable flow control
1035 * according to the "hw->fc.current_mode" parameter.
1037 * The possible values of the "fc" parameter are:
1038 * 0: Flow control is completely disabled
1039 * 1: Rx flow control is enabled (we can receive pause
1040 * frames but not send pause frames).
1041 * 2: Tx flow control is enabled (we can send pause frames
1042 * frames but we do not receive pause frames).
1043 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1044 * other: No other values should be possible at this point.
1046 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1048 switch (hw->fc.current_mode) {
1050 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1052 case e1000_fc_rx_pause:
1053 ctrl &= (~E1000_CTRL_TFCE);
1054 ctrl |= E1000_CTRL_RFCE;
1056 case e1000_fc_tx_pause:
1057 ctrl &= (~E1000_CTRL_RFCE);
1058 ctrl |= E1000_CTRL_TFCE;
1061 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1064 e_dbg("Flow control param set incorrectly\n");
1065 return -E1000_ERR_CONFIG;
1074 * e1000e_config_fc_after_link_up - Configures flow control after link
1075 * @hw: pointer to the HW structure
1077 * Checks the status of auto-negotiation after link up to ensure that the
1078 * speed and duplex were not forced. If the link needed to be forced, then
1079 * flow control needs to be forced also. If auto-negotiation is enabled
1080 * and did not fail, then we configure flow control based on our link
1083 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1085 struct e1000_mac_info *mac = &hw->mac;
1087 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1091 * Check for the case where we have fiber media and auto-neg failed
1092 * so we had to force link. In this case, we need to force the
1093 * configuration of the MAC to match the "fc" parameter.
1095 if (mac->autoneg_failed) {
1096 if (hw->phy.media_type == e1000_media_type_fiber ||
1097 hw->phy.media_type == e1000_media_type_internal_serdes)
1098 ret_val = e1000e_force_mac_fc(hw);
1100 if (hw->phy.media_type == e1000_media_type_copper)
1101 ret_val = e1000e_force_mac_fc(hw);
1105 e_dbg("Error forcing flow control settings\n");
1110 * Check for the case where we have copper media and auto-neg is
1111 * enabled. In this case, we need to check and see if Auto-Neg
1112 * has completed, and if so, how the PHY and link partner has
1113 * flow control configured.
1115 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1117 * Read the MII Status Register and check to see if AutoNeg
1118 * has completed. We read this twice because this reg has
1119 * some "sticky" (latched) bits.
1121 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1124 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1128 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1129 e_dbg("Copper PHY and Auto Neg "
1130 "has not completed.\n");
1135 * The AutoNeg process has completed, so we now need to
1136 * read both the Auto Negotiation Advertisement
1137 * Register (Address 4) and the Auto_Negotiation Base
1138 * Page Ability Register (Address 5) to determine how
1139 * flow control was negotiated.
1141 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1145 e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1150 * Two bits in the Auto Negotiation Advertisement Register
1151 * (Address 4) and two bits in the Auto Negotiation Base
1152 * Page Ability Register (Address 5) determine flow control
1153 * for both the PHY and the link partner. The following
1154 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1155 * 1999, describes these PAUSE resolution bits and how flow
1156 * control is determined based upon these settings.
1157 * NOTE: DC = Don't Care
1159 * LOCAL DEVICE | LINK PARTNER
1160 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1161 *-------|---------|-------|---------|--------------------
1162 * 0 | 0 | DC | DC | e1000_fc_none
1163 * 0 | 1 | 0 | DC | e1000_fc_none
1164 * 0 | 1 | 1 | 0 | e1000_fc_none
1165 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1166 * 1 | 0 | 0 | DC | e1000_fc_none
1167 * 1 | DC | 1 | DC | e1000_fc_full
1168 * 1 | 1 | 0 | 0 | e1000_fc_none
1169 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1171 * Are both PAUSE bits set to 1? If so, this implies
1172 * Symmetric Flow Control is enabled at both ends. The
1173 * ASM_DIR bits are irrelevant per the spec.
1175 * For Symmetric Flow Control:
1177 * LOCAL DEVICE | LINK PARTNER
1178 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1179 *-------|---------|-------|---------|--------------------
1180 * 1 | DC | 1 | DC | E1000_fc_full
1183 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1184 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1186 * Now we need to check if the user selected Rx ONLY
1187 * of pause frames. In this case, we had to advertise
1188 * FULL flow control because we could not advertise Rx
1189 * ONLY. Hence, we must now check to see if we need to
1190 * turn OFF the TRANSMISSION of PAUSE frames.
1192 if (hw->fc.requested_mode == e1000_fc_full) {
1193 hw->fc.current_mode = e1000_fc_full;
1194 e_dbg("Flow Control = FULL.\r\n");
1196 hw->fc.current_mode = e1000_fc_rx_pause;
1197 e_dbg("Flow Control = "
1198 "Rx PAUSE frames only.\r\n");
1202 * For receiving PAUSE frames ONLY.
1204 * LOCAL DEVICE | LINK PARTNER
1205 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1206 *-------|---------|-------|---------|--------------------
1207 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1209 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1210 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1211 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1212 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1213 hw->fc.current_mode = e1000_fc_tx_pause;
1214 e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
1217 * For transmitting PAUSE frames ONLY.
1219 * LOCAL DEVICE | LINK PARTNER
1220 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1221 *-------|---------|-------|---------|--------------------
1222 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1224 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1225 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1226 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1227 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1228 hw->fc.current_mode = e1000_fc_rx_pause;
1229 e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
1232 * Per the IEEE spec, at this point flow control
1233 * should be disabled.
1235 hw->fc.current_mode = e1000_fc_none;
1236 e_dbg("Flow Control = NONE.\r\n");
1240 * Now we need to do one last check... If we auto-
1241 * negotiated to HALF DUPLEX, flow control should not be
1242 * enabled per IEEE 802.3 spec.
1244 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1246 e_dbg("Error getting link speed and duplex\n");
1250 if (duplex == HALF_DUPLEX)
1251 hw->fc.current_mode = e1000_fc_none;
1254 * Now we call a subroutine to actually force the MAC
1255 * controller to use the correct flow control settings.
1257 ret_val = e1000e_force_mac_fc(hw);
1259 e_dbg("Error forcing flow control settings\n");
1268 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1269 * @hw: pointer to the HW structure
1270 * @speed: stores the current speed
1271 * @duplex: stores the current duplex
1273 * Read the status register for the current speed/duplex and store the current
1274 * speed and duplex for copper connections.
1276 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1280 status = er32(STATUS);
1281 if (status & E1000_STATUS_SPEED_1000)
1282 *speed = SPEED_1000;
1283 else if (status & E1000_STATUS_SPEED_100)
1288 if (status & E1000_STATUS_FD)
1289 *duplex = FULL_DUPLEX;
1291 *duplex = HALF_DUPLEX;
1293 e_dbg("%u Mbps, %s Duplex\n",
1294 *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
1295 *duplex == FULL_DUPLEX ? "Full" : "Half");
1301 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1302 * @hw: pointer to the HW structure
1303 * @speed: stores the current speed
1304 * @duplex: stores the current duplex
1306 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1307 * for fiber/serdes links.
1309 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1311 *speed = SPEED_1000;
1312 *duplex = FULL_DUPLEX;
1318 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1319 * @hw: pointer to the HW structure
1321 * Acquire the HW semaphore to access the PHY or NVM
1323 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1326 s32 timeout = hw->nvm.word_size + 1;
1329 /* Get the SW semaphore */
1330 while (i < timeout) {
1332 if (!(swsm & E1000_SWSM_SMBI))
1340 e_dbg("Driver can't access device - SMBI bit is set.\n");
1341 return -E1000_ERR_NVM;
1344 /* Get the FW semaphore. */
1345 for (i = 0; i < timeout; i++) {
1347 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1349 /* Semaphore acquired if bit latched */
1350 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1357 /* Release semaphores */
1358 e1000e_put_hw_semaphore(hw);
1359 e_dbg("Driver can't access the NVM\n");
1360 return -E1000_ERR_NVM;
1367 * e1000e_put_hw_semaphore - Release hardware semaphore
1368 * @hw: pointer to the HW structure
1370 * Release hardware semaphore used to access the PHY or NVM
1372 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1377 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1382 * e1000e_get_auto_rd_done - Check for auto read completion
1383 * @hw: pointer to the HW structure
1385 * Check EEPROM for Auto Read done bit.
1387 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1391 while (i < AUTO_READ_DONE_TIMEOUT) {
1392 if (er32(EECD) & E1000_EECD_AUTO_RD)
1394 usleep_range(1000, 2000);
1398 if (i == AUTO_READ_DONE_TIMEOUT) {
1399 e_dbg("Auto read by HW from NVM has not completed.\n");
1400 return -E1000_ERR_RESET;
1407 * e1000e_valid_led_default - Verify a valid default LED config
1408 * @hw: pointer to the HW structure
1409 * @data: pointer to the NVM (EEPROM)
1411 * Read the EEPROM for the current default LED configuration. If the
1412 * LED configuration is not valid, set to a valid LED configuration.
1414 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1418 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1420 e_dbg("NVM Read Error\n");
1424 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1425 *data = ID_LED_DEFAULT;
1431 * e1000e_id_led_init -
1432 * @hw: pointer to the HW structure
1435 s32 e1000e_id_led_init(struct e1000_hw *hw)
1437 struct e1000_mac_info *mac = &hw->mac;
1439 const u32 ledctl_mask = 0x000000FF;
1440 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1441 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1443 const u16 led_mask = 0x0F;
1445 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1449 mac->ledctl_default = er32(LEDCTL);
1450 mac->ledctl_mode1 = mac->ledctl_default;
1451 mac->ledctl_mode2 = mac->ledctl_default;
1453 for (i = 0; i < 4; i++) {
1454 temp = (data >> (i << 2)) & led_mask;
1456 case ID_LED_ON1_DEF2:
1457 case ID_LED_ON1_ON2:
1458 case ID_LED_ON1_OFF2:
1459 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1460 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1462 case ID_LED_OFF1_DEF2:
1463 case ID_LED_OFF1_ON2:
1464 case ID_LED_OFF1_OFF2:
1465 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1466 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1473 case ID_LED_DEF1_ON2:
1474 case ID_LED_ON1_ON2:
1475 case ID_LED_OFF1_ON2:
1476 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1477 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1479 case ID_LED_DEF1_OFF2:
1480 case ID_LED_ON1_OFF2:
1481 case ID_LED_OFF1_OFF2:
1482 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1483 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1495 * e1000e_setup_led_generic - Configures SW controllable LED
1496 * @hw: pointer to the HW structure
1498 * This prepares the SW controllable LED for use and saves the current state
1499 * of the LED so it can be later restored.
1501 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1505 if (hw->mac.ops.setup_led != e1000e_setup_led_generic)
1506 return -E1000_ERR_CONFIG;
1508 if (hw->phy.media_type == e1000_media_type_fiber) {
1509 ledctl = er32(LEDCTL);
1510 hw->mac.ledctl_default = ledctl;
1512 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1513 E1000_LEDCTL_LED0_BLINK |
1514 E1000_LEDCTL_LED0_MODE_MASK);
1515 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1516 E1000_LEDCTL_LED0_MODE_SHIFT);
1517 ew32(LEDCTL, ledctl);
1518 } else if (hw->phy.media_type == e1000_media_type_copper) {
1519 ew32(LEDCTL, hw->mac.ledctl_mode1);
1526 * e1000e_cleanup_led_generic - Set LED config to default operation
1527 * @hw: pointer to the HW structure
1529 * Remove the current LED configuration and set the LED configuration
1530 * to the default value, saved from the EEPROM.
1532 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1534 ew32(LEDCTL, hw->mac.ledctl_default);
1539 * e1000e_blink_led_generic - Blink LED
1540 * @hw: pointer to the HW structure
1542 * Blink the LEDs which are set to be on.
1544 s32 e1000e_blink_led_generic(struct e1000_hw *hw)
1546 u32 ledctl_blink = 0;
1549 if (hw->phy.media_type == e1000_media_type_fiber) {
1550 /* always blink LED0 for PCI-E fiber */
1551 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1552 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1555 * set the blink bit for each LED that's "on" (0x0E)
1558 ledctl_blink = hw->mac.ledctl_mode2;
1559 for (i = 0; i < 4; i++)
1560 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1561 E1000_LEDCTL_MODE_LED_ON)
1562 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1566 ew32(LEDCTL, ledctl_blink);
1572 * e1000e_led_on_generic - Turn LED on
1573 * @hw: pointer to the HW structure
1577 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1581 switch (hw->phy.media_type) {
1582 case e1000_media_type_fiber:
1584 ctrl &= ~E1000_CTRL_SWDPIN0;
1585 ctrl |= E1000_CTRL_SWDPIO0;
1588 case e1000_media_type_copper:
1589 ew32(LEDCTL, hw->mac.ledctl_mode2);
1599 * e1000e_led_off_generic - Turn LED off
1600 * @hw: pointer to the HW structure
1604 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1608 switch (hw->phy.media_type) {
1609 case e1000_media_type_fiber:
1611 ctrl |= E1000_CTRL_SWDPIN0;
1612 ctrl |= E1000_CTRL_SWDPIO0;
1615 case e1000_media_type_copper:
1616 ew32(LEDCTL, hw->mac.ledctl_mode1);
1626 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1627 * @hw: pointer to the HW structure
1628 * @no_snoop: bitmap of snoop events
1630 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1632 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1638 gcr &= ~(PCIE_NO_SNOOP_ALL);
1645 * e1000e_disable_pcie_master - Disables PCI-express master access
1646 * @hw: pointer to the HW structure
1648 * Returns 0 if successful, else returns -10
1649 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1650 * the master requests to be disabled.
1652 * Disables PCI-Express master access and verifies there are no pending
1655 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1658 s32 timeout = MASTER_DISABLE_TIMEOUT;
1661 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1665 if (!(er32(STATUS) &
1666 E1000_STATUS_GIO_MASTER_ENABLE))
1673 e_dbg("Master requests are pending.\n");
1674 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1681 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1682 * @hw: pointer to the HW structure
1684 * Reset the Adaptive Interframe Spacing throttle to default values.
1686 void e1000e_reset_adaptive(struct e1000_hw *hw)
1688 struct e1000_mac_info *mac = &hw->mac;
1690 if (!mac->adaptive_ifs) {
1691 e_dbg("Not in Adaptive IFS mode!\n");
1695 mac->current_ifs_val = 0;
1696 mac->ifs_min_val = IFS_MIN;
1697 mac->ifs_max_val = IFS_MAX;
1698 mac->ifs_step_size = IFS_STEP;
1699 mac->ifs_ratio = IFS_RATIO;
1701 mac->in_ifs_mode = false;
1708 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1709 * @hw: pointer to the HW structure
1711 * Update the Adaptive Interframe Spacing Throttle value based on the
1712 * time between transmitted packets and time between collisions.
1714 void e1000e_update_adaptive(struct e1000_hw *hw)
1716 struct e1000_mac_info *mac = &hw->mac;
1718 if (!mac->adaptive_ifs) {
1719 e_dbg("Not in Adaptive IFS mode!\n");
1723 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1724 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1725 mac->in_ifs_mode = true;
1726 if (mac->current_ifs_val < mac->ifs_max_val) {
1727 if (!mac->current_ifs_val)
1728 mac->current_ifs_val = mac->ifs_min_val;
1730 mac->current_ifs_val +=
1732 ew32(AIT, mac->current_ifs_val);
1736 if (mac->in_ifs_mode &&
1737 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1738 mac->current_ifs_val = 0;
1739 mac->in_ifs_mode = false;
1748 * e1000_raise_eec_clk - Raise EEPROM clock
1749 * @hw: pointer to the HW structure
1750 * @eecd: pointer to the EEPROM
1752 * Enable/Raise the EEPROM clock bit.
1754 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1756 *eecd = *eecd | E1000_EECD_SK;
1759 udelay(hw->nvm.delay_usec);
1763 * e1000_lower_eec_clk - Lower EEPROM clock
1764 * @hw: pointer to the HW structure
1765 * @eecd: pointer to the EEPROM
1767 * Clear/Lower the EEPROM clock bit.
1769 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1771 *eecd = *eecd & ~E1000_EECD_SK;
1774 udelay(hw->nvm.delay_usec);
1778 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1779 * @hw: pointer to the HW structure
1780 * @data: data to send to the EEPROM
1781 * @count: number of bits to shift out
1783 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1784 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1785 * In order to do this, "data" must be broken down into bits.
1787 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1789 struct e1000_nvm_info *nvm = &hw->nvm;
1790 u32 eecd = er32(EECD);
1793 mask = 0x01 << (count - 1);
1794 if (nvm->type == e1000_nvm_eeprom_spi)
1795 eecd |= E1000_EECD_DO;
1798 eecd &= ~E1000_EECD_DI;
1801 eecd |= E1000_EECD_DI;
1806 udelay(nvm->delay_usec);
1808 e1000_raise_eec_clk(hw, &eecd);
1809 e1000_lower_eec_clk(hw, &eecd);
1814 eecd &= ~E1000_EECD_DI;
1819 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1820 * @hw: pointer to the HW structure
1821 * @count: number of bits to shift in
1823 * In order to read a register from the EEPROM, we need to shift 'count' bits
1824 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1825 * the EEPROM (setting the SK bit), and then reading the value of the data out
1826 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1829 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1837 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1840 for (i = 0; i < count; i++) {
1842 e1000_raise_eec_clk(hw, &eecd);
1846 eecd &= ~E1000_EECD_DI;
1847 if (eecd & E1000_EECD_DO)
1850 e1000_lower_eec_clk(hw, &eecd);
1857 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1858 * @hw: pointer to the HW structure
1859 * @ee_reg: EEPROM flag for polling
1861 * Polls the EEPROM status bit for either read or write completion based
1862 * upon the value of 'ee_reg'.
1864 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1866 u32 attempts = 100000;
1869 for (i = 0; i < attempts; i++) {
1870 if (ee_reg == E1000_NVM_POLL_READ)
1875 if (reg & E1000_NVM_RW_REG_DONE)
1881 return -E1000_ERR_NVM;
1885 * e1000e_acquire_nvm - Generic request for access to EEPROM
1886 * @hw: pointer to the HW structure
1888 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1889 * Return successful if access grant bit set, else clear the request for
1890 * EEPROM access and return -E1000_ERR_NVM (-1).
1892 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1894 u32 eecd = er32(EECD);
1895 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1897 ew32(EECD, eecd | E1000_EECD_REQ);
1901 if (eecd & E1000_EECD_GNT)
1909 eecd &= ~E1000_EECD_REQ;
1911 e_dbg("Could not acquire NVM grant\n");
1912 return -E1000_ERR_NVM;
1919 * e1000_standby_nvm - Return EEPROM to standby state
1920 * @hw: pointer to the HW structure
1922 * Return the EEPROM to a standby state.
1924 static void e1000_standby_nvm(struct e1000_hw *hw)
1926 struct e1000_nvm_info *nvm = &hw->nvm;
1927 u32 eecd = er32(EECD);
1929 if (nvm->type == e1000_nvm_eeprom_spi) {
1930 /* Toggle CS to flush commands */
1931 eecd |= E1000_EECD_CS;
1934 udelay(nvm->delay_usec);
1935 eecd &= ~E1000_EECD_CS;
1938 udelay(nvm->delay_usec);
1943 * e1000_stop_nvm - Terminate EEPROM command
1944 * @hw: pointer to the HW structure
1946 * Terminates the current command by inverting the EEPROM's chip select pin.
1948 static void e1000_stop_nvm(struct e1000_hw *hw)
1953 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1955 eecd |= E1000_EECD_CS;
1956 e1000_lower_eec_clk(hw, &eecd);
1961 * e1000e_release_nvm - Release exclusive access to EEPROM
1962 * @hw: pointer to the HW structure
1964 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1966 void e1000e_release_nvm(struct e1000_hw *hw)
1973 eecd &= ~E1000_EECD_REQ;
1978 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1979 * @hw: pointer to the HW structure
1981 * Setups the EEPROM for reading and writing.
1983 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1985 struct e1000_nvm_info *nvm = &hw->nvm;
1986 u32 eecd = er32(EECD);
1989 if (nvm->type == e1000_nvm_eeprom_spi) {
1990 u16 timeout = NVM_MAX_RETRY_SPI;
1992 /* Clear SK and CS */
1993 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1999 * Read "Status Register" repeatedly until the LSB is cleared.
2000 * The EEPROM will signal that the command has been completed
2001 * by clearing bit 0 of the internal status register. If it's
2002 * not cleared within 'timeout', then error out.
2005 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
2006 hw->nvm.opcode_bits);
2007 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
2008 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
2012 e1000_standby_nvm(hw);
2017 e_dbg("SPI NVM Status error\n");
2018 return -E1000_ERR_NVM;
2026 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
2027 * @hw: pointer to the HW structure
2028 * @offset: offset of word in the EEPROM to read
2029 * @words: number of words to read
2030 * @data: word read from the EEPROM
2032 * Reads a 16 bit word from the EEPROM using the EERD register.
2034 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2036 struct e1000_nvm_info *nvm = &hw->nvm;
2041 * A check for invalid values: offset too large, too many words,
2042 * too many words for the offset, and not enough words.
2044 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2046 e_dbg("nvm parameter(s) out of bounds\n");
2047 return -E1000_ERR_NVM;
2050 for (i = 0; i < words; i++) {
2051 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
2052 E1000_NVM_RW_REG_START;
2055 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
2059 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
2066 * e1000e_write_nvm_spi - Write to EEPROM using SPI
2067 * @hw: pointer to the HW structure
2068 * @offset: offset within the EEPROM to be written to
2069 * @words: number of words to write
2070 * @data: 16 bit word(s) to be written to the EEPROM
2072 * Writes data to EEPROM at offset using SPI interface.
2074 * If e1000e_update_nvm_checksum is not called after this function , the
2075 * EEPROM will most likely contain an invalid checksum.
2077 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2079 struct e1000_nvm_info *nvm = &hw->nvm;
2084 * A check for invalid values: offset too large, too many words,
2085 * and not enough words.
2087 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2089 e_dbg("nvm parameter(s) out of bounds\n");
2090 return -E1000_ERR_NVM;
2093 ret_val = nvm->ops.acquire(hw);
2097 while (widx < words) {
2098 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2100 ret_val = e1000_ready_nvm_eeprom(hw);
2102 nvm->ops.release(hw);
2106 e1000_standby_nvm(hw);
2108 /* Send the WRITE ENABLE command (8 bit opcode) */
2109 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2112 e1000_standby_nvm(hw);
2115 * Some SPI eeproms use the 8th address bit embedded in the
2118 if ((nvm->address_bits == 8) && (offset >= 128))
2119 write_opcode |= NVM_A8_OPCODE_SPI;
2121 /* Send the Write command (8-bit opcode + addr) */
2122 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2123 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2126 /* Loop to allow for up to whole page write of eeprom */
2127 while (widx < words) {
2128 u16 word_out = data[widx];
2129 word_out = (word_out >> 8) | (word_out << 8);
2130 e1000_shift_out_eec_bits(hw, word_out, 16);
2133 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2134 e1000_standby_nvm(hw);
2140 usleep_range(10000, 20000);
2141 nvm->ops.release(hw);
2146 * e1000_read_pba_string_generic - Read device part number
2147 * @hw: pointer to the HW structure
2148 * @pba_num: pointer to device part number
2149 * @pba_num_size: size of part number buffer
2151 * Reads the product board assembly (PBA) number from the EEPROM and stores
2152 * the value in pba_num.
2154 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
2163 if (pba_num == NULL) {
2164 e_dbg("PBA string buffer was null\n");
2165 ret_val = E1000_ERR_INVALID_ARGUMENT;
2169 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2171 e_dbg("NVM Read Error\n");
2175 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
2177 e_dbg("NVM Read Error\n");
2182 * if nvm_data is not ptr guard the PBA must be in legacy format which
2183 * means pba_ptr is actually our second data word for the PBA number
2184 * and we can decode it into an ascii string
2186 if (nvm_data != NVM_PBA_PTR_GUARD) {
2187 e_dbg("NVM PBA number is not stored as string\n");
2189 /* we will need 11 characters to store the PBA */
2190 if (pba_num_size < 11) {
2191 e_dbg("PBA string buffer too small\n");
2192 return E1000_ERR_NO_SPACE;
2195 /* extract hex string from data and pba_ptr */
2196 pba_num[0] = (nvm_data >> 12) & 0xF;
2197 pba_num[1] = (nvm_data >> 8) & 0xF;
2198 pba_num[2] = (nvm_data >> 4) & 0xF;
2199 pba_num[3] = nvm_data & 0xF;
2200 pba_num[4] = (pba_ptr >> 12) & 0xF;
2201 pba_num[5] = (pba_ptr >> 8) & 0xF;
2204 pba_num[8] = (pba_ptr >> 4) & 0xF;
2205 pba_num[9] = pba_ptr & 0xF;
2207 /* put a null character on the end of our string */
2210 /* switch all the data but the '-' to hex char */
2211 for (offset = 0; offset < 10; offset++) {
2212 if (pba_num[offset] < 0xA)
2213 pba_num[offset] += '0';
2214 else if (pba_num[offset] < 0x10)
2215 pba_num[offset] += 'A' - 0xA;
2221 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
2223 e_dbg("NVM Read Error\n");
2227 if (length == 0xFFFF || length == 0) {
2228 e_dbg("NVM PBA number section invalid length\n");
2229 ret_val = E1000_ERR_NVM_PBA_SECTION;
2232 /* check if pba_num buffer is big enough */
2233 if (pba_num_size < (((u32)length * 2) - 1)) {
2234 e_dbg("PBA string buffer too small\n");
2235 ret_val = E1000_ERR_NO_SPACE;
2239 /* trim pba length from start of string */
2243 for (offset = 0; offset < length; offset++) {
2244 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
2246 e_dbg("NVM Read Error\n");
2249 pba_num[offset * 2] = (u8)(nvm_data >> 8);
2250 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
2252 pba_num[offset * 2] = '\0';
2259 * e1000_read_mac_addr_generic - Read device MAC address
2260 * @hw: pointer to the HW structure
2262 * Reads the device MAC address from the EEPROM and stores the value.
2263 * Since devices with two ports use the same EEPROM, we increment the
2264 * last bit in the MAC address for the second port.
2266 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
2272 rar_high = er32(RAH(0));
2273 rar_low = er32(RAL(0));
2275 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
2276 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
2278 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
2279 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
2281 for (i = 0; i < ETH_ALEN; i++)
2282 hw->mac.addr[i] = hw->mac.perm_addr[i];
2288 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2289 * @hw: pointer to the HW structure
2291 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2292 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2294 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2300 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2301 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2303 e_dbg("NVM Read Error\n");
2306 checksum += nvm_data;
2309 if (checksum != (u16) NVM_SUM) {
2310 e_dbg("NVM Checksum Invalid\n");
2311 return -E1000_ERR_NVM;
2318 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2319 * @hw: pointer to the HW structure
2321 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2322 * up to the checksum. Then calculates the EEPROM checksum and writes the
2323 * value to the EEPROM.
2325 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2331 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2332 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2334 e_dbg("NVM Read Error while updating checksum.\n");
2337 checksum += nvm_data;
2339 checksum = (u16) NVM_SUM - checksum;
2340 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2342 e_dbg("NVM Write Error while updating checksum.\n");
2348 * e1000e_reload_nvm - Reloads EEPROM
2349 * @hw: pointer to the HW structure
2351 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2352 * extended control register.
2354 void e1000e_reload_nvm(struct e1000_hw *hw)
2359 ctrl_ext = er32(CTRL_EXT);
2360 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2361 ew32(CTRL_EXT, ctrl_ext);
2366 * e1000_calculate_checksum - Calculate checksum for buffer
2367 * @buffer: pointer to EEPROM
2368 * @length: size of EEPROM to calculate a checksum for
2370 * Calculates the checksum for some buffer on a specified length. The
2371 * checksum calculated is returned.
2373 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2381 for (i = 0; i < length; i++)
2384 return (u8) (0 - sum);
2388 * e1000_mng_enable_host_if - Checks host interface is enabled
2389 * @hw: pointer to the HW structure
2391 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2393 * This function checks whether the HOST IF is enabled for command operation
2394 * and also checks whether the previous command is completed. It busy waits
2395 * in case of previous command is not completed.
2397 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2402 if (!(hw->mac.arc_subsystem_valid)) {
2403 e_dbg("ARC subsystem not valid.\n");
2404 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2407 /* Check that the host interface is enabled. */
2409 if ((hicr & E1000_HICR_EN) == 0) {
2410 e_dbg("E1000_HOST_EN bit disabled.\n");
2411 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2413 /* check the previous command is completed */
2414 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2416 if (!(hicr & E1000_HICR_C))
2421 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2422 e_dbg("Previous command timeout failed .\n");
2423 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2430 * e1000e_check_mng_mode_generic - check management mode
2431 * @hw: pointer to the HW structure
2433 * Reads the firmware semaphore register and returns true (>0) if
2434 * manageability is enabled, else false (0).
2436 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2438 u32 fwsm = er32(FWSM);
2440 return (fwsm & E1000_FWSM_MODE_MASK) ==
2441 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2445 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2446 * @hw: pointer to the HW structure
2448 * Enables packet filtering on transmit packets if manageability is enabled
2449 * and host interface is enabled.
2451 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2453 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2454 u32 *buffer = (u32 *)&hw->mng_cookie;
2456 s32 ret_val, hdr_csum, csum;
2459 hw->mac.tx_pkt_filtering = true;
2461 /* No manageability, no filtering */
2462 if (!e1000e_check_mng_mode(hw)) {
2463 hw->mac.tx_pkt_filtering = false;
2468 * If we can't read from the host interface for whatever
2469 * reason, disable filtering.
2471 ret_val = e1000_mng_enable_host_if(hw);
2473 hw->mac.tx_pkt_filtering = false;
2477 /* Read in the header. Length and offset are in dwords. */
2478 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2479 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2480 for (i = 0; i < len; i++)
2481 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2482 hdr_csum = hdr->checksum;
2484 csum = e1000_calculate_checksum((u8 *)hdr,
2485 E1000_MNG_DHCP_COOKIE_LENGTH);
2487 * If either the checksums or signature don't match, then
2488 * the cookie area isn't considered valid, in which case we
2489 * take the safe route of assuming Tx filtering is enabled.
2491 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2492 hw->mac.tx_pkt_filtering = true;
2496 /* Cookie area is valid, make the final check for filtering. */
2497 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2498 hw->mac.tx_pkt_filtering = false;
2503 return hw->mac.tx_pkt_filtering;
2507 * e1000_mng_write_cmd_header - Writes manageability command header
2508 * @hw: pointer to the HW structure
2509 * @hdr: pointer to the host interface command header
2511 * Writes the command header after does the checksum calculation.
2513 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2514 struct e1000_host_mng_command_header *hdr)
2516 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2518 /* Write the whole command header structure with new checksum. */
2520 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2523 /* Write the relevant command block into the ram area. */
2524 for (i = 0; i < length; i++) {
2525 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2526 *((u32 *) hdr + i));
2534 * e1000_mng_host_if_write - Write to the manageability host interface
2535 * @hw: pointer to the HW structure
2536 * @buffer: pointer to the host interface buffer
2537 * @length: size of the buffer
2538 * @offset: location in the buffer to write to
2539 * @sum: sum of the data (not checksum)
2541 * This function writes the buffer content at the offset given on the host if.
2542 * It also does alignment considerations to do the writes in most efficient
2543 * way. Also fills up the sum of the buffer in *buffer parameter.
2545 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2546 u16 length, u16 offset, u8 *sum)
2549 u8 *bufptr = buffer;
2551 u16 remaining, i, j, prev_bytes;
2553 /* sum = only sum of the data and it is not checksum */
2555 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2556 return -E1000_ERR_PARAM;
2559 prev_bytes = offset & 0x3;
2563 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2564 for (j = prev_bytes; j < sizeof(u32); j++) {
2565 *(tmp + j) = *bufptr++;
2568 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2569 length -= j - prev_bytes;
2573 remaining = length & 0x3;
2574 length -= remaining;
2576 /* Calculate length in DWORDs */
2580 * The device driver writes the relevant command block into the
2583 for (i = 0; i < length; i++) {
2584 for (j = 0; j < sizeof(u32); j++) {
2585 *(tmp + j) = *bufptr++;
2589 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2592 for (j = 0; j < sizeof(u32); j++) {
2594 *(tmp + j) = *bufptr++;
2600 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2607 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2608 * @hw: pointer to the HW structure
2609 * @buffer: pointer to the host interface
2610 * @length: size of the buffer
2612 * Writes the DHCP information to the host interface.
2614 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2616 struct e1000_host_mng_command_header hdr;
2620 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2621 hdr.command_length = length;
2626 /* Enable the host interface */
2627 ret_val = e1000_mng_enable_host_if(hw);
2631 /* Populate the host interface with the contents of "buffer". */
2632 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2633 sizeof(hdr), &(hdr.checksum));
2637 /* Write the manageability command header */
2638 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2642 /* Tell the ARC a new command is pending. */
2644 ew32(HICR, hicr | E1000_HICR_C);
2650 * e1000e_enable_mng_pass_thru - Check if management passthrough is needed
2651 * @hw: pointer to the HW structure
2653 * Verifies the hardware needs to leave interface enabled so that frames can
2654 * be directed to and from the management interface.
2656 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2660 bool ret_val = false;
2664 if (!(manc & E1000_MANC_RCV_TCO_EN))
2667 if (hw->mac.has_fwsm) {
2669 factps = er32(FACTPS);
2671 if (!(factps & E1000_FACTPS_MNGCG) &&
2672 ((fwsm & E1000_FWSM_MODE_MASK) ==
2673 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2677 } else if ((hw->mac.type == e1000_82574) ||
2678 (hw->mac.type == e1000_82583)) {
2681 factps = er32(FACTPS);
2682 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
2684 if (!(factps & E1000_FACTPS_MNGCG) &&
2685 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
2686 (e1000_mng_mode_pt << 13))) {
2690 } else if ((manc & E1000_MANC_SMBUS_EN) &&
2691 !(manc & E1000_MANC_ASF_EN)) {