2 * EP93xx ethernet network device driver
3 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
4 * Dedicated to Marija Kulikova.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
14 #include <linux/dma-mapping.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/mii.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/moduleparam.h>
24 #include <linux/platform_device.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
29 #include <mach/hardware.h>
31 #define DRV_MODULE_NAME "ep93xx-eth"
32 #define DRV_MODULE_VERSION "0.1"
34 #define RX_QUEUE_ENTRIES 64
35 #define TX_QUEUE_ENTRIES 8
37 #define MAX_PKT_SIZE 2044
38 #define PKT_BUF_SIZE 2048
40 #define REG_RXCTL 0x0000
41 #define REG_RXCTL_DEFAULT 0x00073800
42 #define REG_TXCTL 0x0004
43 #define REG_TXCTL_ENABLE 0x00000001
44 #define REG_MIICMD 0x0010
45 #define REG_MIICMD_READ 0x00008000
46 #define REG_MIICMD_WRITE 0x00004000
47 #define REG_MIIDATA 0x0014
48 #define REG_MIISTS 0x0018
49 #define REG_MIISTS_BUSY 0x00000001
50 #define REG_SELFCTL 0x0020
51 #define REG_SELFCTL_RESET 0x00000001
52 #define REG_INTEN 0x0024
53 #define REG_INTEN_TX 0x00000008
54 #define REG_INTEN_RX 0x00000007
55 #define REG_INTSTSP 0x0028
56 #define REG_INTSTS_TX 0x00000008
57 #define REG_INTSTS_RX 0x00000004
58 #define REG_INTSTSC 0x002c
59 #define REG_AFP 0x004c
60 #define REG_INDAD0 0x0050
61 #define REG_INDAD1 0x0051
62 #define REG_INDAD2 0x0052
63 #define REG_INDAD3 0x0053
64 #define REG_INDAD4 0x0054
65 #define REG_INDAD5 0x0055
66 #define REG_GIINTMSK 0x0064
67 #define REG_GIINTMSK_ENABLE 0x00008000
68 #define REG_BMCTL 0x0080
69 #define REG_BMCTL_ENABLE_TX 0x00000100
70 #define REG_BMCTL_ENABLE_RX 0x00000001
71 #define REG_BMSTS 0x0084
72 #define REG_BMSTS_RX_ACTIVE 0x00000008
73 #define REG_RXDQBADD 0x0090
74 #define REG_RXDQBLEN 0x0094
75 #define REG_RXDCURADD 0x0098
76 #define REG_RXDENQ 0x009c
77 #define REG_RXSTSQBADD 0x00a0
78 #define REG_RXSTSQBLEN 0x00a4
79 #define REG_RXSTSQCURADD 0x00a8
80 #define REG_RXSTSENQ 0x00ac
81 #define REG_TXDQBADD 0x00b0
82 #define REG_TXDQBLEN 0x00b4
83 #define REG_TXDQCURADD 0x00b8
84 #define REG_TXDENQ 0x00bc
85 #define REG_TXSTSQBADD 0x00c0
86 #define REG_TXSTSQBLEN 0x00c4
87 #define REG_TXSTSQCURADD 0x00c8
88 #define REG_MAXFRMLEN 0x00e8
96 #define RDESC1_NSOF 0x80000000
97 #define RDESC1_BUFFER_INDEX 0x7fff0000
98 #define RDESC1_BUFFER_LENGTH 0x0000ffff
106 #define RSTAT0_RFP 0x80000000
107 #define RSTAT0_RWE 0x40000000
108 #define RSTAT0_EOF 0x20000000
109 #define RSTAT0_EOB 0x10000000
110 #define RSTAT0_AM 0x00c00000
111 #define RSTAT0_RX_ERR 0x00200000
112 #define RSTAT0_OE 0x00100000
113 #define RSTAT0_FE 0x00080000
114 #define RSTAT0_RUNT 0x00040000
115 #define RSTAT0_EDATA 0x00020000
116 #define RSTAT0_CRCE 0x00010000
117 #define RSTAT0_CRCI 0x00008000
118 #define RSTAT0_HTI 0x00003f00
119 #define RSTAT1_RFP 0x80000000
120 #define RSTAT1_BUFFER_INDEX 0x7fff0000
121 #define RSTAT1_FRAME_LENGTH 0x0000ffff
129 #define TDESC1_EOF 0x80000000
130 #define TDESC1_BUFFER_INDEX 0x7fff0000
131 #define TDESC1_BUFFER_ABORT 0x00008000
132 #define TDESC1_BUFFER_LENGTH 0x00000fff
139 #define TSTAT0_TXFP 0x80000000
140 #define TSTAT0_TXWE 0x40000000
141 #define TSTAT0_FA 0x20000000
142 #define TSTAT0_LCRS 0x10000000
143 #define TSTAT0_OW 0x04000000
144 #define TSTAT0_TXU 0x02000000
145 #define TSTAT0_ECOLL 0x01000000
146 #define TSTAT0_NCOLL 0x001f0000
147 #define TSTAT0_BUFFER_INDEX 0x00007fff
151 struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
152 struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
153 struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
154 struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
159 struct resource *res;
160 void __iomem *base_addr;
163 struct ep93xx_descs *descs;
164 dma_addr_t descs_dma_addr;
166 void *rx_buf[RX_QUEUE_ENTRIES];
167 void *tx_buf[TX_QUEUE_ENTRIES];
170 unsigned int rx_pointer;
171 unsigned int tx_clean_pointer;
172 unsigned int tx_pointer;
173 spinlock_t tx_pending_lock;
174 unsigned int tx_pending;
176 struct net_device *dev;
177 struct napi_struct napi;
179 struct mii_if_info mii;
183 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
184 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
185 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
186 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
187 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
188 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
190 static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
192 struct ep93xx_priv *ep = netdev_priv(dev);
196 wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
198 for (i = 0; i < 10; i++) {
199 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
205 pr_info("mdio read timed out\n");
208 data = rdl(ep, REG_MIIDATA);
214 static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
216 struct ep93xx_priv *ep = netdev_priv(dev);
219 wrl(ep, REG_MIIDATA, data);
220 wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
222 for (i = 0; i < 10; i++) {
223 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
229 pr_info("mdio write timed out\n");
232 static int ep93xx_rx(struct net_device *dev, int processed, int budget)
234 struct ep93xx_priv *ep = netdev_priv(dev);
236 while (processed < budget) {
238 struct ep93xx_rstat *rstat;
244 entry = ep->rx_pointer;
245 rstat = ep->descs->rstat + entry;
247 rstat0 = rstat->rstat0;
248 rstat1 = rstat->rstat1;
249 if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
255 if (!(rstat0 & RSTAT0_EOF))
256 pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1);
257 if (!(rstat0 & RSTAT0_EOB))
258 pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1);
259 if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
260 pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1);
262 if (!(rstat0 & RSTAT0_RWE)) {
263 dev->stats.rx_errors++;
264 if (rstat0 & RSTAT0_OE)
265 dev->stats.rx_fifo_errors++;
266 if (rstat0 & RSTAT0_FE)
267 dev->stats.rx_frame_errors++;
268 if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
269 dev->stats.rx_length_errors++;
270 if (rstat0 & RSTAT0_CRCE)
271 dev->stats.rx_crc_errors++;
275 length = rstat1 & RSTAT1_FRAME_LENGTH;
276 if (length > MAX_PKT_SIZE) {
277 pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1);
282 if (rstat0 & RSTAT0_CRCI)
285 skb = dev_alloc_skb(length + 2);
286 if (likely(skb != NULL)) {
287 struct ep93xx_rdesc *rxd = &ep->descs->rdesc[entry];
289 dma_sync_single_for_cpu(dev->dev.parent, rxd->buf_addr,
290 length, DMA_FROM_DEVICE);
291 skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
292 dma_sync_single_for_device(dev->dev.parent,
293 rxd->buf_addr, length,
295 skb_put(skb, length);
296 skb->protocol = eth_type_trans(skb, dev);
298 netif_receive_skb(skb);
300 dev->stats.rx_packets++;
301 dev->stats.rx_bytes += length;
303 dev->stats.rx_dropped++;
307 ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
314 static int ep93xx_have_more_rx(struct ep93xx_priv *ep)
316 struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer;
317 return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP));
320 static int ep93xx_poll(struct napi_struct *napi, int budget)
322 struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
323 struct net_device *dev = ep->dev;
327 rx = ep93xx_rx(dev, rx, budget);
331 spin_lock_irq(&ep->rx_lock);
332 __napi_complete(napi);
333 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
334 if (ep93xx_have_more_rx(ep)) {
335 wrl(ep, REG_INTEN, REG_INTEN_TX);
336 wrl(ep, REG_INTSTSP, REG_INTSTS_RX);
339 spin_unlock_irq(&ep->rx_lock);
341 if (more && napi_reschedule(napi))
346 wrw(ep, REG_RXDENQ, rx);
347 wrw(ep, REG_RXSTSENQ, rx);
353 static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
355 struct ep93xx_priv *ep = netdev_priv(dev);
356 struct ep93xx_tdesc *txd;
359 if (unlikely(skb->len > MAX_PKT_SIZE)) {
360 dev->stats.tx_dropped++;
365 entry = ep->tx_pointer;
366 ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
368 txd = &ep->descs->tdesc[entry];
370 txd->tdesc1 = TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
371 dma_sync_single_for_cpu(dev->dev.parent, txd->buf_addr, skb->len,
373 skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
374 dma_sync_single_for_device(dev->dev.parent, txd->buf_addr, skb->len,
378 spin_lock_irq(&ep->tx_pending_lock);
380 if (ep->tx_pending == TX_QUEUE_ENTRIES)
381 netif_stop_queue(dev);
382 spin_unlock_irq(&ep->tx_pending_lock);
384 wrl(ep, REG_TXDENQ, 1);
389 static void ep93xx_tx_complete(struct net_device *dev)
391 struct ep93xx_priv *ep = netdev_priv(dev);
396 spin_lock(&ep->tx_pending_lock);
399 struct ep93xx_tstat *tstat;
402 entry = ep->tx_clean_pointer;
403 tstat = ep->descs->tstat + entry;
405 tstat0 = tstat->tstat0;
406 if (!(tstat0 & TSTAT0_TXFP))
411 if (tstat0 & TSTAT0_FA)
412 pr_crit("frame aborted %.8x\n", tstat0);
413 if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
414 pr_crit("entry mismatch %.8x\n", tstat0);
416 if (tstat0 & TSTAT0_TXWE) {
417 int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
419 dev->stats.tx_packets++;
420 dev->stats.tx_bytes += length;
422 dev->stats.tx_errors++;
425 if (tstat0 & TSTAT0_OW)
426 dev->stats.tx_window_errors++;
427 if (tstat0 & TSTAT0_TXU)
428 dev->stats.tx_fifo_errors++;
429 dev->stats.collisions += (tstat0 >> 16) & 0x1f;
431 ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
432 if (ep->tx_pending == TX_QUEUE_ENTRIES)
436 spin_unlock(&ep->tx_pending_lock);
439 netif_wake_queue(dev);
442 static irqreturn_t ep93xx_irq(int irq, void *dev_id)
444 struct net_device *dev = dev_id;
445 struct ep93xx_priv *ep = netdev_priv(dev);
448 status = rdl(ep, REG_INTSTSC);
452 if (status & REG_INTSTS_RX) {
453 spin_lock(&ep->rx_lock);
454 if (likely(napi_schedule_prep(&ep->napi))) {
455 wrl(ep, REG_INTEN, REG_INTEN_TX);
456 __napi_schedule(&ep->napi);
458 spin_unlock(&ep->rx_lock);
461 if (status & REG_INTSTS_TX)
462 ep93xx_tx_complete(dev);
467 static void ep93xx_free_buffers(struct ep93xx_priv *ep)
469 struct device *dev = ep->dev->dev.parent;
475 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
478 d = ep->descs->rdesc[i].buf_addr;
480 dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_FROM_DEVICE);
482 if (ep->rx_buf[i] != NULL)
483 kfree(ep->rx_buf[i]);
486 for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
489 d = ep->descs->tdesc[i].buf_addr;
491 dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_TO_DEVICE);
493 if (ep->tx_buf[i] != NULL)
494 kfree(ep->tx_buf[i]);
497 dma_free_coherent(dev, sizeof(struct ep93xx_descs), ep->descs,
502 static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
504 struct device *dev = ep->dev->dev.parent;
507 ep->descs = dma_alloc_coherent(dev, sizeof(struct ep93xx_descs),
508 &ep->descs_dma_addr, GFP_KERNEL);
509 if (ep->descs == NULL)
512 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
516 buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
520 d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_FROM_DEVICE);
521 if (dma_mapping_error(dev, d)) {
527 ep->descs->rdesc[i].buf_addr = d;
528 ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
531 for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
535 buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
539 d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_TO_DEVICE);
540 if (dma_mapping_error(dev, d)) {
546 ep->descs->tdesc[i].buf_addr = d;
552 ep93xx_free_buffers(ep);
556 static int ep93xx_start_hw(struct net_device *dev)
558 struct ep93xx_priv *ep = netdev_priv(dev);
562 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
563 for (i = 0; i < 10; i++) {
564 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
570 pr_crit("hw failed to reset\n");
574 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
576 /* Does the PHY support preamble suppress? */
577 if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
578 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
580 /* Receive descriptor ring. */
581 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
582 wrl(ep, REG_RXDQBADD, addr);
583 wrl(ep, REG_RXDCURADD, addr);
584 wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
586 /* Receive status ring. */
587 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
588 wrl(ep, REG_RXSTSQBADD, addr);
589 wrl(ep, REG_RXSTSQCURADD, addr);
590 wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
592 /* Transmit descriptor ring. */
593 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
594 wrl(ep, REG_TXDQBADD, addr);
595 wrl(ep, REG_TXDQCURADD, addr);
596 wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
598 /* Transmit status ring. */
599 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
600 wrl(ep, REG_TXSTSQBADD, addr);
601 wrl(ep, REG_TXSTSQCURADD, addr);
602 wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
604 wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
605 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
606 wrl(ep, REG_GIINTMSK, 0);
608 for (i = 0; i < 10; i++) {
609 if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
615 pr_crit("hw failed to start\n");
619 wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
620 wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
622 wrb(ep, REG_INDAD0, dev->dev_addr[0]);
623 wrb(ep, REG_INDAD1, dev->dev_addr[1]);
624 wrb(ep, REG_INDAD2, dev->dev_addr[2]);
625 wrb(ep, REG_INDAD3, dev->dev_addr[3]);
626 wrb(ep, REG_INDAD4, dev->dev_addr[4]);
627 wrb(ep, REG_INDAD5, dev->dev_addr[5]);
630 wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
632 wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
633 wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
638 static void ep93xx_stop_hw(struct net_device *dev)
640 struct ep93xx_priv *ep = netdev_priv(dev);
643 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
644 for (i = 0; i < 10; i++) {
645 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
651 pr_crit("hw failed to reset\n");
654 static int ep93xx_open(struct net_device *dev)
656 struct ep93xx_priv *ep = netdev_priv(dev);
659 if (ep93xx_alloc_buffers(ep))
662 napi_enable(&ep->napi);
664 if (ep93xx_start_hw(dev)) {
665 napi_disable(&ep->napi);
666 ep93xx_free_buffers(ep);
670 spin_lock_init(&ep->rx_lock);
672 ep->tx_clean_pointer = 0;
674 spin_lock_init(&ep->tx_pending_lock);
677 err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
679 napi_disable(&ep->napi);
681 ep93xx_free_buffers(ep);
685 wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
687 netif_start_queue(dev);
692 static int ep93xx_close(struct net_device *dev)
694 struct ep93xx_priv *ep = netdev_priv(dev);
696 napi_disable(&ep->napi);
697 netif_stop_queue(dev);
699 wrl(ep, REG_GIINTMSK, 0);
700 free_irq(ep->irq, dev);
702 ep93xx_free_buffers(ep);
707 static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
709 struct ep93xx_priv *ep = netdev_priv(dev);
710 struct mii_ioctl_data *data = if_mii(ifr);
712 return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
715 static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
717 strcpy(info->driver, DRV_MODULE_NAME);
718 strcpy(info->version, DRV_MODULE_VERSION);
721 static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
723 struct ep93xx_priv *ep = netdev_priv(dev);
724 return mii_ethtool_gset(&ep->mii, cmd);
727 static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
729 struct ep93xx_priv *ep = netdev_priv(dev);
730 return mii_ethtool_sset(&ep->mii, cmd);
733 static int ep93xx_nway_reset(struct net_device *dev)
735 struct ep93xx_priv *ep = netdev_priv(dev);
736 return mii_nway_restart(&ep->mii);
739 static u32 ep93xx_get_link(struct net_device *dev)
741 struct ep93xx_priv *ep = netdev_priv(dev);
742 return mii_link_ok(&ep->mii);
745 static const struct ethtool_ops ep93xx_ethtool_ops = {
746 .get_drvinfo = ep93xx_get_drvinfo,
747 .get_settings = ep93xx_get_settings,
748 .set_settings = ep93xx_set_settings,
749 .nway_reset = ep93xx_nway_reset,
750 .get_link = ep93xx_get_link,
753 static const struct net_device_ops ep93xx_netdev_ops = {
754 .ndo_open = ep93xx_open,
755 .ndo_stop = ep93xx_close,
756 .ndo_start_xmit = ep93xx_xmit,
757 .ndo_do_ioctl = ep93xx_ioctl,
758 .ndo_validate_addr = eth_validate_addr,
759 .ndo_change_mtu = eth_change_mtu,
760 .ndo_set_mac_address = eth_mac_addr,
763 static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
765 struct net_device *dev;
767 dev = alloc_etherdev(sizeof(struct ep93xx_priv));
771 memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
773 dev->ethtool_ops = &ep93xx_ethtool_ops;
774 dev->netdev_ops = &ep93xx_netdev_ops;
776 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
782 static int ep93xx_eth_remove(struct platform_device *pdev)
784 struct net_device *dev;
785 struct ep93xx_priv *ep;
787 dev = platform_get_drvdata(pdev);
790 platform_set_drvdata(pdev, NULL);
792 ep = netdev_priv(dev);
794 /* @@@ Force down. */
795 unregister_netdev(dev);
796 ep93xx_free_buffers(ep);
798 if (ep->base_addr != NULL)
799 iounmap(ep->base_addr);
801 if (ep->res != NULL) {
802 release_resource(ep->res);
811 static int ep93xx_eth_probe(struct platform_device *pdev)
813 struct ep93xx_eth_data *data;
814 struct net_device *dev;
815 struct ep93xx_priv *ep;
816 struct resource *mem;
822 data = pdev->dev.platform_data;
824 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
825 irq = platform_get_irq(pdev, 0);
829 dev = ep93xx_dev_alloc(data);
834 ep = netdev_priv(dev);
836 SET_NETDEV_DEV(dev, &pdev->dev);
837 netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
839 platform_set_drvdata(pdev, dev);
841 ep->res = request_mem_region(mem->start, resource_size(mem),
842 dev_name(&pdev->dev));
843 if (ep->res == NULL) {
844 dev_err(&pdev->dev, "Could not reserve memory region\n");
849 ep->base_addr = ioremap(mem->start, resource_size(mem));
850 if (ep->base_addr == NULL) {
851 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
857 ep->mii.phy_id = data->phy_id;
858 ep->mii.phy_id_mask = 0x1f;
859 ep->mii.reg_num_mask = 0x1f;
861 ep->mii.mdio_read = ep93xx_mdio_read;
862 ep->mii.mdio_write = ep93xx_mdio_write;
863 ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
865 if (is_zero_ether_addr(dev->dev_addr))
866 random_ether_addr(dev->dev_addr);
868 err = register_netdev(dev);
870 dev_err(&pdev->dev, "Failed to register netdev\n");
874 printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
875 dev->name, ep->irq, dev->dev_addr);
880 ep93xx_eth_remove(pdev);
885 static struct platform_driver ep93xx_eth_driver = {
886 .probe = ep93xx_eth_probe,
887 .remove = ep93xx_eth_remove,
889 .name = "ep93xx-eth",
890 .owner = THIS_MODULE,
894 static int __init ep93xx_eth_init_module(void)
896 printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n");
897 return platform_driver_register(&ep93xx_eth_driver);
900 static void __exit ep93xx_eth_cleanup_module(void)
902 platform_driver_unregister(&ep93xx_eth_driver);
905 module_init(ep93xx_eth_init_module);
906 module_exit(ep93xx_eth_cleanup_module);
907 MODULE_LICENSE("GPL");
908 MODULE_ALIAS("platform:ep93xx-eth");