1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
12 #include "bnx2x_fw_defs.h"
14 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
20 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
22 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
23 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
28 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
29 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
30 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
40 #define NVM_PATH_MAX 2
42 /****************************************************************************
43 * Shared HW configuration *
44 ****************************************************************************/
45 #define PIN_CFG_NA 0x00000000
46 #define PIN_CFG_GPIO0_P0 0x00000001
47 #define PIN_CFG_GPIO1_P0 0x00000002
48 #define PIN_CFG_GPIO2_P0 0x00000003
49 #define PIN_CFG_GPIO3_P0 0x00000004
50 #define PIN_CFG_GPIO0_P1 0x00000005
51 #define PIN_CFG_GPIO1_P1 0x00000006
52 #define PIN_CFG_GPIO2_P1 0x00000007
53 #define PIN_CFG_GPIO3_P1 0x00000008
54 #define PIN_CFG_EPIO0 0x00000009
55 #define PIN_CFG_EPIO1 0x0000000a
56 #define PIN_CFG_EPIO2 0x0000000b
57 #define PIN_CFG_EPIO3 0x0000000c
58 #define PIN_CFG_EPIO4 0x0000000d
59 #define PIN_CFG_EPIO5 0x0000000e
60 #define PIN_CFG_EPIO6 0x0000000f
61 #define PIN_CFG_EPIO7 0x00000010
62 #define PIN_CFG_EPIO8 0x00000011
63 #define PIN_CFG_EPIO9 0x00000012
64 #define PIN_CFG_EPIO10 0x00000013
65 #define PIN_CFG_EPIO11 0x00000014
66 #define PIN_CFG_EPIO12 0x00000015
67 #define PIN_CFG_EPIO13 0x00000016
68 #define PIN_CFG_EPIO14 0x00000017
69 #define PIN_CFG_EPIO15 0x00000018
70 #define PIN_CFG_EPIO16 0x00000019
71 #define PIN_CFG_EPIO17 0x0000001a
72 #define PIN_CFG_EPIO18 0x0000001b
73 #define PIN_CFG_EPIO19 0x0000001c
74 #define PIN_CFG_EPIO20 0x0000001d
75 #define PIN_CFG_EPIO21 0x0000001e
76 #define PIN_CFG_EPIO22 0x0000001f
77 #define PIN_CFG_EPIO23 0x00000020
78 #define PIN_CFG_EPIO24 0x00000021
79 #define PIN_CFG_EPIO25 0x00000022
80 #define PIN_CFG_EPIO26 0x00000023
81 #define PIN_CFG_EPIO27 0x00000024
82 #define PIN_CFG_EPIO28 0x00000025
83 #define PIN_CFG_EPIO29 0x00000026
84 #define PIN_CFG_EPIO30 0x00000027
85 #define PIN_CFG_EPIO31 0x00000028
88 #define EPIO_CFG_NA 0x00000000
89 #define EPIO_CFG_EPIO0 0x00000001
90 #define EPIO_CFG_EPIO1 0x00000002
91 #define EPIO_CFG_EPIO2 0x00000003
92 #define EPIO_CFG_EPIO3 0x00000004
93 #define EPIO_CFG_EPIO4 0x00000005
94 #define EPIO_CFG_EPIO5 0x00000006
95 #define EPIO_CFG_EPIO6 0x00000007
96 #define EPIO_CFG_EPIO7 0x00000008
97 #define EPIO_CFG_EPIO8 0x00000009
98 #define EPIO_CFG_EPIO9 0x0000000a
99 #define EPIO_CFG_EPIO10 0x0000000b
100 #define EPIO_CFG_EPIO11 0x0000000c
101 #define EPIO_CFG_EPIO12 0x0000000d
102 #define EPIO_CFG_EPIO13 0x0000000e
103 #define EPIO_CFG_EPIO14 0x0000000f
104 #define EPIO_CFG_EPIO15 0x00000010
105 #define EPIO_CFG_EPIO16 0x00000011
106 #define EPIO_CFG_EPIO17 0x00000012
107 #define EPIO_CFG_EPIO18 0x00000013
108 #define EPIO_CFG_EPIO19 0x00000014
109 #define EPIO_CFG_EPIO20 0x00000015
110 #define EPIO_CFG_EPIO21 0x00000016
111 #define EPIO_CFG_EPIO22 0x00000017
112 #define EPIO_CFG_EPIO23 0x00000018
113 #define EPIO_CFG_EPIO24 0x00000019
114 #define EPIO_CFG_EPIO25 0x0000001a
115 #define EPIO_CFG_EPIO26 0x0000001b
116 #define EPIO_CFG_EPIO27 0x0000001c
117 #define EPIO_CFG_EPIO28 0x0000001d
118 #define EPIO_CFG_EPIO29 0x0000001e
119 #define EPIO_CFG_EPIO30 0x0000001f
120 #define EPIO_CFG_EPIO31 0x00000020
123 struct shared_hw_cfg { /* NVRAM Offset */
124 /* Up to 16 bytes of NULL-terminated string */
125 u8 part_num[16]; /* 0x104 */
127 u32 config; /* 0x114 */
128 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
129 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
130 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
131 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
132 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
134 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
136 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
138 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
139 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
141 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
142 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
143 /* Whatever MFW found in NVM
144 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
145 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
146 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
147 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
148 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
149 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
150 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
151 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
152 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
153 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
154 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
155 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
156 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
157 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
159 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
160 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
161 #define SHARED_HW_CFG_LED_MAC1 0x00000000
162 #define SHARED_HW_CFG_LED_PHY1 0x00010000
163 #define SHARED_HW_CFG_LED_PHY2 0x00020000
164 #define SHARED_HW_CFG_LED_PHY3 0x00030000
165 #define SHARED_HW_CFG_LED_MAC2 0x00040000
166 #define SHARED_HW_CFG_LED_PHY4 0x00050000
167 #define SHARED_HW_CFG_LED_PHY5 0x00060000
168 #define SHARED_HW_CFG_LED_PHY6 0x00070000
169 #define SHARED_HW_CFG_LED_MAC3 0x00080000
170 #define SHARED_HW_CFG_LED_PHY7 0x00090000
171 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
172 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
173 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
174 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
175 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
178 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
179 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
180 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
181 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
182 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
183 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
184 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
185 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
187 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
188 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
189 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
191 #define SHARED_HW_CFG_ATC_MASK 0x80000000
192 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
193 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
195 u32 config2; /* 0x118 */
196 /* one time auto detect grace period (in sec) */
197 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
198 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
200 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
201 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
203 /* The default value for the core clock is 250MHz and it is
204 achieved by setting the clock change to 4 */
205 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
206 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
208 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
209 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
210 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
212 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
214 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
215 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
216 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
218 /* Output low when PERST is asserted */
219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
221 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
228 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
230 /* The fan failure mechanism is usually related to the PHY type
231 since the power consumption of the board is determined by the PHY.
232 Currently, fan is required for most designs with SFX7101, BCM8727
233 and BCM8481. If a fan is not required for a board which uses one
234 of those PHYs, this field should be set to "Disabled". If a fan is
235 required for a different PHY type, this option should be set to
236 "Enabled". The fan failure indication is expected on SPIO5 */
237 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
238 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
239 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
240 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
241 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
243 /* ASPM Power Management support */
244 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
245 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
247 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
248 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
249 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
251 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
252 tl_control_0 (register 0x2800) */
253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
255 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
257 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
258 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
259 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
261 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
262 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
263 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
265 /* Set the MDC/MDIO access for the first external phy */
266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
274 /* Set the MDC/MDIO access for the second external phy */
275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
284 u32 power_dissipated; /* 0x11c */
285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
286 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
287 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
288 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
289 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
290 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
292 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
293 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
295 u32 ump_nc_si_config; /* 0x120 */
296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
301 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
304 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
309 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
311 u32 board; /* 0x124 */
312 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
313 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
314 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
315 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
316 /* Use the PIN_CFG_XXX defines on top */
317 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
318 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
321 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
323 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
324 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
326 u32 wc_lane_config; /* 0x128 */
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
332 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
334 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
336 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
338 /* TX lane Polarity swap */
339 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
340 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
341 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
342 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
343 /* TX lane Polarity swap */
344 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
345 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
346 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
347 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
349 /* Selects the port layout of the board */
350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
357 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
361 /****************************************************************************
362 * Port HW configuration *
363 ****************************************************************************/
364 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
367 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
368 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
371 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
372 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
374 u32 power_dissipated;
375 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
376 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
377 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
378 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
379 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
380 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
381 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
382 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
385 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
386 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
387 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
388 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
389 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
390 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
391 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
392 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
395 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
396 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
399 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
402 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
407 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
410 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
413 /* Default values: 2P-64, 4P-32 */
414 u32 pf_config; /* 0x158 */
415 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
416 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
418 /* Default values: 17 */
419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
420 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8
422 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
423 #define PORT_HW_CFG_FLR_ENABLED 0x00010000
425 u32 vf_config; /* 0x15C */
426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
427 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
430 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
432 u32 mf_pci_id; /* 0x160 */
433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
434 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
436 /* Controls the TX laser of the SFP+ module */
437 u32 sfp_ctrl; /* 0x164 */
438 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
439 #define PORT_HW_CFG_TX_LASER_SHIFT 0
440 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
441 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
442 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
443 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
444 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
446 /* Controls the fault module LED of the SFP+ */
447 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
448 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
452 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
453 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
455 /* The output pin TX_DIS that controls the TX laser of the SFP+
456 module. Use the PIN_CFG_XXX defines on top */
457 u32 e3_sfp_ctrl; /* 0x168 */
458 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
459 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
461 /* The output pin for SFPP_TYPE which turns on the Fault module LED */
462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
463 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
465 /* The input pin MOD_ABS that indicates whether SFP+ module is
466 present or not. Use the PIN_CFG_XXX defines on top */
467 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
468 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
470 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+
471 module. Use the PIN_CFG_XXX defines on top */
472 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
473 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
476 * The input pin which signals module transmit fault. Use the
477 * PIN_CFG_XXX defines on top
479 u32 e3_cmn_pin_cfg; /* 0x16C */
480 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
481 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
483 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
485 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
486 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
489 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
492 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
493 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
495 /* The output pin values BSC_SEL which selects the I2C for this port
497 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
498 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
502 * The input pin I_FAULT which indicate over-current has occurred.
503 * Use the PIN_CFG_XXX defines on top
505 u32 e3_cmn_pin_cfg1; /* 0x170 */
506 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
507 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
508 u32 reserved0[7]; /* 0x174 */
510 u32 aeu_int_mask; /* 0x190 */
512 u32 media_type; /* 0x194 */
513 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
514 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
516 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
517 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
519 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
520 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
522 /* 4 times 16 bits for all 4 lanes. In case external PHY is present
523 (not direct mode), those values will not take effect on the 4 XGXS
524 lanes. For some external PHYs (such as 8706 and 8726) the values
525 will be used to configure the external PHY in those cases, not
526 all 4 values are needed. */
527 u16 xgxs_config_rx[4]; /* 0x198 */
528 u16 xgxs_config_tx[4]; /* 0x1A0 */
530 /* For storing FCOE mac on shared memory */
531 u32 fcoe_fip_mac_upper;
532 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
533 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
534 u32 fcoe_fip_mac_lower;
536 u32 fcoe_wwn_port_name_upper;
537 u32 fcoe_wwn_port_name_lower;
539 u32 fcoe_wwn_node_name_upper;
540 u32 fcoe_wwn_node_name_lower;
542 u32 Reserved1[49]; /* 0x1C0 */
544 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
546 u32 xgbt_phy_cfg; /* 0x284 */
547 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
548 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
550 u32 default_cfg; /* 0x288 */
551 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
552 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
553 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
554 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
555 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
556 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
558 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
559 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
560 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
561 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
562 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
563 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
565 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
566 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
567 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
568 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
569 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
570 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
572 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
573 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
574 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
575 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
576 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
577 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
579 /* When KR link is required to be set to force which is not
580 KR-compliant, this parameter determine what is the trigger for it.
581 When GPIO is selected, low input will force the speed. Currently
582 default speed is 1G. In the future, it may be widen to select the
583 forced speed in with another parameter. Note when force-1G is
584 enabled, it override option 56: Link Speed option. */
585 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
586 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
587 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
588 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
589 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
590 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
591 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
592 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
593 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
594 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
595 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
596 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
597 /* Enable to determine with which GPIO to reset the external phy */
598 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
599 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
600 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
604 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
605 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
606 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
607 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
608 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
610 /* Enable BAM on KR */
611 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
612 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
613 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
614 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
616 /* Enable Common Mode Sense */
617 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
618 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
619 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
620 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
622 /* Determine the Serdes electrical interface */
623 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
624 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
625 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
626 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
627 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
628 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
629 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
630 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
633 u32 speed_capability_mask2; /* 0x28C */
634 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
635 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
636 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
637 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
638 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
639 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
647 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
649 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
650 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
654 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
657 /* In the case where two media types (e.g. copper and fiber) are
658 present and electrically active at the same time, PHY Selection
659 will determine which of the two PHYs will be designated as the
660 Active PHY and used for a connection to the network. */
661 u32 multi_phy_config; /* 0x290 */
662 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
663 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
664 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
665 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
666 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
667 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
668 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
670 /* When enabled, all second phy nvram parameters will be swapped
671 with the first phy parameters */
672 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
673 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
674 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
675 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
678 /* Address of the second external phy */
679 u32 external_phy_config2; /* 0x294 */
680 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
681 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
683 /* The second XGXS external PHY type */
684 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
685 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
686 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
687 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
688 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
707 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
708 8706, 8726 and 8727) not all 4 values are needed. */
709 u16 xgxs_config2_rx[4]; /* 0x296 */
710 u16 xgxs_config2_tx[4]; /* 0x2A0 */
713 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
714 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
716 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
718 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
720 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
722 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
723 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
724 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
725 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
726 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
727 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
728 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
730 /* Indicate whether to swap the external phy polarity */
731 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
732 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
733 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
736 u32 external_phy_config;
737 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
738 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
740 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
741 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
742 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
743 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
744 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
763 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
764 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
766 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
767 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
768 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
769 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
770 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
771 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
773 u32 speed_capability_mask;
774 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
775 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
776 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
777 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
778 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
782 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
783 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
784 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
786 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
787 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
788 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
789 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
790 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
794 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
795 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
796 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
798 /* A place to hold the original MAC address as a backup */
799 u32 backup_mac_upper; /* 0x2B4 */
800 u32 backup_mac_lower; /* 0x2B8 */
805 /****************************************************************************
806 * Shared Feature configuration *
807 ****************************************************************************/
808 struct shared_feat_cfg { /* NVRAM Offset */
810 u32 config; /* 0x450 */
811 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
813 /* Use NVRAM values instead of HW default values */
814 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
816 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
818 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
821 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
822 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
823 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
825 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
826 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
828 /* Override the OTP back to single function mode. When using GPIO,
829 high means only SF, 0 is according to CLP configuration */
830 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
831 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
832 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
833 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
834 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
835 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
836 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
838 /* The interval in seconds between sending LLDP packets. Set to zero
839 to disable the feature */
840 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
841 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
843 /* The assigned device type ID for LLDP usage */
844 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
845 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
850 /****************************************************************************
851 * Port Feature configuration *
852 ****************************************************************************/
853 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
856 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
857 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
858 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
859 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
860 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
861 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
862 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
863 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
864 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
865 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
866 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
867 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
868 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
869 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
870 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
871 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
872 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
873 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
874 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
875 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
876 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
877 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
878 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
879 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
880 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
881 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
882 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
883 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
884 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
885 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
886 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
887 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
888 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
889 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
890 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
891 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
893 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
894 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
895 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
897 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
898 #define PORT_FEATURE_EN_SIZE_SHIFT 24
899 #define PORT_FEATURE_WOL_ENABLED 0x01000000
900 #define PORT_FEATURE_MBA_ENABLED 0x02000000
901 #define PORT_FEATURE_MFW_ENABLED 0x04000000
903 /* Advertise expansion ROM even if MBA is disabled */
904 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
905 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
906 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
908 /* Check the optic vendor via i2c against a list of approved modules
909 in a separate nvram image */
910 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
911 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
912 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
914 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
916 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
917 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
920 /* Default is used when driver sets to "auto" mode */
921 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
922 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
923 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
924 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
925 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
926 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
927 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
928 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
929 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
932 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
933 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
934 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
935 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
936 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
937 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
938 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
939 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
941 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
942 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
944 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
945 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
946 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
947 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
948 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
949 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
950 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
951 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
952 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
953 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
954 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
955 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
956 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
957 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
958 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
963 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
964 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
965 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
966 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
967 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
968 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
969 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
970 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
971 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
972 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
973 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
974 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
975 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
976 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
977 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
978 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
979 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
980 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
981 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
982 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
983 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
984 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
985 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
986 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
988 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
989 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
990 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
993 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
994 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
995 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
998 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
999 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
1000 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
1001 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
1002 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
1005 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1006 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1009 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1010 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1011 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1012 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1013 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1014 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1015 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1016 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1017 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1022 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1024 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1025 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1026 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1028 u32 link_config; /* Used as HW defaults for the driver */
1029 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1030 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1031 /* (forced) low speed switch (< 10G) */
1032 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1033 /* (forced) high speed switch (>= 10G) */
1034 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1035 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1036 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1038 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1039 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1040 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1041 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1042 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1043 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1044 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1045 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1046 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1047 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1048 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1050 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1051 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1052 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1053 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1054 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1055 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1056 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1058 /* The default for MCP link configuration,
1059 uses the same defines as link_config */
1060 u32 mfw_wol_link_cfg;
1062 /* The default for the driver of the second external phy,
1063 uses the same defines as link_config */
1064 u32 link_config2; /* 0x47C */
1066 /* The default for MCP of the second external phy,
1067 uses the same defines as link_config */
1068 u32 mfw_wol_link_cfg2; /* 0x480 */
1070 u32 Reserved2[17]; /* 0x484 */
1075 /****************************************************************************
1076 * Device Information *
1077 ****************************************************************************/
1078 struct shm_dev_info { /* size */
1080 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
1082 struct shared_hw_cfg shared_hw_config; /* 40 */
1084 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
1086 struct shared_feat_cfg shared_feature_config; /* 4 */
1088 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
1093 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1094 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1105 #define E1_FUNC_MAX 2
1106 #define E1H_FUNC_MAX 8
1107 #define E2_FUNC_MAX 4 /* per path */
1116 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */
1117 /* This value (in milliseconds) determines the frequency of the driver
1118 * issuing the PULSE message code. The firmware monitors this periodic
1119 * pulse to determine when to switch to an OS-absent mode. */
1120 #define DRV_PULSE_PERIOD_MS 250
1122 /* This value (in milliseconds) determines how long the driver should
1123 * wait for an acknowledgement from the firmware before timing out. Once
1124 * the firmware has timed out, the driver will assume there is no firmware
1125 * running and there won't be any firmware-driver synchronization during a
1127 #define FW_ACK_TIME_OUT_MS 5000
1129 #define FW_ACK_POLL_TIME_MS 1
1131 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1133 #define MFW_TRACE_SIGNATURE 0x54524342
1135 /****************************************************************************
1136 * Driver <-> FW Mailbox *
1137 ****************************************************************************/
1138 struct drv_port_mb {
1141 /* Driver should update this field on any link change event */
1143 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1144 #define LINK_STATUS_LINK_UP 0x00000001
1145 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1146 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1147 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1148 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1149 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1150 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1151 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1152 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1153 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1154 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1155 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1156 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1157 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1158 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1159 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1160 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1161 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1163 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1164 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1166 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1167 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1168 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1170 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1171 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1172 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1173 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1174 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1175 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1176 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1178 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1179 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1181 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1182 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1184 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1185 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1186 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1187 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1188 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1190 #define LINK_STATUS_SERDES_LINK 0x00100000
1192 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1193 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1194 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1195 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1197 #define LINK_STATUS_PFC_ENABLED 0x20000000
1199 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1205 /* MCP firmware does not use this field */
1206 u32 ext_phy_fw_version;
1211 struct drv_func_mb {
1214 #define DRV_MSG_CODE_MASK 0xffff0000
1215 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1216 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1217 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1218 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1219 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1220 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1221 #define DRV_MSG_CODE_DCC_OK 0x30000000
1222 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1223 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1224 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1225 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1226 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1227 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1228 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1229 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1231 * The optic module verification command requires bootcode
1232 * v5.0.6 or later, te specific optic module verification command
1233 * requires bootcode v5.2.12 or later
1235 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1236 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1237 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1238 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1239 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1240 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1241 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1242 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1244 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1245 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1247 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1249 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1250 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1251 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1252 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1253 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1255 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1256 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1258 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1259 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1260 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1262 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1264 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1265 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1267 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1268 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1269 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1270 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1272 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1275 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1276 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1279 #define FW_MSG_CODE_MASK 0xffff0000
1280 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1281 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1282 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1283 /* Load common chip is supported from bc 6.0.0 */
1284 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1285 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1287 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1288 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1289 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1290 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1291 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1292 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1293 #define FW_MSG_CODE_DCC_DONE 0x30100000
1294 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1295 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1296 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1297 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1298 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1299 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1300 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1301 #define FW_MSG_CODE_NO_KEY 0x80f00000
1302 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1303 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1304 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1305 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1306 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1307 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1308 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1309 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1310 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1311 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1312 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1314 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1315 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1316 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1317 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1318 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1320 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1321 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1323 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1324 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1326 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1328 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1329 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1330 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1331 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1333 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1338 #define DRV_PULSE_SEQ_MASK 0x00007fff
1339 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1341 * The system time is in the format of
1342 * (year-2001)*12*32 + month*32 + day.
1344 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1346 * Indicate to the firmware not to go into the
1347 * OS-absent when it is not getting driver pulse.
1348 * This is used for debugging as well for PXE(MBA).
1352 #define MCP_PULSE_SEQ_MASK 0x00007fff
1353 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1354 /* Indicates to the driver not to assert due to lack
1355 * of MCP response */
1356 #define MCP_EVENT_MASK 0xffff0000
1357 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1359 u32 iscsi_boot_signature;
1360 u32 iscsi_boot_block_offset;
1363 #define DRV_STATUS_PMF 0x00000001
1364 #define DRV_STATUS_VF_DISABLED 0x00000002
1365 #define DRV_STATUS_SET_MF_BW 0x00000004
1366 #define DRV_STATUS_LINK_EVENT 0x00000008
1368 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1369 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1370 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1371 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1372 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1373 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1374 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1376 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1377 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1378 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1379 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1380 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1381 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1382 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1384 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1387 #define VIRT_MAC_SIGN_MASK 0xffff0000
1388 #define VIRT_MAC_SIGNATURE 0x564d0000
1394 /****************************************************************************
1395 * Management firmware state *
1396 ****************************************************************************/
1397 /* Allocate 440 bytes for management firmware */
1398 #define MGMTFW_STATE_WORD_SIZE 110
1400 struct mgmtfw_state {
1401 u32 opaque[MGMTFW_STATE_WORD_SIZE];
1405 /****************************************************************************
1406 * Multi-Function configuration *
1407 ****************************************************************************/
1408 struct shared_mf_cfg {
1411 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1413 #define SHARED_MF_CLP_EXIT 0x00000001
1415 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1419 struct port_mf_cfg {
1421 u32 dynamic_cfg; /* device control channel */
1422 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1423 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1424 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1430 struct func_mf_cfg {
1434 /* function 0 of each port cannot be hidden */
1435 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1437 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1438 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1439 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1440 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1441 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1442 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1443 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1445 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1446 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1449 /* 0 - low priority, 3 - high priority */
1450 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1451 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1452 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1455 /* value range - 0..100, increments in 100Mbps */
1456 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1457 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1458 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1459 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1460 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1461 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1463 u32 mac_upper; /* MAC */
1464 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1465 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1466 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1468 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1470 u32 e1hov_tag; /* VNI */
1471 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1472 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1473 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1475 /* afex default VLAN ID - 12 bits */
1476 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
1477 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16
1480 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
1481 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
1482 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
1483 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8
1484 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
1485 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
1486 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16
1491 enum mf_cfg_afex_vlan_mode {
1492 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1493 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1494 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1497 /* This structure is not applicable and should not be accessed on 57711 */
1498 struct func_ext_cfg {
1500 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF
1501 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1502 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1503 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1504 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1505 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1507 u32 iscsi_mac_addr_upper;
1508 u32 iscsi_mac_addr_lower;
1510 u32 fcoe_mac_addr_upper;
1511 u32 fcoe_mac_addr_lower;
1513 u32 fcoe_wwn_port_name_upper;
1514 u32 fcoe_wwn_port_name_lower;
1516 u32 fcoe_wwn_node_name_upper;
1517 u32 fcoe_wwn_node_name_lower;
1520 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1521 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1522 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1523 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1524 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1525 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1530 struct shared_mf_cfg shared_mf_config; /* 0x4 */
1532 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];
1533 /* for all chips, there are 8 mf functions */
1534 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1536 * Extended configuration per function - this array does not exist and
1537 * should not be accessed on 57711
1539 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1542 /****************************************************************************
1543 * Shared Memory Region *
1544 ****************************************************************************/
1545 struct shmem_region { /* SharedMem Offset (size) */
1547 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1548 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1549 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1551 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1552 #define SHR_MEM_VALIDITY_MB 0x00200000
1553 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1554 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1555 /* One licensing bit should be set */
1556 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1557 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1558 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1559 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1561 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1562 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1563 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1564 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1565 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1566 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1568 struct shm_dev_info dev_info; /* 0x8 (0x438) */
1570 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1572 /* FW information (for internal FW use) */
1573 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
1574 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1576 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1579 /* This is a variable length array */
1580 /* the number of function depends on the chip type */
1581 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1583 /* the number of function depends on the chip type */
1584 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1587 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1589 /****************************************************************************
1590 * Shared Memory 2 Region *
1591 ****************************************************************************/
1592 /* The fw_flr_ack is actually built in the following way: */
1594 /* 64 bit: VF ack */
1595 /* 8 bit: ios_dis_ack */
1596 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1597 /* u32. The fw must have the VF right after the PF since this is how it */
1598 /* access arrays(it expects always the VF to reside after the PF, and that */
1599 /* makes the calculation much easier for it. ) */
1600 /* In order to answer both limitations, and keep the struct small, the code */
1601 /* will abuse the structure defined here to achieve the actual partition */
1603 /****************************************************************************/
1613 struct fw_flr_ack ack;
1616 /**** SUPPORT FOR SHMEM ARRRAYS ***
1617 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1618 * define arrays with storage types smaller then unsigned dwords.
1619 * The macros below add generic support for SHMEM arrays with numeric elements
1620 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1621 * array with individual bit-filed elements accessed using shifts and masks.
1625 /* eb is the bitwidth of a single element */
1626 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1627 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1629 /* the bit-position macro allows the used to flip the order of the arrays
1630 * elements on a per byte or word boundary.
1632 * example: an array with 8 entries each 4 bit wide. This array will fit into
1633 * a single dword. The diagrmas below show the array order of the nibbles.
1635 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1638 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1641 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1644 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1647 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1650 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1653 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1654 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1655 (((i)%((fb)/(eb))) * (eb)))
1657 #define SHMEM_ARRAY_GET(a, i, eb, fb) \
1658 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1659 SHMEM_ARRAY_MASK(eb))
1661 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1663 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1664 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1665 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1666 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1670 /****START OF DCBX STRUCTURES DECLARATIONS****/
1671 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1672 #define DCBX_PRI_PG_BITWIDTH 4
1673 #define DCBX_PRI_PG_FBITS 8
1674 #define DCBX_PRI_PG_GET(a, i) \
1675 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1676 #define DCBX_PRI_PG_SET(a, i, val) \
1677 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1678 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1679 #define DCBX_BW_PG_BITWIDTH 8
1680 #define DCBX_PG_BW_GET(a, i) \
1681 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1682 #define DCBX_PG_BW_SET(a, i, val) \
1683 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1684 #define DCBX_STRICT_PRI_PG 15
1685 #define DCBX_MAX_APP_PROTOCOL 16
1686 #define FCOE_APP_IDX 0
1687 #define ISCSI_APP_IDX 1
1688 #define PREDEFINED_APP_IDX_MAX 2
1691 /* Big/Little endian have the same representation. */
1692 struct dcbx_ets_feature {
1694 * For Admin MIB - is this feature supported by the
1695 * driver | For Local MIB - should this feature be enabled.
1702 /* Driver structure in LE */
1703 struct dcbx_pfc_feature {
1706 #define DCBX_PFC_PRI_0 0x01
1707 #define DCBX_PFC_PRI_1 0x02
1708 #define DCBX_PFC_PRI_2 0x04
1709 #define DCBX_PFC_PRI_3 0x08
1710 #define DCBX_PFC_PRI_4 0x10
1711 #define DCBX_PFC_PRI_5 0x20
1712 #define DCBX_PFC_PRI_6 0x40
1713 #define DCBX_PFC_PRI_7 0x80
1717 #elif defined(__LITTLE_ENDIAN)
1722 #define DCBX_PFC_PRI_0 0x01
1723 #define DCBX_PFC_PRI_1 0x02
1724 #define DCBX_PFC_PRI_2 0x04
1725 #define DCBX_PFC_PRI_3 0x08
1726 #define DCBX_PFC_PRI_4 0x10
1727 #define DCBX_PFC_PRI_5 0x20
1728 #define DCBX_PFC_PRI_6 0x40
1729 #define DCBX_PFC_PRI_7 0x80
1733 struct dcbx_app_priority_entry {
1738 #define DCBX_APP_ENTRY_VALID 0x01
1739 #define DCBX_APP_ENTRY_SF_MASK 0x30
1740 #define DCBX_APP_ENTRY_SF_SHIFT 4
1741 #define DCBX_APP_SF_ETH_TYPE 0x10
1742 #define DCBX_APP_SF_PORT 0x20
1743 #elif defined(__LITTLE_ENDIAN)
1745 #define DCBX_APP_ENTRY_VALID 0x01
1746 #define DCBX_APP_ENTRY_SF_MASK 0x30
1747 #define DCBX_APP_ENTRY_SF_SHIFT 4
1748 #define DCBX_APP_SF_ETH_TYPE 0x10
1749 #define DCBX_APP_SF_PORT 0x20
1756 /* FW structure in BE */
1757 struct dcbx_app_priority_feature {
1763 #elif defined(__LITTLE_ENDIAN)
1769 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1772 /* FW structure in BE */
1773 struct dcbx_features {
1775 struct dcbx_ets_feature ets;
1777 struct dcbx_pfc_feature pfc;
1779 struct dcbx_app_priority_feature app;
1782 /* LLDP protocol parameters */
1783 /* FW structure in BE */
1784 struct lldp_params {
1786 u8 msg_fast_tx_interval;
1790 #define LLDP_TX_ONLY 0x01
1791 #define LLDP_RX_ONLY 0x02
1792 #define LLDP_TX_RX 0x03
1793 #define LLDP_DISABLED 0x04
1798 #elif defined(__LITTLE_ENDIAN)
1800 #define LLDP_TX_ONLY 0x01
1801 #define LLDP_RX_ONLY 0x02
1802 #define LLDP_TX_RX 0x03
1803 #define LLDP_DISABLED 0x04
1806 u8 msg_fast_tx_interval;
1812 #define REM_CHASSIS_ID_STAT_LEN 4
1813 #define REM_PORT_ID_STAT_LEN 4
1814 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1815 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1816 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1817 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1820 struct lldp_dcbx_stat {
1821 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1822 #define LOCAL_PORT_ID_STAT_LEN 2
1823 /* Holds local Chassis ID 8B payload of constant subtype 4. */
1824 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1825 /* Holds local Port ID 8B payload of constant subtype 3. */
1826 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1827 /* Number of DCBX frames transmitted. */
1828 u32 num_tx_dcbx_pkts;
1829 /* Number of DCBX frames received. */
1830 u32 num_rx_dcbx_pkts;
1833 /* ADMIN MIB - DCBX local machine default configuration. */
1834 struct lldp_admin_mib {
1836 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1837 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1838 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1839 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1840 #define DCBX_ETS_RECO_VALID 0x00000010
1841 #define DCBX_ETS_WILLING 0x00000020
1842 #define DCBX_PFC_WILLING 0x00000040
1843 #define DCBX_APP_WILLING 0x00000080
1844 #define DCBX_VERSION_CEE 0x00000100
1845 #define DCBX_VERSION_IEEE 0x00000200
1846 #define DCBX_DCBX_ENABLED 0x00000400
1847 #define DCBX_CEE_VERSION_MASK 0x0000f000
1848 #define DCBX_CEE_VERSION_SHIFT 12
1849 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1850 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1851 struct dcbx_features features;
1854 /* REMOTE MIB - remote machine DCBX configuration. */
1855 struct lldp_remote_mib {
1858 #define DCBX_ETS_TLV_RX 0x00000001
1859 #define DCBX_PFC_TLV_RX 0x00000002
1860 #define DCBX_APP_TLV_RX 0x00000004
1861 #define DCBX_ETS_RX_ERROR 0x00000010
1862 #define DCBX_PFC_RX_ERROR 0x00000020
1863 #define DCBX_APP_RX_ERROR 0x00000040
1864 #define DCBX_ETS_REM_WILLING 0x00000100
1865 #define DCBX_PFC_REM_WILLING 0x00000200
1866 #define DCBX_APP_REM_WILLING 0x00000400
1867 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1868 #define DCBX_REMOTE_MIB_VALID 0x00002000
1869 struct dcbx_features features;
1873 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1874 struct lldp_local_mib {
1876 /* Indicates if there is mismatch with negotiation results. */
1878 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1879 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1880 #define DCBX_LOCAL_APP_ERROR 0x00000004
1881 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1882 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1883 #define DCBX_REMOTE_MIB_ERROR 0x00000040
1884 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
1885 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
1886 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
1887 struct dcbx_features features;
1890 /***END OF DCBX STRUCTURES DECLARATIONS***/
1892 struct ncsi_oem_fcoe_features {
1894 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
1895 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
1897 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
1898 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16
1901 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
1902 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
1904 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
1905 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16
1908 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
1909 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
1911 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
1912 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16
1915 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
1916 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
1919 struct ncsi_oem_data {
1920 u32 driver_version[4];
1921 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
1924 struct shmem2_region {
1926 u32 size; /* 0x0000 */
1928 u32 dcc_support; /* 0x0004 */
1929 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
1930 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
1931 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
1932 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
1933 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
1934 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
1936 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */
1938 * For backwards compatibility, if the mf_cfg_addr does not exist
1939 * (the size filed is smaller than 0xc) the mf_cfg resides at the
1940 * end of struct shmem_region
1942 u32 mf_cfg_addr; /* 0x0010 */
1943 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
1945 struct fw_flr_mb flr_mb; /* 0x0014 */
1946 u32 dcbx_lldp_params_offset; /* 0x0028 */
1947 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
1948 u32 dcbx_neg_res_offset; /* 0x002c */
1949 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
1950 u32 dcbx_remote_mib_offset; /* 0x0030 */
1951 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
1953 * The other shmemX_base_addr holds the other path's shmem address
1954 * required for example in case of common phy init, or for path1 to know
1955 * the address of mcp debug trace which is located in offset from shmem
1958 u32 other_shmem_base_addr; /* 0x0034 */
1959 u32 other_shmem2_base_addr; /* 0x0038 */
1961 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
1962 * which were disabled/flred
1964 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */
1967 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
1970 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
1972 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */
1973 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
1976 * edebug_driver_if field is used to transfer messages between edebug
1977 * app to the driver through shmem2.
1980 * bits 0-2 - function number / instance of driver to perform request
1981 * bits 3-5 - op code / is_ack?
1984 u32 edebug_driver_if[2]; /* 0x0068 */
1985 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
1986 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
1987 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
1989 u32 nvm_retain_bitmap_addr; /* 0x0070 */
1991 /* afex support of that driver */
1992 u32 afex_driver_support; /* 0x0074 */
1993 #define SHMEM_AFEX_VERSION_MASK 0x100f
1994 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
1995 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
1997 /* driver receives addr in scratchpad to which it should respond */
1998 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2000 /* generic params from MCP to driver (value depends on the msg sent
2003 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
2004 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
2006 u32 swim_base_addr; /* 0x0108 */
2010 /* bitmap notifying which VIF profiles stored in nvram are enabled by
2013 u32 afex_profiles_enabled[2];
2015 /* generic flags controlled by the driver */
2017 #define DRV_FLAGS_DCB_CONFIGURED 0x1
2019 /* pointer to extended dev_info shared data copied from nvm image */
2020 u32 extended_dev_info_shared_addr;
2021 u32 ncsi_oem_data_addr;
2023 u32 ocsd_host_addr; /* initialized by option ROM */
2024 u32 ocbb_host_addr; /* initialized by option ROM */
2025 u32 ocsd_req_update_interval; /* initialized by option ROM */
2026 u32 temperature_in_half_celsius;
2027 u32 glob_struct_in_host;
2029 u32 dcbx_neg_res_ext_offset;
2030 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2032 u32 drv_capabilities_flag[E2_FUNC_MAX];
2033 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2034 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2035 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2036 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2038 u32 extended_dev_info_shared_cfg_size;
2040 u32 dcbx_en[PORT_MAX];
2042 /* The offset points to the multi threaded meta structure */
2043 u32 multi_thread_data_offset;
2045 /* address of DMAable host address holding values from the drivers */
2046 u32 drv_info_host_addr_lo;
2047 u32 drv_info_host_addr_hi;
2049 /* general values written by the MFW (such as current version) */
2050 u32 drv_info_control;
2051 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2052 #define DRV_INFO_CONTROL_VER_SHIFT 0
2053 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2054 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
2055 u32 ibft_host_addr; /* initialized by option ROM */
2060 u32 rx_stat_ifhcinoctets;
2061 u32 rx_stat_ifhcinbadoctets;
2062 u32 rx_stat_etherstatsfragments;
2063 u32 rx_stat_ifhcinucastpkts;
2064 u32 rx_stat_ifhcinmulticastpkts;
2065 u32 rx_stat_ifhcinbroadcastpkts;
2066 u32 rx_stat_dot3statsfcserrors;
2067 u32 rx_stat_dot3statsalignmenterrors;
2068 u32 rx_stat_dot3statscarriersenseerrors;
2069 u32 rx_stat_xonpauseframesreceived;
2070 u32 rx_stat_xoffpauseframesreceived;
2071 u32 rx_stat_maccontrolframesreceived;
2072 u32 rx_stat_xoffstateentered;
2073 u32 rx_stat_dot3statsframestoolong;
2074 u32 rx_stat_etherstatsjabbers;
2075 u32 rx_stat_etherstatsundersizepkts;
2076 u32 rx_stat_etherstatspkts64octets;
2077 u32 rx_stat_etherstatspkts65octetsto127octets;
2078 u32 rx_stat_etherstatspkts128octetsto255octets;
2079 u32 rx_stat_etherstatspkts256octetsto511octets;
2080 u32 rx_stat_etherstatspkts512octetsto1023octets;
2081 u32 rx_stat_etherstatspkts1024octetsto1522octets;
2082 u32 rx_stat_etherstatspktsover1522octets;
2084 u32 rx_stat_falsecarriererrors;
2086 u32 tx_stat_ifhcoutoctets;
2087 u32 tx_stat_ifhcoutbadoctets;
2088 u32 tx_stat_etherstatscollisions;
2089 u32 tx_stat_outxonsent;
2090 u32 tx_stat_outxoffsent;
2091 u32 tx_stat_flowcontroldone;
2092 u32 tx_stat_dot3statssinglecollisionframes;
2093 u32 tx_stat_dot3statsmultiplecollisionframes;
2094 u32 tx_stat_dot3statsdeferredtransmissions;
2095 u32 tx_stat_dot3statsexcessivecollisions;
2096 u32 tx_stat_dot3statslatecollisions;
2097 u32 tx_stat_ifhcoutucastpkts;
2098 u32 tx_stat_ifhcoutmulticastpkts;
2099 u32 tx_stat_ifhcoutbroadcastpkts;
2100 u32 tx_stat_etherstatspkts64octets;
2101 u32 tx_stat_etherstatspkts65octetsto127octets;
2102 u32 tx_stat_etherstatspkts128octetsto255octets;
2103 u32 tx_stat_etherstatspkts256octetsto511octets;
2104 u32 tx_stat_etherstatspkts512octetsto1023octets;
2105 u32 tx_stat_etherstatspkts1024octetsto1522octets;
2106 u32 tx_stat_etherstatspktsover1522octets;
2107 u32 tx_stat_dot3statsinternalmactransmiterrors;
2111 struct bmac1_stats {
2112 u32 tx_stat_gtpkt_lo;
2113 u32 tx_stat_gtpkt_hi;
2114 u32 tx_stat_gtxpf_lo;
2115 u32 tx_stat_gtxpf_hi;
2116 u32 tx_stat_gtfcs_lo;
2117 u32 tx_stat_gtfcs_hi;
2118 u32 tx_stat_gtmca_lo;
2119 u32 tx_stat_gtmca_hi;
2120 u32 tx_stat_gtbca_lo;
2121 u32 tx_stat_gtbca_hi;
2122 u32 tx_stat_gtfrg_lo;
2123 u32 tx_stat_gtfrg_hi;
2124 u32 tx_stat_gtovr_lo;
2125 u32 tx_stat_gtovr_hi;
2126 u32 tx_stat_gt64_lo;
2127 u32 tx_stat_gt64_hi;
2128 u32 tx_stat_gt127_lo;
2129 u32 tx_stat_gt127_hi;
2130 u32 tx_stat_gt255_lo;
2131 u32 tx_stat_gt255_hi;
2132 u32 tx_stat_gt511_lo;
2133 u32 tx_stat_gt511_hi;
2134 u32 tx_stat_gt1023_lo;
2135 u32 tx_stat_gt1023_hi;
2136 u32 tx_stat_gt1518_lo;
2137 u32 tx_stat_gt1518_hi;
2138 u32 tx_stat_gt2047_lo;
2139 u32 tx_stat_gt2047_hi;
2140 u32 tx_stat_gt4095_lo;
2141 u32 tx_stat_gt4095_hi;
2142 u32 tx_stat_gt9216_lo;
2143 u32 tx_stat_gt9216_hi;
2144 u32 tx_stat_gt16383_lo;
2145 u32 tx_stat_gt16383_hi;
2146 u32 tx_stat_gtmax_lo;
2147 u32 tx_stat_gtmax_hi;
2148 u32 tx_stat_gtufl_lo;
2149 u32 tx_stat_gtufl_hi;
2150 u32 tx_stat_gterr_lo;
2151 u32 tx_stat_gterr_hi;
2152 u32 tx_stat_gtbyt_lo;
2153 u32 tx_stat_gtbyt_hi;
2155 u32 rx_stat_gr64_lo;
2156 u32 rx_stat_gr64_hi;
2157 u32 rx_stat_gr127_lo;
2158 u32 rx_stat_gr127_hi;
2159 u32 rx_stat_gr255_lo;
2160 u32 rx_stat_gr255_hi;
2161 u32 rx_stat_gr511_lo;
2162 u32 rx_stat_gr511_hi;
2163 u32 rx_stat_gr1023_lo;
2164 u32 rx_stat_gr1023_hi;
2165 u32 rx_stat_gr1518_lo;
2166 u32 rx_stat_gr1518_hi;
2167 u32 rx_stat_gr2047_lo;
2168 u32 rx_stat_gr2047_hi;
2169 u32 rx_stat_gr4095_lo;
2170 u32 rx_stat_gr4095_hi;
2171 u32 rx_stat_gr9216_lo;
2172 u32 rx_stat_gr9216_hi;
2173 u32 rx_stat_gr16383_lo;
2174 u32 rx_stat_gr16383_hi;
2175 u32 rx_stat_grmax_lo;
2176 u32 rx_stat_grmax_hi;
2177 u32 rx_stat_grpkt_lo;
2178 u32 rx_stat_grpkt_hi;
2179 u32 rx_stat_grfcs_lo;
2180 u32 rx_stat_grfcs_hi;
2181 u32 rx_stat_grmca_lo;
2182 u32 rx_stat_grmca_hi;
2183 u32 rx_stat_grbca_lo;
2184 u32 rx_stat_grbca_hi;
2185 u32 rx_stat_grxcf_lo;
2186 u32 rx_stat_grxcf_hi;
2187 u32 rx_stat_grxpf_lo;
2188 u32 rx_stat_grxpf_hi;
2189 u32 rx_stat_grxuo_lo;
2190 u32 rx_stat_grxuo_hi;
2191 u32 rx_stat_grjbr_lo;
2192 u32 rx_stat_grjbr_hi;
2193 u32 rx_stat_grovr_lo;
2194 u32 rx_stat_grovr_hi;
2195 u32 rx_stat_grflr_lo;
2196 u32 rx_stat_grflr_hi;
2197 u32 rx_stat_grmeg_lo;
2198 u32 rx_stat_grmeg_hi;
2199 u32 rx_stat_grmeb_lo;
2200 u32 rx_stat_grmeb_hi;
2201 u32 rx_stat_grbyt_lo;
2202 u32 rx_stat_grbyt_hi;
2203 u32 rx_stat_grund_lo;
2204 u32 rx_stat_grund_hi;
2205 u32 rx_stat_grfrg_lo;
2206 u32 rx_stat_grfrg_hi;
2207 u32 rx_stat_grerb_lo;
2208 u32 rx_stat_grerb_hi;
2209 u32 rx_stat_grfre_lo;
2210 u32 rx_stat_grfre_hi;
2211 u32 rx_stat_gripj_lo;
2212 u32 rx_stat_gripj_hi;
2215 struct bmac2_stats {
2216 u32 tx_stat_gtpk_lo; /* gtpok */
2217 u32 tx_stat_gtpk_hi; /* gtpok */
2218 u32 tx_stat_gtxpf_lo; /* gtpf */
2219 u32 tx_stat_gtxpf_hi; /* gtpf */
2220 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */
2221 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */
2222 u32 tx_stat_gtfcs_lo;
2223 u32 tx_stat_gtfcs_hi;
2224 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */
2225 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */
2226 u32 tx_stat_gtmca_lo;
2227 u32 tx_stat_gtmca_hi;
2228 u32 tx_stat_gtbca_lo;
2229 u32 tx_stat_gtbca_hi;
2230 u32 tx_stat_gtovr_lo;
2231 u32 tx_stat_gtovr_hi;
2232 u32 tx_stat_gtfrg_lo;
2233 u32 tx_stat_gtfrg_hi;
2234 u32 tx_stat_gtpkt1_lo; /* gtpkt */
2235 u32 tx_stat_gtpkt1_hi; /* gtpkt */
2236 u32 tx_stat_gt64_lo;
2237 u32 tx_stat_gt64_hi;
2238 u32 tx_stat_gt127_lo;
2239 u32 tx_stat_gt127_hi;
2240 u32 tx_stat_gt255_lo;
2241 u32 tx_stat_gt255_hi;
2242 u32 tx_stat_gt511_lo;
2243 u32 tx_stat_gt511_hi;
2244 u32 tx_stat_gt1023_lo;
2245 u32 tx_stat_gt1023_hi;
2246 u32 tx_stat_gt1518_lo;
2247 u32 tx_stat_gt1518_hi;
2248 u32 tx_stat_gt2047_lo;
2249 u32 tx_stat_gt2047_hi;
2250 u32 tx_stat_gt4095_lo;
2251 u32 tx_stat_gt4095_hi;
2252 u32 tx_stat_gt9216_lo;
2253 u32 tx_stat_gt9216_hi;
2254 u32 tx_stat_gt16383_lo;
2255 u32 tx_stat_gt16383_hi;
2256 u32 tx_stat_gtmax_lo;
2257 u32 tx_stat_gtmax_hi;
2258 u32 tx_stat_gtufl_lo;
2259 u32 tx_stat_gtufl_hi;
2260 u32 tx_stat_gterr_lo;
2261 u32 tx_stat_gterr_hi;
2262 u32 tx_stat_gtbyt_lo;
2263 u32 tx_stat_gtbyt_hi;
2265 u32 rx_stat_gr64_lo;
2266 u32 rx_stat_gr64_hi;
2267 u32 rx_stat_gr127_lo;
2268 u32 rx_stat_gr127_hi;
2269 u32 rx_stat_gr255_lo;
2270 u32 rx_stat_gr255_hi;
2271 u32 rx_stat_gr511_lo;
2272 u32 rx_stat_gr511_hi;
2273 u32 rx_stat_gr1023_lo;
2274 u32 rx_stat_gr1023_hi;
2275 u32 rx_stat_gr1518_lo;
2276 u32 rx_stat_gr1518_hi;
2277 u32 rx_stat_gr2047_lo;
2278 u32 rx_stat_gr2047_hi;
2279 u32 rx_stat_gr4095_lo;
2280 u32 rx_stat_gr4095_hi;
2281 u32 rx_stat_gr9216_lo;
2282 u32 rx_stat_gr9216_hi;
2283 u32 rx_stat_gr16383_lo;
2284 u32 rx_stat_gr16383_hi;
2285 u32 rx_stat_grmax_lo;
2286 u32 rx_stat_grmax_hi;
2287 u32 rx_stat_grpkt_lo;
2288 u32 rx_stat_grpkt_hi;
2289 u32 rx_stat_grfcs_lo;
2290 u32 rx_stat_grfcs_hi;
2291 u32 rx_stat_gruca_lo;
2292 u32 rx_stat_gruca_hi;
2293 u32 rx_stat_grmca_lo;
2294 u32 rx_stat_grmca_hi;
2295 u32 rx_stat_grbca_lo;
2296 u32 rx_stat_grbca_hi;
2297 u32 rx_stat_grxpf_lo; /* grpf */
2298 u32 rx_stat_grxpf_hi; /* grpf */
2299 u32 rx_stat_grpp_lo;
2300 u32 rx_stat_grpp_hi;
2301 u32 rx_stat_grxuo_lo; /* gruo */
2302 u32 rx_stat_grxuo_hi; /* gruo */
2303 u32 rx_stat_grjbr_lo;
2304 u32 rx_stat_grjbr_hi;
2305 u32 rx_stat_grovr_lo;
2306 u32 rx_stat_grovr_hi;
2307 u32 rx_stat_grxcf_lo; /* grcf */
2308 u32 rx_stat_grxcf_hi; /* grcf */
2309 u32 rx_stat_grflr_lo;
2310 u32 rx_stat_grflr_hi;
2311 u32 rx_stat_grpok_lo;
2312 u32 rx_stat_grpok_hi;
2313 u32 rx_stat_grmeg_lo;
2314 u32 rx_stat_grmeg_hi;
2315 u32 rx_stat_grmeb_lo;
2316 u32 rx_stat_grmeb_hi;
2317 u32 rx_stat_grbyt_lo;
2318 u32 rx_stat_grbyt_hi;
2319 u32 rx_stat_grund_lo;
2320 u32 rx_stat_grund_hi;
2321 u32 rx_stat_grfrg_lo;
2322 u32 rx_stat_grfrg_hi;
2323 u32 rx_stat_grerb_lo; /* grerrbyt */
2324 u32 rx_stat_grerb_hi; /* grerrbyt */
2325 u32 rx_stat_grfre_lo; /* grfrerr */
2326 u32 rx_stat_grfre_hi; /* grfrerr */
2327 u32 rx_stat_gripj_lo;
2328 u32 rx_stat_gripj_hi;
2331 struct mstat_stats {
2333 /* OTE MSTAT on E3 has a bug where this register's contents are
2334 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2378 u32 tx_collisions_lo;
2379 u32 tx_collisions_hi;
2380 u32 tx_singlecollision_lo;
2381 u32 tx_singlecollision_hi;
2382 u32 tx_multiplecollisions_lo;
2383 u32 tx_multiplecollisions_hi;
2386 u32 tx_excessivecollisions_lo;
2387 u32 tx_excessivecollisions_hi;
2388 u32 tx_latecollisions_lo;
2389 u32 tx_latecollisions_hi;
2448 u32 rx_alignmenterrors_lo;
2449 u32 rx_alignmenterrors_hi;
2450 u32 rx_falsecarrier_lo;
2451 u32 rx_falsecarrier_hi;
2452 u32 rx_llfcmsgcnt_lo;
2453 u32 rx_llfcmsgcnt_hi;
2458 struct emac_stats emac_stats;
2459 struct bmac1_stats bmac1_stats;
2460 struct bmac2_stats bmac2_stats;
2461 struct mstat_stats mstat_stats;
2467 u32 rx_stat_ifhcinbadoctets_hi;
2468 u32 rx_stat_ifhcinbadoctets_lo;
2470 /* out_bad_octets */
2471 u32 tx_stat_ifhcoutbadoctets_hi;
2472 u32 tx_stat_ifhcoutbadoctets_lo;
2474 /* crc_receive_errors */
2475 u32 rx_stat_dot3statsfcserrors_hi;
2476 u32 rx_stat_dot3statsfcserrors_lo;
2477 /* alignment_errors */
2478 u32 rx_stat_dot3statsalignmenterrors_hi;
2479 u32 rx_stat_dot3statsalignmenterrors_lo;
2480 /* carrier_sense_errors */
2481 u32 rx_stat_dot3statscarriersenseerrors_hi;
2482 u32 rx_stat_dot3statscarriersenseerrors_lo;
2483 /* false_carrier_detections */
2484 u32 rx_stat_falsecarriererrors_hi;
2485 u32 rx_stat_falsecarriererrors_lo;
2487 /* runt_packets_received */
2488 u32 rx_stat_etherstatsundersizepkts_hi;
2489 u32 rx_stat_etherstatsundersizepkts_lo;
2490 /* jabber_packets_received */
2491 u32 rx_stat_dot3statsframestoolong_hi;
2492 u32 rx_stat_dot3statsframestoolong_lo;
2494 /* error_runt_packets_received */
2495 u32 rx_stat_etherstatsfragments_hi;
2496 u32 rx_stat_etherstatsfragments_lo;
2497 /* error_jabber_packets_received */
2498 u32 rx_stat_etherstatsjabbers_hi;
2499 u32 rx_stat_etherstatsjabbers_lo;
2501 /* control_frames_received */
2502 u32 rx_stat_maccontrolframesreceived_hi;
2503 u32 rx_stat_maccontrolframesreceived_lo;
2504 u32 rx_stat_mac_xpf_hi;
2505 u32 rx_stat_mac_xpf_lo;
2506 u32 rx_stat_mac_xcf_hi;
2507 u32 rx_stat_mac_xcf_lo;
2509 /* xoff_state_entered */
2510 u32 rx_stat_xoffstateentered_hi;
2511 u32 rx_stat_xoffstateentered_lo;
2512 /* pause_xon_frames_received */
2513 u32 rx_stat_xonpauseframesreceived_hi;
2514 u32 rx_stat_xonpauseframesreceived_lo;
2515 /* pause_xoff_frames_received */
2516 u32 rx_stat_xoffpauseframesreceived_hi;
2517 u32 rx_stat_xoffpauseframesreceived_lo;
2518 /* pause_xon_frames_transmitted */
2519 u32 tx_stat_outxonsent_hi;
2520 u32 tx_stat_outxonsent_lo;
2521 /* pause_xoff_frames_transmitted */
2522 u32 tx_stat_outxoffsent_hi;
2523 u32 tx_stat_outxoffsent_lo;
2524 /* flow_control_done */
2525 u32 tx_stat_flowcontroldone_hi;
2526 u32 tx_stat_flowcontroldone_lo;
2528 /* ether_stats_collisions */
2529 u32 tx_stat_etherstatscollisions_hi;
2530 u32 tx_stat_etherstatscollisions_lo;
2531 /* single_collision_transmit_frames */
2532 u32 tx_stat_dot3statssinglecollisionframes_hi;
2533 u32 tx_stat_dot3statssinglecollisionframes_lo;
2534 /* multiple_collision_transmit_frames */
2535 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
2536 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
2537 /* deferred_transmissions */
2538 u32 tx_stat_dot3statsdeferredtransmissions_hi;
2539 u32 tx_stat_dot3statsdeferredtransmissions_lo;
2540 /* excessive_collision_frames */
2541 u32 tx_stat_dot3statsexcessivecollisions_hi;
2542 u32 tx_stat_dot3statsexcessivecollisions_lo;
2543 /* late_collision_frames */
2544 u32 tx_stat_dot3statslatecollisions_hi;
2545 u32 tx_stat_dot3statslatecollisions_lo;
2547 /* frames_transmitted_64_bytes */
2548 u32 tx_stat_etherstatspkts64octets_hi;
2549 u32 tx_stat_etherstatspkts64octets_lo;
2550 /* frames_transmitted_65_127_bytes */
2551 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
2552 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
2553 /* frames_transmitted_128_255_bytes */
2554 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
2555 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
2556 /* frames_transmitted_256_511_bytes */
2557 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
2558 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
2559 /* frames_transmitted_512_1023_bytes */
2560 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
2561 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
2562 /* frames_transmitted_1024_1522_bytes */
2563 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
2564 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
2565 /* frames_transmitted_1523_9022_bytes */
2566 u32 tx_stat_etherstatspktsover1522octets_hi;
2567 u32 tx_stat_etherstatspktsover1522octets_lo;
2568 u32 tx_stat_mac_2047_hi;
2569 u32 tx_stat_mac_2047_lo;
2570 u32 tx_stat_mac_4095_hi;
2571 u32 tx_stat_mac_4095_lo;
2572 u32 tx_stat_mac_9216_hi;
2573 u32 tx_stat_mac_9216_lo;
2574 u32 tx_stat_mac_16383_hi;
2575 u32 tx_stat_mac_16383_lo;
2577 /* internal_mac_transmit_errors */
2578 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
2579 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
2581 /* if_out_discards */
2582 u32 tx_stat_mac_ufl_hi;
2583 u32 tx_stat_mac_ufl_lo;
2587 #define MAC_STX_IDX_MAX 2
2589 struct host_port_stats {
2590 u32 host_port_stats_counter;
2592 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2597 u32 not_used; /* obsolete */
2598 u32 pfc_frames_tx_hi;
2599 u32 pfc_frames_tx_lo;
2600 u32 pfc_frames_rx_hi;
2601 u32 pfc_frames_rx_lo;
2605 struct host_func_stats {
2606 u32 host_func_stats_start;
2608 u32 total_bytes_received_hi;
2609 u32 total_bytes_received_lo;
2611 u32 total_bytes_transmitted_hi;
2612 u32 total_bytes_transmitted_lo;
2614 u32 total_unicast_packets_received_hi;
2615 u32 total_unicast_packets_received_lo;
2617 u32 total_multicast_packets_received_hi;
2618 u32 total_multicast_packets_received_lo;
2620 u32 total_broadcast_packets_received_hi;
2621 u32 total_broadcast_packets_received_lo;
2623 u32 total_unicast_packets_transmitted_hi;
2624 u32 total_unicast_packets_transmitted_lo;
2626 u32 total_multicast_packets_transmitted_hi;
2627 u32 total_multicast_packets_transmitted_lo;
2629 u32 total_broadcast_packets_transmitted_hi;
2630 u32 total_broadcast_packets_transmitted_lo;
2632 u32 valid_bytes_received_hi;
2633 u32 valid_bytes_received_lo;
2635 u32 host_func_stats_end;
2638 /* VIC definitions */
2639 #define VICSTATST_UIF_INDEX 2
2641 /* current drv_info version */
2642 #define DRV_INFO_CUR_VER 1
2644 /* drv_info op codes supported */
2645 enum drv_info_opcode {
2651 #define ETH_STAT_INFO_VERSION_LEN 12
2652 /* Per PCI Function Ethernet Statistics required from the driver */
2653 struct eth_stats_info {
2654 /* Function's Driver Version. padded to 12 */
2655 u8 version[ETH_STAT_INFO_VERSION_LEN];
2656 /* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */
2658 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */
2659 u8 mac_add2[8]; /* Additional Programmed MAC Addr 2. */
2660 u32 mtu_size; /* MTU Size. Note : Negotiated MTU */
2661 u32 feature_flags; /* Feature_Flags. */
2662 #define FEATURE_ETH_CHKSUM_OFFLOAD_MASK 0x01
2663 #define FEATURE_ETH_LSO_MASK 0x02
2664 #define FEATURE_ETH_BOOTMODE_MASK 0x1C
2665 #define FEATURE_ETH_BOOTMODE_SHIFT 2
2666 #define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2)
2667 #define FEATURE_ETH_BOOTMODE_PXE (0x1 << 2)
2668 #define FEATURE_ETH_BOOTMODE_ISCSI (0x2 << 2)
2669 #define FEATURE_ETH_BOOTMODE_FCOE (0x3 << 2)
2670 #define FEATURE_ETH_TOE_MASK 0x20
2671 u32 lso_max_size; /* LSO MaxOffloadSize. */
2672 u32 lso_min_seg_cnt; /* LSO MinSegmentCount. */
2673 /* Num Offloaded Connections TCP_IPv4. */
2675 /* Num Offloaded Connections TCP_IPv6. */
2677 u32 promiscuous_mode; /* Promiscuous Mode. non-zero true */
2678 u32 txq_size; /* TX Descriptors Queue Size */
2679 u32 rxq_size; /* RX Descriptors Queue Size */
2680 /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
2682 /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
2684 /* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/
2686 /* Number of NetQueue/VMQ Config'd. */
2688 u32 vf_cnt; /* Num VF assigned to this PF. */
2691 /* Per PCI Function FCOE Statistics required from the driver */
2692 struct fcoe_stats_info {
2693 u8 version[12]; /* Function's Driver Version. */
2694 u8 mac_local[8]; /* Locally Admin Addr. */
2695 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */
2696 u8 mac_add2[8]; /* Additional Programmed MAC Addr 2. */
2697 /* QoS Priority (per 802.1p). 0-7255 */
2699 u32 txq_size; /* FCoE TX Descriptors Queue Size. */
2700 u32 rxq_size; /* FCoE RX Descriptors Queue Size. */
2701 /* FCoE TX Descriptor Queue Avg Depth. */
2703 /* FCoE RX Descriptors Queue Avg Depth. */
2705 u32 rx_frames_lo; /* FCoE RX Frames received. */
2706 u32 rx_frames_hi; /* FCoE RX Frames received. */
2707 u32 rx_bytes_lo; /* FCoE RX Bytes received. */
2708 u32 rx_bytes_hi; /* FCoE RX Bytes received. */
2709 u32 tx_frames_lo; /* FCoE TX Frames sent. */
2710 u32 tx_frames_hi; /* FCoE TX Frames sent. */
2711 u32 tx_bytes_lo; /* FCoE TX Bytes sent. */
2712 u32 tx_bytes_hi; /* FCoE TX Bytes sent. */
2715 /* Per PCI Function iSCSI Statistics required from the driver*/
2716 struct iscsi_stats_info {
2717 u8 version[12]; /* Function's Driver Version. */
2718 u8 mac_local[8]; /* Locally Admin iSCSI MAC Addr. */
2719 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */
2720 /* QoS Priority (per 802.1p). 0-7255 */
2722 u8 initiator_name[64]; /* iSCSI Boot Initiator Node name. */
2723 u8 ww_port_name[64]; /* iSCSI World wide port name */
2724 u8 boot_target_name[64];/* iSCSI Boot Target Name. */
2725 u8 boot_target_ip[16]; /* iSCSI Boot Target IP. */
2726 u32 boot_target_portal; /* iSCSI Boot Target Portal. */
2727 u8 boot_init_ip[16]; /* iSCSI Boot Initiator IP Address. */
2728 u32 max_frame_size; /* Max Frame Size. bytes */
2729 u32 txq_size; /* PDU TX Descriptors Queue Size. */
2730 u32 rxq_size; /* PDU RX Descriptors Queue Size. */
2731 u32 txq_avg_depth; /* PDU TX Descriptor Queue Avg Depth. */
2732 u32 rxq_avg_depth; /* PDU RX Descriptors Queue Avg Depth. */
2733 u32 rx_pdus_lo; /* iSCSI PDUs received. */
2734 u32 rx_pdus_hi; /* iSCSI PDUs received. */
2735 u32 rx_bytes_lo; /* iSCSI RX Bytes received. */
2736 u32 rx_bytes_hi; /* iSCSI RX Bytes received. */
2737 u32 tx_pdus_lo; /* iSCSI PDUs sent. */
2738 u32 tx_pdus_hi; /* iSCSI PDUs sent. */
2739 u32 tx_bytes_lo; /* iSCSI PDU TX Bytes sent. */
2740 u32 tx_bytes_hi; /* iSCSI PDU TX Bytes sent. */
2741 u32 pcp_prior_map_tbl; /* C-PCP to S-PCP Priority MapTable.
2742 * 9 nibbles, the position of each nibble
2743 * represents the C-PCP value, the value
2744 * of the nibble = S-PCP value.
2748 union drv_info_to_mcp {
2749 struct eth_stats_info ether_stat;
2750 struct fcoe_stats_info fcoe_stat;
2751 struct iscsi_stats_info iscsi_stat;
2754 /* stats collected for afex.
2755 * NOTE: structure is exactly as expected to be received by the switch.
2756 * order must remain exactly as is unless protocol changes !
2759 u32 tx_unicast_frames_hi;
2760 u32 tx_unicast_frames_lo;
2761 u32 tx_unicast_bytes_hi;
2762 u32 tx_unicast_bytes_lo;
2763 u32 tx_multicast_frames_hi;
2764 u32 tx_multicast_frames_lo;
2765 u32 tx_multicast_bytes_hi;
2766 u32 tx_multicast_bytes_lo;
2767 u32 tx_broadcast_frames_hi;
2768 u32 tx_broadcast_frames_lo;
2769 u32 tx_broadcast_bytes_hi;
2770 u32 tx_broadcast_bytes_lo;
2771 u32 tx_frames_discarded_hi;
2772 u32 tx_frames_discarded_lo;
2773 u32 tx_frames_dropped_hi;
2774 u32 tx_frames_dropped_lo;
2776 u32 rx_unicast_frames_hi;
2777 u32 rx_unicast_frames_lo;
2778 u32 rx_unicast_bytes_hi;
2779 u32 rx_unicast_bytes_lo;
2780 u32 rx_multicast_frames_hi;
2781 u32 rx_multicast_frames_lo;
2782 u32 rx_multicast_bytes_hi;
2783 u32 rx_multicast_bytes_lo;
2784 u32 rx_broadcast_frames_hi;
2785 u32 rx_broadcast_frames_lo;
2786 u32 rx_broadcast_bytes_hi;
2787 u32 rx_broadcast_bytes_lo;
2788 u32 rx_frames_discarded_hi;
2789 u32 rx_frames_discarded_lo;
2790 u32 rx_frames_dropped_hi;
2791 u32 rx_frames_dropped_lo;
2794 #define BCM_5710_FW_MAJOR_VERSION 7
2795 #define BCM_5710_FW_MINOR_VERSION 2
2796 #define BCM_5710_FW_REVISION_VERSION 51
2797 #define BCM_5710_FW_ENGINEERING_VERSION 0
2798 #define BCM_5710_FW_COMPILE_FLAGS 1
2804 struct atten_sp_status_block {
2806 __le32 attn_bits_ack;
2809 __le16 attn_bits_index;
2815 * The eth aggregative context of Cstorm
2817 struct cstorm_eth_ag_context {
2818 u32 __reserved0[10];
2823 * dmae command structure
2825 struct dmae_command {
2827 #define DMAE_COMMAND_SRC (0x1<<0)
2828 #define DMAE_COMMAND_SRC_SHIFT 0
2829 #define DMAE_COMMAND_DST (0x3<<1)
2830 #define DMAE_COMMAND_DST_SHIFT 1
2831 #define DMAE_COMMAND_C_DST (0x1<<3)
2832 #define DMAE_COMMAND_C_DST_SHIFT 3
2833 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2834 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2835 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2836 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2837 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2838 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2839 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2840 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2841 #define DMAE_COMMAND_PORT (0x1<<11)
2842 #define DMAE_COMMAND_PORT_SHIFT 11
2843 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2844 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2845 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2846 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2847 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2848 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2849 #define DMAE_COMMAND_E1HVN (0x3<<15)
2850 #define DMAE_COMMAND_E1HVN_SHIFT 15
2851 #define DMAE_COMMAND_DST_VN (0x3<<17)
2852 #define DMAE_COMMAND_DST_VN_SHIFT 17
2853 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2854 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2855 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2856 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2857 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2858 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2863 #if defined(__BIG_ENDIAN)
2865 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2866 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2867 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2868 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2869 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2870 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2871 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2872 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2873 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2874 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2875 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2876 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2878 #elif defined(__LITTLE_ENDIAN)
2881 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2882 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2883 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2884 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2885 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2886 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2887 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2888 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2889 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2890 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2891 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2892 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2899 #if defined(__BIG_ENDIAN)
2902 #elif defined(__LITTLE_ENDIAN)
2906 #if defined(__BIG_ENDIAN)
2909 #elif defined(__LITTLE_ENDIAN)
2913 #if defined(__BIG_ENDIAN)
2916 #elif defined(__LITTLE_ENDIAN)
2924 * common data for all protocols
2926 struct doorbell_hdr {
2928 #define DOORBELL_HDR_RX (0x1<<0)
2929 #define DOORBELL_HDR_RX_SHIFT 0
2930 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
2931 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
2932 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
2933 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
2934 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
2935 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
2941 struct eth_tx_doorbell {
2942 #if defined(__BIG_ENDIAN)
2945 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2946 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2947 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2948 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2949 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2950 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2951 struct doorbell_hdr hdr;
2952 #elif defined(__LITTLE_ENDIAN)
2953 struct doorbell_hdr hdr;
2955 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2956 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2957 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2958 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2959 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2960 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2967 * 3 lines. status block
2969 struct hc_status_block_e1x {
2970 __le16 index_values[HC_SB_MAX_INDICES_E1X];
2971 __le16 running_index[HC_SB_MAX_SM];
2978 struct host_hc_status_block_e1x {
2979 struct hc_status_block_e1x sb;
2984 * 3 lines. status block
2986 struct hc_status_block_e2 {
2987 __le16 index_values[HC_SB_MAX_INDICES_E2];
2988 __le16 running_index[HC_SB_MAX_SM];
2989 __le32 reserved[11];
2995 struct host_hc_status_block_e2 {
2996 struct hc_status_block_e2 sb;
3001 * 5 lines. slow-path status block
3003 struct hc_sp_status_block {
3004 __le16 index_values[HC_SP_SB_MAX_INDICES];
3005 __le16 running_index;
3013 struct host_sp_status_block {
3014 struct atten_sp_status_block atten_status_block;
3015 struct hc_sp_status_block sp_sb;
3020 * IGU driver acknowledgment register
3022 struct igu_ack_register {
3023 #if defined(__BIG_ENDIAN)
3024 u16 sb_id_and_flags;
3025 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3026 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3027 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3028 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3029 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3030 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3031 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3032 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3033 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3034 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3035 u16 status_block_index;
3036 #elif defined(__LITTLE_ENDIAN)
3037 u16 status_block_index;
3038 u16 sb_id_and_flags;
3039 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3040 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3041 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3042 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3043 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3044 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3045 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3046 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3047 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3048 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3054 * IGU driver acknowledgement register
3056 struct igu_backward_compatible {
3057 u32 sb_id_and_flags;
3058 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3059 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3060 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3061 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3062 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3063 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3064 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3065 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3066 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3067 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3068 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3069 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3075 * IGU driver acknowledgement register
3077 struct igu_regular {
3078 u32 sb_id_and_flags;
3079 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3080 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3081 #define IGU_REGULAR_RESERVED0 (0x1<<20)
3082 #define IGU_REGULAR_RESERVED0_SHIFT 20
3083 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3084 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3085 #define IGU_REGULAR_BUPDATE (0x1<<24)
3086 #define IGU_REGULAR_BUPDATE_SHIFT 24
3087 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
3088 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
3089 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
3090 #define IGU_REGULAR_RESERVED_1_SHIFT 27
3091 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3092 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3093 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3094 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3095 #define IGU_REGULAR_BCLEANUP (0x1<<31)
3096 #define IGU_REGULAR_BCLEANUP_SHIFT 31
3101 * IGU driver acknowledgement register
3103 union igu_consprod_reg {
3104 struct igu_regular regular;
3105 struct igu_backward_compatible backward_compatible;
3110 * Igu control commands
3113 IGU_CTRL_CMD_TYPE_RD,
3114 IGU_CTRL_CMD_TYPE_WR,
3120 * Control register for the IGU command register
3122 struct igu_ctrl_reg {
3124 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3125 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3126 #define IGU_CTRL_REG_FID (0x7F<<12)
3127 #define IGU_CTRL_REG_FID_SHIFT 12
3128 #define IGU_CTRL_REG_RESERVED (0x1<<19)
3129 #define IGU_CTRL_REG_RESERVED_SHIFT 19
3130 #define IGU_CTRL_REG_TYPE (0x1<<20)
3131 #define IGU_CTRL_REG_TYPE_SHIFT 20
3132 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3133 #define IGU_CTRL_REG_UNUSED_SHIFT 21
3138 * Igu interrupt command
3152 enum igu_seg_access {
3153 IGU_SEG_ACCESS_NORM,
3155 IGU_SEG_ACCESS_ATTN,
3161 * Parser parsing flags field
3163 struct parsing_flags {
3165 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3166 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3167 #define PARSING_FLAGS_VLAN (0x1<<1)
3168 #define PARSING_FLAGS_VLAN_SHIFT 1
3169 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3170 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3171 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3172 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3173 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3174 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3175 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3176 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3177 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3178 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3179 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3180 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3181 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3182 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3183 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3184 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3185 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3186 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3187 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3188 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3189 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
3190 #define PARSING_FLAGS_RESERVED0_SHIFT 14
3195 * Parsing flags for TCP ACK type
3197 enum prs_flags_ack_type {
3198 PRS_FLAG_PUREACK_PIGGY,
3199 PRS_FLAG_PUREACK_PURE,
3200 MAX_PRS_FLAGS_ACK_TYPE
3205 * Parsing flags for Ethernet address type
3207 enum prs_flags_eth_addr_type {
3208 PRS_FLAG_ETHTYPE_NON_UNICAST,
3209 PRS_FLAG_ETHTYPE_UNICAST,
3210 MAX_PRS_FLAGS_ETH_ADDR_TYPE
3215 * Parsing flags for over-ethernet protocol
3217 enum prs_flags_over_eth {
3218 PRS_FLAG_OVERETH_UNKNOWN,
3219 PRS_FLAG_OVERETH_IPV4,
3220 PRS_FLAG_OVERETH_IPV6,
3221 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3222 MAX_PRS_FLAGS_OVER_ETH
3227 * Parsing flags for over-IP protocol
3229 enum prs_flags_over_ip {
3230 PRS_FLAG_OVERIP_UNKNOWN,
3231 PRS_FLAG_OVERIP_TCP,
3232 PRS_FLAG_OVERIP_UDP,
3233 MAX_PRS_FLAGS_OVER_IP
3238 * SDM operation gen command (generate aggregative interrupt)
3242 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3243 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3244 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3245 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3246 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3247 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3248 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3249 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3250 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3251 #define SDM_OP_GEN_RESERVED_SHIFT 17
3256 * Timers connection context
3258 struct timers_block_context {
3263 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3264 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3265 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3266 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3267 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3268 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3273 * The eth aggregative context of Tstorm
3275 struct tstorm_eth_ag_context {
3276 u32 __reserved0[14];
3281 * The eth aggregative context of Ustorm
3283 struct ustorm_eth_ag_context {
3285 #if defined(__BIG_ENDIAN)
3289 #elif defined(__LITTLE_ENDIAN)
3299 * The eth aggregative context of Xstorm
3301 struct xstorm_eth_ag_context {
3303 #if defined(__BIG_ENDIAN)
3307 #elif defined(__LITTLE_ENDIAN)
3317 * doorbell message sent to the chip
3320 #if defined(__BIG_ENDIAN)
3323 struct doorbell_hdr header;
3324 #elif defined(__LITTLE_ENDIAN)
3325 struct doorbell_hdr header;
3333 * doorbell message sent to the chip
3335 struct doorbell_set_prod {
3336 #if defined(__BIG_ENDIAN)
3339 struct doorbell_hdr header;
3340 #elif defined(__LITTLE_ENDIAN)
3341 struct doorbell_hdr header;
3355 * Classify rule opcodes in E2/E3
3357 enum classify_rule {
3358 CLASSIFY_RULE_OPCODE_MAC,
3359 CLASSIFY_RULE_OPCODE_VLAN,
3360 CLASSIFY_RULE_OPCODE_PAIR,
3366 * Classify rule types in E2/E3
3368 enum classify_rule_action_type {
3369 CLASSIFY_RULE_REMOVE,
3371 MAX_CLASSIFY_RULE_ACTION_TYPE
3376 * client init ramrod data
3378 struct client_init_general_data {
3380 u8 statistics_counter_id;
3381 u8 statistics_en_flg;
3386 u8 statistics_zero_flg;
3395 * client init rx data
3397 struct client_init_rx_data {
3399 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3400 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3401 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3402 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3403 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3404 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3405 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3406 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3407 u8 vmqueue_mode_en_flg;
3408 u8 extra_data_over_sgl_en_flg;
3409 u8 cache_line_alignment_log_size;
3410 u8 enable_dynamic_hc;
3411 u8 max_sges_for_packet;
3413 u8 drop_ip_cs_err_flg;
3414 u8 drop_tcp_cs_err_flg;
3416 u8 drop_udp_cs_err_flg;
3417 u8 inner_vlan_removal_enable_flg;
3418 u8 outer_vlan_removal_enable_flg;
3420 u8 rx_sb_index_number;
3421 u8 dont_verify_rings_pause_thr_flg;
3423 u8 silent_vlan_removal_flg;
3424 __le16 max_bytes_on_bd;
3425 __le16 sge_buff_size;
3426 u8 approx_mcast_engine_id;
3428 struct regpair bd_page_base;
3429 struct regpair sge_page_base;
3430 struct regpair cqe_page_base;
3433 __le16 max_agg_size;
3435 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3436 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3437 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3438 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3439 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3440 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3441 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3442 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3443 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3444 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3445 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3446 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3447 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3448 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3449 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3450 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3451 __le16 cqe_pause_thr_low;
3452 __le16 cqe_pause_thr_high;
3453 __le16 bd_pause_thr_low;
3454 __le16 bd_pause_thr_high;
3455 __le16 sge_pause_thr_low;
3456 __le16 sge_pause_thr_high;
3458 __le16 silent_vlan_value;
3459 __le16 silent_vlan_mask;
3460 __le32 reserved6[2];
3464 * client init tx data
3466 struct client_init_tx_data {
3467 u8 enforce_security_flg;
3468 u8 tx_status_block_id;
3469 u8 tx_sb_index_number;
3470 u8 tss_leading_client_id;
3471 u8 tx_switching_flg;
3472 u8 anti_spoofing_flg;
3473 __le16 default_vlan;
3474 struct regpair tx_bd_page_base;
3476 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3477 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3478 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3479 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3480 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3481 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3482 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3483 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3484 #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)
3485 #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4
3486 u8 default_vlan_flg;
3487 u8 force_default_pri_flg;
3492 * client init ramrod data
3494 struct client_init_ramrod_data {
3495 struct client_init_general_data general;
3496 struct client_init_rx_data rx;
3497 struct client_init_tx_data tx;
3502 * client update ramrod data
3504 struct client_update_ramrod_data {
3507 u8 inner_vlan_removal_enable_flg;
3508 u8 inner_vlan_removal_change_flg;
3509 u8 outer_vlan_removal_enable_flg;
3510 u8 outer_vlan_removal_change_flg;
3511 u8 anti_spoofing_enable_flg;
3512 u8 anti_spoofing_change_flg;
3514 u8 activate_change_flg;
3515 __le16 default_vlan;
3516 u8 default_vlan_enable_flg;
3517 u8 default_vlan_change_flg;
3518 __le16 silent_vlan_value;
3519 __le16 silent_vlan_mask;
3520 u8 silent_vlan_removal_flg;
3521 u8 silent_vlan_change_flg;
3527 * The eth storm context of Cstorm
3529 struct cstorm_eth_st_context {
3534 struct double_regpair {
3543 * Ethernet address typesm used in ethernet tx BDs
3545 enum eth_addr_type {
3557 struct eth_classify_cmd_header {
3558 u8 cmd_general_data;
3559 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3560 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3561 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3562 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3563 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3564 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3565 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3566 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3567 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3568 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3576 * header for eth classification config ramrod
3578 struct eth_classify_header {
3587 * Command for adding/removing a MAC classification rule
3589 struct eth_classify_mac_cmd {
3590 struct eth_classify_cmd_header header;
3600 * Command for adding/removing a MAC-VLAN pair classification rule
3602 struct eth_classify_pair_cmd {
3603 struct eth_classify_cmd_header header;
3613 * Command for adding/removing a VLAN classification rule
3615 struct eth_classify_vlan_cmd {
3616 struct eth_classify_cmd_header header;
3624 * union for eth classification rule
3626 union eth_classify_rule_cmd {
3627 struct eth_classify_mac_cmd mac;
3628 struct eth_classify_vlan_cmd vlan;
3629 struct eth_classify_pair_cmd pair;
3633 * parameters for eth classification configuration ramrod
3635 struct eth_classify_rules_ramrod_data {
3636 struct eth_classify_header header;
3637 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3642 * The data contain client ID need to the ramrod
3644 struct eth_common_ramrod_data {
3651 * The eth storm context of Ustorm
3653 struct ustorm_eth_st_context {
3658 * The eth storm context of Tstorm
3660 struct tstorm_eth_st_context {
3661 u32 __reserved0[28];
3665 * The eth storm context of Xstorm
3667 struct xstorm_eth_st_context {
3672 * Ethernet connection context
3674 struct eth_context {
3675 struct ustorm_eth_st_context ustorm_st_context;
3676 struct tstorm_eth_st_context tstorm_st_context;
3677 struct xstorm_eth_ag_context xstorm_ag_context;
3678 struct tstorm_eth_ag_context tstorm_ag_context;
3679 struct cstorm_eth_ag_context cstorm_ag_context;
3680 struct ustorm_eth_ag_context ustorm_ag_context;
3681 struct timers_block_context timers_context;
3682 struct xstorm_eth_st_context xstorm_st_context;
3683 struct cstorm_eth_st_context cstorm_st_context;
3688 * union for sgl and raw data.
3690 union eth_sgl_or_raw_data {
3696 * eth FP end aggregation CQE parameters struct
3698 struct eth_end_agg_rx_cqe {
3699 u8 type_error_flags;
3700 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3701 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3702 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3703 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3704 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3705 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3709 __le32 timestamp_delta;
3710 __le16 num_of_coalesced_segs;
3715 union eth_sgl_or_raw_data sgl_or_raw_data;
3716 __le32 reserved5[8];
3721 * regular eth FP CQE parameters struct
3723 struct eth_fast_path_rx_cqe {
3724 u8 type_error_flags;
3725 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3726 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3727 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3728 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3729 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3730 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3731 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3732 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3733 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3734 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3735 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3736 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3738 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3739 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3740 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3741 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3742 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3743 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3744 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3745 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3746 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3747 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3748 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3749 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3751 u8 placement_offset;
3752 __le32 rss_hash_result;
3754 __le16 pkt_len_or_gro_seg_len;
3756 struct parsing_flags pars_flags;
3757 union eth_sgl_or_raw_data sgl_or_raw_data;
3758 __le32 reserved1[8];
3763 * Command for setting classification flags for a client
3765 struct eth_filter_rules_cmd {
3766 u8 cmd_general_data;
3767 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3768 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3769 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3770 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3771 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3772 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3777 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3778 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3779 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3780 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3781 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3782 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3783 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3784 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3785 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3786 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3787 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3788 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3789 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3790 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3791 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3792 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3794 struct regpair reserved4;
3799 * parameters for eth classification filters ramrod
3801 struct eth_filter_rules_ramrod_data {
3802 struct eth_classify_header header;
3803 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3808 * parameters for eth classification configuration ramrod
3810 struct eth_general_rules_ramrod_data {
3811 struct eth_classify_header header;
3812 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3817 * The data for Halt ramrod
3819 struct eth_halt_ramrod_data {
3826 * Command for setting multicast classification for a client
3828 struct eth_multicast_rules_cmd {
3829 u8 cmd_general_data;
3830 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3831 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3832 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3833 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3834 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3835 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3836 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3837 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3842 struct regpair reserved3;
3847 * parameters for multicast classification ramrod
3849 struct eth_multicast_rules_ramrod_data {
3850 struct eth_classify_header header;
3851 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
3856 * Place holder for ramrods protocol specific data
3858 struct ramrod_data {
3864 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
3866 union eth_ramrod_data {
3867 struct ramrod_data general;
3872 * RSS toeplitz hash type, as reported in CQE
3874 enum eth_rss_hash_type {
3881 E1HOV_PRI_HASH_TYPE,
3883 MAX_ETH_RSS_HASH_TYPE
3891 ETH_RSS_MODE_DISABLED,
3892 ETH_RSS_MODE_REGULAR,
3893 ETH_RSS_MODE_VLAN_PRI,
3894 ETH_RSS_MODE_E1HOV_PRI,
3895 ETH_RSS_MODE_IP_DSCP,
3901 * parameters for RSS update ramrod (E2)
3903 struct eth_rss_update_ramrod_data {
3906 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
3907 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
3908 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
3909 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
3910 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
3911 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
3912 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
3913 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
3914 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
3915 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
3916 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
3917 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
3918 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6)
3919 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6
3920 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7)
3921 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7
3925 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
3926 __le32 rss_key[T_ETH_RSS_KEY];
3933 * The eth Rx Buffer Descriptor
3942 * Eth Rx Cqe structure- general structure for ramrods
3944 struct common_ramrod_eth_rx_cqe {
3946 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
3947 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
3948 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
3949 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
3950 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
3951 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
3954 __le32 conn_and_cmd_data;
3955 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
3956 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
3957 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
3958 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
3959 struct ramrod_data protocol_data;
3961 __le32 reserved2[11];
3965 * Rx Last CQE in page (in ETH)
3967 struct eth_rx_cqe_next_page {
3970 __le32 reserved[14];
3974 * union for all eth rx cqe types (fix their sizes)
3977 struct eth_fast_path_rx_cqe fast_path_cqe;
3978 struct common_ramrod_eth_rx_cqe ramrod_cqe;
3979 struct eth_rx_cqe_next_page next_page_cqe;
3980 struct eth_end_agg_rx_cqe end_agg_cqe;
3985 * Values for RX ETH CQE type field
3987 enum eth_rx_cqe_type {
3988 RX_ETH_CQE_TYPE_ETH_FASTPATH,
3989 RX_ETH_CQE_TYPE_ETH_RAMROD,
3990 RX_ETH_CQE_TYPE_ETH_START_AGG,
3991 RX_ETH_CQE_TYPE_ETH_STOP_AGG,
3997 * Type of SGL/Raw field in ETH RX fast path CQE
3999 enum eth_rx_fp_sel {
4007 * The eth Rx SGE Descriptor
4016 * common data for all protocols
4019 __le32 conn_and_cmd_data;
4020 #define SPE_HDR_CID (0xFFFFFF<<0)
4021 #define SPE_HDR_CID_SHIFT 0
4022 #define SPE_HDR_CMD_ID (0xFF<<24)
4023 #define SPE_HDR_CMD_ID_SHIFT 24
4025 #define SPE_HDR_CONN_TYPE (0xFF<<0)
4026 #define SPE_HDR_CONN_TYPE_SHIFT 0
4027 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
4028 #define SPE_HDR_FUNCTION_ID_SHIFT 8
4033 * specific data for ethernet slow path element
4035 union eth_specific_data {
4036 u8 protocol_data[8];
4037 struct regpair client_update_ramrod_data;
4038 struct regpair client_init_ramrod_init_data;
4039 struct eth_halt_ramrod_data halt_ramrod_data;
4040 struct regpair update_data_addr;
4041 struct eth_common_ramrod_data common_ramrod_data;
4042 struct regpair classify_cfg_addr;
4043 struct regpair filter_cfg_addr;
4044 struct regpair mcast_cfg_addr;
4048 * Ethernet slow path element
4052 union eth_specific_data data;
4057 * Ethernet command ID for slow path elements
4059 enum eth_spqe_cmd_id {
4060 RAMROD_CMD_ID_ETH_UNUSED,
4061 RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4062 RAMROD_CMD_ID_ETH_HALT,
4063 RAMROD_CMD_ID_ETH_FORWARD_SETUP,
4064 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
4065 RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4066 RAMROD_CMD_ID_ETH_EMPTY,
4067 RAMROD_CMD_ID_ETH_TERMINATE,
4068 RAMROD_CMD_ID_ETH_TPA_UPDATE,
4069 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
4070 RAMROD_CMD_ID_ETH_FILTER_RULES,
4071 RAMROD_CMD_ID_ETH_MULTICAST_RULES,
4072 RAMROD_CMD_ID_ETH_RSS_UPDATE,
4073 RAMROD_CMD_ID_ETH_SET_MAC,
4079 * eth tpa update command
4081 enum eth_tpa_update_command {
4082 TPA_UPDATE_NONE_COMMAND,
4083 TPA_UPDATE_ENABLE_COMMAND,
4084 TPA_UPDATE_DISABLE_COMMAND,
4085 MAX_ETH_TPA_UPDATE_COMMAND
4090 * Tx regular BD structure
4095 __le16 total_pkt_bytes;
4102 * structure for easy accessibility to assembler
4104 struct eth_tx_bd_flags {
4106 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4107 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4108 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4109 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4110 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4111 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4112 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4113 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4114 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4115 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4116 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4117 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4118 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4119 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4123 * The eth Tx Buffer Descriptor
4125 struct eth_tx_start_bd {
4130 __le16 vlan_or_ethertype;
4131 struct eth_tx_bd_flags bd_flags;
4133 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
4134 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4135 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4136 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4137 #define ETH_TX_START_BD_RESREVED (0x1<<5)
4138 #define ETH_TX_START_BD_RESREVED_SHIFT 5
4139 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
4140 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
4144 * Tx parsing BD structure for ETH E1/E1h
4146 struct eth_tx_parse_bd_e1x {
4148 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4149 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4150 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
4151 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
4152 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
4153 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
4154 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
4155 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
4156 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
4157 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
4159 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4160 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4161 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4162 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4163 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4164 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4165 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4166 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4167 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4168 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4169 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4170 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4171 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4172 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4173 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4174 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4177 __le16 total_hlen_w;
4178 __le16 tcp_pseudo_csum;
4181 __le32 tcp_send_seq;
4185 * Tx parsing BD structure for ETH E2
4187 struct eth_tx_parse_bd_e2 {
4188 __le16 dst_mac_addr_lo;
4189 __le16 dst_mac_addr_mid;
4190 __le16 dst_mac_addr_hi;
4191 __le16 src_mac_addr_lo;
4192 __le16 src_mac_addr_mid;
4193 __le16 src_mac_addr_hi;
4194 __le32 parsing_data;
4195 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
4196 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
4197 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
4198 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
4199 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
4200 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
4201 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
4202 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
4206 * The last BD in the BD memory will hold a pointer to the next BD memory
4208 struct eth_tx_next_bd {
4215 * union for 4 Bd types
4217 union eth_tx_bd_types {
4218 struct eth_tx_start_bd start_bd;
4219 struct eth_tx_bd reg_bd;
4220 struct eth_tx_parse_bd_e1x parse_bd_e1x;
4221 struct eth_tx_parse_bd_e2 parse_bd_e2;
4222 struct eth_tx_next_bd next_bd;
4226 * array of 13 bds as appears in the eth xstorm context
4228 struct eth_tx_bds_array {
4229 union eth_tx_bd_types bds[13];
4234 * VLAN mode on TX BDs
4236 enum eth_tx_vlan_type {
4240 X_ETH_FW_ADDED_VLAN,
4241 MAX_ETH_TX_VLAN_TYPE
4246 * Ethernet VLAN filtering mode in E1x
4248 enum eth_vlan_filter_mode {
4249 ETH_VLAN_FILTER_ANY_VLAN,
4250 ETH_VLAN_FILTER_SPECIFIC_VLAN,
4251 ETH_VLAN_FILTER_CLASSIFY,
4252 MAX_ETH_VLAN_FILTER_MODE
4257 * MAC filtering configuration command header
4259 struct mac_configuration_hdr {
4267 * MAC address in list for ramrod
4269 struct mac_configuration_entry {
4270 __le16 lsb_mac_addr;
4271 __le16 middle_mac_addr;
4272 __le16 msb_mac_addr;
4276 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4277 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4278 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4279 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4280 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4281 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4282 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4283 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4284 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4285 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4286 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4287 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4289 __le32 clients_bit_vector;
4293 * MAC filtering configuration command
4295 struct mac_configuration_cmd {
4296 struct mac_configuration_hdr hdr;
4297 struct mac_configuration_entry config_table[64];
4302 * Set-MAC command type (in E1x)
4304 enum set_mac_action_type {
4305 T_ETH_MAC_COMMAND_INVALIDATE,
4306 T_ETH_MAC_COMMAND_SET,
4307 MAX_SET_MAC_ACTION_TYPE
4312 * Ethernet TPA Modes
4321 * tpa update ramrod data
4323 struct tpa_update_ramrod_data {
4328 u8 max_sges_for_packet;
4329 u8 complete_on_both_clients;
4330 u8 dont_verify_rings_pause_thr_flg;
4332 __le16 sge_buff_size;
4333 __le16 max_agg_size;
4334 __le32 sge_page_base_lo;
4335 __le32 sge_page_base_hi;
4336 __le16 sge_pause_thr_low;
4337 __le16 sge_pause_thr_high;
4342 * approximate-match multicast filtering for E1H per function in Tstorm
4344 struct tstorm_eth_approximate_match_multicast_filtering {
4345 u32 mcast_add_hash_bit_array[8];
4350 * Common configuration parameters per function in Tstorm
4352 struct tstorm_eth_function_common_config {
4353 __le16 config_flags;
4354 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4355 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4356 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4357 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4358 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4359 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4360 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4361 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4362 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4363 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4364 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4365 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4366 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4367 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4375 * MAC filtering configuration parameters per port in Tstorm
4377 struct tstorm_eth_mac_filter_config {
4378 __le32 ucast_drop_all;
4379 __le32 ucast_accept_all;
4380 __le32 mcast_drop_all;
4381 __le32 mcast_accept_all;
4382 __le32 bcast_accept_all;
4383 __le32 vlan_filter[2];
4384 __le32 unmatched_unicast;
4389 * tx only queue init ramrod data
4391 struct tx_queue_init_ramrod_data {
4392 struct client_init_general_data general;
4393 struct client_init_tx_data tx;
4398 * Three RX producers for ETH
4400 struct ustorm_eth_rx_producers {
4401 #if defined(__BIG_ENDIAN)
4404 #elif defined(__LITTLE_ENDIAN)
4408 #if defined(__BIG_ENDIAN)
4411 #elif defined(__LITTLE_ENDIAN)
4419 * FCoE RX statistics parameters section#0
4421 struct fcoe_rx_stat_params_section0 {
4422 __le32 fcoe_rx_pkt_cnt;
4423 __le32 fcoe_rx_byte_cnt;
4428 * FCoE RX statistics parameters section#1
4430 struct fcoe_rx_stat_params_section1 {
4431 __le32 fcoe_ver_cnt;
4432 __le32 fcoe_rx_drop_pkt_cnt;
4437 * FCoE RX statistics parameters section#2
4439 struct fcoe_rx_stat_params_section2 {
4441 __le32 eofa_del_cnt;
4442 __le32 miss_frame_cnt;
4443 __le32 seq_timeout_cnt;
4444 __le32 drop_seq_cnt;
4445 __le32 fcoe_rx_drop_pkt_cnt;
4446 __le32 fcp_rx_pkt_cnt;
4452 * FCoE TX statistics parameters
4454 struct fcoe_tx_stat_params {
4455 __le32 fcoe_tx_pkt_cnt;
4456 __le32 fcoe_tx_byte_cnt;
4457 __le32 fcp_tx_pkt_cnt;
4462 * FCoE statistics parameters
4464 struct fcoe_statistics_params {
4465 struct fcoe_tx_stat_params tx_stat;
4466 struct fcoe_rx_stat_params_section0 rx_stat0;
4467 struct fcoe_rx_stat_params_section1 rx_stat1;
4468 struct fcoe_rx_stat_params_section2 rx_stat2;
4473 * The data afex vif list ramrod need
4475 struct afex_vif_list_ramrod_data {
4476 u8 afex_vif_list_command;
4478 __le16 vif_list_index;
4486 * cfc delete event data
4488 struct cfc_del_event_data {
4496 * per-port SAFC demo variables
4498 struct cmng_flags_per_port {
4500 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4501 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4502 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4503 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4504 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4505 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4506 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4507 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4508 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4509 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4515 * per-port rate shaping variables
4517 struct rate_shaping_vars_per_port {
4518 u32 rs_periodic_timeout;
4523 * per-port fairness variables
4525 struct fairness_vars_per_port {
4528 u32 fairness_timeout;
4533 * per-port SAFC variables
4535 struct safc_struct_per_port {
4536 #if defined(__BIG_ENDIAN)
4539 u8 safc_timeout_usec;
4540 #elif defined(__LITTLE_ENDIAN)
4541 u8 safc_timeout_usec;
4545 u8 cos_to_traffic_types[MAX_COS_NUMBER];
4546 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4550 * Per-port congestion management variables
4552 struct cmng_struct_per_port {
4553 struct rate_shaping_vars_per_port rs_vars;
4554 struct fairness_vars_per_port fair_vars;
4555 struct safc_struct_per_port safc_vars;
4556 struct cmng_flags_per_port flags;
4560 * a single rate shaping counter. can be used as protocol or vnic counter
4562 struct rate_shaping_counter {
4564 #if defined(__BIG_ENDIAN)
4567 #elif defined(__LITTLE_ENDIAN)
4574 * per-vnic rate shaping variables
4576 struct rate_shaping_vars_per_vn {
4577 struct rate_shaping_counter vn_counter;
4581 * per-vnic fairness variables
4583 struct fairness_vars_per_vn {
4584 u32 cos_credit_delta[MAX_COS_NUMBER];
4585 u32 vn_credit_delta;
4590 * cmng port init state
4593 struct rate_shaping_vars_per_vn vnic_max_rate[4];
4594 struct fairness_vars_per_vn vnic_min_rate[4];
4598 * cmng port init state
4601 struct cmng_struct_per_port port;
4602 struct cmng_vnic vnic;
4607 * driver parameters for congestion management init, all rates are in Mbps
4609 struct cmng_init_input {
4611 u16 vnic_min_rate[4];
4612 u16 vnic_max_rate[4];
4613 u16 cos_min_rate[MAX_COS_NUMBER];
4614 u16 cos_to_pause_mask[MAX_COS_NUMBER];
4615 struct cmng_flags_per_port flags;
4620 * Protocol-common command ID for slow path elements
4622 enum common_spqe_cmd_id {
4623 RAMROD_CMD_ID_COMMON_UNUSED,
4624 RAMROD_CMD_ID_COMMON_FUNCTION_START,
4625 RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4626 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
4627 RAMROD_CMD_ID_COMMON_CFC_DEL,
4628 RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4629 RAMROD_CMD_ID_COMMON_STAT_QUERY,
4630 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4631 RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4632 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
4633 MAX_COMMON_SPQE_CMD_ID
4638 * Per-protocol connection types
4640 enum connection_type {
4641 ETH_CONNECTION_TYPE,
4642 TOE_CONNECTION_TYPE,
4643 RDMA_CONNECTION_TYPE,
4644 ISCSI_CONNECTION_TYPE,
4645 FCOE_CONNECTION_TYPE,
4646 RESERVED_CONNECTION_TYPE_0,
4647 RESERVED_CONNECTION_TYPE_1,
4648 RESERVED_CONNECTION_TYPE_2,
4649 NONE_CONNECTION_TYPE,
4666 * Dynamic HC counters set by the driver
4668 struct hc_dynamic_drv_counter {
4669 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4673 * zone A per-queue data
4675 struct cstorm_queue_zone_data {
4676 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4677 struct regpair reserved[2];
4682 * Vf-PF channel data in cstorm ram (non-triggered zone)
4684 struct vf_pf_channel_zone_data {
4690 * zone for VF non-triggered data
4692 struct non_trigger_vf_zone {
4693 struct vf_pf_channel_zone_data vf_pf_channel;
4697 * Vf-PF channel trigger zone in cstorm ram
4699 struct vf_pf_channel_zone_trigger {
4704 * zone that triggers the in-bound interrupt
4706 struct trigger_vf_zone {
4707 #if defined(__BIG_ENDIAN)
4710 struct vf_pf_channel_zone_trigger vf_pf_channel;
4711 #elif defined(__LITTLE_ENDIAN)
4712 struct vf_pf_channel_zone_trigger vf_pf_channel;
4720 * zone B per-VF data
4722 struct cstorm_vf_zone_data {
4723 struct non_trigger_vf_zone non_trigger;
4724 struct trigger_vf_zone trigger;
4729 * Dynamic host coalescing init parameters, per state machine
4731 struct dynamic_hc_sm_config {
4733 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
4734 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
4735 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
4736 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
4737 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
4741 * Dynamic host coalescing init parameters
4743 struct dynamic_hc_config {
4744 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
4748 struct e2_integ_data {
4749 #if defined(__BIG_ENDIAN)
4751 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4752 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4753 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4754 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4755 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4756 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4757 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4758 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4759 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4760 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4761 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4762 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4766 #elif defined(__LITTLE_ENDIAN)
4771 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4772 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4773 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4774 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4775 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4776 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4777 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4778 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4779 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4780 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4781 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4782 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4784 #if defined(__BIG_ENDIAN)
4788 #elif defined(__LITTLE_ENDIAN)
4797 * set mac event data
4799 struct eth_event_data {
4809 struct vf_pf_event_data {
4820 struct vf_flr_event_data {
4829 * malicious VF event data
4831 struct malicious_vf_event_data {
4840 * vif list event data
4842 struct vif_list_event_data {
4851 * union for all event ring message types
4854 struct vf_pf_event_data vf_pf_event;
4855 struct eth_event_data eth_event;
4856 struct cfc_del_event_data cfc_del_event;
4857 struct vf_flr_event_data vf_flr_event;
4858 struct malicious_vf_event_data malicious_vf_event;
4859 struct vif_list_event_data vif_list_event;
4864 * per PF event ring data
4866 struct event_ring_data {
4867 struct regpair base_addr;
4868 #if defined(__BIG_ENDIAN)
4872 #elif defined(__LITTLE_ENDIAN)
4882 * event ring message element (each element is 128 bits)
4884 struct event_ring_msg {
4888 union event_data data;
4892 * event ring next page element (128 bits)
4894 struct event_ring_next {
4895 struct regpair addr;
4900 * union for event ring element types (each element is 128 bits)
4902 union event_ring_elem {
4903 struct event_ring_msg message;
4904 struct event_ring_next next_page;
4909 * Common event ring opcodes
4911 enum event_ring_opcode {
4912 EVENT_RING_OPCODE_VF_PF_CHANNEL,
4913 EVENT_RING_OPCODE_FUNCTION_START,
4914 EVENT_RING_OPCODE_FUNCTION_STOP,
4915 EVENT_RING_OPCODE_CFC_DEL,
4916 EVENT_RING_OPCODE_CFC_DEL_WB,
4917 EVENT_RING_OPCODE_STAT_QUERY,
4918 EVENT_RING_OPCODE_STOP_TRAFFIC,
4919 EVENT_RING_OPCODE_START_TRAFFIC,
4920 EVENT_RING_OPCODE_VF_FLR,
4921 EVENT_RING_OPCODE_MALICIOUS_VF,
4922 EVENT_RING_OPCODE_FORWARD_SETUP,
4923 EVENT_RING_OPCODE_RSS_UPDATE_RULES,
4924 EVENT_RING_OPCODE_FUNCTION_UPDATE,
4925 EVENT_RING_OPCODE_AFEX_VIF_LISTS,
4926 EVENT_RING_OPCODE_SET_MAC,
4927 EVENT_RING_OPCODE_CLASSIFICATION_RULES,
4928 EVENT_RING_OPCODE_FILTERS_RULES,
4929 EVENT_RING_OPCODE_MULTICAST_RULES,
4930 MAX_EVENT_RING_OPCODE
4935 * Modes for fairness algorithm
4937 enum fairness_mode {
4938 FAIRNESS_COS_WRR_MODE,
4939 FAIRNESS_COS_ETS_MODE,
4947 struct priority_cos {
4954 * The data for flow control configuration
4956 struct flow_control_configuration {
4957 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
4960 u8 dont_add_pri_0_en;
4969 struct function_start_data {
4970 __le16 function_mode;
4974 u8 network_cos_mode;
4978 struct function_update_data {
4979 u8 vif_id_change_flg;
4980 u8 afex_default_vlan_change_flg;
4981 u8 allowed_priorities_change_flg;
4982 u8 network_cos_mode_change_flg;
4984 __le16 afex_default_vlan;
4985 u8 allowed_priorities;
4986 u8 network_cos_mode;
4994 * FW version stored in the Xstorm RAM
4997 #if defined(__BIG_ENDIAN)
5002 #elif defined(__LITTLE_ENDIAN)
5009 #define FW_VERSION_OPTIMIZED (0x1<<0)
5010 #define FW_VERSION_OPTIMIZED_SHIFT 0
5011 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
5012 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
5013 #define FW_VERSION_CHIP_VERSION (0x3<<2)
5014 #define FW_VERSION_CHIP_VERSION_SHIFT 2
5015 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
5016 #define __FW_VERSION_RESERVED_SHIFT 4
5021 * Dynamic Host-Coalescing - Driver(host) counters
5023 struct hc_dynamic_sb_drv_counters {
5024 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
5029 * 2 bytes. configuration/state parameters for a single protocol index
5031 struct hc_index_data {
5032 #if defined(__BIG_ENDIAN)
5034 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5035 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5036 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5037 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5038 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5039 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5040 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5041 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5043 #elif defined(__LITTLE_ENDIAN)
5046 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5047 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5048 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5049 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5050 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5051 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5052 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5053 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5061 struct hc_status_block_sm {
5062 #if defined(__BIG_ENDIAN)
5067 #elif defined(__LITTLE_ENDIAN)
5077 * hold PCI identification variables- used in various places in firmware
5080 #if defined(__BIG_ENDIAN)
5085 #elif defined(__LITTLE_ENDIAN)
5094 * The fast-path status block meta-data, common to all chips
5097 struct regpair host_sb_addr;
5098 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
5099 struct pci_entity p_func;
5100 #if defined(__BIG_ENDIAN)
5105 #elif defined(__LITTLE_ENDIAN)
5111 struct regpair rsrv1[2];
5116 * Segment types for host coaslescing
5126 * The fast-path status block meta-data
5128 struct hc_sp_status_block_data {
5129 struct regpair host_sb_addr;
5130 #if defined(__BIG_ENDIAN)
5135 #elif defined(__LITTLE_ENDIAN)
5141 struct pci_entity p_func;
5146 * The fast-path status block meta-data
5148 struct hc_status_block_data_e1x {
5149 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
5150 struct hc_sb_data common;
5155 * The fast-path status block meta-data
5157 struct hc_status_block_data_e2 {
5158 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
5159 struct hc_sb_data common;
5164 * IGU block operartion modes (in Everest2)
5184 * Multi-function modes
5190 MULTI_FUNCTION_AFEX,
5195 * Protocol-common statistics collected by the Tstorm (per pf)
5197 struct tstorm_per_pf_stats {
5198 struct regpair rcv_error_bytes;
5204 struct per_pf_stats {
5205 struct tstorm_per_pf_stats tstorm_pf_statistics;
5210 * Protocol-common statistics collected by the Tstorm (per port)
5212 struct tstorm_per_port_stats {
5214 __le32 mac_filter_discard;
5215 __le32 brb_truncate_discard;
5216 __le32 mf_tag_discard;
5224 struct per_port_stats {
5225 struct tstorm_per_port_stats tstorm_port_statistics;
5230 * Protocol-common statistics collected by the Tstorm (per client)
5232 struct tstorm_per_queue_stats {
5233 struct regpair rcv_ucast_bytes;
5234 __le32 rcv_ucast_pkts;
5235 __le32 checksum_discard;
5236 struct regpair rcv_bcast_bytes;
5237 __le32 rcv_bcast_pkts;
5238 __le32 pkts_too_big_discard;
5239 struct regpair rcv_mcast_bytes;
5240 __le32 rcv_mcast_pkts;
5241 __le32 ttl0_discard;
5242 __le16 no_buff_discard;
5248 * Protocol-common statistics collected by the Ustorm (per client)
5250 struct ustorm_per_queue_stats {
5251 struct regpair ucast_no_buff_bytes;
5252 struct regpair mcast_no_buff_bytes;
5253 struct regpair bcast_no_buff_bytes;
5254 __le32 ucast_no_buff_pkts;
5255 __le32 mcast_no_buff_pkts;
5256 __le32 bcast_no_buff_pkts;
5257 __le32 coalesced_pkts;
5258 struct regpair coalesced_bytes;
5259 __le32 coalesced_events;
5260 __le32 coalesced_aborts;
5264 * Protocol-common statistics collected by the Xstorm (per client)
5266 struct xstorm_per_queue_stats {
5267 struct regpair ucast_bytes_sent;
5268 struct regpair mcast_bytes_sent;
5269 struct regpair bcast_bytes_sent;
5270 __le32 ucast_pkts_sent;
5271 __le32 mcast_pkts_sent;
5272 __le32 bcast_pkts_sent;
5273 __le32 error_drop_pkts;
5279 struct per_queue_stats {
5280 struct tstorm_per_queue_stats tstorm_queue_statistics;
5281 struct ustorm_per_queue_stats ustorm_queue_statistics;
5282 struct xstorm_per_queue_stats xstorm_queue_statistics;
5287 * FW version stored in first line of pram
5289 struct pram_fw_version {
5295 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5296 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5297 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5298 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
5299 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5300 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
5301 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5302 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
5303 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
5304 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
5309 * Ethernet slow path element
5311 union protocol_common_specific_data {
5312 u8 protocol_data[8];
5313 struct regpair phy_address;
5314 struct regpair mac_config_addr;
5315 struct afex_vif_list_ramrod_data afex_vif_list_data;
5319 * The send queue element
5321 struct protocol_common_spe {
5323 union protocol_common_specific_data data;
5328 * The send queue element
5330 struct slow_path_element {
5332 struct regpair protocol_data;
5337 * Protocol-common statistics counter
5339 struct stats_counter {
5340 __le16 xstats_counter;
5343 __le16 tstats_counter;
5346 __le16 ustats_counter;
5349 __le16 cstats_counter;
5358 struct stats_query_entry {
5363 struct regpair address;
5369 struct stats_query_cmd_group {
5370 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
5375 * statistic command header
5377 struct stats_query_header {
5380 __le16 drv_stats_counter;
5382 struct regpair stats_counters_addrs;
5387 * Types of statistcis query entry
5389 enum stats_query_type {
5395 MAX_STATS_QUERY_TYPE
5400 * Indicate of the function status block state
5402 enum status_block_state {
5406 MAX_STATUS_BLOCK_STATE
5411 * Storm IDs (including attentions for IGU related enums)
5424 * Taffic types used in ETS and flow control algorithms
5427 LLFC_TRAFFIC_TYPE_NW,
5428 LLFC_TRAFFIC_TYPE_FCOE,
5429 LLFC_TRAFFIC_TYPE_ISCSI,
5435 * zone A per-queue data
5437 struct tstorm_queue_zone_data {
5438 struct regpair reserved[4];
5443 * zone B per-VF data
5445 struct tstorm_vf_zone_data {
5446 struct regpair reserved;
5451 * zone A per-queue data
5453 struct ustorm_queue_zone_data {
5454 struct ustorm_eth_rx_producers eth_rx_producers;
5455 struct regpair reserved[3];
5460 * zone B per-VF data
5462 struct ustorm_vf_zone_data {
5463 struct regpair reserved;
5468 * data per VF-PF channel
5470 struct vf_pf_channel_data {
5471 #if defined(__BIG_ENDIAN)
5475 #elif defined(__LITTLE_ENDIAN)
5485 * State of VF-PF channel
5487 enum vf_pf_channel_state {
5488 VF_PF_CHANNEL_STATE_READY,
5489 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5490 MAX_VF_PF_CHANNEL_STATE
5495 * vif_list_rule_kind
5497 enum vif_list_rule_kind {
5500 VIF_LIST_RULE_CLEAR_ALL,
5501 VIF_LIST_RULE_CLEAR_FUNC,
5502 MAX_VIF_LIST_RULE_KIND
5507 * zone A per-queue data
5509 struct xstorm_queue_zone_data {
5510 struct regpair reserved[4];
5515 * zone B per-VF data
5517 struct xstorm_vf_zone_data {
5518 struct regpair reserved;
5521 #endif /* BNX2X_HSI_H */
git.openpandora.org / pandora-kernel.git / blob