drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2011 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29 #include "bnx2x_dump.h"
  30 #include "bnx2x_init.h"
  31 #include "bnx2x_sp.h"
  32
  33 /* Note: in the format strings below %s is replaced by the queue-name which is
  34  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  35  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  36  */
  37 #define MAX_QUEUE_NAME_LEN      4
  38 static const struct {
  39         long offset;
  40         int size;
  41         char string[ETH_GSTRING_LEN];
  42 } bnx2x_q_stats_arr[] = {
  43 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  44         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  45                                                 8, "[%s]: rx_ucast_packets" },
  46         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  47                                                 8, "[%s]: rx_mcast_packets" },
  48         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  49                                                 8, "[%s]: rx_bcast_packets" },
  50         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  51         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  52                                          4, "[%s]: rx_phy_ip_err_discards"},
  53         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  54                                          4, "[%s]: rx_skb_alloc_discard" },
  55         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  56
  57         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  58 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  59                                                 8, "[%s]: tx_ucast_packets" },
  60         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  61                                                 8, "[%s]: tx_mcast_packets" },
  62         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  63                                                 8, "[%s]: tx_bcast_packets" },
  64         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  65                                                 8, "[%s]: tpa_aggregations" },
  66         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  67                                         8, "[%s]: tpa_aggregated_frames"},
  68         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
  69 };
  70
  71 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  72
  73 static const struct {
  74         long offset;
  75         int size;
  76         u32 flags;
  77 #define STATS_FLAGS_PORT                1
  78 #define STATS_FLAGS_FUNC                2
  79 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  80         char string[ETH_GSTRING_LEN];
  81 } bnx2x_stats_arr[] = {
  82 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  83                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  84         { STATS_OFFSET32(error_bytes_received_hi),
  85                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  86         { STATS_OFFSET32(total_unicast_packets_received_hi),
  87                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  88         { STATS_OFFSET32(total_multicast_packets_received_hi),
  89                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  90         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  91                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  92         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  93                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  94         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  95                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  96         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  97                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  98         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  99                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
 100 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
 101                                 8, STATS_FLAGS_PORT, "rx_fragments" },
 102         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 103                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 104         { STATS_OFFSET32(no_buff_discard_hi),
 105                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 106         { STATS_OFFSET32(mac_filter_discard),
 107                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 108         { STATS_OFFSET32(mf_tag_discard),
 109                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 110         { STATS_OFFSET32(brb_drop_hi),
 111                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 112         { STATS_OFFSET32(brb_truncate_hi),
 113                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 114         { STATS_OFFSET32(pause_frames_received_hi),
 115                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 116         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 117                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 118         { STATS_OFFSET32(nig_timer_max),
 119                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 120 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 121                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 122         { STATS_OFFSET32(rx_skb_alloc_failed),
 123                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 124         { STATS_OFFSET32(hw_csum_err),
 125                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 126
 127         { STATS_OFFSET32(total_bytes_transmitted_hi),
 128                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 129         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 130                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 131         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 132                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 133         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 134                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 135         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 136                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 137         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 138                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 139         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 140                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 141 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 142                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 143         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 144                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 145         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 146                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 147         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 148                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 149         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 150                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 151         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 152                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 153         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 154                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 155         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 156                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 157         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 158                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 159         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 160                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 161 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 162                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 163         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 164                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 165         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 166                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 167         { STATS_OFFSET32(pause_frames_sent_hi),
 168                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 169         { STATS_OFFSET32(total_tpa_aggregations_hi),
 170                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 171         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 172                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 173         { STATS_OFFSET32(total_tpa_bytes_hi),
 174                         8, STATS_FLAGS_FUNC, "tpa_bytes"}
 175 };
 176
 177 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 178 static int bnx2x_get_port_type(struct bnx2x *bp)
 179 {
 180         int port_type;
 181         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 182         switch (bp->link_params.phy[phy_idx].media_type) {
 183         case ETH_PHY_SFP_FIBER:
 184         case ETH_PHY_XFP_FIBER:
 185         case ETH_PHY_KR:
 186         case ETH_PHY_CX4:
 187                 port_type = PORT_FIBRE;
 188                 break;
 189         case ETH_PHY_DA_TWINAX:
 190                 port_type = PORT_DA;
 191                 break;
 192         case ETH_PHY_BASE_T:
 193                 port_type = PORT_TP;
 194                 break;
 195         case ETH_PHY_NOT_PRESENT:
 196                 port_type = PORT_NONE;
 197                 break;
 198         case ETH_PHY_UNSPECIFIED:
 199         default:
 200                 port_type = PORT_OTHER;
 201                 break;
 202         }
 203         return port_type;
 204 }
 205
 206 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 207 {
 208         struct bnx2x *bp = netdev_priv(dev);
 209         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 210
 211         /* Dual Media boards present all available port types */
 212         cmd->supported = bp->port.supported[cfg_idx] |
 213                 (bp->port.supported[cfg_idx ^ 1] &
 214                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 215         cmd->advertising = bp->port.advertising[cfg_idx];
 216
 217         if ((bp->state == BNX2X_STATE_OPEN) &&
 218             !(bp->flags & MF_FUNC_DIS) &&
 219             (bp->link_vars.link_up)) {
 220                 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 221                 cmd->duplex = bp->link_vars.duplex;
 222         } else {
 223                 ethtool_cmd_speed_set(
 224                         cmd, bp->link_params.req_line_speed[cfg_idx]);
 225                 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
 226         }
 227
 228         if (IS_MF(bp))
 229                 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 230
 231         cmd->port = bnx2x_get_port_type(bp);
 232
 233         cmd->phy_address = bp->mdio.prtad;
 234         cmd->transceiver = XCVR_INTERNAL;
 235
 236         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 237                 cmd->autoneg = AUTONEG_ENABLE;
 238         else
 239                 cmd->autoneg = AUTONEG_DISABLE;
 240
 241         cmd->maxtxpkt = 0;
 242         cmd->maxrxpkt = 0;
 243
 244         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 245            "  supported 0x%x  advertising 0x%x  speed %u\n"
 246            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 247            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 248            cmd->cmd, cmd->supported, cmd->advertising,
 249            ethtool_cmd_speed(cmd),
 250            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 251            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 252
 253         return 0;
 254 }
 255
 256 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 257 {
 258         struct bnx2x *bp = netdev_priv(dev);
 259         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 260         u32 speed;
 261
 262         if (IS_MF_SD(bp))
 263                 return 0;
 264
 265         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 266            "  supported 0x%x  advertising 0x%x  speed %u\n"
 267            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 268            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 269            cmd->cmd, cmd->supported, cmd->advertising,
 270            ethtool_cmd_speed(cmd),
 271            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 272            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 273
 274         speed = ethtool_cmd_speed(cmd);
 275
 276         if (IS_MF_SI(bp)) {
 277                 u32 part;
 278                 u32 line_speed = bp->link_vars.line_speed;
 279
 280                 /* use 10G if no link detected */
 281                 if (!line_speed)
 282                         line_speed = 10000;
 283
 284                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 285                         BNX2X_DEV_INFO("To set speed BC %X or higher "
 286                                        "is required, please upgrade BC\n",
 287                                        REQ_BC_VER_4_SET_MF_BW);
 288                         return -EINVAL;
 289                 }
 290
 291                 part = (speed * 100) / line_speed;
 292
 293                 if (line_speed < speed || !part) {
 294                         BNX2X_DEV_INFO("Speed setting should be in a range "
 295                                        "from 1%% to 100%% "
 296                                        "of actual line speed\n");
 297                         return -EINVAL;
 298                 }
 299
 300                 if (bp->state != BNX2X_STATE_OPEN)
 301                         /* store value for following "load" */
 302                         bp->pending_max = part;
 303                 else
 304                         bnx2x_update_max_mf_config(bp, part);
 305
 306                 return 0;
 307         }
 308
 309         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 310         old_multi_phy_config = bp->link_params.multi_phy_config;
 311         switch (cmd->port) {
 312         case PORT_TP:
 313                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 314                         break; /* no port change */
 315
 316                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 317                       bp->port.supported[1] & SUPPORTED_TP)) {
 318                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 319                         return -EINVAL;
 320                 }
 321                 bp->link_params.multi_phy_config &=
 322                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 323                 if (bp->link_params.multi_phy_config &
 324                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 325                         bp->link_params.multi_phy_config |=
 326                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 327                 else
 328                         bp->link_params.multi_phy_config |=
 329                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 330                 break;
 331         case PORT_FIBRE:
 332                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 333                         break; /* no port change */
 334
 335                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 336                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 337                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 338                         return -EINVAL;
 339                 }
 340                 bp->link_params.multi_phy_config &=
 341                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 342                 if (bp->link_params.multi_phy_config &
 343                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 344                         bp->link_params.multi_phy_config |=
 345                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 346                 else
 347                         bp->link_params.multi_phy_config |=
 348                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 349                 break;
 350         default:
 351                 DP(NETIF_MSG_LINK, "Unsupported port type\n");
 352                 return -EINVAL;
 353         }
 354         /* Save new config in case command complete successuly */
 355         new_multi_phy_config = bp->link_params.multi_phy_config;
 356         /* Get the new cfg_idx */
 357         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 358         /* Restore old config in case command failed */
 359         bp->link_params.multi_phy_config = old_multi_phy_config;
 360         DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
 361
 362         if (cmd->autoneg == AUTONEG_ENABLE) {
 363                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 364                         DP(NETIF_MSG_LINK, "Autoneg not supported\n");
 365                         return -EINVAL;
 366                 }
 367
 368                 /* advertise the requested speed and duplex if supported */
 369                 cmd->advertising &= bp->port.supported[cfg_idx];
 370
 371                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 372                 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
 373                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
 374                                          cmd->advertising);
 375
 376         } else { /* forced speed */
 377                 /* advertise the requested speed and duplex if supported */
 378                 switch (speed) {
 379                 case SPEED_10:
 380                         if (cmd->duplex == DUPLEX_FULL) {
 381                                 if (!(bp->port.supported[cfg_idx] &
 382                                       SUPPORTED_10baseT_Full)) {
 383                                         DP(NETIF_MSG_LINK,
 384                                            "10M full not supported\n");
 385                                         return -EINVAL;
 386                                 }
 387
 388                                 advertising = (ADVERTISED_10baseT_Full |
 389                                                ADVERTISED_TP);
 390                         } else {
 391                                 if (!(bp->port.supported[cfg_idx] &
 392                                       SUPPORTED_10baseT_Half)) {
 393                                         DP(NETIF_MSG_LINK,
 394                                            "10M half not supported\n");
 395                                         return -EINVAL;
 396                                 }
 397
 398                                 advertising = (ADVERTISED_10baseT_Half |
 399                                                ADVERTISED_TP);
 400                         }
 401                         break;
 402
 403                 case SPEED_100:
 404                         if (cmd->duplex == DUPLEX_FULL) {
 405                                 if (!(bp->port.supported[cfg_idx] &
 406                                                 SUPPORTED_100baseT_Full)) {
 407                                         DP(NETIF_MSG_LINK,
 408                                            "100M full not supported\n");
 409                                         return -EINVAL;
 410                                 }
 411
 412                                 advertising = (ADVERTISED_100baseT_Full |
 413                                                ADVERTISED_TP);
 414                         } else {
 415                                 if (!(bp->port.supported[cfg_idx] &
 416                                                 SUPPORTED_100baseT_Half)) {
 417                                         DP(NETIF_MSG_LINK,
 418                                            "100M half not supported\n");
 419                                         return -EINVAL;
 420                                 }
 421
 422                                 advertising = (ADVERTISED_100baseT_Half |
 423                                                ADVERTISED_TP);
 424                         }
 425                         break;
 426
 427                 case SPEED_1000:
 428                         if (cmd->duplex != DUPLEX_FULL) {
 429                                 DP(NETIF_MSG_LINK, "1G half not supported\n");
 430                                 return -EINVAL;
 431                         }
 432
 433                         if (!(bp->port.supported[cfg_idx] &
 434                               SUPPORTED_1000baseT_Full)) {
 435                                 DP(NETIF_MSG_LINK, "1G full not supported\n");
 436                                 return -EINVAL;
 437                         }
 438
 439                         advertising = (ADVERTISED_1000baseT_Full |
 440                                        ADVERTISED_TP);
 441                         break;
 442
 443                 case SPEED_2500:
 444                         if (cmd->duplex != DUPLEX_FULL) {
 445                                 DP(NETIF_MSG_LINK,
 446                                    "2.5G half not supported\n");
 447                                 return -EINVAL;
 448                         }
 449
 450                         if (!(bp->port.supported[cfg_idx]
 451                               & SUPPORTED_2500baseX_Full)) {
 452                                 DP(NETIF_MSG_LINK,
 453                                    "2.5G full not supported\n");
 454                                 return -EINVAL;
 455                         }
 456
 457                         advertising = (ADVERTISED_2500baseX_Full |
 458                                        ADVERTISED_TP);
 459                         break;
 460
 461                 case SPEED_10000:
 462                         if (cmd->duplex != DUPLEX_FULL) {
 463                                 DP(NETIF_MSG_LINK, "10G half not supported\n");
 464                                 return -EINVAL;
 465                         }
 466
 467                         if (!(bp->port.supported[cfg_idx]
 468                               & SUPPORTED_10000baseT_Full)) {
 469                                 DP(NETIF_MSG_LINK, "10G full not supported\n");
 470                                 return -EINVAL;
 471                         }
 472
 473                         advertising = (ADVERTISED_10000baseT_Full |
 474                                        ADVERTISED_FIBRE);
 475                         break;
 476
 477                 default:
 478                         DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
 479                         return -EINVAL;
 480                 }
 481
 482                 bp->link_params.req_line_speed[cfg_idx] = speed;
 483                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 484                 bp->port.advertising[cfg_idx] = advertising;
 485         }
 486
 487         DP(NETIF_MSG_LINK, "req_line_speed %d\n"
 488            "  req_duplex %d  advertising 0x%x\n",
 489            bp->link_params.req_line_speed[cfg_idx],
 490            bp->link_params.req_duplex[cfg_idx],
 491            bp->port.advertising[cfg_idx]);
 492
 493         /* Set new config */
 494         bp->link_params.multi_phy_config = new_multi_phy_config;
 495         if (netif_running(dev)) {
 496                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 497                 bnx2x_link_set(bp);
 498         }
 499
 500         return 0;
 501 }
 502
 503 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 504 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 505 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 506 #define IS_E3_ONLINE(info)      (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
 507 #define IS_E3B0_ONLINE(info)    (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
 508
 509 static inline bool bnx2x_is_reg_online(struct bnx2x *bp,
 510                                        const struct reg_addr *reg_info)
 511 {
 512         if (CHIP_IS_E1(bp))
 513                 return IS_E1_ONLINE(reg_info->info);
 514         else if (CHIP_IS_E1H(bp))
 515                 return IS_E1H_ONLINE(reg_info->info);
 516         else if (CHIP_IS_E2(bp))
 517                 return IS_E2_ONLINE(reg_info->info);
 518         else if (CHIP_IS_E3A0(bp))
 519                 return IS_E3_ONLINE(reg_info->info);
 520         else if (CHIP_IS_E3B0(bp))
 521                 return IS_E3B0_ONLINE(reg_info->info);
 522         else
 523                 return false;
 524 }
 525
 526 /******* Paged registers info selectors ********/
 527 static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 528 {
 529         if (CHIP_IS_E2(bp))
 530                 return page_vals_e2;
 531         else if (CHIP_IS_E3(bp))
 532                 return page_vals_e3;
 533         else
 534                 return NULL;
 535 }
 536
 537 static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 538 {
 539         if (CHIP_IS_E2(bp))
 540                 return PAGE_MODE_VALUES_E2;
 541         else if (CHIP_IS_E3(bp))
 542                 return PAGE_MODE_VALUES_E3;
 543         else
 544                 return 0;
 545 }
 546
 547 static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 548 {
 549         if (CHIP_IS_E2(bp))
 550                 return page_write_regs_e2;
 551         else if (CHIP_IS_E3(bp))
 552                 return page_write_regs_e3;
 553         else
 554                 return NULL;
 555 }
 556
 557 static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 558 {
 559         if (CHIP_IS_E2(bp))
 560                 return PAGE_WRITE_REGS_E2;
 561         else if (CHIP_IS_E3(bp))
 562                 return PAGE_WRITE_REGS_E3;
 563         else
 564                 return 0;
 565 }
 566
 567 static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 568 {
 569         if (CHIP_IS_E2(bp))
 570                 return page_read_regs_e2;
 571         else if (CHIP_IS_E3(bp))
 572                 return page_read_regs_e3;
 573         else
 574                 return NULL;
 575 }
 576
 577 static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 578 {
 579         if (CHIP_IS_E2(bp))
 580                 return PAGE_READ_REGS_E2;
 581         else if (CHIP_IS_E3(bp))
 582                 return PAGE_READ_REGS_E3;
 583         else
 584                 return 0;
 585 }
 586
 587 static inline int __bnx2x_get_regs_len(struct bnx2x *bp)
 588 {
 589         int num_pages = __bnx2x_get_page_reg_num(bp);
 590         int page_write_num = __bnx2x_get_page_write_num(bp);
 591         const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
 592         int page_read_num = __bnx2x_get_page_read_num(bp);
 593         int regdump_len = 0;
 594         int i, j, k;
 595
 596         for (i = 0; i < REGS_COUNT; i++)
 597                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 598                         regdump_len += reg_addrs[i].size;
 599
 600         for (i = 0; i < num_pages; i++)
 601                 for (j = 0; j < page_write_num; j++)
 602                         for (k = 0; k < page_read_num; k++)
 603                                 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
 604                                         regdump_len += page_read_addr[k].size;
 605
 606         return regdump_len;
 607 }
 608
 609 static int bnx2x_get_regs_len(struct net_device *dev)
 610 {
 611         struct bnx2x *bp = netdev_priv(dev);
 612         int regdump_len = 0;
 613
 614         regdump_len = __bnx2x_get_regs_len(bp);
 615         regdump_len *= 4;
 616         regdump_len += sizeof(struct dump_hdr);
 617
 618         return regdump_len;
 619 }
 620
 621 /**
 622  * bnx2x_read_pages_regs - read "paged" registers
 623  *
 624  * @bp          device handle
 625  * @p           output buffer
 626  *
 627  * Reads "paged" memories: memories that may only be read by first writing to a
 628  * specific address ("write address") and then reading from a specific address
 629  * ("read address"). There may be more than one write address per "page" and
 630  * more than one read address per write address.
 631  */
 632 static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
 633 {
 634         u32 i, j, k, n;
 635         /* addresses of the paged registers */
 636         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 637         /* number of paged registers */
 638         int num_pages = __bnx2x_get_page_reg_num(bp);
 639         /* write addresses */
 640         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 641         /* number of write addresses */
 642         int write_num = __bnx2x_get_page_write_num(bp);
 643         /* read addresses info */
 644         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 645         /* number of read addresses */
 646         int read_num = __bnx2x_get_page_read_num(bp);
 647
 648         for (i = 0; i < num_pages; i++) {
 649                 for (j = 0; j < write_num; j++) {
 650                         REG_WR(bp, write_addr[j], page_addr[i]);
 651                         for (k = 0; k < read_num; k++)
 652                                 if (bnx2x_is_reg_online(bp, &read_addr[k]))
 653                                         for (n = 0; n <
 654                                               read_addr[k].size; n++)
 655                                                 *p++ = REG_RD(bp,
 656                                                        read_addr[k].addr + n*4);
 657                 }
 658         }
 659 }
 660
 661 static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 662 {
 663         u32 i, j;
 664
 665         /* Read the regular registers */
 666         for (i = 0; i < REGS_COUNT; i++)
 667                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 668                         for (j = 0; j < reg_addrs[i].size; j++)
 669                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 670
 671         /* Read "paged" registes */
 672         bnx2x_read_pages_regs(bp, p);
 673 }
 674
 675 static void bnx2x_get_regs(struct net_device *dev,
 676                            struct ethtool_regs *regs, void *_p)
 677 {
 678         u32 *p = _p;
 679         struct bnx2x *bp = netdev_priv(dev);
 680         struct dump_hdr dump_hdr = {0};
 681
 682         regs->version = 0;
 683         memset(p, 0, regs->len);
 684
 685         if (!netif_running(bp->dev))
 686                 return;
 687
 688         /* Disable parity attentions as long as following dump may
 689          * cause false alarms by reading never written registers. We
 690          * will re-enable parity attentions right after the dump.
 691          */
 692         bnx2x_disable_blocks_parity(bp);
 693
 694         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 695         dump_hdr.dump_sign = dump_sign_all;
 696         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 697         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 698         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 699         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 700
 701         if (CHIP_IS_E1(bp))
 702                 dump_hdr.info = RI_E1_ONLINE;
 703         else if (CHIP_IS_E1H(bp))
 704                 dump_hdr.info = RI_E1H_ONLINE;
 705         else if (!CHIP_IS_E1x(bp))
 706                 dump_hdr.info = RI_E2_ONLINE |
 707                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 708
 709         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 710         p += dump_hdr.hdr_size + 1;
 711
 712         /* Actually read the registers */
 713         __bnx2x_get_regs(bp, p);
 714
 715         /* Re-enable parity attentions */
 716         bnx2x_clear_blocks_parity(bp);
 717         bnx2x_enable_blocks_parity(bp);
 718 }
 719
 720 static void bnx2x_get_drvinfo(struct net_device *dev,
 721                               struct ethtool_drvinfo *info)
 722 {
 723         struct bnx2x *bp = netdev_priv(dev);
 724         u8 phy_fw_ver[PHY_FW_VER_LEN];
 725
 726         strcpy(info->driver, DRV_MODULE_NAME);
 727         strcpy(info->version, DRV_MODULE_VERSION);
 728
 729         phy_fw_ver[0] = '\0';
 730         if (bp->port.pmf) {
 731                 bnx2x_acquire_phy_lock(bp);
 732                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
 733                                              (bp->state != BNX2X_STATE_CLOSED),
 734                                              phy_fw_ver, PHY_FW_VER_LEN);
 735                 bnx2x_release_phy_lock(bp);
 736         }
 737
 738         strncpy(info->fw_version, bp->fw_ver, 32);
 739         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 740                  "bc %d.%d.%d%s%s",
 741                  (bp->common.bc_ver & 0xff0000) >> 16,
 742                  (bp->common.bc_ver & 0xff00) >> 8,
 743                  (bp->common.bc_ver & 0xff),
 744                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 745         strcpy(info->bus_info, pci_name(bp->pdev));
 746         info->n_stats = BNX2X_NUM_STATS;
 747         info->testinfo_len = BNX2X_NUM_TESTS;
 748         info->eedump_len = bp->common.flash_size;
 749         info->regdump_len = bnx2x_get_regs_len(dev);
 750 }
 751
 752 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 753 {
 754         struct bnx2x *bp = netdev_priv(dev);
 755
 756         if (bp->flags & NO_WOL_FLAG) {
 757                 wol->supported = 0;
 758                 wol->wolopts = 0;
 759         } else {
 760                 wol->supported = WAKE_MAGIC;
 761                 if (bp->wol)
 762                         wol->wolopts = WAKE_MAGIC;
 763                 else
 764                         wol->wolopts = 0;
 765         }
 766         memset(&wol->sopass, 0, sizeof(wol->sopass));
 767 }
 768
 769 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 770 {
 771         struct bnx2x *bp = netdev_priv(dev);
 772
 773         if (wol->wolopts & ~WAKE_MAGIC)
 774                 return -EINVAL;
 775
 776         if (wol->wolopts & WAKE_MAGIC) {
 777                 if (bp->flags & NO_WOL_FLAG)
 778                         return -EINVAL;
 779
 780                 bp->wol = 1;
 781         } else
 782                 bp->wol = 0;
 783
 784         return 0;
 785 }
 786
 787 static u32 bnx2x_get_msglevel(struct net_device *dev)
 788 {
 789         struct bnx2x *bp = netdev_priv(dev);
 790
 791         return bp->msg_enable;
 792 }
 793
 794 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 795 {
 796         struct bnx2x *bp = netdev_priv(dev);
 797
 798         if (capable(CAP_NET_ADMIN)) {
 799                 /* dump MCP trace */
 800                 if (level & BNX2X_MSG_MCP)
 801                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
 802                 bp->msg_enable = level;
 803         }
 804 }
 805
 806 static int bnx2x_nway_reset(struct net_device *dev)
 807 {
 808         struct bnx2x *bp = netdev_priv(dev);
 809
 810         if (!bp->port.pmf)
 811                 return 0;
 812
 813         if (netif_running(dev)) {
 814                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 815                 bnx2x_link_set(bp);
 816         }
 817
 818         return 0;
 819 }
 820
 821 static u32 bnx2x_get_link(struct net_device *dev)
 822 {
 823         struct bnx2x *bp = netdev_priv(dev);
 824
 825         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 826                 return 0;
 827
 828         return bp->link_vars.link_up;
 829 }
 830
 831 static int bnx2x_get_eeprom_len(struct net_device *dev)
 832 {
 833         struct bnx2x *bp = netdev_priv(dev);
 834
 835         return bp->common.flash_size;
 836 }
 837
 838 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 839 {
 840         int port = BP_PORT(bp);
 841         int count, i;
 842         u32 val = 0;
 843
 844         /* adjust timeout for emulation/FPGA */
 845         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 846         if (CHIP_REV_IS_SLOW(bp))
 847                 count *= 100;
 848
 849         /* request access to nvram interface */
 850         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 851                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 852
 853         for (i = 0; i < count*10; i++) {
 854                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 855                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 856                         break;
 857
 858                 udelay(5);
 859         }
 860
 861         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 862                 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
 863                 return -EBUSY;
 864         }
 865
 866         return 0;
 867 }
 868
 869 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 870 {
 871         int port = BP_PORT(bp);
 872         int count, i;
 873         u32 val = 0;
 874
 875         /* adjust timeout for emulation/FPGA */
 876         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 877         if (CHIP_REV_IS_SLOW(bp))
 878                 count *= 100;
 879
 880         /* relinquish nvram interface */
 881         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 882                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 883
 884         for (i = 0; i < count*10; i++) {
 885                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 886                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 887                         break;
 888
 889                 udelay(5);
 890         }
 891
 892         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
 893                 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
 894                 return -EBUSY;
 895         }
 896
 897         return 0;
 898 }
 899
 900 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
 901 {
 902         u32 val;
 903
 904         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 905
 906         /* enable both bits, even on read */
 907         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 908                (val | MCPR_NVM_ACCESS_ENABLE_EN |
 909                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
 910 }
 911
 912 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
 913 {
 914         u32 val;
 915
 916         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 917
 918         /* disable both bits, even after read */
 919         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 920                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
 921                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
 922 }
 923
 924 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
 925                                   u32 cmd_flags)
 926 {
 927         int count, i, rc;
 928         u32 val;
 929
 930         /* build the command word */
 931         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
 932
 933         /* need to clear DONE bit separately */
 934         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 935
 936         /* address of the NVRAM to read from */
 937         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 938                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 939
 940         /* issue a read command */
 941         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 942
 943         /* adjust timeout for emulation/FPGA */
 944         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 945         if (CHIP_REV_IS_SLOW(bp))
 946                 count *= 100;
 947
 948         /* wait for completion */
 949         *ret_val = 0;
 950         rc = -EBUSY;
 951         for (i = 0; i < count; i++) {
 952                 udelay(5);
 953                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 954
 955                 if (val & MCPR_NVM_COMMAND_DONE) {
 956                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
 957                         /* we read nvram data in cpu order
 958                          * but ethtool sees it as an array of bytes
 959                          * converting to big-endian will do the work */
 960                         *ret_val = cpu_to_be32(val);
 961                         rc = 0;
 962                         break;
 963                 }
 964         }
 965
 966         return rc;
 967 }
 968
 969 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
 970                             int buf_size)
 971 {
 972         int rc;
 973         u32 cmd_flags;
 974         __be32 val;
 975
 976         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
 977                 DP(BNX2X_MSG_NVM,
 978                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
 979                    offset, buf_size);
 980                 return -EINVAL;
 981         }
 982
 983         if (offset + buf_size > bp->common.flash_size) {
 984                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
 985                                   " buf_size (0x%x) > flash_size (0x%x)\n",
 986                    offset, buf_size, bp->common.flash_size);
 987                 return -EINVAL;
 988         }
 989
 990         /* request access to nvram interface */
 991         rc = bnx2x_acquire_nvram_lock(bp);
 992         if (rc)
 993                 return rc;
 994
 995         /* enable access to nvram interface */
 996         bnx2x_enable_nvram_access(bp);
 997
 998         /* read the first word(s) */
 999         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1000         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1001                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1002                 memcpy(ret_buf, &val, 4);
1003
1004                 /* advance to the next dword */
1005                 offset += sizeof(u32);
1006                 ret_buf += sizeof(u32);
1007                 buf_size -= sizeof(u32);
1008                 cmd_flags = 0;
1009         }
1010
1011         if (rc == 0) {
1012                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1013                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1014                 memcpy(ret_buf, &val, 4);
1015         }
1016
1017         /* disable access to nvram interface */
1018         bnx2x_disable_nvram_access(bp);
1019         bnx2x_release_nvram_lock(bp);
1020
1021         return rc;
1022 }
1023
1024 static int bnx2x_get_eeprom(struct net_device *dev,
1025                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1026 {
1027         struct bnx2x *bp = netdev_priv(dev);
1028         int rc;
1029
1030         if (!netif_running(dev))
1031                 return -EAGAIN;
1032
1033         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1034            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1035            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1036            eeprom->len, eeprom->len);
1037
1038         /* parameters already validated in ethtool_get_eeprom */
1039
1040         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1041
1042         return rc;
1043 }
1044
1045 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1046                                    u32 cmd_flags)
1047 {
1048         int count, i, rc;
1049
1050         /* build the command word */
1051         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1052
1053         /* need to clear DONE bit separately */
1054         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1055
1056         /* write the data */
1057         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1058
1059         /* address of the NVRAM to write to */
1060         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1061                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1062
1063         /* issue the write command */
1064         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1065
1066         /* adjust timeout for emulation/FPGA */
1067         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1068         if (CHIP_REV_IS_SLOW(bp))
1069                 count *= 100;
1070
1071         /* wait for completion */
1072         rc = -EBUSY;
1073         for (i = 0; i < count; i++) {
1074                 udelay(5);
1075                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1076                 if (val & MCPR_NVM_COMMAND_DONE) {
1077                         rc = 0;
1078                         break;
1079                 }
1080         }
1081
1082         return rc;
1083 }
1084
1085 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1086
1087 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1088                               int buf_size)
1089 {
1090         int rc;
1091         u32 cmd_flags;
1092         u32 align_offset;
1093         __be32 val;
1094
1095         if (offset + buf_size > bp->common.flash_size) {
1096                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1097                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1098                    offset, buf_size, bp->common.flash_size);
1099                 return -EINVAL;
1100         }
1101
1102         /* request access to nvram interface */
1103         rc = bnx2x_acquire_nvram_lock(bp);
1104         if (rc)
1105                 return rc;
1106
1107         /* enable access to nvram interface */
1108         bnx2x_enable_nvram_access(bp);
1109
1110         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1111         align_offset = (offset & ~0x03);
1112         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1113
1114         if (rc == 0) {
1115                 val &= ~(0xff << BYTE_OFFSET(offset));
1116                 val |= (*data_buf << BYTE_OFFSET(offset));
1117
1118                 /* nvram data is returned as an array of bytes
1119                  * convert it back to cpu order */
1120                 val = be32_to_cpu(val);
1121
1122                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1123                                              cmd_flags);
1124         }
1125
1126         /* disable access to nvram interface */
1127         bnx2x_disable_nvram_access(bp);
1128         bnx2x_release_nvram_lock(bp);
1129
1130         return rc;
1131 }
1132
1133 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1134                              int buf_size)
1135 {
1136         int rc;
1137         u32 cmd_flags;
1138         u32 val;
1139         u32 written_so_far;
1140
1141         if (buf_size == 1)      /* ethtool */
1142                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1143
1144         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1145                 DP(BNX2X_MSG_NVM,
1146                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1147                    offset, buf_size);
1148                 return -EINVAL;
1149         }
1150
1151         if (offset + buf_size > bp->common.flash_size) {
1152                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1153                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1154                    offset, buf_size, bp->common.flash_size);
1155                 return -EINVAL;
1156         }
1157
1158         /* request access to nvram interface */
1159         rc = bnx2x_acquire_nvram_lock(bp);
1160         if (rc)
1161                 return rc;
1162
1163         /* enable access to nvram interface */
1164         bnx2x_enable_nvram_access(bp);
1165
1166         written_so_far = 0;
1167         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1168         while ((written_so_far < buf_size) && (rc == 0)) {
1169                 if (written_so_far == (buf_size - sizeof(u32)))
1170                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1171                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1172                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1173                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1174                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1175
1176                 memcpy(&val, data_buf, 4);
1177
1178                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1179
1180                 /* advance to the next dword */
1181                 offset += sizeof(u32);
1182                 data_buf += sizeof(u32);
1183                 written_so_far += sizeof(u32);
1184                 cmd_flags = 0;
1185         }
1186
1187         /* disable access to nvram interface */
1188         bnx2x_disable_nvram_access(bp);
1189         bnx2x_release_nvram_lock(bp);
1190
1191         return rc;
1192 }
1193
1194 static int bnx2x_set_eeprom(struct net_device *dev,
1195                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1196 {
1197         struct bnx2x *bp = netdev_priv(dev);
1198         int port = BP_PORT(bp);
1199         int rc = 0;
1200         u32 ext_phy_config;
1201         if (!netif_running(dev))
1202                 return -EAGAIN;
1203
1204         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1205            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1206            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1207            eeprom->len, eeprom->len);
1208
1209         /* parameters already validated in ethtool_set_eeprom */
1210
1211         /* PHY eeprom can be accessed only by the PMF */
1212         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1213             !bp->port.pmf)
1214                 return -EINVAL;
1215
1216         ext_phy_config =
1217                 SHMEM_RD(bp,
1218                          dev_info.port_hw_config[port].external_phy_config);
1219
1220         if (eeprom->magic == 0x50485950) {
1221                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1222                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1223
1224                 bnx2x_acquire_phy_lock(bp);
1225                 rc |= bnx2x_link_reset(&bp->link_params,
1226                                        &bp->link_vars, 0);
1227                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1228                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1229                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1230                                        MISC_REGISTERS_GPIO_HIGH, port);
1231                 bnx2x_release_phy_lock(bp);
1232                 bnx2x_link_report(bp);
1233
1234         } else if (eeprom->magic == 0x50485952) {
1235                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1236                 if (bp->state == BNX2X_STATE_OPEN) {
1237                         bnx2x_acquire_phy_lock(bp);
1238                         rc |= bnx2x_link_reset(&bp->link_params,
1239                                                &bp->link_vars, 1);
1240
1241                         rc |= bnx2x_phy_init(&bp->link_params,
1242                                              &bp->link_vars);
1243                         bnx2x_release_phy_lock(bp);
1244                         bnx2x_calc_fc_adv(bp);
1245                 }
1246         } else if (eeprom->magic == 0x53985943) {
1247                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1248                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1249                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1250
1251                         /* DSP Remove Download Mode */
1252                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1253                                        MISC_REGISTERS_GPIO_LOW, port);
1254
1255                         bnx2x_acquire_phy_lock(bp);
1256
1257                         bnx2x_sfx7101_sp_sw_reset(bp,
1258                                                 &bp->link_params.phy[EXT_PHY1]);
1259
1260                         /* wait 0.5 sec to allow it to run */
1261                         msleep(500);
1262                         bnx2x_ext_phy_hw_reset(bp, port);
1263                         msleep(500);
1264                         bnx2x_release_phy_lock(bp);
1265                 }
1266         } else
1267                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1268
1269         return rc;
1270 }
1271
1272 static int bnx2x_get_coalesce(struct net_device *dev,
1273                               struct ethtool_coalesce *coal)
1274 {
1275         struct bnx2x *bp = netdev_priv(dev);
1276
1277         memset(coal, 0, sizeof(struct ethtool_coalesce));
1278
1279         coal->rx_coalesce_usecs = bp->rx_ticks;
1280         coal->tx_coalesce_usecs = bp->tx_ticks;
1281
1282         return 0;
1283 }
1284
1285 static int bnx2x_set_coalesce(struct net_device *dev,
1286                               struct ethtool_coalesce *coal)
1287 {
1288         struct bnx2x *bp = netdev_priv(dev);
1289
1290         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1291         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1292                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1293
1294         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1295         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1296                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1297
1298         if (netif_running(dev))
1299                 bnx2x_update_coalesce(bp);
1300
1301         return 0;
1302 }
1303
1304 static void bnx2x_get_ringparam(struct net_device *dev,
1305                                 struct ethtool_ringparam *ering)
1306 {
1307         struct bnx2x *bp = netdev_priv(dev);
1308
1309         ering->rx_max_pending = MAX_RX_AVAIL;
1310         ering->rx_mini_max_pending = 0;
1311         ering->rx_jumbo_max_pending = 0;
1312
1313         if (bp->rx_ring_size)
1314                 ering->rx_pending = bp->rx_ring_size;
1315         else
1316                 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1317                         ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1318                 else
1319                         ering->rx_pending = MAX_RX_AVAIL;
1320
1321         ering->rx_mini_pending = 0;
1322         ering->rx_jumbo_pending = 0;
1323
1324         ering->tx_max_pending = MAX_TX_AVAIL;
1325         ering->tx_pending = bp->tx_ring_size;
1326 }
1327
1328 static int bnx2x_set_ringparam(struct net_device *dev,
1329                                struct ethtool_ringparam *ering)
1330 {
1331         struct bnx2x *bp = netdev_priv(dev);
1332
1333         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1334                 pr_err("Handling parity error recovery. Try again later\n");
1335                 return -EAGAIN;
1336         }
1337
1338         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1339             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1340                                                     MIN_RX_SIZE_TPA)) ||
1341             (ering->tx_pending > MAX_TX_AVAIL) ||
1342             (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1343                 return -EINVAL;
1344
1345         bp->rx_ring_size = ering->rx_pending;
1346         bp->tx_ring_size = ering->tx_pending;
1347
1348         return bnx2x_reload_if_running(dev);
1349 }
1350
1351 static void bnx2x_get_pauseparam(struct net_device *dev,
1352                                  struct ethtool_pauseparam *epause)
1353 {
1354         struct bnx2x *bp = netdev_priv(dev);
1355         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1356         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1357                            BNX2X_FLOW_CTRL_AUTO);
1358
1359         epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1360                             BNX2X_FLOW_CTRL_RX);
1361         epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1362                             BNX2X_FLOW_CTRL_TX);
1363
1364         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1365            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1366            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1367 }
1368
1369 static int bnx2x_set_pauseparam(struct net_device *dev,
1370                                 struct ethtool_pauseparam *epause)
1371 {
1372         struct bnx2x *bp = netdev_priv(dev);
1373         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1374         if (IS_MF(bp))
1375                 return 0;
1376
1377         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1378            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1379            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1380
1381         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1382
1383         if (epause->rx_pause)
1384                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1385
1386         if (epause->tx_pause)
1387                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1388
1389         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1390                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1391
1392         if (epause->autoneg) {
1393                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1394                         DP(NETIF_MSG_LINK, "autoneg not supported\n");
1395                         return -EINVAL;
1396                 }
1397
1398                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1399                         bp->link_params.req_flow_ctrl[cfg_idx] =
1400                                 BNX2X_FLOW_CTRL_AUTO;
1401                 }
1402         }
1403
1404         DP(NETIF_MSG_LINK,
1405            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1406
1407         if (netif_running(dev)) {
1408                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1409                 bnx2x_link_set(bp);
1410         }
1411
1412         return 0;
1413 }
1414
1415 static const struct {
1416         char string[ETH_GSTRING_LEN];
1417 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1418         { "register_test (offline)" },
1419         { "memory_test (offline)" },
1420         { "loopback_test (offline)" },
1421         { "nvram_test (online)" },
1422         { "interrupt_test (online)" },
1423         { "link_test (online)" },
1424         { "idle check (online)" }
1425 };
1426
1427 enum {
1428         BNX2X_CHIP_E1_OFST = 0,
1429         BNX2X_CHIP_E1H_OFST,
1430         BNX2X_CHIP_E2_OFST,
1431         BNX2X_CHIP_E3_OFST,
1432         BNX2X_CHIP_E3B0_OFST,
1433         BNX2X_CHIP_MAX_OFST
1434 };
1435
1436 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
1437 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
1438 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
1439 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
1440 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
1441
1442 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1443 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1444
1445 static int bnx2x_test_registers(struct bnx2x *bp)
1446 {
1447         int idx, i, rc = -ENODEV;
1448         u32 wr_val = 0, hw;
1449         int port = BP_PORT(bp);
1450         static const struct {
1451                 u32 hw;
1452                 u32 offset0;
1453                 u32 offset1;
1454                 u32 mask;
1455         } reg_tbl[] = {
1456 /* 0 */         { BNX2X_CHIP_MASK_ALL,
1457                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1458                 { BNX2X_CHIP_MASK_ALL,
1459                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
1460                 { BNX2X_CHIP_MASK_E1X,
1461                         HC_REG_AGG_INT_0,               4, 0x000003ff },
1462                 { BNX2X_CHIP_MASK_ALL,
1463                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
1464                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1465                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
1466                 { BNX2X_CHIP_MASK_E3B0,
1467                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
1468                 { BNX2X_CHIP_MASK_ALL,
1469                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
1470                 { BNX2X_CHIP_MASK_ALL,
1471                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
1472                 { BNX2X_CHIP_MASK_ALL,
1473                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1474                 { BNX2X_CHIP_MASK_ALL,
1475                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
1476 /* 10 */        { BNX2X_CHIP_MASK_ALL,
1477                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1478                 { BNX2X_CHIP_MASK_ALL,
1479                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
1480                 { BNX2X_CHIP_MASK_ALL,
1481                         QM_REG_CONNNUM_0,               4, 0x000fffff },
1482                 { BNX2X_CHIP_MASK_ALL,
1483                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
1484                 { BNX2X_CHIP_MASK_ALL,
1485                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
1486                 { BNX2X_CHIP_MASK_ALL,
1487                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
1488                 { BNX2X_CHIP_MASK_ALL,
1489                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1490                 { BNX2X_CHIP_MASK_ALL,
1491                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
1492                 { BNX2X_CHIP_MASK_ALL,
1493                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
1494                 { BNX2X_CHIP_MASK_ALL,
1495                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
1496 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1497                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
1498                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1499                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
1500                 { BNX2X_CHIP_MASK_ALL,
1501                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
1502                 { BNX2X_CHIP_MASK_ALL,
1503                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
1504                 { BNX2X_CHIP_MASK_ALL,
1505                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
1506                 { BNX2X_CHIP_MASK_ALL,
1507                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
1508                 { BNX2X_CHIP_MASK_ALL,
1509                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
1510                 { BNX2X_CHIP_MASK_ALL,
1511                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
1512                 { BNX2X_CHIP_MASK_ALL,
1513                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
1514                 { BNX2X_CHIP_MASK_ALL,
1515                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
1516 /* 30 */        { BNX2X_CHIP_MASK_ALL,
1517                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
1518                 { BNX2X_CHIP_MASK_ALL,
1519                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
1520                 { BNX2X_CHIP_MASK_ALL,
1521                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1522                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1523                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
1524                 { BNX2X_CHIP_MASK_ALL,
1525                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1526                 { BNX2X_CHIP_MASK_ALL,
1527                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1528                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1529                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1530                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1531                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
1532
1533                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
1534         };
1535
1536         if (!netif_running(bp->dev))
1537                 return rc;
1538
1539         if (CHIP_IS_E1(bp))
1540                 hw = BNX2X_CHIP_MASK_E1;
1541         else if (CHIP_IS_E1H(bp))
1542                 hw = BNX2X_CHIP_MASK_E1H;
1543         else if (CHIP_IS_E2(bp))
1544                 hw = BNX2X_CHIP_MASK_E2;
1545         else if (CHIP_IS_E3B0(bp))
1546                 hw = BNX2X_CHIP_MASK_E3B0;
1547         else /* e3 A0 */
1548                 hw = BNX2X_CHIP_MASK_E3;
1549
1550         /* Repeat the test twice:
1551            First by writing 0x00000000, second by writing 0xffffffff */
1552         for (idx = 0; idx < 2; idx++) {
1553
1554                 switch (idx) {
1555                 case 0:
1556                         wr_val = 0;
1557                         break;
1558                 case 1:
1559                         wr_val = 0xffffffff;
1560                         break;
1561                 }
1562
1563                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1564                         u32 offset, mask, save_val, val;
1565                         if (!(hw & reg_tbl[i].hw))
1566                                 continue;
1567
1568                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1569                         mask = reg_tbl[i].mask;
1570
1571                         save_val = REG_RD(bp, offset);
1572
1573                         REG_WR(bp, offset, wr_val & mask);
1574
1575                         val = REG_RD(bp, offset);
1576
1577                         /* Restore the original register's value */
1578                         REG_WR(bp, offset, save_val);
1579
1580                         /* verify value is as expected */
1581                         if ((val & mask) != (wr_val & mask)) {
1582                                 DP(NETIF_MSG_HW,
1583                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1584                                    offset, val, wr_val, mask);
1585                                 goto test_reg_exit;
1586                         }
1587                 }
1588         }
1589
1590         rc = 0;
1591
1592 test_reg_exit:
1593         return rc;
1594 }
1595
1596 static int bnx2x_test_memory(struct bnx2x *bp)
1597 {
1598         int i, j, rc = -ENODEV;
1599         u32 val, index;
1600         static const struct {
1601                 u32 offset;
1602                 int size;
1603         } mem_tbl[] = {
1604                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1605                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1606                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1607                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1608                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1609                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1610                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1611
1612                 { 0xffffffff, 0 }
1613         };
1614
1615         static const struct {
1616                 char *name;
1617                 u32 offset;
1618                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
1619         } prty_tbl[] = {
1620                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
1621                         {0x3ffc0, 0,   0, 0} },
1622                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
1623                         {0x2,     0x2, 0, 0} },
1624                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1625                         {0,       0,   0, 0} },
1626                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
1627                         {0x3ffc0, 0,   0, 0} },
1628                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
1629                         {0x3ffc0, 0,   0, 0} },
1630                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
1631                         {0x3ffc1, 0,   0, 0} },
1632
1633                 { NULL, 0xffffffff, {0, 0, 0, 0} }
1634         };
1635
1636         if (!netif_running(bp->dev))
1637                 return rc;
1638
1639         if (CHIP_IS_E1(bp))
1640                 index = BNX2X_CHIP_E1_OFST;
1641         else if (CHIP_IS_E1H(bp))
1642                 index = BNX2X_CHIP_E1H_OFST;
1643         else if (CHIP_IS_E2(bp))
1644                 index = BNX2X_CHIP_E2_OFST;
1645         else /* e3 */
1646                 index = BNX2X_CHIP_E3_OFST;
1647
1648         /* pre-Check the parity status */
1649         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1650                 val = REG_RD(bp, prty_tbl[i].offset);
1651                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1652                         DP(NETIF_MSG_HW,
1653                            "%s is 0x%x\n", prty_tbl[i].name, val);
1654                         goto test_mem_exit;
1655                 }
1656         }
1657
1658         /* Go through all the memories */
1659         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1660                 for (j = 0; j < mem_tbl[i].size; j++)
1661                         REG_RD(bp, mem_tbl[i].offset + j*4);
1662
1663         /* Check the parity status */
1664         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1665                 val = REG_RD(bp, prty_tbl[i].offset);
1666                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1667                         DP(NETIF_MSG_HW,
1668                            "%s is 0x%x\n", prty_tbl[i].name, val);
1669                         goto test_mem_exit;
1670                 }
1671         }
1672
1673         rc = 0;
1674
1675 test_mem_exit:
1676         return rc;
1677 }
1678
1679 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1680 {
1681         int cnt = 1400;
1682
1683         if (link_up) {
1684                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1685                         msleep(20);
1686
1687                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1688                         DP(NETIF_MSG_LINK, "Timeout waiting for link up\n");
1689         }
1690 }
1691
1692 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
1693 {
1694         unsigned int pkt_size, num_pkts, i;
1695         struct sk_buff *skb;
1696         unsigned char *packet;
1697         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1698         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1699         struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
1700         u16 tx_start_idx, tx_idx;
1701         u16 rx_start_idx, rx_idx;
1702         u16 pkt_prod, bd_prod, rx_comp_cons;
1703         struct sw_tx_bd *tx_buf;
1704         struct eth_tx_start_bd *tx_start_bd;
1705         struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
1706         struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
1707         dma_addr_t mapping;
1708         union eth_rx_cqe *cqe;
1709         u8 cqe_fp_flags, cqe_fp_type;
1710         struct sw_rx_bd *rx_buf;
1711         u16 len;
1712         int rc = -ENODEV;
1713
1714         /* check the loopback mode */
1715         switch (loopback_mode) {
1716         case BNX2X_PHY_LOOPBACK:
1717                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1718                         return -EINVAL;
1719                 break;
1720         case BNX2X_MAC_LOOPBACK:
1721                 bp->link_params.loopback_mode = CHIP_IS_E3(bp) ?
1722                                                 LOOPBACK_XMAC : LOOPBACK_BMAC;
1723                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1724                 break;
1725         default:
1726                 return -EINVAL;
1727         }
1728
1729         /* prepare the loopback packet */
1730         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1731                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1732         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1733         if (!skb) {
1734                 rc = -ENOMEM;
1735                 goto test_loopback_exit;
1736         }
1737         packet = skb_put(skb, pkt_size);
1738         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1739         memset(packet + ETH_ALEN, 0, ETH_ALEN);
1740         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1741         for (i = ETH_HLEN; i < pkt_size; i++)
1742                 packet[i] = (unsigned char) (i & 0xff);
1743         mapping = dma_map_single(&bp->pdev->dev, skb->data,
1744                                  skb_headlen(skb), DMA_TO_DEVICE);
1745         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1746                 rc = -ENOMEM;
1747                 dev_kfree_skb(skb);
1748                 BNX2X_ERR("Unable to map SKB\n");
1749                 goto test_loopback_exit;
1750         }
1751
1752         /* send the loopback packet */
1753         num_pkts = 0;
1754         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
1755         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1756
1757         pkt_prod = txdata->tx_pkt_prod++;
1758         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
1759         tx_buf->first_bd = txdata->tx_bd_prod;
1760         tx_buf->skb = skb;
1761         tx_buf->flags = 0;
1762
1763         bd_prod = TX_BD(txdata->tx_bd_prod);
1764         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
1765         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1766         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1767         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1768         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1769         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1770         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1771         SET_FLAG(tx_start_bd->general_data,
1772                  ETH_TX_START_BD_ETH_ADDR_TYPE,
1773                  UNICAST_ADDRESS);
1774         SET_FLAG(tx_start_bd->general_data,
1775                  ETH_TX_START_BD_HDR_NBDS,
1776                  1);
1777
1778         /* turn on parsing and get a BD */
1779         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1780
1781         pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
1782         pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
1783
1784         memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1785         memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1786
1787         wmb();
1788
1789         txdata->tx_db.data.prod += 2;
1790         barrier();
1791         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
1792
1793         mmiowb();
1794         barrier();
1795
1796         num_pkts++;
1797         txdata->tx_bd_prod += 2; /* start + pbd */
1798
1799         udelay(100);
1800
1801         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
1802         if (tx_idx != tx_start_idx + num_pkts)
1803                 goto test_loopback_exit;
1804
1805         /* Unlike HC IGU won't generate an interrupt for status block
1806          * updates that have been performed while interrupts were
1807          * disabled.
1808          */
1809         if (bp->common.int_block == INT_BLOCK_IGU) {
1810                 /* Disable local BHes to prevent a dead-lock situation between
1811                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
1812                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
1813                  */
1814                 local_bh_disable();
1815                 bnx2x_tx_int(bp, txdata);
1816                 local_bh_enable();
1817         }
1818
1819         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1820         if (rx_idx != rx_start_idx + num_pkts)
1821                 goto test_loopback_exit;
1822
1823         rx_comp_cons = le16_to_cpu(fp_rx->rx_comp_cons);
1824         cqe = &fp_rx->rx_comp_ring[RCQ_BD(rx_comp_cons)];
1825         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1826         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1827         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1828                 goto test_loopback_rx_exit;
1829
1830         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1831         if (len != pkt_size)
1832                 goto test_loopback_rx_exit;
1833
1834         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1835         dma_sync_single_for_cpu(&bp->pdev->dev,
1836                                    dma_unmap_addr(rx_buf, mapping),
1837                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
1838         skb = rx_buf->skb;
1839         skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1840         for (i = ETH_HLEN; i < pkt_size; i++)
1841                 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1842                         goto test_loopback_rx_exit;
1843
1844         rc = 0;
1845
1846 test_loopback_rx_exit:
1847
1848         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1849         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1850         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1851         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1852
1853         /* Update producers */
1854         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1855                              fp_rx->rx_sge_prod);
1856
1857 test_loopback_exit:
1858         bp->link_params.loopback_mode = LOOPBACK_NONE;
1859
1860         return rc;
1861 }
1862
1863 static int bnx2x_test_loopback(struct bnx2x *bp)
1864 {
1865         int rc = 0, res;
1866
1867         if (BP_NOMCP(bp))
1868                 return rc;
1869
1870         if (!netif_running(bp->dev))
1871                 return BNX2X_LOOPBACK_FAILED;
1872
1873         bnx2x_netif_stop(bp, 1);
1874         bnx2x_acquire_phy_lock(bp);
1875
1876         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
1877         if (res) {
1878                 DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
1879                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1880         }
1881
1882         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
1883         if (res) {
1884                 DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
1885                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1886         }
1887
1888         bnx2x_release_phy_lock(bp);
1889         bnx2x_netif_start(bp);
1890
1891         return rc;
1892 }
1893
1894 #define CRC32_RESIDUAL                  0xdebb20e3
1895
1896 static int bnx2x_test_nvram(struct bnx2x *bp)
1897 {
1898         static const struct {
1899                 int offset;
1900                 int size;
1901         } nvram_tbl[] = {
1902                 {     0,  0x14 }, /* bootstrap */
1903                 {  0x14,  0xec }, /* dir */
1904                 { 0x100, 0x350 }, /* manuf_info */
1905                 { 0x450,  0xf0 }, /* feature_info */
1906                 { 0x640,  0x64 }, /* upgrade_key_info */
1907                 { 0x708,  0x70 }, /* manuf_key_info */
1908                 {     0,     0 }
1909         };
1910         __be32 buf[0x350 / 4];
1911         u8 *data = (u8 *)buf;
1912         int i, rc;
1913         u32 magic, crc;
1914
1915         if (BP_NOMCP(bp))
1916                 return 0;
1917
1918         rc = bnx2x_nvram_read(bp, 0, data, 4);
1919         if (rc) {
1920                 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1921                 goto test_nvram_exit;
1922         }
1923
1924         magic = be32_to_cpu(buf[0]);
1925         if (magic != 0x669955aa) {
1926                 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1927                 rc = -ENODEV;
1928                 goto test_nvram_exit;
1929         }
1930
1931         for (i = 0; nvram_tbl[i].size; i++) {
1932
1933                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1934                                       nvram_tbl[i].size);
1935                 if (rc) {
1936                         DP(NETIF_MSG_PROBE,
1937                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1938                         goto test_nvram_exit;
1939                 }
1940
1941                 crc = ether_crc_le(nvram_tbl[i].size, data);
1942                 if (crc != CRC32_RESIDUAL) {
1943                         DP(NETIF_MSG_PROBE,
1944                            "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1945                         rc = -ENODEV;
1946                         goto test_nvram_exit;
1947                 }
1948         }
1949
1950 test_nvram_exit:
1951         return rc;
1952 }
1953
1954 /* Send an EMPTY ramrod on the first queue */
1955 static int bnx2x_test_intr(struct bnx2x *bp)
1956 {
1957         struct bnx2x_queue_state_params params = {0};
1958
1959         if (!netif_running(bp->dev))
1960                 return -ENODEV;
1961
1962         params.q_obj = &bp->fp->q_obj;
1963         params.cmd = BNX2X_Q_CMD_EMPTY;
1964
1965         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
1966
1967         return bnx2x_queue_state_change(bp, &params);
1968 }
1969
1970 static void bnx2x_self_test(struct net_device *dev,
1971                             struct ethtool_test *etest, u64 *buf)
1972 {
1973         struct bnx2x *bp = netdev_priv(dev);
1974         u8 is_serdes;
1975         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1976                 pr_err("Handling parity error recovery. Try again later\n");
1977                 etest->flags |= ETH_TEST_FL_FAILED;
1978                 return;
1979         }
1980
1981         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1982
1983         if (!netif_running(dev))
1984                 return;
1985
1986         /* offline tests are not supported in MF mode */
1987         if (IS_MF(bp))
1988                 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1989         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
1990
1991         if (etest->flags & ETH_TEST_FL_OFFLINE) {
1992                 int port = BP_PORT(bp);
1993                 u32 val;
1994                 u8 link_up;
1995
1996                 /* save current value of input enable for TX port IF */
1997                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1998                 /* disable input for TX port IF */
1999                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2000
2001                 link_up = bp->link_vars.link_up;
2002
2003                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2004                 bnx2x_nic_load(bp, LOAD_DIAG);
2005                 /* wait until link state is restored */
2006                 bnx2x_wait_for_link(bp, 1, is_serdes);
2007
2008                 if (bnx2x_test_registers(bp) != 0) {
2009                         buf[0] = 1;
2010                         etest->flags |= ETH_TEST_FL_FAILED;
2011                 }
2012                 if (bnx2x_test_memory(bp) != 0) {
2013                         buf[1] = 1;
2014                         etest->flags |= ETH_TEST_FL_FAILED;
2015                 }
2016
2017                 buf[2] = bnx2x_test_loopback(bp);
2018                 if (buf[2] != 0)
2019                         etest->flags |= ETH_TEST_FL_FAILED;
2020
2021                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2022
2023                 /* restore input for TX port IF */
2024                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2025
2026                 bnx2x_nic_load(bp, LOAD_NORMAL);
2027                 /* wait until link state is restored */
2028                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2029         }
2030         if (bnx2x_test_nvram(bp) != 0) {
2031                 buf[3] = 1;
2032                 etest->flags |= ETH_TEST_FL_FAILED;
2033         }
2034         if (bnx2x_test_intr(bp) != 0) {
2035                 buf[4] = 1;
2036                 etest->flags |= ETH_TEST_FL_FAILED;
2037         }
2038
2039         if (bnx2x_link_test(bp, is_serdes) != 0) {
2040                 buf[5] = 1;
2041                 etest->flags |= ETH_TEST_FL_FAILED;
2042         }
2043
2044 #ifdef BNX2X_EXTRA_DEBUG
2045         bnx2x_panic_dump(bp);
2046 #endif
2047 }
2048
2049 #define IS_PORT_STAT(i) \
2050         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2051 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2052 #define IS_MF_MODE_STAT(bp) \
2053                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2054
2055 /* ethtool statistics are displayed for all regular ethernet queues and the
2056  * fcoe L2 queue if not disabled
2057  */
2058 static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
2059 {
2060         return BNX2X_NUM_ETH_QUEUES(bp);
2061 }
2062
2063 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2064 {
2065         struct bnx2x *bp = netdev_priv(dev);
2066         int i, num_stats;
2067
2068         switch (stringset) {
2069         case ETH_SS_STATS:
2070                 if (is_multi(bp)) {
2071                         num_stats = bnx2x_num_stat_queues(bp) *
2072                                 BNX2X_NUM_Q_STATS;
2073                         if (!IS_MF_MODE_STAT(bp))
2074                                 num_stats += BNX2X_NUM_STATS;
2075                 } else {
2076                         if (IS_MF_MODE_STAT(bp)) {
2077                                 num_stats = 0;
2078                                 for (i = 0; i < BNX2X_NUM_STATS; i++)
2079                                         if (IS_FUNC_STAT(i))
2080                                                 num_stats++;
2081                         } else
2082                                 num_stats = BNX2X_NUM_STATS;
2083                 }
2084                 return num_stats;
2085
2086         case ETH_SS_TEST:
2087                 return BNX2X_NUM_TESTS;
2088
2089         default:
2090                 return -EINVAL;
2091         }
2092 }
2093
2094 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2095 {
2096         struct bnx2x *bp = netdev_priv(dev);
2097         int i, j, k;
2098         char queue_name[MAX_QUEUE_NAME_LEN+1];
2099
2100         switch (stringset) {
2101         case ETH_SS_STATS:
2102                 if (is_multi(bp)) {
2103                         k = 0;
2104                         for_each_eth_queue(bp, i) {
2105                                 memset(queue_name, 0, sizeof(queue_name));
2106                                 sprintf(queue_name, "%d", i);
2107                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2108                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2109                                                 ETH_GSTRING_LEN,
2110                                                 bnx2x_q_stats_arr[j].string,
2111                                                 queue_name);
2112                                 k += BNX2X_NUM_Q_STATS;
2113                         }
2114                         if (IS_MF_MODE_STAT(bp))
2115                                 break;
2116                         for (j = 0; j < BNX2X_NUM_STATS; j++)
2117                                 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2118                                        bnx2x_stats_arr[j].string);
2119                 } else {
2120                         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2121                                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2122                                         continue;
2123                                 strcpy(buf + j*ETH_GSTRING_LEN,
2124                                        bnx2x_stats_arr[i].string);
2125                                 j++;
2126                         }
2127                 }
2128                 break;
2129
2130         case ETH_SS_TEST:
2131                 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2132                 break;
2133         }
2134 }
2135
2136 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2137                                     struct ethtool_stats *stats, u64 *buf)
2138 {
2139         struct bnx2x *bp = netdev_priv(dev);
2140         u32 *hw_stats, *offset;
2141         int i, j, k;
2142
2143         if (is_multi(bp)) {
2144                 k = 0;
2145                 for_each_eth_queue(bp, i) {
2146                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2147                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2148                                 if (bnx2x_q_stats_arr[j].size == 0) {
2149                                         /* skip this counter */
2150                                         buf[k + j] = 0;
2151                                         continue;
2152                                 }
2153                                 offset = (hw_stats +
2154                                           bnx2x_q_stats_arr[j].offset);
2155                                 if (bnx2x_q_stats_arr[j].size == 4) {
2156                                         /* 4-byte counter */
2157                                         buf[k + j] = (u64) *offset;
2158                                         continue;
2159                                 }
2160                                 /* 8-byte counter */
2161                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2162                         }
2163                         k += BNX2X_NUM_Q_STATS;
2164                 }
2165                 if (IS_MF_MODE_STAT(bp))
2166                         return;
2167                 hw_stats = (u32 *)&bp->eth_stats;
2168                 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2169                         if (bnx2x_stats_arr[j].size == 0) {
2170                                 /* skip this counter */
2171                                 buf[k + j] = 0;
2172                                 continue;
2173                         }
2174                         offset = (hw_stats + bnx2x_stats_arr[j].offset);
2175                         if (bnx2x_stats_arr[j].size == 4) {
2176                                 /* 4-byte counter */
2177                                 buf[k + j] = (u64) *offset;
2178                                 continue;
2179                         }
2180                         /* 8-byte counter */
2181                         buf[k + j] = HILO_U64(*offset, *(offset + 1));
2182                 }
2183         } else {
2184                 hw_stats = (u32 *)&bp->eth_stats;
2185                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2186                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2187                                 continue;
2188                         if (bnx2x_stats_arr[i].size == 0) {
2189                                 /* skip this counter */
2190                                 buf[j] = 0;
2191                                 j++;
2192                                 continue;
2193                         }
2194                         offset = (hw_stats + bnx2x_stats_arr[i].offset);
2195                         if (bnx2x_stats_arr[i].size == 4) {
2196                                 /* 4-byte counter */
2197                                 buf[j] = (u64) *offset;
2198                                 j++;
2199                                 continue;
2200                         }
2201                         /* 8-byte counter */
2202                         buf[j] = HILO_U64(*offset, *(offset + 1));
2203                         j++;
2204                 }
2205         }
2206 }
2207
2208 static int bnx2x_set_phys_id(struct net_device *dev,
2209                              enum ethtool_phys_id_state state)
2210 {
2211         struct bnx2x *bp = netdev_priv(dev);
2212
2213         if (!netif_running(dev))
2214                 return -EAGAIN;
2215
2216         if (!bp->port.pmf)
2217                 return -EOPNOTSUPP;
2218
2219         switch (state) {
2220         case ETHTOOL_ID_ACTIVE:
2221                 return 1;       /* cycle on/off once per second */
2222
2223         case ETHTOOL_ID_ON:
2224                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2225                               LED_MODE_ON, SPEED_1000);
2226                 break;
2227
2228         case ETHTOOL_ID_OFF:
2229                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2230                               LED_MODE_FRONT_PANEL_OFF, 0);
2231
2232                 break;
2233
2234         case ETHTOOL_ID_INACTIVE:
2235                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2236                               LED_MODE_OPER,
2237                               bp->link_vars.line_speed);
2238         }
2239
2240         return 0;
2241 }
2242
2243 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2244                            u32 *rules __always_unused)
2245 {
2246         struct bnx2x *bp = netdev_priv(dev);
2247
2248         switch (info->cmd) {
2249         case ETHTOOL_GRXRINGS:
2250                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2251                 return 0;
2252
2253         default:
2254                 return -EOPNOTSUPP;
2255         }
2256 }
2257
2258 static int bnx2x_get_rxfh_indir(struct net_device *dev,
2259                                 struct ethtool_rxfh_indir *indir)
2260 {
2261         struct bnx2x *bp = netdev_priv(dev);
2262         size_t copy_size =
2263                 min_t(size_t, indir->size, T_ETH_INDIRECTION_TABLE_SIZE);
2264         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2265         size_t i;
2266
2267         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2268                 return -EOPNOTSUPP;
2269
2270         /* Get the current configuration of the RSS indirection table */
2271         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2272
2273         /*
2274          * We can't use a memcpy() as an internal storage of an
2275          * indirection table is a u8 array while indir->ring_index
2276          * points to an array of u32.
2277          *
2278          * Indirection table contains the FW Client IDs, so we need to
2279          * align the returned table to the Client ID of the leading RSS
2280          * queue.
2281          */
2282         for (i = 0; i < copy_size; i++)
2283                 indir->ring_index[i] = ind_table[i] - bp->fp->cl_id;
2284
2285         indir->size = T_ETH_INDIRECTION_TABLE_SIZE;
2286
2287         return 0;
2288 }
2289
2290 static int bnx2x_set_rxfh_indir(struct net_device *dev,
2291                                 const struct ethtool_rxfh_indir *indir)
2292 {
2293         struct bnx2x *bp = netdev_priv(dev);
2294         size_t i;
2295         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2296         u32 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
2297
2298         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2299                 return -EOPNOTSUPP;
2300
2301         /* validate the size */
2302         if (indir->size != T_ETH_INDIRECTION_TABLE_SIZE)
2303                 return -EINVAL;
2304
2305         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2306                 /* validate the indices */
2307                 if (indir->ring_index[i] >= num_eth_queues)
2308                         return -EINVAL;
2309                 /*
2310                  * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2311                  * as an internal storage of an indirection table is a u8 array
2312                  * while indir->ring_index points to an array of u32.
2313                  *
2314                  * Indirection table contains the FW Client IDs, so we need to
2315                  * align the received table to the Client ID of the leading RSS
2316                  * queue
2317                  */
2318                 ind_table[i] = indir->ring_index[i] + bp->fp->cl_id;
2319         }
2320
2321         return bnx2x_config_rss_pf(bp, ind_table, false);
2322 }
2323
2324 static const struct ethtool_ops bnx2x_ethtool_ops = {
2325         .get_settings           = bnx2x_get_settings,
2326         .set_settings           = bnx2x_set_settings,
2327         .get_drvinfo            = bnx2x_get_drvinfo,
2328         .get_regs_len           = bnx2x_get_regs_len,
2329         .get_regs               = bnx2x_get_regs,
2330         .get_wol                = bnx2x_get_wol,
2331         .set_wol                = bnx2x_set_wol,
2332         .get_msglevel           = bnx2x_get_msglevel,
2333         .set_msglevel           = bnx2x_set_msglevel,
2334         .nway_reset             = bnx2x_nway_reset,
2335         .get_link               = bnx2x_get_link,
2336         .get_eeprom_len         = bnx2x_get_eeprom_len,
2337         .get_eeprom             = bnx2x_get_eeprom,
2338         .set_eeprom             = bnx2x_set_eeprom,
2339         .get_coalesce           = bnx2x_get_coalesce,
2340         .set_coalesce           = bnx2x_set_coalesce,
2341         .get_ringparam          = bnx2x_get_ringparam,
2342         .set_ringparam          = bnx2x_set_ringparam,
2343         .get_pauseparam         = bnx2x_get_pauseparam,
2344         .set_pauseparam         = bnx2x_set_pauseparam,
2345         .self_test              = bnx2x_self_test,
2346         .get_sset_count         = bnx2x_get_sset_count,
2347         .get_strings            = bnx2x_get_strings,
2348         .set_phys_id            = bnx2x_set_phys_id,
2349         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2350         .get_rxnfc              = bnx2x_get_rxnfc,
2351         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
2352         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
2353 };
2354
2355 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2356 {
2357         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2358 }