drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2011 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/ethtool.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/types.h>
  23 #include <linux/sched.h>
  24 #include <linux/crc32.h>
  25
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29 #include "bnx2x_dump.h"
  30 #include "bnx2x_init.h"
  31 #include "bnx2x_sp.h"
  32
  33 /* Note: in the format strings below %s is replaced by the queue-name which is
  34  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  35  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  36  */
  37 #define MAX_QUEUE_NAME_LEN      4
  38 static const struct {
  39         long offset;
  40         int size;
  41         char string[ETH_GSTRING_LEN];
  42 } bnx2x_q_stats_arr[] = {
  43 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  44         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  45                                                 8, "[%s]: rx_ucast_packets" },
  46         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  47                                                 8, "[%s]: rx_mcast_packets" },
  48         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  49                                                 8, "[%s]: rx_bcast_packets" },
  50         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  51         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  52                                          4, "[%s]: rx_phy_ip_err_discards"},
  53         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  54                                          4, "[%s]: rx_skb_alloc_discard" },
  55         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  56
  57         { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  58 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  59                                                 8, "[%s]: tx_ucast_packets" },
  60         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  61                                                 8, "[%s]: tx_mcast_packets" },
  62         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  63                                                 8, "[%s]: tx_bcast_packets" },
  64         { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
  65                                                 8, "[%s]: tpa_aggregations" },
  66         { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
  67                                         8, "[%s]: tpa_aggregated_frames"},
  68         { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
  69 };
  70
  71 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  72
  73 static const struct {
  74         long offset;
  75         int size;
  76         u32 flags;
  77 #define STATS_FLAGS_PORT                1
  78 #define STATS_FLAGS_FUNC                2
  79 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  80         char string[ETH_GSTRING_LEN];
  81 } bnx2x_stats_arr[] = {
  82 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  83                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  84         { STATS_OFFSET32(error_bytes_received_hi),
  85                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  86         { STATS_OFFSET32(total_unicast_packets_received_hi),
  87                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  88         { STATS_OFFSET32(total_multicast_packets_received_hi),
  89                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  90         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  91                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  92         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  93                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  94         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  95                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  96         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  97                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  98         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  99                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
 100 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
 101                                 8, STATS_FLAGS_PORT, "rx_fragments" },
 102         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
 103                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
 104         { STATS_OFFSET32(no_buff_discard_hi),
 105                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 106         { STATS_OFFSET32(mac_filter_discard),
 107                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 108         { STATS_OFFSET32(mf_tag_discard),
 109                                 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
 110         { STATS_OFFSET32(brb_drop_hi),
 111                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 112         { STATS_OFFSET32(brb_truncate_hi),
 113                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 114         { STATS_OFFSET32(pause_frames_received_hi),
 115                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 116         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 117                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 118         { STATS_OFFSET32(nig_timer_max),
 119                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 120 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 121                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 122         { STATS_OFFSET32(rx_skb_alloc_failed),
 123                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 124         { STATS_OFFSET32(hw_csum_err),
 125                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 126
 127         { STATS_OFFSET32(total_bytes_transmitted_hi),
 128                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 129         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 130                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 131         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 132                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 133         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 134                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 135         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 136                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 137         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 138                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 139         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 140                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 141 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 142                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 143         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 144                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 145         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 146                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 147         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 148                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 149         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 150                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 151         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 152                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 153         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 154                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 155         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 156                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 157         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 158                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 159         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 160                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 161 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 162                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 163         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 164                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 165         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 166                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 167         { STATS_OFFSET32(pause_frames_sent_hi),
 168                                 8, STATS_FLAGS_PORT, "tx_pause_frames" },
 169         { STATS_OFFSET32(total_tpa_aggregations_hi),
 170                         8, STATS_FLAGS_FUNC, "tpa_aggregations" },
 171         { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
 172                         8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
 173         { STATS_OFFSET32(total_tpa_bytes_hi),
 174                         8, STATS_FLAGS_FUNC, "tpa_bytes"}
 175 };
 176
 177 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 178 static int bnx2x_get_port_type(struct bnx2x *bp)
 179 {
 180         int port_type;
 181         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 182         switch (bp->link_params.phy[phy_idx].media_type) {
 183         case ETH_PHY_SFP_FIBER:
 184         case ETH_PHY_XFP_FIBER:
 185         case ETH_PHY_KR:
 186         case ETH_PHY_CX4:
 187                 port_type = PORT_FIBRE;
 188                 break;
 189         case ETH_PHY_DA_TWINAX:
 190                 port_type = PORT_DA;
 191                 break;
 192         case ETH_PHY_BASE_T:
 193                 port_type = PORT_TP;
 194                 break;
 195         case ETH_PHY_NOT_PRESENT:
 196                 port_type = PORT_NONE;
 197                 break;
 198         case ETH_PHY_UNSPECIFIED:
 199         default:
 200                 port_type = PORT_OTHER;
 201                 break;
 202         }
 203         return port_type;
 204 }
 205
 206 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 207 {
 208         struct bnx2x *bp = netdev_priv(dev);
 209         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 210
 211         /* Dual Media boards present all available port types */
 212         cmd->supported = bp->port.supported[cfg_idx] |
 213                 (bp->port.supported[cfg_idx ^ 1] &
 214                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 215         cmd->advertising = bp->port.advertising[cfg_idx];
 216
 217         if ((bp->state == BNX2X_STATE_OPEN) &&
 218             !(bp->flags & MF_FUNC_DIS) &&
 219             (bp->link_vars.link_up)) {
 220                 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 221                 cmd->duplex = bp->link_vars.duplex;
 222         } else {
 223                 ethtool_cmd_speed_set(
 224                         cmd, bp->link_params.req_line_speed[cfg_idx]);
 225                 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
 226         }
 227
 228         if (IS_MF(bp))
 229                 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 230
 231         cmd->port = bnx2x_get_port_type(bp);
 232
 233         cmd->phy_address = bp->mdio.prtad;
 234         cmd->transceiver = XCVR_INTERNAL;
 235
 236         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 237                 cmd->autoneg = AUTONEG_ENABLE;
 238         else
 239                 cmd->autoneg = AUTONEG_DISABLE;
 240
 241         cmd->maxtxpkt = 0;
 242         cmd->maxrxpkt = 0;
 243
 244         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 245            "  supported 0x%x  advertising 0x%x  speed %u\n"
 246            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 247            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 248            cmd->cmd, cmd->supported, cmd->advertising,
 249            ethtool_cmd_speed(cmd),
 250            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 251            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 252
 253         return 0;
 254 }
 255
 256 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 257 {
 258         struct bnx2x *bp = netdev_priv(dev);
 259         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 260         u32 speed;
 261
 262         if (IS_MF_SD(bp))
 263                 return 0;
 264
 265         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 266            "  supported 0x%x  advertising 0x%x  speed %u\n"
 267            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 268            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 269            cmd->cmd, cmd->supported, cmd->advertising,
 270            ethtool_cmd_speed(cmd),
 271            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 272            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 273
 274         speed = ethtool_cmd_speed(cmd);
 275
 276         if (IS_MF_SI(bp)) {
 277                 u32 part;
 278                 u32 line_speed = bp->link_vars.line_speed;
 279
 280                 /* use 10G if no link detected */
 281                 if (!line_speed)
 282                         line_speed = 10000;
 283
 284                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 285                         BNX2X_DEV_INFO("To set speed BC %X or higher "
 286                                        "is required, please upgrade BC\n",
 287                                        REQ_BC_VER_4_SET_MF_BW);
 288                         return -EINVAL;
 289                 }
 290
 291                 part = (speed * 100) / line_speed;
 292
 293                 if (line_speed < speed || !part) {
 294                         BNX2X_DEV_INFO("Speed setting should be in a range "
 295                                        "from 1%% to 100%% "
 296                                        "of actual line speed\n");
 297                         return -EINVAL;
 298                 }
 299
 300                 if (bp->state != BNX2X_STATE_OPEN)
 301                         /* store value for following "load" */
 302                         bp->pending_max = part;
 303                 else
 304                         bnx2x_update_max_mf_config(bp, part);
 305
 306                 return 0;
 307         }
 308
 309         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 310         old_multi_phy_config = bp->link_params.multi_phy_config;
 311         switch (cmd->port) {
 312         case PORT_TP:
 313                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 314                         break; /* no port change */
 315
 316                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 317                       bp->port.supported[1] & SUPPORTED_TP)) {
 318                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 319                         return -EINVAL;
 320                 }
 321                 bp->link_params.multi_phy_config &=
 322                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 323                 if (bp->link_params.multi_phy_config &
 324                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 325                         bp->link_params.multi_phy_config |=
 326                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 327                 else
 328                         bp->link_params.multi_phy_config |=
 329                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 330                 break;
 331         case PORT_FIBRE:
 332                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 333                         break; /* no port change */
 334
 335                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 336                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 337                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 338                         return -EINVAL;
 339                 }
 340                 bp->link_params.multi_phy_config &=
 341                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 342                 if (bp->link_params.multi_phy_config &
 343                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 344                         bp->link_params.multi_phy_config |=
 345                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 346                 else
 347                         bp->link_params.multi_phy_config |=
 348                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 349                 break;
 350         default:
 351                 DP(NETIF_MSG_LINK, "Unsupported port type\n");
 352                 return -EINVAL;
 353         }
 354         /* Save new config in case command complete successuly */
 355         new_multi_phy_config = bp->link_params.multi_phy_config;
 356         /* Get the new cfg_idx */
 357         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 358         /* Restore old config in case command failed */
 359         bp->link_params.multi_phy_config = old_multi_phy_config;
 360         DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
 361
 362         if (cmd->autoneg == AUTONEG_ENABLE) {
 363                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 364                         DP(NETIF_MSG_LINK, "Autoneg not supported\n");
 365                         return -EINVAL;
 366                 }
 367
 368                 /* advertise the requested speed and duplex if supported */
 369                 if (cmd->advertising & ~(bp->port.supported[cfg_idx])) {
 370                         DP(NETIF_MSG_LINK, "Advertisement parameters "
 371                                            "are not supported\n");
 372                         return -EINVAL;
 373                 }
 374
 375                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 376                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 377                 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
 378                                          cmd->advertising);
 379                 if (cmd->advertising) {
 380
 381                         bp->link_params.speed_cap_mask[cfg_idx] = 0;
 382                         if (cmd->advertising & ADVERTISED_10baseT_Half) {
 383                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 384                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
 385                         }
 386                         if (cmd->advertising & ADVERTISED_10baseT_Full)
 387                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 388                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
 389
 390                         if (cmd->advertising & ADVERTISED_100baseT_Full)
 391                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 392                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
 393
 394                         if (cmd->advertising & ADVERTISED_100baseT_Half) {
 395                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 396                                      PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
 397                         }
 398                         if (cmd->advertising & ADVERTISED_1000baseT_Half) {
 399                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 400                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 401                         }
 402                         if (cmd->advertising & (ADVERTISED_1000baseT_Full |
 403                                                 ADVERTISED_1000baseKX_Full))
 404                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 405                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
 406
 407                         if (cmd->advertising & (ADVERTISED_10000baseT_Full |
 408                                                 ADVERTISED_10000baseKX4_Full |
 409                                                 ADVERTISED_10000baseKR_Full))
 410                                 bp->link_params.speed_cap_mask[cfg_idx] |=
 411                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
 412                 }
 413         } else { /* forced speed */
 414                 /* advertise the requested speed and duplex if supported */
 415                 switch (speed) {
 416                 case SPEED_10:
 417                         if (cmd->duplex == DUPLEX_FULL) {
 418                                 if (!(bp->port.supported[cfg_idx] &
 419                                       SUPPORTED_10baseT_Full)) {
 420                                         DP(NETIF_MSG_LINK,
 421                                            "10M full not supported\n");
 422                                         return -EINVAL;
 423                                 }
 424
 425                                 advertising = (ADVERTISED_10baseT_Full |
 426                                                ADVERTISED_TP);
 427                         } else {
 428                                 if (!(bp->port.supported[cfg_idx] &
 429                                       SUPPORTED_10baseT_Half)) {
 430                                         DP(NETIF_MSG_LINK,
 431                                            "10M half not supported\n");
 432                                         return -EINVAL;
 433                                 }
 434
 435                                 advertising = (ADVERTISED_10baseT_Half |
 436                                                ADVERTISED_TP);
 437                         }
 438                         break;
 439
 440                 case SPEED_100:
 441                         if (cmd->duplex == DUPLEX_FULL) {
 442                                 if (!(bp->port.supported[cfg_idx] &
 443                                                 SUPPORTED_100baseT_Full)) {
 444                                         DP(NETIF_MSG_LINK,
 445                                            "100M full not supported\n");
 446                                         return -EINVAL;
 447                                 }
 448
 449                                 advertising = (ADVERTISED_100baseT_Full |
 450                                                ADVERTISED_TP);
 451                         } else {
 452                                 if (!(bp->port.supported[cfg_idx] &
 453                                                 SUPPORTED_100baseT_Half)) {
 454                                         DP(NETIF_MSG_LINK,
 455                                            "100M half not supported\n");
 456                                         return -EINVAL;
 457                                 }
 458
 459                                 advertising = (ADVERTISED_100baseT_Half |
 460                                                ADVERTISED_TP);
 461                         }
 462                         break;
 463
 464                 case SPEED_1000:
 465                         if (cmd->duplex != DUPLEX_FULL) {
 466                                 DP(NETIF_MSG_LINK, "1G half not supported\n");
 467                                 return -EINVAL;
 468                         }
 469
 470                         if (!(bp->port.supported[cfg_idx] &
 471                               SUPPORTED_1000baseT_Full)) {
 472                                 DP(NETIF_MSG_LINK, "1G full not supported\n");
 473                                 return -EINVAL;
 474                         }
 475
 476                         advertising = (ADVERTISED_1000baseT_Full |
 477                                        ADVERTISED_TP);
 478                         break;
 479
 480                 case SPEED_2500:
 481                         if (cmd->duplex != DUPLEX_FULL) {
 482                                 DP(NETIF_MSG_LINK,
 483                                    "2.5G half not supported\n");
 484                                 return -EINVAL;
 485                         }
 486
 487                         if (!(bp->port.supported[cfg_idx]
 488                               & SUPPORTED_2500baseX_Full)) {
 489                                 DP(NETIF_MSG_LINK,
 490                                    "2.5G full not supported\n");
 491                                 return -EINVAL;
 492                         }
 493
 494                         advertising = (ADVERTISED_2500baseX_Full |
 495                                        ADVERTISED_TP);
 496                         break;
 497
 498                 case SPEED_10000:
 499                         if (cmd->duplex != DUPLEX_FULL) {
 500                                 DP(NETIF_MSG_LINK, "10G half not supported\n");
 501                                 return -EINVAL;
 502                         }
 503
 504                         if (!(bp->port.supported[cfg_idx]
 505                               & SUPPORTED_10000baseT_Full)) {
 506                                 DP(NETIF_MSG_LINK, "10G full not supported\n");
 507                                 return -EINVAL;
 508                         }
 509
 510                         advertising = (ADVERTISED_10000baseT_Full |
 511                                        ADVERTISED_FIBRE);
 512                         break;
 513
 514                 default:
 515                         DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
 516                         return -EINVAL;
 517                 }
 518
 519                 bp->link_params.req_line_speed[cfg_idx] = speed;
 520                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 521                 bp->port.advertising[cfg_idx] = advertising;
 522         }
 523
 524         DP(NETIF_MSG_LINK, "req_line_speed %d\n"
 525            "  req_duplex %d  advertising 0x%x\n",
 526            bp->link_params.req_line_speed[cfg_idx],
 527            bp->link_params.req_duplex[cfg_idx],
 528            bp->port.advertising[cfg_idx]);
 529
 530         /* Set new config */
 531         bp->link_params.multi_phy_config = new_multi_phy_config;
 532         if (netif_running(dev)) {
 533                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 534                 bnx2x_link_set(bp);
 535         }
 536
 537         return 0;
 538 }
 539
 540 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 541 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 542 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 543 #define IS_E3_ONLINE(info)      (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
 544 #define IS_E3B0_ONLINE(info)    (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
 545
 546 static inline bool bnx2x_is_reg_online(struct bnx2x *bp,
 547                                        const struct reg_addr *reg_info)
 548 {
 549         if (CHIP_IS_E1(bp))
 550                 return IS_E1_ONLINE(reg_info->info);
 551         else if (CHIP_IS_E1H(bp))
 552                 return IS_E1H_ONLINE(reg_info->info);
 553         else if (CHIP_IS_E2(bp))
 554                 return IS_E2_ONLINE(reg_info->info);
 555         else if (CHIP_IS_E3A0(bp))
 556                 return IS_E3_ONLINE(reg_info->info);
 557         else if (CHIP_IS_E3B0(bp))
 558                 return IS_E3B0_ONLINE(reg_info->info);
 559         else
 560                 return false;
 561 }
 562
 563 /******* Paged registers info selectors ********/
 564 static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
 565 {
 566         if (CHIP_IS_E2(bp))
 567                 return page_vals_e2;
 568         else if (CHIP_IS_E3(bp))
 569                 return page_vals_e3;
 570         else
 571                 return NULL;
 572 }
 573
 574 static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
 575 {
 576         if (CHIP_IS_E2(bp))
 577                 return PAGE_MODE_VALUES_E2;
 578         else if (CHIP_IS_E3(bp))
 579                 return PAGE_MODE_VALUES_E3;
 580         else
 581                 return 0;
 582 }
 583
 584 static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
 585 {
 586         if (CHIP_IS_E2(bp))
 587                 return page_write_regs_e2;
 588         else if (CHIP_IS_E3(bp))
 589                 return page_write_regs_e3;
 590         else
 591                 return NULL;
 592 }
 593
 594 static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
 595 {
 596         if (CHIP_IS_E2(bp))
 597                 return PAGE_WRITE_REGS_E2;
 598         else if (CHIP_IS_E3(bp))
 599                 return PAGE_WRITE_REGS_E3;
 600         else
 601                 return 0;
 602 }
 603
 604 static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
 605 {
 606         if (CHIP_IS_E2(bp))
 607                 return page_read_regs_e2;
 608         else if (CHIP_IS_E3(bp))
 609                 return page_read_regs_e3;
 610         else
 611                 return NULL;
 612 }
 613
 614 static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
 615 {
 616         if (CHIP_IS_E2(bp))
 617                 return PAGE_READ_REGS_E2;
 618         else if (CHIP_IS_E3(bp))
 619                 return PAGE_READ_REGS_E3;
 620         else
 621                 return 0;
 622 }
 623
 624 static inline int __bnx2x_get_regs_len(struct bnx2x *bp)
 625 {
 626         int num_pages = __bnx2x_get_page_reg_num(bp);
 627         int page_write_num = __bnx2x_get_page_write_num(bp);
 628         const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
 629         int page_read_num = __bnx2x_get_page_read_num(bp);
 630         int regdump_len = 0;
 631         int i, j, k;
 632
 633         for (i = 0; i < REGS_COUNT; i++)
 634                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 635                         regdump_len += reg_addrs[i].size;
 636
 637         for (i = 0; i < num_pages; i++)
 638                 for (j = 0; j < page_write_num; j++)
 639                         for (k = 0; k < page_read_num; k++)
 640                                 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
 641                                         regdump_len += page_read_addr[k].size;
 642
 643         return regdump_len;
 644 }
 645
 646 static int bnx2x_get_regs_len(struct net_device *dev)
 647 {
 648         struct bnx2x *bp = netdev_priv(dev);
 649         int regdump_len = 0;
 650
 651         regdump_len = __bnx2x_get_regs_len(bp);
 652         regdump_len *= 4;
 653         regdump_len += sizeof(struct dump_hdr);
 654
 655         return regdump_len;
 656 }
 657
 658 /**
 659  * bnx2x_read_pages_regs - read "paged" registers
 660  *
 661  * @bp          device handle
 662  * @p           output buffer
 663  *
 664  * Reads "paged" memories: memories that may only be read by first writing to a
 665  * specific address ("write address") and then reading from a specific address
 666  * ("read address"). There may be more than one write address per "page" and
 667  * more than one read address per write address.
 668  */
 669 static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
 670 {
 671         u32 i, j, k, n;
 672         /* addresses of the paged registers */
 673         const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
 674         /* number of paged registers */
 675         int num_pages = __bnx2x_get_page_reg_num(bp);
 676         /* write addresses */
 677         const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
 678         /* number of write addresses */
 679         int write_num = __bnx2x_get_page_write_num(bp);
 680         /* read addresses info */
 681         const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
 682         /* number of read addresses */
 683         int read_num = __bnx2x_get_page_read_num(bp);
 684
 685         for (i = 0; i < num_pages; i++) {
 686                 for (j = 0; j < write_num; j++) {
 687                         REG_WR(bp, write_addr[j], page_addr[i]);
 688                         for (k = 0; k < read_num; k++)
 689                                 if (bnx2x_is_reg_online(bp, &read_addr[k]))
 690                                         for (n = 0; n <
 691                                               read_addr[k].size; n++)
 692                                                 *p++ = REG_RD(bp,
 693                                                        read_addr[k].addr + n*4);
 694                 }
 695         }
 696 }
 697
 698 static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
 699 {
 700         u32 i, j;
 701
 702         /* Read the regular registers */
 703         for (i = 0; i < REGS_COUNT; i++)
 704                 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
 705                         for (j = 0; j < reg_addrs[i].size; j++)
 706                                 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
 707
 708         /* Read "paged" registes */
 709         bnx2x_read_pages_regs(bp, p);
 710 }
 711
 712 static void bnx2x_get_regs(struct net_device *dev,
 713                            struct ethtool_regs *regs, void *_p)
 714 {
 715         u32 *p = _p;
 716         struct bnx2x *bp = netdev_priv(dev);
 717         struct dump_hdr dump_hdr = {0};
 718
 719         regs->version = 0;
 720         memset(p, 0, regs->len);
 721
 722         if (!netif_running(bp->dev))
 723                 return;
 724
 725         /* Disable parity attentions as long as following dump may
 726          * cause false alarms by reading never written registers. We
 727          * will re-enable parity attentions right after the dump.
 728          */
 729         bnx2x_disable_blocks_parity(bp);
 730
 731         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 732         dump_hdr.dump_sign = dump_sign_all;
 733         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 734         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 735         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 736         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 737
 738         if (CHIP_IS_E1(bp))
 739                 dump_hdr.info = RI_E1_ONLINE;
 740         else if (CHIP_IS_E1H(bp))
 741                 dump_hdr.info = RI_E1H_ONLINE;
 742         else if (!CHIP_IS_E1x(bp))
 743                 dump_hdr.info = RI_E2_ONLINE |
 744                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 745
 746         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 747         p += dump_hdr.hdr_size + 1;
 748
 749         /* Actually read the registers */
 750         __bnx2x_get_regs(bp, p);
 751
 752         /* Re-enable parity attentions */
 753         bnx2x_clear_blocks_parity(bp);
 754         bnx2x_enable_blocks_parity(bp);
 755 }
 756
 757 static void bnx2x_get_drvinfo(struct net_device *dev,
 758                               struct ethtool_drvinfo *info)
 759 {
 760         struct bnx2x *bp = netdev_priv(dev);
 761         u8 phy_fw_ver[PHY_FW_VER_LEN];
 762
 763         strcpy(info->driver, DRV_MODULE_NAME);
 764         strcpy(info->version, DRV_MODULE_VERSION);
 765
 766         phy_fw_ver[0] = '\0';
 767         if (bp->port.pmf) {
 768                 bnx2x_acquire_phy_lock(bp);
 769                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
 770                                              (bp->state != BNX2X_STATE_CLOSED),
 771                                              phy_fw_ver, PHY_FW_VER_LEN);
 772                 bnx2x_release_phy_lock(bp);
 773         }
 774
 775         strncpy(info->fw_version, bp->fw_ver, 32);
 776         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 777                  "bc %d.%d.%d%s%s",
 778                  (bp->common.bc_ver & 0xff0000) >> 16,
 779                  (bp->common.bc_ver & 0xff00) >> 8,
 780                  (bp->common.bc_ver & 0xff),
 781                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 782         strcpy(info->bus_info, pci_name(bp->pdev));
 783         info->n_stats = BNX2X_NUM_STATS;
 784         info->testinfo_len = BNX2X_NUM_TESTS;
 785         info->eedump_len = bp->common.flash_size;
 786         info->regdump_len = bnx2x_get_regs_len(dev);
 787 }
 788
 789 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 790 {
 791         struct bnx2x *bp = netdev_priv(dev);
 792
 793         if (bp->flags & NO_WOL_FLAG) {
 794                 wol->supported = 0;
 795                 wol->wolopts = 0;
 796         } else {
 797                 wol->supported = WAKE_MAGIC;
 798                 if (bp->wol)
 799                         wol->wolopts = WAKE_MAGIC;
 800                 else
 801                         wol->wolopts = 0;
 802         }
 803         memset(&wol->sopass, 0, sizeof(wol->sopass));
 804 }
 805
 806 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 807 {
 808         struct bnx2x *bp = netdev_priv(dev);
 809
 810         if (wol->wolopts & ~WAKE_MAGIC)
 811                 return -EINVAL;
 812
 813         if (wol->wolopts & WAKE_MAGIC) {
 814                 if (bp->flags & NO_WOL_FLAG)
 815                         return -EINVAL;
 816
 817                 bp->wol = 1;
 818         } else
 819                 bp->wol = 0;
 820
 821         return 0;
 822 }
 823
 824 static u32 bnx2x_get_msglevel(struct net_device *dev)
 825 {
 826         struct bnx2x *bp = netdev_priv(dev);
 827
 828         return bp->msg_enable;
 829 }
 830
 831 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 832 {
 833         struct bnx2x *bp = netdev_priv(dev);
 834
 835         if (capable(CAP_NET_ADMIN)) {
 836                 /* dump MCP trace */
 837                 if (level & BNX2X_MSG_MCP)
 838                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
 839                 bp->msg_enable = level;
 840         }
 841 }
 842
 843 static int bnx2x_nway_reset(struct net_device *dev)
 844 {
 845         struct bnx2x *bp = netdev_priv(dev);
 846
 847         if (!bp->port.pmf)
 848                 return 0;
 849
 850         if (netif_running(dev)) {
 851                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 852                 bnx2x_link_set(bp);
 853         }
 854
 855         return 0;
 856 }
 857
 858 static u32 bnx2x_get_link(struct net_device *dev)
 859 {
 860         struct bnx2x *bp = netdev_priv(dev);
 861
 862         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 863                 return 0;
 864
 865         return bp->link_vars.link_up;
 866 }
 867
 868 static int bnx2x_get_eeprom_len(struct net_device *dev)
 869 {
 870         struct bnx2x *bp = netdev_priv(dev);
 871
 872         return bp->common.flash_size;
 873 }
 874
 875 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 876 {
 877         int port = BP_PORT(bp);
 878         int count, i;
 879         u32 val = 0;
 880
 881         /* adjust timeout for emulation/FPGA */
 882         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 883         if (CHIP_REV_IS_SLOW(bp))
 884                 count *= 100;
 885
 886         /* request access to nvram interface */
 887         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 888                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 889
 890         for (i = 0; i < count*10; i++) {
 891                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 892                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 893                         break;
 894
 895                 udelay(5);
 896         }
 897
 898         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 899                 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
 900                 return -EBUSY;
 901         }
 902
 903         return 0;
 904 }
 905
 906 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 907 {
 908         int port = BP_PORT(bp);
 909         int count, i;
 910         u32 val = 0;
 911
 912         /* adjust timeout for emulation/FPGA */
 913         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 914         if (CHIP_REV_IS_SLOW(bp))
 915                 count *= 100;
 916
 917         /* relinquish nvram interface */
 918         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 919                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 920
 921         for (i = 0; i < count*10; i++) {
 922                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 923                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 924                         break;
 925
 926                 udelay(5);
 927         }
 928
 929         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
 930                 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
 931                 return -EBUSY;
 932         }
 933
 934         return 0;
 935 }
 936
 937 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
 938 {
 939         u32 val;
 940
 941         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 942
 943         /* enable both bits, even on read */
 944         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 945                (val | MCPR_NVM_ACCESS_ENABLE_EN |
 946                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
 947 }
 948
 949 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
 950 {
 951         u32 val;
 952
 953         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 954
 955         /* disable both bits, even after read */
 956         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 957                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
 958                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
 959 }
 960
 961 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
 962                                   u32 cmd_flags)
 963 {
 964         int count, i, rc;
 965         u32 val;
 966
 967         /* build the command word */
 968         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
 969
 970         /* need to clear DONE bit separately */
 971         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 972
 973         /* address of the NVRAM to read from */
 974         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 975                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 976
 977         /* issue a read command */
 978         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 979
 980         /* adjust timeout for emulation/FPGA */
 981         count = BNX2X_NVRAM_TIMEOUT_COUNT;
 982         if (CHIP_REV_IS_SLOW(bp))
 983                 count *= 100;
 984
 985         /* wait for completion */
 986         *ret_val = 0;
 987         rc = -EBUSY;
 988         for (i = 0; i < count; i++) {
 989                 udelay(5);
 990                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 991
 992                 if (val & MCPR_NVM_COMMAND_DONE) {
 993                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
 994                         /* we read nvram data in cpu order
 995                          * but ethtool sees it as an array of bytes
 996                          * converting to big-endian will do the work */
 997                         *ret_val = cpu_to_be32(val);
 998                         rc = 0;
 999                         break;
1000                 }
1001         }
1002
1003         return rc;
1004 }
1005
1006 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1007                             int buf_size)
1008 {
1009         int rc;
1010         u32 cmd_flags;
1011         __be32 val;
1012
1013         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1014                 DP(BNX2X_MSG_NVM,
1015                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1016                    offset, buf_size);
1017                 return -EINVAL;
1018         }
1019
1020         if (offset + buf_size > bp->common.flash_size) {
1021                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1022                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1023                    offset, buf_size, bp->common.flash_size);
1024                 return -EINVAL;
1025         }
1026
1027         /* request access to nvram interface */
1028         rc = bnx2x_acquire_nvram_lock(bp);
1029         if (rc)
1030                 return rc;
1031
1032         /* enable access to nvram interface */
1033         bnx2x_enable_nvram_access(bp);
1034
1035         /* read the first word(s) */
1036         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1037         while ((buf_size > sizeof(u32)) && (rc == 0)) {
1038                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1039                 memcpy(ret_buf, &val, 4);
1040
1041                 /* advance to the next dword */
1042                 offset += sizeof(u32);
1043                 ret_buf += sizeof(u32);
1044                 buf_size -= sizeof(u32);
1045                 cmd_flags = 0;
1046         }
1047
1048         if (rc == 0) {
1049                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1050                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1051                 memcpy(ret_buf, &val, 4);
1052         }
1053
1054         /* disable access to nvram interface */
1055         bnx2x_disable_nvram_access(bp);
1056         bnx2x_release_nvram_lock(bp);
1057
1058         return rc;
1059 }
1060
1061 static int bnx2x_get_eeprom(struct net_device *dev,
1062                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1063 {
1064         struct bnx2x *bp = netdev_priv(dev);
1065         int rc;
1066
1067         if (!netif_running(dev))
1068                 return -EAGAIN;
1069
1070         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1071            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1072            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1073            eeprom->len, eeprom->len);
1074
1075         /* parameters already validated in ethtool_get_eeprom */
1076
1077         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1078
1079         return rc;
1080 }
1081
1082 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1083                                    u32 cmd_flags)
1084 {
1085         int count, i, rc;
1086
1087         /* build the command word */
1088         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1089
1090         /* need to clear DONE bit separately */
1091         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1092
1093         /* write the data */
1094         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1095
1096         /* address of the NVRAM to write to */
1097         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1098                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1099
1100         /* issue the write command */
1101         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1102
1103         /* adjust timeout for emulation/FPGA */
1104         count = BNX2X_NVRAM_TIMEOUT_COUNT;
1105         if (CHIP_REV_IS_SLOW(bp))
1106                 count *= 100;
1107
1108         /* wait for completion */
1109         rc = -EBUSY;
1110         for (i = 0; i < count; i++) {
1111                 udelay(5);
1112                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1113                 if (val & MCPR_NVM_COMMAND_DONE) {
1114                         rc = 0;
1115                         break;
1116                 }
1117         }
1118
1119         return rc;
1120 }
1121
1122 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
1123
1124 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1125                               int buf_size)
1126 {
1127         int rc;
1128         u32 cmd_flags;
1129         u32 align_offset;
1130         __be32 val;
1131
1132         if (offset + buf_size > bp->common.flash_size) {
1133                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1134                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1135                    offset, buf_size, bp->common.flash_size);
1136                 return -EINVAL;
1137         }
1138
1139         /* request access to nvram interface */
1140         rc = bnx2x_acquire_nvram_lock(bp);
1141         if (rc)
1142                 return rc;
1143
1144         /* enable access to nvram interface */
1145         bnx2x_enable_nvram_access(bp);
1146
1147         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1148         align_offset = (offset & ~0x03);
1149         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1150
1151         if (rc == 0) {
1152                 val &= ~(0xff << BYTE_OFFSET(offset));
1153                 val |= (*data_buf << BYTE_OFFSET(offset));
1154
1155                 /* nvram data is returned as an array of bytes
1156                  * convert it back to cpu order */
1157                 val = be32_to_cpu(val);
1158
1159                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1160                                              cmd_flags);
1161         }
1162
1163         /* disable access to nvram interface */
1164         bnx2x_disable_nvram_access(bp);
1165         bnx2x_release_nvram_lock(bp);
1166
1167         return rc;
1168 }
1169
1170 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1171                              int buf_size)
1172 {
1173         int rc;
1174         u32 cmd_flags;
1175         u32 val;
1176         u32 written_so_far;
1177
1178         if (buf_size == 1)      /* ethtool */
1179                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1180
1181         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1182                 DP(BNX2X_MSG_NVM,
1183                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1184                    offset, buf_size);
1185                 return -EINVAL;
1186         }
1187
1188         if (offset + buf_size > bp->common.flash_size) {
1189                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1190                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1191                    offset, buf_size, bp->common.flash_size);
1192                 return -EINVAL;
1193         }
1194
1195         /* request access to nvram interface */
1196         rc = bnx2x_acquire_nvram_lock(bp);
1197         if (rc)
1198                 return rc;
1199
1200         /* enable access to nvram interface */
1201         bnx2x_enable_nvram_access(bp);
1202
1203         written_so_far = 0;
1204         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1205         while ((written_so_far < buf_size) && (rc == 0)) {
1206                 if (written_so_far == (buf_size - sizeof(u32)))
1207                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1208                 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1209                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1210                 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1211                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1212
1213                 memcpy(&val, data_buf, 4);
1214
1215                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1216
1217                 /* advance to the next dword */
1218                 offset += sizeof(u32);
1219                 data_buf += sizeof(u32);
1220                 written_so_far += sizeof(u32);
1221                 cmd_flags = 0;
1222         }
1223
1224         /* disable access to nvram interface */
1225         bnx2x_disable_nvram_access(bp);
1226         bnx2x_release_nvram_lock(bp);
1227
1228         return rc;
1229 }
1230
1231 static int bnx2x_set_eeprom(struct net_device *dev,
1232                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1233 {
1234         struct bnx2x *bp = netdev_priv(dev);
1235         int port = BP_PORT(bp);
1236         int rc = 0;
1237         u32 ext_phy_config;
1238         if (!netif_running(dev))
1239                 return -EAGAIN;
1240
1241         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1242            "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1243            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1244            eeprom->len, eeprom->len);
1245
1246         /* parameters already validated in ethtool_set_eeprom */
1247
1248         /* PHY eeprom can be accessed only by the PMF */
1249         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1250             !bp->port.pmf)
1251                 return -EINVAL;
1252
1253         ext_phy_config =
1254                 SHMEM_RD(bp,
1255                          dev_info.port_hw_config[port].external_phy_config);
1256
1257         if (eeprom->magic == 0x50485950) {
1258                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1259                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1260
1261                 bnx2x_acquire_phy_lock(bp);
1262                 rc |= bnx2x_link_reset(&bp->link_params,
1263                                        &bp->link_vars, 0);
1264                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1265                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1266                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1267                                        MISC_REGISTERS_GPIO_HIGH, port);
1268                 bnx2x_release_phy_lock(bp);
1269                 bnx2x_link_report(bp);
1270
1271         } else if (eeprom->magic == 0x50485952) {
1272                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1273                 if (bp->state == BNX2X_STATE_OPEN) {
1274                         bnx2x_acquire_phy_lock(bp);
1275                         rc |= bnx2x_link_reset(&bp->link_params,
1276                                                &bp->link_vars, 1);
1277
1278                         rc |= bnx2x_phy_init(&bp->link_params,
1279                                              &bp->link_vars);
1280                         bnx2x_release_phy_lock(bp);
1281                         bnx2x_calc_fc_adv(bp);
1282                 }
1283         } else if (eeprom->magic == 0x53985943) {
1284                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1285                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1286                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1287
1288                         /* DSP Remove Download Mode */
1289                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1290                                        MISC_REGISTERS_GPIO_LOW, port);
1291
1292                         bnx2x_acquire_phy_lock(bp);
1293
1294                         bnx2x_sfx7101_sp_sw_reset(bp,
1295                                                 &bp->link_params.phy[EXT_PHY1]);
1296
1297                         /* wait 0.5 sec to allow it to run */
1298                         msleep(500);
1299                         bnx2x_ext_phy_hw_reset(bp, port);
1300                         msleep(500);
1301                         bnx2x_release_phy_lock(bp);
1302                 }
1303         } else
1304                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1305
1306         return rc;
1307 }
1308
1309 static int bnx2x_get_coalesce(struct net_device *dev,
1310                               struct ethtool_coalesce *coal)
1311 {
1312         struct bnx2x *bp = netdev_priv(dev);
1313
1314         memset(coal, 0, sizeof(struct ethtool_coalesce));
1315
1316         coal->rx_coalesce_usecs = bp->rx_ticks;
1317         coal->tx_coalesce_usecs = bp->tx_ticks;
1318
1319         return 0;
1320 }
1321
1322 static int bnx2x_set_coalesce(struct net_device *dev,
1323                               struct ethtool_coalesce *coal)
1324 {
1325         struct bnx2x *bp = netdev_priv(dev);
1326
1327         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1328         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1329                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1330
1331         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1332         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1333                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1334
1335         if (netif_running(dev))
1336                 bnx2x_update_coalesce(bp);
1337
1338         return 0;
1339 }
1340
1341 static void bnx2x_get_ringparam(struct net_device *dev,
1342                                 struct ethtool_ringparam *ering)
1343 {
1344         struct bnx2x *bp = netdev_priv(dev);
1345
1346         ering->rx_max_pending = MAX_RX_AVAIL;
1347
1348         if (bp->rx_ring_size)
1349                 ering->rx_pending = bp->rx_ring_size;
1350         else
1351                 ering->rx_pending = MAX_RX_AVAIL;
1352
1353         ering->tx_max_pending = MAX_TX_AVAIL;
1354         ering->tx_pending = bp->tx_ring_size;
1355 }
1356
1357 static int bnx2x_set_ringparam(struct net_device *dev,
1358                                struct ethtool_ringparam *ering)
1359 {
1360         struct bnx2x *bp = netdev_priv(dev);
1361
1362         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1363                 pr_err("Handling parity error recovery. Try again later\n");
1364                 return -EAGAIN;
1365         }
1366
1367         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1368             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1369                                                     MIN_RX_SIZE_TPA)) ||
1370             (ering->tx_pending > MAX_TX_AVAIL) ||
1371             (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1372                 return -EINVAL;
1373
1374         bp->rx_ring_size = ering->rx_pending;
1375         bp->tx_ring_size = ering->tx_pending;
1376
1377         return bnx2x_reload_if_running(dev);
1378 }
1379
1380 static void bnx2x_get_pauseparam(struct net_device *dev,
1381                                  struct ethtool_pauseparam *epause)
1382 {
1383         struct bnx2x *bp = netdev_priv(dev);
1384         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1385         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1386                            BNX2X_FLOW_CTRL_AUTO);
1387
1388         epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1389                             BNX2X_FLOW_CTRL_RX);
1390         epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1391                             BNX2X_FLOW_CTRL_TX);
1392
1393         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1394            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1395            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1396 }
1397
1398 static int bnx2x_set_pauseparam(struct net_device *dev,
1399                                 struct ethtool_pauseparam *epause)
1400 {
1401         struct bnx2x *bp = netdev_priv(dev);
1402         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1403         if (IS_MF(bp))
1404                 return 0;
1405
1406         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1407            "  autoneg %d  rx_pause %d  tx_pause %d\n",
1408            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1409
1410         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1411
1412         if (epause->rx_pause)
1413                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1414
1415         if (epause->tx_pause)
1416                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1417
1418         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1419                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1420
1421         if (epause->autoneg) {
1422                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1423                         DP(NETIF_MSG_LINK, "autoneg not supported\n");
1424                         return -EINVAL;
1425                 }
1426
1427                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1428                         bp->link_params.req_flow_ctrl[cfg_idx] =
1429                                 BNX2X_FLOW_CTRL_AUTO;
1430                 }
1431         }
1432
1433         DP(NETIF_MSG_LINK,
1434            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1435
1436         if (netif_running(dev)) {
1437                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1438                 bnx2x_link_set(bp);
1439         }
1440
1441         return 0;
1442 }
1443
1444 static const struct {
1445         char string[ETH_GSTRING_LEN];
1446 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1447         { "register_test (offline)" },
1448         { "memory_test (offline)" },
1449         { "loopback_test (offline)" },
1450         { "nvram_test (online)" },
1451         { "interrupt_test (online)" },
1452         { "link_test (online)" },
1453         { "idle check (online)" }
1454 };
1455
1456 enum {
1457         BNX2X_CHIP_E1_OFST = 0,
1458         BNX2X_CHIP_E1H_OFST,
1459         BNX2X_CHIP_E2_OFST,
1460         BNX2X_CHIP_E3_OFST,
1461         BNX2X_CHIP_E3B0_OFST,
1462         BNX2X_CHIP_MAX_OFST
1463 };
1464
1465 #define BNX2X_CHIP_MASK_E1      (1 << BNX2X_CHIP_E1_OFST)
1466 #define BNX2X_CHIP_MASK_E1H     (1 << BNX2X_CHIP_E1H_OFST)
1467 #define BNX2X_CHIP_MASK_E2      (1 << BNX2X_CHIP_E2_OFST)
1468 #define BNX2X_CHIP_MASK_E3      (1 << BNX2X_CHIP_E3_OFST)
1469 #define BNX2X_CHIP_MASK_E3B0    (1 << BNX2X_CHIP_E3B0_OFST)
1470
1471 #define BNX2X_CHIP_MASK_ALL     ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1472 #define BNX2X_CHIP_MASK_E1X     (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1473
1474 static int bnx2x_test_registers(struct bnx2x *bp)
1475 {
1476         int idx, i, rc = -ENODEV;
1477         u32 wr_val = 0, hw;
1478         int port = BP_PORT(bp);
1479         static const struct {
1480                 u32 hw;
1481                 u32 offset0;
1482                 u32 offset1;
1483                 u32 mask;
1484         } reg_tbl[] = {
1485 /* 0 */         { BNX2X_CHIP_MASK_ALL,
1486                         BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1487                 { BNX2X_CHIP_MASK_ALL,
1488                         DORQ_REG_DB_ADDR0,              4, 0xffffffff },
1489                 { BNX2X_CHIP_MASK_E1X,
1490                         HC_REG_AGG_INT_0,               4, 0x000003ff },
1491                 { BNX2X_CHIP_MASK_ALL,
1492                         PBF_REG_MAC_IF0_ENABLE,         4, 0x00000001 },
1493                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1494                         PBF_REG_P0_INIT_CRD,            4, 0x000007ff },
1495                 { BNX2X_CHIP_MASK_E3B0,
1496                         PBF_REG_INIT_CRD_Q0,            4, 0x000007ff },
1497                 { BNX2X_CHIP_MASK_ALL,
1498                         PRS_REG_CID_PORT_0,             4, 0x00ffffff },
1499                 { BNX2X_CHIP_MASK_ALL,
1500                         PXP2_REG_PSWRQ_CDU0_L2P,        4, 0x000fffff },
1501                 { BNX2X_CHIP_MASK_ALL,
1502                         PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1503                 { BNX2X_CHIP_MASK_ALL,
1504                         PXP2_REG_PSWRQ_TM0_L2P,         4, 0x000fffff },
1505 /* 10 */        { BNX2X_CHIP_MASK_ALL,
1506                         PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1507                 { BNX2X_CHIP_MASK_ALL,
1508                         PXP2_REG_PSWRQ_TSDM0_L2P,       4, 0x000fffff },
1509                 { BNX2X_CHIP_MASK_ALL,
1510                         QM_REG_CONNNUM_0,               4, 0x000fffff },
1511                 { BNX2X_CHIP_MASK_ALL,
1512                         TM_REG_LIN0_MAX_ACTIVE_CID,     4, 0x0003ffff },
1513                 { BNX2X_CHIP_MASK_ALL,
1514                         SRC_REG_KEYRSS0_0,              40, 0xffffffff },
1515                 { BNX2X_CHIP_MASK_ALL,
1516                         SRC_REG_KEYRSS0_7,              40, 0xffffffff },
1517                 { BNX2X_CHIP_MASK_ALL,
1518                         XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1519                 { BNX2X_CHIP_MASK_ALL,
1520                         XCM_REG_WU_DA_CNT_CMD00,        4, 0x00000003 },
1521                 { BNX2X_CHIP_MASK_ALL,
1522                         XCM_REG_GLB_DEL_ACK_MAX_CNT_0,  4, 0x000000ff },
1523                 { BNX2X_CHIP_MASK_ALL,
1524                         NIG_REG_LLH0_T_BIT,             4, 0x00000001 },
1525 /* 20 */        { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1526                         NIG_REG_EMAC0_IN_EN,            4, 0x00000001 },
1527                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1528                         NIG_REG_BMAC0_IN_EN,            4, 0x00000001 },
1529                 { BNX2X_CHIP_MASK_ALL,
1530                         NIG_REG_XCM0_OUT_EN,            4, 0x00000001 },
1531                 { BNX2X_CHIP_MASK_ALL,
1532                         NIG_REG_BRB0_OUT_EN,            4, 0x00000001 },
1533                 { BNX2X_CHIP_MASK_ALL,
1534                         NIG_REG_LLH0_XCM_MASK,          4, 0x00000007 },
1535                 { BNX2X_CHIP_MASK_ALL,
1536                         NIG_REG_LLH0_ACPI_PAT_6_LEN,    68, 0x000000ff },
1537                 { BNX2X_CHIP_MASK_ALL,
1538                         NIG_REG_LLH0_ACPI_PAT_0_CRC,    68, 0xffffffff },
1539                 { BNX2X_CHIP_MASK_ALL,
1540                         NIG_REG_LLH0_DEST_MAC_0_0,      160, 0xffffffff },
1541                 { BNX2X_CHIP_MASK_ALL,
1542                         NIG_REG_LLH0_DEST_IP_0_1,       160, 0xffffffff },
1543                 { BNX2X_CHIP_MASK_ALL,
1544                         NIG_REG_LLH0_IPV4_IPV6_0,       160, 0x00000001 },
1545 /* 30 */        { BNX2X_CHIP_MASK_ALL,
1546                         NIG_REG_LLH0_DEST_UDP_0,        160, 0x0000ffff },
1547                 { BNX2X_CHIP_MASK_ALL,
1548                         NIG_REG_LLH0_DEST_TCP_0,        160, 0x0000ffff },
1549                 { BNX2X_CHIP_MASK_ALL,
1550                         NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1551                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1552                         NIG_REG_XGXS_SERDES0_MODE_SEL,  4, 0x00000001 },
1553                 { BNX2X_CHIP_MASK_ALL,
1554                         NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1555                 { BNX2X_CHIP_MASK_ALL,
1556                         NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1557                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1558                         NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1559                 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1560                         NIG_REG_SERDES0_CTRL_PHY_ADDR,  16, 0x0000001f },
1561
1562                 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
1563         };
1564
1565         if (!netif_running(bp->dev))
1566                 return rc;
1567
1568         if (CHIP_IS_E1(bp))
1569                 hw = BNX2X_CHIP_MASK_E1;
1570         else if (CHIP_IS_E1H(bp))
1571                 hw = BNX2X_CHIP_MASK_E1H;
1572         else if (CHIP_IS_E2(bp))
1573                 hw = BNX2X_CHIP_MASK_E2;
1574         else if (CHIP_IS_E3B0(bp))
1575                 hw = BNX2X_CHIP_MASK_E3B0;
1576         else /* e3 A0 */
1577                 hw = BNX2X_CHIP_MASK_E3;
1578
1579         /* Repeat the test twice:
1580            First by writing 0x00000000, second by writing 0xffffffff */
1581         for (idx = 0; idx < 2; idx++) {
1582
1583                 switch (idx) {
1584                 case 0:
1585                         wr_val = 0;
1586                         break;
1587                 case 1:
1588                         wr_val = 0xffffffff;
1589                         break;
1590                 }
1591
1592                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1593                         u32 offset, mask, save_val, val;
1594                         if (!(hw & reg_tbl[i].hw))
1595                                 continue;
1596
1597                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1598                         mask = reg_tbl[i].mask;
1599
1600                         save_val = REG_RD(bp, offset);
1601
1602                         REG_WR(bp, offset, wr_val & mask);
1603
1604                         val = REG_RD(bp, offset);
1605
1606                         /* Restore the original register's value */
1607                         REG_WR(bp, offset, save_val);
1608
1609                         /* verify value is as expected */
1610                         if ((val & mask) != (wr_val & mask)) {
1611                                 DP(NETIF_MSG_HW,
1612                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1613                                    offset, val, wr_val, mask);
1614                                 goto test_reg_exit;
1615                         }
1616                 }
1617         }
1618
1619         rc = 0;
1620
1621 test_reg_exit:
1622         return rc;
1623 }
1624
1625 static int bnx2x_test_memory(struct bnx2x *bp)
1626 {
1627         int i, j, rc = -ENODEV;
1628         u32 val, index;
1629         static const struct {
1630                 u32 offset;
1631                 int size;
1632         } mem_tbl[] = {
1633                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1634                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1635                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1636                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1637                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1638                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1639                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1640
1641                 { 0xffffffff, 0 }
1642         };
1643
1644         static const struct {
1645                 char *name;
1646                 u32 offset;
1647                 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
1648         } prty_tbl[] = {
1649                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,
1650                         {0x3ffc0, 0,   0, 0} },
1651                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,
1652                         {0x2,     0x2, 0, 0} },
1653                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1654                         {0,       0,   0, 0} },
1655                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,
1656                         {0x3ffc0, 0,   0, 0} },
1657                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,
1658                         {0x3ffc0, 0,   0, 0} },
1659                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,
1660                         {0x3ffc1, 0,   0, 0} },
1661
1662                 { NULL, 0xffffffff, {0, 0, 0, 0} }
1663         };
1664
1665         if (!netif_running(bp->dev))
1666                 return rc;
1667
1668         if (CHIP_IS_E1(bp))
1669                 index = BNX2X_CHIP_E1_OFST;
1670         else if (CHIP_IS_E1H(bp))
1671                 index = BNX2X_CHIP_E1H_OFST;
1672         else if (CHIP_IS_E2(bp))
1673                 index = BNX2X_CHIP_E2_OFST;
1674         else /* e3 */
1675                 index = BNX2X_CHIP_E3_OFST;
1676
1677         /* pre-Check the parity status */
1678         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1679                 val = REG_RD(bp, prty_tbl[i].offset);
1680                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1681                         DP(NETIF_MSG_HW,
1682                            "%s is 0x%x\n", prty_tbl[i].name, val);
1683                         goto test_mem_exit;
1684                 }
1685         }
1686
1687         /* Go through all the memories */
1688         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1689                 for (j = 0; j < mem_tbl[i].size; j++)
1690                         REG_RD(bp, mem_tbl[i].offset + j*4);
1691
1692         /* Check the parity status */
1693         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1694                 val = REG_RD(bp, prty_tbl[i].offset);
1695                 if (val & ~(prty_tbl[i].hw_mask[index])) {
1696                         DP(NETIF_MSG_HW,
1697                            "%s is 0x%x\n", prty_tbl[i].name, val);
1698                         goto test_mem_exit;
1699                 }
1700         }
1701
1702         rc = 0;
1703
1704 test_mem_exit:
1705         return rc;
1706 }
1707
1708 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1709 {
1710         int cnt = 1400;
1711
1712         if (link_up) {
1713                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1714                         msleep(20);
1715
1716                 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1717                         DP(NETIF_MSG_LINK, "Timeout waiting for link up\n");
1718         }
1719 }
1720
1721 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
1722 {
1723         unsigned int pkt_size, num_pkts, i;
1724         struct sk_buff *skb;
1725         unsigned char *packet;
1726         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1727         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1728         struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
1729         u16 tx_start_idx, tx_idx;
1730         u16 rx_start_idx, rx_idx;
1731         u16 pkt_prod, bd_prod, rx_comp_cons;
1732         struct sw_tx_bd *tx_buf;
1733         struct eth_tx_start_bd *tx_start_bd;
1734         struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
1735         struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
1736         dma_addr_t mapping;
1737         union eth_rx_cqe *cqe;
1738         u8 cqe_fp_flags, cqe_fp_type;
1739         struct sw_rx_bd *rx_buf;
1740         u16 len;
1741         int rc = -ENODEV;
1742
1743         /* check the loopback mode */
1744         switch (loopback_mode) {
1745         case BNX2X_PHY_LOOPBACK:
1746                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1747                         return -EINVAL;
1748                 break;
1749         case BNX2X_MAC_LOOPBACK:
1750                 bp->link_params.loopback_mode = CHIP_IS_E3(bp) ?
1751                                                 LOOPBACK_XMAC : LOOPBACK_BMAC;
1752                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1753                 break;
1754         default:
1755                 return -EINVAL;
1756         }
1757
1758         /* prepare the loopback packet */
1759         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1760                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1761         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1762         if (!skb) {
1763                 rc = -ENOMEM;
1764                 goto test_loopback_exit;
1765         }
1766         packet = skb_put(skb, pkt_size);
1767         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1768         memset(packet + ETH_ALEN, 0, ETH_ALEN);
1769         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1770         for (i = ETH_HLEN; i < pkt_size; i++)
1771                 packet[i] = (unsigned char) (i & 0xff);
1772         mapping = dma_map_single(&bp->pdev->dev, skb->data,
1773                                  skb_headlen(skb), DMA_TO_DEVICE);
1774         if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1775                 rc = -ENOMEM;
1776                 dev_kfree_skb(skb);
1777                 BNX2X_ERR("Unable to map SKB\n");
1778                 goto test_loopback_exit;
1779         }
1780
1781         /* send the loopback packet */
1782         num_pkts = 0;
1783         tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
1784         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1785
1786         pkt_prod = txdata->tx_pkt_prod++;
1787         tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
1788         tx_buf->first_bd = txdata->tx_bd_prod;
1789         tx_buf->skb = skb;
1790         tx_buf->flags = 0;
1791
1792         bd_prod = TX_BD(txdata->tx_bd_prod);
1793         tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
1794         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1795         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1796         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1797         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1798         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1799         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1800         SET_FLAG(tx_start_bd->general_data,
1801                  ETH_TX_START_BD_ETH_ADDR_TYPE,
1802                  UNICAST_ADDRESS);
1803         SET_FLAG(tx_start_bd->general_data,
1804                  ETH_TX_START_BD_HDR_NBDS,
1805                  1);
1806
1807         /* turn on parsing and get a BD */
1808         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1809
1810         pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
1811         pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
1812
1813         memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1814         memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1815
1816         wmb();
1817
1818         txdata->tx_db.data.prod += 2;
1819         barrier();
1820         DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
1821
1822         mmiowb();
1823         barrier();
1824
1825         num_pkts++;
1826         txdata->tx_bd_prod += 2; /* start + pbd */
1827
1828         udelay(100);
1829
1830         tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
1831         if (tx_idx != tx_start_idx + num_pkts)
1832                 goto test_loopback_exit;
1833
1834         /* Unlike HC IGU won't generate an interrupt for status block
1835          * updates that have been performed while interrupts were
1836          * disabled.
1837          */
1838         if (bp->common.int_block == INT_BLOCK_IGU) {
1839                 /* Disable local BHes to prevent a dead-lock situation between
1840                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
1841                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
1842                  */
1843                 local_bh_disable();
1844                 bnx2x_tx_int(bp, txdata);
1845                 local_bh_enable();
1846         }
1847
1848         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1849         if (rx_idx != rx_start_idx + num_pkts)
1850                 goto test_loopback_exit;
1851
1852         rx_comp_cons = le16_to_cpu(fp_rx->rx_comp_cons);
1853         cqe = &fp_rx->rx_comp_ring[RCQ_BD(rx_comp_cons)];
1854         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1855         cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1856         if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1857                 goto test_loopback_rx_exit;
1858
1859         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1860         if (len != pkt_size)
1861                 goto test_loopback_rx_exit;
1862
1863         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1864         dma_sync_single_for_cpu(&bp->pdev->dev,
1865                                    dma_unmap_addr(rx_buf, mapping),
1866                                    fp_rx->rx_buf_size, DMA_FROM_DEVICE);
1867         skb = rx_buf->skb;
1868         skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1869         for (i = ETH_HLEN; i < pkt_size; i++)
1870                 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1871                         goto test_loopback_rx_exit;
1872
1873         rc = 0;
1874
1875 test_loopback_rx_exit:
1876
1877         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1878         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1879         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1880         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1881
1882         /* Update producers */
1883         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1884                              fp_rx->rx_sge_prod);
1885
1886 test_loopback_exit:
1887         bp->link_params.loopback_mode = LOOPBACK_NONE;
1888
1889         return rc;
1890 }
1891
1892 static int bnx2x_test_loopback(struct bnx2x *bp)
1893 {
1894         int rc = 0, res;
1895
1896         if (BP_NOMCP(bp))
1897                 return rc;
1898
1899         if (!netif_running(bp->dev))
1900                 return BNX2X_LOOPBACK_FAILED;
1901
1902         bnx2x_netif_stop(bp, 1);
1903         bnx2x_acquire_phy_lock(bp);
1904
1905         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
1906         if (res) {
1907                 DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
1908                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1909         }
1910
1911         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
1912         if (res) {
1913                 DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
1914                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1915         }
1916
1917         bnx2x_release_phy_lock(bp);
1918         bnx2x_netif_start(bp);
1919
1920         return rc;
1921 }
1922
1923 #define CRC32_RESIDUAL                  0xdebb20e3
1924
1925 static int bnx2x_test_nvram(struct bnx2x *bp)
1926 {
1927         static const struct {
1928                 int offset;
1929                 int size;
1930         } nvram_tbl[] = {
1931                 {     0,  0x14 }, /* bootstrap */
1932                 {  0x14,  0xec }, /* dir */
1933                 { 0x100, 0x350 }, /* manuf_info */
1934                 { 0x450,  0xf0 }, /* feature_info */
1935                 { 0x640,  0x64 }, /* upgrade_key_info */
1936                 { 0x708,  0x70 }, /* manuf_key_info */
1937                 {     0,     0 }
1938         };
1939         __be32 buf[0x350 / 4];
1940         u8 *data = (u8 *)buf;
1941         int i, rc;
1942         u32 magic, crc;
1943
1944         if (BP_NOMCP(bp))
1945                 return 0;
1946
1947         rc = bnx2x_nvram_read(bp, 0, data, 4);
1948         if (rc) {
1949                 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1950                 goto test_nvram_exit;
1951         }
1952
1953         magic = be32_to_cpu(buf[0]);
1954         if (magic != 0x669955aa) {
1955                 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1956                 rc = -ENODEV;
1957                 goto test_nvram_exit;
1958         }
1959
1960         for (i = 0; nvram_tbl[i].size; i++) {
1961
1962                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1963                                       nvram_tbl[i].size);
1964                 if (rc) {
1965                         DP(NETIF_MSG_PROBE,
1966                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1967                         goto test_nvram_exit;
1968                 }
1969
1970                 crc = ether_crc_le(nvram_tbl[i].size, data);
1971                 if (crc != CRC32_RESIDUAL) {
1972                         DP(NETIF_MSG_PROBE,
1973                            "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1974                         rc = -ENODEV;
1975                         goto test_nvram_exit;
1976                 }
1977         }
1978
1979 test_nvram_exit:
1980         return rc;
1981 }
1982
1983 /* Send an EMPTY ramrod on the first queue */
1984 static int bnx2x_test_intr(struct bnx2x *bp)
1985 {
1986         struct bnx2x_queue_state_params params = {0};
1987
1988         if (!netif_running(bp->dev))
1989                 return -ENODEV;
1990
1991         params.q_obj = &bp->fp->q_obj;
1992         params.cmd = BNX2X_Q_CMD_EMPTY;
1993
1994         __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
1995
1996         return bnx2x_queue_state_change(bp, &params);
1997 }
1998
1999 static void bnx2x_self_test(struct net_device *dev,
2000                             struct ethtool_test *etest, u64 *buf)
2001 {
2002         struct bnx2x *bp = netdev_priv(dev);
2003         u8 is_serdes;
2004         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2005                 pr_err("Handling parity error recovery. Try again later\n");
2006                 etest->flags |= ETH_TEST_FL_FAILED;
2007                 return;
2008         }
2009
2010         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
2011
2012         if (!netif_running(dev))
2013                 return;
2014
2015         /* offline tests are not supported in MF mode */
2016         if (IS_MF(bp))
2017                 etest->flags &= ~ETH_TEST_FL_OFFLINE;
2018         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2019
2020         if (etest->flags & ETH_TEST_FL_OFFLINE) {
2021                 int port = BP_PORT(bp);
2022                 u32 val;
2023                 u8 link_up;
2024
2025                 /* save current value of input enable for TX port IF */
2026                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2027                 /* disable input for TX port IF */
2028                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2029
2030                 link_up = bp->link_vars.link_up;
2031
2032                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2033                 bnx2x_nic_load(bp, LOAD_DIAG);
2034                 /* wait until link state is restored */
2035                 bnx2x_wait_for_link(bp, 1, is_serdes);
2036
2037                 if (bnx2x_test_registers(bp) != 0) {
2038                         buf[0] = 1;
2039                         etest->flags |= ETH_TEST_FL_FAILED;
2040                 }
2041                 if (bnx2x_test_memory(bp) != 0) {
2042                         buf[1] = 1;
2043                         etest->flags |= ETH_TEST_FL_FAILED;
2044                 }
2045
2046                 buf[2] = bnx2x_test_loopback(bp);
2047                 if (buf[2] != 0)
2048                         etest->flags |= ETH_TEST_FL_FAILED;
2049
2050                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2051
2052                 /* restore input for TX port IF */
2053                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2054
2055                 bnx2x_nic_load(bp, LOAD_NORMAL);
2056                 /* wait until link state is restored */
2057                 bnx2x_wait_for_link(bp, link_up, is_serdes);
2058         }
2059         if (bnx2x_test_nvram(bp) != 0) {
2060                 buf[3] = 1;
2061                 etest->flags |= ETH_TEST_FL_FAILED;
2062         }
2063         if (bnx2x_test_intr(bp) != 0) {
2064                 buf[4] = 1;
2065                 etest->flags |= ETH_TEST_FL_FAILED;
2066         }
2067
2068         if (bnx2x_link_test(bp, is_serdes) != 0) {
2069                 buf[5] = 1;
2070                 etest->flags |= ETH_TEST_FL_FAILED;
2071         }
2072
2073 #ifdef BNX2X_EXTRA_DEBUG
2074         bnx2x_panic_dump(bp);
2075 #endif
2076 }
2077
2078 #define IS_PORT_STAT(i) \
2079         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2080 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2081 #define IS_MF_MODE_STAT(bp) \
2082                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2083
2084 /* ethtool statistics are displayed for all regular ethernet queues and the
2085  * fcoe L2 queue if not disabled
2086  */
2087 static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
2088 {
2089         return BNX2X_NUM_ETH_QUEUES(bp);
2090 }
2091
2092 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2093 {
2094         struct bnx2x *bp = netdev_priv(dev);
2095         int i, num_stats;
2096
2097         switch (stringset) {
2098         case ETH_SS_STATS:
2099                 if (is_multi(bp)) {
2100                         num_stats = bnx2x_num_stat_queues(bp) *
2101                                 BNX2X_NUM_Q_STATS;
2102                         if (!IS_MF_MODE_STAT(bp))
2103                                 num_stats += BNX2X_NUM_STATS;
2104                 } else {
2105                         if (IS_MF_MODE_STAT(bp)) {
2106                                 num_stats = 0;
2107                                 for (i = 0; i < BNX2X_NUM_STATS; i++)
2108                                         if (IS_FUNC_STAT(i))
2109                                                 num_stats++;
2110                         } else
2111                                 num_stats = BNX2X_NUM_STATS;
2112                 }
2113                 return num_stats;
2114
2115         case ETH_SS_TEST:
2116                 return BNX2X_NUM_TESTS;
2117
2118         default:
2119                 return -EINVAL;
2120         }
2121 }
2122
2123 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2124 {
2125         struct bnx2x *bp = netdev_priv(dev);
2126         int i, j, k;
2127         char queue_name[MAX_QUEUE_NAME_LEN+1];
2128
2129         switch (stringset) {
2130         case ETH_SS_STATS:
2131                 if (is_multi(bp)) {
2132                         k = 0;
2133                         for_each_eth_queue(bp, i) {
2134                                 memset(queue_name, 0, sizeof(queue_name));
2135                                 sprintf(queue_name, "%d", i);
2136                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2137                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2138                                                 ETH_GSTRING_LEN,
2139                                                 bnx2x_q_stats_arr[j].string,
2140                                                 queue_name);
2141                                 k += BNX2X_NUM_Q_STATS;
2142                         }
2143                         if (IS_MF_MODE_STAT(bp))
2144                                 break;
2145                         for (j = 0; j < BNX2X_NUM_STATS; j++)
2146                                 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2147                                        bnx2x_stats_arr[j].string);
2148                 } else {
2149                         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2150                                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2151                                         continue;
2152                                 strcpy(buf + j*ETH_GSTRING_LEN,
2153                                        bnx2x_stats_arr[i].string);
2154                                 j++;
2155                         }
2156                 }
2157                 break;
2158
2159         case ETH_SS_TEST:
2160                 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2161                 break;
2162         }
2163 }
2164
2165 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2166                                     struct ethtool_stats *stats, u64 *buf)
2167 {
2168         struct bnx2x *bp = netdev_priv(dev);
2169         u32 *hw_stats, *offset;
2170         int i, j, k;
2171
2172         if (is_multi(bp)) {
2173                 k = 0;
2174                 for_each_eth_queue(bp, i) {
2175                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2176                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2177                                 if (bnx2x_q_stats_arr[j].size == 0) {
2178                                         /* skip this counter */
2179                                         buf[k + j] = 0;
2180                                         continue;
2181                                 }
2182                                 offset = (hw_stats +
2183                                           bnx2x_q_stats_arr[j].offset);
2184                                 if (bnx2x_q_stats_arr[j].size == 4) {
2185                                         /* 4-byte counter */
2186                                         buf[k + j] = (u64) *offset;
2187                                         continue;
2188                                 }
2189                                 /* 8-byte counter */
2190                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2191                         }
2192                         k += BNX2X_NUM_Q_STATS;
2193                 }
2194                 if (IS_MF_MODE_STAT(bp))
2195                         return;
2196                 hw_stats = (u32 *)&bp->eth_stats;
2197                 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2198                         if (bnx2x_stats_arr[j].size == 0) {
2199                                 /* skip this counter */
2200                                 buf[k + j] = 0;
2201                                 continue;
2202                         }
2203                         offset = (hw_stats + bnx2x_stats_arr[j].offset);
2204                         if (bnx2x_stats_arr[j].size == 4) {
2205                                 /* 4-byte counter */
2206                                 buf[k + j] = (u64) *offset;
2207                                 continue;
2208                         }
2209                         /* 8-byte counter */
2210                         buf[k + j] = HILO_U64(*offset, *(offset + 1));
2211                 }
2212         } else {
2213                 hw_stats = (u32 *)&bp->eth_stats;
2214                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2215                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2216                                 continue;
2217                         if (bnx2x_stats_arr[i].size == 0) {
2218                                 /* skip this counter */
2219                                 buf[j] = 0;
2220                                 j++;
2221                                 continue;
2222                         }
2223                         offset = (hw_stats + bnx2x_stats_arr[i].offset);
2224                         if (bnx2x_stats_arr[i].size == 4) {
2225                                 /* 4-byte counter */
2226                                 buf[j] = (u64) *offset;
2227                                 j++;
2228                                 continue;
2229                         }
2230                         /* 8-byte counter */
2231                         buf[j] = HILO_U64(*offset, *(offset + 1));
2232                         j++;
2233                 }
2234         }
2235 }
2236
2237 static int bnx2x_set_phys_id(struct net_device *dev,
2238                              enum ethtool_phys_id_state state)
2239 {
2240         struct bnx2x *bp = netdev_priv(dev);
2241
2242         if (!netif_running(dev))
2243                 return -EAGAIN;
2244
2245         if (!bp->port.pmf)
2246                 return -EOPNOTSUPP;
2247
2248         switch (state) {
2249         case ETHTOOL_ID_ACTIVE:
2250                 return 1;       /* cycle on/off once per second */
2251
2252         case ETHTOOL_ID_ON:
2253                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2254                               LED_MODE_ON, SPEED_1000);
2255                 break;
2256
2257         case ETHTOOL_ID_OFF:
2258                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2259                               LED_MODE_FRONT_PANEL_OFF, 0);
2260
2261                 break;
2262
2263         case ETHTOOL_ID_INACTIVE:
2264                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2265                               LED_MODE_OPER,
2266                               bp->link_vars.line_speed);
2267         }
2268
2269         return 0;
2270 }
2271
2272 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2273                            u32 *rules __always_unused)
2274 {
2275         struct bnx2x *bp = netdev_priv(dev);
2276
2277         switch (info->cmd) {
2278         case ETHTOOL_GRXRINGS:
2279                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2280                 return 0;
2281
2282         default:
2283                 return -EOPNOTSUPP;
2284         }
2285 }
2286
2287 static int bnx2x_get_rxfh_indir(struct net_device *dev,
2288                                 struct ethtool_rxfh_indir *indir)
2289 {
2290         struct bnx2x *bp = netdev_priv(dev);
2291         size_t copy_size =
2292                 min_t(size_t, indir->size, T_ETH_INDIRECTION_TABLE_SIZE);
2293         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2294         size_t i;
2295
2296         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2297                 return -EOPNOTSUPP;
2298
2299         /* Get the current configuration of the RSS indirection table */
2300         bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2301
2302         /*
2303          * We can't use a memcpy() as an internal storage of an
2304          * indirection table is a u8 array while indir->ring_index
2305          * points to an array of u32.
2306          *
2307          * Indirection table contains the FW Client IDs, so we need to
2308          * align the returned table to the Client ID of the leading RSS
2309          * queue.
2310          */
2311         for (i = 0; i < copy_size; i++)
2312                 indir->ring_index[i] = ind_table[i] - bp->fp->cl_id;
2313
2314         indir->size = T_ETH_INDIRECTION_TABLE_SIZE;
2315
2316         return 0;
2317 }
2318
2319 static int bnx2x_set_rxfh_indir(struct net_device *dev,
2320                                 const struct ethtool_rxfh_indir *indir)
2321 {
2322         struct bnx2x *bp = netdev_priv(dev);
2323         size_t i;
2324         u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2325         u32 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
2326
2327         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2328                 return -EOPNOTSUPP;
2329
2330         /* validate the size */
2331         if (indir->size != T_ETH_INDIRECTION_TABLE_SIZE)
2332                 return -EINVAL;
2333
2334         for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2335                 /* validate the indices */
2336                 if (indir->ring_index[i] >= num_eth_queues)
2337                         return -EINVAL;
2338                 /*
2339                  * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2340                  * as an internal storage of an indirection table is a u8 array
2341                  * while indir->ring_index points to an array of u32.
2342                  *
2343                  * Indirection table contains the FW Client IDs, so we need to
2344                  * align the received table to the Client ID of the leading RSS
2345                  * queue
2346                  */
2347                 ind_table[i] = indir->ring_index[i] + bp->fp->cl_id;
2348         }
2349
2350         return bnx2x_config_rss_pf(bp, ind_table, false);
2351 }
2352
2353 static const struct ethtool_ops bnx2x_ethtool_ops = {
2354         .get_settings           = bnx2x_get_settings,
2355         .set_settings           = bnx2x_set_settings,
2356         .get_drvinfo            = bnx2x_get_drvinfo,
2357         .get_regs_len           = bnx2x_get_regs_len,
2358         .get_regs               = bnx2x_get_regs,
2359         .get_wol                = bnx2x_get_wol,
2360         .set_wol                = bnx2x_set_wol,
2361         .get_msglevel           = bnx2x_get_msglevel,
2362         .set_msglevel           = bnx2x_set_msglevel,
2363         .nway_reset             = bnx2x_nway_reset,
2364         .get_link               = bnx2x_get_link,
2365         .get_eeprom_len         = bnx2x_get_eeprom_len,
2366         .get_eeprom             = bnx2x_get_eeprom,
2367         .set_eeprom             = bnx2x_set_eeprom,
2368         .get_coalesce           = bnx2x_get_coalesce,
2369         .set_coalesce           = bnx2x_set_coalesce,
2370         .get_ringparam          = bnx2x_get_ringparam,
2371         .set_ringparam          = bnx2x_set_ringparam,
2372         .get_pauseparam         = bnx2x_get_pauseparam,
2373         .set_pauseparam         = bnx2x_set_pauseparam,
2374         .self_test              = bnx2x_self_test,
2375         .get_sset_count         = bnx2x_get_sset_count,
2376         .get_strings            = bnx2x_get_strings,
2377         .set_phys_id            = bnx2x_set_phys_id,
2378         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2379         .get_rxnfc              = bnx2x_get_rxnfc,
2380         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
2381         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
2382 };
2383
2384 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2385 {
2386         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2387 }