drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                 PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK     0x6000
 142
 143 /* Strapping Option Register - RO */
 144 #define E1000_STRAP                     0x0000C
 145 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 146 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 147
 148 /* OEM Bits Phy Register */
 149 #define HV_OEM_BITS            PHY_REG(768, 25)
 150 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 151 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 152 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 153
 154 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 155 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 156
 157 /* KMRN Mode Control */
 158 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 159 #define HV_KMRN_MDIO_SLOW      0x0400
 160
 161 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 162 /* Offset 04h HSFSTS */
 163 union ich8_hws_flash_status {
 164         struct ich8_hsfsts {
 165                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 166                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 167                 u16 dael       :1; /* bit 2 Direct Access error Log */
 168                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 169                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 170                 u16 reserved1  :2; /* bit 13:6 Reserved */
 171                 u16 reserved2  :6; /* bit 13:6 Reserved */
 172                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 173                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 174         } hsf_status;
 175         u16 regval;
 176 };
 177
 178 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 179 /* Offset 06h FLCTL */
 180 union ich8_hws_flash_ctrl {
 181         struct ich8_hsflctl {
 182                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 183                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 184                 u16 reserved   :5;   /* 7:3 Reserved  */
 185                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 186                 u16 flockdn    :6;   /* 15:10 Reserved */
 187         } hsf_ctrl;
 188         u16 regval;
 189 };
 190
 191 /* ICH Flash Region Access Permissions */
 192 union ich8_hws_flash_regacc {
 193         struct ich8_flracc {
 194                 u32 grra      :8; /* 0:7 GbE region Read Access */
 195                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 196                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 197                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 198         } hsf_flregacc;
 199         u16 regval;
 200 };
 201
 202 /* ICH Flash Protected Region */
 203 union ich8_flash_protected_range {
 204         struct ich8_pr {
 205                 u32 base:13;     /* 0:12 Protected Range Base */
 206                 u32 reserved1:2; /* 13:14 Reserved */
 207                 u32 rpe:1;       /* 15 Read Protection Enable */
 208                 u32 limit:13;    /* 16:28 Protected Range Limit */
 209                 u32 reserved2:2; /* 29:30 Reserved */
 210                 u32 wpe:1;       /* 31 Write Protection Enable */
 211         } range;
 212         u32 regval;
 213 };
 214
 215 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 216 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 217 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 218 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 219 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 220                                                 u32 offset, u8 byte);
 221 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 222                                          u8 *data);
 223 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 224                                          u16 *data);
 225 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 226                                          u8 size, u16 *data);
 227 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 228 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 229 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 230 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 231 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 232 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 233 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 234 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 235 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 236 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 237 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 238 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 239 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 240 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 241 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 242 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 243 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 244 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 245 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 246 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 247
 248 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 249 {
 250         return readw(hw->flash_address + reg);
 251 }
 252
 253 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 254 {
 255         return readl(hw->flash_address + reg);
 256 }
 257
 258 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 259 {
 260         writew(val, hw->flash_address + reg);
 261 }
 262
 263 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 264 {
 265         writel(val, hw->flash_address + reg);
 266 }
 267
 268 #define er16flash(reg)          __er16flash(hw, (reg))
 269 #define er32flash(reg)          __er32flash(hw, (reg))
 270 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 271 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 272
 273 /**
 274  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 275  *  @hw: pointer to the HW structure
 276  *
 277  *  Initialize family-specific PHY parameters and function pointers.
 278  **/
 279 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 280 {
 281         struct e1000_phy_info *phy = &hw->phy;
 282         u32 ctrl, fwsm;
 283         s32 ret_val = 0;
 284
 285         phy->addr                     = 1;
 286         phy->reset_delay_us           = 100;
 287
 288         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 289         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 290         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 291         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 292         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 293         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 294         phy->ops.power_up             = e1000_power_up_phy_copper;
 295         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 296         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 297
 298         /*
 299          * The MAC-PHY interconnect may still be in SMBus mode
 300          * after Sx->S0.  If the manageability engine (ME) is
 301          * disabled, then toggle the LANPHYPC Value bit to force
 302          * the interconnect to PCIe mode.
 303          */
 304         fwsm = er32(FWSM);
 305         if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 306                 ctrl = er32(CTRL);
 307                 ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
 308                 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 309                 ew32(CTRL, ctrl);
 310                 udelay(10);
 311                 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 312                 ew32(CTRL, ctrl);
 313                 msleep(50);
 314
 315                 /*
 316                  * Gate automatic PHY configuration by hardware on
 317                  * non-managed 82579
 318                  */
 319                 if (hw->mac.type == e1000_pch2lan)
 320                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 321         }
 322
 323         /*
 324          * Reset the PHY before any access to it.  Doing so, ensures that
 325          * the PHY is in a known good state before we read/write PHY registers.
 326          * The generic reset is sufficient here, because we haven't determined
 327          * the PHY type yet.
 328          */
 329         ret_val = e1000e_phy_hw_reset_generic(hw);
 330         if (ret_val)
 331                 goto out;
 332
 333         /* Ungate automatic PHY configuration on non-managed 82579 */
 334         if ((hw->mac.type == e1000_pch2lan)  &&
 335             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 336                 msleep(10);
 337                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 338         }
 339
 340         phy->id = e1000_phy_unknown;
 341         switch (hw->mac.type) {
 342         default:
 343                 ret_val = e1000e_get_phy_id(hw);
 344                 if (ret_val)
 345                         goto out;
 346                 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 347                         break;
 348                 /* fall-through */
 349         case e1000_pch2lan:
 350                 /*
 351                  * In case the PHY needs to be in mdio slow mode,
 352                  * set slow mode and try to get the PHY id again.
 353                  */
 354                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 355                 if (ret_val)
 356                         goto out;
 357                 ret_val = e1000e_get_phy_id(hw);
 358                 if (ret_val)
 359                         goto out;
 360                 break;
 361         }
 362         phy->type = e1000e_get_phy_type_from_id(phy->id);
 363
 364         switch (phy->type) {
 365         case e1000_phy_82577:
 366         case e1000_phy_82579:
 367                 phy->ops.check_polarity = e1000_check_polarity_82577;
 368                 phy->ops.force_speed_duplex =
 369                         e1000_phy_force_speed_duplex_82577;
 370                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 371                 phy->ops.get_info = e1000_get_phy_info_82577;
 372                 phy->ops.commit = e1000e_phy_sw_reset;
 373                 break;
 374         case e1000_phy_82578:
 375                 phy->ops.check_polarity = e1000_check_polarity_m88;
 376                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 377                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 378                 phy->ops.get_info = e1000e_get_phy_info_m88;
 379                 break;
 380         default:
 381                 ret_val = -E1000_ERR_PHY;
 382                 break;
 383         }
 384
 385 out:
 386         return ret_val;
 387 }
 388
 389 /**
 390  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 391  *  @hw: pointer to the HW structure
 392  *
 393  *  Initialize family-specific PHY parameters and function pointers.
 394  **/
 395 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 396 {
 397         struct e1000_phy_info *phy = &hw->phy;
 398         s32 ret_val;
 399         u16 i = 0;
 400
 401         phy->addr                       = 1;
 402         phy->reset_delay_us             = 100;
 403
 404         phy->ops.power_up               = e1000_power_up_phy_copper;
 405         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 406
 407         /*
 408          * We may need to do this twice - once for IGP and if that fails,
 409          * we'll set BM func pointers and try again
 410          */
 411         ret_val = e1000e_determine_phy_address(hw);
 412         if (ret_val) {
 413                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 414                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 415                 ret_val = e1000e_determine_phy_address(hw);
 416                 if (ret_val) {
 417                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 418                         return ret_val;
 419                 }
 420         }
 421
 422         phy->id = 0;
 423         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 424                (i++ < 100)) {
 425                 msleep(1);
 426                 ret_val = e1000e_get_phy_id(hw);
 427                 if (ret_val)
 428                         return ret_val;
 429         }
 430
 431         /* Verify phy id */
 432         switch (phy->id) {
 433         case IGP03E1000_E_PHY_ID:
 434                 phy->type = e1000_phy_igp_3;
 435                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 436                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 437                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 438                 phy->ops.get_info = e1000e_get_phy_info_igp;
 439                 phy->ops.check_polarity = e1000_check_polarity_igp;
 440                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 441                 break;
 442         case IFE_E_PHY_ID:
 443         case IFE_PLUS_E_PHY_ID:
 444         case IFE_C_E_PHY_ID:
 445                 phy->type = e1000_phy_ife;
 446                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 447                 phy->ops.get_info = e1000_get_phy_info_ife;
 448                 phy->ops.check_polarity = e1000_check_polarity_ife;
 449                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 450                 break;
 451         case BME1000_E_PHY_ID:
 452                 phy->type = e1000_phy_bm;
 453                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 454                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 455                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 456                 phy->ops.commit = e1000e_phy_sw_reset;
 457                 phy->ops.get_info = e1000e_get_phy_info_m88;
 458                 phy->ops.check_polarity = e1000_check_polarity_m88;
 459                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 460                 break;
 461         default:
 462                 return -E1000_ERR_PHY;
 463                 break;
 464         }
 465
 466         return 0;
 467 }
 468
 469 /**
 470  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 471  *  @hw: pointer to the HW structure
 472  *
 473  *  Initialize family-specific NVM parameters and function
 474  *  pointers.
 475  **/
 476 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 477 {
 478         struct e1000_nvm_info *nvm = &hw->nvm;
 479         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 480         u32 gfpreg, sector_base_addr, sector_end_addr;
 481         u16 i;
 482
 483         /* Can't read flash registers if the register set isn't mapped. */
 484         if (!hw->flash_address) {
 485                 e_dbg("ERROR: Flash registers not mapped\n");
 486                 return -E1000_ERR_CONFIG;
 487         }
 488
 489         nvm->type = e1000_nvm_flash_sw;
 490
 491         gfpreg = er32flash(ICH_FLASH_GFPREG);
 492
 493         /*
 494          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 495          * Add 1 to sector_end_addr since this sector is included in
 496          * the overall size.
 497          */
 498         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 499         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 500
 501         /* flash_base_addr is byte-aligned */
 502         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 503
 504         /*
 505          * find total size of the NVM, then cut in half since the total
 506          * size represents two separate NVM banks.
 507          */
 508         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 509                                 << FLASH_SECTOR_ADDR_SHIFT;
 510         nvm->flash_bank_size /= 2;
 511         /* Adjust to word count */
 512         nvm->flash_bank_size /= sizeof(u16);
 513
 514         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 515
 516         /* Clear shadow ram */
 517         for (i = 0; i < nvm->word_size; i++) {
 518                 dev_spec->shadow_ram[i].modified = false;
 519                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 520         }
 521
 522         return 0;
 523 }
 524
 525 /**
 526  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 527  *  @hw: pointer to the HW structure
 528  *
 529  *  Initialize family-specific MAC parameters and function
 530  *  pointers.
 531  **/
 532 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 533 {
 534         struct e1000_hw *hw = &adapter->hw;
 535         struct e1000_mac_info *mac = &hw->mac;
 536
 537         /* Set media type function pointer */
 538         hw->phy.media_type = e1000_media_type_copper;
 539
 540         /* Set mta register count */
 541         mac->mta_reg_count = 32;
 542         /* Set rar entry count */
 543         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 544         if (mac->type == e1000_ich8lan)
 545                 mac->rar_entry_count--;
 546         /* FWSM register */
 547         mac->has_fwsm = true;
 548         /* ARC subsystem not supported */
 549         mac->arc_subsystem_valid = false;
 550         /* Adaptive IFS supported */
 551         mac->adaptive_ifs = true;
 552
 553         /* LED operations */
 554         switch (mac->type) {
 555         case e1000_ich8lan:
 556         case e1000_ich9lan:
 557         case e1000_ich10lan:
 558                 /* check management mode */
 559                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 560                 /* ID LED init */
 561                 mac->ops.id_led_init = e1000e_id_led_init;
 562                 /* setup LED */
 563                 mac->ops.setup_led = e1000e_setup_led_generic;
 564                 /* cleanup LED */
 565                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 566                 /* turn on/off LED */
 567                 mac->ops.led_on = e1000_led_on_ich8lan;
 568                 mac->ops.led_off = e1000_led_off_ich8lan;
 569                 break;
 570         case e1000_pchlan:
 571         case e1000_pch2lan:
 572                 /* check management mode */
 573                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 574                 /* ID LED init */
 575                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 576                 /* setup LED */
 577                 mac->ops.setup_led = e1000_setup_led_pchlan;
 578                 /* cleanup LED */
 579                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 580                 /* turn on/off LED */
 581                 mac->ops.led_on = e1000_led_on_pchlan;
 582                 mac->ops.led_off = e1000_led_off_pchlan;
 583                 break;
 584         default:
 585                 break;
 586         }
 587
 588         /* Enable PCS Lock-loss workaround for ICH8 */
 589         if (mac->type == e1000_ich8lan)
 590                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 591
 592         /* Gate automatic PHY configuration by hardware on managed 82579 */
 593         if ((mac->type == e1000_pch2lan) &&
 594             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 595                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 596
 597         return 0;
 598 }
 599
 600 /**
 601  *  e1000_set_eee_pchlan - Enable/disable EEE support
 602  *  @hw: pointer to the HW structure
 603  *
 604  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 605  *  the LPI Control register will remain set only if/when link is up.
 606  **/
 607 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 608 {
 609         s32 ret_val = 0;
 610         u16 phy_reg;
 611
 612         if (hw->phy.type != e1000_phy_82579)
 613                 goto out;
 614
 615         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 616         if (ret_val)
 617                 goto out;
 618
 619         if (hw->dev_spec.ich8lan.eee_disable)
 620                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 621         else
 622                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 623
 624         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 625 out:
 626         return ret_val;
 627 }
 628
 629 /**
 630  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 631  *  @hw: pointer to the HW structure
 632  *
 633  *  Checks to see of the link status of the hardware has changed.  If a
 634  *  change in link status has been detected, then we read the PHY registers
 635  *  to get the current speed/duplex if link exists.
 636  **/
 637 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 638 {
 639         struct e1000_mac_info *mac = &hw->mac;
 640         s32 ret_val;
 641         bool link;
 642
 643         /*
 644          * We only want to go out to the PHY registers to see if Auto-Neg
 645          * has completed and/or if our link status has changed.  The
 646          * get_link_status flag is set upon receiving a Link Status
 647          * Change or Rx Sequence Error interrupt.
 648          */
 649         if (!mac->get_link_status) {
 650                 ret_val = 0;
 651                 goto out;
 652         }
 653
 654         /*
 655          * First we want to see if the MII Status Register reports
 656          * link.  If so, then we want to get the current speed/duplex
 657          * of the PHY.
 658          */
 659         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 660         if (ret_val)
 661                 goto out;
 662
 663         if (hw->mac.type == e1000_pchlan) {
 664                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 665                 if (ret_val)
 666                         goto out;
 667         }
 668
 669         if (!link)
 670                 goto out; /* No link detected */
 671
 672         mac->get_link_status = false;
 673
 674         if (hw->phy.type == e1000_phy_82578) {
 675                 ret_val = e1000_link_stall_workaround_hv(hw);
 676                 if (ret_val)
 677                         goto out;
 678         }
 679
 680         if (hw->mac.type == e1000_pch2lan) {
 681                 ret_val = e1000_k1_workaround_lv(hw);
 682                 if (ret_val)
 683                         goto out;
 684         }
 685
 686         /*
 687          * Check if there was DownShift, must be checked
 688          * immediately after link-up
 689          */
 690         e1000e_check_downshift(hw);
 691
 692         /* Enable/Disable EEE after link up */
 693         ret_val = e1000_set_eee_pchlan(hw);
 694         if (ret_val)
 695                 goto out;
 696
 697         /*
 698          * If we are forcing speed/duplex, then we simply return since
 699          * we have already determined whether we have link or not.
 700          */
 701         if (!mac->autoneg) {
 702                 ret_val = -E1000_ERR_CONFIG;
 703                 goto out;
 704         }
 705
 706         /*
 707          * Auto-Neg is enabled.  Auto Speed Detection takes care
 708          * of MAC speed/duplex configuration.  So we only need to
 709          * configure Collision Distance in the MAC.
 710          */
 711         e1000e_config_collision_dist(hw);
 712
 713         /*
 714          * Configure Flow Control now that Auto-Neg has completed.
 715          * First, we need to restore the desired flow control
 716          * settings because we may have had to re-autoneg with a
 717          * different link partner.
 718          */
 719         ret_val = e1000e_config_fc_after_link_up(hw);
 720         if (ret_val)
 721                 e_dbg("Error configuring flow control\n");
 722
 723 out:
 724         return ret_val;
 725 }
 726
 727 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 728 {
 729         struct e1000_hw *hw = &adapter->hw;
 730         s32 rc;
 731
 732         rc = e1000_init_mac_params_ich8lan(adapter);
 733         if (rc)
 734                 return rc;
 735
 736         rc = e1000_init_nvm_params_ich8lan(hw);
 737         if (rc)
 738                 return rc;
 739
 740         switch (hw->mac.type) {
 741         case e1000_ich8lan:
 742         case e1000_ich9lan:
 743         case e1000_ich10lan:
 744                 rc = e1000_init_phy_params_ich8lan(hw);
 745                 break;
 746         case e1000_pchlan:
 747         case e1000_pch2lan:
 748                 rc = e1000_init_phy_params_pchlan(hw);
 749                 break;
 750         default:
 751                 break;
 752         }
 753         if (rc)
 754                 return rc;
 755
 756         if (adapter->hw.phy.type == e1000_phy_ife) {
 757                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 758                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 759         }
 760
 761         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 762             (adapter->hw.phy.type == e1000_phy_igp_3))
 763                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 764
 765         /* Disable EEE by default until IEEE802.3az spec is finalized */
 766         if (adapter->flags2 & FLAG2_HAS_EEE)
 767                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 768
 769         return 0;
 770 }
 771
 772 static DEFINE_MUTEX(nvm_mutex);
 773
 774 /**
 775  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 776  *  @hw: pointer to the HW structure
 777  *
 778  *  Acquires the mutex for performing NVM operations.
 779  **/
 780 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 781 {
 782         mutex_lock(&nvm_mutex);
 783
 784         return 0;
 785 }
 786
 787 /**
 788  *  e1000_release_nvm_ich8lan - Release NVM mutex
 789  *  @hw: pointer to the HW structure
 790  *
 791  *  Releases the mutex used while performing NVM operations.
 792  **/
 793 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 794 {
 795         mutex_unlock(&nvm_mutex);
 796 }
 797
 798 static DEFINE_MUTEX(swflag_mutex);
 799
 800 /**
 801  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 802  *  @hw: pointer to the HW structure
 803  *
 804  *  Acquires the software control flag for performing PHY and select
 805  *  MAC CSR accesses.
 806  **/
 807 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 808 {
 809         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 810         s32 ret_val = 0;
 811
 812         mutex_lock(&swflag_mutex);
 813
 814         while (timeout) {
 815                 extcnf_ctrl = er32(EXTCNF_CTRL);
 816                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 817                         break;
 818
 819                 mdelay(1);
 820                 timeout--;
 821         }
 822
 823         if (!timeout) {
 824                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 825                 ret_val = -E1000_ERR_CONFIG;
 826                 goto out;
 827         }
 828
 829         timeout = SW_FLAG_TIMEOUT;
 830
 831         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 832         ew32(EXTCNF_CTRL, extcnf_ctrl);
 833
 834         while (timeout) {
 835                 extcnf_ctrl = er32(EXTCNF_CTRL);
 836                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 837                         break;
 838
 839                 mdelay(1);
 840                 timeout--;
 841         }
 842
 843         if (!timeout) {
 844                 e_dbg("Failed to acquire the semaphore.\n");
 845                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 846                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 847                 ret_val = -E1000_ERR_CONFIG;
 848                 goto out;
 849         }
 850
 851 out:
 852         if (ret_val)
 853                 mutex_unlock(&swflag_mutex);
 854
 855         return ret_val;
 856 }
 857
 858 /**
 859  *  e1000_release_swflag_ich8lan - Release software control flag
 860  *  @hw: pointer to the HW structure
 861  *
 862  *  Releases the software control flag for performing PHY and select
 863  *  MAC CSR accesses.
 864  **/
 865 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 866 {
 867         u32 extcnf_ctrl;
 868
 869         extcnf_ctrl = er32(EXTCNF_CTRL);
 870         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 871         ew32(EXTCNF_CTRL, extcnf_ctrl);
 872
 873         mutex_unlock(&swflag_mutex);
 874 }
 875
 876 /**
 877  *  e1000_check_mng_mode_ich8lan - Checks management mode
 878  *  @hw: pointer to the HW structure
 879  *
 880  *  This checks if the adapter has any manageability enabled.
 881  *  This is a function pointer entry point only called by read/write
 882  *  routines for the PHY and NVM parts.
 883  **/
 884 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 885 {
 886         u32 fwsm;
 887
 888         fwsm = er32(FWSM);
 889         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 890                ((fwsm & E1000_FWSM_MODE_MASK) ==
 891                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 892 }
 893
 894 /**
 895  *  e1000_check_mng_mode_pchlan - Checks management mode
 896  *  @hw: pointer to the HW structure
 897  *
 898  *  This checks if the adapter has iAMT enabled.
 899  *  This is a function pointer entry point only called by read/write
 900  *  routines for the PHY and NVM parts.
 901  **/
 902 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 903 {
 904         u32 fwsm;
 905
 906         fwsm = er32(FWSM);
 907         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 908                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 909 }
 910
 911 /**
 912  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 913  *  @hw: pointer to the HW structure
 914  *
 915  *  Checks if firmware is blocking the reset of the PHY.
 916  *  This is a function pointer entry point only called by
 917  *  reset routines.
 918  **/
 919 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 920 {
 921         u32 fwsm;
 922
 923         fwsm = er32(FWSM);
 924
 925         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 926 }
 927
 928 /**
 929  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 930  *  @hw: pointer to the HW structure
 931  *
 932  *  Assumes semaphore already acquired.
 933  *
 934  **/
 935 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
 936 {
 937         u16 phy_data;
 938         u32 strap = er32(STRAP);
 939         s32 ret_val = 0;
 940
 941         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 942
 943         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
 944         if (ret_val)
 945                 goto out;
 946
 947         phy_data &= ~HV_SMB_ADDR_MASK;
 948         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
 949         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 950         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
 951
 952 out:
 953         return ret_val;
 954 }
 955
 956 /**
 957  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 958  *  @hw:   pointer to the HW structure
 959  *
 960  *  SW should configure the LCD from the NVM extended configuration region
 961  *  as a workaround for certain parts.
 962  **/
 963 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 964 {
 965         struct e1000_phy_info *phy = &hw->phy;
 966         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 967         s32 ret_val = 0;
 968         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 969
 970         /*
 971          * Initialize the PHY from the NVM on ICH platforms.  This
 972          * is needed due to an issue where the NVM configuration is
 973          * not properly autoloaded after power transitions.
 974          * Therefore, after each PHY reset, we will load the
 975          * configuration data out of the NVM manually.
 976          */
 977         switch (hw->mac.type) {
 978         case e1000_ich8lan:
 979                 if (phy->type != e1000_phy_igp_3)
 980                         return ret_val;
 981
 982                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
 983                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
 984                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 985                         break;
 986                 }
 987                 /* Fall-thru */
 988         case e1000_pchlan:
 989         case e1000_pch2lan:
 990                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 991                 break;
 992         default:
 993                 return ret_val;
 994         }
 995
 996         ret_val = hw->phy.ops.acquire(hw);
 997         if (ret_val)
 998                 return ret_val;
 999
1000         data = er32(FEXTNVM);
1001         if (!(data & sw_cfg_mask))
1002                 goto out;
1003
1004         /*
1005          * Make sure HW does not configure LCD from PHY
1006          * extended configuration before SW configuration
1007          */
1008         data = er32(EXTCNF_CTRL);
1009         if (!(hw->mac.type == e1000_pch2lan)) {
1010                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1011                         goto out;
1012         }
1013
1014         cnf_size = er32(EXTCNF_SIZE);
1015         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1016         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1017         if (!cnf_size)
1018                 goto out;
1019
1020         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1021         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1022
1023         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1024             (hw->mac.type == e1000_pchlan)) ||
1025              (hw->mac.type == e1000_pch2lan)) {
1026                 /*
1027                  * HW configures the SMBus address and LEDs when the
1028                  * OEM and LCD Write Enable bits are set in the NVM.
1029                  * When both NVM bits are cleared, SW will configure
1030                  * them instead.
1031                  */
1032                 ret_val = e1000_write_smbus_addr(hw);
1033                 if (ret_val)
1034                         goto out;
1035
1036                 data = er32(LEDCTL);
1037                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1038                                                         (u16)data);
1039                 if (ret_val)
1040                         goto out;
1041         }
1042
1043         /* Configure LCD from extended configuration region. */
1044
1045         /* cnf_base_addr is in DWORD */
1046         word_addr = (u16)(cnf_base_addr << 1);
1047
1048         for (i = 0; i < cnf_size; i++) {
1049                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1050                                          &reg_data);
1051                 if (ret_val)
1052                         goto out;
1053
1054                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1055                                          1, &reg_addr);
1056                 if (ret_val)
1057                         goto out;
1058
1059                 /* Save off the PHY page for future writes. */
1060                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1061                         phy_page = reg_data;
1062                         continue;
1063                 }
1064
1065                 reg_addr &= PHY_REG_MASK;
1066                 reg_addr |= phy_page;
1067
1068                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1069                                                     reg_data);
1070                 if (ret_val)
1071                         goto out;
1072         }
1073
1074 out:
1075         hw->phy.ops.release(hw);
1076         return ret_val;
1077 }
1078
1079 /**
1080  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1081  *  @hw:   pointer to the HW structure
1082  *  @link: link up bool flag
1083  *
1084  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1085  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1086  *  If link is down, the function will restore the default K1 setting located
1087  *  in the NVM.
1088  **/
1089 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1090 {
1091         s32 ret_val = 0;
1092         u16 status_reg = 0;
1093         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1094
1095         if (hw->mac.type != e1000_pchlan)
1096                 goto out;
1097
1098         /* Wrap the whole flow with the sw flag */
1099         ret_val = hw->phy.ops.acquire(hw);
1100         if (ret_val)
1101                 goto out;
1102
1103         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1104         if (link) {
1105                 if (hw->phy.type == e1000_phy_82578) {
1106                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1107                                                                   &status_reg);
1108                         if (ret_val)
1109                                 goto release;
1110
1111                         status_reg &= BM_CS_STATUS_LINK_UP |
1112                                       BM_CS_STATUS_RESOLVED |
1113                                       BM_CS_STATUS_SPEED_MASK;
1114
1115                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1116                                            BM_CS_STATUS_RESOLVED |
1117                                            BM_CS_STATUS_SPEED_1000))
1118                                 k1_enable = false;
1119                 }
1120
1121                 if (hw->phy.type == e1000_phy_82577) {
1122                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1123                                                                   &status_reg);
1124                         if (ret_val)
1125                                 goto release;
1126
1127                         status_reg &= HV_M_STATUS_LINK_UP |
1128                                       HV_M_STATUS_AUTONEG_COMPLETE |
1129                                       HV_M_STATUS_SPEED_MASK;
1130
1131                         if (status_reg == (HV_M_STATUS_LINK_UP |
1132                                            HV_M_STATUS_AUTONEG_COMPLETE |
1133                                            HV_M_STATUS_SPEED_1000))
1134                                 k1_enable = false;
1135                 }
1136
1137                 /* Link stall fix for link up */
1138                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1139                                                            0x0100);
1140                 if (ret_val)
1141                         goto release;
1142
1143         } else {
1144                 /* Link stall fix for link down */
1145                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1146                                                            0x4100);
1147                 if (ret_val)
1148                         goto release;
1149         }
1150
1151         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1152
1153 release:
1154         hw->phy.ops.release(hw);
1155 out:
1156         return ret_val;
1157 }
1158
1159 /**
1160  *  e1000_configure_k1_ich8lan - Configure K1 power state
1161  *  @hw: pointer to the HW structure
1162  *  @enable: K1 state to configure
1163  *
1164  *  Configure the K1 power state based on the provided parameter.
1165  *  Assumes semaphore already acquired.
1166  *
1167  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1168  **/
1169 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1170 {
1171         s32 ret_val = 0;
1172         u32 ctrl_reg = 0;
1173         u32 ctrl_ext = 0;
1174         u32 reg = 0;
1175         u16 kmrn_reg = 0;
1176
1177         ret_val = e1000e_read_kmrn_reg_locked(hw,
1178                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1179                                              &kmrn_reg);
1180         if (ret_val)
1181                 goto out;
1182
1183         if (k1_enable)
1184                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1185         else
1186                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1187
1188         ret_val = e1000e_write_kmrn_reg_locked(hw,
1189                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1190                                               kmrn_reg);
1191         if (ret_val)
1192                 goto out;
1193
1194         udelay(20);
1195         ctrl_ext = er32(CTRL_EXT);
1196         ctrl_reg = er32(CTRL);
1197
1198         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1199         reg |= E1000_CTRL_FRCSPD;
1200         ew32(CTRL, reg);
1201
1202         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1203         udelay(20);
1204         ew32(CTRL, ctrl_reg);
1205         ew32(CTRL_EXT, ctrl_ext);
1206         udelay(20);
1207
1208 out:
1209         return ret_val;
1210 }
1211
1212 /**
1213  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1214  *  @hw:       pointer to the HW structure
1215  *  @d0_state: boolean if entering d0 or d3 device state
1216  *
1217  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1218  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1219  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1220  **/
1221 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1222 {
1223         s32 ret_val = 0;
1224         u32 mac_reg;
1225         u16 oem_reg;
1226
1227         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1228                 return ret_val;
1229
1230         ret_val = hw->phy.ops.acquire(hw);
1231         if (ret_val)
1232                 return ret_val;
1233
1234         if (!(hw->mac.type == e1000_pch2lan)) {
1235                 mac_reg = er32(EXTCNF_CTRL);
1236                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1237                         goto out;
1238         }
1239
1240         mac_reg = er32(FEXTNVM);
1241         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1242                 goto out;
1243
1244         mac_reg = er32(PHY_CTRL);
1245
1246         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1247         if (ret_val)
1248                 goto out;
1249
1250         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1251
1252         if (d0_state) {
1253                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1254                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1255
1256                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1257                         oem_reg |= HV_OEM_BITS_LPLU;
1258         } else {
1259                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1260                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1261
1262                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1263                         oem_reg |= HV_OEM_BITS_LPLU;
1264         }
1265         /* Restart auto-neg to activate the bits */
1266         if (!e1000_check_reset_block(hw))
1267                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1268         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1269
1270 out:
1271         hw->phy.ops.release(hw);
1272
1273         return ret_val;
1274 }
1275
1276
1277 /**
1278  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1279  *  @hw:   pointer to the HW structure
1280  **/
1281 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1282 {
1283         s32 ret_val;
1284         u16 data;
1285
1286         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1287         if (ret_val)
1288                 return ret_val;
1289
1290         data |= HV_KMRN_MDIO_SLOW;
1291
1292         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1293
1294         return ret_val;
1295 }
1296
1297 /**
1298  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1299  *  done after every PHY reset.
1300  **/
1301 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1302 {
1303         s32 ret_val = 0;
1304         u16 phy_data;
1305
1306         if (hw->mac.type != e1000_pchlan)
1307                 return ret_val;
1308
1309         /* Set MDIO slow mode before any other MDIO access */
1310         if (hw->phy.type == e1000_phy_82577) {
1311                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1312                 if (ret_val)
1313                         goto out;
1314         }
1315
1316         if (((hw->phy.type == e1000_phy_82577) &&
1317              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1318             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1319                 /* Disable generation of early preamble */
1320                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1321                 if (ret_val)
1322                         return ret_val;
1323
1324                 /* Preamble tuning for SSC */
1325                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1326                 if (ret_val)
1327                         return ret_val;
1328         }
1329
1330         if (hw->phy.type == e1000_phy_82578) {
1331                 /*
1332                  * Return registers to default by doing a soft reset then
1333                  * writing 0x3140 to the control register.
1334                  */
1335                 if (hw->phy.revision < 2) {
1336                         e1000e_phy_sw_reset(hw);
1337                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1338                 }
1339         }
1340
1341         /* Select page 0 */
1342         ret_val = hw->phy.ops.acquire(hw);
1343         if (ret_val)
1344                 return ret_val;
1345
1346         hw->phy.addr = 1;
1347         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1348         hw->phy.ops.release(hw);
1349         if (ret_val)
1350                 goto out;
1351
1352         /*
1353          * Configure the K1 Si workaround during phy reset assuming there is
1354          * link so that it disables K1 if link is in 1Gbps.
1355          */
1356         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1357         if (ret_val)
1358                 goto out;
1359
1360         /* Workaround for link disconnects on a busy hub in half duplex */
1361         ret_val = hw->phy.ops.acquire(hw);
1362         if (ret_val)
1363                 goto out;
1364         ret_val = hw->phy.ops.read_reg_locked(hw,
1365                                               PHY_REG(BM_PORT_CTRL_PAGE, 17),
1366                                               &phy_data);
1367         if (ret_val)
1368                 goto release;
1369         ret_val = hw->phy.ops.write_reg_locked(hw,
1370                                                PHY_REG(BM_PORT_CTRL_PAGE, 17),
1371                                                phy_data & 0x00FF);
1372 release:
1373         hw->phy.ops.release(hw);
1374 out:
1375         return ret_val;
1376 }
1377
1378 /**
1379  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1380  *  @hw:   pointer to the HW structure
1381  **/
1382 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1383 {
1384         u32 mac_reg;
1385         u16 i;
1386
1387         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1388         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1389                 mac_reg = er32(RAL(i));
1390                 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1391                 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1392                 mac_reg = er32(RAH(i));
1393                 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1394                 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1395         }
1396 }
1397
1398 /**
1399  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1400  *  with 82579 PHY
1401  *  @hw: pointer to the HW structure
1402  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1403  **/
1404 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1405 {
1406         s32 ret_val = 0;
1407         u16 phy_reg, data;
1408         u32 mac_reg;
1409         u16 i;
1410
1411         if (hw->mac.type != e1000_pch2lan)
1412                 goto out;
1413
1414         /* disable Rx path while enabling/disabling workaround */
1415         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1416         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1417         if (ret_val)
1418                 goto out;
1419
1420         if (enable) {
1421                 /*
1422                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1423                  * SHRAL/H) and initial CRC values to the MAC
1424                  */
1425                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1426                         u8 mac_addr[ETH_ALEN] = {0};
1427                         u32 addr_high, addr_low;
1428
1429                         addr_high = er32(RAH(i));
1430                         if (!(addr_high & E1000_RAH_AV))
1431                                 continue;
1432                         addr_low = er32(RAL(i));
1433                         mac_addr[0] = (addr_low & 0xFF);
1434                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1435                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1436                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1437                         mac_addr[4] = (addr_high & 0xFF);
1438                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1439
1440                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1441                 }
1442
1443                 /* Write Rx addresses to the PHY */
1444                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1445
1446                 /* Enable jumbo frame workaround in the MAC */
1447                 mac_reg = er32(FFLT_DBG);
1448                 mac_reg &= ~(1 << 14);
1449                 mac_reg |= (7 << 15);
1450                 ew32(FFLT_DBG, mac_reg);
1451
1452                 mac_reg = er32(RCTL);
1453                 mac_reg |= E1000_RCTL_SECRC;
1454                 ew32(RCTL, mac_reg);
1455
1456                 ret_val = e1000e_read_kmrn_reg(hw,
1457                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1458                                                 &data);
1459                 if (ret_val)
1460                         goto out;
1461                 ret_val = e1000e_write_kmrn_reg(hw,
1462                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1463                                                 data | (1 << 0));
1464                 if (ret_val)
1465                         goto out;
1466                 ret_val = e1000e_read_kmrn_reg(hw,
1467                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1468                                                 &data);
1469                 if (ret_val)
1470                         goto out;
1471                 data &= ~(0xF << 8);
1472                 data |= (0xB << 8);
1473                 ret_val = e1000e_write_kmrn_reg(hw,
1474                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1475                                                 data);
1476                 if (ret_val)
1477                         goto out;
1478
1479                 /* Enable jumbo frame workaround in the PHY */
1480                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1481                 data &= ~(0x7F << 5);
1482                 data |= (0x37 << 5);
1483                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1484                 if (ret_val)
1485                         goto out;
1486                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1487                 data &= ~(1 << 13);
1488                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1489                 if (ret_val)
1490                         goto out;
1491                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1492                 data &= ~(0x3FF << 2);
1493                 data |= (0x1A << 2);
1494                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1495                 if (ret_val)
1496                         goto out;
1497                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1498                 if (ret_val)
1499                         goto out;
1500                 e1e_rphy(hw, HV_PM_CTRL, &data);
1501                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1502                 if (ret_val)
1503                         goto out;
1504         } else {
1505                 /* Write MAC register values back to h/w defaults */
1506                 mac_reg = er32(FFLT_DBG);
1507                 mac_reg &= ~(0xF << 14);
1508                 ew32(FFLT_DBG, mac_reg);
1509
1510                 mac_reg = er32(RCTL);
1511                 mac_reg &= ~E1000_RCTL_SECRC;
1512                 ew32(RCTL, mac_reg);
1513
1514                 ret_val = e1000e_read_kmrn_reg(hw,
1515                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1516                                                 &data);
1517                 if (ret_val)
1518                         goto out;
1519                 ret_val = e1000e_write_kmrn_reg(hw,
1520                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1521                                                 data & ~(1 << 0));
1522                 if (ret_val)
1523                         goto out;
1524                 ret_val = e1000e_read_kmrn_reg(hw,
1525                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1526                                                 &data);
1527                 if (ret_val)
1528                         goto out;
1529                 data &= ~(0xF << 8);
1530                 data |= (0xB << 8);
1531                 ret_val = e1000e_write_kmrn_reg(hw,
1532                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1533                                                 data);
1534                 if (ret_val)
1535                         goto out;
1536
1537                 /* Write PHY register values back to h/w defaults */
1538                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1539                 data &= ~(0x7F << 5);
1540                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1541                 if (ret_val)
1542                         goto out;
1543                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1544                 data |= (1 << 13);
1545                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1546                 if (ret_val)
1547                         goto out;
1548                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1549                 data &= ~(0x3FF << 2);
1550                 data |= (0x8 << 2);
1551                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1552                 if (ret_val)
1553                         goto out;
1554                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1555                 if (ret_val)
1556                         goto out;
1557                 e1e_rphy(hw, HV_PM_CTRL, &data);
1558                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1559                 if (ret_val)
1560                         goto out;
1561         }
1562
1563         /* re-enable Rx path after enabling/disabling workaround */
1564         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1565
1566 out:
1567         return ret_val;
1568 }
1569
1570 /**
1571  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1572  *  done after every PHY reset.
1573  **/
1574 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1575 {
1576         s32 ret_val = 0;
1577
1578         if (hw->mac.type != e1000_pch2lan)
1579                 goto out;
1580
1581         /* Set MDIO slow mode before any other MDIO access */
1582         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1583
1584 out:
1585         return ret_val;
1586 }
1587
1588 /**
1589  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1590  *  @hw:   pointer to the HW structure
1591  *
1592  *  Workaround to set the K1 beacon duration for 82579 parts
1593  **/
1594 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1595 {
1596         s32 ret_val = 0;
1597         u16 status_reg = 0;
1598         u32 mac_reg;
1599
1600         if (hw->mac.type != e1000_pch2lan)
1601                 goto out;
1602
1603         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1604         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1605         if (ret_val)
1606                 goto out;
1607
1608         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1609             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1610                 mac_reg = er32(FEXTNVM4);
1611                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1612
1613                 if (status_reg & HV_M_STATUS_SPEED_1000)
1614                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1615                 else
1616                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1617
1618                 ew32(FEXTNVM4, mac_reg);
1619         }
1620
1621 out:
1622         return ret_val;
1623 }
1624
1625 /**
1626  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1627  *  @hw:   pointer to the HW structure
1628  *  @gate: boolean set to true to gate, false to ungate
1629  *
1630  *  Gate/ungate the automatic PHY configuration via hardware; perform
1631  *  the configuration via software instead.
1632  **/
1633 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1634 {
1635         u32 extcnf_ctrl;
1636
1637         if (hw->mac.type != e1000_pch2lan)
1638                 return;
1639
1640         extcnf_ctrl = er32(EXTCNF_CTRL);
1641
1642         if (gate)
1643                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1644         else
1645                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1646
1647         ew32(EXTCNF_CTRL, extcnf_ctrl);
1648         return;
1649 }
1650
1651 /**
1652  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1653  *  @hw: pointer to the HW structure
1654  *
1655  *  Check the appropriate indication the MAC has finished configuring the
1656  *  PHY after a software reset.
1657  **/
1658 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1659 {
1660         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1661
1662         /* Wait for basic configuration completes before proceeding */
1663         do {
1664                 data = er32(STATUS);
1665                 data &= E1000_STATUS_LAN_INIT_DONE;
1666                 udelay(100);
1667         } while ((!data) && --loop);
1668
1669         /*
1670          * If basic configuration is incomplete before the above loop
1671          * count reaches 0, loading the configuration from NVM will
1672          * leave the PHY in a bad state possibly resulting in no link.
1673          */
1674         if (loop == 0)
1675                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1676
1677         /* Clear the Init Done bit for the next init event */
1678         data = er32(STATUS);
1679         data &= ~E1000_STATUS_LAN_INIT_DONE;
1680         ew32(STATUS, data);
1681 }
1682
1683 /**
1684  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1685  *  @hw: pointer to the HW structure
1686  **/
1687 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1688 {
1689         s32 ret_val = 0;
1690         u16 reg;
1691
1692         if (e1000_check_reset_block(hw))
1693                 goto out;
1694
1695         /* Allow time for h/w to get to quiescent state after reset */
1696         msleep(10);
1697
1698         /* Perform any necessary post-reset workarounds */
1699         switch (hw->mac.type) {
1700         case e1000_pchlan:
1701                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1702                 if (ret_val)
1703                         goto out;
1704                 break;
1705         case e1000_pch2lan:
1706                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1707                 if (ret_val)
1708                         goto out;
1709                 break;
1710         default:
1711                 break;
1712         }
1713
1714         /* Dummy read to clear the phy wakeup bit after lcd reset */
1715         if (hw->mac.type >= e1000_pchlan)
1716                 e1e_rphy(hw, BM_WUC, &reg);
1717
1718         /* Configure the LCD with the extended configuration region in NVM */
1719         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1720         if (ret_val)
1721                 goto out;
1722
1723         /* Configure the LCD with the OEM bits in NVM */
1724         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1725
1726         /* Ungate automatic PHY configuration on non-managed 82579 */
1727         if ((hw->mac.type == e1000_pch2lan) &&
1728             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1729                 msleep(10);
1730                 e1000_gate_hw_phy_config_ich8lan(hw, false);
1731         }
1732
1733 out:
1734         return ret_val;
1735 }
1736
1737 /**
1738  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1739  *  @hw: pointer to the HW structure
1740  *
1741  *  Resets the PHY
1742  *  This is a function pointer entry point called by drivers
1743  *  or other shared routines.
1744  **/
1745 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1746 {
1747         s32 ret_val = 0;
1748
1749         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1750         if ((hw->mac.type == e1000_pch2lan) &&
1751             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1752                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1753
1754         ret_val = e1000e_phy_hw_reset_generic(hw);
1755         if (ret_val)
1756                 goto out;
1757
1758         ret_val = e1000_post_phy_reset_ich8lan(hw);
1759
1760 out:
1761         return ret_val;
1762 }
1763
1764 /**
1765  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1766  *  @hw: pointer to the HW structure
1767  *  @active: true to enable LPLU, false to disable
1768  *
1769  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1770  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1771  *  the phy speed. This function will manually set the LPLU bit and restart
1772  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1773  *  since it configures the same bit.
1774  **/
1775 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1776 {
1777         s32 ret_val = 0;
1778         u16 oem_reg;
1779
1780         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1781         if (ret_val)
1782                 goto out;
1783
1784         if (active)
1785                 oem_reg |= HV_OEM_BITS_LPLU;
1786         else
1787                 oem_reg &= ~HV_OEM_BITS_LPLU;
1788
1789         oem_reg |= HV_OEM_BITS_RESTART_AN;
1790         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1791
1792 out:
1793         return ret_val;
1794 }
1795
1796 /**
1797  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1798  *  @hw: pointer to the HW structure
1799  *  @active: true to enable LPLU, false to disable
1800  *
1801  *  Sets the LPLU D0 state according to the active flag.  When
1802  *  activating LPLU this function also disables smart speed
1803  *  and vice versa.  LPLU will not be activated unless the
1804  *  device autonegotiation advertisement meets standards of
1805  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1806  *  This is a function pointer entry point only called by
1807  *  PHY setup routines.
1808  **/
1809 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1810 {
1811         struct e1000_phy_info *phy = &hw->phy;
1812         u32 phy_ctrl;
1813         s32 ret_val = 0;
1814         u16 data;
1815
1816         if (phy->type == e1000_phy_ife)
1817                 return ret_val;
1818
1819         phy_ctrl = er32(PHY_CTRL);
1820
1821         if (active) {
1822                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1823                 ew32(PHY_CTRL, phy_ctrl);
1824
1825                 if (phy->type != e1000_phy_igp_3)
1826                         return 0;
1827
1828                 /*
1829                  * Call gig speed drop workaround on LPLU before accessing
1830                  * any PHY registers
1831                  */
1832                 if (hw->mac.type == e1000_ich8lan)
1833                         e1000e_gig_downshift_workaround_ich8lan(hw);
1834
1835                 /* When LPLU is enabled, we should disable SmartSpeed */
1836                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1837                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1838                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1839                 if (ret_val)
1840                         return ret_val;
1841         } else {
1842                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1843                 ew32(PHY_CTRL, phy_ctrl);
1844
1845                 if (phy->type != e1000_phy_igp_3)
1846                         return 0;
1847
1848                 /*
1849                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1850                  * during Dx states where the power conservation is most
1851                  * important.  During driver activity we should enable
1852                  * SmartSpeed, so performance is maintained.
1853                  */
1854                 if (phy->smart_speed == e1000_smart_speed_on) {
1855                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1856                                            &data);
1857                         if (ret_val)
1858                                 return ret_val;
1859
1860                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1861                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1862                                            data);
1863                         if (ret_val)
1864                                 return ret_val;
1865                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1866                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1867                                            &data);
1868                         if (ret_val)
1869                                 return ret_val;
1870
1871                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1872                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1873                                            data);
1874                         if (ret_val)
1875                                 return ret_val;
1876                 }
1877         }
1878
1879         return 0;
1880 }
1881
1882 /**
1883  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1884  *  @hw: pointer to the HW structure
1885  *  @active: true to enable LPLU, false to disable
1886  *
1887  *  Sets the LPLU D3 state according to the active flag.  When
1888  *  activating LPLU this function also disables smart speed
1889  *  and vice versa.  LPLU will not be activated unless the
1890  *  device autonegotiation advertisement meets standards of
1891  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1892  *  This is a function pointer entry point only called by
1893  *  PHY setup routines.
1894  **/
1895 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1896 {
1897         struct e1000_phy_info *phy = &hw->phy;
1898         u32 phy_ctrl;
1899         s32 ret_val;
1900         u16 data;
1901
1902         phy_ctrl = er32(PHY_CTRL);
1903
1904         if (!active) {
1905                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1906                 ew32(PHY_CTRL, phy_ctrl);
1907
1908                 if (phy->type != e1000_phy_igp_3)
1909                         return 0;
1910
1911                 /*
1912                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1913                  * during Dx states where the power conservation is most
1914                  * important.  During driver activity we should enable
1915                  * SmartSpeed, so performance is maintained.
1916                  */
1917                 if (phy->smart_speed == e1000_smart_speed_on) {
1918                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1919                                            &data);
1920                         if (ret_val)
1921                                 return ret_val;
1922
1923                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1924                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1925                                            data);
1926                         if (ret_val)
1927                                 return ret_val;
1928                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1929                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1930                                            &data);
1931                         if (ret_val)
1932                                 return ret_val;
1933
1934                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1935                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1936                                            data);
1937                         if (ret_val)
1938                                 return ret_val;
1939                 }
1940         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1941                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1942                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1943                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1944                 ew32(PHY_CTRL, phy_ctrl);
1945
1946                 if (phy->type != e1000_phy_igp_3)
1947                         return 0;
1948
1949                 /*
1950                  * Call gig speed drop workaround on LPLU before accessing
1951                  * any PHY registers
1952                  */
1953                 if (hw->mac.type == e1000_ich8lan)
1954                         e1000e_gig_downshift_workaround_ich8lan(hw);
1955
1956                 /* When LPLU is enabled, we should disable SmartSpeed */
1957                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1958                 if (ret_val)
1959                         return ret_val;
1960
1961                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1962                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1963         }
1964
1965         return 0;
1966 }
1967
1968 /**
1969  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1970  *  @hw: pointer to the HW structure
1971  *  @bank:  pointer to the variable that returns the active bank
1972  *
1973  *  Reads signature byte from the NVM using the flash access registers.
1974  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1975  **/
1976 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1977 {
1978         u32 eecd;
1979         struct e1000_nvm_info *nvm = &hw->nvm;
1980         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1981         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1982         u8 sig_byte = 0;
1983         s32 ret_val = 0;
1984
1985         switch (hw->mac.type) {
1986         case e1000_ich8lan:
1987         case e1000_ich9lan:
1988                 eecd = er32(EECD);
1989                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1990                     E1000_EECD_SEC1VAL_VALID_MASK) {
1991                         if (eecd & E1000_EECD_SEC1VAL)
1992                                 *bank = 1;
1993                         else
1994                                 *bank = 0;
1995
1996                         return 0;
1997                 }
1998                 e_dbg("Unable to determine valid NVM bank via EEC - "
1999                        "reading flash signature\n");
2000                 /* fall-thru */
2001         default:
2002                 /* set bank to 0 in case flash read fails */
2003                 *bank = 0;
2004
2005                 /* Check bank 0 */
2006                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2007                                                         &sig_byte);
2008                 if (ret_val)
2009                         return ret_val;
2010                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2011                     E1000_ICH_NVM_SIG_VALUE) {
2012                         *bank = 0;
2013                         return 0;
2014                 }
2015
2016                 /* Check bank 1 */
2017                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2018                                                         bank1_offset,
2019                                                         &sig_byte);
2020                 if (ret_val)
2021                         return ret_val;
2022                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2023                     E1000_ICH_NVM_SIG_VALUE) {
2024                         *bank = 1;
2025                         return 0;
2026                 }
2027
2028                 e_dbg("ERROR: No valid NVM bank present\n");
2029                 return -E1000_ERR_NVM;
2030         }
2031
2032         return 0;
2033 }
2034
2035 /**
2036  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2037  *  @hw: pointer to the HW structure
2038  *  @offset: The offset (in bytes) of the word(s) to read.
2039  *  @words: Size of data to read in words
2040  *  @data: Pointer to the word(s) to read at offset.
2041  *
2042  *  Reads a word(s) from the NVM using the flash access registers.
2043  **/
2044 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2045                                   u16 *data)
2046 {
2047         struct e1000_nvm_info *nvm = &hw->nvm;
2048         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2049         u32 act_offset;
2050         s32 ret_val = 0;
2051         u32 bank = 0;
2052         u16 i, word;
2053
2054         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2055             (words == 0)) {
2056                 e_dbg("nvm parameter(s) out of bounds\n");
2057                 ret_val = -E1000_ERR_NVM;
2058                 goto out;
2059         }
2060
2061         nvm->ops.acquire(hw);
2062
2063         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2064         if (ret_val) {
2065                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2066                 bank = 0;
2067         }
2068
2069         act_offset = (bank) ? nvm->flash_bank_size : 0;
2070         act_offset += offset;
2071
2072         ret_val = 0;
2073         for (i = 0; i < words; i++) {
2074                 if ((dev_spec->shadow_ram) &&
2075                     (dev_spec->shadow_ram[offset+i].modified)) {
2076                         data[i] = dev_spec->shadow_ram[offset+i].value;
2077                 } else {
2078                         ret_val = e1000_read_flash_word_ich8lan(hw,
2079                                                                 act_offset + i,
2080                                                                 &word);
2081                         if (ret_val)
2082                                 break;
2083                         data[i] = word;
2084                 }
2085         }
2086
2087         nvm->ops.release(hw);
2088
2089 out:
2090         if (ret_val)
2091                 e_dbg("NVM read error: %d\n", ret_val);
2092
2093         return ret_val;
2094 }
2095
2096 /**
2097  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2098  *  @hw: pointer to the HW structure
2099  *
2100  *  This function does initial flash setup so that a new read/write/erase cycle
2101  *  can be started.
2102  **/
2103 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2104 {
2105         union ich8_hws_flash_status hsfsts;
2106         s32 ret_val = -E1000_ERR_NVM;
2107         s32 i = 0;
2108
2109         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2110
2111         /* Check if the flash descriptor is valid */
2112         if (hsfsts.hsf_status.fldesvalid == 0) {
2113                 e_dbg("Flash descriptor invalid.  "
2114                          "SW Sequencing must be used.\n");
2115                 return -E1000_ERR_NVM;
2116         }
2117
2118         /* Clear FCERR and DAEL in hw status by writing 1 */
2119         hsfsts.hsf_status.flcerr = 1;
2120         hsfsts.hsf_status.dael = 1;
2121
2122         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2123
2124         /*
2125          * Either we should have a hardware SPI cycle in progress
2126          * bit to check against, in order to start a new cycle or
2127          * FDONE bit should be changed in the hardware so that it
2128          * is 1 after hardware reset, which can then be used as an
2129          * indication whether a cycle is in progress or has been
2130          * completed.
2131          */
2132
2133         if (hsfsts.hsf_status.flcinprog == 0) {
2134                 /*
2135                  * There is no cycle running at present,
2136                  * so we can start a cycle.
2137                  * Begin by setting Flash Cycle Done.
2138                  */
2139                 hsfsts.hsf_status.flcdone = 1;
2140                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2141                 ret_val = 0;
2142         } else {
2143                 /*
2144                  * Otherwise poll for sometime so the current
2145                  * cycle has a chance to end before giving up.
2146                  */
2147                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2148                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2149                         if (hsfsts.hsf_status.flcinprog == 0) {
2150                                 ret_val = 0;
2151                                 break;
2152                         }
2153                         udelay(1);
2154                 }
2155                 if (ret_val == 0) {
2156                         /*
2157                          * Successful in waiting for previous cycle to timeout,
2158                          * now set the Flash Cycle Done.
2159                          */
2160                         hsfsts.hsf_status.flcdone = 1;
2161                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2162                 } else {
2163                         e_dbg("Flash controller busy, cannot get access\n");
2164                 }
2165         }
2166
2167         return ret_val;
2168 }
2169
2170 /**
2171  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2172  *  @hw: pointer to the HW structure
2173  *  @timeout: maximum time to wait for completion
2174  *
2175  *  This function starts a flash cycle and waits for its completion.
2176  **/
2177 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2178 {
2179         union ich8_hws_flash_ctrl hsflctl;
2180         union ich8_hws_flash_status hsfsts;
2181         s32 ret_val = -E1000_ERR_NVM;
2182         u32 i = 0;
2183
2184         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2185         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2186         hsflctl.hsf_ctrl.flcgo = 1;
2187         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2188
2189         /* wait till FDONE bit is set to 1 */
2190         do {
2191                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2192                 if (hsfsts.hsf_status.flcdone == 1)
2193                         break;
2194                 udelay(1);
2195         } while (i++ < timeout);
2196
2197         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2198                 return 0;
2199
2200         return ret_val;
2201 }
2202
2203 /**
2204  *  e1000_read_flash_word_ich8lan - Read word from flash
2205  *  @hw: pointer to the HW structure
2206  *  @offset: offset to data location
2207  *  @data: pointer to the location for storing the data
2208  *
2209  *  Reads the flash word at offset into data.  Offset is converted
2210  *  to bytes before read.
2211  **/
2212 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2213                                          u16 *data)
2214 {
2215         /* Must convert offset into bytes. */
2216         offset <<= 1;
2217
2218         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2219 }
2220
2221 /**
2222  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2223  *  @hw: pointer to the HW structure
2224  *  @offset: The offset of the byte to read.
2225  *  @data: Pointer to a byte to store the value read.
2226  *
2227  *  Reads a single byte from the NVM using the flash access registers.
2228  **/
2229 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2230                                          u8 *data)
2231 {
2232         s32 ret_val;
2233         u16 word = 0;
2234
2235         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2236         if (ret_val)
2237                 return ret_val;
2238
2239         *data = (u8)word;
2240
2241         return 0;
2242 }
2243
2244 /**
2245  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2246  *  @hw: pointer to the HW structure
2247  *  @offset: The offset (in bytes) of the byte or word to read.
2248  *  @size: Size of data to read, 1=byte 2=word
2249  *  @data: Pointer to the word to store the value read.
2250  *
2251  *  Reads a byte or word from the NVM using the flash access registers.
2252  **/
2253 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2254                                          u8 size, u16 *data)
2255 {
2256         union ich8_hws_flash_status hsfsts;
2257         union ich8_hws_flash_ctrl hsflctl;
2258         u32 flash_linear_addr;
2259         u32 flash_data = 0;
2260         s32 ret_val = -E1000_ERR_NVM;
2261         u8 count = 0;
2262
2263         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2264                 return -E1000_ERR_NVM;
2265
2266         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2267                             hw->nvm.flash_base_addr;
2268
2269         do {
2270                 udelay(1);
2271                 /* Steps */
2272                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2273                 if (ret_val != 0)
2274                         break;
2275
2276                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2277                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2278                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2279                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2280                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2281
2282                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2283
2284                 ret_val = e1000_flash_cycle_ich8lan(hw,
2285                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2286
2287                 /*
2288                  * Check if FCERR is set to 1, if set to 1, clear it
2289                  * and try the whole sequence a few more times, else
2290                  * read in (shift in) the Flash Data0, the order is
2291                  * least significant byte first msb to lsb
2292                  */
2293                 if (ret_val == 0) {
2294                         flash_data = er32flash(ICH_FLASH_FDATA0);
2295                         if (size == 1)
2296                                 *data = (u8)(flash_data & 0x000000FF);
2297                         else if (size == 2)
2298                                 *data = (u16)(flash_data & 0x0000FFFF);
2299                         break;
2300                 } else {
2301                         /*
2302                          * If we've gotten here, then things are probably
2303                          * completely hosed, but if the error condition is
2304                          * detected, it won't hurt to give it another try...
2305                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2306                          */
2307                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2308                         if (hsfsts.hsf_status.flcerr == 1) {
2309                                 /* Repeat for some time before giving up. */
2310                                 continue;
2311                         } else if (hsfsts.hsf_status.flcdone == 0) {
2312                                 e_dbg("Timeout error - flash cycle "
2313                                          "did not complete.\n");
2314                                 break;
2315                         }
2316                 }
2317         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2318
2319         return ret_val;
2320 }
2321
2322 /**
2323  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2324  *  @hw: pointer to the HW structure
2325  *  @offset: The offset (in bytes) of the word(s) to write.
2326  *  @words: Size of data to write in words
2327  *  @data: Pointer to the word(s) to write at offset.
2328  *
2329  *  Writes a byte or word to the NVM using the flash access registers.
2330  **/
2331 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2332                                    u16 *data)
2333 {
2334         struct e1000_nvm_info *nvm = &hw->nvm;
2335         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2336         u16 i;
2337
2338         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2339             (words == 0)) {
2340                 e_dbg("nvm parameter(s) out of bounds\n");
2341                 return -E1000_ERR_NVM;
2342         }
2343
2344         nvm->ops.acquire(hw);
2345
2346         for (i = 0; i < words; i++) {
2347                 dev_spec->shadow_ram[offset+i].modified = true;
2348                 dev_spec->shadow_ram[offset+i].value = data[i];
2349         }
2350
2351         nvm->ops.release(hw);
2352
2353         return 0;
2354 }
2355
2356 /**
2357  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2358  *  @hw: pointer to the HW structure
2359  *
2360  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2361  *  which writes the checksum to the shadow ram.  The changes in the shadow
2362  *  ram are then committed to the EEPROM by processing each bank at a time
2363  *  checking for the modified bit and writing only the pending changes.
2364  *  After a successful commit, the shadow ram is cleared and is ready for
2365  *  future writes.
2366  **/
2367 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2368 {
2369         struct e1000_nvm_info *nvm = &hw->nvm;
2370         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2371         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2372         s32 ret_val;
2373         u16 data;
2374
2375         ret_val = e1000e_update_nvm_checksum_generic(hw);
2376         if (ret_val)
2377                 goto out;
2378
2379         if (nvm->type != e1000_nvm_flash_sw)
2380                 goto out;
2381
2382         nvm->ops.acquire(hw);
2383
2384         /*
2385          * We're writing to the opposite bank so if we're on bank 1,
2386          * write to bank 0 etc.  We also need to erase the segment that
2387          * is going to be written
2388          */
2389         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2390         if (ret_val) {
2391                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2392                 bank = 0;
2393         }
2394
2395         if (bank == 0) {
2396                 new_bank_offset = nvm->flash_bank_size;
2397                 old_bank_offset = 0;
2398                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2399                 if (ret_val)
2400                         goto release;
2401         } else {
2402                 old_bank_offset = nvm->flash_bank_size;
2403                 new_bank_offset = 0;
2404                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2405                 if (ret_val)
2406                         goto release;
2407         }
2408
2409         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2410                 /*
2411                  * Determine whether to write the value stored
2412                  * in the other NVM bank or a modified value stored
2413                  * in the shadow RAM
2414                  */
2415                 if (dev_spec->shadow_ram[i].modified) {
2416                         data = dev_spec->shadow_ram[i].value;
2417                 } else {
2418                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2419                                                                 old_bank_offset,
2420                                                                 &data);
2421                         if (ret_val)
2422                                 break;
2423                 }
2424
2425                 /*
2426                  * If the word is 0x13, then make sure the signature bits
2427                  * (15:14) are 11b until the commit has completed.
2428                  * This will allow us to write 10b which indicates the
2429                  * signature is valid.  We want to do this after the write
2430                  * has completed so that we don't mark the segment valid
2431                  * while the write is still in progress
2432                  */
2433                 if (i == E1000_ICH_NVM_SIG_WORD)
2434                         data |= E1000_ICH_NVM_SIG_MASK;
2435
2436                 /* Convert offset to bytes. */
2437                 act_offset = (i + new_bank_offset) << 1;
2438
2439                 udelay(100);
2440                 /* Write the bytes to the new bank. */
2441                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2442                                                                act_offset,
2443                                                                (u8)data);
2444                 if (ret_val)
2445                         break;
2446
2447                 udelay(100);
2448                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2449                                                           act_offset + 1,
2450                                                           (u8)(data >> 8));
2451                 if (ret_val)
2452                         break;
2453         }
2454
2455         /*
2456          * Don't bother writing the segment valid bits if sector
2457          * programming failed.
2458          */
2459         if (ret_val) {
2460                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2461                 e_dbg("Flash commit failed.\n");
2462                 goto release;
2463         }
2464
2465         /*
2466          * Finally validate the new segment by setting bit 15:14
2467          * to 10b in word 0x13 , this can be done without an
2468          * erase as well since these bits are 11 to start with
2469          * and we need to change bit 14 to 0b
2470          */
2471         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2472         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2473         if (ret_val)
2474                 goto release;
2475
2476         data &= 0xBFFF;
2477         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2478                                                        act_offset * 2 + 1,
2479                                                        (u8)(data >> 8));
2480         if (ret_val)
2481                 goto release;
2482
2483         /*
2484          * And invalidate the previously valid segment by setting
2485          * its signature word (0x13) high_byte to 0b. This can be
2486          * done without an erase because flash erase sets all bits
2487          * to 1's. We can write 1's to 0's without an erase
2488          */
2489         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2490         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2491         if (ret_val)
2492                 goto release;
2493
2494         /* Great!  Everything worked, we can now clear the cached entries. */
2495         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2496                 dev_spec->shadow_ram[i].modified = false;
2497                 dev_spec->shadow_ram[i].value = 0xFFFF;
2498         }
2499
2500 release:
2501         nvm->ops.release(hw);
2502
2503         /*
2504          * Reload the EEPROM, or else modifications will not appear
2505          * until after the next adapter reset.
2506          */
2507         if (!ret_val) {
2508                 e1000e_reload_nvm(hw);
2509                 msleep(10);
2510         }
2511
2512 out:
2513         if (ret_val)
2514                 e_dbg("NVM update error: %d\n", ret_val);
2515
2516         return ret_val;
2517 }
2518
2519 /**
2520  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2521  *  @hw: pointer to the HW structure
2522  *
2523  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2524  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2525  *  calculated, in which case we need to calculate the checksum and set bit 6.
2526  **/
2527 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2528 {
2529         s32 ret_val;
2530         u16 data;
2531
2532         /*
2533          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2534          * needs to be fixed.  This bit is an indication that the NVM
2535          * was prepared by OEM software and did not calculate the
2536          * checksum...a likely scenario.
2537          */
2538         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2539         if (ret_val)
2540                 return ret_val;
2541
2542         if ((data & 0x40) == 0) {
2543                 data |= 0x40;
2544                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2545                 if (ret_val)
2546                         return ret_val;
2547                 ret_val = e1000e_update_nvm_checksum(hw);
2548                 if (ret_val)
2549                         return ret_val;
2550         }
2551
2552         return e1000e_validate_nvm_checksum_generic(hw);
2553 }
2554
2555 /**
2556  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2557  *  @hw: pointer to the HW structure
2558  *
2559  *  To prevent malicious write/erase of the NVM, set it to be read-only
2560  *  so that the hardware ignores all write/erase cycles of the NVM via
2561  *  the flash control registers.  The shadow-ram copy of the NVM will
2562  *  still be updated, however any updates to this copy will not stick
2563  *  across driver reloads.
2564  **/
2565 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2566 {
2567         struct e1000_nvm_info *nvm = &hw->nvm;
2568         union ich8_flash_protected_range pr0;
2569         union ich8_hws_flash_status hsfsts;
2570         u32 gfpreg;
2571
2572         nvm->ops.acquire(hw);
2573
2574         gfpreg = er32flash(ICH_FLASH_GFPREG);
2575
2576         /* Write-protect GbE Sector of NVM */
2577         pr0.regval = er32flash(ICH_FLASH_PR0);
2578         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2579         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2580         pr0.range.wpe = true;
2581         ew32flash(ICH_FLASH_PR0, pr0.regval);
2582
2583         /*
2584          * Lock down a subset of GbE Flash Control Registers, e.g.
2585          * PR0 to prevent the write-protection from being lifted.
2586          * Once FLOCKDN is set, the registers protected by it cannot
2587          * be written until FLOCKDN is cleared by a hardware reset.
2588          */
2589         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2590         hsfsts.hsf_status.flockdn = true;
2591         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2592
2593         nvm->ops.release(hw);
2594 }
2595
2596 /**
2597  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2598  *  @hw: pointer to the HW structure
2599  *  @offset: The offset (in bytes) of the byte/word to read.
2600  *  @size: Size of data to read, 1=byte 2=word
2601  *  @data: The byte(s) to write to the NVM.
2602  *
2603  *  Writes one/two bytes to the NVM using the flash access registers.
2604  **/
2605 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2606                                           u8 size, u16 data)
2607 {
2608         union ich8_hws_flash_status hsfsts;
2609         union ich8_hws_flash_ctrl hsflctl;
2610         u32 flash_linear_addr;
2611         u32 flash_data = 0;
2612         s32 ret_val;
2613         u8 count = 0;
2614
2615         if (size < 1 || size > 2 || data > size * 0xff ||
2616             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2617                 return -E1000_ERR_NVM;
2618
2619         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2620                             hw->nvm.flash_base_addr;
2621
2622         do {
2623                 udelay(1);
2624                 /* Steps */
2625                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2626                 if (ret_val)
2627                         break;
2628
2629                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2630                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2631                 hsflctl.hsf_ctrl.fldbcount = size -1;
2632                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2633                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2634
2635                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2636
2637                 if (size == 1)
2638                         flash_data = (u32)data & 0x00FF;
2639                 else
2640                         flash_data = (u32)data;
2641
2642                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2643
2644                 /*
2645                  * check if FCERR is set to 1 , if set to 1, clear it
2646                  * and try the whole sequence a few more times else done
2647                  */
2648                 ret_val = e1000_flash_cycle_ich8lan(hw,
2649                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2650                 if (!ret_val)
2651                         break;
2652
2653                 /*
2654                  * If we're here, then things are most likely
2655                  * completely hosed, but if the error condition
2656                  * is detected, it won't hurt to give it another
2657                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2658                  */
2659                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2660                 if (hsfsts.hsf_status.flcerr == 1)
2661                         /* Repeat for some time before giving up. */
2662                         continue;
2663                 if (hsfsts.hsf_status.flcdone == 0) {
2664                         e_dbg("Timeout error - flash cycle "
2665                                  "did not complete.");
2666                         break;
2667                 }
2668         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2669
2670         return ret_val;
2671 }
2672
2673 /**
2674  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2675  *  @hw: pointer to the HW structure
2676  *  @offset: The index of the byte to read.
2677  *  @data: The byte to write to the NVM.
2678  *
2679  *  Writes a single byte to the NVM using the flash access registers.
2680  **/
2681 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2682                                           u8 data)
2683 {
2684         u16 word = (u16)data;
2685
2686         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2687 }
2688
2689 /**
2690  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2691  *  @hw: pointer to the HW structure
2692  *  @offset: The offset of the byte to write.
2693  *  @byte: The byte to write to the NVM.
2694  *
2695  *  Writes a single byte to the NVM using the flash access registers.
2696  *  Goes through a retry algorithm before giving up.
2697  **/
2698 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2699                                                 u32 offset, u8 byte)
2700 {
2701         s32 ret_val;
2702         u16 program_retries;
2703
2704         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2705         if (!ret_val)
2706                 return ret_val;
2707
2708         for (program_retries = 0; program_retries < 100; program_retries++) {
2709                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2710                 udelay(100);
2711                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2712                 if (!ret_val)
2713                         break;
2714         }
2715         if (program_retries == 100)
2716                 return -E1000_ERR_NVM;
2717
2718         return 0;
2719 }
2720
2721 /**
2722  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2723  *  @hw: pointer to the HW structure
2724  *  @bank: 0 for first bank, 1 for second bank, etc.
2725  *
2726  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2727  *  bank N is 4096 * N + flash_reg_addr.
2728  **/
2729 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2730 {
2731         struct e1000_nvm_info *nvm = &hw->nvm;
2732         union ich8_hws_flash_status hsfsts;
2733         union ich8_hws_flash_ctrl hsflctl;
2734         u32 flash_linear_addr;
2735         /* bank size is in 16bit words - adjust to bytes */
2736         u32 flash_bank_size = nvm->flash_bank_size * 2;
2737         s32 ret_val;
2738         s32 count = 0;
2739         s32 j, iteration, sector_size;
2740
2741         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2742
2743         /*
2744          * Determine HW Sector size: Read BERASE bits of hw flash status
2745          * register
2746          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2747          *     consecutive sectors.  The start index for the nth Hw sector
2748          *     can be calculated as = bank * 4096 + n * 256
2749          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2750          *     The start index for the nth Hw sector can be calculated
2751          *     as = bank * 4096
2752          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2753          *     (ich9 only, otherwise error condition)
2754          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2755          */
2756         switch (hsfsts.hsf_status.berasesz) {
2757         case 0:
2758                 /* Hw sector size 256 */
2759                 sector_size = ICH_FLASH_SEG_SIZE_256;
2760                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2761                 break;
2762         case 1:
2763                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2764                 iteration = 1;
2765                 break;
2766         case 2:
2767                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2768                 iteration = 1;
2769                 break;
2770         case 3:
2771                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2772                 iteration = 1;
2773                 break;
2774         default:
2775                 return -E1000_ERR_NVM;
2776         }
2777
2778         /* Start with the base address, then add the sector offset. */
2779         flash_linear_addr = hw->nvm.flash_base_addr;
2780         flash_linear_addr += (bank) ? flash_bank_size : 0;
2781
2782         for (j = 0; j < iteration ; j++) {
2783                 do {
2784                         /* Steps */
2785                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2786                         if (ret_val)
2787                                 return ret_val;
2788
2789                         /*
2790                          * Write a value 11 (block Erase) in Flash
2791                          * Cycle field in hw flash control
2792                          */
2793                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2794                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2795                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2796
2797                         /*
2798                          * Write the last 24 bits of an index within the
2799                          * block into Flash Linear address field in Flash
2800                          * Address.
2801                          */
2802                         flash_linear_addr += (j * sector_size);
2803                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2804
2805                         ret_val = e1000_flash_cycle_ich8lan(hw,
2806                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2807                         if (ret_val == 0)
2808                                 break;
2809
2810                         /*
2811                          * Check if FCERR is set to 1.  If 1,
2812                          * clear it and try the whole sequence
2813                          * a few more times else Done
2814                          */
2815                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2816                         if (hsfsts.hsf_status.flcerr == 1)
2817                                 /* repeat for some time before giving up */
2818                                 continue;
2819                         else if (hsfsts.hsf_status.flcdone == 0)
2820                                 return ret_val;
2821                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2822         }
2823
2824         return 0;
2825 }
2826
2827 /**
2828  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2829  *  @hw: pointer to the HW structure
2830  *  @data: Pointer to the LED settings
2831  *
2832  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2833  *  settings is all 0's or F's, set the LED default to a valid LED default
2834  *  setting.
2835  **/
2836 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2837 {
2838         s32 ret_val;
2839
2840         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2841         if (ret_val) {
2842                 e_dbg("NVM Read Error\n");
2843                 return ret_val;
2844         }
2845
2846         if (*data == ID_LED_RESERVED_0000 ||
2847             *data == ID_LED_RESERVED_FFFF)
2848                 *data = ID_LED_DEFAULT_ICH8LAN;
2849
2850         return 0;
2851 }
2852
2853 /**
2854  *  e1000_id_led_init_pchlan - store LED configurations
2855  *  @hw: pointer to the HW structure
2856  *
2857  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2858  *  the PHY LED configuration register.
2859  *
2860  *  PCH also does not have an "always on" or "always off" mode which
2861  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2862  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2863  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2864  *  link based on logic in e1000_led_[on|off]_pchlan().
2865  **/
2866 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2867 {
2868         struct e1000_mac_info *mac = &hw->mac;
2869         s32 ret_val;
2870         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2871         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2872         u16 data, i, temp, shift;
2873
2874         /* Get default ID LED modes */
2875         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2876         if (ret_val)
2877                 goto out;
2878
2879         mac->ledctl_default = er32(LEDCTL);
2880         mac->ledctl_mode1 = mac->ledctl_default;
2881         mac->ledctl_mode2 = mac->ledctl_default;
2882
2883         for (i = 0; i < 4; i++) {
2884                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2885                 shift = (i * 5);
2886                 switch (temp) {
2887                 case ID_LED_ON1_DEF2:
2888                 case ID_LED_ON1_ON2:
2889                 case ID_LED_ON1_OFF2:
2890                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2891                         mac->ledctl_mode1 |= (ledctl_on << shift);
2892                         break;
2893                 case ID_LED_OFF1_DEF2:
2894                 case ID_LED_OFF1_ON2:
2895                 case ID_LED_OFF1_OFF2:
2896                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2897                         mac->ledctl_mode1 |= (ledctl_off << shift);
2898                         break;
2899                 default:
2900                         /* Do nothing */
2901                         break;
2902                 }
2903                 switch (temp) {
2904                 case ID_LED_DEF1_ON2:
2905                 case ID_LED_ON1_ON2:
2906                 case ID_LED_OFF1_ON2:
2907                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2908                         mac->ledctl_mode2 |= (ledctl_on << shift);
2909                         break;
2910                 case ID_LED_DEF1_OFF2:
2911                 case ID_LED_ON1_OFF2:
2912                 case ID_LED_OFF1_OFF2:
2913                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2914                         mac->ledctl_mode2 |= (ledctl_off << shift);
2915                         break;
2916                 default:
2917                         /* Do nothing */
2918                         break;
2919                 }
2920         }
2921
2922 out:
2923         return ret_val;
2924 }
2925
2926 /**
2927  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2928  *  @hw: pointer to the HW structure
2929  *
2930  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2931  *  register, so the the bus width is hard coded.
2932  **/
2933 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2934 {
2935         struct e1000_bus_info *bus = &hw->bus;
2936         s32 ret_val;
2937
2938         ret_val = e1000e_get_bus_info_pcie(hw);
2939
2940         /*
2941          * ICH devices are "PCI Express"-ish.  They have
2942          * a configuration space, but do not contain
2943          * PCI Express Capability registers, so bus width
2944          * must be hardcoded.
2945          */
2946         if (bus->width == e1000_bus_width_unknown)
2947                 bus->width = e1000_bus_width_pcie_x1;
2948
2949         return ret_val;
2950 }
2951
2952 /**
2953  *  e1000_reset_hw_ich8lan - Reset the hardware
2954  *  @hw: pointer to the HW structure
2955  *
2956  *  Does a full reset of the hardware which includes a reset of the PHY and
2957  *  MAC.
2958  **/
2959 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2960 {
2961         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2962         u16 reg;
2963         u32 ctrl, kab;
2964         s32 ret_val;
2965
2966         /*
2967          * Prevent the PCI-E bus from sticking if there is no TLP connection
2968          * on the last TLP read/write transaction when MAC is reset.
2969          */
2970         ret_val = e1000e_disable_pcie_master(hw);
2971         if (ret_val)
2972                 e_dbg("PCI-E Master disable polling has failed.\n");
2973
2974         e_dbg("Masking off all interrupts\n");
2975         ew32(IMC, 0xffffffff);
2976
2977         /*
2978          * Disable the Transmit and Receive units.  Then delay to allow
2979          * any pending transactions to complete before we hit the MAC
2980          * with the global reset.
2981          */
2982         ew32(RCTL, 0);
2983         ew32(TCTL, E1000_TCTL_PSP);
2984         e1e_flush();
2985
2986         msleep(10);
2987
2988         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2989         if (hw->mac.type == e1000_ich8lan) {
2990                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2991                 ew32(PBA, E1000_PBA_8K);
2992                 /* Set Packet Buffer Size to 16k. */
2993                 ew32(PBS, E1000_PBS_16K);
2994         }
2995
2996         if (hw->mac.type == e1000_pchlan) {
2997                 /* Save the NVM K1 bit setting*/
2998                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2999                 if (ret_val)
3000                         return ret_val;
3001
3002                 if (reg & E1000_NVM_K1_ENABLE)
3003                         dev_spec->nvm_k1_enabled = true;
3004                 else
3005                         dev_spec->nvm_k1_enabled = false;
3006         }
3007
3008         ctrl = er32(CTRL);
3009
3010         if (!e1000_check_reset_block(hw)) {
3011                 /*
3012                  * Full-chip reset requires MAC and PHY reset at the same
3013                  * time to make sure the interface between MAC and the
3014                  * external PHY is reset.
3015                  */
3016                 ctrl |= E1000_CTRL_PHY_RST;
3017
3018                 /*
3019                  * Gate automatic PHY configuration by hardware on
3020                  * non-managed 82579
3021                  */
3022                 if ((hw->mac.type == e1000_pch2lan) &&
3023                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3024                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3025         }
3026         ret_val = e1000_acquire_swflag_ich8lan(hw);
3027         e_dbg("Issuing a global reset to ich8lan\n");
3028         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3029         msleep(20);
3030
3031         if (!ret_val)
3032                 e1000_release_swflag_ich8lan(hw);
3033
3034         if (ctrl & E1000_CTRL_PHY_RST) {
3035                 ret_val = hw->phy.ops.get_cfg_done(hw);
3036                 if (ret_val)
3037                         goto out;
3038
3039                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3040                 if (ret_val)
3041                         goto out;
3042         }
3043
3044         /*
3045          * For PCH, this write will make sure that any noise
3046          * will be detected as a CRC error and be dropped rather than show up
3047          * as a bad packet to the DMA engine.
3048          */
3049         if (hw->mac.type == e1000_pchlan)
3050                 ew32(CRC_OFFSET, 0x65656565);
3051
3052         ew32(IMC, 0xffffffff);
3053         er32(ICR);
3054
3055         kab = er32(KABGTXD);
3056         kab |= E1000_KABGTXD_BGSQLBIAS;
3057         ew32(KABGTXD, kab);
3058
3059 out:
3060         return ret_val;
3061 }
3062
3063 /**
3064  *  e1000_init_hw_ich8lan - Initialize the hardware
3065  *  @hw: pointer to the HW structure
3066  *
3067  *  Prepares the hardware for transmit and receive by doing the following:
3068  *   - initialize hardware bits
3069  *   - initialize LED identification
3070  *   - setup receive address registers
3071  *   - setup flow control
3072  *   - setup transmit descriptors
3073  *   - clear statistics
3074  **/
3075 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3076 {
3077         struct e1000_mac_info *mac = &hw->mac;
3078         u32 ctrl_ext, txdctl, snoop;
3079         s32 ret_val;
3080         u16 i;
3081
3082         e1000_initialize_hw_bits_ich8lan(hw);
3083
3084         /* Initialize identification LED */
3085         ret_val = mac->ops.id_led_init(hw);
3086         if (ret_val)
3087                 e_dbg("Error initializing identification LED\n");
3088                 /* This is not fatal and we should not stop init due to this */
3089
3090         /* Setup the receive address. */
3091         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3092
3093         /* Zero out the Multicast HASH table */
3094         e_dbg("Zeroing the MTA\n");
3095         for (i = 0; i < mac->mta_reg_count; i++)
3096                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3097
3098         /*
3099          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3100          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
3101          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3102          */
3103         if (hw->phy.type == e1000_phy_82578) {
3104                 e1e_rphy(hw, BM_WUC, &i);
3105                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3106                 if (ret_val)
3107                         return ret_val;
3108         }
3109
3110         /* Setup link and flow control */
3111         ret_val = e1000_setup_link_ich8lan(hw);
3112
3113         /* Set the transmit descriptor write-back policy for both queues */
3114         txdctl = er32(TXDCTL(0));
3115         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3116                  E1000_TXDCTL_FULL_TX_DESC_WB;
3117         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3118                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3119         ew32(TXDCTL(0), txdctl);
3120         txdctl = er32(TXDCTL(1));
3121         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3122                  E1000_TXDCTL_FULL_TX_DESC_WB;
3123         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3124                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3125         ew32(TXDCTL(1), txdctl);
3126
3127         /*
3128          * ICH8 has opposite polarity of no_snoop bits.
3129          * By default, we should use snoop behavior.
3130          */
3131         if (mac->type == e1000_ich8lan)
3132                 snoop = PCIE_ICH8_SNOOP_ALL;
3133         else
3134                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3135         e1000e_set_pcie_no_snoop(hw, snoop);
3136
3137         ctrl_ext = er32(CTRL_EXT);
3138         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3139         ew32(CTRL_EXT, ctrl_ext);
3140
3141         /*
3142          * Clear all of the statistics registers (clear on read).  It is
3143          * important that we do this after we have tried to establish link
3144          * because the symbol error count will increment wildly if there
3145          * is no link.
3146          */
3147         e1000_clear_hw_cntrs_ich8lan(hw);
3148
3149         return 0;
3150 }
3151 /**
3152  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3153  *  @hw: pointer to the HW structure
3154  *
3155  *  Sets/Clears required hardware bits necessary for correctly setting up the
3156  *  hardware for transmit and receive.
3157  **/
3158 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3159 {
3160         u32 reg;
3161
3162         /* Extended Device Control */
3163         reg = er32(CTRL_EXT);
3164         reg |= (1 << 22);
3165         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3166         if (hw->mac.type >= e1000_pchlan)
3167                 reg |= E1000_CTRL_EXT_PHYPDEN;
3168         ew32(CTRL_EXT, reg);
3169
3170         /* Transmit Descriptor Control 0 */
3171         reg = er32(TXDCTL(0));
3172         reg |= (1 << 22);
3173         ew32(TXDCTL(0), reg);
3174
3175         /* Transmit Descriptor Control 1 */
3176         reg = er32(TXDCTL(1));
3177         reg |= (1 << 22);
3178         ew32(TXDCTL(1), reg);
3179
3180         /* Transmit Arbitration Control 0 */
3181         reg = er32(TARC(0));
3182         if (hw->mac.type == e1000_ich8lan)
3183                 reg |= (1 << 28) | (1 << 29);
3184         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3185         ew32(TARC(0), reg);
3186
3187         /* Transmit Arbitration Control 1 */
3188         reg = er32(TARC(1));
3189         if (er32(TCTL) & E1000_TCTL_MULR)
3190                 reg &= ~(1 << 28);
3191         else
3192                 reg |= (1 << 28);
3193         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3194         ew32(TARC(1), reg);
3195
3196         /* Device Status */
3197         if (hw->mac.type == e1000_ich8lan) {
3198                 reg = er32(STATUS);
3199                 reg &= ~(1 << 31);
3200                 ew32(STATUS, reg);
3201         }
3202
3203         /*
3204          * work-around descriptor data corruption issue during nfs v2 udp
3205          * traffic, just disable the nfs filtering capability
3206          */
3207         reg = er32(RFCTL);
3208         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3209         ew32(RFCTL, reg);
3210 }
3211
3212 /**
3213  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3214  *  @hw: pointer to the HW structure
3215  *
3216  *  Determines which flow control settings to use, then configures flow
3217  *  control.  Calls the appropriate media-specific link configuration
3218  *  function.  Assuming the adapter has a valid link partner, a valid link
3219  *  should be established.  Assumes the hardware has previously been reset
3220  *  and the transmitter and receiver are not enabled.
3221  **/
3222 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3223 {
3224         s32 ret_val;
3225
3226         if (e1000_check_reset_block(hw))
3227                 return 0;
3228
3229         /*
3230          * ICH parts do not have a word in the NVM to determine
3231          * the default flow control setting, so we explicitly
3232          * set it to full.
3233          */
3234         if (hw->fc.requested_mode == e1000_fc_default) {
3235                 /* Workaround h/w hang when Tx flow control enabled */
3236                 if (hw->mac.type == e1000_pchlan)
3237                         hw->fc.requested_mode = e1000_fc_rx_pause;
3238                 else
3239                         hw->fc.requested_mode = e1000_fc_full;
3240         }
3241
3242         /*
3243          * Save off the requested flow control mode for use later.  Depending
3244          * on the link partner's capabilities, we may or may not use this mode.
3245          */
3246         hw->fc.current_mode = hw->fc.requested_mode;
3247
3248         e_dbg("After fix-ups FlowControl is now = %x\n",
3249                 hw->fc.current_mode);
3250
3251         /* Continue to configure the copper link. */
3252         ret_val = e1000_setup_copper_link_ich8lan(hw);
3253         if (ret_val)
3254                 return ret_val;
3255
3256         ew32(FCTTV, hw->fc.pause_time);
3257         if ((hw->phy.type == e1000_phy_82578) ||
3258             (hw->phy.type == e1000_phy_82579) ||
3259             (hw->phy.type == e1000_phy_82577)) {
3260                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3261
3262                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3263                                    hw->fc.pause_time);
3264                 if (ret_val)
3265                         return ret_val;
3266         }
3267
3268         return e1000e_set_fc_watermarks(hw);
3269 }
3270
3271 /**
3272  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3273  *  @hw: pointer to the HW structure
3274  *
3275  *  Configures the kumeran interface to the PHY to wait the appropriate time
3276  *  when polling the PHY, then call the generic setup_copper_link to finish
3277  *  configuring the copper link.
3278  **/
3279 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3280 {
3281         u32 ctrl;
3282         s32 ret_val;
3283         u16 reg_data;
3284
3285         ctrl = er32(CTRL);
3286         ctrl |= E1000_CTRL_SLU;
3287         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3288         ew32(CTRL, ctrl);
3289
3290         /*
3291          * Set the mac to wait the maximum time between each iteration
3292          * and increase the max iterations when polling the phy;
3293          * this fixes erroneous timeouts at 10Mbps.
3294          */
3295         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3296         if (ret_val)
3297                 return ret_val;
3298         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3299                                        &reg_data);
3300         if (ret_val)
3301                 return ret_val;
3302         reg_data |= 0x3F;
3303         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3304                                         reg_data);
3305         if (ret_val)
3306                 return ret_val;
3307
3308         switch (hw->phy.type) {
3309         case e1000_phy_igp_3:
3310                 ret_val = e1000e_copper_link_setup_igp(hw);
3311                 if (ret_val)
3312                         return ret_val;
3313                 break;
3314         case e1000_phy_bm:
3315         case e1000_phy_82578:
3316                 ret_val = e1000e_copper_link_setup_m88(hw);
3317                 if (ret_val)
3318                         return ret_val;
3319                 break;
3320         case e1000_phy_82577:
3321         case e1000_phy_82579:
3322                 ret_val = e1000_copper_link_setup_82577(hw);
3323                 if (ret_val)
3324                         return ret_val;
3325                 break;
3326         case e1000_phy_ife:
3327                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3328                 if (ret_val)
3329                         return ret_val;
3330
3331                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3332
3333                 switch (hw->phy.mdix) {
3334                 case 1:
3335                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3336                         break;
3337                 case 2:
3338                         reg_data |= IFE_PMC_FORCE_MDIX;
3339                         break;
3340                 case 0:
3341                 default:
3342                         reg_data |= IFE_PMC_AUTO_MDIX;
3343                         break;
3344                 }
3345                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3346                 if (ret_val)
3347                         return ret_val;
3348                 break;
3349         default:
3350                 break;
3351         }
3352         return e1000e_setup_copper_link(hw);
3353 }
3354
3355 /**
3356  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3357  *  @hw: pointer to the HW structure
3358  *  @speed: pointer to store current link speed
3359  *  @duplex: pointer to store the current link duplex
3360  *
3361  *  Calls the generic get_speed_and_duplex to retrieve the current link
3362  *  information and then calls the Kumeran lock loss workaround for links at
3363  *  gigabit speeds.
3364  **/
3365 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3366                                           u16 *duplex)
3367 {
3368         s32 ret_val;
3369
3370         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3371         if (ret_val)
3372                 return ret_val;
3373
3374         if ((hw->mac.type == e1000_ich8lan) &&
3375             (hw->phy.type == e1000_phy_igp_3) &&
3376             (*speed == SPEED_1000)) {
3377                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3378         }
3379
3380         return ret_val;
3381 }
3382
3383 /**
3384  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3385  *  @hw: pointer to the HW structure
3386  *
3387  *  Work-around for 82566 Kumeran PCS lock loss:
3388  *  On link status change (i.e. PCI reset, speed change) and link is up and
3389  *  speed is gigabit-
3390  *    0) if workaround is optionally disabled do nothing
3391  *    1) wait 1ms for Kumeran link to come up
3392  *    2) check Kumeran Diagnostic register PCS lock loss bit
3393  *    3) if not set the link is locked (all is good), otherwise...
3394  *    4) reset the PHY
3395  *    5) repeat up to 10 times
3396  *  Note: this is only called for IGP3 copper when speed is 1gb.
3397  **/
3398 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3399 {
3400         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3401         u32 phy_ctrl;
3402         s32 ret_val;
3403         u16 i, data;
3404         bool link;
3405
3406         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3407                 return 0;
3408
3409         /*
3410          * Make sure link is up before proceeding.  If not just return.
3411          * Attempting this while link is negotiating fouled up link
3412          * stability
3413          */
3414         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3415         if (!link)
3416                 return 0;
3417
3418         for (i = 0; i < 10; i++) {
3419                 /* read once to clear */
3420                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3421                 if (ret_val)
3422                         return ret_val;
3423                 /* and again to get new status */
3424                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3425                 if (ret_val)
3426                         return ret_val;
3427
3428                 /* check for PCS lock */
3429                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3430                         return 0;
3431
3432                 /* Issue PHY reset */
3433                 e1000_phy_hw_reset(hw);
3434                 mdelay(5);
3435         }
3436         /* Disable GigE link negotiation */
3437         phy_ctrl = er32(PHY_CTRL);
3438         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3439                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3440         ew32(PHY_CTRL, phy_ctrl);
3441
3442         /*
3443          * Call gig speed drop workaround on Gig disable before accessing
3444          * any PHY registers
3445          */
3446         e1000e_gig_downshift_workaround_ich8lan(hw);
3447
3448         /* unable to acquire PCS lock */
3449         return -E1000_ERR_PHY;
3450 }
3451
3452 /**
3453  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3454  *  @hw: pointer to the HW structure
3455  *  @state: boolean value used to set the current Kumeran workaround state
3456  *
3457  *  If ICH8, set the current Kumeran workaround state (enabled - true
3458  *  /disabled - false).
3459  **/
3460 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3461                                                  bool state)
3462 {
3463         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3464
3465         if (hw->mac.type != e1000_ich8lan) {
3466                 e_dbg("Workaround applies to ICH8 only.\n");
3467                 return;
3468         }
3469
3470         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3471 }
3472
3473 /**
3474  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3475  *  @hw: pointer to the HW structure
3476  *
3477  *  Workaround for 82566 power-down on D3 entry:
3478  *    1) disable gigabit link
3479  *    2) write VR power-down enable
3480  *    3) read it back
3481  *  Continue if successful, else issue LCD reset and repeat
3482  **/
3483 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3484 {
3485         u32 reg;
3486         u16 data;
3487         u8  retry = 0;
3488
3489         if (hw->phy.type != e1000_phy_igp_3)
3490                 return;
3491
3492         /* Try the workaround twice (if needed) */
3493         do {
3494                 /* Disable link */
3495                 reg = er32(PHY_CTRL);
3496                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3497                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3498                 ew32(PHY_CTRL, reg);
3499
3500                 /*
3501                  * Call gig speed drop workaround on Gig disable before
3502                  * accessing any PHY registers
3503                  */
3504                 if (hw->mac.type == e1000_ich8lan)
3505                         e1000e_gig_downshift_workaround_ich8lan(hw);
3506
3507                 /* Write VR power-down enable */
3508                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3509                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3510                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3511
3512                 /* Read it back and test */
3513                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3514                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3515                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3516                         break;
3517
3518                 /* Issue PHY reset and repeat at most one more time */
3519                 reg = er32(CTRL);
3520                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3521                 retry++;
3522         } while (retry);
3523 }
3524
3525 /**
3526  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3527  *  @hw: pointer to the HW structure
3528  *
3529  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3530  *  LPLU, Gig disable, MDIC PHY reset):
3531  *    1) Set Kumeran Near-end loopback
3532  *    2) Clear Kumeran Near-end loopback
3533  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3534  **/
3535 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3536 {
3537         s32 ret_val;
3538         u16 reg_data;
3539
3540         if ((hw->mac.type != e1000_ich8lan) ||
3541             (hw->phy.type != e1000_phy_igp_3))
3542                 return;
3543
3544         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3545                                       &reg_data);
3546         if (ret_val)
3547                 return;
3548         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3549         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3550                                        reg_data);
3551         if (ret_val)
3552                 return;
3553         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3554         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3555                                        reg_data);
3556 }
3557
3558 /**
3559  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3560  *  @hw: pointer to the HW structure
3561  *
3562  *  During S0 to Sx transition, it is possible the link remains at gig
3563  *  instead of negotiating to a lower speed.  Before going to Sx, set
3564  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3565  *  to a lower speed.
3566  *
3567  *  Should only be called for applicable parts.
3568  **/
3569 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3570 {
3571         u32 phy_ctrl;
3572         s32 ret_val;
3573
3574         phy_ctrl = er32(PHY_CTRL);
3575         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3576         ew32(PHY_CTRL, phy_ctrl);
3577
3578         if (hw->mac.type >= e1000_pchlan) {
3579                 e1000_oem_bits_config_ich8lan(hw, false);
3580                 ret_val = hw->phy.ops.acquire(hw);
3581                 if (ret_val)
3582                         return;
3583                 e1000_write_smbus_addr(hw);
3584                 hw->phy.ops.release(hw);
3585         }
3586 }
3587
3588 /**
3589  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3590  *  @hw: pointer to the HW structure
3591  *
3592  *  Return the LED back to the default configuration.
3593  **/
3594 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3595 {
3596         if (hw->phy.type == e1000_phy_ife)
3597                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3598
3599         ew32(LEDCTL, hw->mac.ledctl_default);
3600         return 0;
3601 }
3602
3603 /**
3604  *  e1000_led_on_ich8lan - Turn LEDs on
3605  *  @hw: pointer to the HW structure
3606  *
3607  *  Turn on the LEDs.
3608  **/
3609 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3610 {
3611         if (hw->phy.type == e1000_phy_ife)
3612                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3613                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3614
3615         ew32(LEDCTL, hw->mac.ledctl_mode2);
3616         return 0;
3617 }
3618
3619 /**
3620  *  e1000_led_off_ich8lan - Turn LEDs off
3621  *  @hw: pointer to the HW structure
3622  *
3623  *  Turn off the LEDs.
3624  **/
3625 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3626 {
3627         if (hw->phy.type == e1000_phy_ife)
3628                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3629                                 (IFE_PSCL_PROBE_MODE |
3630                                  IFE_PSCL_PROBE_LEDS_OFF));
3631
3632         ew32(LEDCTL, hw->mac.ledctl_mode1);
3633         return 0;
3634 }
3635
3636 /**
3637  *  e1000_setup_led_pchlan - Configures SW controllable LED
3638  *  @hw: pointer to the HW structure
3639  *
3640  *  This prepares the SW controllable LED for use.
3641  **/
3642 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3643 {
3644         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3645 }
3646
3647 /**
3648  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3649  *  @hw: pointer to the HW structure
3650  *
3651  *  Return the LED back to the default configuration.
3652  **/
3653 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3654 {
3655         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3656 }
3657
3658 /**
3659  *  e1000_led_on_pchlan - Turn LEDs on
3660  *  @hw: pointer to the HW structure
3661  *
3662  *  Turn on the LEDs.
3663  **/
3664 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3665 {
3666         u16 data = (u16)hw->mac.ledctl_mode2;
3667         u32 i, led;
3668
3669         /*
3670          * If no link, then turn LED on by setting the invert bit
3671          * for each LED that's mode is "link_up" in ledctl_mode2.
3672          */
3673         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3674                 for (i = 0; i < 3; i++) {
3675                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3676                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3677                             E1000_LEDCTL_MODE_LINK_UP)
3678                                 continue;
3679                         if (led & E1000_PHY_LED0_IVRT)
3680                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3681                         else
3682                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3683                 }
3684         }
3685
3686         return e1e_wphy(hw, HV_LED_CONFIG, data);
3687 }
3688
3689 /**
3690  *  e1000_led_off_pchlan - Turn LEDs off
3691  *  @hw: pointer to the HW structure
3692  *
3693  *  Turn off the LEDs.
3694  **/
3695 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3696 {
3697         u16 data = (u16)hw->mac.ledctl_mode1;
3698         u32 i, led;
3699
3700         /*
3701          * If no link, then turn LED off by clearing the invert bit
3702          * for each LED that's mode is "link_up" in ledctl_mode1.
3703          */
3704         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3705                 for (i = 0; i < 3; i++) {
3706                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3707                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3708                             E1000_LEDCTL_MODE_LINK_UP)
3709                                 continue;
3710                         if (led & E1000_PHY_LED0_IVRT)
3711                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3712                         else
3713                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3714                 }
3715         }
3716
3717         return e1e_wphy(hw, HV_LED_CONFIG, data);
3718 }
3719
3720 /**
3721  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3722  *  @hw: pointer to the HW structure
3723  *
3724  *  Read appropriate register for the config done bit for completion status
3725  *  and configure the PHY through s/w for EEPROM-less parts.
3726  *
3727  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3728  *  config done bit, so only an error is logged and continues.  If we were
3729  *  to return with error, EEPROM-less silicon would not be able to be reset
3730  *  or change link.
3731  **/
3732 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3733 {
3734         s32 ret_val = 0;
3735         u32 bank = 0;
3736         u32 status;
3737
3738         e1000e_get_cfg_done(hw);
3739
3740         /* Wait for indication from h/w that it has completed basic config */
3741         if (hw->mac.type >= e1000_ich10lan) {
3742                 e1000_lan_init_done_ich8lan(hw);
3743         } else {
3744                 ret_val = e1000e_get_auto_rd_done(hw);
3745                 if (ret_val) {
3746                         /*
3747                          * When auto config read does not complete, do not
3748                          * return with an error. This can happen in situations
3749                          * where there is no eeprom and prevents getting link.
3750                          */
3751                         e_dbg("Auto Read Done did not complete\n");
3752                         ret_val = 0;
3753                 }
3754         }
3755
3756         /* Clear PHY Reset Asserted bit */
3757         status = er32(STATUS);
3758         if (status & E1000_STATUS_PHYRA)
3759                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3760         else
3761                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3762
3763         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3764         if (hw->mac.type <= e1000_ich9lan) {
3765                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3766                     (hw->phy.type == e1000_phy_igp_3)) {
3767                         e1000e_phy_init_script_igp3(hw);
3768                 }
3769         } else {
3770                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3771                         /* Maybe we should do a basic PHY config */
3772                         e_dbg("EEPROM not present\n");
3773                         ret_val = -E1000_ERR_CONFIG;
3774                 }
3775         }
3776
3777         return ret_val;
3778 }
3779
3780 /**
3781  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3782  * @hw: pointer to the HW structure
3783  *
3784  * In the case of a PHY power down to save power, or to turn off link during a
3785  * driver unload, or wake on lan is not enabled, remove the link.
3786  **/
3787 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3788 {
3789         /* If the management interface is not enabled, then power down */
3790         if (!(hw->mac.ops.check_mng_mode(hw) ||
3791               hw->phy.ops.check_reset_block(hw)))
3792                 e1000_power_down_phy_copper(hw);
3793 }
3794
3795 /**
3796  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3797  *  @hw: pointer to the HW structure
3798  *
3799  *  Clears hardware counters specific to the silicon family and calls
3800  *  clear_hw_cntrs_generic to clear all general purpose counters.
3801  **/
3802 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3803 {
3804         u16 phy_data;
3805
3806         e1000e_clear_hw_cntrs_base(hw);
3807
3808         er32(ALGNERRC);
3809         er32(RXERRC);
3810         er32(TNCRS);
3811         er32(CEXTERR);
3812         er32(TSCTC);
3813         er32(TSCTFC);
3814
3815         er32(MGTPRC);
3816         er32(MGTPDC);
3817         er32(MGTPTC);
3818
3819         er32(IAC);
3820         er32(ICRXOC);
3821
3822         /* Clear PHY statistics registers */
3823         if ((hw->phy.type == e1000_phy_82578) ||
3824             (hw->phy.type == e1000_phy_82579) ||
3825             (hw->phy.type == e1000_phy_82577)) {
3826                 e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
3827                 e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
3828                 e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
3829                 e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
3830                 e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
3831                 e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
3832                 e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
3833                 e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
3834                 e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
3835                 e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
3836                 e1e_rphy(hw, HV_DC_UPPER, &phy_data);
3837                 e1e_rphy(hw, HV_DC_LOWER, &phy_data);
3838                 e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
3839                 e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
3840         }
3841 }
3842
3843 static struct e1000_mac_operations ich8_mac_ops = {
3844         .id_led_init            = e1000e_id_led_init,
3845         /* check_mng_mode dependent on mac type */
3846         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3847         /* cleanup_led dependent on mac type */
3848         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3849         .get_bus_info           = e1000_get_bus_info_ich8lan,
3850         .set_lan_id             = e1000_set_lan_id_single_port,
3851         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3852         /* led_on dependent on mac type */
3853         /* led_off dependent on mac type */
3854         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3855         .reset_hw               = e1000_reset_hw_ich8lan,
3856         .init_hw                = e1000_init_hw_ich8lan,
3857         .setup_link             = e1000_setup_link_ich8lan,
3858         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3859         /* id_led_init dependent on mac type */
3860 };
3861
3862 static struct e1000_phy_operations ich8_phy_ops = {
3863         .acquire                = e1000_acquire_swflag_ich8lan,
3864         .check_reset_block      = e1000_check_reset_block_ich8lan,
3865         .commit                 = NULL,
3866         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3867         .get_cable_length       = e1000e_get_cable_length_igp_2,
3868         .read_reg               = e1000e_read_phy_reg_igp,
3869         .release                = e1000_release_swflag_ich8lan,
3870         .reset                  = e1000_phy_hw_reset_ich8lan,
3871         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3872         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3873         .write_reg              = e1000e_write_phy_reg_igp,
3874 };
3875
3876 static struct e1000_nvm_operations ich8_nvm_ops = {
3877         .acquire                = e1000_acquire_nvm_ich8lan,
3878         .read                   = e1000_read_nvm_ich8lan,
3879         .release                = e1000_release_nvm_ich8lan,
3880         .update                 = e1000_update_nvm_checksum_ich8lan,
3881         .valid_led_default      = e1000_valid_led_default_ich8lan,
3882         .validate               = e1000_validate_nvm_checksum_ich8lan,
3883         .write                  = e1000_write_nvm_ich8lan,
3884 };
3885
3886 struct e1000_info e1000_ich8_info = {
3887         .mac                    = e1000_ich8lan,
3888         .flags                  = FLAG_HAS_WOL
3889                                   | FLAG_IS_ICH
3890                                   | FLAG_RX_CSUM_ENABLED
3891                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3892                                   | FLAG_HAS_AMT
3893                                   | FLAG_HAS_FLASH
3894                                   | FLAG_APME_IN_WUC,
3895         .pba                    = 8,
3896         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3897         .get_variants           = e1000_get_variants_ich8lan,
3898         .mac_ops                = &ich8_mac_ops,
3899         .phy_ops                = &ich8_phy_ops,
3900         .nvm_ops                = &ich8_nvm_ops,
3901 };
3902
3903 struct e1000_info e1000_ich9_info = {
3904         .mac                    = e1000_ich9lan,
3905         .flags                  = FLAG_HAS_JUMBO_FRAMES
3906                                   | FLAG_IS_ICH
3907                                   | FLAG_HAS_WOL
3908                                   | FLAG_RX_CSUM_ENABLED
3909                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3910                                   | FLAG_HAS_AMT
3911                                   | FLAG_HAS_ERT
3912                                   | FLAG_HAS_FLASH
3913                                   | FLAG_APME_IN_WUC,
3914         .pba                    = 10,
3915         .max_hw_frame_size      = DEFAULT_JUMBO,
3916         .get_variants           = e1000_get_variants_ich8lan,
3917         .mac_ops                = &ich8_mac_ops,
3918         .phy_ops                = &ich8_phy_ops,
3919         .nvm_ops                = &ich8_nvm_ops,
3920 };
3921
3922 struct e1000_info e1000_ich10_info = {
3923         .mac                    = e1000_ich10lan,
3924         .flags                  = FLAG_HAS_JUMBO_FRAMES
3925                                   | FLAG_IS_ICH
3926                                   | FLAG_HAS_WOL
3927                                   | FLAG_RX_CSUM_ENABLED
3928                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3929                                   | FLAG_HAS_AMT
3930                                   | FLAG_HAS_ERT
3931                                   | FLAG_HAS_FLASH
3932                                   | FLAG_APME_IN_WUC,
3933         .pba                    = 10,
3934         .max_hw_frame_size      = DEFAULT_JUMBO,
3935         .get_variants           = e1000_get_variants_ich8lan,
3936         .mac_ops                = &ich8_mac_ops,
3937         .phy_ops                = &ich8_phy_ops,
3938         .nvm_ops                = &ich8_nvm_ops,
3939 };
3940
3941 struct e1000_info e1000_pch_info = {
3942         .mac                    = e1000_pchlan,
3943         .flags                  = FLAG_IS_ICH
3944                                   | FLAG_HAS_WOL
3945                                   | FLAG_RX_CSUM_ENABLED
3946                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3947                                   | FLAG_HAS_AMT
3948                                   | FLAG_HAS_FLASH
3949                                   | FLAG_HAS_JUMBO_FRAMES
3950                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3951                                   | FLAG_APME_IN_WUC,
3952         .flags2                 = FLAG2_HAS_PHY_STATS,
3953         .pba                    = 26,
3954         .max_hw_frame_size      = 4096,
3955         .get_variants           = e1000_get_variants_ich8lan,
3956         .mac_ops                = &ich8_mac_ops,
3957         .phy_ops                = &ich8_phy_ops,
3958         .nvm_ops                = &ich8_nvm_ops,
3959 };
3960
3961 struct e1000_info e1000_pch2_info = {
3962         .mac                    = e1000_pch2lan,
3963         .flags                  = FLAG_IS_ICH
3964                                   | FLAG_HAS_WOL
3965                                   | FLAG_RX_CSUM_ENABLED
3966                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3967                                   | FLAG_HAS_AMT
3968                                   | FLAG_HAS_FLASH
3969                                   | FLAG_HAS_JUMBO_FRAMES
3970                                   | FLAG_APME_IN_WUC,
3971         .flags2                 = FLAG2_HAS_PHY_STATS
3972                                   | FLAG2_HAS_EEE,
3973         .pba                    = 26,
3974         .max_hw_frame_size      = DEFAULT_JUMBO,
3975         .get_variants           = e1000_get_variants_ich8lan,
3976         .mac_ops                = &ich8_mac_ops,
3977         .phy_ops                = &ich8_phy_ops,
3978         .nvm_ops                = &ich8_nvm_ops,
3979 };