drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                 PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK     0x6000
 142
 143 /* EMI Registers */
 144 #define I82579_EMI_ADDR         0x10
 145 #define I82579_EMI_DATA         0x11
 146 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 147
 148 /* Strapping Option Register - RO */
 149 #define E1000_STRAP                     0x0000C
 150 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 151 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 152
 153 /* OEM Bits Phy Register */
 154 #define HV_OEM_BITS            PHY_REG(768, 25)
 155 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 156 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 157 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 158
 159 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 160 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 161
 162 /* KMRN Mode Control */
 163 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 164 #define HV_KMRN_MDIO_SLOW      0x0400
 165
 166 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 167 /* Offset 04h HSFSTS */
 168 union ich8_hws_flash_status {
 169         struct ich8_hsfsts {
 170                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 171                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 172                 u16 dael       :1; /* bit 2 Direct Access error Log */
 173                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 174                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 175                 u16 reserved1  :2; /* bit 13:6 Reserved */
 176                 u16 reserved2  :6; /* bit 13:6 Reserved */
 177                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 178                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 179         } hsf_status;
 180         u16 regval;
 181 };
 182
 183 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 184 /* Offset 06h FLCTL */
 185 union ich8_hws_flash_ctrl {
 186         struct ich8_hsflctl {
 187                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 188                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 189                 u16 reserved   :5;   /* 7:3 Reserved  */
 190                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 191                 u16 flockdn    :6;   /* 15:10 Reserved */
 192         } hsf_ctrl;
 193         u16 regval;
 194 };
 195
 196 /* ICH Flash Region Access Permissions */
 197 union ich8_hws_flash_regacc {
 198         struct ich8_flracc {
 199                 u32 grra      :8; /* 0:7 GbE region Read Access */
 200                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 201                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 202                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 203         } hsf_flregacc;
 204         u16 regval;
 205 };
 206
 207 /* ICH Flash Protected Region */
 208 union ich8_flash_protected_range {
 209         struct ich8_pr {
 210                 u32 base:13;     /* 0:12 Protected Range Base */
 211                 u32 reserved1:2; /* 13:14 Reserved */
 212                 u32 rpe:1;       /* 15 Read Protection Enable */
 213                 u32 limit:13;    /* 16:28 Protected Range Limit */
 214                 u32 reserved2:2; /* 29:30 Reserved */
 215                 u32 wpe:1;       /* 31 Write Protection Enable */
 216         } range;
 217         u32 regval;
 218 };
 219
 220 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 221 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 222 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 223 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 224 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 225                                                 u32 offset, u8 byte);
 226 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 227                                          u8 *data);
 228 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 229                                          u16 *data);
 230 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 231                                          u8 size, u16 *data);
 232 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 233 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 234 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 235 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 236 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 237 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 238 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 239 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 240 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 241 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 242 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 243 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 244 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 245 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 246 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 247 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 248 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 249 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 250 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 251 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 252
 253 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 254 {
 255         return readw(hw->flash_address + reg);
 256 }
 257
 258 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 259 {
 260         return readl(hw->flash_address + reg);
 261 }
 262
 263 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 264 {
 265         writew(val, hw->flash_address + reg);
 266 }
 267
 268 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 269 {
 270         writel(val, hw->flash_address + reg);
 271 }
 272
 273 #define er16flash(reg)          __er16flash(hw, (reg))
 274 #define er32flash(reg)          __er32flash(hw, (reg))
 275 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 276 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 277
 278 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
 279 {
 280         u32 ctrl;
 281
 282         ctrl = er32(CTRL);
 283         ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
 284         ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 285         ew32(CTRL, ctrl);
 286         udelay(10);
 287         ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 288         ew32(CTRL, ctrl);
 289 }
 290
 291 /**
 292  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 293  *  @hw: pointer to the HW structure
 294  *
 295  *  Initialize family-specific PHY parameters and function pointers.
 296  **/
 297 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 298 {
 299         struct e1000_phy_info *phy = &hw->phy;
 300         u32 fwsm;
 301         s32 ret_val = 0;
 302
 303         phy->addr                     = 1;
 304         phy->reset_delay_us           = 100;
 305
 306         phy->ops.set_page             = e1000_set_page_igp;
 307         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 308         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 309         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 310         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 311         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 312         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 313         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 314         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 315         phy->ops.power_up             = e1000_power_up_phy_copper;
 316         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 317         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 318
 319         /*
 320          * The MAC-PHY interconnect may still be in SMBus mode
 321          * after Sx->S0.  If the manageability engine (ME) is
 322          * disabled, then toggle the LANPHYPC Value bit to force
 323          * the interconnect to PCIe mode.
 324          */
 325         fwsm = er32(FWSM);
 326         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
 327                 e1000_toggle_lanphypc_value_ich8lan(hw);
 328                 msleep(50);
 329
 330                 /*
 331                  * Gate automatic PHY configuration by hardware on
 332                  * non-managed 82579
 333                  */
 334                 if (hw->mac.type == e1000_pch2lan)
 335                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 336         }
 337
 338         /*
 339          * Reset the PHY before any access to it.  Doing so, ensures that
 340          * the PHY is in a known good state before we read/write PHY registers.
 341          * The generic reset is sufficient here, because we haven't determined
 342          * the PHY type yet.
 343          */
 344         ret_val = e1000e_phy_hw_reset_generic(hw);
 345         if (ret_val)
 346                 goto out;
 347
 348         /* Ungate automatic PHY configuration on non-managed 82579 */
 349         if ((hw->mac.type == e1000_pch2lan) &&
 350             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 351                 usleep_range(10000, 20000);
 352                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 353         }
 354
 355         phy->id = e1000_phy_unknown;
 356         switch (hw->mac.type) {
 357         default:
 358                 ret_val = e1000e_get_phy_id(hw);
 359                 if (ret_val)
 360                         goto out;
 361                 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 362                         break;
 363                 /* fall-through */
 364         case e1000_pch2lan:
 365                 /*
 366                  * In case the PHY needs to be in mdio slow mode,
 367                  * set slow mode and try to get the PHY id again.
 368                  */
 369                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 370                 if (ret_val)
 371                         goto out;
 372                 ret_val = e1000e_get_phy_id(hw);
 373                 if (ret_val)
 374                         goto out;
 375                 break;
 376         }
 377         phy->type = e1000e_get_phy_type_from_id(phy->id);
 378
 379         switch (phy->type) {
 380         case e1000_phy_82577:
 381         case e1000_phy_82579:
 382                 phy->ops.check_polarity = e1000_check_polarity_82577;
 383                 phy->ops.force_speed_duplex =
 384                     e1000_phy_force_speed_duplex_82577;
 385                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 386                 phy->ops.get_info = e1000_get_phy_info_82577;
 387                 phy->ops.commit = e1000e_phy_sw_reset;
 388                 break;
 389         case e1000_phy_82578:
 390                 phy->ops.check_polarity = e1000_check_polarity_m88;
 391                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 392                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 393                 phy->ops.get_info = e1000e_get_phy_info_m88;
 394                 break;
 395         default:
 396                 ret_val = -E1000_ERR_PHY;
 397                 break;
 398         }
 399
 400 out:
 401         return ret_val;
 402 }
 403
 404 /**
 405  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 406  *  @hw: pointer to the HW structure
 407  *
 408  *  Initialize family-specific PHY parameters and function pointers.
 409  **/
 410 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 411 {
 412         struct e1000_phy_info *phy = &hw->phy;
 413         s32 ret_val;
 414         u16 i = 0;
 415
 416         phy->addr                       = 1;
 417         phy->reset_delay_us             = 100;
 418
 419         phy->ops.power_up               = e1000_power_up_phy_copper;
 420         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 421
 422         /*
 423          * We may need to do this twice - once for IGP and if that fails,
 424          * we'll set BM func pointers and try again
 425          */
 426         ret_val = e1000e_determine_phy_address(hw);
 427         if (ret_val) {
 428                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 429                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 430                 ret_val = e1000e_determine_phy_address(hw);
 431                 if (ret_val) {
 432                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 433                         return ret_val;
 434                 }
 435         }
 436
 437         phy->id = 0;
 438         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 439                (i++ < 100)) {
 440                 usleep_range(1000, 2000);
 441                 ret_val = e1000e_get_phy_id(hw);
 442                 if (ret_val)
 443                         return ret_val;
 444         }
 445
 446         /* Verify phy id */
 447         switch (phy->id) {
 448         case IGP03E1000_E_PHY_ID:
 449                 phy->type = e1000_phy_igp_3;
 450                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 451                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 452                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 453                 phy->ops.get_info = e1000e_get_phy_info_igp;
 454                 phy->ops.check_polarity = e1000_check_polarity_igp;
 455                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 456                 break;
 457         case IFE_E_PHY_ID:
 458         case IFE_PLUS_E_PHY_ID:
 459         case IFE_C_E_PHY_ID:
 460                 phy->type = e1000_phy_ife;
 461                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 462                 phy->ops.get_info = e1000_get_phy_info_ife;
 463                 phy->ops.check_polarity = e1000_check_polarity_ife;
 464                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 465                 break;
 466         case BME1000_E_PHY_ID:
 467                 phy->type = e1000_phy_bm;
 468                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 469                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 470                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 471                 phy->ops.commit = e1000e_phy_sw_reset;
 472                 phy->ops.get_info = e1000e_get_phy_info_m88;
 473                 phy->ops.check_polarity = e1000_check_polarity_m88;
 474                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 475                 break;
 476         default:
 477                 return -E1000_ERR_PHY;
 478                 break;
 479         }
 480
 481         return 0;
 482 }
 483
 484 /**
 485  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 486  *  @hw: pointer to the HW structure
 487  *
 488  *  Initialize family-specific NVM parameters and function
 489  *  pointers.
 490  **/
 491 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 492 {
 493         struct e1000_nvm_info *nvm = &hw->nvm;
 494         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 495         u32 gfpreg, sector_base_addr, sector_end_addr;
 496         u16 i;
 497
 498         /* Can't read flash registers if the register set isn't mapped. */
 499         if (!hw->flash_address) {
 500                 e_dbg("ERROR: Flash registers not mapped\n");
 501                 return -E1000_ERR_CONFIG;
 502         }
 503
 504         nvm->type = e1000_nvm_flash_sw;
 505
 506         gfpreg = er32flash(ICH_FLASH_GFPREG);
 507
 508         /*
 509          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 510          * Add 1 to sector_end_addr since this sector is included in
 511          * the overall size.
 512          */
 513         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 514         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 515
 516         /* flash_base_addr is byte-aligned */
 517         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 518
 519         /*
 520          * find total size of the NVM, then cut in half since the total
 521          * size represents two separate NVM banks.
 522          */
 523         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 524                                 << FLASH_SECTOR_ADDR_SHIFT;
 525         nvm->flash_bank_size /= 2;
 526         /* Adjust to word count */
 527         nvm->flash_bank_size /= sizeof(u16);
 528
 529         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 530
 531         /* Clear shadow ram */
 532         for (i = 0; i < nvm->word_size; i++) {
 533                 dev_spec->shadow_ram[i].modified = false;
 534                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 535         }
 536
 537         return 0;
 538 }
 539
 540 /**
 541  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 542  *  @hw: pointer to the HW structure
 543  *
 544  *  Initialize family-specific MAC parameters and function
 545  *  pointers.
 546  **/
 547 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 548 {
 549         struct e1000_hw *hw = &adapter->hw;
 550         struct e1000_mac_info *mac = &hw->mac;
 551
 552         /* Set media type function pointer */
 553         hw->phy.media_type = e1000_media_type_copper;
 554
 555         /* Set mta register count */
 556         mac->mta_reg_count = 32;
 557         /* Set rar entry count */
 558         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 559         if (mac->type == e1000_ich8lan)
 560                 mac->rar_entry_count--;
 561         /* FWSM register */
 562         mac->has_fwsm = true;
 563         /* ARC subsystem not supported */
 564         mac->arc_subsystem_valid = false;
 565         /* Adaptive IFS supported */
 566         mac->adaptive_ifs = true;
 567
 568         /* LED operations */
 569         switch (mac->type) {
 570         case e1000_ich8lan:
 571         case e1000_ich9lan:
 572         case e1000_ich10lan:
 573                 /* check management mode */
 574                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 575                 /* ID LED init */
 576                 mac->ops.id_led_init = e1000e_id_led_init;
 577                 /* blink LED */
 578                 mac->ops.blink_led = e1000e_blink_led_generic;
 579                 /* setup LED */
 580                 mac->ops.setup_led = e1000e_setup_led_generic;
 581                 /* cleanup LED */
 582                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 583                 /* turn on/off LED */
 584                 mac->ops.led_on = e1000_led_on_ich8lan;
 585                 mac->ops.led_off = e1000_led_off_ich8lan;
 586                 break;
 587         case e1000_pchlan:
 588         case e1000_pch2lan:
 589                 /* check management mode */
 590                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 591                 /* ID LED init */
 592                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 593                 /* setup LED */
 594                 mac->ops.setup_led = e1000_setup_led_pchlan;
 595                 /* cleanup LED */
 596                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 597                 /* turn on/off LED */
 598                 mac->ops.led_on = e1000_led_on_pchlan;
 599                 mac->ops.led_off = e1000_led_off_pchlan;
 600                 break;
 601         default:
 602                 break;
 603         }
 604
 605         /* Enable PCS Lock-loss workaround for ICH8 */
 606         if (mac->type == e1000_ich8lan)
 607                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 608
 609         /* Gate automatic PHY configuration by hardware on managed 82579 */
 610         if ((mac->type == e1000_pch2lan) &&
 611             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 612                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 613
 614         return 0;
 615 }
 616
 617 /**
 618  *  e1000_set_eee_pchlan - Enable/disable EEE support
 619  *  @hw: pointer to the HW structure
 620  *
 621  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 622  *  the LPI Control register will remain set only if/when link is up.
 623  **/
 624 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 625 {
 626         s32 ret_val = 0;
 627         u16 phy_reg;
 628
 629         if (hw->phy.type != e1000_phy_82579)
 630                 goto out;
 631
 632         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 633         if (ret_val)
 634                 goto out;
 635
 636         if (hw->dev_spec.ich8lan.eee_disable)
 637                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 638         else
 639                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 640
 641         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 642 out:
 643         return ret_val;
 644 }
 645
 646 /**
 647  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 648  *  @hw: pointer to the HW structure
 649  *
 650  *  Checks to see of the link status of the hardware has changed.  If a
 651  *  change in link status has been detected, then we read the PHY registers
 652  *  to get the current speed/duplex if link exists.
 653  **/
 654 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 655 {
 656         struct e1000_mac_info *mac = &hw->mac;
 657         s32 ret_val;
 658         bool link;
 659
 660         /*
 661          * We only want to go out to the PHY registers to see if Auto-Neg
 662          * has completed and/or if our link status has changed.  The
 663          * get_link_status flag is set upon receiving a Link Status
 664          * Change or Rx Sequence Error interrupt.
 665          */
 666         if (!mac->get_link_status) {
 667                 ret_val = 0;
 668                 goto out;
 669         }
 670
 671         /*
 672          * First we want to see if the MII Status Register reports
 673          * link.  If so, then we want to get the current speed/duplex
 674          * of the PHY.
 675          */
 676         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 677         if (ret_val)
 678                 goto out;
 679
 680         if (hw->mac.type == e1000_pchlan) {
 681                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 682                 if (ret_val)
 683                         goto out;
 684         }
 685
 686         if (!link)
 687                 goto out; /* No link detected */
 688
 689         mac->get_link_status = false;
 690
 691         if (hw->phy.type == e1000_phy_82578) {
 692                 ret_val = e1000_link_stall_workaround_hv(hw);
 693                 if (ret_val)
 694                         goto out;
 695         }
 696
 697         if (hw->mac.type == e1000_pch2lan) {
 698                 ret_val = e1000_k1_workaround_lv(hw);
 699                 if (ret_val)
 700                         goto out;
 701         }
 702
 703         /*
 704          * Check if there was DownShift, must be checked
 705          * immediately after link-up
 706          */
 707         e1000e_check_downshift(hw);
 708
 709         /* Enable/Disable EEE after link up */
 710         ret_val = e1000_set_eee_pchlan(hw);
 711         if (ret_val)
 712                 goto out;
 713
 714         /*
 715          * If we are forcing speed/duplex, then we simply return since
 716          * we have already determined whether we have link or not.
 717          */
 718         if (!mac->autoneg) {
 719                 ret_val = -E1000_ERR_CONFIG;
 720                 goto out;
 721         }
 722
 723         /*
 724          * Auto-Neg is enabled.  Auto Speed Detection takes care
 725          * of MAC speed/duplex configuration.  So we only need to
 726          * configure Collision Distance in the MAC.
 727          */
 728         e1000e_config_collision_dist(hw);
 729
 730         /*
 731          * Configure Flow Control now that Auto-Neg has completed.
 732          * First, we need to restore the desired flow control
 733          * settings because we may have had to re-autoneg with a
 734          * different link partner.
 735          */
 736         ret_val = e1000e_config_fc_after_link_up(hw);
 737         if (ret_val)
 738                 e_dbg("Error configuring flow control\n");
 739
 740 out:
 741         return ret_val;
 742 }
 743
 744 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 745 {
 746         struct e1000_hw *hw = &adapter->hw;
 747         s32 rc;
 748
 749         rc = e1000_init_mac_params_ich8lan(adapter);
 750         if (rc)
 751                 return rc;
 752
 753         rc = e1000_init_nvm_params_ich8lan(hw);
 754         if (rc)
 755                 return rc;
 756
 757         switch (hw->mac.type) {
 758         case e1000_ich8lan:
 759         case e1000_ich9lan:
 760         case e1000_ich10lan:
 761                 rc = e1000_init_phy_params_ich8lan(hw);
 762                 break;
 763         case e1000_pchlan:
 764         case e1000_pch2lan:
 765                 rc = e1000_init_phy_params_pchlan(hw);
 766                 break;
 767         default:
 768                 break;
 769         }
 770         if (rc)
 771                 return rc;
 772
 773         /*
 774          * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 775          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 776          */
 777         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 778             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 779              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 780                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 781                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 782
 783                 hw->mac.ops.blink_led = NULL;
 784         }
 785
 786         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 787             (adapter->hw.phy.type == e1000_phy_igp_3))
 788                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 789
 790         /* Disable EEE by default until IEEE802.3az spec is finalized */
 791         if (adapter->flags2 & FLAG2_HAS_EEE)
 792                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 793
 794         return 0;
 795 }
 796
 797 static DEFINE_MUTEX(nvm_mutex);
 798
 799 /**
 800  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 801  *  @hw: pointer to the HW structure
 802  *
 803  *  Acquires the mutex for performing NVM operations.
 804  **/
 805 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 806 {
 807         mutex_lock(&nvm_mutex);
 808
 809         return 0;
 810 }
 811
 812 /**
 813  *  e1000_release_nvm_ich8lan - Release NVM mutex
 814  *  @hw: pointer to the HW structure
 815  *
 816  *  Releases the mutex used while performing NVM operations.
 817  **/
 818 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 819 {
 820         mutex_unlock(&nvm_mutex);
 821 }
 822
 823 static DEFINE_MUTEX(swflag_mutex);
 824
 825 /**
 826  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 827  *  @hw: pointer to the HW structure
 828  *
 829  *  Acquires the software control flag for performing PHY and select
 830  *  MAC CSR accesses.
 831  **/
 832 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 833 {
 834         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 835         s32 ret_val = 0;
 836
 837         mutex_lock(&swflag_mutex);
 838
 839         while (timeout) {
 840                 extcnf_ctrl = er32(EXTCNF_CTRL);
 841                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 842                         break;
 843
 844                 mdelay(1);
 845                 timeout--;
 846         }
 847
 848         if (!timeout) {
 849                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 850                 ret_val = -E1000_ERR_CONFIG;
 851                 goto out;
 852         }
 853
 854         timeout = SW_FLAG_TIMEOUT;
 855
 856         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 857         ew32(EXTCNF_CTRL, extcnf_ctrl);
 858
 859         while (timeout) {
 860                 extcnf_ctrl = er32(EXTCNF_CTRL);
 861                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 862                         break;
 863
 864                 mdelay(1);
 865                 timeout--;
 866         }
 867
 868         if (!timeout) {
 869                 e_dbg("Failed to acquire the semaphore.\n");
 870                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 871                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 872                 ret_val = -E1000_ERR_CONFIG;
 873                 goto out;
 874         }
 875
 876 out:
 877         if (ret_val)
 878                 mutex_unlock(&swflag_mutex);
 879
 880         return ret_val;
 881 }
 882
 883 /**
 884  *  e1000_release_swflag_ich8lan - Release software control flag
 885  *  @hw: pointer to the HW structure
 886  *
 887  *  Releases the software control flag for performing PHY and select
 888  *  MAC CSR accesses.
 889  **/
 890 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 891 {
 892         u32 extcnf_ctrl;
 893
 894         extcnf_ctrl = er32(EXTCNF_CTRL);
 895
 896         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
 897                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 898                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 899         } else {
 900                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
 901         }
 902
 903         mutex_unlock(&swflag_mutex);
 904 }
 905
 906 /**
 907  *  e1000_check_mng_mode_ich8lan - Checks management mode
 908  *  @hw: pointer to the HW structure
 909  *
 910  *  This checks if the adapter has any manageability enabled.
 911  *  This is a function pointer entry point only called by read/write
 912  *  routines for the PHY and NVM parts.
 913  **/
 914 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 915 {
 916         u32 fwsm;
 917
 918         fwsm = er32(FWSM);
 919         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 920                ((fwsm & E1000_FWSM_MODE_MASK) ==
 921                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 922 }
 923
 924 /**
 925  *  e1000_check_mng_mode_pchlan - Checks management mode
 926  *  @hw: pointer to the HW structure
 927  *
 928  *  This checks if the adapter has iAMT enabled.
 929  *  This is a function pointer entry point only called by read/write
 930  *  routines for the PHY and NVM parts.
 931  **/
 932 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 933 {
 934         u32 fwsm;
 935
 936         fwsm = er32(FWSM);
 937         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 938                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 939 }
 940
 941 /**
 942  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 943  *  @hw: pointer to the HW structure
 944  *
 945  *  Checks if firmware is blocking the reset of the PHY.
 946  *  This is a function pointer entry point only called by
 947  *  reset routines.
 948  **/
 949 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 950 {
 951         u32 fwsm;
 952
 953         fwsm = er32(FWSM);
 954
 955         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 956 }
 957
 958 /**
 959  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 960  *  @hw: pointer to the HW structure
 961  *
 962  *  Assumes semaphore already acquired.
 963  *
 964  **/
 965 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
 966 {
 967         u16 phy_data;
 968         u32 strap = er32(STRAP);
 969         s32 ret_val = 0;
 970
 971         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 972
 973         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
 974         if (ret_val)
 975                 goto out;
 976
 977         phy_data &= ~HV_SMB_ADDR_MASK;
 978         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
 979         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 980         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
 981
 982 out:
 983         return ret_val;
 984 }
 985
 986 /**
 987  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 988  *  @hw:   pointer to the HW structure
 989  *
 990  *  SW should configure the LCD from the NVM extended configuration region
 991  *  as a workaround for certain parts.
 992  **/
 993 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 994 {
 995         struct e1000_phy_info *phy = &hw->phy;
 996         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 997         s32 ret_val = 0;
 998         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 999
1000         /*
1001          * Initialize the PHY from the NVM on ICH platforms.  This
1002          * is needed due to an issue where the NVM configuration is
1003          * not properly autoloaded after power transitions.
1004          * Therefore, after each PHY reset, we will load the
1005          * configuration data out of the NVM manually.
1006          */
1007         switch (hw->mac.type) {
1008         case e1000_ich8lan:
1009                 if (phy->type != e1000_phy_igp_3)
1010                         return ret_val;
1011
1012                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1013                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1014                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1015                         break;
1016                 }
1017                 /* Fall-thru */
1018         case e1000_pchlan:
1019         case e1000_pch2lan:
1020                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1021                 break;
1022         default:
1023                 return ret_val;
1024         }
1025
1026         ret_val = hw->phy.ops.acquire(hw);
1027         if (ret_val)
1028                 return ret_val;
1029
1030         data = er32(FEXTNVM);
1031         if (!(data & sw_cfg_mask))
1032                 goto out;
1033
1034         /*
1035          * Make sure HW does not configure LCD from PHY
1036          * extended configuration before SW configuration
1037          */
1038         data = er32(EXTCNF_CTRL);
1039         if (!(hw->mac.type == e1000_pch2lan)) {
1040                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1041                         goto out;
1042         }
1043
1044         cnf_size = er32(EXTCNF_SIZE);
1045         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1046         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1047         if (!cnf_size)
1048                 goto out;
1049
1050         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1051         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1052
1053         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1054             (hw->mac.type == e1000_pchlan)) ||
1055              (hw->mac.type == e1000_pch2lan)) {
1056                 /*
1057                  * HW configures the SMBus address and LEDs when the
1058                  * OEM and LCD Write Enable bits are set in the NVM.
1059                  * When both NVM bits are cleared, SW will configure
1060                  * them instead.
1061                  */
1062                 ret_val = e1000_write_smbus_addr(hw);
1063                 if (ret_val)
1064                         goto out;
1065
1066                 data = er32(LEDCTL);
1067                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1068                                                         (u16)data);
1069                 if (ret_val)
1070                         goto out;
1071         }
1072
1073         /* Configure LCD from extended configuration region. */
1074
1075         /* cnf_base_addr is in DWORD */
1076         word_addr = (u16)(cnf_base_addr << 1);
1077
1078         for (i = 0; i < cnf_size; i++) {
1079                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1080                                          &reg_data);
1081                 if (ret_val)
1082                         goto out;
1083
1084                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1085                                          1, &reg_addr);
1086                 if (ret_val)
1087                         goto out;
1088
1089                 /* Save off the PHY page for future writes. */
1090                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1091                         phy_page = reg_data;
1092                         continue;
1093                 }
1094
1095                 reg_addr &= PHY_REG_MASK;
1096                 reg_addr |= phy_page;
1097
1098                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1099                                                     reg_data);
1100                 if (ret_val)
1101                         goto out;
1102         }
1103
1104 out:
1105         hw->phy.ops.release(hw);
1106         return ret_val;
1107 }
1108
1109 /**
1110  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1111  *  @hw:   pointer to the HW structure
1112  *  @link: link up bool flag
1113  *
1114  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1115  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1116  *  If link is down, the function will restore the default K1 setting located
1117  *  in the NVM.
1118  **/
1119 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1120 {
1121         s32 ret_val = 0;
1122         u16 status_reg = 0;
1123         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1124
1125         if (hw->mac.type != e1000_pchlan)
1126                 goto out;
1127
1128         /* Wrap the whole flow with the sw flag */
1129         ret_val = hw->phy.ops.acquire(hw);
1130         if (ret_val)
1131                 goto out;
1132
1133         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1134         if (link) {
1135                 if (hw->phy.type == e1000_phy_82578) {
1136                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1137                                                                   &status_reg);
1138                         if (ret_val)
1139                                 goto release;
1140
1141                         status_reg &= BM_CS_STATUS_LINK_UP |
1142                                       BM_CS_STATUS_RESOLVED |
1143                                       BM_CS_STATUS_SPEED_MASK;
1144
1145                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1146                                            BM_CS_STATUS_RESOLVED |
1147                                            BM_CS_STATUS_SPEED_1000))
1148                                 k1_enable = false;
1149                 }
1150
1151                 if (hw->phy.type == e1000_phy_82577) {
1152                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1153                                                                   &status_reg);
1154                         if (ret_val)
1155                                 goto release;
1156
1157                         status_reg &= HV_M_STATUS_LINK_UP |
1158                                       HV_M_STATUS_AUTONEG_COMPLETE |
1159                                       HV_M_STATUS_SPEED_MASK;
1160
1161                         if (status_reg == (HV_M_STATUS_LINK_UP |
1162                                            HV_M_STATUS_AUTONEG_COMPLETE |
1163                                            HV_M_STATUS_SPEED_1000))
1164                                 k1_enable = false;
1165                 }
1166
1167                 /* Link stall fix for link up */
1168                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1169                                                            0x0100);
1170                 if (ret_val)
1171                         goto release;
1172
1173         } else {
1174                 /* Link stall fix for link down */
1175                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1176                                                            0x4100);
1177                 if (ret_val)
1178                         goto release;
1179         }
1180
1181         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1182
1183 release:
1184         hw->phy.ops.release(hw);
1185 out:
1186         return ret_val;
1187 }
1188
1189 /**
1190  *  e1000_configure_k1_ich8lan - Configure K1 power state
1191  *  @hw: pointer to the HW structure
1192  *  @enable: K1 state to configure
1193  *
1194  *  Configure the K1 power state based on the provided parameter.
1195  *  Assumes semaphore already acquired.
1196  *
1197  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1198  **/
1199 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1200 {
1201         s32 ret_val = 0;
1202         u32 ctrl_reg = 0;
1203         u32 ctrl_ext = 0;
1204         u32 reg = 0;
1205         u16 kmrn_reg = 0;
1206
1207         ret_val = e1000e_read_kmrn_reg_locked(hw,
1208                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1209                                              &kmrn_reg);
1210         if (ret_val)
1211                 goto out;
1212
1213         if (k1_enable)
1214                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1215         else
1216                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1217
1218         ret_val = e1000e_write_kmrn_reg_locked(hw,
1219                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1220                                               kmrn_reg);
1221         if (ret_val)
1222                 goto out;
1223
1224         udelay(20);
1225         ctrl_ext = er32(CTRL_EXT);
1226         ctrl_reg = er32(CTRL);
1227
1228         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1229         reg |= E1000_CTRL_FRCSPD;
1230         ew32(CTRL, reg);
1231
1232         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1233         udelay(20);
1234         ew32(CTRL, ctrl_reg);
1235         ew32(CTRL_EXT, ctrl_ext);
1236         udelay(20);
1237
1238 out:
1239         return ret_val;
1240 }
1241
1242 /**
1243  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1244  *  @hw:       pointer to the HW structure
1245  *  @d0_state: boolean if entering d0 or d3 device state
1246  *
1247  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1248  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1249  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1250  **/
1251 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1252 {
1253         s32 ret_val = 0;
1254         u32 mac_reg;
1255         u16 oem_reg;
1256
1257         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1258                 return ret_val;
1259
1260         ret_val = hw->phy.ops.acquire(hw);
1261         if (ret_val)
1262                 return ret_val;
1263
1264         if (!(hw->mac.type == e1000_pch2lan)) {
1265                 mac_reg = er32(EXTCNF_CTRL);
1266                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1267                         goto out;
1268         }
1269
1270         mac_reg = er32(FEXTNVM);
1271         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1272                 goto out;
1273
1274         mac_reg = er32(PHY_CTRL);
1275
1276         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1277         if (ret_val)
1278                 goto out;
1279
1280         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1281
1282         if (d0_state) {
1283                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1284                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1285
1286                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1287                         oem_reg |= HV_OEM_BITS_LPLU;
1288         } else {
1289                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1290                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1291
1292                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1293                         oem_reg |= HV_OEM_BITS_LPLU;
1294         }
1295         /* Restart auto-neg to activate the bits */
1296         if (!e1000_check_reset_block(hw))
1297                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1298         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1299
1300 out:
1301         hw->phy.ops.release(hw);
1302
1303         return ret_val;
1304 }
1305
1306
1307 /**
1308  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1309  *  @hw:   pointer to the HW structure
1310  **/
1311 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1312 {
1313         s32 ret_val;
1314         u16 data;
1315
1316         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1317         if (ret_val)
1318                 return ret_val;
1319
1320         data |= HV_KMRN_MDIO_SLOW;
1321
1322         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1323
1324         return ret_val;
1325 }
1326
1327 /**
1328  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1329  *  done after every PHY reset.
1330  **/
1331 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1332 {
1333         s32 ret_val = 0;
1334         u16 phy_data;
1335
1336         if (hw->mac.type != e1000_pchlan)
1337                 return ret_val;
1338
1339         /* Set MDIO slow mode before any other MDIO access */
1340         if (hw->phy.type == e1000_phy_82577) {
1341                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1342                 if (ret_val)
1343                         goto out;
1344         }
1345
1346         if (((hw->phy.type == e1000_phy_82577) &&
1347              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1348             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1349                 /* Disable generation of early preamble */
1350                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1351                 if (ret_val)
1352                         return ret_val;
1353
1354                 /* Preamble tuning for SSC */
1355                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1356                 if (ret_val)
1357                         return ret_val;
1358         }
1359
1360         if (hw->phy.type == e1000_phy_82578) {
1361                 /*
1362                  * Return registers to default by doing a soft reset then
1363                  * writing 0x3140 to the control register.
1364                  */
1365                 if (hw->phy.revision < 2) {
1366                         e1000e_phy_sw_reset(hw);
1367                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1368                 }
1369         }
1370
1371         /* Select page 0 */
1372         ret_val = hw->phy.ops.acquire(hw);
1373         if (ret_val)
1374                 return ret_val;
1375
1376         hw->phy.addr = 1;
1377         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1378         hw->phy.ops.release(hw);
1379         if (ret_val)
1380                 goto out;
1381
1382         /*
1383          * Configure the K1 Si workaround during phy reset assuming there is
1384          * link so that it disables K1 if link is in 1Gbps.
1385          */
1386         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1387         if (ret_val)
1388                 goto out;
1389
1390         /* Workaround for link disconnects on a busy hub in half duplex */
1391         ret_val = hw->phy.ops.acquire(hw);
1392         if (ret_val)
1393                 goto out;
1394         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1395         if (ret_val)
1396                 goto release;
1397         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1398                                                phy_data & 0x00FF);
1399 release:
1400         hw->phy.ops.release(hw);
1401 out:
1402         return ret_val;
1403 }
1404
1405 /**
1406  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1407  *  @hw:   pointer to the HW structure
1408  **/
1409 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1410 {
1411         u32 mac_reg;
1412         u16 i, phy_reg = 0;
1413         s32 ret_val;
1414
1415         ret_val = hw->phy.ops.acquire(hw);
1416         if (ret_val)
1417                 return;
1418         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1419         if (ret_val)
1420                 goto release;
1421
1422         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1423         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1424                 mac_reg = er32(RAL(i));
1425                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1426                                            (u16)(mac_reg & 0xFFFF));
1427                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1428                                            (u16)((mac_reg >> 16) & 0xFFFF));
1429
1430                 mac_reg = er32(RAH(i));
1431                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1432                                            (u16)(mac_reg & 0xFFFF));
1433                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1434                                            (u16)((mac_reg & E1000_RAH_AV)
1435                                                  >> 16));
1436         }
1437
1438         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1439
1440 release:
1441         hw->phy.ops.release(hw);
1442 }
1443
1444 /**
1445  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1446  *  with 82579 PHY
1447  *  @hw: pointer to the HW structure
1448  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1449  **/
1450 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1451 {
1452         s32 ret_val = 0;
1453         u16 phy_reg, data;
1454         u32 mac_reg;
1455         u16 i;
1456
1457         if (hw->mac.type != e1000_pch2lan)
1458                 goto out;
1459
1460         /* disable Rx path while enabling/disabling workaround */
1461         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1462         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1463         if (ret_val)
1464                 goto out;
1465
1466         if (enable) {
1467                 /*
1468                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1469                  * SHRAL/H) and initial CRC values to the MAC
1470                  */
1471                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1472                         u8 mac_addr[ETH_ALEN] = {0};
1473                         u32 addr_high, addr_low;
1474
1475                         addr_high = er32(RAH(i));
1476                         if (!(addr_high & E1000_RAH_AV))
1477                                 continue;
1478                         addr_low = er32(RAL(i));
1479                         mac_addr[0] = (addr_low & 0xFF);
1480                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1481                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1482                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1483                         mac_addr[4] = (addr_high & 0xFF);
1484                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1485
1486                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1487                 }
1488
1489                 /* Write Rx addresses to the PHY */
1490                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1491
1492                 /* Enable jumbo frame workaround in the MAC */
1493                 mac_reg = er32(FFLT_DBG);
1494                 mac_reg &= ~(1 << 14);
1495                 mac_reg |= (7 << 15);
1496                 ew32(FFLT_DBG, mac_reg);
1497
1498                 mac_reg = er32(RCTL);
1499                 mac_reg |= E1000_RCTL_SECRC;
1500                 ew32(RCTL, mac_reg);
1501
1502                 ret_val = e1000e_read_kmrn_reg(hw,
1503                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1504                                                 &data);
1505                 if (ret_val)
1506                         goto out;
1507                 ret_val = e1000e_write_kmrn_reg(hw,
1508                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1509                                                 data | (1 << 0));
1510                 if (ret_val)
1511                         goto out;
1512                 ret_val = e1000e_read_kmrn_reg(hw,
1513                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1514                                                 &data);
1515                 if (ret_val)
1516                         goto out;
1517                 data &= ~(0xF << 8);
1518                 data |= (0xB << 8);
1519                 ret_val = e1000e_write_kmrn_reg(hw,
1520                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1521                                                 data);
1522                 if (ret_val)
1523                         goto out;
1524
1525                 /* Enable jumbo frame workaround in the PHY */
1526                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1527                 data &= ~(0x7F << 5);
1528                 data |= (0x37 << 5);
1529                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1530                 if (ret_val)
1531                         goto out;
1532                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1533                 data &= ~(1 << 13);
1534                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1535                 if (ret_val)
1536                         goto out;
1537                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1538                 data &= ~(0x3FF << 2);
1539                 data |= (0x1A << 2);
1540                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1541                 if (ret_val)
1542                         goto out;
1543                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1544                 if (ret_val)
1545                         goto out;
1546                 e1e_rphy(hw, HV_PM_CTRL, &data);
1547                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1548                 if (ret_val)
1549                         goto out;
1550         } else {
1551                 /* Write MAC register values back to h/w defaults */
1552                 mac_reg = er32(FFLT_DBG);
1553                 mac_reg &= ~(0xF << 14);
1554                 ew32(FFLT_DBG, mac_reg);
1555
1556                 mac_reg = er32(RCTL);
1557                 mac_reg &= ~E1000_RCTL_SECRC;
1558                 ew32(RCTL, mac_reg);
1559
1560                 ret_val = e1000e_read_kmrn_reg(hw,
1561                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1562                                                 &data);
1563                 if (ret_val)
1564                         goto out;
1565                 ret_val = e1000e_write_kmrn_reg(hw,
1566                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1567                                                 data & ~(1 << 0));
1568                 if (ret_val)
1569                         goto out;
1570                 ret_val = e1000e_read_kmrn_reg(hw,
1571                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1572                                                 &data);
1573                 if (ret_val)
1574                         goto out;
1575                 data &= ~(0xF << 8);
1576                 data |= (0xB << 8);
1577                 ret_val = e1000e_write_kmrn_reg(hw,
1578                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1579                                                 data);
1580                 if (ret_val)
1581                         goto out;
1582
1583                 /* Write PHY register values back to h/w defaults */
1584                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1585                 data &= ~(0x7F << 5);
1586                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1587                 if (ret_val)
1588                         goto out;
1589                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1590                 data |= (1 << 13);
1591                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1592                 if (ret_val)
1593                         goto out;
1594                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1595                 data &= ~(0x3FF << 2);
1596                 data |= (0x8 << 2);
1597                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1598                 if (ret_val)
1599                         goto out;
1600                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1601                 if (ret_val)
1602                         goto out;
1603                 e1e_rphy(hw, HV_PM_CTRL, &data);
1604                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1605                 if (ret_val)
1606                         goto out;
1607         }
1608
1609         /* re-enable Rx path after enabling/disabling workaround */
1610         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1611
1612 out:
1613         return ret_val;
1614 }
1615
1616 /**
1617  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1618  *  done after every PHY reset.
1619  **/
1620 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1621 {
1622         s32 ret_val = 0;
1623
1624         if (hw->mac.type != e1000_pch2lan)
1625                 goto out;
1626
1627         /* Set MDIO slow mode before any other MDIO access */
1628         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1629
1630 out:
1631         return ret_val;
1632 }
1633
1634 /**
1635  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1636  *  @hw:   pointer to the HW structure
1637  *
1638  *  Workaround to set the K1 beacon duration for 82579 parts
1639  **/
1640 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1641 {
1642         s32 ret_val = 0;
1643         u16 status_reg = 0;
1644         u32 mac_reg;
1645
1646         if (hw->mac.type != e1000_pch2lan)
1647                 goto out;
1648
1649         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1650         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1651         if (ret_val)
1652                 goto out;
1653
1654         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1655             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1656                 mac_reg = er32(FEXTNVM4);
1657                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1658
1659                 if (status_reg & HV_M_STATUS_SPEED_1000)
1660                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1661                 else
1662                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1663
1664                 ew32(FEXTNVM4, mac_reg);
1665         }
1666
1667 out:
1668         return ret_val;
1669 }
1670
1671 /**
1672  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1673  *  @hw:   pointer to the HW structure
1674  *  @gate: boolean set to true to gate, false to ungate
1675  *
1676  *  Gate/ungate the automatic PHY configuration via hardware; perform
1677  *  the configuration via software instead.
1678  **/
1679 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1680 {
1681         u32 extcnf_ctrl;
1682
1683         if (hw->mac.type != e1000_pch2lan)
1684                 return;
1685
1686         extcnf_ctrl = er32(EXTCNF_CTRL);
1687
1688         if (gate)
1689                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1690         else
1691                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1692
1693         ew32(EXTCNF_CTRL, extcnf_ctrl);
1694         return;
1695 }
1696
1697 /**
1698  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1699  *  @hw: pointer to the HW structure
1700  *
1701  *  Check the appropriate indication the MAC has finished configuring the
1702  *  PHY after a software reset.
1703  **/
1704 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1705 {
1706         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1707
1708         /* Wait for basic configuration completes before proceeding */
1709         do {
1710                 data = er32(STATUS);
1711                 data &= E1000_STATUS_LAN_INIT_DONE;
1712                 udelay(100);
1713         } while ((!data) && --loop);
1714
1715         /*
1716          * If basic configuration is incomplete before the above loop
1717          * count reaches 0, loading the configuration from NVM will
1718          * leave the PHY in a bad state possibly resulting in no link.
1719          */
1720         if (loop == 0)
1721                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1722
1723         /* Clear the Init Done bit for the next init event */
1724         data = er32(STATUS);
1725         data &= ~E1000_STATUS_LAN_INIT_DONE;
1726         ew32(STATUS, data);
1727 }
1728
1729 /**
1730  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1731  *  @hw: pointer to the HW structure
1732  **/
1733 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1734 {
1735         s32 ret_val = 0;
1736         u16 reg;
1737
1738         if (e1000_check_reset_block(hw))
1739                 goto out;
1740
1741         /* Allow time for h/w to get to quiescent state after reset */
1742         usleep_range(10000, 20000);
1743
1744         /* Perform any necessary post-reset workarounds */
1745         switch (hw->mac.type) {
1746         case e1000_pchlan:
1747                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1748                 if (ret_val)
1749                         goto out;
1750                 break;
1751         case e1000_pch2lan:
1752                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1753                 if (ret_val)
1754                         goto out;
1755                 break;
1756         default:
1757                 break;
1758         }
1759
1760         /* Clear the host wakeup bit after lcd reset */
1761         if (hw->mac.type >= e1000_pchlan) {
1762                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
1763                 reg &= ~BM_WUC_HOST_WU_BIT;
1764                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1765         }
1766
1767         /* Configure the LCD with the extended configuration region in NVM */
1768         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1769         if (ret_val)
1770                 goto out;
1771
1772         /* Configure the LCD with the OEM bits in NVM */
1773         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1774
1775         if (hw->mac.type == e1000_pch2lan) {
1776                 /* Ungate automatic PHY configuration on non-managed 82579 */
1777                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1778                         usleep_range(10000, 20000);
1779                         e1000_gate_hw_phy_config_ich8lan(hw, false);
1780                 }
1781
1782                 /* Set EEE LPI Update Timer to 200usec */
1783                 ret_val = hw->phy.ops.acquire(hw);
1784                 if (ret_val)
1785                         goto out;
1786                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1787                                                        I82579_LPI_UPDATE_TIMER);
1788                 if (ret_val)
1789                         goto release;
1790                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1791                                                        0x1387);
1792 release:
1793                 hw->phy.ops.release(hw);
1794         }
1795
1796 out:
1797         return ret_val;
1798 }
1799
1800 /**
1801  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1802  *  @hw: pointer to the HW structure
1803  *
1804  *  Resets the PHY
1805  *  This is a function pointer entry point called by drivers
1806  *  or other shared routines.
1807  **/
1808 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1809 {
1810         s32 ret_val = 0;
1811
1812         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1813         if ((hw->mac.type == e1000_pch2lan) &&
1814             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1815                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1816
1817         ret_val = e1000e_phy_hw_reset_generic(hw);
1818         if (ret_val)
1819                 goto out;
1820
1821         ret_val = e1000_post_phy_reset_ich8lan(hw);
1822
1823 out:
1824         return ret_val;
1825 }
1826
1827 /**
1828  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1829  *  @hw: pointer to the HW structure
1830  *  @active: true to enable LPLU, false to disable
1831  *
1832  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1833  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1834  *  the phy speed. This function will manually set the LPLU bit and restart
1835  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1836  *  since it configures the same bit.
1837  **/
1838 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1839 {
1840         s32 ret_val = 0;
1841         u16 oem_reg;
1842
1843         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1844         if (ret_val)
1845                 goto out;
1846
1847         if (active)
1848                 oem_reg |= HV_OEM_BITS_LPLU;
1849         else
1850                 oem_reg &= ~HV_OEM_BITS_LPLU;
1851
1852         oem_reg |= HV_OEM_BITS_RESTART_AN;
1853         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1854
1855 out:
1856         return ret_val;
1857 }
1858
1859 /**
1860  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1861  *  @hw: pointer to the HW structure
1862  *  @active: true to enable LPLU, false to disable
1863  *
1864  *  Sets the LPLU D0 state according to the active flag.  When
1865  *  activating LPLU this function also disables smart speed
1866  *  and vice versa.  LPLU will not be activated unless the
1867  *  device autonegotiation advertisement meets standards of
1868  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1869  *  This is a function pointer entry point only called by
1870  *  PHY setup routines.
1871  **/
1872 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1873 {
1874         struct e1000_phy_info *phy = &hw->phy;
1875         u32 phy_ctrl;
1876         s32 ret_val = 0;
1877         u16 data;
1878
1879         if (phy->type == e1000_phy_ife)
1880                 return ret_val;
1881
1882         phy_ctrl = er32(PHY_CTRL);
1883
1884         if (active) {
1885                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1886                 ew32(PHY_CTRL, phy_ctrl);
1887
1888                 if (phy->type != e1000_phy_igp_3)
1889                         return 0;
1890
1891                 /*
1892                  * Call gig speed drop workaround on LPLU before accessing
1893                  * any PHY registers
1894                  */
1895                 if (hw->mac.type == e1000_ich8lan)
1896                         e1000e_gig_downshift_workaround_ich8lan(hw);
1897
1898                 /* When LPLU is enabled, we should disable SmartSpeed */
1899                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1900                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1901                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1902                 if (ret_val)
1903                         return ret_val;
1904         } else {
1905                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1906                 ew32(PHY_CTRL, phy_ctrl);
1907
1908                 if (phy->type != e1000_phy_igp_3)
1909                         return 0;
1910
1911                 /*
1912                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1913                  * during Dx states where the power conservation is most
1914                  * important.  During driver activity we should enable
1915                  * SmartSpeed, so performance is maintained.
1916                  */
1917                 if (phy->smart_speed == e1000_smart_speed_on) {
1918                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1919                                            &data);
1920                         if (ret_val)
1921                                 return ret_val;
1922
1923                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1924                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1925                                            data);
1926                         if (ret_val)
1927                                 return ret_val;
1928                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1929                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1930                                            &data);
1931                         if (ret_val)
1932                                 return ret_val;
1933
1934                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1935                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1936                                            data);
1937                         if (ret_val)
1938                                 return ret_val;
1939                 }
1940         }
1941
1942         return 0;
1943 }
1944
1945 /**
1946  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1947  *  @hw: pointer to the HW structure
1948  *  @active: true to enable LPLU, false to disable
1949  *
1950  *  Sets the LPLU D3 state according to the active flag.  When
1951  *  activating LPLU this function also disables smart speed
1952  *  and vice versa.  LPLU will not be activated unless the
1953  *  device autonegotiation advertisement meets standards of
1954  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1955  *  This is a function pointer entry point only called by
1956  *  PHY setup routines.
1957  **/
1958 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1959 {
1960         struct e1000_phy_info *phy = &hw->phy;
1961         u32 phy_ctrl;
1962         s32 ret_val;
1963         u16 data;
1964
1965         phy_ctrl = er32(PHY_CTRL);
1966
1967         if (!active) {
1968                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1969                 ew32(PHY_CTRL, phy_ctrl);
1970
1971                 if (phy->type != e1000_phy_igp_3)
1972                         return 0;
1973
1974                 /*
1975                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1976                  * during Dx states where the power conservation is most
1977                  * important.  During driver activity we should enable
1978                  * SmartSpeed, so performance is maintained.
1979                  */
1980                 if (phy->smart_speed == e1000_smart_speed_on) {
1981                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1982                                            &data);
1983                         if (ret_val)
1984                                 return ret_val;
1985
1986                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1987                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1988                                            data);
1989                         if (ret_val)
1990                                 return ret_val;
1991                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1992                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1993                                            &data);
1994                         if (ret_val)
1995                                 return ret_val;
1996
1997                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1998                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1999                                            data);
2000                         if (ret_val)
2001                                 return ret_val;
2002                 }
2003         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2004                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2005                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2006                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2007                 ew32(PHY_CTRL, phy_ctrl);
2008
2009                 if (phy->type != e1000_phy_igp_3)
2010                         return 0;
2011
2012                 /*
2013                  * Call gig speed drop workaround on LPLU before accessing
2014                  * any PHY registers
2015                  */
2016                 if (hw->mac.type == e1000_ich8lan)
2017                         e1000e_gig_downshift_workaround_ich8lan(hw);
2018
2019                 /* When LPLU is enabled, we should disable SmartSpeed */
2020                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2021                 if (ret_val)
2022                         return ret_val;
2023
2024                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2025                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2026         }
2027
2028         return 0;
2029 }
2030
2031 /**
2032  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2033  *  @hw: pointer to the HW structure
2034  *  @bank:  pointer to the variable that returns the active bank
2035  *
2036  *  Reads signature byte from the NVM using the flash access registers.
2037  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2038  **/
2039 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2040 {
2041         u32 eecd;
2042         struct e1000_nvm_info *nvm = &hw->nvm;
2043         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2044         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2045         u8 sig_byte = 0;
2046         s32 ret_val = 0;
2047
2048         switch (hw->mac.type) {
2049         case e1000_ich8lan:
2050         case e1000_ich9lan:
2051                 eecd = er32(EECD);
2052                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2053                     E1000_EECD_SEC1VAL_VALID_MASK) {
2054                         if (eecd & E1000_EECD_SEC1VAL)
2055                                 *bank = 1;
2056                         else
2057                                 *bank = 0;
2058
2059                         return 0;
2060                 }
2061                 e_dbg("Unable to determine valid NVM bank via EEC - "
2062                        "reading flash signature\n");
2063                 /* fall-thru */
2064         default:
2065                 /* set bank to 0 in case flash read fails */
2066                 *bank = 0;
2067
2068                 /* Check bank 0 */
2069                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2070                                                         &sig_byte);
2071                 if (ret_val)
2072                         return ret_val;
2073                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2074                     E1000_ICH_NVM_SIG_VALUE) {
2075                         *bank = 0;
2076                         return 0;
2077                 }
2078
2079                 /* Check bank 1 */
2080                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2081                                                         bank1_offset,
2082                                                         &sig_byte);
2083                 if (ret_val)
2084                         return ret_val;
2085                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2086                     E1000_ICH_NVM_SIG_VALUE) {
2087                         *bank = 1;
2088                         return 0;
2089                 }
2090
2091                 e_dbg("ERROR: No valid NVM bank present\n");
2092                 return -E1000_ERR_NVM;
2093         }
2094
2095         return 0;
2096 }
2097
2098 /**
2099  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2100  *  @hw: pointer to the HW structure
2101  *  @offset: The offset (in bytes) of the word(s) to read.
2102  *  @words: Size of data to read in words
2103  *  @data: Pointer to the word(s) to read at offset.
2104  *
2105  *  Reads a word(s) from the NVM using the flash access registers.
2106  **/
2107 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2108                                   u16 *data)
2109 {
2110         struct e1000_nvm_info *nvm = &hw->nvm;
2111         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2112         u32 act_offset;
2113         s32 ret_val = 0;
2114         u32 bank = 0;
2115         u16 i, word;
2116
2117         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2118             (words == 0)) {
2119                 e_dbg("nvm parameter(s) out of bounds\n");
2120                 ret_val = -E1000_ERR_NVM;
2121                 goto out;
2122         }
2123
2124         nvm->ops.acquire(hw);
2125
2126         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2127         if (ret_val) {
2128                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2129                 bank = 0;
2130         }
2131
2132         act_offset = (bank) ? nvm->flash_bank_size : 0;
2133         act_offset += offset;
2134
2135         ret_val = 0;
2136         for (i = 0; i < words; i++) {
2137                 if ((dev_spec->shadow_ram) &&
2138                     (dev_spec->shadow_ram[offset+i].modified)) {
2139                         data[i] = dev_spec->shadow_ram[offset+i].value;
2140                 } else {
2141                         ret_val = e1000_read_flash_word_ich8lan(hw,
2142                                                                 act_offset + i,
2143                                                                 &word);
2144                         if (ret_val)
2145                                 break;
2146                         data[i] = word;
2147                 }
2148         }
2149
2150         nvm->ops.release(hw);
2151
2152 out:
2153         if (ret_val)
2154                 e_dbg("NVM read error: %d\n", ret_val);
2155
2156         return ret_val;
2157 }
2158
2159 /**
2160  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2161  *  @hw: pointer to the HW structure
2162  *
2163  *  This function does initial flash setup so that a new read/write/erase cycle
2164  *  can be started.
2165  **/
2166 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2167 {
2168         union ich8_hws_flash_status hsfsts;
2169         s32 ret_val = -E1000_ERR_NVM;
2170
2171         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2172
2173         /* Check if the flash descriptor is valid */
2174         if (hsfsts.hsf_status.fldesvalid == 0) {
2175                 e_dbg("Flash descriptor invalid.  "
2176                          "SW Sequencing must be used.\n");
2177                 return -E1000_ERR_NVM;
2178         }
2179
2180         /* Clear FCERR and DAEL in hw status by writing 1 */
2181         hsfsts.hsf_status.flcerr = 1;
2182         hsfsts.hsf_status.dael = 1;
2183
2184         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2185
2186         /*
2187          * Either we should have a hardware SPI cycle in progress
2188          * bit to check against, in order to start a new cycle or
2189          * FDONE bit should be changed in the hardware so that it
2190          * is 1 after hardware reset, which can then be used as an
2191          * indication whether a cycle is in progress or has been
2192          * completed.
2193          */
2194
2195         if (hsfsts.hsf_status.flcinprog == 0) {
2196                 /*
2197                  * There is no cycle running at present,
2198                  * so we can start a cycle.
2199                  * Begin by setting Flash Cycle Done.
2200                  */
2201                 hsfsts.hsf_status.flcdone = 1;
2202                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2203                 ret_val = 0;
2204         } else {
2205                 s32 i = 0;
2206
2207                 /*
2208                  * Otherwise poll for sometime so the current
2209                  * cycle has a chance to end before giving up.
2210                  */
2211                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2212                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2213                         if (hsfsts.hsf_status.flcinprog == 0) {
2214                                 ret_val = 0;
2215                                 break;
2216                         }
2217                         udelay(1);
2218                 }
2219                 if (ret_val == 0) {
2220                         /*
2221                          * Successful in waiting for previous cycle to timeout,
2222                          * now set the Flash Cycle Done.
2223                          */
2224                         hsfsts.hsf_status.flcdone = 1;
2225                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2226                 } else {
2227                         e_dbg("Flash controller busy, cannot get access\n");
2228                 }
2229         }
2230
2231         return ret_val;
2232 }
2233
2234 /**
2235  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2236  *  @hw: pointer to the HW structure
2237  *  @timeout: maximum time to wait for completion
2238  *
2239  *  This function starts a flash cycle and waits for its completion.
2240  **/
2241 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2242 {
2243         union ich8_hws_flash_ctrl hsflctl;
2244         union ich8_hws_flash_status hsfsts;
2245         s32 ret_val = -E1000_ERR_NVM;
2246         u32 i = 0;
2247
2248         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2249         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2250         hsflctl.hsf_ctrl.flcgo = 1;
2251         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2252
2253         /* wait till FDONE bit is set to 1 */
2254         do {
2255                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2256                 if (hsfsts.hsf_status.flcdone == 1)
2257                         break;
2258                 udelay(1);
2259         } while (i++ < timeout);
2260
2261         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2262                 return 0;
2263
2264         return ret_val;
2265 }
2266
2267 /**
2268  *  e1000_read_flash_word_ich8lan - Read word from flash
2269  *  @hw: pointer to the HW structure
2270  *  @offset: offset to data location
2271  *  @data: pointer to the location for storing the data
2272  *
2273  *  Reads the flash word at offset into data.  Offset is converted
2274  *  to bytes before read.
2275  **/
2276 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2277                                          u16 *data)
2278 {
2279         /* Must convert offset into bytes. */
2280         offset <<= 1;
2281
2282         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2283 }
2284
2285 /**
2286  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2287  *  @hw: pointer to the HW structure
2288  *  @offset: The offset of the byte to read.
2289  *  @data: Pointer to a byte to store the value read.
2290  *
2291  *  Reads a single byte from the NVM using the flash access registers.
2292  **/
2293 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2294                                          u8 *data)
2295 {
2296         s32 ret_val;
2297         u16 word = 0;
2298
2299         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2300         if (ret_val)
2301                 return ret_val;
2302
2303         *data = (u8)word;
2304
2305         return 0;
2306 }
2307
2308 /**
2309  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2310  *  @hw: pointer to the HW structure
2311  *  @offset: The offset (in bytes) of the byte or word to read.
2312  *  @size: Size of data to read, 1=byte 2=word
2313  *  @data: Pointer to the word to store the value read.
2314  *
2315  *  Reads a byte or word from the NVM using the flash access registers.
2316  **/
2317 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2318                                          u8 size, u16 *data)
2319 {
2320         union ich8_hws_flash_status hsfsts;
2321         union ich8_hws_flash_ctrl hsflctl;
2322         u32 flash_linear_addr;
2323         u32 flash_data = 0;
2324         s32 ret_val = -E1000_ERR_NVM;
2325         u8 count = 0;
2326
2327         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2328                 return -E1000_ERR_NVM;
2329
2330         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2331                             hw->nvm.flash_base_addr;
2332
2333         do {
2334                 udelay(1);
2335                 /* Steps */
2336                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2337                 if (ret_val != 0)
2338                         break;
2339
2340                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2341                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2342                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2343                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2344                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2345
2346                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2347
2348                 ret_val = e1000_flash_cycle_ich8lan(hw,
2349                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2350
2351                 /*
2352                  * Check if FCERR is set to 1, if set to 1, clear it
2353                  * and try the whole sequence a few more times, else
2354                  * read in (shift in) the Flash Data0, the order is
2355                  * least significant byte first msb to lsb
2356                  */
2357                 if (ret_val == 0) {
2358                         flash_data = er32flash(ICH_FLASH_FDATA0);
2359                         if (size == 1)
2360                                 *data = (u8)(flash_data & 0x000000FF);
2361                         else if (size == 2)
2362                                 *data = (u16)(flash_data & 0x0000FFFF);
2363                         break;
2364                 } else {
2365                         /*
2366                          * If we've gotten here, then things are probably
2367                          * completely hosed, but if the error condition is
2368                          * detected, it won't hurt to give it another try...
2369                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2370                          */
2371                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2372                         if (hsfsts.hsf_status.flcerr == 1) {
2373                                 /* Repeat for some time before giving up. */
2374                                 continue;
2375                         } else if (hsfsts.hsf_status.flcdone == 0) {
2376                                 e_dbg("Timeout error - flash cycle "
2377                                          "did not complete.\n");
2378                                 break;
2379                         }
2380                 }
2381         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2382
2383         return ret_val;
2384 }
2385
2386 /**
2387  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2388  *  @hw: pointer to the HW structure
2389  *  @offset: The offset (in bytes) of the word(s) to write.
2390  *  @words: Size of data to write in words
2391  *  @data: Pointer to the word(s) to write at offset.
2392  *
2393  *  Writes a byte or word to the NVM using the flash access registers.
2394  **/
2395 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2396                                    u16 *data)
2397 {
2398         struct e1000_nvm_info *nvm = &hw->nvm;
2399         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2400         u16 i;
2401
2402         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2403             (words == 0)) {
2404                 e_dbg("nvm parameter(s) out of bounds\n");
2405                 return -E1000_ERR_NVM;
2406         }
2407
2408         nvm->ops.acquire(hw);
2409
2410         for (i = 0; i < words; i++) {
2411                 dev_spec->shadow_ram[offset+i].modified = true;
2412                 dev_spec->shadow_ram[offset+i].value = data[i];
2413         }
2414
2415         nvm->ops.release(hw);
2416
2417         return 0;
2418 }
2419
2420 /**
2421  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2422  *  @hw: pointer to the HW structure
2423  *
2424  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2425  *  which writes the checksum to the shadow ram.  The changes in the shadow
2426  *  ram are then committed to the EEPROM by processing each bank at a time
2427  *  checking for the modified bit and writing only the pending changes.
2428  *  After a successful commit, the shadow ram is cleared and is ready for
2429  *  future writes.
2430  **/
2431 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2432 {
2433         struct e1000_nvm_info *nvm = &hw->nvm;
2434         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2435         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2436         s32 ret_val;
2437         u16 data;
2438
2439         ret_val = e1000e_update_nvm_checksum_generic(hw);
2440         if (ret_val)
2441                 goto out;
2442
2443         if (nvm->type != e1000_nvm_flash_sw)
2444                 goto out;
2445
2446         nvm->ops.acquire(hw);
2447
2448         /*
2449          * We're writing to the opposite bank so if we're on bank 1,
2450          * write to bank 0 etc.  We also need to erase the segment that
2451          * is going to be written
2452          */
2453         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2454         if (ret_val) {
2455                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2456                 bank = 0;
2457         }
2458
2459         if (bank == 0) {
2460                 new_bank_offset = nvm->flash_bank_size;
2461                 old_bank_offset = 0;
2462                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2463                 if (ret_val)
2464                         goto release;
2465         } else {
2466                 old_bank_offset = nvm->flash_bank_size;
2467                 new_bank_offset = 0;
2468                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2469                 if (ret_val)
2470                         goto release;
2471         }
2472
2473         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2474                 /*
2475                  * Determine whether to write the value stored
2476                  * in the other NVM bank or a modified value stored
2477                  * in the shadow RAM
2478                  */
2479                 if (dev_spec->shadow_ram[i].modified) {
2480                         data = dev_spec->shadow_ram[i].value;
2481                 } else {
2482                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2483                                                                 old_bank_offset,
2484                                                                 &data);
2485                         if (ret_val)
2486                                 break;
2487                 }
2488
2489                 /*
2490                  * If the word is 0x13, then make sure the signature bits
2491                  * (15:14) are 11b until the commit has completed.
2492                  * This will allow us to write 10b which indicates the
2493                  * signature is valid.  We want to do this after the write
2494                  * has completed so that we don't mark the segment valid
2495                  * while the write is still in progress
2496                  */
2497                 if (i == E1000_ICH_NVM_SIG_WORD)
2498                         data |= E1000_ICH_NVM_SIG_MASK;
2499
2500                 /* Convert offset to bytes. */
2501                 act_offset = (i + new_bank_offset) << 1;
2502
2503                 udelay(100);
2504                 /* Write the bytes to the new bank. */
2505                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2506                                                                act_offset,
2507                                                                (u8)data);
2508                 if (ret_val)
2509                         break;
2510
2511                 udelay(100);
2512                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2513                                                           act_offset + 1,
2514                                                           (u8)(data >> 8));
2515                 if (ret_val)
2516                         break;
2517         }
2518
2519         /*
2520          * Don't bother writing the segment valid bits if sector
2521          * programming failed.
2522          */
2523         if (ret_val) {
2524                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2525                 e_dbg("Flash commit failed.\n");
2526                 goto release;
2527         }
2528
2529         /*
2530          * Finally validate the new segment by setting bit 15:14
2531          * to 10b in word 0x13 , this can be done without an
2532          * erase as well since these bits are 11 to start with
2533          * and we need to change bit 14 to 0b
2534          */
2535         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2536         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2537         if (ret_val)
2538                 goto release;
2539
2540         data &= 0xBFFF;
2541         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2542                                                        act_offset * 2 + 1,
2543                                                        (u8)(data >> 8));
2544         if (ret_val)
2545                 goto release;
2546
2547         /*
2548          * And invalidate the previously valid segment by setting
2549          * its signature word (0x13) high_byte to 0b. This can be
2550          * done without an erase because flash erase sets all bits
2551          * to 1's. We can write 1's to 0's without an erase
2552          */
2553         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2554         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2555         if (ret_val)
2556                 goto release;
2557
2558         /* Great!  Everything worked, we can now clear the cached entries. */
2559         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2560                 dev_spec->shadow_ram[i].modified = false;
2561                 dev_spec->shadow_ram[i].value = 0xFFFF;
2562         }
2563
2564 release:
2565         nvm->ops.release(hw);
2566
2567         /*
2568          * Reload the EEPROM, or else modifications will not appear
2569          * until after the next adapter reset.
2570          */
2571         if (!ret_val) {
2572                 e1000e_reload_nvm(hw);
2573                 usleep_range(10000, 20000);
2574         }
2575
2576 out:
2577         if (ret_val)
2578                 e_dbg("NVM update error: %d\n", ret_val);
2579
2580         return ret_val;
2581 }
2582
2583 /**
2584  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2585  *  @hw: pointer to the HW structure
2586  *
2587  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2588  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2589  *  calculated, in which case we need to calculate the checksum and set bit 6.
2590  **/
2591 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2592 {
2593         s32 ret_val;
2594         u16 data;
2595
2596         /*
2597          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2598          * needs to be fixed.  This bit is an indication that the NVM
2599          * was prepared by OEM software and did not calculate the
2600          * checksum...a likely scenario.
2601          */
2602         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2603         if (ret_val)
2604                 return ret_val;
2605
2606         if ((data & 0x40) == 0) {
2607                 data |= 0x40;
2608                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2609                 if (ret_val)
2610                         return ret_val;
2611                 ret_val = e1000e_update_nvm_checksum(hw);
2612                 if (ret_val)
2613                         return ret_val;
2614         }
2615
2616         return e1000e_validate_nvm_checksum_generic(hw);
2617 }
2618
2619 /**
2620  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2621  *  @hw: pointer to the HW structure
2622  *
2623  *  To prevent malicious write/erase of the NVM, set it to be read-only
2624  *  so that the hardware ignores all write/erase cycles of the NVM via
2625  *  the flash control registers.  The shadow-ram copy of the NVM will
2626  *  still be updated, however any updates to this copy will not stick
2627  *  across driver reloads.
2628  **/
2629 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2630 {
2631         struct e1000_nvm_info *nvm = &hw->nvm;
2632         union ich8_flash_protected_range pr0;
2633         union ich8_hws_flash_status hsfsts;
2634         u32 gfpreg;
2635
2636         nvm->ops.acquire(hw);
2637
2638         gfpreg = er32flash(ICH_FLASH_GFPREG);
2639
2640         /* Write-protect GbE Sector of NVM */
2641         pr0.regval = er32flash(ICH_FLASH_PR0);
2642         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2643         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2644         pr0.range.wpe = true;
2645         ew32flash(ICH_FLASH_PR0, pr0.regval);
2646
2647         /*
2648          * Lock down a subset of GbE Flash Control Registers, e.g.
2649          * PR0 to prevent the write-protection from being lifted.
2650          * Once FLOCKDN is set, the registers protected by it cannot
2651          * be written until FLOCKDN is cleared by a hardware reset.
2652          */
2653         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2654         hsfsts.hsf_status.flockdn = true;
2655         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2656
2657         nvm->ops.release(hw);
2658 }
2659
2660 /**
2661  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2662  *  @hw: pointer to the HW structure
2663  *  @offset: The offset (in bytes) of the byte/word to read.
2664  *  @size: Size of data to read, 1=byte 2=word
2665  *  @data: The byte(s) to write to the NVM.
2666  *
2667  *  Writes one/two bytes to the NVM using the flash access registers.
2668  **/
2669 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2670                                           u8 size, u16 data)
2671 {
2672         union ich8_hws_flash_status hsfsts;
2673         union ich8_hws_flash_ctrl hsflctl;
2674         u32 flash_linear_addr;
2675         u32 flash_data = 0;
2676         s32 ret_val;
2677         u8 count = 0;
2678
2679         if (size < 1 || size > 2 || data > size * 0xff ||
2680             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2681                 return -E1000_ERR_NVM;
2682
2683         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2684                             hw->nvm.flash_base_addr;
2685
2686         do {
2687                 udelay(1);
2688                 /* Steps */
2689                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2690                 if (ret_val)
2691                         break;
2692
2693                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2694                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2695                 hsflctl.hsf_ctrl.fldbcount = size -1;
2696                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2697                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2698
2699                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2700
2701                 if (size == 1)
2702                         flash_data = (u32)data & 0x00FF;
2703                 else
2704                         flash_data = (u32)data;
2705
2706                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2707
2708                 /*
2709                  * check if FCERR is set to 1 , if set to 1, clear it
2710                  * and try the whole sequence a few more times else done
2711                  */
2712                 ret_val = e1000_flash_cycle_ich8lan(hw,
2713                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2714                 if (!ret_val)
2715                         break;
2716
2717                 /*
2718                  * If we're here, then things are most likely
2719                  * completely hosed, but if the error condition
2720                  * is detected, it won't hurt to give it another
2721                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2722                  */
2723                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2724                 if (hsfsts.hsf_status.flcerr == 1)
2725                         /* Repeat for some time before giving up. */
2726                         continue;
2727                 if (hsfsts.hsf_status.flcdone == 0) {
2728                         e_dbg("Timeout error - flash cycle "
2729                                  "did not complete.");
2730                         break;
2731                 }
2732         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2733
2734         return ret_val;
2735 }
2736
2737 /**
2738  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2739  *  @hw: pointer to the HW structure
2740  *  @offset: The index of the byte to read.
2741  *  @data: The byte to write to the NVM.
2742  *
2743  *  Writes a single byte to the NVM using the flash access registers.
2744  **/
2745 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2746                                           u8 data)
2747 {
2748         u16 word = (u16)data;
2749
2750         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2751 }
2752
2753 /**
2754  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2755  *  @hw: pointer to the HW structure
2756  *  @offset: The offset of the byte to write.
2757  *  @byte: The byte to write to the NVM.
2758  *
2759  *  Writes a single byte to the NVM using the flash access registers.
2760  *  Goes through a retry algorithm before giving up.
2761  **/
2762 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2763                                                 u32 offset, u8 byte)
2764 {
2765         s32 ret_val;
2766         u16 program_retries;
2767
2768         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2769         if (!ret_val)
2770                 return ret_val;
2771
2772         for (program_retries = 0; program_retries < 100; program_retries++) {
2773                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2774                 udelay(100);
2775                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2776                 if (!ret_val)
2777                         break;
2778         }
2779         if (program_retries == 100)
2780                 return -E1000_ERR_NVM;
2781
2782         return 0;
2783 }
2784
2785 /**
2786  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2787  *  @hw: pointer to the HW structure
2788  *  @bank: 0 for first bank, 1 for second bank, etc.
2789  *
2790  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2791  *  bank N is 4096 * N + flash_reg_addr.
2792  **/
2793 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2794 {
2795         struct e1000_nvm_info *nvm = &hw->nvm;
2796         union ich8_hws_flash_status hsfsts;
2797         union ich8_hws_flash_ctrl hsflctl;
2798         u32 flash_linear_addr;
2799         /* bank size is in 16bit words - adjust to bytes */
2800         u32 flash_bank_size = nvm->flash_bank_size * 2;
2801         s32 ret_val;
2802         s32 count = 0;
2803         s32 j, iteration, sector_size;
2804
2805         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2806
2807         /*
2808          * Determine HW Sector size: Read BERASE bits of hw flash status
2809          * register
2810          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2811          *     consecutive sectors.  The start index for the nth Hw sector
2812          *     can be calculated as = bank * 4096 + n * 256
2813          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2814          *     The start index for the nth Hw sector can be calculated
2815          *     as = bank * 4096
2816          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2817          *     (ich9 only, otherwise error condition)
2818          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2819          */
2820         switch (hsfsts.hsf_status.berasesz) {
2821         case 0:
2822                 /* Hw sector size 256 */
2823                 sector_size = ICH_FLASH_SEG_SIZE_256;
2824                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2825                 break;
2826         case 1:
2827                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2828                 iteration = 1;
2829                 break;
2830         case 2:
2831                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2832                 iteration = 1;
2833                 break;
2834         case 3:
2835                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2836                 iteration = 1;
2837                 break;
2838         default:
2839                 return -E1000_ERR_NVM;
2840         }
2841
2842         /* Start with the base address, then add the sector offset. */
2843         flash_linear_addr = hw->nvm.flash_base_addr;
2844         flash_linear_addr += (bank) ? flash_bank_size : 0;
2845
2846         for (j = 0; j < iteration ; j++) {
2847                 do {
2848                         /* Steps */
2849                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2850                         if (ret_val)
2851                                 return ret_val;
2852
2853                         /*
2854                          * Write a value 11 (block Erase) in Flash
2855                          * Cycle field in hw flash control
2856                          */
2857                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2858                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2859                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2860
2861                         /*
2862                          * Write the last 24 bits of an index within the
2863                          * block into Flash Linear address field in Flash
2864                          * Address.
2865                          */
2866                         flash_linear_addr += (j * sector_size);
2867                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2868
2869                         ret_val = e1000_flash_cycle_ich8lan(hw,
2870                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2871                         if (ret_val == 0)
2872                                 break;
2873
2874                         /*
2875                          * Check if FCERR is set to 1.  If 1,
2876                          * clear it and try the whole sequence
2877                          * a few more times else Done
2878                          */
2879                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2880                         if (hsfsts.hsf_status.flcerr == 1)
2881                                 /* repeat for some time before giving up */
2882                                 continue;
2883                         else if (hsfsts.hsf_status.flcdone == 0)
2884                                 return ret_val;
2885                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2886         }
2887
2888         return 0;
2889 }
2890
2891 /**
2892  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2893  *  @hw: pointer to the HW structure
2894  *  @data: Pointer to the LED settings
2895  *
2896  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2897  *  settings is all 0's or F's, set the LED default to a valid LED default
2898  *  setting.
2899  **/
2900 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2901 {
2902         s32 ret_val;
2903
2904         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2905         if (ret_val) {
2906                 e_dbg("NVM Read Error\n");
2907                 return ret_val;
2908         }
2909
2910         if (*data == ID_LED_RESERVED_0000 ||
2911             *data == ID_LED_RESERVED_FFFF)
2912                 *data = ID_LED_DEFAULT_ICH8LAN;
2913
2914         return 0;
2915 }
2916
2917 /**
2918  *  e1000_id_led_init_pchlan - store LED configurations
2919  *  @hw: pointer to the HW structure
2920  *
2921  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2922  *  the PHY LED configuration register.
2923  *
2924  *  PCH also does not have an "always on" or "always off" mode which
2925  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2926  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2927  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2928  *  link based on logic in e1000_led_[on|off]_pchlan().
2929  **/
2930 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2931 {
2932         struct e1000_mac_info *mac = &hw->mac;
2933         s32 ret_val;
2934         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2935         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2936         u16 data, i, temp, shift;
2937
2938         /* Get default ID LED modes */
2939         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2940         if (ret_val)
2941                 goto out;
2942
2943         mac->ledctl_default = er32(LEDCTL);
2944         mac->ledctl_mode1 = mac->ledctl_default;
2945         mac->ledctl_mode2 = mac->ledctl_default;
2946
2947         for (i = 0; i < 4; i++) {
2948                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2949                 shift = (i * 5);
2950                 switch (temp) {
2951                 case ID_LED_ON1_DEF2:
2952                 case ID_LED_ON1_ON2:
2953                 case ID_LED_ON1_OFF2:
2954                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2955                         mac->ledctl_mode1 |= (ledctl_on << shift);
2956                         break;
2957                 case ID_LED_OFF1_DEF2:
2958                 case ID_LED_OFF1_ON2:
2959                 case ID_LED_OFF1_OFF2:
2960                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2961                         mac->ledctl_mode1 |= (ledctl_off << shift);
2962                         break;
2963                 default:
2964                         /* Do nothing */
2965                         break;
2966                 }
2967                 switch (temp) {
2968                 case ID_LED_DEF1_ON2:
2969                 case ID_LED_ON1_ON2:
2970                 case ID_LED_OFF1_ON2:
2971                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2972                         mac->ledctl_mode2 |= (ledctl_on << shift);
2973                         break;
2974                 case ID_LED_DEF1_OFF2:
2975                 case ID_LED_ON1_OFF2:
2976                 case ID_LED_OFF1_OFF2:
2977                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2978                         mac->ledctl_mode2 |= (ledctl_off << shift);
2979                         break;
2980                 default:
2981                         /* Do nothing */
2982                         break;
2983                 }
2984         }
2985
2986 out:
2987         return ret_val;
2988 }
2989
2990 /**
2991  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2992  *  @hw: pointer to the HW structure
2993  *
2994  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2995  *  register, so the the bus width is hard coded.
2996  **/
2997 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2998 {
2999         struct e1000_bus_info *bus = &hw->bus;
3000         s32 ret_val;
3001
3002         ret_val = e1000e_get_bus_info_pcie(hw);
3003
3004         /*
3005          * ICH devices are "PCI Express"-ish.  They have
3006          * a configuration space, but do not contain
3007          * PCI Express Capability registers, so bus width
3008          * must be hardcoded.
3009          */
3010         if (bus->width == e1000_bus_width_unknown)
3011                 bus->width = e1000_bus_width_pcie_x1;
3012
3013         return ret_val;
3014 }
3015
3016 /**
3017  *  e1000_reset_hw_ich8lan - Reset the hardware
3018  *  @hw: pointer to the HW structure
3019  *
3020  *  Does a full reset of the hardware which includes a reset of the PHY and
3021  *  MAC.
3022  **/
3023 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3024 {
3025         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3026         u16 reg;
3027         u32 ctrl, kab;
3028         s32 ret_val;
3029
3030         /*
3031          * Prevent the PCI-E bus from sticking if there is no TLP connection
3032          * on the last TLP read/write transaction when MAC is reset.
3033          */
3034         ret_val = e1000e_disable_pcie_master(hw);
3035         if (ret_val)
3036                 e_dbg("PCI-E Master disable polling has failed.\n");
3037
3038         e_dbg("Masking off all interrupts\n");
3039         ew32(IMC, 0xffffffff);
3040
3041         /*
3042          * Disable the Transmit and Receive units.  Then delay to allow
3043          * any pending transactions to complete before we hit the MAC
3044          * with the global reset.
3045          */
3046         ew32(RCTL, 0);
3047         ew32(TCTL, E1000_TCTL_PSP);
3048         e1e_flush();
3049
3050         usleep_range(10000, 20000);
3051
3052         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3053         if (hw->mac.type == e1000_ich8lan) {
3054                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3055                 ew32(PBA, E1000_PBA_8K);
3056                 /* Set Packet Buffer Size to 16k. */
3057                 ew32(PBS, E1000_PBS_16K);
3058         }
3059
3060         if (hw->mac.type == e1000_pchlan) {
3061                 /* Save the NVM K1 bit setting*/
3062                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3063                 if (ret_val)
3064                         return ret_val;
3065
3066                 if (reg & E1000_NVM_K1_ENABLE)
3067                         dev_spec->nvm_k1_enabled = true;
3068                 else
3069                         dev_spec->nvm_k1_enabled = false;
3070         }
3071
3072         ctrl = er32(CTRL);
3073
3074         if (!e1000_check_reset_block(hw)) {
3075                 /*
3076                  * Full-chip reset requires MAC and PHY reset at the same
3077                  * time to make sure the interface between MAC and the
3078                  * external PHY is reset.
3079                  */
3080                 ctrl |= E1000_CTRL_PHY_RST;
3081
3082                 /*
3083                  * Gate automatic PHY configuration by hardware on
3084                  * non-managed 82579
3085                  */
3086                 if ((hw->mac.type == e1000_pch2lan) &&
3087                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3088                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3089         }
3090         ret_val = e1000_acquire_swflag_ich8lan(hw);
3091         e_dbg("Issuing a global reset to ich8lan\n");
3092         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3093         msleep(20);
3094
3095         if (!ret_val)
3096                 mutex_unlock(&swflag_mutex);
3097
3098         if (ctrl & E1000_CTRL_PHY_RST) {
3099                 ret_val = hw->phy.ops.get_cfg_done(hw);
3100                 if (ret_val)
3101                         goto out;
3102
3103                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3104                 if (ret_val)
3105                         goto out;
3106         }
3107
3108         /*
3109          * For PCH, this write will make sure that any noise
3110          * will be detected as a CRC error and be dropped rather than show up
3111          * as a bad packet to the DMA engine.
3112          */
3113         if (hw->mac.type == e1000_pchlan)
3114                 ew32(CRC_OFFSET, 0x65656565);
3115
3116         ew32(IMC, 0xffffffff);
3117         er32(ICR);
3118
3119         kab = er32(KABGTXD);
3120         kab |= E1000_KABGTXD_BGSQLBIAS;
3121         ew32(KABGTXD, kab);
3122
3123 out:
3124         return ret_val;
3125 }
3126
3127 /**
3128  *  e1000_init_hw_ich8lan - Initialize the hardware
3129  *  @hw: pointer to the HW structure
3130  *
3131  *  Prepares the hardware for transmit and receive by doing the following:
3132  *   - initialize hardware bits
3133  *   - initialize LED identification
3134  *   - setup receive address registers
3135  *   - setup flow control
3136  *   - setup transmit descriptors
3137  *   - clear statistics
3138  **/
3139 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3140 {
3141         struct e1000_mac_info *mac = &hw->mac;
3142         u32 ctrl_ext, txdctl, snoop;
3143         s32 ret_val;
3144         u16 i;
3145
3146         e1000_initialize_hw_bits_ich8lan(hw);
3147
3148         /* Initialize identification LED */
3149         ret_val = mac->ops.id_led_init(hw);
3150         if (ret_val)
3151                 e_dbg("Error initializing identification LED\n");
3152                 /* This is not fatal and we should not stop init due to this */
3153
3154         /* Setup the receive address. */
3155         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3156
3157         /* Zero out the Multicast HASH table */
3158         e_dbg("Zeroing the MTA\n");
3159         for (i = 0; i < mac->mta_reg_count; i++)
3160                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3161
3162         /*
3163          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3164          * the ME.  Disable wakeup by clearing the host wakeup bit.
3165          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3166          */
3167         if (hw->phy.type == e1000_phy_82578) {
3168                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3169                 i &= ~BM_WUC_HOST_WU_BIT;
3170                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3171                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3172                 if (ret_val)
3173                         return ret_val;
3174         }
3175
3176         /* Setup link and flow control */
3177         ret_val = e1000_setup_link_ich8lan(hw);
3178
3179         /* Set the transmit descriptor write-back policy for both queues */
3180         txdctl = er32(TXDCTL(0));
3181         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3182                  E1000_TXDCTL_FULL_TX_DESC_WB;
3183         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3184                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3185         ew32(TXDCTL(0), txdctl);
3186         txdctl = er32(TXDCTL(1));
3187         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3188                  E1000_TXDCTL_FULL_TX_DESC_WB;
3189         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3190                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3191         ew32(TXDCTL(1), txdctl);
3192
3193         /*
3194          * ICH8 has opposite polarity of no_snoop bits.
3195          * By default, we should use snoop behavior.
3196          */
3197         if (mac->type == e1000_ich8lan)
3198                 snoop = PCIE_ICH8_SNOOP_ALL;
3199         else
3200                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3201         e1000e_set_pcie_no_snoop(hw, snoop);
3202
3203         ctrl_ext = er32(CTRL_EXT);
3204         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3205         ew32(CTRL_EXT, ctrl_ext);
3206
3207         /*
3208          * Clear all of the statistics registers (clear on read).  It is
3209          * important that we do this after we have tried to establish link
3210          * because the symbol error count will increment wildly if there
3211          * is no link.
3212          */
3213         e1000_clear_hw_cntrs_ich8lan(hw);
3214
3215         return 0;
3216 }
3217 /**
3218  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3219  *  @hw: pointer to the HW structure
3220  *
3221  *  Sets/Clears required hardware bits necessary for correctly setting up the
3222  *  hardware for transmit and receive.
3223  **/
3224 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3225 {
3226         u32 reg;
3227
3228         /* Extended Device Control */
3229         reg = er32(CTRL_EXT);
3230         reg |= (1 << 22);
3231         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3232         if (hw->mac.type >= e1000_pchlan)
3233                 reg |= E1000_CTRL_EXT_PHYPDEN;
3234         ew32(CTRL_EXT, reg);
3235
3236         /* Transmit Descriptor Control 0 */
3237         reg = er32(TXDCTL(0));
3238         reg |= (1 << 22);
3239         ew32(TXDCTL(0), reg);
3240
3241         /* Transmit Descriptor Control 1 */
3242         reg = er32(TXDCTL(1));
3243         reg |= (1 << 22);
3244         ew32(TXDCTL(1), reg);
3245
3246         /* Transmit Arbitration Control 0 */
3247         reg = er32(TARC(0));
3248         if (hw->mac.type == e1000_ich8lan)
3249                 reg |= (1 << 28) | (1 << 29);
3250         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3251         ew32(TARC(0), reg);
3252
3253         /* Transmit Arbitration Control 1 */
3254         reg = er32(TARC(1));
3255         if (er32(TCTL) & E1000_TCTL_MULR)
3256                 reg &= ~(1 << 28);
3257         else
3258                 reg |= (1 << 28);
3259         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3260         ew32(TARC(1), reg);
3261
3262         /* Device Status */
3263         if (hw->mac.type == e1000_ich8lan) {
3264                 reg = er32(STATUS);
3265                 reg &= ~(1 << 31);
3266                 ew32(STATUS, reg);
3267         }
3268
3269         /*
3270          * work-around descriptor data corruption issue during nfs v2 udp
3271          * traffic, just disable the nfs filtering capability
3272          */
3273         reg = er32(RFCTL);
3274         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3275         ew32(RFCTL, reg);
3276 }
3277
3278 /**
3279  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3280  *  @hw: pointer to the HW structure
3281  *
3282  *  Determines which flow control settings to use, then configures flow
3283  *  control.  Calls the appropriate media-specific link configuration
3284  *  function.  Assuming the adapter has a valid link partner, a valid link
3285  *  should be established.  Assumes the hardware has previously been reset
3286  *  and the transmitter and receiver are not enabled.
3287  **/
3288 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3289 {
3290         s32 ret_val;
3291
3292         if (e1000_check_reset_block(hw))
3293                 return 0;
3294
3295         /*
3296          * ICH parts do not have a word in the NVM to determine
3297          * the default flow control setting, so we explicitly
3298          * set it to full.
3299          */
3300         if (hw->fc.requested_mode == e1000_fc_default) {
3301                 /* Workaround h/w hang when Tx flow control enabled */
3302                 if (hw->mac.type == e1000_pchlan)
3303                         hw->fc.requested_mode = e1000_fc_rx_pause;
3304                 else
3305                         hw->fc.requested_mode = e1000_fc_full;
3306         }
3307
3308         /*
3309          * Save off the requested flow control mode for use later.  Depending
3310          * on the link partner's capabilities, we may or may not use this mode.
3311          */
3312         hw->fc.current_mode = hw->fc.requested_mode;
3313
3314         e_dbg("After fix-ups FlowControl is now = %x\n",
3315                 hw->fc.current_mode);
3316
3317         /* Continue to configure the copper link. */
3318         ret_val = e1000_setup_copper_link_ich8lan(hw);
3319         if (ret_val)
3320                 return ret_val;
3321
3322         ew32(FCTTV, hw->fc.pause_time);
3323         if ((hw->phy.type == e1000_phy_82578) ||
3324             (hw->phy.type == e1000_phy_82579) ||
3325             (hw->phy.type == e1000_phy_82577)) {
3326                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3327
3328                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3329                                    hw->fc.pause_time);
3330                 if (ret_val)
3331                         return ret_val;
3332         }
3333
3334         return e1000e_set_fc_watermarks(hw);
3335 }
3336
3337 /**
3338  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3339  *  @hw: pointer to the HW structure
3340  *
3341  *  Configures the kumeran interface to the PHY to wait the appropriate time
3342  *  when polling the PHY, then call the generic setup_copper_link to finish
3343  *  configuring the copper link.
3344  **/
3345 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3346 {
3347         u32 ctrl;
3348         s32 ret_val;
3349         u16 reg_data;
3350
3351         ctrl = er32(CTRL);
3352         ctrl |= E1000_CTRL_SLU;
3353         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3354         ew32(CTRL, ctrl);
3355
3356         /*
3357          * Set the mac to wait the maximum time between each iteration
3358          * and increase the max iterations when polling the phy;
3359          * this fixes erroneous timeouts at 10Mbps.
3360          */
3361         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3362         if (ret_val)
3363                 return ret_val;
3364         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3365                                        &reg_data);
3366         if (ret_val)
3367                 return ret_val;
3368         reg_data |= 0x3F;
3369         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3370                                         reg_data);
3371         if (ret_val)
3372                 return ret_val;
3373
3374         switch (hw->phy.type) {
3375         case e1000_phy_igp_3:
3376                 ret_val = e1000e_copper_link_setup_igp(hw);
3377                 if (ret_val)
3378                         return ret_val;
3379                 break;
3380         case e1000_phy_bm:
3381         case e1000_phy_82578:
3382                 ret_val = e1000e_copper_link_setup_m88(hw);
3383                 if (ret_val)
3384                         return ret_val;
3385                 break;
3386         case e1000_phy_82577:
3387         case e1000_phy_82579:
3388                 ret_val = e1000_copper_link_setup_82577(hw);
3389                 if (ret_val)
3390                         return ret_val;
3391                 break;
3392         case e1000_phy_ife:
3393                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3394                 if (ret_val)
3395                         return ret_val;
3396
3397                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3398
3399                 switch (hw->phy.mdix) {
3400                 case 1:
3401                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3402                         break;
3403                 case 2:
3404                         reg_data |= IFE_PMC_FORCE_MDIX;
3405                         break;
3406                 case 0:
3407                 default:
3408                         reg_data |= IFE_PMC_AUTO_MDIX;
3409                         break;
3410                 }
3411                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3412                 if (ret_val)
3413                         return ret_val;
3414                 break;
3415         default:
3416                 break;
3417         }
3418         return e1000e_setup_copper_link(hw);
3419 }
3420
3421 /**
3422  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3423  *  @hw: pointer to the HW structure
3424  *  @speed: pointer to store current link speed
3425  *  @duplex: pointer to store the current link duplex
3426  *
3427  *  Calls the generic get_speed_and_duplex to retrieve the current link
3428  *  information and then calls the Kumeran lock loss workaround for links at
3429  *  gigabit speeds.
3430  **/
3431 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3432                                           u16 *duplex)
3433 {
3434         s32 ret_val;
3435
3436         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3437         if (ret_val)
3438                 return ret_val;
3439
3440         if ((hw->mac.type == e1000_ich8lan) &&
3441             (hw->phy.type == e1000_phy_igp_3) &&
3442             (*speed == SPEED_1000)) {
3443                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3444         }
3445
3446         return ret_val;
3447 }
3448
3449 /**
3450  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3451  *  @hw: pointer to the HW structure
3452  *
3453  *  Work-around for 82566 Kumeran PCS lock loss:
3454  *  On link status change (i.e. PCI reset, speed change) and link is up and
3455  *  speed is gigabit-
3456  *    0) if workaround is optionally disabled do nothing
3457  *    1) wait 1ms for Kumeran link to come up
3458  *    2) check Kumeran Diagnostic register PCS lock loss bit
3459  *    3) if not set the link is locked (all is good), otherwise...
3460  *    4) reset the PHY
3461  *    5) repeat up to 10 times
3462  *  Note: this is only called for IGP3 copper when speed is 1gb.
3463  **/
3464 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3465 {
3466         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3467         u32 phy_ctrl;
3468         s32 ret_val;
3469         u16 i, data;
3470         bool link;
3471
3472         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3473                 return 0;
3474
3475         /*
3476          * Make sure link is up before proceeding.  If not just return.
3477          * Attempting this while link is negotiating fouled up link
3478          * stability
3479          */
3480         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3481         if (!link)
3482                 return 0;
3483
3484         for (i = 0; i < 10; i++) {
3485                 /* read once to clear */
3486                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3487                 if (ret_val)
3488                         return ret_val;
3489                 /* and again to get new status */
3490                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3491                 if (ret_val)
3492                         return ret_val;
3493
3494                 /* check for PCS lock */
3495                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3496                         return 0;
3497
3498                 /* Issue PHY reset */
3499                 e1000_phy_hw_reset(hw);
3500                 mdelay(5);
3501         }
3502         /* Disable GigE link negotiation */
3503         phy_ctrl = er32(PHY_CTRL);
3504         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3505                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3506         ew32(PHY_CTRL, phy_ctrl);
3507
3508         /*
3509          * Call gig speed drop workaround on Gig disable before accessing
3510          * any PHY registers
3511          */
3512         e1000e_gig_downshift_workaround_ich8lan(hw);
3513
3514         /* unable to acquire PCS lock */
3515         return -E1000_ERR_PHY;
3516 }
3517
3518 /**
3519  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3520  *  @hw: pointer to the HW structure
3521  *  @state: boolean value used to set the current Kumeran workaround state
3522  *
3523  *  If ICH8, set the current Kumeran workaround state (enabled - true
3524  *  /disabled - false).
3525  **/
3526 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3527                                                  bool state)
3528 {
3529         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3530
3531         if (hw->mac.type != e1000_ich8lan) {
3532                 e_dbg("Workaround applies to ICH8 only.\n");
3533                 return;
3534         }
3535
3536         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3537 }
3538
3539 /**
3540  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3541  *  @hw: pointer to the HW structure
3542  *
3543  *  Workaround for 82566 power-down on D3 entry:
3544  *    1) disable gigabit link
3545  *    2) write VR power-down enable
3546  *    3) read it back
3547  *  Continue if successful, else issue LCD reset and repeat
3548  **/
3549 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3550 {
3551         u32 reg;
3552         u16 data;
3553         u8  retry = 0;
3554
3555         if (hw->phy.type != e1000_phy_igp_3)
3556                 return;
3557
3558         /* Try the workaround twice (if needed) */
3559         do {
3560                 /* Disable link */
3561                 reg = er32(PHY_CTRL);
3562                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3563                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3564                 ew32(PHY_CTRL, reg);
3565
3566                 /*
3567                  * Call gig speed drop workaround on Gig disable before
3568                  * accessing any PHY registers
3569                  */
3570                 if (hw->mac.type == e1000_ich8lan)
3571                         e1000e_gig_downshift_workaround_ich8lan(hw);
3572
3573                 /* Write VR power-down enable */
3574                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3575                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3576                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3577
3578                 /* Read it back and test */
3579                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3580                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3581                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3582                         break;
3583
3584                 /* Issue PHY reset and repeat at most one more time */
3585                 reg = er32(CTRL);
3586                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3587                 retry++;
3588         } while (retry);
3589 }
3590
3591 /**
3592  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3593  *  @hw: pointer to the HW structure
3594  *
3595  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3596  *  LPLU, Gig disable, MDIC PHY reset):
3597  *    1) Set Kumeran Near-end loopback
3598  *    2) Clear Kumeran Near-end loopback
3599  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3600  **/
3601 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3602 {
3603         s32 ret_val;
3604         u16 reg_data;
3605
3606         if ((hw->mac.type != e1000_ich8lan) ||
3607             (hw->phy.type != e1000_phy_igp_3))
3608                 return;
3609
3610         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3611                                       &reg_data);
3612         if (ret_val)
3613                 return;
3614         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3615         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3616                                        reg_data);
3617         if (ret_val)
3618                 return;
3619         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3620         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3621                                        reg_data);
3622 }
3623
3624 /**
3625  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3626  *  @hw: pointer to the HW structure
3627  *
3628  *  During S0 to Sx transition, it is possible the link remains at gig
3629  *  instead of negotiating to a lower speed.  Before going to Sx, set
3630  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3631  *  to a lower speed.  For PCH and newer parts, the OEM bits PHY register
3632  *  (LED, GbE disable and LPLU configurations) also needs to be written.
3633  **/
3634 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3635 {
3636         u32 phy_ctrl;
3637         s32 ret_val;
3638
3639         phy_ctrl = er32(PHY_CTRL);
3640         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3641         ew32(PHY_CTRL, phy_ctrl);
3642
3643         if (hw->mac.type >= e1000_pchlan) {
3644                 e1000_oem_bits_config_ich8lan(hw, false);
3645                 ret_val = hw->phy.ops.acquire(hw);
3646                 if (ret_val)
3647                         return;
3648                 e1000_write_smbus_addr(hw);
3649                 hw->phy.ops.release(hw);
3650         }
3651 }
3652
3653 /**
3654  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3655  *  @hw: pointer to the HW structure
3656  *
3657  *  During Sx to S0 transitions on non-managed devices or managed devices
3658  *  on which PHY resets are not blocked, if the PHY registers cannot be
3659  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
3660  *  the PHY.
3661  **/
3662 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3663 {
3664         u32 fwsm;
3665
3666         if (hw->mac.type != e1000_pch2lan)
3667                 return;
3668
3669         fwsm = er32(FWSM);
3670         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) || !e1000_check_reset_block(hw)) {
3671                 u16 phy_id1, phy_id2;
3672                 s32 ret_val;
3673
3674                 ret_val = hw->phy.ops.acquire(hw);
3675                 if (ret_val) {
3676                         e_dbg("Failed to acquire PHY semaphore in resume\n");
3677                         return;
3678                 }
3679
3680                 /* Test access to the PHY registers by reading the ID regs */
3681                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3682                 if (ret_val)
3683                         goto release;
3684                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3685                 if (ret_val)
3686                         goto release;
3687
3688                 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3689                                    (u32)(phy_id2 & PHY_REVISION_MASK)))
3690                         goto release;
3691
3692                 e1000_toggle_lanphypc_value_ich8lan(hw);
3693
3694                 hw->phy.ops.release(hw);
3695                 msleep(50);
3696                 e1000_phy_hw_reset(hw);
3697                 msleep(50);
3698                 return;
3699         }
3700
3701 release:
3702         hw->phy.ops.release(hw);
3703
3704         return;
3705 }
3706
3707 /**
3708  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3709  *  @hw: pointer to the HW structure
3710  *
3711  *  Return the LED back to the default configuration.
3712  **/
3713 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3714 {
3715         if (hw->phy.type == e1000_phy_ife)
3716                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3717
3718         ew32(LEDCTL, hw->mac.ledctl_default);
3719         return 0;
3720 }
3721
3722 /**
3723  *  e1000_led_on_ich8lan - Turn LEDs on
3724  *  @hw: pointer to the HW structure
3725  *
3726  *  Turn on the LEDs.
3727  **/
3728 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3729 {
3730         if (hw->phy.type == e1000_phy_ife)
3731                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3732                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3733
3734         ew32(LEDCTL, hw->mac.ledctl_mode2);
3735         return 0;
3736 }
3737
3738 /**
3739  *  e1000_led_off_ich8lan - Turn LEDs off
3740  *  @hw: pointer to the HW structure
3741  *
3742  *  Turn off the LEDs.
3743  **/
3744 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3745 {
3746         if (hw->phy.type == e1000_phy_ife)
3747                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3748                                 (IFE_PSCL_PROBE_MODE |
3749                                  IFE_PSCL_PROBE_LEDS_OFF));
3750
3751         ew32(LEDCTL, hw->mac.ledctl_mode1);
3752         return 0;
3753 }
3754
3755 /**
3756  *  e1000_setup_led_pchlan - Configures SW controllable LED
3757  *  @hw: pointer to the HW structure
3758  *
3759  *  This prepares the SW controllable LED for use.
3760  **/
3761 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3762 {
3763         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3764 }
3765
3766 /**
3767  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3768  *  @hw: pointer to the HW structure
3769  *
3770  *  Return the LED back to the default configuration.
3771  **/
3772 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3773 {
3774         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3775 }
3776
3777 /**
3778  *  e1000_led_on_pchlan - Turn LEDs on
3779  *  @hw: pointer to the HW structure
3780  *
3781  *  Turn on the LEDs.
3782  **/
3783 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3784 {
3785         u16 data = (u16)hw->mac.ledctl_mode2;
3786         u32 i, led;
3787
3788         /*
3789          * If no link, then turn LED on by setting the invert bit
3790          * for each LED that's mode is "link_up" in ledctl_mode2.
3791          */
3792         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3793                 for (i = 0; i < 3; i++) {
3794                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3795                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3796                             E1000_LEDCTL_MODE_LINK_UP)
3797                                 continue;
3798                         if (led & E1000_PHY_LED0_IVRT)
3799                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3800                         else
3801                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3802                 }
3803         }
3804
3805         return e1e_wphy(hw, HV_LED_CONFIG, data);
3806 }
3807
3808 /**
3809  *  e1000_led_off_pchlan - Turn LEDs off
3810  *  @hw: pointer to the HW structure
3811  *
3812  *  Turn off the LEDs.
3813  **/
3814 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3815 {
3816         u16 data = (u16)hw->mac.ledctl_mode1;
3817         u32 i, led;
3818
3819         /*
3820          * If no link, then turn LED off by clearing the invert bit
3821          * for each LED that's mode is "link_up" in ledctl_mode1.
3822          */
3823         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3824                 for (i = 0; i < 3; i++) {
3825                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3826                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3827                             E1000_LEDCTL_MODE_LINK_UP)
3828                                 continue;
3829                         if (led & E1000_PHY_LED0_IVRT)
3830                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3831                         else
3832                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3833                 }
3834         }
3835
3836         return e1e_wphy(hw, HV_LED_CONFIG, data);
3837 }
3838
3839 /**
3840  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3841  *  @hw: pointer to the HW structure
3842  *
3843  *  Read appropriate register for the config done bit for completion status
3844  *  and configure the PHY through s/w for EEPROM-less parts.
3845  *
3846  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3847  *  config done bit, so only an error is logged and continues.  If we were
3848  *  to return with error, EEPROM-less silicon would not be able to be reset
3849  *  or change link.
3850  **/
3851 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3852 {
3853         s32 ret_val = 0;
3854         u32 bank = 0;
3855         u32 status;
3856
3857         e1000e_get_cfg_done(hw);
3858
3859         /* Wait for indication from h/w that it has completed basic config */
3860         if (hw->mac.type >= e1000_ich10lan) {
3861                 e1000_lan_init_done_ich8lan(hw);
3862         } else {
3863                 ret_val = e1000e_get_auto_rd_done(hw);
3864                 if (ret_val) {
3865                         /*
3866                          * When auto config read does not complete, do not
3867                          * return with an error. This can happen in situations
3868                          * where there is no eeprom and prevents getting link.
3869                          */
3870                         e_dbg("Auto Read Done did not complete\n");
3871                         ret_val = 0;
3872                 }
3873         }
3874
3875         /* Clear PHY Reset Asserted bit */
3876         status = er32(STATUS);
3877         if (status & E1000_STATUS_PHYRA)
3878                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3879         else
3880                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3881
3882         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3883         if (hw->mac.type <= e1000_ich9lan) {
3884                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3885                     (hw->phy.type == e1000_phy_igp_3)) {
3886                         e1000e_phy_init_script_igp3(hw);
3887                 }
3888         } else {
3889                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3890                         /* Maybe we should do a basic PHY config */
3891                         e_dbg("EEPROM not present\n");
3892                         ret_val = -E1000_ERR_CONFIG;
3893                 }
3894         }
3895
3896         return ret_val;
3897 }
3898
3899 /**
3900  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3901  * @hw: pointer to the HW structure
3902  *
3903  * In the case of a PHY power down to save power, or to turn off link during a
3904  * driver unload, or wake on lan is not enabled, remove the link.
3905  **/
3906 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3907 {
3908         /* If the management interface is not enabled, then power down */
3909         if (!(hw->mac.ops.check_mng_mode(hw) ||
3910               hw->phy.ops.check_reset_block(hw)))
3911                 e1000_power_down_phy_copper(hw);
3912 }
3913
3914 /**
3915  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3916  *  @hw: pointer to the HW structure
3917  *
3918  *  Clears hardware counters specific to the silicon family and calls
3919  *  clear_hw_cntrs_generic to clear all general purpose counters.
3920  **/
3921 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3922 {
3923         u16 phy_data;
3924         s32 ret_val;
3925
3926         e1000e_clear_hw_cntrs_base(hw);
3927
3928         er32(ALGNERRC);
3929         er32(RXERRC);
3930         er32(TNCRS);
3931         er32(CEXTERR);
3932         er32(TSCTC);
3933         er32(TSCTFC);
3934
3935         er32(MGTPRC);
3936         er32(MGTPDC);
3937         er32(MGTPTC);
3938
3939         er32(IAC);
3940         er32(ICRXOC);
3941
3942         /* Clear PHY statistics registers */
3943         if ((hw->phy.type == e1000_phy_82578) ||
3944             (hw->phy.type == e1000_phy_82579) ||
3945             (hw->phy.type == e1000_phy_82577)) {
3946                 ret_val = hw->phy.ops.acquire(hw);
3947                 if (ret_val)
3948                         return;
3949                 ret_val = hw->phy.ops.set_page(hw,
3950                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
3951                 if (ret_val)
3952                         goto release;
3953                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
3954                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
3955                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
3956                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
3957                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
3958                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
3959                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
3960                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
3961                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
3962                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
3963                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
3964                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
3965                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
3966                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
3967 release:
3968                 hw->phy.ops.release(hw);
3969         }
3970 }
3971
3972 static struct e1000_mac_operations ich8_mac_ops = {
3973         .id_led_init            = e1000e_id_led_init,
3974         /* check_mng_mode dependent on mac type */
3975         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3976         /* cleanup_led dependent on mac type */
3977         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3978         .get_bus_info           = e1000_get_bus_info_ich8lan,
3979         .set_lan_id             = e1000_set_lan_id_single_port,
3980         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3981         /* led_on dependent on mac type */
3982         /* led_off dependent on mac type */
3983         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3984         .reset_hw               = e1000_reset_hw_ich8lan,
3985         .init_hw                = e1000_init_hw_ich8lan,
3986         .setup_link             = e1000_setup_link_ich8lan,
3987         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3988         /* id_led_init dependent on mac type */
3989 };
3990
3991 static struct e1000_phy_operations ich8_phy_ops = {
3992         .acquire                = e1000_acquire_swflag_ich8lan,
3993         .check_reset_block      = e1000_check_reset_block_ich8lan,
3994         .commit                 = NULL,
3995         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3996         .get_cable_length       = e1000e_get_cable_length_igp_2,
3997         .read_reg               = e1000e_read_phy_reg_igp,
3998         .release                = e1000_release_swflag_ich8lan,
3999         .reset                  = e1000_phy_hw_reset_ich8lan,
4000         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4001         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4002         .write_reg              = e1000e_write_phy_reg_igp,
4003 };
4004
4005 static struct e1000_nvm_operations ich8_nvm_ops = {
4006         .acquire                = e1000_acquire_nvm_ich8lan,
4007         .read                   = e1000_read_nvm_ich8lan,
4008         .release                = e1000_release_nvm_ich8lan,
4009         .update                 = e1000_update_nvm_checksum_ich8lan,
4010         .valid_led_default      = e1000_valid_led_default_ich8lan,
4011         .validate               = e1000_validate_nvm_checksum_ich8lan,
4012         .write                  = e1000_write_nvm_ich8lan,
4013 };
4014
4015 struct e1000_info e1000_ich8_info = {
4016         .mac                    = e1000_ich8lan,
4017         .flags                  = FLAG_HAS_WOL
4018                                   | FLAG_IS_ICH
4019                                   | FLAG_RX_CSUM_ENABLED
4020                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4021                                   | FLAG_HAS_AMT
4022                                   | FLAG_HAS_FLASH
4023                                   | FLAG_APME_IN_WUC,
4024         .pba                    = 8,
4025         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4026         .get_variants           = e1000_get_variants_ich8lan,
4027         .mac_ops                = &ich8_mac_ops,
4028         .phy_ops                = &ich8_phy_ops,
4029         .nvm_ops                = &ich8_nvm_ops,
4030 };
4031
4032 struct e1000_info e1000_ich9_info = {
4033         .mac                    = e1000_ich9lan,
4034         .flags                  = FLAG_HAS_JUMBO_FRAMES
4035                                   | FLAG_IS_ICH
4036                                   | FLAG_HAS_WOL
4037                                   | FLAG_RX_CSUM_ENABLED
4038                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4039                                   | FLAG_HAS_AMT
4040                                   | FLAG_HAS_ERT
4041                                   | FLAG_HAS_FLASH
4042                                   | FLAG_APME_IN_WUC,
4043         .pba                    = 10,
4044         .max_hw_frame_size      = DEFAULT_JUMBO,
4045         .get_variants           = e1000_get_variants_ich8lan,
4046         .mac_ops                = &ich8_mac_ops,
4047         .phy_ops                = &ich8_phy_ops,
4048         .nvm_ops                = &ich8_nvm_ops,
4049 };
4050
4051 struct e1000_info e1000_ich10_info = {
4052         .mac                    = e1000_ich10lan,
4053         .flags                  = FLAG_HAS_JUMBO_FRAMES
4054                                   | FLAG_IS_ICH
4055                                   | FLAG_HAS_WOL
4056                                   | FLAG_RX_CSUM_ENABLED
4057                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4058                                   | FLAG_HAS_AMT
4059                                   | FLAG_HAS_ERT
4060                                   | FLAG_HAS_FLASH
4061                                   | FLAG_APME_IN_WUC,
4062         .pba                    = 10,
4063         .max_hw_frame_size      = DEFAULT_JUMBO,
4064         .get_variants           = e1000_get_variants_ich8lan,
4065         .mac_ops                = &ich8_mac_ops,
4066         .phy_ops                = &ich8_phy_ops,
4067         .nvm_ops                = &ich8_nvm_ops,
4068 };
4069
4070 struct e1000_info e1000_pch_info = {
4071         .mac                    = e1000_pchlan,
4072         .flags                  = FLAG_IS_ICH
4073                                   | FLAG_HAS_WOL
4074                                   | FLAG_RX_CSUM_ENABLED
4075                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4076                                   | FLAG_HAS_AMT
4077                                   | FLAG_HAS_FLASH
4078                                   | FLAG_HAS_JUMBO_FRAMES
4079                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4080                                   | FLAG_APME_IN_WUC,
4081         .flags2                 = FLAG2_HAS_PHY_STATS,
4082         .pba                    = 26,
4083         .max_hw_frame_size      = 4096,
4084         .get_variants           = e1000_get_variants_ich8lan,
4085         .mac_ops                = &ich8_mac_ops,
4086         .phy_ops                = &ich8_phy_ops,
4087         .nvm_ops                = &ich8_nvm_ops,
4088 };
4089
4090 struct e1000_info e1000_pch2_info = {
4091         .mac                    = e1000_pch2lan,
4092         .flags                  = FLAG_IS_ICH
4093                                   | FLAG_HAS_WOL
4094                                   | FLAG_RX_CSUM_ENABLED
4095                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4096                                   | FLAG_HAS_AMT
4097                                   | FLAG_HAS_FLASH
4098                                   | FLAG_HAS_JUMBO_FRAMES
4099                                   | FLAG_APME_IN_WUC,
4100         .flags2                 = FLAG2_HAS_PHY_STATS
4101                                   | FLAG2_HAS_EEE,
4102         .pba                    = 26,
4103         .max_hw_frame_size      = DEFAULT_JUMBO,
4104         .get_variants           = e1000_get_variants_ich8lan,
4105         .mac_ops                = &ich8_mac_ops,
4106         .phy_ops                = &ich8_phy_ops,
4107         .nvm_ops                = &ich8_nvm_ops,
4108 };