drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                 PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK     0x6000
 142
 143 /* Strapping Option Register - RO */
 144 #define E1000_STRAP                     0x0000C
 145 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 146 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 147
 148 /* OEM Bits Phy Register */
 149 #define HV_OEM_BITS            PHY_REG(768, 25)
 150 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 151 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 152 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 153
 154 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 155 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 156
 157 /* KMRN Mode Control */
 158 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 159 #define HV_KMRN_MDIO_SLOW      0x0400
 160
 161 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 162 /* Offset 04h HSFSTS */
 163 union ich8_hws_flash_status {
 164         struct ich8_hsfsts {
 165                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 166                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 167                 u16 dael       :1; /* bit 2 Direct Access error Log */
 168                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 169                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 170                 u16 reserved1  :2; /* bit 13:6 Reserved */
 171                 u16 reserved2  :6; /* bit 13:6 Reserved */
 172                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 173                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 174         } hsf_status;
 175         u16 regval;
 176 };
 177
 178 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 179 /* Offset 06h FLCTL */
 180 union ich8_hws_flash_ctrl {
 181         struct ich8_hsflctl {
 182                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 183                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 184                 u16 reserved   :5;   /* 7:3 Reserved  */
 185                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 186                 u16 flockdn    :6;   /* 15:10 Reserved */
 187         } hsf_ctrl;
 188         u16 regval;
 189 };
 190
 191 /* ICH Flash Region Access Permissions */
 192 union ich8_hws_flash_regacc {
 193         struct ich8_flracc {
 194                 u32 grra      :8; /* 0:7 GbE region Read Access */
 195                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 196                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 197                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 198         } hsf_flregacc;
 199         u16 regval;
 200 };
 201
 202 /* ICH Flash Protected Region */
 203 union ich8_flash_protected_range {
 204         struct ich8_pr {
 205                 u32 base:13;     /* 0:12 Protected Range Base */
 206                 u32 reserved1:2; /* 13:14 Reserved */
 207                 u32 rpe:1;       /* 15 Read Protection Enable */
 208                 u32 limit:13;    /* 16:28 Protected Range Limit */
 209                 u32 reserved2:2; /* 29:30 Reserved */
 210                 u32 wpe:1;       /* 31 Write Protection Enable */
 211         } range;
 212         u32 regval;
 213 };
 214
 215 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 216 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 217 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 218 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 219 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 220                                                 u32 offset, u8 byte);
 221 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 222                                          u8 *data);
 223 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 224                                          u16 *data);
 225 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 226                                          u8 size, u16 *data);
 227 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 228 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 229 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 230 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 231 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 232 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 233 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 234 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 235 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 236 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 237 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 238 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 239 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 240 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 241 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 242 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 243 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 244 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 245 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 246 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 247
 248 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 249 {
 250         return readw(hw->flash_address + reg);
 251 }
 252
 253 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 254 {
 255         return readl(hw->flash_address + reg);
 256 }
 257
 258 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 259 {
 260         writew(val, hw->flash_address + reg);
 261 }
 262
 263 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 264 {
 265         writel(val, hw->flash_address + reg);
 266 }
 267
 268 #define er16flash(reg)          __er16flash(hw, (reg))
 269 #define er32flash(reg)          __er32flash(hw, (reg))
 270 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 271 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 272
 273 /**
 274  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 275  *  @hw: pointer to the HW structure
 276  *
 277  *  Initialize family-specific PHY parameters and function pointers.
 278  **/
 279 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 280 {
 281         struct e1000_phy_info *phy = &hw->phy;
 282         u32 ctrl, fwsm;
 283         s32 ret_val = 0;
 284
 285         phy->addr                     = 1;
 286         phy->reset_delay_us           = 100;
 287
 288         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 289         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 290         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 291         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 292         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 293         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 294         phy->ops.power_up             = e1000_power_up_phy_copper;
 295         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 296         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 297
 298         /*
 299          * The MAC-PHY interconnect may still be in SMBus mode
 300          * after Sx->S0.  If the manageability engine (ME) is
 301          * disabled, then toggle the LANPHYPC Value bit to force
 302          * the interconnect to PCIe mode.
 303          */
 304         fwsm = er32(FWSM);
 305         if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 306                 ctrl = er32(CTRL);
 307                 ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
 308                 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 309                 ew32(CTRL, ctrl);
 310                 udelay(10);
 311                 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 312                 ew32(CTRL, ctrl);
 313                 msleep(50);
 314
 315                 /*
 316                  * Gate automatic PHY configuration by hardware on
 317                  * non-managed 82579
 318                  */
 319                 if (hw->mac.type == e1000_pch2lan)
 320                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 321         }
 322
 323         /*
 324          * Reset the PHY before any acccess to it.  Doing so, ensures that
 325          * the PHY is in a known good state before we read/write PHY registers.
 326          * The generic reset is sufficient here, because we haven't determined
 327          * the PHY type yet.
 328          */
 329         ret_val = e1000e_phy_hw_reset_generic(hw);
 330         if (ret_val)
 331                 goto out;
 332
 333         /* Ungate automatic PHY configuration on non-managed 82579 */
 334         if ((hw->mac.type == e1000_pch2lan)  &&
 335             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 336                 msleep(10);
 337                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 338         }
 339
 340         phy->id = e1000_phy_unknown;
 341         ret_val = e1000e_get_phy_id(hw);
 342         if (ret_val)
 343                 goto out;
 344         if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
 345                 /*
 346                  * In case the PHY needs to be in mdio slow mode (eg. 82577),
 347                  * set slow mode and try to get the PHY id again.
 348                  */
 349                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 350                 if (ret_val)
 351                         goto out;
 352                 ret_val = e1000e_get_phy_id(hw);
 353                 if (ret_val)
 354                         goto out;
 355         }
 356         phy->type = e1000e_get_phy_type_from_id(phy->id);
 357
 358         switch (phy->type) {
 359         case e1000_phy_82577:
 360         case e1000_phy_82579:
 361                 phy->ops.check_polarity = e1000_check_polarity_82577;
 362                 phy->ops.force_speed_duplex =
 363                         e1000_phy_force_speed_duplex_82577;
 364                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 365                 phy->ops.get_info = e1000_get_phy_info_82577;
 366                 phy->ops.commit = e1000e_phy_sw_reset;
 367                 break;
 368         case e1000_phy_82578:
 369                 phy->ops.check_polarity = e1000_check_polarity_m88;
 370                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 371                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 372                 phy->ops.get_info = e1000e_get_phy_info_m88;
 373                 break;
 374         default:
 375                 ret_val = -E1000_ERR_PHY;
 376                 break;
 377         }
 378
 379 out:
 380         return ret_val;
 381 }
 382
 383 /**
 384  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 385  *  @hw: pointer to the HW structure
 386  *
 387  *  Initialize family-specific PHY parameters and function pointers.
 388  **/
 389 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 390 {
 391         struct e1000_phy_info *phy = &hw->phy;
 392         s32 ret_val;
 393         u16 i = 0;
 394
 395         phy->addr                       = 1;
 396         phy->reset_delay_us             = 100;
 397
 398         phy->ops.power_up               = e1000_power_up_phy_copper;
 399         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 400
 401         /*
 402          * We may need to do this twice - once for IGP and if that fails,
 403          * we'll set BM func pointers and try again
 404          */
 405         ret_val = e1000e_determine_phy_address(hw);
 406         if (ret_val) {
 407                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 408                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 409                 ret_val = e1000e_determine_phy_address(hw);
 410                 if (ret_val) {
 411                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 412                         return ret_val;
 413                 }
 414         }
 415
 416         phy->id = 0;
 417         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 418                (i++ < 100)) {
 419                 msleep(1);
 420                 ret_val = e1000e_get_phy_id(hw);
 421                 if (ret_val)
 422                         return ret_val;
 423         }
 424
 425         /* Verify phy id */
 426         switch (phy->id) {
 427         case IGP03E1000_E_PHY_ID:
 428                 phy->type = e1000_phy_igp_3;
 429                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 430                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 431                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 432                 phy->ops.get_info = e1000e_get_phy_info_igp;
 433                 phy->ops.check_polarity = e1000_check_polarity_igp;
 434                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 435                 break;
 436         case IFE_E_PHY_ID:
 437         case IFE_PLUS_E_PHY_ID:
 438         case IFE_C_E_PHY_ID:
 439                 phy->type = e1000_phy_ife;
 440                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 441                 phy->ops.get_info = e1000_get_phy_info_ife;
 442                 phy->ops.check_polarity = e1000_check_polarity_ife;
 443                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 444                 break;
 445         case BME1000_E_PHY_ID:
 446                 phy->type = e1000_phy_bm;
 447                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 448                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 449                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 450                 phy->ops.commit = e1000e_phy_sw_reset;
 451                 phy->ops.get_info = e1000e_get_phy_info_m88;
 452                 phy->ops.check_polarity = e1000_check_polarity_m88;
 453                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 454                 break;
 455         default:
 456                 return -E1000_ERR_PHY;
 457                 break;
 458         }
 459
 460         return 0;
 461 }
 462
 463 /**
 464  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 465  *  @hw: pointer to the HW structure
 466  *
 467  *  Initialize family-specific NVM parameters and function
 468  *  pointers.
 469  **/
 470 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 471 {
 472         struct e1000_nvm_info *nvm = &hw->nvm;
 473         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 474         u32 gfpreg, sector_base_addr, sector_end_addr;
 475         u16 i;
 476
 477         /* Can't read flash registers if the register set isn't mapped. */
 478         if (!hw->flash_address) {
 479                 e_dbg("ERROR: Flash registers not mapped\n");
 480                 return -E1000_ERR_CONFIG;
 481         }
 482
 483         nvm->type = e1000_nvm_flash_sw;
 484
 485         gfpreg = er32flash(ICH_FLASH_GFPREG);
 486
 487         /*
 488          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 489          * Add 1 to sector_end_addr since this sector is included in
 490          * the overall size.
 491          */
 492         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 493         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 494
 495         /* flash_base_addr is byte-aligned */
 496         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 497
 498         /*
 499          * find total size of the NVM, then cut in half since the total
 500          * size represents two separate NVM banks.
 501          */
 502         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 503                                 << FLASH_SECTOR_ADDR_SHIFT;
 504         nvm->flash_bank_size /= 2;
 505         /* Adjust to word count */
 506         nvm->flash_bank_size /= sizeof(u16);
 507
 508         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 509
 510         /* Clear shadow ram */
 511         for (i = 0; i < nvm->word_size; i++) {
 512                 dev_spec->shadow_ram[i].modified = false;
 513                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 514         }
 515
 516         return 0;
 517 }
 518
 519 /**
 520  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 521  *  @hw: pointer to the HW structure
 522  *
 523  *  Initialize family-specific MAC parameters and function
 524  *  pointers.
 525  **/
 526 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 527 {
 528         struct e1000_hw *hw = &adapter->hw;
 529         struct e1000_mac_info *mac = &hw->mac;
 530
 531         /* Set media type function pointer */
 532         hw->phy.media_type = e1000_media_type_copper;
 533
 534         /* Set mta register count */
 535         mac->mta_reg_count = 32;
 536         /* Set rar entry count */
 537         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 538         if (mac->type == e1000_ich8lan)
 539                 mac->rar_entry_count--;
 540         /* FWSM register */
 541         mac->has_fwsm = true;
 542         /* ARC subsystem not supported */
 543         mac->arc_subsystem_valid = false;
 544         /* Adaptive IFS supported */
 545         mac->adaptive_ifs = true;
 546
 547         /* LED operations */
 548         switch (mac->type) {
 549         case e1000_ich8lan:
 550         case e1000_ich9lan:
 551         case e1000_ich10lan:
 552                 /* check management mode */
 553                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 554                 /* ID LED init */
 555                 mac->ops.id_led_init = e1000e_id_led_init;
 556                 /* setup LED */
 557                 mac->ops.setup_led = e1000e_setup_led_generic;
 558                 /* cleanup LED */
 559                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 560                 /* turn on/off LED */
 561                 mac->ops.led_on = e1000_led_on_ich8lan;
 562                 mac->ops.led_off = e1000_led_off_ich8lan;
 563                 break;
 564         case e1000_pchlan:
 565         case e1000_pch2lan:
 566                 /* check management mode */
 567                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 568                 /* ID LED init */
 569                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 570                 /* setup LED */
 571                 mac->ops.setup_led = e1000_setup_led_pchlan;
 572                 /* cleanup LED */
 573                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 574                 /* turn on/off LED */
 575                 mac->ops.led_on = e1000_led_on_pchlan;
 576                 mac->ops.led_off = e1000_led_off_pchlan;
 577                 break;
 578         default:
 579                 break;
 580         }
 581
 582         /* Enable PCS Lock-loss workaround for ICH8 */
 583         if (mac->type == e1000_ich8lan)
 584                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 585
 586         /* Gate automatic PHY configuration by hardware on managed 82579 */
 587         if ((mac->type == e1000_pch2lan) &&
 588             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 589                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 590
 591         return 0;
 592 }
 593
 594 /**
 595  *  e1000_set_eee_pchlan - Enable/disable EEE support
 596  *  @hw: pointer to the HW structure
 597  *
 598  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 599  *  the LPI Control register will remain set only if/when link is up.
 600  **/
 601 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 602 {
 603         s32 ret_val = 0;
 604         u16 phy_reg;
 605
 606         if (hw->phy.type != e1000_phy_82579)
 607                 goto out;
 608
 609         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 610         if (ret_val)
 611                 goto out;
 612
 613         if (hw->dev_spec.ich8lan.eee_disable)
 614                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 615         else
 616                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 617
 618         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 619 out:
 620         return ret_val;
 621 }
 622
 623 /**
 624  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 625  *  @hw: pointer to the HW structure
 626  *
 627  *  Checks to see of the link status of the hardware has changed.  If a
 628  *  change in link status has been detected, then we read the PHY registers
 629  *  to get the current speed/duplex if link exists.
 630  **/
 631 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 632 {
 633         struct e1000_mac_info *mac = &hw->mac;
 634         s32 ret_val;
 635         bool link;
 636
 637         /*
 638          * We only want to go out to the PHY registers to see if Auto-Neg
 639          * has completed and/or if our link status has changed.  The
 640          * get_link_status flag is set upon receiving a Link Status
 641          * Change or Rx Sequence Error interrupt.
 642          */
 643         if (!mac->get_link_status) {
 644                 ret_val = 0;
 645                 goto out;
 646         }
 647
 648         /*
 649          * First we want to see if the MII Status Register reports
 650          * link.  If so, then we want to get the current speed/duplex
 651          * of the PHY.
 652          */
 653         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 654         if (ret_val)
 655                 goto out;
 656
 657         if (hw->mac.type == e1000_pchlan) {
 658                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 659                 if (ret_val)
 660                         goto out;
 661         }
 662
 663         if (!link)
 664                 goto out; /* No link detected */
 665
 666         mac->get_link_status = false;
 667
 668         if (hw->phy.type == e1000_phy_82578) {
 669                 ret_val = e1000_link_stall_workaround_hv(hw);
 670                 if (ret_val)
 671                         goto out;
 672         }
 673
 674         if (hw->mac.type == e1000_pch2lan) {
 675                 ret_val = e1000_k1_workaround_lv(hw);
 676                 if (ret_val)
 677                         goto out;
 678         }
 679
 680         /*
 681          * Check if there was DownShift, must be checked
 682          * immediately after link-up
 683          */
 684         e1000e_check_downshift(hw);
 685
 686         /* Enable/Disable EEE after link up */
 687         ret_val = e1000_set_eee_pchlan(hw);
 688         if (ret_val)
 689                 goto out;
 690
 691         /*
 692          * If we are forcing speed/duplex, then we simply return since
 693          * we have already determined whether we have link or not.
 694          */
 695         if (!mac->autoneg) {
 696                 ret_val = -E1000_ERR_CONFIG;
 697                 goto out;
 698         }
 699
 700         /*
 701          * Auto-Neg is enabled.  Auto Speed Detection takes care
 702          * of MAC speed/duplex configuration.  So we only need to
 703          * configure Collision Distance in the MAC.
 704          */
 705         e1000e_config_collision_dist(hw);
 706
 707         /*
 708          * Configure Flow Control now that Auto-Neg has completed.
 709          * First, we need to restore the desired flow control
 710          * settings because we may have had to re-autoneg with a
 711          * different link partner.
 712          */
 713         ret_val = e1000e_config_fc_after_link_up(hw);
 714         if (ret_val)
 715                 e_dbg("Error configuring flow control\n");
 716
 717 out:
 718         return ret_val;
 719 }
 720
 721 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 722 {
 723         struct e1000_hw *hw = &adapter->hw;
 724         s32 rc;
 725
 726         rc = e1000_init_mac_params_ich8lan(adapter);
 727         if (rc)
 728                 return rc;
 729
 730         rc = e1000_init_nvm_params_ich8lan(hw);
 731         if (rc)
 732                 return rc;
 733
 734         switch (hw->mac.type) {
 735         case e1000_ich8lan:
 736         case e1000_ich9lan:
 737         case e1000_ich10lan:
 738                 rc = e1000_init_phy_params_ich8lan(hw);
 739                 break;
 740         case e1000_pchlan:
 741         case e1000_pch2lan:
 742                 rc = e1000_init_phy_params_pchlan(hw);
 743                 break;
 744         default:
 745                 break;
 746         }
 747         if (rc)
 748                 return rc;
 749
 750         if (adapter->hw.phy.type == e1000_phy_ife) {
 751                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 752                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 753         }
 754
 755         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 756             (adapter->hw.phy.type == e1000_phy_igp_3))
 757                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 758
 759         /* Disable EEE by default until IEEE802.3az spec is finalized */
 760         if (adapter->flags2 & FLAG2_HAS_EEE)
 761                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 762
 763         return 0;
 764 }
 765
 766 static DEFINE_MUTEX(nvm_mutex);
 767
 768 /**
 769  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 770  *  @hw: pointer to the HW structure
 771  *
 772  *  Acquires the mutex for performing NVM operations.
 773  **/
 774 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 775 {
 776         mutex_lock(&nvm_mutex);
 777
 778         return 0;
 779 }
 780
 781 /**
 782  *  e1000_release_nvm_ich8lan - Release NVM mutex
 783  *  @hw: pointer to the HW structure
 784  *
 785  *  Releases the mutex used while performing NVM operations.
 786  **/
 787 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 788 {
 789         mutex_unlock(&nvm_mutex);
 790 }
 791
 792 static DEFINE_MUTEX(swflag_mutex);
 793
 794 /**
 795  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 796  *  @hw: pointer to the HW structure
 797  *
 798  *  Acquires the software control flag for performing PHY and select
 799  *  MAC CSR accesses.
 800  **/
 801 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 802 {
 803         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 804         s32 ret_val = 0;
 805
 806         mutex_lock(&swflag_mutex);
 807
 808         while (timeout) {
 809                 extcnf_ctrl = er32(EXTCNF_CTRL);
 810                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 811                         break;
 812
 813                 mdelay(1);
 814                 timeout--;
 815         }
 816
 817         if (!timeout) {
 818                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 819                 ret_val = -E1000_ERR_CONFIG;
 820                 goto out;
 821         }
 822
 823         timeout = SW_FLAG_TIMEOUT;
 824
 825         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 826         ew32(EXTCNF_CTRL, extcnf_ctrl);
 827
 828         while (timeout) {
 829                 extcnf_ctrl = er32(EXTCNF_CTRL);
 830                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 831                         break;
 832
 833                 mdelay(1);
 834                 timeout--;
 835         }
 836
 837         if (!timeout) {
 838                 e_dbg("Failed to acquire the semaphore.\n");
 839                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 840                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 841                 ret_val = -E1000_ERR_CONFIG;
 842                 goto out;
 843         }
 844
 845 out:
 846         if (ret_val)
 847                 mutex_unlock(&swflag_mutex);
 848
 849         return ret_val;
 850 }
 851
 852 /**
 853  *  e1000_release_swflag_ich8lan - Release software control flag
 854  *  @hw: pointer to the HW structure
 855  *
 856  *  Releases the software control flag for performing PHY and select
 857  *  MAC CSR accesses.
 858  **/
 859 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 860 {
 861         u32 extcnf_ctrl;
 862
 863         extcnf_ctrl = er32(EXTCNF_CTRL);
 864         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 865         ew32(EXTCNF_CTRL, extcnf_ctrl);
 866
 867         mutex_unlock(&swflag_mutex);
 868 }
 869
 870 /**
 871  *  e1000_check_mng_mode_ich8lan - Checks management mode
 872  *  @hw: pointer to the HW structure
 873  *
 874  *  This checks if the adapter has any manageability enabled.
 875  *  This is a function pointer entry point only called by read/write
 876  *  routines for the PHY and NVM parts.
 877  **/
 878 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 879 {
 880         u32 fwsm;
 881
 882         fwsm = er32(FWSM);
 883         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 884                ((fwsm & E1000_FWSM_MODE_MASK) ==
 885                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 886 }
 887
 888 /**
 889  *  e1000_check_mng_mode_pchlan - Checks management mode
 890  *  @hw: pointer to the HW structure
 891  *
 892  *  This checks if the adapter has iAMT enabled.
 893  *  This is a function pointer entry point only called by read/write
 894  *  routines for the PHY and NVM parts.
 895  **/
 896 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 897 {
 898         u32 fwsm;
 899
 900         fwsm = er32(FWSM);
 901         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 902                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 903 }
 904
 905 /**
 906  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 907  *  @hw: pointer to the HW structure
 908  *
 909  *  Checks if firmware is blocking the reset of the PHY.
 910  *  This is a function pointer entry point only called by
 911  *  reset routines.
 912  **/
 913 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 914 {
 915         u32 fwsm;
 916
 917         fwsm = er32(FWSM);
 918
 919         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 920 }
 921
 922 /**
 923  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 924  *  @hw: pointer to the HW structure
 925  *
 926  *  Assumes semaphore already acquired.
 927  *
 928  **/
 929 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
 930 {
 931         u16 phy_data;
 932         u32 strap = er32(STRAP);
 933         s32 ret_val = 0;
 934
 935         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 936
 937         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
 938         if (ret_val)
 939                 goto out;
 940
 941         phy_data &= ~HV_SMB_ADDR_MASK;
 942         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
 943         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 944         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
 945
 946 out:
 947         return ret_val;
 948 }
 949
 950 /**
 951  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 952  *  @hw:   pointer to the HW structure
 953  *
 954  *  SW should configure the LCD from the NVM extended configuration region
 955  *  as a workaround for certain parts.
 956  **/
 957 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 958 {
 959         struct e1000_phy_info *phy = &hw->phy;
 960         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 961         s32 ret_val = 0;
 962         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 963
 964         /*
 965          * Initialize the PHY from the NVM on ICH platforms.  This
 966          * is needed due to an issue where the NVM configuration is
 967          * not properly autoloaded after power transitions.
 968          * Therefore, after each PHY reset, we will load the
 969          * configuration data out of the NVM manually.
 970          */
 971         switch (hw->mac.type) {
 972         case e1000_ich8lan:
 973                 if (phy->type != e1000_phy_igp_3)
 974                         return ret_val;
 975
 976                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
 977                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
 978                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 979                         break;
 980                 }
 981                 /* Fall-thru */
 982         case e1000_pchlan:
 983         case e1000_pch2lan:
 984                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 985                 break;
 986         default:
 987                 return ret_val;
 988         }
 989
 990         ret_val = hw->phy.ops.acquire(hw);
 991         if (ret_val)
 992                 return ret_val;
 993
 994         data = er32(FEXTNVM);
 995         if (!(data & sw_cfg_mask))
 996                 goto out;
 997
 998         /*
 999          * Make sure HW does not configure LCD from PHY
1000          * extended configuration before SW configuration
1001          */
1002         data = er32(EXTCNF_CTRL);
1003         if (!(hw->mac.type == e1000_pch2lan)) {
1004                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1005                         goto out;
1006         }
1007
1008         cnf_size = er32(EXTCNF_SIZE);
1009         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1010         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1011         if (!cnf_size)
1012                 goto out;
1013
1014         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1015         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1016
1017         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1018             (hw->mac.type == e1000_pchlan)) ||
1019              (hw->mac.type == e1000_pch2lan)) {
1020                 /*
1021                  * HW configures the SMBus address and LEDs when the
1022                  * OEM and LCD Write Enable bits are set in the NVM.
1023                  * When both NVM bits are cleared, SW will configure
1024                  * them instead.
1025                  */
1026                 ret_val = e1000_write_smbus_addr(hw);
1027                 if (ret_val)
1028                         goto out;
1029
1030                 data = er32(LEDCTL);
1031                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1032                                                         (u16)data);
1033                 if (ret_val)
1034                         goto out;
1035         }
1036
1037         /* Configure LCD from extended configuration region. */
1038
1039         /* cnf_base_addr is in DWORD */
1040         word_addr = (u16)(cnf_base_addr << 1);
1041
1042         for (i = 0; i < cnf_size; i++) {
1043                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1044                                          &reg_data);
1045                 if (ret_val)
1046                         goto out;
1047
1048                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1049                                          1, &reg_addr);
1050                 if (ret_val)
1051                         goto out;
1052
1053                 /* Save off the PHY page for future writes. */
1054                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1055                         phy_page = reg_data;
1056                         continue;
1057                 }
1058
1059                 reg_addr &= PHY_REG_MASK;
1060                 reg_addr |= phy_page;
1061
1062                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1063                                                     reg_data);
1064                 if (ret_val)
1065                         goto out;
1066         }
1067
1068 out:
1069         hw->phy.ops.release(hw);
1070         return ret_val;
1071 }
1072
1073 /**
1074  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1075  *  @hw:   pointer to the HW structure
1076  *  @link: link up bool flag
1077  *
1078  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1079  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1080  *  If link is down, the function will restore the default K1 setting located
1081  *  in the NVM.
1082  **/
1083 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1084 {
1085         s32 ret_val = 0;
1086         u16 status_reg = 0;
1087         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1088
1089         if (hw->mac.type != e1000_pchlan)
1090                 goto out;
1091
1092         /* Wrap the whole flow with the sw flag */
1093         ret_val = hw->phy.ops.acquire(hw);
1094         if (ret_val)
1095                 goto out;
1096
1097         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1098         if (link) {
1099                 if (hw->phy.type == e1000_phy_82578) {
1100                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1101                                                                   &status_reg);
1102                         if (ret_val)
1103                                 goto release;
1104
1105                         status_reg &= BM_CS_STATUS_LINK_UP |
1106                                       BM_CS_STATUS_RESOLVED |
1107                                       BM_CS_STATUS_SPEED_MASK;
1108
1109                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1110                                            BM_CS_STATUS_RESOLVED |
1111                                            BM_CS_STATUS_SPEED_1000))
1112                                 k1_enable = false;
1113                 }
1114
1115                 if (hw->phy.type == e1000_phy_82577) {
1116                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1117                                                                   &status_reg);
1118                         if (ret_val)
1119                                 goto release;
1120
1121                         status_reg &= HV_M_STATUS_LINK_UP |
1122                                       HV_M_STATUS_AUTONEG_COMPLETE |
1123                                       HV_M_STATUS_SPEED_MASK;
1124
1125                         if (status_reg == (HV_M_STATUS_LINK_UP |
1126                                            HV_M_STATUS_AUTONEG_COMPLETE |
1127                                            HV_M_STATUS_SPEED_1000))
1128                                 k1_enable = false;
1129                 }
1130
1131                 /* Link stall fix for link up */
1132                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1133                                                            0x0100);
1134                 if (ret_val)
1135                         goto release;
1136
1137         } else {
1138                 /* Link stall fix for link down */
1139                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1140                                                            0x4100);
1141                 if (ret_val)
1142                         goto release;
1143         }
1144
1145         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1146
1147 release:
1148         hw->phy.ops.release(hw);
1149 out:
1150         return ret_val;
1151 }
1152
1153 /**
1154  *  e1000_configure_k1_ich8lan - Configure K1 power state
1155  *  @hw: pointer to the HW structure
1156  *  @enable: K1 state to configure
1157  *
1158  *  Configure the K1 power state based on the provided parameter.
1159  *  Assumes semaphore already acquired.
1160  *
1161  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1162  **/
1163 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1164 {
1165         s32 ret_val = 0;
1166         u32 ctrl_reg = 0;
1167         u32 ctrl_ext = 0;
1168         u32 reg = 0;
1169         u16 kmrn_reg = 0;
1170
1171         ret_val = e1000e_read_kmrn_reg_locked(hw,
1172                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1173                                              &kmrn_reg);
1174         if (ret_val)
1175                 goto out;
1176
1177         if (k1_enable)
1178                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1179         else
1180                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1181
1182         ret_val = e1000e_write_kmrn_reg_locked(hw,
1183                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1184                                               kmrn_reg);
1185         if (ret_val)
1186                 goto out;
1187
1188         udelay(20);
1189         ctrl_ext = er32(CTRL_EXT);
1190         ctrl_reg = er32(CTRL);
1191
1192         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1193         reg |= E1000_CTRL_FRCSPD;
1194         ew32(CTRL, reg);
1195
1196         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1197         udelay(20);
1198         ew32(CTRL, ctrl_reg);
1199         ew32(CTRL_EXT, ctrl_ext);
1200         udelay(20);
1201
1202 out:
1203         return ret_val;
1204 }
1205
1206 /**
1207  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1208  *  @hw:       pointer to the HW structure
1209  *  @d0_state: boolean if entering d0 or d3 device state
1210  *
1211  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1212  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1213  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1214  **/
1215 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1216 {
1217         s32 ret_val = 0;
1218         u32 mac_reg;
1219         u16 oem_reg;
1220
1221         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1222                 return ret_val;
1223
1224         ret_val = hw->phy.ops.acquire(hw);
1225         if (ret_val)
1226                 return ret_val;
1227
1228         if (!(hw->mac.type == e1000_pch2lan)) {
1229                 mac_reg = er32(EXTCNF_CTRL);
1230                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1231                         goto out;
1232         }
1233
1234         mac_reg = er32(FEXTNVM);
1235         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1236                 goto out;
1237
1238         mac_reg = er32(PHY_CTRL);
1239
1240         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1241         if (ret_val)
1242                 goto out;
1243
1244         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1245
1246         if (d0_state) {
1247                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1248                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1249
1250                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1251                         oem_reg |= HV_OEM_BITS_LPLU;
1252         } else {
1253                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1254                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1255
1256                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1257                         oem_reg |= HV_OEM_BITS_LPLU;
1258         }
1259         /* Restart auto-neg to activate the bits */
1260         if (!e1000_check_reset_block(hw))
1261                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1262         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1263
1264 out:
1265         hw->phy.ops.release(hw);
1266
1267         return ret_val;
1268 }
1269
1270
1271 /**
1272  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1273  *  @hw:   pointer to the HW structure
1274  **/
1275 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1276 {
1277         s32 ret_val;
1278         u16 data;
1279
1280         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1281         if (ret_val)
1282                 return ret_val;
1283
1284         data |= HV_KMRN_MDIO_SLOW;
1285
1286         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1287
1288         return ret_val;
1289 }
1290
1291 /**
1292  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1293  *  done after every PHY reset.
1294  **/
1295 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1296 {
1297         s32 ret_val = 0;
1298         u16 phy_data;
1299
1300         if (hw->mac.type != e1000_pchlan)
1301                 return ret_val;
1302
1303         /* Set MDIO slow mode before any other MDIO access */
1304         if (hw->phy.type == e1000_phy_82577) {
1305                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1306                 if (ret_val)
1307                         goto out;
1308         }
1309
1310         if (((hw->phy.type == e1000_phy_82577) &&
1311              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1312             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1313                 /* Disable generation of early preamble */
1314                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1315                 if (ret_val)
1316                         return ret_val;
1317
1318                 /* Preamble tuning for SSC */
1319                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1320                 if (ret_val)
1321                         return ret_val;
1322         }
1323
1324         if (hw->phy.type == e1000_phy_82578) {
1325                 /*
1326                  * Return registers to default by doing a soft reset then
1327                  * writing 0x3140 to the control register.
1328                  */
1329                 if (hw->phy.revision < 2) {
1330                         e1000e_phy_sw_reset(hw);
1331                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1332                 }
1333         }
1334
1335         /* Select page 0 */
1336         ret_val = hw->phy.ops.acquire(hw);
1337         if (ret_val)
1338                 return ret_val;
1339
1340         hw->phy.addr = 1;
1341         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1342         hw->phy.ops.release(hw);
1343         if (ret_val)
1344                 goto out;
1345
1346         /*
1347          * Configure the K1 Si workaround during phy reset assuming there is
1348          * link so that it disables K1 if link is in 1Gbps.
1349          */
1350         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1351         if (ret_val)
1352                 goto out;
1353
1354         /* Workaround for link disconnects on a busy hub in half duplex */
1355         ret_val = hw->phy.ops.acquire(hw);
1356         if (ret_val)
1357                 goto out;
1358         ret_val = hw->phy.ops.read_reg_locked(hw,
1359                                               PHY_REG(BM_PORT_CTRL_PAGE, 17),
1360                                               &phy_data);
1361         if (ret_val)
1362                 goto release;
1363         ret_val = hw->phy.ops.write_reg_locked(hw,
1364                                                PHY_REG(BM_PORT_CTRL_PAGE, 17),
1365                                                phy_data & 0x00FF);
1366 release:
1367         hw->phy.ops.release(hw);
1368 out:
1369         return ret_val;
1370 }
1371
1372 /**
1373  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1374  *  @hw:   pointer to the HW structure
1375  **/
1376 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1377 {
1378         u32 mac_reg;
1379         u16 i;
1380
1381         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1382         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1383                 mac_reg = er32(RAL(i));
1384                 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1385                 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1386                 mac_reg = er32(RAH(i));
1387                 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1388                 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1389         }
1390 }
1391
1392 static u32 e1000_calc_rx_da_crc(u8 mac[])
1393 {
1394         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
1395         u32 i, j, mask, crc;
1396
1397         crc = 0xffffffff;
1398         for (i = 0; i < 6; i++) {
1399                 crc = crc ^ mac[i];
1400                 for (j = 8; j > 0; j--) {
1401                         mask = (crc & 1) * (-1);
1402                         crc = (crc >> 1) ^ (poly & mask);
1403                 }
1404         }
1405         return ~crc;
1406 }
1407
1408 /**
1409  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1410  *  with 82579 PHY
1411  *  @hw: pointer to the HW structure
1412  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1413  **/
1414 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1415 {
1416         s32 ret_val = 0;
1417         u16 phy_reg, data;
1418         u32 mac_reg;
1419         u16 i;
1420
1421         if (hw->mac.type != e1000_pch2lan)
1422                 goto out;
1423
1424         /* disable Rx path while enabling/disabling workaround */
1425         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1426         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1427         if (ret_val)
1428                 goto out;
1429
1430         if (enable) {
1431                 /*
1432                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1433                  * SHRAL/H) and initial CRC values to the MAC
1434                  */
1435                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1436                         u8 mac_addr[ETH_ALEN] = {0};
1437                         u32 addr_high, addr_low;
1438
1439                         addr_high = er32(RAH(i));
1440                         if (!(addr_high & E1000_RAH_AV))
1441                                 continue;
1442                         addr_low = er32(RAL(i));
1443                         mac_addr[0] = (addr_low & 0xFF);
1444                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1445                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1446                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1447                         mac_addr[4] = (addr_high & 0xFF);
1448                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1449
1450                         ew32(PCH_RAICC(i),
1451                                         e1000_calc_rx_da_crc(mac_addr));
1452                 }
1453
1454                 /* Write Rx addresses to the PHY */
1455                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1456
1457                 /* Enable jumbo frame workaround in the MAC */
1458                 mac_reg = er32(FFLT_DBG);
1459                 mac_reg &= ~(1 << 14);
1460                 mac_reg |= (7 << 15);
1461                 ew32(FFLT_DBG, mac_reg);
1462
1463                 mac_reg = er32(RCTL);
1464                 mac_reg |= E1000_RCTL_SECRC;
1465                 ew32(RCTL, mac_reg);
1466
1467                 ret_val = e1000e_read_kmrn_reg(hw,
1468                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1469                                                 &data);
1470                 if (ret_val)
1471                         goto out;
1472                 ret_val = e1000e_write_kmrn_reg(hw,
1473                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1474                                                 data | (1 << 0));
1475                 if (ret_val)
1476                         goto out;
1477                 ret_val = e1000e_read_kmrn_reg(hw,
1478                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1479                                                 &data);
1480                 if (ret_val)
1481                         goto out;
1482                 data &= ~(0xF << 8);
1483                 data |= (0xB << 8);
1484                 ret_val = e1000e_write_kmrn_reg(hw,
1485                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1486                                                 data);
1487                 if (ret_val)
1488                         goto out;
1489
1490                 /* Enable jumbo frame workaround in the PHY */
1491                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1492                 data &= ~(0x7F << 5);
1493                 data |= (0x37 << 5);
1494                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1495                 if (ret_val)
1496                         goto out;
1497                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1498                 data &= ~(1 << 13);
1499                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1500                 if (ret_val)
1501                         goto out;
1502                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1503                 data &= ~(0x3FF << 2);
1504                 data |= (0x1A << 2);
1505                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1506                 if (ret_val)
1507                         goto out;
1508                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1509                 if (ret_val)
1510                         goto out;
1511                 e1e_rphy(hw, HV_PM_CTRL, &data);
1512                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1513                 if (ret_val)
1514                         goto out;
1515         } else {
1516                 /* Write MAC register values back to h/w defaults */
1517                 mac_reg = er32(FFLT_DBG);
1518                 mac_reg &= ~(0xF << 14);
1519                 ew32(FFLT_DBG, mac_reg);
1520
1521                 mac_reg = er32(RCTL);
1522                 mac_reg &= ~E1000_RCTL_SECRC;
1523                 ew32(RCTL, mac_reg);
1524
1525                 ret_val = e1000e_read_kmrn_reg(hw,
1526                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1527                                                 &data);
1528                 if (ret_val)
1529                         goto out;
1530                 ret_val = e1000e_write_kmrn_reg(hw,
1531                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1532                                                 data & ~(1 << 0));
1533                 if (ret_val)
1534                         goto out;
1535                 ret_val = e1000e_read_kmrn_reg(hw,
1536                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1537                                                 &data);
1538                 if (ret_val)
1539                         goto out;
1540                 data &= ~(0xF << 8);
1541                 data |= (0xB << 8);
1542                 ret_val = e1000e_write_kmrn_reg(hw,
1543                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1544                                                 data);
1545                 if (ret_val)
1546                         goto out;
1547
1548                 /* Write PHY register values back to h/w defaults */
1549                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1550                 data &= ~(0x7F << 5);
1551                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1552                 if (ret_val)
1553                         goto out;
1554                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1555                 data |= (1 << 13);
1556                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1557                 if (ret_val)
1558                         goto out;
1559                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1560                 data &= ~(0x3FF << 2);
1561                 data |= (0x8 << 2);
1562                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1563                 if (ret_val)
1564                         goto out;
1565                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1566                 if (ret_val)
1567                         goto out;
1568                 e1e_rphy(hw, HV_PM_CTRL, &data);
1569                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1570                 if (ret_val)
1571                         goto out;
1572         }
1573
1574         /* re-enable Rx path after enabling/disabling workaround */
1575         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1576
1577 out:
1578         return ret_val;
1579 }
1580
1581 /**
1582  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1583  *  done after every PHY reset.
1584  **/
1585 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1586 {
1587         s32 ret_val = 0;
1588
1589         if (hw->mac.type != e1000_pch2lan)
1590                 goto out;
1591
1592         /* Set MDIO slow mode before any other MDIO access */
1593         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1594
1595 out:
1596         return ret_val;
1597 }
1598
1599 /**
1600  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1601  *  @hw:   pointer to the HW structure
1602  *
1603  *  Workaround to set the K1 beacon duration for 82579 parts
1604  **/
1605 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1606 {
1607         s32 ret_val = 0;
1608         u16 status_reg = 0;
1609         u32 mac_reg;
1610
1611         if (hw->mac.type != e1000_pch2lan)
1612                 goto out;
1613
1614         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1615         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1616         if (ret_val)
1617                 goto out;
1618
1619         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1620             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1621                 mac_reg = er32(FEXTNVM4);
1622                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1623
1624                 if (status_reg & HV_M_STATUS_SPEED_1000)
1625                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1626                 else
1627                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1628
1629                 ew32(FEXTNVM4, mac_reg);
1630         }
1631
1632 out:
1633         return ret_val;
1634 }
1635
1636 /**
1637  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1638  *  @hw:   pointer to the HW structure
1639  *  @gate: boolean set to true to gate, false to ungate
1640  *
1641  *  Gate/ungate the automatic PHY configuration via hardware; perform
1642  *  the configuration via software instead.
1643  **/
1644 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1645 {
1646         u32 extcnf_ctrl;
1647
1648         if (hw->mac.type != e1000_pch2lan)
1649                 return;
1650
1651         extcnf_ctrl = er32(EXTCNF_CTRL);
1652
1653         if (gate)
1654                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1655         else
1656                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1657
1658         ew32(EXTCNF_CTRL, extcnf_ctrl);
1659         return;
1660 }
1661
1662 /**
1663  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1664  *  @hw: pointer to the HW structure
1665  *
1666  *  Check the appropriate indication the MAC has finished configuring the
1667  *  PHY after a software reset.
1668  **/
1669 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1670 {
1671         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1672
1673         /* Wait for basic configuration completes before proceeding */
1674         do {
1675                 data = er32(STATUS);
1676                 data &= E1000_STATUS_LAN_INIT_DONE;
1677                 udelay(100);
1678         } while ((!data) && --loop);
1679
1680         /*
1681          * If basic configuration is incomplete before the above loop
1682          * count reaches 0, loading the configuration from NVM will
1683          * leave the PHY in a bad state possibly resulting in no link.
1684          */
1685         if (loop == 0)
1686                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1687
1688         /* Clear the Init Done bit for the next init event */
1689         data = er32(STATUS);
1690         data &= ~E1000_STATUS_LAN_INIT_DONE;
1691         ew32(STATUS, data);
1692 }
1693
1694 /**
1695  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1696  *  @hw: pointer to the HW structure
1697  **/
1698 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1699 {
1700         s32 ret_val = 0;
1701         u16 reg;
1702
1703         if (e1000_check_reset_block(hw))
1704                 goto out;
1705
1706         /* Allow time for h/w to get to quiescent state after reset */
1707         msleep(10);
1708
1709         /* Perform any necessary post-reset workarounds */
1710         switch (hw->mac.type) {
1711         case e1000_pchlan:
1712                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1713                 if (ret_val)
1714                         goto out;
1715                 break;
1716         case e1000_pch2lan:
1717                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1718                 if (ret_val)
1719                         goto out;
1720                 break;
1721         default:
1722                 break;
1723         }
1724
1725         /* Dummy read to clear the phy wakeup bit after lcd reset */
1726         if (hw->mac.type >= e1000_pchlan)
1727                 e1e_rphy(hw, BM_WUC, &reg);
1728
1729         /* Configure the LCD with the extended configuration region in NVM */
1730         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1731         if (ret_val)
1732                 goto out;
1733
1734         /* Configure the LCD with the OEM bits in NVM */
1735         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1736
1737         /* Ungate automatic PHY configuration on non-managed 82579 */
1738         if ((hw->mac.type == e1000_pch2lan) &&
1739             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1740                 msleep(10);
1741                 e1000_gate_hw_phy_config_ich8lan(hw, false);
1742         }
1743
1744 out:
1745         return ret_val;
1746 }
1747
1748 /**
1749  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1750  *  @hw: pointer to the HW structure
1751  *
1752  *  Resets the PHY
1753  *  This is a function pointer entry point called by drivers
1754  *  or other shared routines.
1755  **/
1756 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1757 {
1758         s32 ret_val = 0;
1759
1760         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1761         if ((hw->mac.type == e1000_pch2lan) &&
1762             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1763                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1764
1765         ret_val = e1000e_phy_hw_reset_generic(hw);
1766         if (ret_val)
1767                 goto out;
1768
1769         ret_val = e1000_post_phy_reset_ich8lan(hw);
1770
1771 out:
1772         return ret_val;
1773 }
1774
1775 /**
1776  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1777  *  @hw: pointer to the HW structure
1778  *  @active: true to enable LPLU, false to disable
1779  *
1780  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1781  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1782  *  the phy speed. This function will manually set the LPLU bit and restart
1783  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1784  *  since it configures the same bit.
1785  **/
1786 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1787 {
1788         s32 ret_val = 0;
1789         u16 oem_reg;
1790
1791         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1792         if (ret_val)
1793                 goto out;
1794
1795         if (active)
1796                 oem_reg |= HV_OEM_BITS_LPLU;
1797         else
1798                 oem_reg &= ~HV_OEM_BITS_LPLU;
1799
1800         oem_reg |= HV_OEM_BITS_RESTART_AN;
1801         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1802
1803 out:
1804         return ret_val;
1805 }
1806
1807 /**
1808  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1809  *  @hw: pointer to the HW structure
1810  *  @active: true to enable LPLU, false to disable
1811  *
1812  *  Sets the LPLU D0 state according to the active flag.  When
1813  *  activating LPLU this function also disables smart speed
1814  *  and vice versa.  LPLU will not be activated unless the
1815  *  device autonegotiation advertisement meets standards of
1816  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1817  *  This is a function pointer entry point only called by
1818  *  PHY setup routines.
1819  **/
1820 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1821 {
1822         struct e1000_phy_info *phy = &hw->phy;
1823         u32 phy_ctrl;
1824         s32 ret_val = 0;
1825         u16 data;
1826
1827         if (phy->type == e1000_phy_ife)
1828                 return ret_val;
1829
1830         phy_ctrl = er32(PHY_CTRL);
1831
1832         if (active) {
1833                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1834                 ew32(PHY_CTRL, phy_ctrl);
1835
1836                 if (phy->type != e1000_phy_igp_3)
1837                         return 0;
1838
1839                 /*
1840                  * Call gig speed drop workaround on LPLU before accessing
1841                  * any PHY registers
1842                  */
1843                 if (hw->mac.type == e1000_ich8lan)
1844                         e1000e_gig_downshift_workaround_ich8lan(hw);
1845
1846                 /* When LPLU is enabled, we should disable SmartSpeed */
1847                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1848                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1849                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1850                 if (ret_val)
1851                         return ret_val;
1852         } else {
1853                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1854                 ew32(PHY_CTRL, phy_ctrl);
1855
1856                 if (phy->type != e1000_phy_igp_3)
1857                         return 0;
1858
1859                 /*
1860                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1861                  * during Dx states where the power conservation is most
1862                  * important.  During driver activity we should enable
1863                  * SmartSpeed, so performance is maintained.
1864                  */
1865                 if (phy->smart_speed == e1000_smart_speed_on) {
1866                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1867                                            &data);
1868                         if (ret_val)
1869                                 return ret_val;
1870
1871                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1872                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1873                                            data);
1874                         if (ret_val)
1875                                 return ret_val;
1876                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1877                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1878                                            &data);
1879                         if (ret_val)
1880                                 return ret_val;
1881
1882                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1883                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1884                                            data);
1885                         if (ret_val)
1886                                 return ret_val;
1887                 }
1888         }
1889
1890         return 0;
1891 }
1892
1893 /**
1894  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1895  *  @hw: pointer to the HW structure
1896  *  @active: true to enable LPLU, false to disable
1897  *
1898  *  Sets the LPLU D3 state according to the active flag.  When
1899  *  activating LPLU this function also disables smart speed
1900  *  and vice versa.  LPLU will not be activated unless the
1901  *  device autonegotiation advertisement meets standards of
1902  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1903  *  This is a function pointer entry point only called by
1904  *  PHY setup routines.
1905  **/
1906 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1907 {
1908         struct e1000_phy_info *phy = &hw->phy;
1909         u32 phy_ctrl;
1910         s32 ret_val;
1911         u16 data;
1912
1913         phy_ctrl = er32(PHY_CTRL);
1914
1915         if (!active) {
1916                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1917                 ew32(PHY_CTRL, phy_ctrl);
1918
1919                 if (phy->type != e1000_phy_igp_3)
1920                         return 0;
1921
1922                 /*
1923                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1924                  * during Dx states where the power conservation is most
1925                  * important.  During driver activity we should enable
1926                  * SmartSpeed, so performance is maintained.
1927                  */
1928                 if (phy->smart_speed == e1000_smart_speed_on) {
1929                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1930                                            &data);
1931                         if (ret_val)
1932                                 return ret_val;
1933
1934                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1935                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1936                                            data);
1937                         if (ret_val)
1938                                 return ret_val;
1939                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1940                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1941                                            &data);
1942                         if (ret_val)
1943                                 return ret_val;
1944
1945                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1946                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1947                                            data);
1948                         if (ret_val)
1949                                 return ret_val;
1950                 }
1951         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1952                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1953                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1954                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1955                 ew32(PHY_CTRL, phy_ctrl);
1956
1957                 if (phy->type != e1000_phy_igp_3)
1958                         return 0;
1959
1960                 /*
1961                  * Call gig speed drop workaround on LPLU before accessing
1962                  * any PHY registers
1963                  */
1964                 if (hw->mac.type == e1000_ich8lan)
1965                         e1000e_gig_downshift_workaround_ich8lan(hw);
1966
1967                 /* When LPLU is enabled, we should disable SmartSpeed */
1968                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1969                 if (ret_val)
1970                         return ret_val;
1971
1972                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1973                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1974         }
1975
1976         return 0;
1977 }
1978
1979 /**
1980  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1981  *  @hw: pointer to the HW structure
1982  *  @bank:  pointer to the variable that returns the active bank
1983  *
1984  *  Reads signature byte from the NVM using the flash access registers.
1985  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1986  **/
1987 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1988 {
1989         u32 eecd;
1990         struct e1000_nvm_info *nvm = &hw->nvm;
1991         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1992         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1993         u8 sig_byte = 0;
1994         s32 ret_val = 0;
1995
1996         switch (hw->mac.type) {
1997         case e1000_ich8lan:
1998         case e1000_ich9lan:
1999                 eecd = er32(EECD);
2000                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2001                     E1000_EECD_SEC1VAL_VALID_MASK) {
2002                         if (eecd & E1000_EECD_SEC1VAL)
2003                                 *bank = 1;
2004                         else
2005                                 *bank = 0;
2006
2007                         return 0;
2008                 }
2009                 e_dbg("Unable to determine valid NVM bank via EEC - "
2010                        "reading flash signature\n");
2011                 /* fall-thru */
2012         default:
2013                 /* set bank to 0 in case flash read fails */
2014                 *bank = 0;
2015
2016                 /* Check bank 0 */
2017                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2018                                                         &sig_byte);
2019                 if (ret_val)
2020                         return ret_val;
2021                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2022                     E1000_ICH_NVM_SIG_VALUE) {
2023                         *bank = 0;
2024                         return 0;
2025                 }
2026
2027                 /* Check bank 1 */
2028                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2029                                                         bank1_offset,
2030                                                         &sig_byte);
2031                 if (ret_val)
2032                         return ret_val;
2033                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2034                     E1000_ICH_NVM_SIG_VALUE) {
2035                         *bank = 1;
2036                         return 0;
2037                 }
2038
2039                 e_dbg("ERROR: No valid NVM bank present\n");
2040                 return -E1000_ERR_NVM;
2041         }
2042
2043         return 0;
2044 }
2045
2046 /**
2047  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2048  *  @hw: pointer to the HW structure
2049  *  @offset: The offset (in bytes) of the word(s) to read.
2050  *  @words: Size of data to read in words
2051  *  @data: Pointer to the word(s) to read at offset.
2052  *
2053  *  Reads a word(s) from the NVM using the flash access registers.
2054  **/
2055 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2056                                   u16 *data)
2057 {
2058         struct e1000_nvm_info *nvm = &hw->nvm;
2059         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2060         u32 act_offset;
2061         s32 ret_val = 0;
2062         u32 bank = 0;
2063         u16 i, word;
2064
2065         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2066             (words == 0)) {
2067                 e_dbg("nvm parameter(s) out of bounds\n");
2068                 ret_val = -E1000_ERR_NVM;
2069                 goto out;
2070         }
2071
2072         nvm->ops.acquire(hw);
2073
2074         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2075         if (ret_val) {
2076                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2077                 bank = 0;
2078         }
2079
2080         act_offset = (bank) ? nvm->flash_bank_size : 0;
2081         act_offset += offset;
2082
2083         ret_val = 0;
2084         for (i = 0; i < words; i++) {
2085                 if ((dev_spec->shadow_ram) &&
2086                     (dev_spec->shadow_ram[offset+i].modified)) {
2087                         data[i] = dev_spec->shadow_ram[offset+i].value;
2088                 } else {
2089                         ret_val = e1000_read_flash_word_ich8lan(hw,
2090                                                                 act_offset + i,
2091                                                                 &word);
2092                         if (ret_val)
2093                                 break;
2094                         data[i] = word;
2095                 }
2096         }
2097
2098         nvm->ops.release(hw);
2099
2100 out:
2101         if (ret_val)
2102                 e_dbg("NVM read error: %d\n", ret_val);
2103
2104         return ret_val;
2105 }
2106
2107 /**
2108  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2109  *  @hw: pointer to the HW structure
2110  *
2111  *  This function does initial flash setup so that a new read/write/erase cycle
2112  *  can be started.
2113  **/
2114 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2115 {
2116         union ich8_hws_flash_status hsfsts;
2117         s32 ret_val = -E1000_ERR_NVM;
2118         s32 i = 0;
2119
2120         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2121
2122         /* Check if the flash descriptor is valid */
2123         if (hsfsts.hsf_status.fldesvalid == 0) {
2124                 e_dbg("Flash descriptor invalid.  "
2125                          "SW Sequencing must be used.\n");
2126                 return -E1000_ERR_NVM;
2127         }
2128
2129         /* Clear FCERR and DAEL in hw status by writing 1 */
2130         hsfsts.hsf_status.flcerr = 1;
2131         hsfsts.hsf_status.dael = 1;
2132
2133         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2134
2135         /*
2136          * Either we should have a hardware SPI cycle in progress
2137          * bit to check against, in order to start a new cycle or
2138          * FDONE bit should be changed in the hardware so that it
2139          * is 1 after hardware reset, which can then be used as an
2140          * indication whether a cycle is in progress or has been
2141          * completed.
2142          */
2143
2144         if (hsfsts.hsf_status.flcinprog == 0) {
2145                 /*
2146                  * There is no cycle running at present,
2147                  * so we can start a cycle.
2148                  * Begin by setting Flash Cycle Done.
2149                  */
2150                 hsfsts.hsf_status.flcdone = 1;
2151                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2152                 ret_val = 0;
2153         } else {
2154                 /*
2155                  * Otherwise poll for sometime so the current
2156                  * cycle has a chance to end before giving up.
2157                  */
2158                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2159                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2160                         if (hsfsts.hsf_status.flcinprog == 0) {
2161                                 ret_val = 0;
2162                                 break;
2163                         }
2164                         udelay(1);
2165                 }
2166                 if (ret_val == 0) {
2167                         /*
2168                          * Successful in waiting for previous cycle to timeout,
2169                          * now set the Flash Cycle Done.
2170                          */
2171                         hsfsts.hsf_status.flcdone = 1;
2172                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2173                 } else {
2174                         e_dbg("Flash controller busy, cannot get access\n");
2175                 }
2176         }
2177
2178         return ret_val;
2179 }
2180
2181 /**
2182  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2183  *  @hw: pointer to the HW structure
2184  *  @timeout: maximum time to wait for completion
2185  *
2186  *  This function starts a flash cycle and waits for its completion.
2187  **/
2188 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2189 {
2190         union ich8_hws_flash_ctrl hsflctl;
2191         union ich8_hws_flash_status hsfsts;
2192         s32 ret_val = -E1000_ERR_NVM;
2193         u32 i = 0;
2194
2195         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2196         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2197         hsflctl.hsf_ctrl.flcgo = 1;
2198         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2199
2200         /* wait till FDONE bit is set to 1 */
2201         do {
2202                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2203                 if (hsfsts.hsf_status.flcdone == 1)
2204                         break;
2205                 udelay(1);
2206         } while (i++ < timeout);
2207
2208         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2209                 return 0;
2210
2211         return ret_val;
2212 }
2213
2214 /**
2215  *  e1000_read_flash_word_ich8lan - Read word from flash
2216  *  @hw: pointer to the HW structure
2217  *  @offset: offset to data location
2218  *  @data: pointer to the location for storing the data
2219  *
2220  *  Reads the flash word at offset into data.  Offset is converted
2221  *  to bytes before read.
2222  **/
2223 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2224                                          u16 *data)
2225 {
2226         /* Must convert offset into bytes. */
2227         offset <<= 1;
2228
2229         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2230 }
2231
2232 /**
2233  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2234  *  @hw: pointer to the HW structure
2235  *  @offset: The offset of the byte to read.
2236  *  @data: Pointer to a byte to store the value read.
2237  *
2238  *  Reads a single byte from the NVM using the flash access registers.
2239  **/
2240 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2241                                          u8 *data)
2242 {
2243         s32 ret_val;
2244         u16 word = 0;
2245
2246         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2247         if (ret_val)
2248                 return ret_val;
2249
2250         *data = (u8)word;
2251
2252         return 0;
2253 }
2254
2255 /**
2256  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2257  *  @hw: pointer to the HW structure
2258  *  @offset: The offset (in bytes) of the byte or word to read.
2259  *  @size: Size of data to read, 1=byte 2=word
2260  *  @data: Pointer to the word to store the value read.
2261  *
2262  *  Reads a byte or word from the NVM using the flash access registers.
2263  **/
2264 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2265                                          u8 size, u16 *data)
2266 {
2267         union ich8_hws_flash_status hsfsts;
2268         union ich8_hws_flash_ctrl hsflctl;
2269         u32 flash_linear_addr;
2270         u32 flash_data = 0;
2271         s32 ret_val = -E1000_ERR_NVM;
2272         u8 count = 0;
2273
2274         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2275                 return -E1000_ERR_NVM;
2276
2277         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2278                             hw->nvm.flash_base_addr;
2279
2280         do {
2281                 udelay(1);
2282                 /* Steps */
2283                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2284                 if (ret_val != 0)
2285                         break;
2286
2287                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2288                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2289                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2290                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2291                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2292
2293                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2294
2295                 ret_val = e1000_flash_cycle_ich8lan(hw,
2296                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2297
2298                 /*
2299                  * Check if FCERR is set to 1, if set to 1, clear it
2300                  * and try the whole sequence a few more times, else
2301                  * read in (shift in) the Flash Data0, the order is
2302                  * least significant byte first msb to lsb
2303                  */
2304                 if (ret_val == 0) {
2305                         flash_data = er32flash(ICH_FLASH_FDATA0);
2306                         if (size == 1) {
2307                                 *data = (u8)(flash_data & 0x000000FF);
2308                         } else if (size == 2) {
2309                                 *data = (u16)(flash_data & 0x0000FFFF);
2310                         }
2311                         break;
2312                 } else {
2313                         /*
2314                          * If we've gotten here, then things are probably
2315                          * completely hosed, but if the error condition is
2316                          * detected, it won't hurt to give it another try...
2317                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2318                          */
2319                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2320                         if (hsfsts.hsf_status.flcerr == 1) {
2321                                 /* Repeat for some time before giving up. */
2322                                 continue;
2323                         } else if (hsfsts.hsf_status.flcdone == 0) {
2324                                 e_dbg("Timeout error - flash cycle "
2325                                          "did not complete.\n");
2326                                 break;
2327                         }
2328                 }
2329         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2330
2331         return ret_val;
2332 }
2333
2334 /**
2335  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2336  *  @hw: pointer to the HW structure
2337  *  @offset: The offset (in bytes) of the word(s) to write.
2338  *  @words: Size of data to write in words
2339  *  @data: Pointer to the word(s) to write at offset.
2340  *
2341  *  Writes a byte or word to the NVM using the flash access registers.
2342  **/
2343 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2344                                    u16 *data)
2345 {
2346         struct e1000_nvm_info *nvm = &hw->nvm;
2347         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2348         u16 i;
2349
2350         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2351             (words == 0)) {
2352                 e_dbg("nvm parameter(s) out of bounds\n");
2353                 return -E1000_ERR_NVM;
2354         }
2355
2356         nvm->ops.acquire(hw);
2357
2358         for (i = 0; i < words; i++) {
2359                 dev_spec->shadow_ram[offset+i].modified = true;
2360                 dev_spec->shadow_ram[offset+i].value = data[i];
2361         }
2362
2363         nvm->ops.release(hw);
2364
2365         return 0;
2366 }
2367
2368 /**
2369  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2370  *  @hw: pointer to the HW structure
2371  *
2372  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2373  *  which writes the checksum to the shadow ram.  The changes in the shadow
2374  *  ram are then committed to the EEPROM by processing each bank at a time
2375  *  checking for the modified bit and writing only the pending changes.
2376  *  After a successful commit, the shadow ram is cleared and is ready for
2377  *  future writes.
2378  **/
2379 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2380 {
2381         struct e1000_nvm_info *nvm = &hw->nvm;
2382         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2383         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2384         s32 ret_val;
2385         u16 data;
2386
2387         ret_val = e1000e_update_nvm_checksum_generic(hw);
2388         if (ret_val)
2389                 goto out;
2390
2391         if (nvm->type != e1000_nvm_flash_sw)
2392                 goto out;
2393
2394         nvm->ops.acquire(hw);
2395
2396         /*
2397          * We're writing to the opposite bank so if we're on bank 1,
2398          * write to bank 0 etc.  We also need to erase the segment that
2399          * is going to be written
2400          */
2401         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2402         if (ret_val) {
2403                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2404                 bank = 0;
2405         }
2406
2407         if (bank == 0) {
2408                 new_bank_offset = nvm->flash_bank_size;
2409                 old_bank_offset = 0;
2410                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2411                 if (ret_val)
2412                         goto release;
2413         } else {
2414                 old_bank_offset = nvm->flash_bank_size;
2415                 new_bank_offset = 0;
2416                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2417                 if (ret_val)
2418                         goto release;
2419         }
2420
2421         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2422                 /*
2423                  * Determine whether to write the value stored
2424                  * in the other NVM bank or a modified value stored
2425                  * in the shadow RAM
2426                  */
2427                 if (dev_spec->shadow_ram[i].modified) {
2428                         data = dev_spec->shadow_ram[i].value;
2429                 } else {
2430                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2431                                                                 old_bank_offset,
2432                                                                 &data);
2433                         if (ret_val)
2434                                 break;
2435                 }
2436
2437                 /*
2438                  * If the word is 0x13, then make sure the signature bits
2439                  * (15:14) are 11b until the commit has completed.
2440                  * This will allow us to write 10b which indicates the
2441                  * signature is valid.  We want to do this after the write
2442                  * has completed so that we don't mark the segment valid
2443                  * while the write is still in progress
2444                  */
2445                 if (i == E1000_ICH_NVM_SIG_WORD)
2446                         data |= E1000_ICH_NVM_SIG_MASK;
2447
2448                 /* Convert offset to bytes. */
2449                 act_offset = (i + new_bank_offset) << 1;
2450
2451                 udelay(100);
2452                 /* Write the bytes to the new bank. */
2453                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2454                                                                act_offset,
2455                                                                (u8)data);
2456                 if (ret_val)
2457                         break;
2458
2459                 udelay(100);
2460                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2461                                                           act_offset + 1,
2462                                                           (u8)(data >> 8));
2463                 if (ret_val)
2464                         break;
2465         }
2466
2467         /*
2468          * Don't bother writing the segment valid bits if sector
2469          * programming failed.
2470          */
2471         if (ret_val) {
2472                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2473                 e_dbg("Flash commit failed.\n");
2474                 goto release;
2475         }
2476
2477         /*
2478          * Finally validate the new segment by setting bit 15:14
2479          * to 10b in word 0x13 , this can be done without an
2480          * erase as well since these bits are 11 to start with
2481          * and we need to change bit 14 to 0b
2482          */
2483         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2484         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2485         if (ret_val)
2486                 goto release;
2487
2488         data &= 0xBFFF;
2489         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2490                                                        act_offset * 2 + 1,
2491                                                        (u8)(data >> 8));
2492         if (ret_val)
2493                 goto release;
2494
2495         /*
2496          * And invalidate the previously valid segment by setting
2497          * its signature word (0x13) high_byte to 0b. This can be
2498          * done without an erase because flash erase sets all bits
2499          * to 1's. We can write 1's to 0's without an erase
2500          */
2501         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2502         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2503         if (ret_val)
2504                 goto release;
2505
2506         /* Great!  Everything worked, we can now clear the cached entries. */
2507         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2508                 dev_spec->shadow_ram[i].modified = false;
2509                 dev_spec->shadow_ram[i].value = 0xFFFF;
2510         }
2511
2512 release:
2513         nvm->ops.release(hw);
2514
2515         /*
2516          * Reload the EEPROM, or else modifications will not appear
2517          * until after the next adapter reset.
2518          */
2519         if (!ret_val) {
2520                 e1000e_reload_nvm(hw);
2521                 msleep(10);
2522         }
2523
2524 out:
2525         if (ret_val)
2526                 e_dbg("NVM update error: %d\n", ret_val);
2527
2528         return ret_val;
2529 }
2530
2531 /**
2532  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2533  *  @hw: pointer to the HW structure
2534  *
2535  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2536  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2537  *  calculated, in which case we need to calculate the checksum and set bit 6.
2538  **/
2539 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2540 {
2541         s32 ret_val;
2542         u16 data;
2543
2544         /*
2545          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2546          * needs to be fixed.  This bit is an indication that the NVM
2547          * was prepared by OEM software and did not calculate the
2548          * checksum...a likely scenario.
2549          */
2550         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2551         if (ret_val)
2552                 return ret_val;
2553
2554         if ((data & 0x40) == 0) {
2555                 data |= 0x40;
2556                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2557                 if (ret_val)
2558                         return ret_val;
2559                 ret_val = e1000e_update_nvm_checksum(hw);
2560                 if (ret_val)
2561                         return ret_val;
2562         }
2563
2564         return e1000e_validate_nvm_checksum_generic(hw);
2565 }
2566
2567 /**
2568  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2569  *  @hw: pointer to the HW structure
2570  *
2571  *  To prevent malicious write/erase of the NVM, set it to be read-only
2572  *  so that the hardware ignores all write/erase cycles of the NVM via
2573  *  the flash control registers.  The shadow-ram copy of the NVM will
2574  *  still be updated, however any updates to this copy will not stick
2575  *  across driver reloads.
2576  **/
2577 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2578 {
2579         struct e1000_nvm_info *nvm = &hw->nvm;
2580         union ich8_flash_protected_range pr0;
2581         union ich8_hws_flash_status hsfsts;
2582         u32 gfpreg;
2583
2584         nvm->ops.acquire(hw);
2585
2586         gfpreg = er32flash(ICH_FLASH_GFPREG);
2587
2588         /* Write-protect GbE Sector of NVM */
2589         pr0.regval = er32flash(ICH_FLASH_PR0);
2590         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2591         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2592         pr0.range.wpe = true;
2593         ew32flash(ICH_FLASH_PR0, pr0.regval);
2594
2595         /*
2596          * Lock down a subset of GbE Flash Control Registers, e.g.
2597          * PR0 to prevent the write-protection from being lifted.
2598          * Once FLOCKDN is set, the registers protected by it cannot
2599          * be written until FLOCKDN is cleared by a hardware reset.
2600          */
2601         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2602         hsfsts.hsf_status.flockdn = true;
2603         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2604
2605         nvm->ops.release(hw);
2606 }
2607
2608 /**
2609  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2610  *  @hw: pointer to the HW structure
2611  *  @offset: The offset (in bytes) of the byte/word to read.
2612  *  @size: Size of data to read, 1=byte 2=word
2613  *  @data: The byte(s) to write to the NVM.
2614  *
2615  *  Writes one/two bytes to the NVM using the flash access registers.
2616  **/
2617 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2618                                           u8 size, u16 data)
2619 {
2620         union ich8_hws_flash_status hsfsts;
2621         union ich8_hws_flash_ctrl hsflctl;
2622         u32 flash_linear_addr;
2623         u32 flash_data = 0;
2624         s32 ret_val;
2625         u8 count = 0;
2626
2627         if (size < 1 || size > 2 || data > size * 0xff ||
2628             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2629                 return -E1000_ERR_NVM;
2630
2631         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2632                             hw->nvm.flash_base_addr;
2633
2634         do {
2635                 udelay(1);
2636                 /* Steps */
2637                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2638                 if (ret_val)
2639                         break;
2640
2641                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2642                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2643                 hsflctl.hsf_ctrl.fldbcount = size -1;
2644                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2645                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2646
2647                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2648
2649                 if (size == 1)
2650                         flash_data = (u32)data & 0x00FF;
2651                 else
2652                         flash_data = (u32)data;
2653
2654                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2655
2656                 /*
2657                  * check if FCERR is set to 1 , if set to 1, clear it
2658                  * and try the whole sequence a few more times else done
2659                  */
2660                 ret_val = e1000_flash_cycle_ich8lan(hw,
2661                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2662                 if (!ret_val)
2663                         break;
2664
2665                 /*
2666                  * If we're here, then things are most likely
2667                  * completely hosed, but if the error condition
2668                  * is detected, it won't hurt to give it another
2669                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2670                  */
2671                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2672                 if (hsfsts.hsf_status.flcerr == 1)
2673                         /* Repeat for some time before giving up. */
2674                         continue;
2675                 if (hsfsts.hsf_status.flcdone == 0) {
2676                         e_dbg("Timeout error - flash cycle "
2677                                  "did not complete.");
2678                         break;
2679                 }
2680         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2681
2682         return ret_val;
2683 }
2684
2685 /**
2686  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2687  *  @hw: pointer to the HW structure
2688  *  @offset: The index of the byte to read.
2689  *  @data: The byte to write to the NVM.
2690  *
2691  *  Writes a single byte to the NVM using the flash access registers.
2692  **/
2693 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2694                                           u8 data)
2695 {
2696         u16 word = (u16)data;
2697
2698         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2699 }
2700
2701 /**
2702  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2703  *  @hw: pointer to the HW structure
2704  *  @offset: The offset of the byte to write.
2705  *  @byte: The byte to write to the NVM.
2706  *
2707  *  Writes a single byte to the NVM using the flash access registers.
2708  *  Goes through a retry algorithm before giving up.
2709  **/
2710 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2711                                                 u32 offset, u8 byte)
2712 {
2713         s32 ret_val;
2714         u16 program_retries;
2715
2716         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2717         if (!ret_val)
2718                 return ret_val;
2719
2720         for (program_retries = 0; program_retries < 100; program_retries++) {
2721                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2722                 udelay(100);
2723                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2724                 if (!ret_val)
2725                         break;
2726         }
2727         if (program_retries == 100)
2728                 return -E1000_ERR_NVM;
2729
2730         return 0;
2731 }
2732
2733 /**
2734  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2735  *  @hw: pointer to the HW structure
2736  *  @bank: 0 for first bank, 1 for second bank, etc.
2737  *
2738  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2739  *  bank N is 4096 * N + flash_reg_addr.
2740  **/
2741 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2742 {
2743         struct e1000_nvm_info *nvm = &hw->nvm;
2744         union ich8_hws_flash_status hsfsts;
2745         union ich8_hws_flash_ctrl hsflctl;
2746         u32 flash_linear_addr;
2747         /* bank size is in 16bit words - adjust to bytes */
2748         u32 flash_bank_size = nvm->flash_bank_size * 2;
2749         s32 ret_val;
2750         s32 count = 0;
2751         s32 j, iteration, sector_size;
2752
2753         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2754
2755         /*
2756          * Determine HW Sector size: Read BERASE bits of hw flash status
2757          * register
2758          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2759          *     consecutive sectors.  The start index for the nth Hw sector
2760          *     can be calculated as = bank * 4096 + n * 256
2761          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2762          *     The start index for the nth Hw sector can be calculated
2763          *     as = bank * 4096
2764          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2765          *     (ich9 only, otherwise error condition)
2766          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2767          */
2768         switch (hsfsts.hsf_status.berasesz) {
2769         case 0:
2770                 /* Hw sector size 256 */
2771                 sector_size = ICH_FLASH_SEG_SIZE_256;
2772                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2773                 break;
2774         case 1:
2775                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2776                 iteration = 1;
2777                 break;
2778         case 2:
2779                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2780                 iteration = 1;
2781                 break;
2782         case 3:
2783                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2784                 iteration = 1;
2785                 break;
2786         default:
2787                 return -E1000_ERR_NVM;
2788         }
2789
2790         /* Start with the base address, then add the sector offset. */
2791         flash_linear_addr = hw->nvm.flash_base_addr;
2792         flash_linear_addr += (bank) ? flash_bank_size : 0;
2793
2794         for (j = 0; j < iteration ; j++) {
2795                 do {
2796                         /* Steps */
2797                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2798                         if (ret_val)
2799                                 return ret_val;
2800
2801                         /*
2802                          * Write a value 11 (block Erase) in Flash
2803                          * Cycle field in hw flash control
2804                          */
2805                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2806                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2807                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2808
2809                         /*
2810                          * Write the last 24 bits of an index within the
2811                          * block into Flash Linear address field in Flash
2812                          * Address.
2813                          */
2814                         flash_linear_addr += (j * sector_size);
2815                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2816
2817                         ret_val = e1000_flash_cycle_ich8lan(hw,
2818                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2819                         if (ret_val == 0)
2820                                 break;
2821
2822                         /*
2823                          * Check if FCERR is set to 1.  If 1,
2824                          * clear it and try the whole sequence
2825                          * a few more times else Done
2826                          */
2827                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2828                         if (hsfsts.hsf_status.flcerr == 1)
2829                                 /* repeat for some time before giving up */
2830                                 continue;
2831                         else if (hsfsts.hsf_status.flcdone == 0)
2832                                 return ret_val;
2833                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2834         }
2835
2836         return 0;
2837 }
2838
2839 /**
2840  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2841  *  @hw: pointer to the HW structure
2842  *  @data: Pointer to the LED settings
2843  *
2844  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2845  *  settings is all 0's or F's, set the LED default to a valid LED default
2846  *  setting.
2847  **/
2848 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2849 {
2850         s32 ret_val;
2851
2852         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2853         if (ret_val) {
2854                 e_dbg("NVM Read Error\n");
2855                 return ret_val;
2856         }
2857
2858         if (*data == ID_LED_RESERVED_0000 ||
2859             *data == ID_LED_RESERVED_FFFF)
2860                 *data = ID_LED_DEFAULT_ICH8LAN;
2861
2862         return 0;
2863 }
2864
2865 /**
2866  *  e1000_id_led_init_pchlan - store LED configurations
2867  *  @hw: pointer to the HW structure
2868  *
2869  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2870  *  the PHY LED configuration register.
2871  *
2872  *  PCH also does not have an "always on" or "always off" mode which
2873  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2874  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2875  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2876  *  link based on logic in e1000_led_[on|off]_pchlan().
2877  **/
2878 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2879 {
2880         struct e1000_mac_info *mac = &hw->mac;
2881         s32 ret_val;
2882         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2883         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2884         u16 data, i, temp, shift;
2885
2886         /* Get default ID LED modes */
2887         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2888         if (ret_val)
2889                 goto out;
2890
2891         mac->ledctl_default = er32(LEDCTL);
2892         mac->ledctl_mode1 = mac->ledctl_default;
2893         mac->ledctl_mode2 = mac->ledctl_default;
2894
2895         for (i = 0; i < 4; i++) {
2896                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2897                 shift = (i * 5);
2898                 switch (temp) {
2899                 case ID_LED_ON1_DEF2:
2900                 case ID_LED_ON1_ON2:
2901                 case ID_LED_ON1_OFF2:
2902                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2903                         mac->ledctl_mode1 |= (ledctl_on << shift);
2904                         break;
2905                 case ID_LED_OFF1_DEF2:
2906                 case ID_LED_OFF1_ON2:
2907                 case ID_LED_OFF1_OFF2:
2908                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2909                         mac->ledctl_mode1 |= (ledctl_off << shift);
2910                         break;
2911                 default:
2912                         /* Do nothing */
2913                         break;
2914                 }
2915                 switch (temp) {
2916                 case ID_LED_DEF1_ON2:
2917                 case ID_LED_ON1_ON2:
2918                 case ID_LED_OFF1_ON2:
2919                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2920                         mac->ledctl_mode2 |= (ledctl_on << shift);
2921                         break;
2922                 case ID_LED_DEF1_OFF2:
2923                 case ID_LED_ON1_OFF2:
2924                 case ID_LED_OFF1_OFF2:
2925                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2926                         mac->ledctl_mode2 |= (ledctl_off << shift);
2927                         break;
2928                 default:
2929                         /* Do nothing */
2930                         break;
2931                 }
2932         }
2933
2934 out:
2935         return ret_val;
2936 }
2937
2938 /**
2939  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2940  *  @hw: pointer to the HW structure
2941  *
2942  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2943  *  register, so the the bus width is hard coded.
2944  **/
2945 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2946 {
2947         struct e1000_bus_info *bus = &hw->bus;
2948         s32 ret_val;
2949
2950         ret_val = e1000e_get_bus_info_pcie(hw);
2951
2952         /*
2953          * ICH devices are "PCI Express"-ish.  They have
2954          * a configuration space, but do not contain
2955          * PCI Express Capability registers, so bus width
2956          * must be hardcoded.
2957          */
2958         if (bus->width == e1000_bus_width_unknown)
2959                 bus->width = e1000_bus_width_pcie_x1;
2960
2961         return ret_val;
2962 }
2963
2964 /**
2965  *  e1000_reset_hw_ich8lan - Reset the hardware
2966  *  @hw: pointer to the HW structure
2967  *
2968  *  Does a full reset of the hardware which includes a reset of the PHY and
2969  *  MAC.
2970  **/
2971 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2972 {
2973         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2974         u16 reg;
2975         u32 ctrl, icr, kab;
2976         s32 ret_val;
2977
2978         /*
2979          * Prevent the PCI-E bus from sticking if there is no TLP connection
2980          * on the last TLP read/write transaction when MAC is reset.
2981          */
2982         ret_val = e1000e_disable_pcie_master(hw);
2983         if (ret_val)
2984                 e_dbg("PCI-E Master disable polling has failed.\n");
2985
2986         e_dbg("Masking off all interrupts\n");
2987         ew32(IMC, 0xffffffff);
2988
2989         /*
2990          * Disable the Transmit and Receive units.  Then delay to allow
2991          * any pending transactions to complete before we hit the MAC
2992          * with the global reset.
2993          */
2994         ew32(RCTL, 0);
2995         ew32(TCTL, E1000_TCTL_PSP);
2996         e1e_flush();
2997
2998         msleep(10);
2999
3000         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3001         if (hw->mac.type == e1000_ich8lan) {
3002                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3003                 ew32(PBA, E1000_PBA_8K);
3004                 /* Set Packet Buffer Size to 16k. */
3005                 ew32(PBS, E1000_PBS_16K);
3006         }
3007
3008         if (hw->mac.type == e1000_pchlan) {
3009                 /* Save the NVM K1 bit setting*/
3010                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3011                 if (ret_val)
3012                         return ret_val;
3013
3014                 if (reg & E1000_NVM_K1_ENABLE)
3015                         dev_spec->nvm_k1_enabled = true;
3016                 else
3017                         dev_spec->nvm_k1_enabled = false;
3018         }
3019
3020         ctrl = er32(CTRL);
3021
3022         if (!e1000_check_reset_block(hw)) {
3023                 /*
3024                  * Full-chip reset requires MAC and PHY reset at the same
3025                  * time to make sure the interface between MAC and the
3026                  * external PHY is reset.
3027                  */
3028                 ctrl |= E1000_CTRL_PHY_RST;
3029
3030                 /*
3031                  * Gate automatic PHY configuration by hardware on
3032                  * non-managed 82579
3033                  */
3034                 if ((hw->mac.type == e1000_pch2lan) &&
3035                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3036                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3037         }
3038         ret_val = e1000_acquire_swflag_ich8lan(hw);
3039         e_dbg("Issuing a global reset to ich8lan\n");
3040         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3041         msleep(20);
3042
3043         if (!ret_val)
3044                 e1000_release_swflag_ich8lan(hw);
3045
3046         if (ctrl & E1000_CTRL_PHY_RST) {
3047                 ret_val = hw->phy.ops.get_cfg_done(hw);
3048                 if (ret_val)
3049                         goto out;
3050
3051                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3052                 if (ret_val)
3053                         goto out;
3054         }
3055
3056         /*
3057          * For PCH, this write will make sure that any noise
3058          * will be detected as a CRC error and be dropped rather than show up
3059          * as a bad packet to the DMA engine.
3060          */
3061         if (hw->mac.type == e1000_pchlan)
3062                 ew32(CRC_OFFSET, 0x65656565);
3063
3064         ew32(IMC, 0xffffffff);
3065         icr = er32(ICR);
3066
3067         kab = er32(KABGTXD);
3068         kab |= E1000_KABGTXD_BGSQLBIAS;
3069         ew32(KABGTXD, kab);
3070
3071 out:
3072         return ret_val;
3073 }
3074
3075 /**
3076  *  e1000_init_hw_ich8lan - Initialize the hardware
3077  *  @hw: pointer to the HW structure
3078  *
3079  *  Prepares the hardware for transmit and receive by doing the following:
3080  *   - initialize hardware bits
3081  *   - initialize LED identification
3082  *   - setup receive address registers
3083  *   - setup flow control
3084  *   - setup transmit descriptors
3085  *   - clear statistics
3086  **/
3087 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3088 {
3089         struct e1000_mac_info *mac = &hw->mac;
3090         u32 ctrl_ext, txdctl, snoop;
3091         s32 ret_val;
3092         u16 i;
3093
3094         e1000_initialize_hw_bits_ich8lan(hw);
3095
3096         /* Initialize identification LED */
3097         ret_val = mac->ops.id_led_init(hw);
3098         if (ret_val)
3099                 e_dbg("Error initializing identification LED\n");
3100                 /* This is not fatal and we should not stop init due to this */
3101
3102         /* Setup the receive address. */
3103         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3104
3105         /* Zero out the Multicast HASH table */
3106         e_dbg("Zeroing the MTA\n");
3107         for (i = 0; i < mac->mta_reg_count; i++)
3108                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3109
3110         /*
3111          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3112          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
3113          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3114          */
3115         if (hw->phy.type == e1000_phy_82578) {
3116                 hw->phy.ops.read_reg(hw, BM_WUC, &i);
3117                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3118                 if (ret_val)
3119                         return ret_val;
3120         }
3121
3122         /* Setup link and flow control */
3123         ret_val = e1000_setup_link_ich8lan(hw);
3124
3125         /* Set the transmit descriptor write-back policy for both queues */
3126         txdctl = er32(TXDCTL(0));
3127         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3128                  E1000_TXDCTL_FULL_TX_DESC_WB;
3129         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3130                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3131         ew32(TXDCTL(0), txdctl);
3132         txdctl = er32(TXDCTL(1));
3133         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3134                  E1000_TXDCTL_FULL_TX_DESC_WB;
3135         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3136                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3137         ew32(TXDCTL(1), txdctl);
3138
3139         /*
3140          * ICH8 has opposite polarity of no_snoop bits.
3141          * By default, we should use snoop behavior.
3142          */
3143         if (mac->type == e1000_ich8lan)
3144                 snoop = PCIE_ICH8_SNOOP_ALL;
3145         else
3146                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3147         e1000e_set_pcie_no_snoop(hw, snoop);
3148
3149         ctrl_ext = er32(CTRL_EXT);
3150         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3151         ew32(CTRL_EXT, ctrl_ext);
3152
3153         /*
3154          * Clear all of the statistics registers (clear on read).  It is
3155          * important that we do this after we have tried to establish link
3156          * because the symbol error count will increment wildly if there
3157          * is no link.
3158          */
3159         e1000_clear_hw_cntrs_ich8lan(hw);
3160
3161         return 0;
3162 }
3163 /**
3164  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3165  *  @hw: pointer to the HW structure
3166  *
3167  *  Sets/Clears required hardware bits necessary for correctly setting up the
3168  *  hardware for transmit and receive.
3169  **/
3170 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3171 {
3172         u32 reg;
3173
3174         /* Extended Device Control */
3175         reg = er32(CTRL_EXT);
3176         reg |= (1 << 22);
3177         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3178         if (hw->mac.type >= e1000_pchlan)
3179                 reg |= E1000_CTRL_EXT_PHYPDEN;
3180         ew32(CTRL_EXT, reg);
3181
3182         /* Transmit Descriptor Control 0 */
3183         reg = er32(TXDCTL(0));
3184         reg |= (1 << 22);
3185         ew32(TXDCTL(0), reg);
3186
3187         /* Transmit Descriptor Control 1 */
3188         reg = er32(TXDCTL(1));
3189         reg |= (1 << 22);
3190         ew32(TXDCTL(1), reg);
3191
3192         /* Transmit Arbitration Control 0 */
3193         reg = er32(TARC(0));
3194         if (hw->mac.type == e1000_ich8lan)
3195                 reg |= (1 << 28) | (1 << 29);
3196         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3197         ew32(TARC(0), reg);
3198
3199         /* Transmit Arbitration Control 1 */
3200         reg = er32(TARC(1));
3201         if (er32(TCTL) & E1000_TCTL_MULR)
3202                 reg &= ~(1 << 28);
3203         else
3204                 reg |= (1 << 28);
3205         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3206         ew32(TARC(1), reg);
3207
3208         /* Device Status */
3209         if (hw->mac.type == e1000_ich8lan) {
3210                 reg = er32(STATUS);
3211                 reg &= ~(1 << 31);
3212                 ew32(STATUS, reg);
3213         }
3214
3215         /*
3216          * work-around descriptor data corruption issue during nfs v2 udp
3217          * traffic, just disable the nfs filtering capability
3218          */
3219         reg = er32(RFCTL);
3220         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3221         ew32(RFCTL, reg);
3222 }
3223
3224 /**
3225  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3226  *  @hw: pointer to the HW structure
3227  *
3228  *  Determines which flow control settings to use, then configures flow
3229  *  control.  Calls the appropriate media-specific link configuration
3230  *  function.  Assuming the adapter has a valid link partner, a valid link
3231  *  should be established.  Assumes the hardware has previously been reset
3232  *  and the transmitter and receiver are not enabled.
3233  **/
3234 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3235 {
3236         s32 ret_val;
3237
3238         if (e1000_check_reset_block(hw))
3239                 return 0;
3240
3241         /*
3242          * ICH parts do not have a word in the NVM to determine
3243          * the default flow control setting, so we explicitly
3244          * set it to full.
3245          */
3246         if (hw->fc.requested_mode == e1000_fc_default) {
3247                 /* Workaround h/w hang when Tx flow control enabled */
3248                 if (hw->mac.type == e1000_pchlan)
3249                         hw->fc.requested_mode = e1000_fc_rx_pause;
3250                 else
3251                         hw->fc.requested_mode = e1000_fc_full;
3252         }
3253
3254         /*
3255          * Save off the requested flow control mode for use later.  Depending
3256          * on the link partner's capabilities, we may or may not use this mode.
3257          */
3258         hw->fc.current_mode = hw->fc.requested_mode;
3259
3260         e_dbg("After fix-ups FlowControl is now = %x\n",
3261                 hw->fc.current_mode);
3262
3263         /* Continue to configure the copper link. */
3264         ret_val = e1000_setup_copper_link_ich8lan(hw);
3265         if (ret_val)
3266                 return ret_val;
3267
3268         ew32(FCTTV, hw->fc.pause_time);
3269         if ((hw->phy.type == e1000_phy_82578) ||
3270             (hw->phy.type == e1000_phy_82579) ||
3271             (hw->phy.type == e1000_phy_82577)) {
3272                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3273
3274                 ret_val = hw->phy.ops.write_reg(hw,
3275                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
3276                                              hw->fc.pause_time);
3277                 if (ret_val)
3278                         return ret_val;
3279         }
3280
3281         return e1000e_set_fc_watermarks(hw);
3282 }
3283
3284 /**
3285  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3286  *  @hw: pointer to the HW structure
3287  *
3288  *  Configures the kumeran interface to the PHY to wait the appropriate time
3289  *  when polling the PHY, then call the generic setup_copper_link to finish
3290  *  configuring the copper link.
3291  **/
3292 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3293 {
3294         u32 ctrl;
3295         s32 ret_val;
3296         u16 reg_data;
3297
3298         ctrl = er32(CTRL);
3299         ctrl |= E1000_CTRL_SLU;
3300         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3301         ew32(CTRL, ctrl);
3302
3303         /*
3304          * Set the mac to wait the maximum time between each iteration
3305          * and increase the max iterations when polling the phy;
3306          * this fixes erroneous timeouts at 10Mbps.
3307          */
3308         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3309         if (ret_val)
3310                 return ret_val;
3311         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3312                                        &reg_data);
3313         if (ret_val)
3314                 return ret_val;
3315         reg_data |= 0x3F;
3316         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3317                                         reg_data);
3318         if (ret_val)
3319                 return ret_val;
3320
3321         switch (hw->phy.type) {
3322         case e1000_phy_igp_3:
3323                 ret_val = e1000e_copper_link_setup_igp(hw);
3324                 if (ret_val)
3325                         return ret_val;
3326                 break;
3327         case e1000_phy_bm:
3328         case e1000_phy_82578:
3329                 ret_val = e1000e_copper_link_setup_m88(hw);
3330                 if (ret_val)
3331                         return ret_val;
3332                 break;
3333         case e1000_phy_82577:
3334         case e1000_phy_82579:
3335                 ret_val = e1000_copper_link_setup_82577(hw);
3336                 if (ret_val)
3337                         return ret_val;
3338                 break;
3339         case e1000_phy_ife:
3340                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3341                                                &reg_data);
3342                 if (ret_val)
3343                         return ret_val;
3344
3345                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3346
3347                 switch (hw->phy.mdix) {
3348                 case 1:
3349                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3350                         break;
3351                 case 2:
3352                         reg_data |= IFE_PMC_FORCE_MDIX;
3353                         break;
3354                 case 0:
3355                 default:
3356                         reg_data |= IFE_PMC_AUTO_MDIX;
3357                         break;
3358                 }
3359                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3360                                                 reg_data);
3361                 if (ret_val)
3362                         return ret_val;
3363                 break;
3364         default:
3365                 break;
3366         }
3367         return e1000e_setup_copper_link(hw);
3368 }
3369
3370 /**
3371  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3372  *  @hw: pointer to the HW structure
3373  *  @speed: pointer to store current link speed
3374  *  @duplex: pointer to store the current link duplex
3375  *
3376  *  Calls the generic get_speed_and_duplex to retrieve the current link
3377  *  information and then calls the Kumeran lock loss workaround for links at
3378  *  gigabit speeds.
3379  **/
3380 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3381                                           u16 *duplex)
3382 {
3383         s32 ret_val;
3384
3385         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3386         if (ret_val)
3387                 return ret_val;
3388
3389         if ((hw->mac.type == e1000_ich8lan) &&
3390             (hw->phy.type == e1000_phy_igp_3) &&
3391             (*speed == SPEED_1000)) {
3392                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3393         }
3394
3395         return ret_val;
3396 }
3397
3398 /**
3399  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3400  *  @hw: pointer to the HW structure
3401  *
3402  *  Work-around for 82566 Kumeran PCS lock loss:
3403  *  On link status change (i.e. PCI reset, speed change) and link is up and
3404  *  speed is gigabit-
3405  *    0) if workaround is optionally disabled do nothing
3406  *    1) wait 1ms for Kumeran link to come up
3407  *    2) check Kumeran Diagnostic register PCS lock loss bit
3408  *    3) if not set the link is locked (all is good), otherwise...
3409  *    4) reset the PHY
3410  *    5) repeat up to 10 times
3411  *  Note: this is only called for IGP3 copper when speed is 1gb.
3412  **/
3413 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3414 {
3415         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3416         u32 phy_ctrl;
3417         s32 ret_val;
3418         u16 i, data;
3419         bool link;
3420
3421         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3422                 return 0;
3423
3424         /*
3425          * Make sure link is up before proceeding.  If not just return.
3426          * Attempting this while link is negotiating fouled up link
3427          * stability
3428          */
3429         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3430         if (!link)
3431                 return 0;
3432
3433         for (i = 0; i < 10; i++) {
3434                 /* read once to clear */
3435                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3436                 if (ret_val)
3437                         return ret_val;
3438                 /* and again to get new status */
3439                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3440                 if (ret_val)
3441                         return ret_val;
3442
3443                 /* check for PCS lock */
3444                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3445                         return 0;
3446
3447                 /* Issue PHY reset */
3448                 e1000_phy_hw_reset(hw);
3449                 mdelay(5);
3450         }
3451         /* Disable GigE link negotiation */
3452         phy_ctrl = er32(PHY_CTRL);
3453         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3454                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3455         ew32(PHY_CTRL, phy_ctrl);
3456
3457         /*
3458          * Call gig speed drop workaround on Gig disable before accessing
3459          * any PHY registers
3460          */
3461         e1000e_gig_downshift_workaround_ich8lan(hw);
3462
3463         /* unable to acquire PCS lock */
3464         return -E1000_ERR_PHY;
3465 }
3466
3467 /**
3468  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3469  *  @hw: pointer to the HW structure
3470  *  @state: boolean value used to set the current Kumeran workaround state
3471  *
3472  *  If ICH8, set the current Kumeran workaround state (enabled - true
3473  *  /disabled - false).
3474  **/
3475 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3476                                                  bool state)
3477 {
3478         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3479
3480         if (hw->mac.type != e1000_ich8lan) {
3481                 e_dbg("Workaround applies to ICH8 only.\n");
3482                 return;
3483         }
3484
3485         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3486 }
3487
3488 /**
3489  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3490  *  @hw: pointer to the HW structure
3491  *
3492  *  Workaround for 82566 power-down on D3 entry:
3493  *    1) disable gigabit link
3494  *    2) write VR power-down enable
3495  *    3) read it back
3496  *  Continue if successful, else issue LCD reset and repeat
3497  **/
3498 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3499 {
3500         u32 reg;
3501         u16 data;
3502         u8  retry = 0;
3503
3504         if (hw->phy.type != e1000_phy_igp_3)
3505                 return;
3506
3507         /* Try the workaround twice (if needed) */
3508         do {
3509                 /* Disable link */
3510                 reg = er32(PHY_CTRL);
3511                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3512                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3513                 ew32(PHY_CTRL, reg);
3514
3515                 /*
3516                  * Call gig speed drop workaround on Gig disable before
3517                  * accessing any PHY registers
3518                  */
3519                 if (hw->mac.type == e1000_ich8lan)
3520                         e1000e_gig_downshift_workaround_ich8lan(hw);
3521
3522                 /* Write VR power-down enable */
3523                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3524                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3525                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3526
3527                 /* Read it back and test */
3528                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3529                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3530                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3531                         break;
3532
3533                 /* Issue PHY reset and repeat at most one more time */
3534                 reg = er32(CTRL);
3535                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3536                 retry++;
3537         } while (retry);
3538 }
3539
3540 /**
3541  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3542  *  @hw: pointer to the HW structure
3543  *
3544  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3545  *  LPLU, Gig disable, MDIC PHY reset):
3546  *    1) Set Kumeran Near-end loopback
3547  *    2) Clear Kumeran Near-end loopback
3548  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3549  **/
3550 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3551 {
3552         s32 ret_val;
3553         u16 reg_data;
3554
3555         if ((hw->mac.type != e1000_ich8lan) ||
3556             (hw->phy.type != e1000_phy_igp_3))
3557                 return;
3558
3559         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3560                                       &reg_data);
3561         if (ret_val)
3562                 return;
3563         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3564         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3565                                        reg_data);
3566         if (ret_val)
3567                 return;
3568         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3569         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3570                                        reg_data);
3571 }
3572
3573 /**
3574  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3575  *  @hw: pointer to the HW structure
3576  *
3577  *  During S0 to Sx transition, it is possible the link remains at gig
3578  *  instead of negotiating to a lower speed.  Before going to Sx, set
3579  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3580  *  to a lower speed.
3581  *
3582  *  Should only be called for applicable parts.
3583  **/
3584 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3585 {
3586         u32 phy_ctrl;
3587         s32 ret_val;
3588
3589         phy_ctrl = er32(PHY_CTRL);
3590         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3591         ew32(PHY_CTRL, phy_ctrl);
3592
3593         if (hw->mac.type >= e1000_pchlan) {
3594                 e1000_oem_bits_config_ich8lan(hw, true);
3595                 ret_val = hw->phy.ops.acquire(hw);
3596                 if (ret_val)
3597                         return;
3598                 e1000_write_smbus_addr(hw);
3599                 hw->phy.ops.release(hw);
3600         }
3601 }
3602
3603 /**
3604  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3605  *  @hw: pointer to the HW structure
3606  *
3607  *  Return the LED back to the default configuration.
3608  **/
3609 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3610 {
3611         if (hw->phy.type == e1000_phy_ife)
3612                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3613
3614         ew32(LEDCTL, hw->mac.ledctl_default);
3615         return 0;
3616 }
3617
3618 /**
3619  *  e1000_led_on_ich8lan - Turn LEDs on
3620  *  @hw: pointer to the HW structure
3621  *
3622  *  Turn on the LEDs.
3623  **/
3624 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3625 {
3626         if (hw->phy.type == e1000_phy_ife)
3627                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3628                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3629
3630         ew32(LEDCTL, hw->mac.ledctl_mode2);
3631         return 0;
3632 }
3633
3634 /**
3635  *  e1000_led_off_ich8lan - Turn LEDs off
3636  *  @hw: pointer to the HW structure
3637  *
3638  *  Turn off the LEDs.
3639  **/
3640 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3641 {
3642         if (hw->phy.type == e1000_phy_ife)
3643                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3644                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3645
3646         ew32(LEDCTL, hw->mac.ledctl_mode1);
3647         return 0;
3648 }
3649
3650 /**
3651  *  e1000_setup_led_pchlan - Configures SW controllable LED
3652  *  @hw: pointer to the HW structure
3653  *
3654  *  This prepares the SW controllable LED for use.
3655  **/
3656 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3657 {
3658         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3659                                         (u16)hw->mac.ledctl_mode1);
3660 }
3661
3662 /**
3663  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3664  *  @hw: pointer to the HW structure
3665  *
3666  *  Return the LED back to the default configuration.
3667  **/
3668 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3669 {
3670         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3671                                         (u16)hw->mac.ledctl_default);
3672 }
3673
3674 /**
3675  *  e1000_led_on_pchlan - Turn LEDs on
3676  *  @hw: pointer to the HW structure
3677  *
3678  *  Turn on the LEDs.
3679  **/
3680 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3681 {
3682         u16 data = (u16)hw->mac.ledctl_mode2;
3683         u32 i, led;
3684
3685         /*
3686          * If no link, then turn LED on by setting the invert bit
3687          * for each LED that's mode is "link_up" in ledctl_mode2.
3688          */
3689         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3690                 for (i = 0; i < 3; i++) {
3691                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3692                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3693                             E1000_LEDCTL_MODE_LINK_UP)
3694                                 continue;
3695                         if (led & E1000_PHY_LED0_IVRT)
3696                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3697                         else
3698                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3699                 }
3700         }
3701
3702         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3703 }
3704
3705 /**
3706  *  e1000_led_off_pchlan - Turn LEDs off
3707  *  @hw: pointer to the HW structure
3708  *
3709  *  Turn off the LEDs.
3710  **/
3711 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3712 {
3713         u16 data = (u16)hw->mac.ledctl_mode1;
3714         u32 i, led;
3715
3716         /*
3717          * If no link, then turn LED off by clearing the invert bit
3718          * for each LED that's mode is "link_up" in ledctl_mode1.
3719          */
3720         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3721                 for (i = 0; i < 3; i++) {
3722                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3723                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3724                             E1000_LEDCTL_MODE_LINK_UP)
3725                                 continue;
3726                         if (led & E1000_PHY_LED0_IVRT)
3727                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3728                         else
3729                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3730                 }
3731         }
3732
3733         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3734 }
3735
3736 /**
3737  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3738  *  @hw: pointer to the HW structure
3739  *
3740  *  Read appropriate register for the config done bit for completion status
3741  *  and configure the PHY through s/w for EEPROM-less parts.
3742  *
3743  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3744  *  config done bit, so only an error is logged and continues.  If we were
3745  *  to return with error, EEPROM-less silicon would not be able to be reset
3746  *  or change link.
3747  **/
3748 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3749 {
3750         s32 ret_val = 0;
3751         u32 bank = 0;
3752         u32 status;
3753
3754         e1000e_get_cfg_done(hw);
3755
3756         /* Wait for indication from h/w that it has completed basic config */
3757         if (hw->mac.type >= e1000_ich10lan) {
3758                 e1000_lan_init_done_ich8lan(hw);
3759         } else {
3760                 ret_val = e1000e_get_auto_rd_done(hw);
3761                 if (ret_val) {
3762                         /*
3763                          * When auto config read does not complete, do not
3764                          * return with an error. This can happen in situations
3765                          * where there is no eeprom and prevents getting link.
3766                          */
3767                         e_dbg("Auto Read Done did not complete\n");
3768                         ret_val = 0;
3769                 }
3770         }
3771
3772         /* Clear PHY Reset Asserted bit */
3773         status = er32(STATUS);
3774         if (status & E1000_STATUS_PHYRA)
3775                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3776         else
3777                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3778
3779         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3780         if (hw->mac.type <= e1000_ich9lan) {
3781                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3782                     (hw->phy.type == e1000_phy_igp_3)) {
3783                         e1000e_phy_init_script_igp3(hw);
3784                 }
3785         } else {
3786                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3787                         /* Maybe we should do a basic PHY config */
3788                         e_dbg("EEPROM not present\n");
3789                         ret_val = -E1000_ERR_CONFIG;
3790                 }
3791         }
3792
3793         return ret_val;
3794 }
3795
3796 /**
3797  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3798  * @hw: pointer to the HW structure
3799  *
3800  * In the case of a PHY power down to save power, or to turn off link during a
3801  * driver unload, or wake on lan is not enabled, remove the link.
3802  **/
3803 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3804 {
3805         /* If the management interface is not enabled, then power down */
3806         if (!(hw->mac.ops.check_mng_mode(hw) ||
3807               hw->phy.ops.check_reset_block(hw)))
3808                 e1000_power_down_phy_copper(hw);
3809 }
3810
3811 /**
3812  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3813  *  @hw: pointer to the HW structure
3814  *
3815  *  Clears hardware counters specific to the silicon family and calls
3816  *  clear_hw_cntrs_generic to clear all general purpose counters.
3817  **/
3818 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3819 {
3820         u16 phy_data;
3821
3822         e1000e_clear_hw_cntrs_base(hw);
3823
3824         er32(ALGNERRC);
3825         er32(RXERRC);
3826         er32(TNCRS);
3827         er32(CEXTERR);
3828         er32(TSCTC);
3829         er32(TSCTFC);
3830
3831         er32(MGTPRC);
3832         er32(MGTPDC);
3833         er32(MGTPTC);
3834
3835         er32(IAC);
3836         er32(ICRXOC);
3837
3838         /* Clear PHY statistics registers */
3839         if ((hw->phy.type == e1000_phy_82578) ||
3840             (hw->phy.type == e1000_phy_82579) ||
3841             (hw->phy.type == e1000_phy_82577)) {
3842                 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3843                 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3844                 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3845                 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3846                 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3847                 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3848                 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3849                 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3850                 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3851                 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3852                 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3853                 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3854                 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3855                 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3856         }
3857 }
3858
3859 static struct e1000_mac_operations ich8_mac_ops = {
3860         .id_led_init            = e1000e_id_led_init,
3861         /* check_mng_mode dependent on mac type */
3862         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3863         /* cleanup_led dependent on mac type */
3864         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3865         .get_bus_info           = e1000_get_bus_info_ich8lan,
3866         .set_lan_id             = e1000_set_lan_id_single_port,
3867         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3868         /* led_on dependent on mac type */
3869         /* led_off dependent on mac type */
3870         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3871         .reset_hw               = e1000_reset_hw_ich8lan,
3872         .init_hw                = e1000_init_hw_ich8lan,
3873         .setup_link             = e1000_setup_link_ich8lan,
3874         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3875         /* id_led_init dependent on mac type */
3876 };
3877
3878 static struct e1000_phy_operations ich8_phy_ops = {
3879         .acquire                = e1000_acquire_swflag_ich8lan,
3880         .check_reset_block      = e1000_check_reset_block_ich8lan,
3881         .commit                 = NULL,
3882         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3883         .get_cable_length       = e1000e_get_cable_length_igp_2,
3884         .read_reg               = e1000e_read_phy_reg_igp,
3885         .release                = e1000_release_swflag_ich8lan,
3886         .reset                  = e1000_phy_hw_reset_ich8lan,
3887         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3888         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3889         .write_reg              = e1000e_write_phy_reg_igp,
3890 };
3891
3892 static struct e1000_nvm_operations ich8_nvm_ops = {
3893         .acquire                = e1000_acquire_nvm_ich8lan,
3894         .read                   = e1000_read_nvm_ich8lan,
3895         .release                = e1000_release_nvm_ich8lan,
3896         .update                 = e1000_update_nvm_checksum_ich8lan,
3897         .valid_led_default      = e1000_valid_led_default_ich8lan,
3898         .validate               = e1000_validate_nvm_checksum_ich8lan,
3899         .write                  = e1000_write_nvm_ich8lan,
3900 };
3901
3902 struct e1000_info e1000_ich8_info = {
3903         .mac                    = e1000_ich8lan,
3904         .flags                  = FLAG_HAS_WOL
3905                                   | FLAG_IS_ICH
3906                                   | FLAG_RX_CSUM_ENABLED
3907                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3908                                   | FLAG_HAS_AMT
3909                                   | FLAG_HAS_FLASH
3910                                   | FLAG_APME_IN_WUC,
3911         .pba                    = 8,
3912         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3913         .get_variants           = e1000_get_variants_ich8lan,
3914         .mac_ops                = &ich8_mac_ops,
3915         .phy_ops                = &ich8_phy_ops,
3916         .nvm_ops                = &ich8_nvm_ops,
3917 };
3918
3919 struct e1000_info e1000_ich9_info = {
3920         .mac                    = e1000_ich9lan,
3921         .flags                  = FLAG_HAS_JUMBO_FRAMES
3922                                   | FLAG_IS_ICH
3923                                   | FLAG_HAS_WOL
3924                                   | FLAG_RX_CSUM_ENABLED
3925                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3926                                   | FLAG_HAS_AMT
3927                                   | FLAG_HAS_ERT
3928                                   | FLAG_HAS_FLASH
3929                                   | FLAG_APME_IN_WUC,
3930         .pba                    = 10,
3931         .max_hw_frame_size      = DEFAULT_JUMBO,
3932         .get_variants           = e1000_get_variants_ich8lan,
3933         .mac_ops                = &ich8_mac_ops,
3934         .phy_ops                = &ich8_phy_ops,
3935         .nvm_ops                = &ich8_nvm_ops,
3936 };
3937
3938 struct e1000_info e1000_ich10_info = {
3939         .mac                    = e1000_ich10lan,
3940         .flags                  = FLAG_HAS_JUMBO_FRAMES
3941                                   | FLAG_IS_ICH
3942                                   | FLAG_HAS_WOL
3943                                   | FLAG_RX_CSUM_ENABLED
3944                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3945                                   | FLAG_HAS_AMT
3946                                   | FLAG_HAS_ERT
3947                                   | FLAG_HAS_FLASH
3948                                   | FLAG_APME_IN_WUC,
3949         .pba                    = 10,
3950         .max_hw_frame_size      = DEFAULT_JUMBO,
3951         .get_variants           = e1000_get_variants_ich8lan,
3952         .mac_ops                = &ich8_mac_ops,
3953         .phy_ops                = &ich8_phy_ops,
3954         .nvm_ops                = &ich8_nvm_ops,
3955 };
3956
3957 struct e1000_info e1000_pch_info = {
3958         .mac                    = e1000_pchlan,
3959         .flags                  = FLAG_IS_ICH
3960                                   | FLAG_HAS_WOL
3961                                   | FLAG_RX_CSUM_ENABLED
3962                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3963                                   | FLAG_HAS_AMT
3964                                   | FLAG_HAS_FLASH
3965                                   | FLAG_HAS_JUMBO_FRAMES
3966                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3967                                   | FLAG_APME_IN_WUC,
3968         .flags2                 = FLAG2_HAS_PHY_STATS,
3969         .pba                    = 26,
3970         .max_hw_frame_size      = 4096,
3971         .get_variants           = e1000_get_variants_ich8lan,
3972         .mac_ops                = &ich8_mac_ops,
3973         .phy_ops                = &ich8_phy_ops,
3974         .nvm_ops                = &ich8_nvm_ops,
3975 };
3976
3977 struct e1000_info e1000_pch2_info = {
3978         .mac                    = e1000_pch2lan,
3979         .flags                  = FLAG_IS_ICH
3980                                   | FLAG_HAS_WOL
3981                                   | FLAG_RX_CSUM_ENABLED
3982                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3983                                   | FLAG_HAS_AMT
3984                                   | FLAG_HAS_FLASH
3985                                   | FLAG_HAS_JUMBO_FRAMES
3986                                   | FLAG_APME_IN_WUC,
3987         .flags2                 = FLAG2_HAS_PHY_STATS
3988                                   | FLAG2_HAS_EEE,
3989         .pba                    = 18,
3990         .max_hw_frame_size      = DEFAULT_JUMBO,
3991         .get_variants           = e1000_get_variants_ich8lan,
3992         .mac_ops                = &ich8_mac_ops,
3993         .phy_ops                = &ich8_phy_ops,
3994         .nvm_ops                = &ich8_nvm_ops,
3995 };