drivers/net/bnx2x_hsi.h

   1 /* bnx2x_hsi.h: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2010 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10 struct license_key {
  11         u32 reserved[6];
  12
  13 #if defined(__BIG_ENDIAN)
  14         u16 max_iscsi_init_conn;
  15         u16 max_iscsi_trgt_conn;
  16 #elif defined(__LITTLE_ENDIAN)
  17         u16 max_iscsi_trgt_conn;
  18         u16 max_iscsi_init_conn;
  19 #endif
  20
  21         u32 reserved_a[6];
  22 };
  23
  24
  25 #define PORT_0                          0
  26 #define PORT_1                          1
  27 #define PORT_MAX                        2
  28
  29 /****************************************************************************
  30  * Shared HW configuration                                                  *
  31  ****************************************************************************/
  32 struct shared_hw_cfg {                                   /* NVRAM Offset */
  33         /* Up to 16 bytes of NULL-terminated string */
  34         u8  part_num[16];                                       /* 0x104 */
  35
  36         u32 config;                                             /* 0x114 */
  37 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
  38 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT            0
  39 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V             0x00000000
  40 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V             0x00000001
  41 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
  42
  43 #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
  44
  45 #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
  46
  47 #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
  48 #define SHARED_HW_CFG_MFW_SELECT_SHIFT              8
  49         /* Whatever MFW found in NVM
  50            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
  51 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT            0x00000000
  52 #define SHARED_HW_CFG_MFW_SELECT_NC_SI              0x00000100
  53 #define SHARED_HW_CFG_MFW_SELECT_UMP                0x00000200
  54 #define SHARED_HW_CFG_MFW_SELECT_IPMI               0x00000300
  55         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
  56           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
  57 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI   0x00000400
  58         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
  59           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
  60 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI     0x00000500
  61         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
  62           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
  63 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP    0x00000600
  64
  65 #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
  66 #define SHARED_HW_CFG_LED_MODE_SHIFT                16
  67 #define SHARED_HW_CFG_LED_MAC1                      0x00000000
  68 #define SHARED_HW_CFG_LED_PHY1                      0x00010000
  69 #define SHARED_HW_CFG_LED_PHY2                      0x00020000
  70 #define SHARED_HW_CFG_LED_PHY3                      0x00030000
  71 #define SHARED_HW_CFG_LED_MAC2                      0x00040000
  72 #define SHARED_HW_CFG_LED_PHY4                      0x00050000
  73 #define SHARED_HW_CFG_LED_PHY5                      0x00060000
  74 #define SHARED_HW_CFG_LED_PHY6                      0x00070000
  75 #define SHARED_HW_CFG_LED_MAC3                      0x00080000
  76 #define SHARED_HW_CFG_LED_PHY7                      0x00090000
  77 #define SHARED_HW_CFG_LED_PHY9                      0x000a0000
  78 #define SHARED_HW_CFG_LED_PHY11                     0x000b0000
  79 #define SHARED_HW_CFG_LED_MAC4                      0x000c0000
  80 #define SHARED_HW_CFG_LED_PHY8                      0x000d0000
  81
  82 #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
  83 #define SHARED_HW_CFG_AN_ENABLE_SHIFT               24
  84 #define SHARED_HW_CFG_AN_ENABLE_CL37                0x01000000
  85 #define SHARED_HW_CFG_AN_ENABLE_CL73                0x02000000
  86 #define SHARED_HW_CFG_AN_ENABLE_BAM                 0x04000000
  87 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION  0x08000000
  88 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
  89 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY          0x20000000
  90
  91         u32 config2;                                            /* 0x118 */
  92         /* one time auto detect grace period (in sec) */
  93 #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
  94 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT            0
  95
  96 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
  97
  98         /* The default value for the core clock is 250MHz and it is
  99            achieved by setting the clock change to 4 */
 100 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
 101 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT            9
 102
 103 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ           0x00000000
 104 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ           0x00001000
 105
 106 #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
 107
 108         /*  The fan failure mechanism is usually related to the PHY type
 109           since the power consumption of the board is determined by the PHY.
 110           Currently, fan is required for most designs with SFX7101, BCM8727
 111           and BCM8481. If a fan is not required for a board which uses one
 112           of those PHYs, this field should be set to "Disabled". If a fan is
 113           required for a different PHY type, this option should be set to
 114           "Enabled".
 115           The fan failure indication is expected on
 116           SPIO5 */
 117 #define SHARED_HW_CFG_FAN_FAILURE_MASK                        0x00180000
 118 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT                       19
 119 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE                    0x00000000
 120 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED                    0x00080000
 121 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED                     0x00100000
 122
 123         u32 power_dissipated;                                   /* 0x11c */
 124 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
 125 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT           24
 126
 127 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
 128 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT        16
 129 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE      0x00000000
 130 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT         0x00010000
 131 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT        0x00020000
 132 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT       0x00030000
 133
 134         u32 ump_nc_si_config;                                   /* 0x120 */
 135 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
 136 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT      0
 137 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC        0x00000000
 138 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY        0x00000001
 139 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII        0x00000000
 140 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII       0x00000002
 141
 142 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
 143 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT      8
 144
 145 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
 146 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT  16
 147 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE   0x00000000
 148 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
 149
 150         u32 board;                                              /* 0x124 */
 151 #define SHARED_HW_CFG_BOARD_REV_MASK                0x00FF0000
 152 #define SHARED_HW_CFG_BOARD_REV_SHIFT               16
 153
 154 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0F000000
 155 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT         24
 156
 157 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xF0000000
 158 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT         28
 159
 160         u32 reserved;                                           /* 0x128 */
 161
 162 };
 163
 164
 165 /****************************************************************************
 166  * Port HW configuration                                                    *
 167  ****************************************************************************/
 168 struct port_hw_cfg {                        /* port 0: 0x12c  port 1: 0x2bc */
 169
 170         u32 pci_id;
 171 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
 172 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
 173
 174         u32 pci_sub_id;
 175 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
 176 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
 177
 178         u32 power_dissipated;
 179 #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
 180 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT              24
 181 #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
 182 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT              16
 183 #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
 184 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT              8
 185 #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
 186 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT              0
 187
 188         u32 power_consumed;
 189 #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
 190 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT             24
 191 #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
 192 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT             16
 193 #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
 194 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT             8
 195 #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
 196 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT             0
 197
 198         u32 mac_upper;
 199 #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
 200 #define PORT_HW_CFG_UPPERMAC_SHIFT                  0
 201         u32 mac_lower;
 202
 203         u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
 204         u32 iscsi_mac_lower;
 205
 206         u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
 207         u32 rdma_mac_lower;
 208
 209         u32 serdes_config;
 210 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK           0x0000FFFF
 211 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT          0
 212
 213 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK              0xFFFF0000
 214 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT             16
 215
 216
 217         u32 Reserved0[16];                                  /* 0x158 */
 218
 219         /*  for external PHY, or forced mode or during AN */
 220         u16 xgxs_config_rx[4];                              /* 0x198 */
 221
 222         u16 xgxs_config_tx[4];                              /* 0x1A0 */
 223
 224         u32 Reserved1[64];                                  /* 0x1A8 */
 225
 226         u32 lane_config;
 227 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
 228 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT             0
 229 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
 230 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT          0
 231 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
 232 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT          8
 233 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
 234 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT      14
 235         /* AN and forced */
 236 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123          0x00001b1b
 237         /* forced only */
 238 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210          0x00001be4
 239         /* forced only */
 240 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120          0x0000d8d8
 241         /* forced only */
 242 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210          0x0000e4e4
 243
 244         u32 external_phy_config;
 245 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
 246 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT       24
 247 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT      0x00000000
 248 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482     0x01000000
 249 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN    0xff000000
 250
 251 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
 252 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT       16
 253
 254 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
 255 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT         8
 256 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT        0x00000000
 257 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071       0x00000100
 258 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072       0x00000200
 259 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073       0x00000300
 260 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705       0x00000400
 261 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706       0x00000500
 262 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726       0x00000600
 263 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481       0x00000700
 264 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101       0x00000800
 265 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727       0x00000900
 266 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC   0x00000a00
 267 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823      0x00000b00
 268 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE       0x0000fd00
 269 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN      0x0000ff00
 270
 271 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
 272 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT         0
 273
 274         u32 speed_capability_mask;
 275 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
 276 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT       16
 277 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL    0x00010000
 278 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF    0x00020000
 279 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF   0x00040000
 280 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL   0x00080000
 281 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G          0x00100000
 282 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G        0x00200000
 283 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G         0x00400000
 284 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G         0x00800000
 285 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G       0x01000000
 286 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G         0x02000000
 287 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G         0x04000000
 288 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G         0x08000000
 289 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED    0xf0000000
 290
 291 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
 292 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT       0
 293 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL    0x00000001
 294 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF    0x00000002
 295 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF   0x00000004
 296 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL   0x00000008
 297 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G          0x00000010
 298 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G        0x00000020
 299 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G         0x00000040
 300 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G         0x00000080
 301 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G       0x00000100
 302 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G         0x00000200
 303 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G         0x00000400
 304 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G         0x00000800
 305 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED    0x0000f000
 306
 307         u32 reserved[2];
 308
 309 };
 310
 311
 312 /****************************************************************************
 313  * Shared Feature configuration                                             *
 314  ****************************************************************************/
 315 struct shared_feat_cfg {                                 /* NVRAM Offset */
 316
 317         u32 config;                                             /* 0x450 */
 318 #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
 319
 320         /*  Use the values from options 47 and 48 instead of the HW default
 321           values */
 322 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED     0x00000000
 323 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED      0x00000002
 324
 325 #define SHARED_FEATURE_MF_MODE_DISABLED             0x00000100
 326
 327 };
 328
 329
 330 /****************************************************************************
 331  * Port Feature configuration                                               *
 332  ****************************************************************************/
 333 struct port_feat_cfg {                      /* port 0: 0x454  port 1: 0x4c8 */
 334
 335         u32 config;
 336 #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
 337 #define PORT_FEATURE_BAR1_SIZE_SHIFT                0
 338 #define PORT_FEATURE_BAR1_SIZE_DISABLED             0x00000000
 339 #define PORT_FEATURE_BAR1_SIZE_64K                  0x00000001
 340 #define PORT_FEATURE_BAR1_SIZE_128K                 0x00000002
 341 #define PORT_FEATURE_BAR1_SIZE_256K                 0x00000003
 342 #define PORT_FEATURE_BAR1_SIZE_512K                 0x00000004
 343 #define PORT_FEATURE_BAR1_SIZE_1M                   0x00000005
 344 #define PORT_FEATURE_BAR1_SIZE_2M                   0x00000006
 345 #define PORT_FEATURE_BAR1_SIZE_4M                   0x00000007
 346 #define PORT_FEATURE_BAR1_SIZE_8M                   0x00000008
 347 #define PORT_FEATURE_BAR1_SIZE_16M                  0x00000009
 348 #define PORT_FEATURE_BAR1_SIZE_32M                  0x0000000a
 349 #define PORT_FEATURE_BAR1_SIZE_64M                  0x0000000b
 350 #define PORT_FEATURE_BAR1_SIZE_128M                 0x0000000c
 351 #define PORT_FEATURE_BAR1_SIZE_256M                 0x0000000d
 352 #define PORT_FEATURE_BAR1_SIZE_512M                 0x0000000e
 353 #define PORT_FEATURE_BAR1_SIZE_1G                   0x0000000f
 354 #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
 355 #define PORT_FEATURE_BAR2_SIZE_SHIFT                4
 356 #define PORT_FEATURE_BAR2_SIZE_DISABLED             0x00000000
 357 #define PORT_FEATURE_BAR2_SIZE_64K                  0x00000010
 358 #define PORT_FEATURE_BAR2_SIZE_128K                 0x00000020
 359 #define PORT_FEATURE_BAR2_SIZE_256K                 0x00000030
 360 #define PORT_FEATURE_BAR2_SIZE_512K                 0x00000040
 361 #define PORT_FEATURE_BAR2_SIZE_1M                   0x00000050
 362 #define PORT_FEATURE_BAR2_SIZE_2M                   0x00000060
 363 #define PORT_FEATURE_BAR2_SIZE_4M                   0x00000070
 364 #define PORT_FEATURE_BAR2_SIZE_8M                   0x00000080
 365 #define PORT_FEATURE_BAR2_SIZE_16M                  0x00000090
 366 #define PORT_FEATURE_BAR2_SIZE_32M                  0x000000a0
 367 #define PORT_FEATURE_BAR2_SIZE_64M                  0x000000b0
 368 #define PORT_FEATURE_BAR2_SIZE_128M                 0x000000c0
 369 #define PORT_FEATURE_BAR2_SIZE_256M                 0x000000d0
 370 #define PORT_FEATURE_BAR2_SIZE_512M                 0x000000e0
 371 #define PORT_FEATURE_BAR2_SIZE_1G                   0x000000f0
 372 #define PORT_FEATURE_EN_SIZE_MASK                   0x07000000
 373 #define PORT_FEATURE_EN_SIZE_SHIFT                  24
 374 #define PORT_FEATURE_WOL_ENABLED                    0x01000000
 375 #define PORT_FEATURE_MBA_ENABLED                    0x02000000
 376 #define PORT_FEATURE_MFW_ENABLED                    0x04000000
 377
 378         /* Reserved bits: 28-29 */
 379         /*  Check the optic vendor via i2c against a list of approved modules
 380           in a separate nvram image */
 381 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK                   0xE0000000
 382 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT                  29
 383 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT         0x00000000
 384 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER       0x20000000
 385 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG            0x40000000
 386 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN             0x60000000
 387
 388
 389         u32 wol_config;
 390         /* Default is used when driver sets to "auto" mode */
 391 #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
 392 #define PORT_FEATURE_WOL_DEFAULT_SHIFT              0
 393 #define PORT_FEATURE_WOL_DEFAULT_DISABLE            0x00000000
 394 #define PORT_FEATURE_WOL_DEFAULT_MAGIC              0x00000001
 395 #define PORT_FEATURE_WOL_DEFAULT_ACPI               0x00000002
 396 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI     0x00000003
 397 #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
 398 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
 399 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
 400
 401         u32 mba_config;
 402 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000003
 403 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT      0
 404 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE        0x00000000
 405 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL        0x00000001
 406 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP      0x00000002
 407 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB     0x00000003
 408 #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
 409 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
 410 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
 411 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S              0x00000000
 412 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B              0x00000800
 413 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
 414 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT         12
 415 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED      0x00000000
 416 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K            0x00001000
 417 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K            0x00002000
 418 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K            0x00003000
 419 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K           0x00004000
 420 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K           0x00005000
 421 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K           0x00006000
 422 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K          0x00007000
 423 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K          0x00008000
 424 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K          0x00009000
 425 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M            0x0000a000
 426 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M            0x0000b000
 427 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M            0x0000c000
 428 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M            0x0000d000
 429 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M           0x0000e000
 430 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M           0x0000f000
 431 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
 432 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT          20
 433 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
 434 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT       24
 435 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO        0x00000000
 436 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS         0x01000000
 437 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H      0x02000000
 438 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H      0x03000000
 439 #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
 440 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT           26
 441 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO            0x00000000
 442 #define PORT_FEATURE_MBA_LINK_SPEED_10HD            0x04000000
 443 #define PORT_FEATURE_MBA_LINK_SPEED_10FD            0x08000000
 444 #define PORT_FEATURE_MBA_LINK_SPEED_100HD           0x0c000000
 445 #define PORT_FEATURE_MBA_LINK_SPEED_100FD           0x10000000
 446 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS           0x14000000
 447 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS         0x18000000
 448 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4      0x1c000000
 449 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4      0x20000000
 450 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR       0x24000000
 451 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS          0x28000000
 452 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS        0x2c000000
 453 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS          0x30000000
 454 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS          0x34000000
 455 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS          0x38000000
 456
 457         u32 bmc_config;
 458 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT      0x00000000
 459 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN           0x00000001
 460
 461         u32 mba_vlan_cfg;
 462 #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
 463 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT             0
 464 #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
 465
 466         u32 resource_cfg;
 467 #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
 468 #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
 469 #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
 470 #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
 471 #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
 472
 473         u32 smbus_config;
 474         /* Obsolete */
 475 #define PORT_FEATURE_SMBUS_EN                       0x00000001
 476 #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
 477 #define PORT_FEATURE_SMBUS_ADDR_SHIFT               1
 478
 479         u32 reserved1;
 480
 481         u32 link_config;    /* Used as HW defaults for the driver */
 482 #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
 483 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT         24
 484         /* (forced) low speed switch (< 10G) */
 485 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH           0x00000000
 486         /* (forced) high speed switch (>= 10G) */
 487 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH          0x01000000
 488 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT         0x02000000
 489 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT     0x03000000
 490
 491 #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
 492 #define PORT_FEATURE_LINK_SPEED_SHIFT               16
 493 #define PORT_FEATURE_LINK_SPEED_AUTO                0x00000000
 494 #define PORT_FEATURE_LINK_SPEED_10M_FULL            0x00010000
 495 #define PORT_FEATURE_LINK_SPEED_10M_HALF            0x00020000
 496 #define PORT_FEATURE_LINK_SPEED_100M_HALF           0x00030000
 497 #define PORT_FEATURE_LINK_SPEED_100M_FULL           0x00040000
 498 #define PORT_FEATURE_LINK_SPEED_1G                  0x00050000
 499 #define PORT_FEATURE_LINK_SPEED_2_5G                0x00060000
 500 #define PORT_FEATURE_LINK_SPEED_10G_CX4             0x00070000
 501 #define PORT_FEATURE_LINK_SPEED_10G_KX4             0x00080000
 502 #define PORT_FEATURE_LINK_SPEED_10G_KR              0x00090000
 503 #define PORT_FEATURE_LINK_SPEED_12G                 0x000a0000
 504 #define PORT_FEATURE_LINK_SPEED_12_5G               0x000b0000
 505 #define PORT_FEATURE_LINK_SPEED_13G                 0x000c0000
 506 #define PORT_FEATURE_LINK_SPEED_15G                 0x000d0000
 507 #define PORT_FEATURE_LINK_SPEED_16G                 0x000e0000
 508
 509 #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
 510 #define PORT_FEATURE_FLOW_CONTROL_SHIFT             8
 511 #define PORT_FEATURE_FLOW_CONTROL_AUTO              0x00000000
 512 #define PORT_FEATURE_FLOW_CONTROL_TX                0x00000100
 513 #define PORT_FEATURE_FLOW_CONTROL_RX                0x00000200
 514 #define PORT_FEATURE_FLOW_CONTROL_BOTH              0x00000300
 515 #define PORT_FEATURE_FLOW_CONTROL_NONE              0x00000400
 516
 517         /* The default for MCP link configuration,
 518            uses the same defines as link_config */
 519         u32 mfw_wol_link_cfg;
 520
 521         u32 reserved[19];
 522
 523 };
 524
 525
 526 /****************************************************************************
 527  * Device Information                                                       *
 528  ****************************************************************************/
 529 struct shm_dev_info {                                               /* size */
 530
 531         u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
 532
 533         struct shared_hw_cfg     shared_hw_config;                    /* 40 */
 534
 535         struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
 536
 537         struct shared_feat_cfg   shared_feature_config;                /* 4 */
 538
 539         struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
 540
 541 };
 542
 543
 544 #define FUNC_0                          0
 545 #define FUNC_1                          1
 546 #define FUNC_2                          2
 547 #define FUNC_3                          3
 548 #define FUNC_4                          4
 549 #define FUNC_5                          5
 550 #define FUNC_6                          6
 551 #define FUNC_7                          7
 552 #define E1_FUNC_MAX                     2
 553 #define E1H_FUNC_MAX                    8
 554
 555 #define VN_0                            0
 556 #define VN_1                            1
 557 #define VN_2                            2
 558 #define VN_3                            3
 559 #define E1VN_MAX                        1
 560 #define E1HVN_MAX                       4
 561
 562
 563 /* This value (in milliseconds) determines the frequency of the driver
 564  * issuing the PULSE message code.  The firmware monitors this periodic
 565  * pulse to determine when to switch to an OS-absent mode. */
 566 #define DRV_PULSE_PERIOD_MS             250
 567
 568 /* This value (in milliseconds) determines how long the driver should
 569  * wait for an acknowledgement from the firmware before timing out.  Once
 570  * the firmware has timed out, the driver will assume there is no firmware
 571  * running and there won't be any firmware-driver synchronization during a
 572  * driver reset. */
 573 #define FW_ACK_TIME_OUT_MS              5000
 574
 575 #define FW_ACK_POLL_TIME_MS             1
 576
 577 #define FW_ACK_NUM_OF_POLL      (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
 578
 579 /* LED Blink rate that will achieve ~15.9Hz */
 580 #define LED_BLINK_RATE_VAL              480
 581
 582 /****************************************************************************
 583  * Driver <-> FW Mailbox                                                    *
 584  ****************************************************************************/
 585 struct drv_port_mb {
 586
 587         u32 link_status;
 588         /* Driver should update this field on any link change event */
 589
 590 #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
 591 #define LINK_STATUS_LINK_UP                             0x00000001
 592 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
 593 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
 594 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
 595 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
 596 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
 597 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
 598 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
 599 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
 600 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
 601 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
 602 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
 603 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
 604 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
 605 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
 606 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
 607 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD             (11<<1)
 608 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD             (11<<1)
 609 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD           (12<<1)
 610 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD           (12<<1)
 611 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD             (13<<1)
 612 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD             (13<<1)
 613 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD             (14<<1)
 614 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD             (14<<1)
 615 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD             (15<<1)
 616 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD             (15<<1)
 617
 618 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
 619 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
 620
 621 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
 622 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
 623 #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
 624
 625 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
 626 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
 627 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
 628 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
 629 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
 630 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
 631 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
 632
 633 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
 634 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
 635
 636 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
 637 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
 638
 639 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
 640 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
 641 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
 642 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
 643 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
 644
 645 #define LINK_STATUS_SERDES_LINK                         0x00100000
 646
 647 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
 648 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
 649 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
 650 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE         0x01000000
 651 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE       0x02000000
 652 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE         0x04000000
 653 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE         0x08000000
 654 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE         0x10000000
 655
 656         u32 port_stx;
 657
 658         u32 stat_nig_timer;
 659
 660         /* MCP firmware does not use this field */
 661         u32 ext_phy_fw_version;
 662
 663 };
 664
 665
 666 struct drv_func_mb {
 667
 668         u32 drv_mb_header;
 669 #define DRV_MSG_CODE_MASK                               0xffff0000
 670 #define DRV_MSG_CODE_LOAD_REQ                           0x10000000
 671 #define DRV_MSG_CODE_LOAD_DONE                          0x11000000
 672 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN                  0x20000000
 673 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS                 0x20010000
 674 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP                 0x20020000
 675 #define DRV_MSG_CODE_UNLOAD_DONE                        0x21000000
 676 #define DRV_MSG_CODE_DCC_OK                             0x30000000
 677 #define DRV_MSG_CODE_DCC_FAILURE                        0x31000000
 678 #define DRV_MSG_CODE_DIAG_ENTER_REQ                     0x50000000
 679 #define DRV_MSG_CODE_DIAG_EXIT_REQ                      0x60000000
 680 #define DRV_MSG_CODE_VALIDATE_KEY                       0x70000000
 681 #define DRV_MSG_CODE_GET_CURR_KEY                       0x80000000
 682 #define DRV_MSG_CODE_GET_UPGRADE_KEY                    0x81000000
 683 #define DRV_MSG_CODE_GET_MANUF_KEY                      0x82000000
 684 #define DRV_MSG_CODE_LOAD_L2B_PRAM                      0x90000000
 685         /*
 686          * The optic module verification commands require bootcode
 687          * v5.0.6 or later
 688          */
 689 #define DRV_MSG_CODE_VRFY_OPT_MDL                       0xa0000000
 690 #define REQ_BC_VER_4_VRFY_OPT_MDL                       0x00050006
 691
 692 #define BIOS_MSG_CODE_LIC_CHALLENGE                     0xff010000
 693 #define BIOS_MSG_CODE_LIC_RESPONSE                      0xff020000
 694 #define BIOS_MSG_CODE_VIRT_MAC_PRIM                     0xff030000
 695 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI                    0xff040000
 696
 697 #define DRV_MSG_SEQ_NUMBER_MASK                         0x0000ffff
 698
 699         u32 drv_mb_param;
 700
 701         u32 fw_mb_header;
 702 #define FW_MSG_CODE_MASK                                0xffff0000
 703 #define FW_MSG_CODE_DRV_LOAD_COMMON                     0x10100000
 704 #define FW_MSG_CODE_DRV_LOAD_PORT                       0x10110000
 705 #define FW_MSG_CODE_DRV_LOAD_FUNCTION                   0x10120000
 706 #define FW_MSG_CODE_DRV_LOAD_REFUSED                    0x10200000
 707 #define FW_MSG_CODE_DRV_LOAD_DONE                       0x11100000
 708 #define FW_MSG_CODE_DRV_UNLOAD_COMMON                   0x20100000
 709 #define FW_MSG_CODE_DRV_UNLOAD_PORT                     0x20110000
 710 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION                 0x20120000
 711 #define FW_MSG_CODE_DRV_UNLOAD_DONE                     0x21100000
 712 #define FW_MSG_CODE_DCC_DONE                            0x30100000
 713 #define FW_MSG_CODE_DIAG_ENTER_DONE                     0x50100000
 714 #define FW_MSG_CODE_DIAG_REFUSE                         0x50200000
 715 #define FW_MSG_CODE_DIAG_EXIT_DONE                      0x60100000
 716 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS                0x70100000
 717 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE                0x70200000
 718 #define FW_MSG_CODE_GET_KEY_DONE                        0x80100000
 719 #define FW_MSG_CODE_NO_KEY                              0x80f00000
 720 #define FW_MSG_CODE_LIC_INFO_NOT_READY                  0x80f80000
 721 #define FW_MSG_CODE_L2B_PRAM_LOADED                     0x90100000
 722 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE             0x90210000
 723 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE             0x90220000
 724 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE             0x90230000
 725 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE             0x90240000
 726 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS                0xa0100000
 727 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG              0xa0200000
 728 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED             0xa0300000
 729
 730 #define FW_MSG_CODE_LIC_CHALLENGE                       0xff010000
 731 #define FW_MSG_CODE_LIC_RESPONSE                        0xff020000
 732 #define FW_MSG_CODE_VIRT_MAC_PRIM                       0xff030000
 733 #define FW_MSG_CODE_VIRT_MAC_ISCSI                      0xff040000
 734
 735 #define FW_MSG_SEQ_NUMBER_MASK                          0x0000ffff
 736
 737         u32 fw_mb_param;
 738
 739         u32 drv_pulse_mb;
 740 #define DRV_PULSE_SEQ_MASK                              0x00007fff
 741 #define DRV_PULSE_SYSTEM_TIME_MASK                      0xffff0000
 742         /* The system time is in the format of
 743          * (year-2001)*12*32 + month*32 + day. */
 744 #define DRV_PULSE_ALWAYS_ALIVE                          0x00008000
 745         /* Indicate to the firmware not to go into the
 746          * OS-absent when it is not getting driver pulse.
 747          * This is used for debugging as well for PXE(MBA). */
 748
 749         u32 mcp_pulse_mb;
 750 #define MCP_PULSE_SEQ_MASK                              0x00007fff
 751 #define MCP_PULSE_ALWAYS_ALIVE                          0x00008000
 752         /* Indicates to the driver not to assert due to lack
 753          * of MCP response */
 754 #define MCP_EVENT_MASK                                  0xffff0000
 755 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ                0x00010000
 756
 757         u32 iscsi_boot_signature;
 758         u32 iscsi_boot_block_offset;
 759
 760         u32 drv_status;
 761 #define DRV_STATUS_PMF                                  0x00000001
 762
 763 #define DRV_STATUS_DCC_EVENT_MASK                       0x0000ff00
 764 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF                0x00000100
 765 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION             0x00000200
 766 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS               0x00000400
 767 #define DRV_STATUS_DCC_RESERVED1                        0x00000800
 768 #define DRV_STATUS_DCC_SET_PROTOCOL                     0x00001000
 769 #define DRV_STATUS_DCC_SET_PRIORITY                     0x00002000
 770
 771         u32 virt_mac_upper;
 772 #define VIRT_MAC_SIGN_MASK                              0xffff0000
 773 #define VIRT_MAC_SIGNATURE                              0x564d0000
 774         u32 virt_mac_lower;
 775
 776 };
 777
 778
 779 /****************************************************************************
 780  * Management firmware state                                                *
 781  ****************************************************************************/
 782 /* Allocate 440 bytes for management firmware */
 783 #define MGMTFW_STATE_WORD_SIZE                              110
 784
 785 struct mgmtfw_state {
 786         u32 opaque[MGMTFW_STATE_WORD_SIZE];
 787 };
 788
 789
 790 /****************************************************************************
 791  * Multi-Function configuration                                             *
 792  ****************************************************************************/
 793 struct shared_mf_cfg {
 794
 795         u32 clp_mb;
 796 #define SHARED_MF_CLP_SET_DEFAULT                   0x00000000
 797         /* set by CLP */
 798 #define SHARED_MF_CLP_EXIT                          0x00000001
 799         /* set by MCP */
 800 #define SHARED_MF_CLP_EXIT_DONE                     0x00010000
 801
 802 };
 803
 804 struct port_mf_cfg {
 805
 806         u32 dynamic_cfg;        /* device control channel */
 807 #define PORT_MF_CFG_E1HOV_TAG_MASK                  0x0000ffff
 808 #define PORT_MF_CFG_E1HOV_TAG_SHIFT                 0
 809 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT               PORT_MF_CFG_E1HOV_TAG_MASK
 810
 811         u32 reserved[3];
 812
 813 };
 814
 815 struct func_mf_cfg {
 816
 817         u32 config;
 818         /* E/R/I/D */
 819         /* function 0 of each port cannot be hidden */
 820 #define FUNC_MF_CFG_FUNC_HIDE                       0x00000001
 821
 822 #define FUNC_MF_CFG_PROTOCOL_MASK                   0x00000007
 823 #define FUNC_MF_CFG_PROTOCOL_ETHERNET               0x00000002
 824 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA     0x00000004
 825 #define FUNC_MF_CFG_PROTOCOL_ISCSI                  0x00000006
 826 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
 827         FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
 828
 829 #define FUNC_MF_CFG_FUNC_DISABLED                   0x00000008
 830
 831         /* PRI */
 832         /* 0 - low priority, 3 - high priority */
 833 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK          0x00000300
 834 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT         8
 835 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT       0x00000000
 836
 837         /* MINBW, MAXBW */
 838         /* value range - 0..100, increments in 100Mbps */
 839 #define FUNC_MF_CFG_MIN_BW_MASK                     0x00ff0000
 840 #define FUNC_MF_CFG_MIN_BW_SHIFT                    16
 841 #define FUNC_MF_CFG_MIN_BW_DEFAULT                  0x00000000
 842 #define FUNC_MF_CFG_MAX_BW_MASK                     0xff000000
 843 #define FUNC_MF_CFG_MAX_BW_SHIFT                    24
 844 #define FUNC_MF_CFG_MAX_BW_DEFAULT                  0x64000000
 845
 846         u32 mac_upper;          /* MAC */
 847 #define FUNC_MF_CFG_UPPERMAC_MASK                   0x0000ffff
 848 #define FUNC_MF_CFG_UPPERMAC_SHIFT                  0
 849 #define FUNC_MF_CFG_UPPERMAC_DEFAULT                FUNC_MF_CFG_UPPERMAC_MASK
 850         u32 mac_lower;
 851 #define FUNC_MF_CFG_LOWERMAC_DEFAULT                0xffffffff
 852
 853         u32 e1hov_tag;  /* VNI */
 854 #define FUNC_MF_CFG_E1HOV_TAG_MASK                  0x0000ffff
 855 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT                 0
 856 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT               FUNC_MF_CFG_E1HOV_TAG_MASK
 857
 858         u32 reserved[2];
 859
 860 };
 861
 862 struct mf_cfg {
 863
 864         struct shared_mf_cfg    shared_mf_config;
 865         struct port_mf_cfg      port_mf_config[PORT_MAX];
 866         struct func_mf_cfg      func_mf_config[E1H_FUNC_MAX];
 867
 868 };
 869
 870
 871 /****************************************************************************
 872  * Shared Memory Region                                                     *
 873  ****************************************************************************/
 874 struct shmem_region {                          /*   SharedMem Offset (size) */
 875
 876         u32                     validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
 877 #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
 878 #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
 879         /* validity bits */
 880 #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
 881 #define SHR_MEM_VALIDITY_MB                         0x00200000
 882 #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
 883 #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
 884         /* One licensing bit should be set */
 885 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
 886 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
 887 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
 888 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
 889         /* Active MFW */
 890 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
 891 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
 892 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
 893 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
 894 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
 895 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
 896
 897         struct shm_dev_info     dev_info;                /* 0x8     (0x438) */
 898
 899         struct license_key      drv_lic_key[PORT_MAX];  /* 0x440 (52*2=0x68) */
 900
 901         /* FW information (for internal FW use) */
 902         u32                     fw_info_fio_offset;    /* 0x4a8       (0x4) */
 903         struct mgmtfw_state     mgmtfw_state;          /* 0x4ac     (0x1b8) */
 904
 905         struct drv_port_mb      port_mb[PORT_MAX];     /* 0x664 (16*2=0x20) */
 906         struct drv_func_mb      func_mb[E1H_FUNC_MAX];
 907
 908         struct mf_cfg           mf_cfg;
 909
 910 };                                                     /* 0x6dc */
 911
 912
 913 struct shmem2_region {
 914
 915         u32                     size;
 916
 917         u32                     dcc_support;
 918 #define SHMEM_DCC_SUPPORT_NONE                      0x00000000
 919 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
 920 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
 921 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
 922 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
 923 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
 924 #define SHMEM_DCC_SUPPORT_DEFAULT                   SHMEM_DCC_SUPPORT_NONE
 925
 926 };
 927
 928
 929 struct emac_stats {
 930     u32     rx_stat_ifhcinoctets;
 931     u32     rx_stat_ifhcinbadoctets;
 932     u32     rx_stat_etherstatsfragments;
 933     u32     rx_stat_ifhcinucastpkts;
 934     u32     rx_stat_ifhcinmulticastpkts;
 935     u32     rx_stat_ifhcinbroadcastpkts;
 936     u32     rx_stat_dot3statsfcserrors;
 937     u32     rx_stat_dot3statsalignmenterrors;
 938     u32     rx_stat_dot3statscarriersenseerrors;
 939     u32     rx_stat_xonpauseframesreceived;
 940     u32     rx_stat_xoffpauseframesreceived;
 941     u32     rx_stat_maccontrolframesreceived;
 942     u32     rx_stat_xoffstateentered;
 943     u32     rx_stat_dot3statsframestoolong;
 944     u32     rx_stat_etherstatsjabbers;
 945     u32     rx_stat_etherstatsundersizepkts;
 946     u32     rx_stat_etherstatspkts64octets;
 947     u32     rx_stat_etherstatspkts65octetsto127octets;
 948     u32     rx_stat_etherstatspkts128octetsto255octets;
 949     u32     rx_stat_etherstatspkts256octetsto511octets;
 950     u32     rx_stat_etherstatspkts512octetsto1023octets;
 951     u32     rx_stat_etherstatspkts1024octetsto1522octets;
 952     u32     rx_stat_etherstatspktsover1522octets;
 953
 954     u32     rx_stat_falsecarriererrors;
 955
 956     u32     tx_stat_ifhcoutoctets;
 957     u32     tx_stat_ifhcoutbadoctets;
 958     u32     tx_stat_etherstatscollisions;
 959     u32     tx_stat_outxonsent;
 960     u32     tx_stat_outxoffsent;
 961     u32     tx_stat_flowcontroldone;
 962     u32     tx_stat_dot3statssinglecollisionframes;
 963     u32     tx_stat_dot3statsmultiplecollisionframes;
 964     u32     tx_stat_dot3statsdeferredtransmissions;
 965     u32     tx_stat_dot3statsexcessivecollisions;
 966     u32     tx_stat_dot3statslatecollisions;
 967     u32     tx_stat_ifhcoutucastpkts;
 968     u32     tx_stat_ifhcoutmulticastpkts;
 969     u32     tx_stat_ifhcoutbroadcastpkts;
 970     u32     tx_stat_etherstatspkts64octets;
 971     u32     tx_stat_etherstatspkts65octetsto127octets;
 972     u32     tx_stat_etherstatspkts128octetsto255octets;
 973     u32     tx_stat_etherstatspkts256octetsto511octets;
 974     u32     tx_stat_etherstatspkts512octetsto1023octets;
 975     u32     tx_stat_etherstatspkts1024octetsto1522octets;
 976     u32     tx_stat_etherstatspktsover1522octets;
 977     u32     tx_stat_dot3statsinternalmactransmiterrors;
 978 };
 979
 980
 981 struct bmac_stats {
 982     u32     tx_stat_gtpkt_lo;
 983     u32     tx_stat_gtpkt_hi;
 984     u32     tx_stat_gtxpf_lo;
 985     u32     tx_stat_gtxpf_hi;
 986     u32     tx_stat_gtfcs_lo;
 987     u32     tx_stat_gtfcs_hi;
 988     u32     tx_stat_gtmca_lo;
 989     u32     tx_stat_gtmca_hi;
 990     u32     tx_stat_gtbca_lo;
 991     u32     tx_stat_gtbca_hi;
 992     u32     tx_stat_gtfrg_lo;
 993     u32     tx_stat_gtfrg_hi;
 994     u32     tx_stat_gtovr_lo;
 995     u32     tx_stat_gtovr_hi;
 996     u32     tx_stat_gt64_lo;
 997     u32     tx_stat_gt64_hi;
 998     u32     tx_stat_gt127_lo;
 999     u32     tx_stat_gt127_hi;
1000     u32     tx_stat_gt255_lo;
1001     u32     tx_stat_gt255_hi;
1002     u32     tx_stat_gt511_lo;
1003     u32     tx_stat_gt511_hi;
1004     u32     tx_stat_gt1023_lo;
1005     u32     tx_stat_gt1023_hi;
1006     u32     tx_stat_gt1518_lo;
1007     u32     tx_stat_gt1518_hi;
1008     u32     tx_stat_gt2047_lo;
1009     u32     tx_stat_gt2047_hi;
1010     u32     tx_stat_gt4095_lo;
1011     u32     tx_stat_gt4095_hi;
1012     u32     tx_stat_gt9216_lo;
1013     u32     tx_stat_gt9216_hi;
1014     u32     tx_stat_gt16383_lo;
1015     u32     tx_stat_gt16383_hi;
1016     u32     tx_stat_gtmax_lo;
1017     u32     tx_stat_gtmax_hi;
1018     u32     tx_stat_gtufl_lo;
1019     u32     tx_stat_gtufl_hi;
1020     u32     tx_stat_gterr_lo;
1021     u32     tx_stat_gterr_hi;
1022     u32     tx_stat_gtbyt_lo;
1023     u32     tx_stat_gtbyt_hi;
1024
1025     u32     rx_stat_gr64_lo;
1026     u32     rx_stat_gr64_hi;
1027     u32     rx_stat_gr127_lo;
1028     u32     rx_stat_gr127_hi;
1029     u32     rx_stat_gr255_lo;
1030     u32     rx_stat_gr255_hi;
1031     u32     rx_stat_gr511_lo;
1032     u32     rx_stat_gr511_hi;
1033     u32     rx_stat_gr1023_lo;
1034     u32     rx_stat_gr1023_hi;
1035     u32     rx_stat_gr1518_lo;
1036     u32     rx_stat_gr1518_hi;
1037     u32     rx_stat_gr2047_lo;
1038     u32     rx_stat_gr2047_hi;
1039     u32     rx_stat_gr4095_lo;
1040     u32     rx_stat_gr4095_hi;
1041     u32     rx_stat_gr9216_lo;
1042     u32     rx_stat_gr9216_hi;
1043     u32     rx_stat_gr16383_lo;
1044     u32     rx_stat_gr16383_hi;
1045     u32     rx_stat_grmax_lo;
1046     u32     rx_stat_grmax_hi;
1047     u32     rx_stat_grpkt_lo;
1048     u32     rx_stat_grpkt_hi;
1049     u32     rx_stat_grfcs_lo;
1050     u32     rx_stat_grfcs_hi;
1051     u32     rx_stat_grmca_lo;
1052     u32     rx_stat_grmca_hi;
1053     u32     rx_stat_grbca_lo;
1054     u32     rx_stat_grbca_hi;
1055     u32     rx_stat_grxcf_lo;
1056     u32     rx_stat_grxcf_hi;
1057     u32     rx_stat_grxpf_lo;
1058     u32     rx_stat_grxpf_hi;
1059     u32     rx_stat_grxuo_lo;
1060     u32     rx_stat_grxuo_hi;
1061     u32     rx_stat_grjbr_lo;
1062     u32     rx_stat_grjbr_hi;
1063     u32     rx_stat_grovr_lo;
1064     u32     rx_stat_grovr_hi;
1065     u32     rx_stat_grflr_lo;
1066     u32     rx_stat_grflr_hi;
1067     u32     rx_stat_grmeg_lo;
1068     u32     rx_stat_grmeg_hi;
1069     u32     rx_stat_grmeb_lo;
1070     u32     rx_stat_grmeb_hi;
1071     u32     rx_stat_grbyt_lo;
1072     u32     rx_stat_grbyt_hi;
1073     u32     rx_stat_grund_lo;
1074     u32     rx_stat_grund_hi;
1075     u32     rx_stat_grfrg_lo;
1076     u32     rx_stat_grfrg_hi;
1077     u32     rx_stat_grerb_lo;
1078     u32     rx_stat_grerb_hi;
1079     u32     rx_stat_grfre_lo;
1080     u32     rx_stat_grfre_hi;
1081     u32     rx_stat_gripj_lo;
1082     u32     rx_stat_gripj_hi;
1083 };
1084
1085
1086 union mac_stats {
1087     struct emac_stats   emac_stats;
1088     struct bmac_stats   bmac_stats;
1089 };
1090
1091
1092 struct mac_stx {
1093     /* in_bad_octets */
1094     u32     rx_stat_ifhcinbadoctets_hi;
1095     u32     rx_stat_ifhcinbadoctets_lo;
1096
1097     /* out_bad_octets */
1098     u32     tx_stat_ifhcoutbadoctets_hi;
1099     u32     tx_stat_ifhcoutbadoctets_lo;
1100
1101     /* crc_receive_errors */
1102     u32     rx_stat_dot3statsfcserrors_hi;
1103     u32     rx_stat_dot3statsfcserrors_lo;
1104     /* alignment_errors */
1105     u32     rx_stat_dot3statsalignmenterrors_hi;
1106     u32     rx_stat_dot3statsalignmenterrors_lo;
1107     /* carrier_sense_errors */
1108     u32     rx_stat_dot3statscarriersenseerrors_hi;
1109     u32     rx_stat_dot3statscarriersenseerrors_lo;
1110     /* false_carrier_detections */
1111     u32     rx_stat_falsecarriererrors_hi;
1112     u32     rx_stat_falsecarriererrors_lo;
1113
1114     /* runt_packets_received */
1115     u32     rx_stat_etherstatsundersizepkts_hi;
1116     u32     rx_stat_etherstatsundersizepkts_lo;
1117     /* jabber_packets_received */
1118     u32     rx_stat_dot3statsframestoolong_hi;
1119     u32     rx_stat_dot3statsframestoolong_lo;
1120
1121     /* error_runt_packets_received */
1122     u32     rx_stat_etherstatsfragments_hi;
1123     u32     rx_stat_etherstatsfragments_lo;
1124     /* error_jabber_packets_received */
1125     u32     rx_stat_etherstatsjabbers_hi;
1126     u32     rx_stat_etherstatsjabbers_lo;
1127
1128     /* control_frames_received */
1129     u32     rx_stat_maccontrolframesreceived_hi;
1130     u32     rx_stat_maccontrolframesreceived_lo;
1131     u32     rx_stat_bmac_xpf_hi;
1132     u32     rx_stat_bmac_xpf_lo;
1133     u32     rx_stat_bmac_xcf_hi;
1134     u32     rx_stat_bmac_xcf_lo;
1135
1136     /* xoff_state_entered */
1137     u32     rx_stat_xoffstateentered_hi;
1138     u32     rx_stat_xoffstateentered_lo;
1139     /* pause_xon_frames_received */
1140     u32     rx_stat_xonpauseframesreceived_hi;
1141     u32     rx_stat_xonpauseframesreceived_lo;
1142     /* pause_xoff_frames_received */
1143     u32     rx_stat_xoffpauseframesreceived_hi;
1144     u32     rx_stat_xoffpauseframesreceived_lo;
1145     /* pause_xon_frames_transmitted */
1146     u32     tx_stat_outxonsent_hi;
1147     u32     tx_stat_outxonsent_lo;
1148     /* pause_xoff_frames_transmitted */
1149     u32     tx_stat_outxoffsent_hi;
1150     u32     tx_stat_outxoffsent_lo;
1151     /* flow_control_done */
1152     u32     tx_stat_flowcontroldone_hi;
1153     u32     tx_stat_flowcontroldone_lo;
1154
1155     /* ether_stats_collisions */
1156     u32     tx_stat_etherstatscollisions_hi;
1157     u32     tx_stat_etherstatscollisions_lo;
1158     /* single_collision_transmit_frames */
1159     u32     tx_stat_dot3statssinglecollisionframes_hi;
1160     u32     tx_stat_dot3statssinglecollisionframes_lo;
1161     /* multiple_collision_transmit_frames */
1162     u32     tx_stat_dot3statsmultiplecollisionframes_hi;
1163     u32     tx_stat_dot3statsmultiplecollisionframes_lo;
1164     /* deferred_transmissions */
1165     u32     tx_stat_dot3statsdeferredtransmissions_hi;
1166     u32     tx_stat_dot3statsdeferredtransmissions_lo;
1167     /* excessive_collision_frames */
1168     u32     tx_stat_dot3statsexcessivecollisions_hi;
1169     u32     tx_stat_dot3statsexcessivecollisions_lo;
1170     /* late_collision_frames */
1171     u32     tx_stat_dot3statslatecollisions_hi;
1172     u32     tx_stat_dot3statslatecollisions_lo;
1173
1174     /* frames_transmitted_64_bytes */
1175     u32     tx_stat_etherstatspkts64octets_hi;
1176     u32     tx_stat_etherstatspkts64octets_lo;
1177     /* frames_transmitted_65_127_bytes */
1178     u32     tx_stat_etherstatspkts65octetsto127octets_hi;
1179     u32     tx_stat_etherstatspkts65octetsto127octets_lo;
1180     /* frames_transmitted_128_255_bytes */
1181     u32     tx_stat_etherstatspkts128octetsto255octets_hi;
1182     u32     tx_stat_etherstatspkts128octetsto255octets_lo;
1183     /* frames_transmitted_256_511_bytes */
1184     u32     tx_stat_etherstatspkts256octetsto511octets_hi;
1185     u32     tx_stat_etherstatspkts256octetsto511octets_lo;
1186     /* frames_transmitted_512_1023_bytes */
1187     u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
1188     u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
1189     /* frames_transmitted_1024_1522_bytes */
1190     u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
1191     u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
1192     /* frames_transmitted_1523_9022_bytes */
1193     u32     tx_stat_etherstatspktsover1522octets_hi;
1194     u32     tx_stat_etherstatspktsover1522octets_lo;
1195     u32     tx_stat_bmac_2047_hi;
1196     u32     tx_stat_bmac_2047_lo;
1197     u32     tx_stat_bmac_4095_hi;
1198     u32     tx_stat_bmac_4095_lo;
1199     u32     tx_stat_bmac_9216_hi;
1200     u32     tx_stat_bmac_9216_lo;
1201     u32     tx_stat_bmac_16383_hi;
1202     u32     tx_stat_bmac_16383_lo;
1203
1204     /* internal_mac_transmit_errors */
1205     u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
1206     u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
1207
1208     /* if_out_discards */
1209     u32     tx_stat_bmac_ufl_hi;
1210     u32     tx_stat_bmac_ufl_lo;
1211 };
1212
1213
1214 #define MAC_STX_IDX_MAX                     2
1215
1216 struct host_port_stats {
1217     u32            host_port_stats_start;
1218
1219     struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1220
1221     u32            brb_drop_hi;
1222     u32            brb_drop_lo;
1223
1224     u32            host_port_stats_end;
1225 };
1226
1227
1228 struct host_func_stats {
1229     u32     host_func_stats_start;
1230
1231     u32     total_bytes_received_hi;
1232     u32     total_bytes_received_lo;
1233
1234     u32     total_bytes_transmitted_hi;
1235     u32     total_bytes_transmitted_lo;
1236
1237     u32     total_unicast_packets_received_hi;
1238     u32     total_unicast_packets_received_lo;
1239
1240     u32     total_multicast_packets_received_hi;
1241     u32     total_multicast_packets_received_lo;
1242
1243     u32     total_broadcast_packets_received_hi;
1244     u32     total_broadcast_packets_received_lo;
1245
1246     u32     total_unicast_packets_transmitted_hi;
1247     u32     total_unicast_packets_transmitted_lo;
1248
1249     u32     total_multicast_packets_transmitted_hi;
1250     u32     total_multicast_packets_transmitted_lo;
1251
1252     u32     total_broadcast_packets_transmitted_hi;
1253     u32     total_broadcast_packets_transmitted_lo;
1254
1255     u32     valid_bytes_received_hi;
1256     u32     valid_bytes_received_lo;
1257
1258     u32     host_func_stats_end;
1259 };
1260
1261
1262 #define BCM_5710_FW_MAJOR_VERSION                       5
1263 #define BCM_5710_FW_MINOR_VERSION                       2
1264 #define BCM_5710_FW_REVISION_VERSION                    13
1265 #define BCM_5710_FW_ENGINEERING_VERSION                 0
1266 #define BCM_5710_FW_COMPILE_FLAGS                       1
1267
1268
1269 /*
1270  * attention bits
1271  */
1272 struct atten_def_status_block {
1273         __le32 attn_bits;
1274         __le32 attn_bits_ack;
1275         u8 status_block_id;
1276         u8 reserved0;
1277         __le16 attn_bits_index;
1278         __le32 reserved1;
1279 };
1280
1281
1282 /*
1283  * common data for all protocols
1284  */
1285 struct doorbell_hdr {
1286         u8 header;
1287 #define DOORBELL_HDR_RX (0x1<<0)
1288 #define DOORBELL_HDR_RX_SHIFT 0
1289 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1290 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1291 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1292 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1293 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1294 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1295 };
1296
1297 /*
1298  * doorbell message sent to the chip
1299  */
1300 struct doorbell {
1301 #if defined(__BIG_ENDIAN)
1302         u16 zero_fill2;
1303         u8 zero_fill1;
1304         struct doorbell_hdr header;
1305 #elif defined(__LITTLE_ENDIAN)
1306         struct doorbell_hdr header;
1307         u8 zero_fill1;
1308         u16 zero_fill2;
1309 #endif
1310 };
1311
1312
1313 /*
1314  * doorbell message sent to the chip
1315  */
1316 struct doorbell_set_prod {
1317 #if defined(__BIG_ENDIAN)
1318         u16 prod;
1319         u8 zero_fill1;
1320         struct doorbell_hdr header;
1321 #elif defined(__LITTLE_ENDIAN)
1322         struct doorbell_hdr header;
1323         u8 zero_fill1;
1324         u16 prod;
1325 #endif
1326 };
1327
1328
1329 /*
1330  * IGU driver acknowledgement register
1331  */
1332 struct igu_ack_register {
1333 #if defined(__BIG_ENDIAN)
1334         u16 sb_id_and_flags;
1335 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1336 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1337 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1338 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1339 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1340 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1341 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1342 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1343 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1344 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1345         u16 status_block_index;
1346 #elif defined(__LITTLE_ENDIAN)
1347         u16 status_block_index;
1348         u16 sb_id_and_flags;
1349 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
1350 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1351 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
1352 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1353 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
1354 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1355 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
1356 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1357 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
1358 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1359 #endif
1360 };
1361
1362
1363 /*
1364  * IGU driver acknowledgement register
1365  */
1366 struct igu_backward_compatible {
1367         u32 sb_id_and_flags;
1368 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
1369 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
1370 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
1371 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
1372 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
1373 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
1374 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
1375 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
1376 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
1377 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
1378 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
1379 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
1380         u32 reserved_2;
1381 };
1382
1383
1384 /*
1385  * IGU driver acknowledgement register
1386  */
1387 struct igu_regular {
1388         u32 sb_id_and_flags;
1389 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
1390 #define IGU_REGULAR_SB_INDEX_SHIFT 0
1391 #define IGU_REGULAR_RESERVED0 (0x1<<20)
1392 #define IGU_REGULAR_RESERVED0_SHIFT 20
1393 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
1394 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
1395 #define IGU_REGULAR_BUPDATE (0x1<<24)
1396 #define IGU_REGULAR_BUPDATE_SHIFT 24
1397 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
1398 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
1399 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
1400 #define IGU_REGULAR_RESERVED_1_SHIFT 27
1401 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
1402 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
1403 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
1404 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
1405 #define IGU_REGULAR_BCLEANUP (0x1<<31)
1406 #define IGU_REGULAR_BCLEANUP_SHIFT 31
1407         u32 reserved_2;
1408 };
1409
1410 /*
1411  * IGU driver acknowledgement register
1412  */
1413 union igu_consprod_reg {
1414         struct igu_regular regular;
1415         struct igu_backward_compatible backward_compatible;
1416 };
1417
1418
1419 /*
1420  * Parser parsing flags field
1421  */
1422 struct parsing_flags {
1423         __le16 flags;
1424 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
1425 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1426 #define PARSING_FLAGS_VLAN (0x1<<1)
1427 #define PARSING_FLAGS_VLAN_SHIFT 1
1428 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
1429 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1430 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
1431 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1432 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
1433 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1434 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
1435 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1436 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
1437 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1438 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
1439 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1440 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
1441 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1442 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
1443 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1444 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
1445 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1446 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1447 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1448 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
1449 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1450 };
1451
1452
1453 struct regpair {
1454         __le32 lo;
1455         __le32 hi;
1456 };
1457
1458
1459 /*
1460  * dmae command structure
1461  */
1462 struct dmae_command {
1463         u32 opcode;
1464 #define DMAE_COMMAND_SRC (0x1<<0)
1465 #define DMAE_COMMAND_SRC_SHIFT 0
1466 #define DMAE_COMMAND_DST (0x3<<1)
1467 #define DMAE_COMMAND_DST_SHIFT 1
1468 #define DMAE_COMMAND_C_DST (0x1<<3)
1469 #define DMAE_COMMAND_C_DST_SHIFT 3
1470 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1471 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1472 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1473 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1474 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1475 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1476 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
1477 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1478 #define DMAE_COMMAND_PORT (0x1<<11)
1479 #define DMAE_COMMAND_PORT_SHIFT 11
1480 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
1481 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1482 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
1483 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1484 #define DMAE_COMMAND_DST_RESET (0x1<<14)
1485 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1486 #define DMAE_COMMAND_E1HVN (0x3<<15)
1487 #define DMAE_COMMAND_E1HVN_SHIFT 15
1488 #define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1489 #define DMAE_COMMAND_RESERVED0_SHIFT 17
1490         u32 src_addr_lo;
1491         u32 src_addr_hi;
1492         u32 dst_addr_lo;
1493         u32 dst_addr_hi;
1494 #if defined(__BIG_ENDIAN)
1495         u16 reserved1;
1496         u16 len;
1497 #elif defined(__LITTLE_ENDIAN)
1498         u16 len;
1499         u16 reserved1;
1500 #endif
1501         u32 comp_addr_lo;
1502         u32 comp_addr_hi;
1503         u32 comp_val;
1504         u32 crc32;
1505         u32 crc32_c;
1506 #if defined(__BIG_ENDIAN)
1507         u16 crc16_c;
1508         u16 crc16;
1509 #elif defined(__LITTLE_ENDIAN)
1510         u16 crc16;
1511         u16 crc16_c;
1512 #endif
1513 #if defined(__BIG_ENDIAN)
1514         u16 reserved2;
1515         u16 crc_t10;
1516 #elif defined(__LITTLE_ENDIAN)
1517         u16 crc_t10;
1518         u16 reserved2;
1519 #endif
1520 #if defined(__BIG_ENDIAN)
1521         u16 xsum8;
1522         u16 xsum16;
1523 #elif defined(__LITTLE_ENDIAN)
1524         u16 xsum16;
1525         u16 xsum8;
1526 #endif
1527 };
1528
1529
1530 struct double_regpair {
1531         u32 regpair0_lo;
1532         u32 regpair0_hi;
1533         u32 regpair1_lo;
1534         u32 regpair1_hi;
1535 };
1536
1537
1538 /*
1539  * The eth storm context of Ustorm (configuration part)
1540  */
1541 struct ustorm_eth_st_context_config {
1542 #if defined(__BIG_ENDIAN)
1543         u8 flags;
1544 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1545 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1546 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1547 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1548 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1549 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1550 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3)
1551 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
1552 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1553 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1554         u8 status_block_id;
1555         u8 clientId;
1556         u8 sb_index_numbers;
1557 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1558 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1559 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1560 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1561 #elif defined(__LITTLE_ENDIAN)
1562         u8 sb_index_numbers;
1563 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1564 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1565 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1566 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1567         u8 clientId;
1568         u8 status_block_id;
1569         u8 flags;
1570 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1571 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1572 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1573 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1574 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1575 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1576 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1<<3)
1577 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
1578 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1579 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1580 #endif
1581 #if defined(__BIG_ENDIAN)
1582         u16 bd_buff_size;
1583         u8 statistics_counter_id;
1584         u8 mc_alignment_log_size;
1585 #elif defined(__LITTLE_ENDIAN)
1586         u8 mc_alignment_log_size;
1587         u8 statistics_counter_id;
1588         u16 bd_buff_size;
1589 #endif
1590 #if defined(__BIG_ENDIAN)
1591         u8 __local_sge_prod;
1592         u8 __local_bd_prod;
1593         u16 sge_buff_size;
1594 #elif defined(__LITTLE_ENDIAN)
1595         u16 sge_buff_size;
1596         u8 __local_bd_prod;
1597         u8 __local_sge_prod;
1598 #endif
1599 #if defined(__BIG_ENDIAN)
1600         u16 __sdm_bd_expected_counter;
1601         u8 cstorm_agg_int;
1602         u8 __expected_bds_on_ram;
1603 #elif defined(__LITTLE_ENDIAN)
1604         u8 __expected_bds_on_ram;
1605         u8 cstorm_agg_int;
1606         u16 __sdm_bd_expected_counter;
1607 #endif
1608 #if defined(__BIG_ENDIAN)
1609         u16 __ring_data_ram_addr;
1610         u16 __hc_cstorm_ram_addr;
1611 #elif defined(__LITTLE_ENDIAN)
1612         u16 __hc_cstorm_ram_addr;
1613         u16 __ring_data_ram_addr;
1614 #endif
1615 #if defined(__BIG_ENDIAN)
1616         u8 reserved1;
1617         u8 max_sges_for_packet;
1618         u16 __bd_ring_ram_addr;
1619 #elif defined(__LITTLE_ENDIAN)
1620         u16 __bd_ring_ram_addr;
1621         u8 max_sges_for_packet;
1622         u8 reserved1;
1623 #endif
1624         u32 bd_page_base_lo;
1625         u32 bd_page_base_hi;
1626         u32 sge_page_base_lo;
1627         u32 sge_page_base_hi;
1628         struct regpair reserved2;
1629 };
1630
1631 /*
1632  * The eth Rx Buffer Descriptor
1633  */
1634 struct eth_rx_bd {
1635         __le32 addr_lo;
1636         __le32 addr_hi;
1637 };
1638
1639 /*
1640  * The eth Rx SGE Descriptor
1641  */
1642 struct eth_rx_sge {
1643         __le32 addr_lo;
1644         __le32 addr_hi;
1645 };
1646
1647 /*
1648  * Local BDs and SGEs rings (in ETH)
1649  */
1650 struct eth_local_rx_rings {
1651         struct eth_rx_bd __local_bd_ring[8];
1652         struct eth_rx_sge __local_sge_ring[10];
1653 };
1654
1655 /*
1656  * The eth storm context of Ustorm
1657  */
1658 struct ustorm_eth_st_context {
1659         struct ustorm_eth_st_context_config common;
1660         struct eth_local_rx_rings __rings;
1661 };
1662
1663 /*
1664  * The eth storm context of Tstorm
1665  */
1666 struct tstorm_eth_st_context {
1667         u32 __reserved0[28];
1668 };
1669
1670 /*
1671  * The eth aggregative context section of Xstorm
1672  */
1673 struct xstorm_eth_extra_ag_context_section {
1674 #if defined(__BIG_ENDIAN)
1675         u8 __tcp_agg_vars1;
1676         u8 __reserved50;
1677         u16 __mss;
1678 #elif defined(__LITTLE_ENDIAN)
1679         u16 __mss;
1680         u8 __reserved50;
1681         u8 __tcp_agg_vars1;
1682 #endif
1683         u32 __snd_nxt;
1684         u32 __tx_wnd;
1685         u32 __snd_una;
1686         u32 __reserved53;
1687 #if defined(__BIG_ENDIAN)
1688         u8 __agg_val8_th;
1689         u8 __agg_val8;
1690         u16 __tcp_agg_vars2;
1691 #elif defined(__LITTLE_ENDIAN)
1692         u16 __tcp_agg_vars2;
1693         u8 __agg_val8;
1694         u8 __agg_val8_th;
1695 #endif
1696         u32 __reserved58;
1697         u32 __reserved59;
1698         u32 __reserved60;
1699         u32 __reserved61;
1700 #if defined(__BIG_ENDIAN)
1701         u16 __agg_val7_th;
1702         u16 __agg_val7;
1703 #elif defined(__LITTLE_ENDIAN)
1704         u16 __agg_val7;
1705         u16 __agg_val7_th;
1706 #endif
1707 #if defined(__BIG_ENDIAN)
1708         u8 __tcp_agg_vars5;
1709         u8 __tcp_agg_vars4;
1710         u8 __tcp_agg_vars3;
1711         u8 __reserved62;
1712 #elif defined(__LITTLE_ENDIAN)
1713         u8 __reserved62;
1714         u8 __tcp_agg_vars3;
1715         u8 __tcp_agg_vars4;
1716         u8 __tcp_agg_vars5;
1717 #endif
1718         u32 __tcp_agg_vars6;
1719 #if defined(__BIG_ENDIAN)
1720         u16 __agg_misc6;
1721         u16 __tcp_agg_vars7;
1722 #elif defined(__LITTLE_ENDIAN)
1723         u16 __tcp_agg_vars7;
1724         u16 __agg_misc6;
1725 #endif
1726         u32 __agg_val10;
1727         u32 __agg_val10_th;
1728 #if defined(__BIG_ENDIAN)
1729         u16 __reserved3;
1730         u8 __reserved2;
1731         u8 __da_only_cnt;
1732 #elif defined(__LITTLE_ENDIAN)
1733         u8 __da_only_cnt;
1734         u8 __reserved2;
1735         u16 __reserved3;
1736 #endif
1737 };
1738
1739 /*
1740  * The eth aggregative context of Xstorm
1741  */
1742 struct xstorm_eth_ag_context {
1743 #if defined(__BIG_ENDIAN)
1744         u16 agg_val1;
1745         u8 __agg_vars1;
1746         u8 __state;
1747 #elif defined(__LITTLE_ENDIAN)
1748         u8 __state;
1749         u8 __agg_vars1;
1750         u16 agg_val1;
1751 #endif
1752 #if defined(__BIG_ENDIAN)
1753         u8 cdu_reserved;
1754         u8 __agg_vars4;
1755         u8 __agg_vars3;
1756         u8 __agg_vars2;
1757 #elif defined(__LITTLE_ENDIAN)
1758         u8 __agg_vars2;
1759         u8 __agg_vars3;
1760         u8 __agg_vars4;
1761         u8 cdu_reserved;
1762 #endif
1763         u32 __bd_prod;
1764 #if defined(__BIG_ENDIAN)
1765         u16 __agg_vars5;
1766         u16 __agg_val4_th;
1767 #elif defined(__LITTLE_ENDIAN)
1768         u16 __agg_val4_th;
1769         u16 __agg_vars5;
1770 #endif
1771         struct xstorm_eth_extra_ag_context_section __extra_section;
1772 #if defined(__BIG_ENDIAN)
1773         u16 __agg_vars7;
1774         u8 __agg_val3_th;
1775         u8 __agg_vars6;
1776 #elif defined(__LITTLE_ENDIAN)
1777         u8 __agg_vars6;
1778         u8 __agg_val3_th;
1779         u16 __agg_vars7;
1780 #endif
1781 #if defined(__BIG_ENDIAN)
1782         u16 __agg_val11_th;
1783         u16 __agg_val11;
1784 #elif defined(__LITTLE_ENDIAN)
1785         u16 __agg_val11;
1786         u16 __agg_val11_th;
1787 #endif
1788 #if defined(__BIG_ENDIAN)
1789         u8 __reserved1;
1790         u8 __agg_val6_th;
1791         u16 __agg_val9;
1792 #elif defined(__LITTLE_ENDIAN)
1793         u16 __agg_val9;
1794         u8 __agg_val6_th;
1795         u8 __reserved1;
1796 #endif
1797 #if defined(__BIG_ENDIAN)
1798         u16 __agg_val2_th;
1799         u16 __agg_val2;
1800 #elif defined(__LITTLE_ENDIAN)
1801         u16 __agg_val2;
1802         u16 __agg_val2_th;
1803 #endif
1804         u32 __agg_vars8;
1805 #if defined(__BIG_ENDIAN)
1806         u16 __agg_misc0;
1807         u16 __agg_val4;
1808 #elif defined(__LITTLE_ENDIAN)
1809         u16 __agg_val4;
1810         u16 __agg_misc0;
1811 #endif
1812 #if defined(__BIG_ENDIAN)
1813         u8 __agg_val3;
1814         u8 __agg_val6;
1815         u8 __agg_val5_th;
1816         u8 __agg_val5;
1817 #elif defined(__LITTLE_ENDIAN)
1818         u8 __agg_val5;
1819         u8 __agg_val5_th;
1820         u8 __agg_val6;
1821         u8 __agg_val3;
1822 #endif
1823 #if defined(__BIG_ENDIAN)
1824         u16 __agg_misc1;
1825         u16 __bd_ind_max_val;
1826 #elif defined(__LITTLE_ENDIAN)
1827         u16 __bd_ind_max_val;
1828         u16 __agg_misc1;
1829 #endif
1830         u32 __reserved57;
1831         u32 __agg_misc4;
1832         u32 __agg_misc5;
1833 };
1834
1835 /*
1836  * The eth extra aggregative context section of Tstorm
1837  */
1838 struct tstorm_eth_extra_ag_context_section {
1839         u32 __agg_val1;
1840 #if defined(__BIG_ENDIAN)
1841         u8 __tcp_agg_vars2;
1842         u8 __agg_val3;
1843         u16 __agg_val2;
1844 #elif defined(__LITTLE_ENDIAN)
1845         u16 __agg_val2;
1846         u8 __agg_val3;
1847         u8 __tcp_agg_vars2;
1848 #endif
1849 #if defined(__BIG_ENDIAN)
1850         u16 __agg_val5;
1851         u8 __agg_val6;
1852         u8 __tcp_agg_vars3;
1853 #elif defined(__LITTLE_ENDIAN)
1854         u8 __tcp_agg_vars3;
1855         u8 __agg_val6;
1856         u16 __agg_val5;
1857 #endif
1858         u32 __reserved63;
1859         u32 __reserved64;
1860         u32 __reserved65;
1861         u32 __reserved66;
1862         u32 __reserved67;
1863         u32 __tcp_agg_vars1;
1864         u32 __reserved61;
1865         u32 __reserved62;
1866         u32 __reserved2;
1867 };
1868
1869 /*
1870  * The eth aggregative context of Tstorm
1871  */
1872 struct tstorm_eth_ag_context {
1873 #if defined(__BIG_ENDIAN)
1874         u16 __reserved54;
1875         u8 __agg_vars1;
1876         u8 __state;
1877 #elif defined(__LITTLE_ENDIAN)
1878         u8 __state;
1879         u8 __agg_vars1;
1880         u16 __reserved54;
1881 #endif
1882 #if defined(__BIG_ENDIAN)
1883         u16 __agg_val4;
1884         u16 __agg_vars2;
1885 #elif defined(__LITTLE_ENDIAN)
1886         u16 __agg_vars2;
1887         u16 __agg_val4;
1888 #endif
1889         struct tstorm_eth_extra_ag_context_section __extra_section;
1890 };
1891
1892 /*
1893  * The eth aggregative context of Cstorm
1894  */
1895 struct cstorm_eth_ag_context {
1896         u32 __agg_vars1;
1897 #if defined(__BIG_ENDIAN)
1898         u8 __aux1_th;
1899         u8 __aux1_val;
1900         u16 __agg_vars2;
1901 #elif defined(__LITTLE_ENDIAN)
1902         u16 __agg_vars2;
1903         u8 __aux1_val;
1904         u8 __aux1_th;
1905 #endif
1906         u32 __num_of_treated_packet;
1907         u32 __last_packet_treated;
1908 #if defined(__BIG_ENDIAN)
1909         u16 __reserved58;
1910         u16 __reserved57;
1911 #elif defined(__LITTLE_ENDIAN)
1912         u16 __reserved57;
1913         u16 __reserved58;
1914 #endif
1915 #if defined(__BIG_ENDIAN)
1916         u8 __reserved62;
1917         u8 __reserved61;
1918         u8 __reserved60;
1919         u8 __reserved59;
1920 #elif defined(__LITTLE_ENDIAN)
1921         u8 __reserved59;
1922         u8 __reserved60;
1923         u8 __reserved61;
1924         u8 __reserved62;
1925 #endif
1926 #if defined(__BIG_ENDIAN)
1927         u16 __reserved64;
1928         u16 __reserved63;
1929 #elif defined(__LITTLE_ENDIAN)
1930         u16 __reserved63;
1931         u16 __reserved64;
1932 #endif
1933         u32 __reserved65;
1934 #if defined(__BIG_ENDIAN)
1935         u16 __agg_vars3;
1936         u16 __rq_inv_cnt;
1937 #elif defined(__LITTLE_ENDIAN)
1938         u16 __rq_inv_cnt;
1939         u16 __agg_vars3;
1940 #endif
1941 #if defined(__BIG_ENDIAN)
1942         u16 __packet_index_th;
1943         u16 __packet_index;
1944 #elif defined(__LITTLE_ENDIAN)
1945         u16 __packet_index;
1946         u16 __packet_index_th;
1947 #endif
1948 };
1949
1950 /*
1951  * The eth aggregative context of Ustorm
1952  */
1953 struct ustorm_eth_ag_context {
1954 #if defined(__BIG_ENDIAN)
1955         u8 __aux_counter_flags;
1956         u8 __agg_vars2;
1957         u8 __agg_vars1;
1958         u8 __state;
1959 #elif defined(__LITTLE_ENDIAN)
1960         u8 __state;
1961         u8 __agg_vars1;
1962         u8 __agg_vars2;
1963         u8 __aux_counter_flags;
1964 #endif
1965 #if defined(__BIG_ENDIAN)
1966         u8 cdu_usage;
1967         u8 __agg_misc2;
1968         u16 __agg_misc1;
1969 #elif defined(__LITTLE_ENDIAN)
1970         u16 __agg_misc1;
1971         u8 __agg_misc2;
1972         u8 cdu_usage;
1973 #endif
1974         u32 __agg_misc4;
1975 #if defined(__BIG_ENDIAN)
1976         u8 __agg_val3_th;
1977         u8 __agg_val3;
1978         u16 __agg_misc3;
1979 #elif defined(__LITTLE_ENDIAN)
1980         u16 __agg_misc3;
1981         u8 __agg_val3;
1982         u8 __agg_val3_th;
1983 #endif
1984         u32 __agg_val1;
1985         u32 __agg_misc4_th;
1986 #if defined(__BIG_ENDIAN)
1987         u16 __agg_val2_th;
1988         u16 __agg_val2;
1989 #elif defined(__LITTLE_ENDIAN)
1990         u16 __agg_val2;
1991         u16 __agg_val2_th;
1992 #endif
1993 #if defined(__BIG_ENDIAN)
1994         u16 __reserved2;
1995         u8 __decision_rules;
1996         u8 __decision_rule_enable_bits;
1997 #elif defined(__LITTLE_ENDIAN)
1998         u8 __decision_rule_enable_bits;
1999         u8 __decision_rules;
2000         u16 __reserved2;
2001 #endif
2002 };
2003
2004 /*
2005  * Timers connection context
2006  */
2007 struct timers_block_context {
2008         u32 __reserved_0;
2009         u32 __reserved_1;
2010         u32 __reserved_2;
2011         u32 flags;
2012 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
2013 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
2014 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
2015 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
2016 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
2017 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
2018 };
2019
2020 /*
2021  * structure for easy accessibility to assembler
2022  */
2023 struct eth_tx_bd_flags {
2024         u8 as_bitfield;
2025 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
2026 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
2027 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
2028 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
2029 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<2)
2030 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 2
2031 #define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
2032 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
2033 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
2034 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
2035 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
2036 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
2037 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
2038 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
2039 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
2040 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
2041 };
2042
2043 /*
2044  * The eth Tx Buffer Descriptor
2045  */
2046 struct eth_tx_start_bd {
2047         __le32 addr_lo;
2048         __le32 addr_hi;
2049         __le16 nbd;
2050         __le16 nbytes;
2051         __le16 vlan;
2052         struct eth_tx_bd_flags bd_flags;
2053         u8 general_data;
2054 #define ETH_TX_START_BD_HDR_NBDS (0x3F<<0)
2055 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
2056 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
2057 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
2058 };
2059
2060 /*
2061  * Tx regular BD structure
2062  */
2063 struct eth_tx_bd {
2064         u32 addr_lo;
2065         u32 addr_hi;
2066         u16 total_pkt_bytes;
2067         u16 nbytes;
2068         u8 reserved[4];
2069 };
2070
2071 /*
2072  * Tx parsing BD structure for ETH,Relevant in START
2073  */
2074 struct eth_tx_parse_bd {
2075         u8 global_data;
2076 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
2077 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
2078 #define ETH_TX_PARSE_BD_UDP_CS_FLG (0x1<<4)
2079 #define ETH_TX_PARSE_BD_UDP_CS_FLG_SHIFT 4
2080 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
2081 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
2082 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
2083 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
2084 #define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
2085 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
2086         u8 tcp_flags;
2087 #define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
2088 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
2089 #define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
2090 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
2091 #define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
2092 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
2093 #define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
2094 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
2095 #define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
2096 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
2097 #define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
2098 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
2099 #define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
2100 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
2101 #define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
2102 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
2103         u8 ip_hlen;
2104         s8 reserved;
2105         __le16 total_hlen;
2106         __le16 tcp_pseudo_csum;
2107         __le16 lso_mss;
2108         __le16 ip_id;
2109         __le32 tcp_send_seq;
2110 };
2111
2112 /*
2113  * The last BD in the BD memory will hold a pointer to the next BD memory
2114  */
2115 struct eth_tx_next_bd {
2116         __le32 addr_lo;
2117         __le32 addr_hi;
2118         u8 reserved[8];
2119 };
2120
2121 /*
2122  * union for 4 Bd types
2123  */
2124 union eth_tx_bd_types {
2125         struct eth_tx_start_bd start_bd;
2126         struct eth_tx_bd reg_bd;
2127         struct eth_tx_parse_bd parse_bd;
2128         struct eth_tx_next_bd next_bd;
2129 };
2130
2131 /*
2132  * The eth storm context of Xstorm
2133  */
2134 struct xstorm_eth_st_context {
2135         u32 tx_bd_page_base_lo;
2136         u32 tx_bd_page_base_hi;
2137 #if defined(__BIG_ENDIAN)
2138         u16 tx_bd_cons;
2139         u8 statistics_data;
2140 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
2141 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
2142 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
2143 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
2144         u8 __local_tx_bd_prod;
2145 #elif defined(__LITTLE_ENDIAN)
2146         u8 __local_tx_bd_prod;
2147         u8 statistics_data;
2148 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
2149 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
2150 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
2151 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
2152         u16 tx_bd_cons;
2153 #endif
2154         u32 __reserved1;
2155         u32 __reserved2;
2156 #if defined(__BIG_ENDIAN)
2157         u8 __ram_cache_index;
2158         u8 __double_buffer_client;
2159         u16 __pkt_cons;
2160 #elif defined(__LITTLE_ENDIAN)
2161         u16 __pkt_cons;
2162         u8 __double_buffer_client;
2163         u8 __ram_cache_index;
2164 #endif
2165 #if defined(__BIG_ENDIAN)
2166         u16 __statistics_address;
2167         u16 __gso_next;
2168 #elif defined(__LITTLE_ENDIAN)
2169         u16 __gso_next;
2170         u16 __statistics_address;
2171 #endif
2172 #if defined(__BIG_ENDIAN)
2173         u8 __local_tx_bd_cons;
2174         u8 safc_group_num;
2175         u8 safc_group_en;
2176         u8 __is_eth_conn;
2177 #elif defined(__LITTLE_ENDIAN)
2178         u8 __is_eth_conn;
2179         u8 safc_group_en;
2180         u8 safc_group_num;
2181         u8 __local_tx_bd_cons;
2182 #endif
2183         union eth_tx_bd_types __bds[13];
2184 };
2185
2186 /*
2187  * The eth storm context of Cstorm
2188  */
2189 struct cstorm_eth_st_context {
2190 #if defined(__BIG_ENDIAN)
2191         u16 __reserved0;
2192         u8 sb_index_number;
2193         u8 status_block_id;
2194 #elif defined(__LITTLE_ENDIAN)
2195         u8 status_block_id;
2196         u8 sb_index_number;
2197         u16 __reserved0;
2198 #endif
2199         u32 __reserved1[3];
2200 };
2201
2202 /*
2203  * Ethernet connection context
2204  */
2205 struct eth_context {
2206         struct ustorm_eth_st_context ustorm_st_context;
2207         struct tstorm_eth_st_context tstorm_st_context;
2208         struct xstorm_eth_ag_context xstorm_ag_context;
2209         struct tstorm_eth_ag_context tstorm_ag_context;
2210         struct cstorm_eth_ag_context cstorm_ag_context;
2211         struct ustorm_eth_ag_context ustorm_ag_context;
2212         struct timers_block_context timers_context;
2213         struct xstorm_eth_st_context xstorm_st_context;
2214         struct cstorm_eth_st_context cstorm_st_context;
2215 };
2216
2217
2218 /*
2219  * Ethernet doorbell
2220  */
2221 struct eth_tx_doorbell {
2222 #if defined(__BIG_ENDIAN)
2223         u16 npackets;
2224         u8 params;
2225 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2226 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2227 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2228 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2229 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2230 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2231         struct doorbell_hdr hdr;
2232 #elif defined(__LITTLE_ENDIAN)
2233         struct doorbell_hdr hdr;
2234         u8 params;
2235 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2236 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2237 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2238 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2239 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2240 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2241         u16 npackets;
2242 #endif
2243 };
2244
2245
2246 /*
2247  * cstorm default status block, generated by ustorm
2248  */
2249 struct cstorm_def_status_block_u {
2250         __le16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
2251         __le16 status_block_index;
2252         u8 func;
2253         u8 status_block_id;
2254         __le32 __flags;
2255 };
2256
2257 /*
2258  * cstorm default status block, generated by cstorm
2259  */
2260 struct cstorm_def_status_block_c {
2261         __le16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
2262         __le16 status_block_index;
2263         u8 func;
2264         u8 status_block_id;
2265         __le32 __flags;
2266 };
2267
2268 /*
2269  * xstorm status block
2270  */
2271 struct xstorm_def_status_block {
2272         __le16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
2273         __le16 status_block_index;
2274         u8 func;
2275         u8 status_block_id;
2276         __le32 __flags;
2277 };
2278
2279 /*
2280  * tstorm status block
2281  */
2282 struct tstorm_def_status_block {
2283         __le16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
2284         __le16 status_block_index;
2285         u8 func;
2286         u8 status_block_id;
2287         __le32 __flags;
2288 };
2289
2290 /*
2291  * host status block
2292  */
2293 struct host_def_status_block {
2294         struct atten_def_status_block atten_status_block;
2295         struct cstorm_def_status_block_u u_def_status_block;
2296         struct cstorm_def_status_block_c c_def_status_block;
2297         struct xstorm_def_status_block x_def_status_block;
2298         struct tstorm_def_status_block t_def_status_block;
2299 };
2300
2301
2302 /*
2303  * cstorm status block, generated by ustorm
2304  */
2305 struct cstorm_status_block_u {
2306         __le16 index_values[HC_USTORM_SB_NUM_INDICES];
2307         __le16 status_block_index;
2308         u8 func;
2309         u8 status_block_id;
2310         __le32 __flags;
2311 };
2312
2313 /*
2314  * cstorm status block, generated by cstorm
2315  */
2316 struct cstorm_status_block_c {
2317         __le16 index_values[HC_CSTORM_SB_NUM_INDICES];
2318         __le16 status_block_index;
2319         u8 func;
2320         u8 status_block_id;
2321         __le32 __flags;
2322 };
2323
2324 /*
2325  * host status block
2326  */
2327 struct host_status_block {
2328         struct cstorm_status_block_u u_status_block;
2329         struct cstorm_status_block_c c_status_block;
2330 };
2331
2332
2333 /*
2334  * The data for RSS setup ramrod
2335  */
2336 struct eth_client_setup_ramrod_data {
2337         u32 client_id;
2338         u8 is_rdma;
2339         u8 is_fcoe;
2340         u16 reserved1;
2341 };
2342
2343
2344 /*
2345  * regular eth FP CQE parameters struct
2346  */
2347 struct eth_fast_path_rx_cqe {
2348         u8 type_error_flags;
2349 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2350 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2351 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2352 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2353 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2354 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2355 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2356 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2357 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2358 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2359 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2360 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2361 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
2362 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
2363         u8 status_flags;
2364 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2365 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2366 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2367 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2368 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2369 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2370 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2371 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2372 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2373 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2374 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2375 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2376         u8 placement_offset;
2377         u8 queue_index;
2378         __le32 rss_hash_result;
2379         __le16 vlan_tag;
2380         __le16 pkt_len;
2381         __le16 len_on_bd;
2382         struct parsing_flags pars_flags;
2383         __le16 sgl[8];
2384 };
2385
2386
2387 /*
2388  * The data for RSS setup ramrod
2389  */
2390 struct eth_halt_ramrod_data {
2391         u32 client_id;
2392         u32 reserved0;
2393 };
2394
2395
2396 /*
2397  * The data for statistics query ramrod
2398  */
2399 struct eth_query_ramrod_data {
2400 #if defined(__BIG_ENDIAN)
2401         u8 reserved0;
2402         u8 collect_port;
2403         u16 drv_counter;
2404 #elif defined(__LITTLE_ENDIAN)
2405         u16 drv_counter;
2406         u8 collect_port;
2407         u8 reserved0;
2408 #endif
2409         u32 ctr_id_vector;
2410 };
2411
2412
2413 /*
2414  * Place holder for ramrods protocol specific data
2415  */
2416 struct ramrod_data {
2417         __le32 data_lo;
2418         __le32 data_hi;
2419 };
2420
2421 /*
2422  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2423  */
2424 union eth_ramrod_data {
2425         struct ramrod_data general;
2426 };
2427
2428
2429 /*
2430  * Eth Rx Cqe structure- general structure for ramrods
2431  */
2432 struct common_ramrod_eth_rx_cqe {
2433         u8 ramrod_type;
2434 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2435 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2436 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<1)
2437 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 1
2438 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x3F<<2)
2439 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 2
2440         u8 conn_type;
2441         __le16 reserved1;
2442         __le32 conn_and_cmd_data;
2443 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2444 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2445 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2446 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2447         struct ramrod_data protocol_data;
2448         __le32 reserved2[4];
2449 };
2450
2451 /*
2452  * Rx Last CQE in page (in ETH)
2453  */
2454 struct eth_rx_cqe_next_page {
2455         __le32 addr_lo;
2456         __le32 addr_hi;
2457         __le32 reserved[6];
2458 };
2459
2460 /*
2461  * union for all eth rx cqe types (fix their sizes)
2462  */
2463 union eth_rx_cqe {
2464         struct eth_fast_path_rx_cqe fast_path_cqe;
2465         struct common_ramrod_eth_rx_cqe ramrod_cqe;
2466         struct eth_rx_cqe_next_page next_page_cqe;
2467 };
2468
2469
2470 /*
2471  * common data for all protocols
2472  */
2473 struct spe_hdr {
2474         __le32 conn_and_cmd_data;
2475 #define SPE_HDR_CID (0xFFFFFF<<0)
2476 #define SPE_HDR_CID_SHIFT 0
2477 #define SPE_HDR_CMD_ID (0xFF<<24)
2478 #define SPE_HDR_CMD_ID_SHIFT 24
2479         __le16 type;
2480 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2481 #define SPE_HDR_CONN_TYPE_SHIFT 0
2482 #define SPE_HDR_COMMON_RAMROD (0xFF<<8)
2483 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
2484         __le16 reserved;
2485 };
2486
2487 /*
2488  * Ethernet slow path element
2489  */
2490 union eth_specific_data {
2491         u8 protocol_data[8];
2492         struct regpair mac_config_addr;
2493         struct eth_client_setup_ramrod_data client_setup_ramrod_data;
2494         struct eth_halt_ramrod_data halt_ramrod_data;
2495         struct regpair leading_cqe_addr;
2496         struct regpair update_data_addr;
2497         struct eth_query_ramrod_data query_ramrod_data;
2498 };
2499
2500 /*
2501  * Ethernet slow path element
2502  */
2503 struct eth_spe {
2504         struct spe_hdr hdr;
2505         union eth_specific_data data;
2506 };
2507
2508
2509 /*
2510  * array of 13 bds as appears in the eth xstorm context
2511  */
2512 struct eth_tx_bds_array {
2513         union eth_tx_bd_types bds[13];
2514 };
2515
2516
2517 /*
2518  * Common configuration parameters per function in Tstorm
2519  */
2520 struct tstorm_eth_function_common_config {
2521 #if defined(__BIG_ENDIAN)
2522         u8 leading_client_id;
2523         u8 rss_result_mask;
2524         u16 config_flags;
2525 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2526 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2527 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2528 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2529 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2530 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2531 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2532 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2533 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2534 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2535 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2536 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2537 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2538 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2539 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2540 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2541 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10)
2542 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
2543 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11)
2544 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
2545 #elif defined(__LITTLE_ENDIAN)
2546         u16 config_flags;
2547 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2548 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2549 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2550 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2551 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2552 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2553 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2554 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2555 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2556 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2557 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<7)
2558 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2559 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<8)
2560 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2561 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1<<9)
2562 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2563 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<10)
2564 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
2565 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F<<11)
2566 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
2567         u8 rss_result_mask;
2568         u8 leading_client_id;
2569 #endif
2570         u16 vlan_id[2];
2571 };
2572
2573 /*
2574  * RSS idirection table update configuration
2575  */
2576 struct rss_update_config {
2577 #if defined(__BIG_ENDIAN)
2578         u16 toe_rss_bitmap;
2579         u16 flags;
2580 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2581 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2582 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2583 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2584 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2585 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2586 #elif defined(__LITTLE_ENDIAN)
2587         u16 flags;
2588 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2589 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2590 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2591 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2592 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2593 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2594         u16 toe_rss_bitmap;
2595 #endif
2596         u32 reserved1;
2597 };
2598
2599 /*
2600  * parameters for eth update ramrod
2601  */
2602 struct eth_update_ramrod_data {
2603         struct tstorm_eth_function_common_config func_config;
2604         u8 indirectionTable[128];
2605         struct rss_update_config rss_config;
2606 };
2607
2608
2609 /*
2610  * MAC filtering configuration command header
2611  */
2612 struct mac_configuration_hdr {
2613         u8 length;
2614         u8 offset;
2615         u16 client_id;
2616         u32 reserved1;
2617 };
2618
2619 /*
2620  * MAC address in list for ramrod
2621  */
2622 struct tstorm_cam_entry {
2623         __le16 lsb_mac_addr;
2624         __le16 middle_mac_addr;
2625         __le16 msb_mac_addr;
2626         __le16 flags;
2627 #define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2628 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2629 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2630 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2631 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2632 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2633 };
2634
2635 /*
2636  * MAC filtering: CAM target table entry
2637  */
2638 struct tstorm_cam_target_table_entry {
2639         u8 flags;
2640 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2641 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2642 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2643 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2644 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2645 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2646 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2647 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2648 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2649 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2650         u8 reserved1;
2651         u16 vlan_id;
2652         u32 clients_bit_vector;
2653 };
2654
2655 /*
2656  * MAC address in list for ramrod
2657  */
2658 struct mac_configuration_entry {
2659         struct tstorm_cam_entry cam_entry;
2660         struct tstorm_cam_target_table_entry target_table_entry;
2661 };
2662
2663 /*
2664  * MAC filtering configuration command
2665  */
2666 struct mac_configuration_cmd {
2667         struct mac_configuration_hdr hdr;
2668         struct mac_configuration_entry config_table[64];
2669 };
2670
2671
2672 /*
2673  * MAC address in list for ramrod
2674  */
2675 struct mac_configuration_entry_e1h {
2676         __le16 lsb_mac_addr;
2677         __le16 middle_mac_addr;
2678         __le16 msb_mac_addr;
2679         __le16 vlan_id;
2680         __le16 e1hov_id;
2681         u8 reserved0;
2682         u8 flags;
2683 #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2684 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2685 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2686 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2687 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2688 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2689 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1 (0x1F<<3)
2690 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1_SHIFT 3
2691         u32 clients_bit_vector;
2692 };
2693
2694 /*
2695  * MAC filtering configuration command
2696  */
2697 struct mac_configuration_cmd_e1h {
2698         struct mac_configuration_hdr hdr;
2699         struct mac_configuration_entry_e1h config_table[32];
2700 };
2701
2702
2703 /*
2704  * approximate-match multicast filtering for E1H per function in Tstorm
2705  */
2706 struct tstorm_eth_approximate_match_multicast_filtering {
2707         u32 mcast_add_hash_bit_array[8];
2708 };
2709
2710
2711 /*
2712  * Configuration parameters per client in Tstorm
2713  */
2714 struct tstorm_eth_client_config {
2715 #if defined(__BIG_ENDIAN)
2716         u8 reserved0;
2717         u8 statistics_counter_id;
2718         u16 mtu;
2719 #elif defined(__LITTLE_ENDIAN)
2720         u16 mtu;
2721         u8 statistics_counter_id;
2722         u8 reserved0;
2723 #endif
2724 #if defined(__BIG_ENDIAN)
2725         u16 drop_flags;
2726 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2727 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2728 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2729 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2730 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2731 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2732 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2733 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2734 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4)
2735 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
2736         u16 config_flags;
2737 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2738 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2739 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2740 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2741 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2742 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2743 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3)
2744 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
2745 #elif defined(__LITTLE_ENDIAN)
2746         u16 config_flags;
2747 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1<<0)
2748 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2749 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1<<1)
2750 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2751 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<2)
2752 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2753 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF<<3)
2754 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
2755         u16 drop_flags;
2756 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2757 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2758 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2759 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2760 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2761 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2762 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2763 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2764 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF<<4)
2765 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
2766 #endif
2767 };
2768
2769
2770 /*
2771  * MAC filtering configuration parameters per port in Tstorm
2772  */
2773 struct tstorm_eth_mac_filter_config {
2774         u32 ucast_drop_all;
2775         u32 ucast_accept_all;
2776         u32 mcast_drop_all;
2777         u32 mcast_accept_all;
2778         u32 bcast_drop_all;
2779         u32 bcast_accept_all;
2780         u32 strict_vlan;
2781         u32 vlan_filter[2];
2782         u32 reserved;
2783 };
2784
2785
2786 /*
2787  * common flag to indicate existance of TPA.
2788  */
2789 struct tstorm_eth_tpa_exist {
2790 #if defined(__BIG_ENDIAN)
2791         u16 reserved1;
2792         u8 reserved0;
2793         u8 tpa_exist;
2794 #elif defined(__LITTLE_ENDIAN)
2795         u8 tpa_exist;
2796         u8 reserved0;
2797         u16 reserved1;
2798 #endif
2799         u32 reserved2;
2800 };
2801
2802
2803 /*
2804  * rx rings pause data for E1h only
2805  */
2806 struct ustorm_eth_rx_pause_data_e1h {
2807 #if defined(__BIG_ENDIAN)
2808         u16 bd_thr_low;
2809         u16 cqe_thr_low;
2810 #elif defined(__LITTLE_ENDIAN)
2811         u16 cqe_thr_low;
2812         u16 bd_thr_low;
2813 #endif
2814 #if defined(__BIG_ENDIAN)
2815         u16 cos;
2816         u16 sge_thr_low;
2817 #elif defined(__LITTLE_ENDIAN)
2818         u16 sge_thr_low;
2819         u16 cos;
2820 #endif
2821 #if defined(__BIG_ENDIAN)
2822         u16 bd_thr_high;
2823         u16 cqe_thr_high;
2824 #elif defined(__LITTLE_ENDIAN)
2825         u16 cqe_thr_high;
2826         u16 bd_thr_high;
2827 #endif
2828 #if defined(__BIG_ENDIAN)
2829         u16 reserved0;
2830         u16 sge_thr_high;
2831 #elif defined(__LITTLE_ENDIAN)
2832         u16 sge_thr_high;
2833         u16 reserved0;
2834 #endif
2835 };
2836
2837
2838 /*
2839  * Three RX producers for ETH
2840  */
2841 struct ustorm_eth_rx_producers {
2842 #if defined(__BIG_ENDIAN)
2843         u16 bd_prod;
2844         u16 cqe_prod;
2845 #elif defined(__LITTLE_ENDIAN)
2846         u16 cqe_prod;
2847         u16 bd_prod;
2848 #endif
2849 #if defined(__BIG_ENDIAN)
2850         u16 reserved;
2851         u16 sge_prod;
2852 #elif defined(__LITTLE_ENDIAN)
2853         u16 sge_prod;
2854         u16 reserved;
2855 #endif
2856 };
2857
2858
2859 /*
2860  * per-port SAFC demo variables
2861  */
2862 struct cmng_flags_per_port {
2863         u8 con_number[NUM_OF_PROTOCOLS];
2864         u32 cmng_enables;
2865 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
2866 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2867 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
2868 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2869 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
2870 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2871 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
2872 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2873 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
2874 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2875 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF<<5)
2876 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5
2877 };
2878
2879
2880 /*
2881  * per-port rate shaping variables
2882  */
2883 struct rate_shaping_vars_per_port {
2884         u32 rs_periodic_timeout;
2885         u32 rs_threshold;
2886 };
2887
2888 /*
2889  * per-port fairness variables
2890  */
2891 struct fairness_vars_per_port {
2892         u32 upper_bound;
2893         u32 fair_threshold;
2894         u32 fairness_timeout;
2895 };
2896
2897 /*
2898  * per-port SAFC variables
2899  */
2900 struct safc_struct_per_port {
2901 #if defined(__BIG_ENDIAN)
2902         u16 __reserved1;
2903         u8 __reserved0;
2904         u8 safc_timeout_usec;
2905 #elif defined(__LITTLE_ENDIAN)
2906         u8 safc_timeout_usec;
2907         u8 __reserved0;
2908         u16 __reserved1;
2909 #endif
2910         u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
2911 };
2912
2913 /*
2914  * Per-port congestion management variables
2915  */
2916 struct cmng_struct_per_port {
2917         struct rate_shaping_vars_per_port rs_vars;
2918         struct fairness_vars_per_port fair_vars;
2919         struct safc_struct_per_port safc_vars;
2920         struct cmng_flags_per_port flags;
2921 };
2922
2923
2924 /*
2925  * Dynamic host coalescing init parameters
2926  */
2927 struct dynamic_hc_config {
2928         u32 threshold[3];
2929         u8 shift_per_protocol[HC_USTORM_SB_NUM_INDICES];
2930         u8 hc_timeout0[HC_USTORM_SB_NUM_INDICES];
2931         u8 hc_timeout1[HC_USTORM_SB_NUM_INDICES];
2932         u8 hc_timeout2[HC_USTORM_SB_NUM_INDICES];
2933         u8 hc_timeout3[HC_USTORM_SB_NUM_INDICES];
2934 };
2935
2936
2937 /*
2938  * Protocol-common statistics collected by the Xstorm (per client)
2939  */
2940 struct xstorm_per_client_stats {
2941         __le32 reserved0;
2942         __le32 unicast_pkts_sent;
2943         struct regpair unicast_bytes_sent;
2944         struct regpair multicast_bytes_sent;
2945         __le32 multicast_pkts_sent;
2946         __le32 broadcast_pkts_sent;
2947         struct regpair broadcast_bytes_sent;
2948         __le16 stats_counter;
2949         __le16 reserved1;
2950         __le32 reserved2;
2951 };
2952
2953 /*
2954  * Common statistics collected by the Xstorm (per port)
2955  */
2956 struct xstorm_common_stats {
2957  struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
2958 };
2959
2960 /*
2961  * Protocol-common statistics collected by the Tstorm (per port)
2962  */
2963 struct tstorm_per_port_stats {
2964         __le32 mac_filter_discard;
2965         __le32 xxoverflow_discard;
2966         __le32 brb_truncate_discard;
2967         __le32 mac_discard;
2968 };
2969
2970 /*
2971  * Protocol-common statistics collected by the Tstorm (per client)
2972  */
2973 struct tstorm_per_client_stats {
2974         struct regpair rcv_unicast_bytes;
2975         struct regpair rcv_broadcast_bytes;
2976         struct regpair rcv_multicast_bytes;
2977         struct regpair rcv_error_bytes;
2978         __le32 checksum_discard;
2979         __le32 packets_too_big_discard;
2980         __le32 rcv_unicast_pkts;
2981         __le32 rcv_broadcast_pkts;
2982         __le32 rcv_multicast_pkts;
2983         __le32 no_buff_discard;
2984         __le32 ttl0_discard;
2985         __le16 stats_counter;
2986         __le16 reserved0;
2987 };
2988
2989 /*
2990  * Protocol-common statistics collected by the Tstorm
2991  */
2992 struct tstorm_common_stats {
2993         struct tstorm_per_port_stats port_statistics;
2994  struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2995 };
2996
2997 /*
2998  * Protocol-common statistics collected by the Ustorm (per client)
2999  */
3000 struct ustorm_per_client_stats {
3001         struct regpair ucast_no_buff_bytes;
3002         struct regpair mcast_no_buff_bytes;
3003         struct regpair bcast_no_buff_bytes;
3004         __le32 ucast_no_buff_pkts;
3005         __le32 mcast_no_buff_pkts;
3006         __le32 bcast_no_buff_pkts;
3007         __le16 stats_counter;
3008         __le16 reserved0;
3009 };
3010
3011 /*
3012  * Protocol-common statistics collected by the Ustorm
3013  */
3014 struct ustorm_common_stats {
3015  struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID];
3016 };
3017
3018 /*
3019  * Eth statistics query structure for the eth_stats_query ramrod
3020  */
3021 struct eth_stats_query {
3022         struct xstorm_common_stats xstorm_common;
3023         struct tstorm_common_stats tstorm_common;
3024         struct ustorm_common_stats ustorm_common;
3025 };
3026
3027
3028 /*
3029  * per-vnic fairness variables
3030  */
3031 struct fairness_vars_per_vn {
3032         u32 cos_credit_delta[MAX_COS_NUMBER];
3033         u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
3034         u32 vn_credit_delta;
3035         u32 __reserved0;
3036 };
3037
3038
3039 /*
3040  * FW version stored in the Xstorm RAM
3041  */
3042 struct fw_version {
3043 #if defined(__BIG_ENDIAN)
3044         u8 engineering;
3045         u8 revision;
3046         u8 minor;
3047         u8 major;
3048 #elif defined(__LITTLE_ENDIAN)
3049         u8 major;
3050         u8 minor;
3051         u8 revision;
3052         u8 engineering;
3053 #endif
3054         u32 flags;
3055 #define FW_VERSION_OPTIMIZED (0x1<<0)
3056 #define FW_VERSION_OPTIMIZED_SHIFT 0
3057 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
3058 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
3059 #define FW_VERSION_CHIP_VERSION (0x3<<2)
3060 #define FW_VERSION_CHIP_VERSION_SHIFT 2
3061 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
3062 #define __FW_VERSION_RESERVED_SHIFT 4
3063 };
3064
3065
3066 /*
3067  * FW version stored in first line of pram
3068  */
3069 struct pram_fw_version {
3070         u8 major;
3071         u8 minor;
3072         u8 revision;
3073         u8 engineering;
3074         u8 flags;
3075 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
3076 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
3077 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
3078 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
3079 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
3080 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
3081 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
3082 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
3083 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
3084 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
3085 };
3086
3087
3088 /*
3089  * The send queue element
3090  */
3091 struct protocol_common_spe {
3092         struct spe_hdr hdr;
3093         struct regpair phy_address;
3094 };
3095
3096
3097 /*
3098  * a single rate shaping counter. can be used as protocol or vnic counter
3099  */
3100 struct rate_shaping_counter {
3101         u32 quota;
3102 #if defined(__BIG_ENDIAN)
3103         u16 __reserved0;
3104         u16 rate;
3105 #elif defined(__LITTLE_ENDIAN)
3106         u16 rate;
3107         u16 __reserved0;
3108 #endif
3109 };
3110
3111
3112 /*
3113  * per-vnic rate shaping variables
3114  */
3115 struct rate_shaping_vars_per_vn {
3116         struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
3117         struct rate_shaping_counter vn_counter;
3118 };
3119
3120
3121 /*
3122  * The send queue element
3123  */
3124 struct slow_path_element {
3125         struct spe_hdr hdr;
3126         u8 protocol_data[8];
3127 };
3128
3129
3130 /*
3131  * eth/toe flags that indicate if to query
3132  */
3133 struct stats_indication_flags {
3134         u32 collect_eth;
3135         u32 collect_toe;
3136 };
3137
3138