1 /* bnx2x_reg.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2010 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
14 * ST - Statistics register (clear on read)
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
22 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
23 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
24 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
25 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
26 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
27 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
28 /* [RW 1] Initiate the ATC array - reset all the valid bits */
29 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
30 /* [R 1] ATC initalization done */
31 #define ATC_REG_ATC_INIT_DONE 0x1100bc
32 /* [RC 6] Interrupt register #0 read clear */
33 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
34 /* [RW 19] Interrupt mask register #0 read/write */
35 #define BRB1_REG_BRB1_INT_MASK 0x60128
36 /* [R 19] Interrupt register #0 read */
37 #define BRB1_REG_BRB1_INT_STS 0x6011c
38 /* [RW 4] Parity mask register #0 read/write */
39 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
40 /* [R 4] Parity register #0 read */
41 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
42 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
43 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
44 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
45 * following reset the first rbc access to this reg must be write; there can
46 * be no more rbc writes after the first one; there can be any number of rbc
47 * read following the first write; rbc access not following these rules will
48 * result in hang condition. */
49 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
50 /* [RW 10] The number of free blocks below which the full signal to class 0
52 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
53 /* [RW 10] The number of free blocks above which the full signal to class 0
55 #define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
56 /* [RW 10] The number of free blocks below which the full signal to class 1
58 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
59 /* [RW 10] The number of free blocks above which the full signal to class 1
61 #define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
62 /* [RW 10] The number of free blocks below which the full signal to the LB
64 #define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
65 /* [RW 10] The number of free blocks above which the full signal to the LB
66 * port is de-asserted */
67 #define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
68 /* [RW 10] The number of free blocks above which the High_llfc signal to
69 interface #n is de-asserted. */
70 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
71 /* [RW 10] The number of free blocks below which the High_llfc signal to
72 interface #n is asserted. */
73 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
74 /* [RW 23] LL RAM data. */
75 #define BRB1_REG_LL_RAM 0x61000
76 /* [RW 10] The number of free blocks above which the Low_llfc signal to
77 interface #n is de-asserted. */
78 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
79 /* [RW 10] The number of free blocks below which the Low_llfc signal to
80 interface #n is asserted. */
81 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
82 /* [RW 10] The number of blocks guarantied for the MAC port */
83 #define BRB1_REG_MAC_GUARANTIED_0 0x601e8
84 #define BRB1_REG_MAC_GUARANTIED_1 0x60240
85 /* [R 24] The number of full blocks. */
86 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
87 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
89 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
90 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
91 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
92 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
94 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
95 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
96 /* [RW 10] The number of free blocks below which the pause signal to class 0
98 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
99 /* [RW 10] The number of free blocks above which the pause signal to class 0
101 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
102 /* [RW 10] The number of free blocks below which the pause signal to class 1
104 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
105 /* [RW 10] The number of free blocks above which the pause signal to class 1
107 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
108 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
109 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
110 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
111 /* [RW 10] Write client 0: Assert pause threshold. */
112 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
113 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
114 /* [R 24] The number of full blocks occupied by port. */
115 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
116 /* [RW 1] Reset the design by software. */
117 #define BRB1_REG_SOFT_RESET 0x600dc
118 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
119 #define CCM_REG_CAM_OCCUP 0xd0188
120 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
121 acknowledge output is deasserted; all other signals are treated as usual;
122 if 1 - normal activity. */
123 #define CCM_REG_CCM_CFC_IFEN 0xd003c
124 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
125 disregarded; valid is deasserted; all other signals are treated as usual;
126 if 1 - normal activity. */
127 #define CCM_REG_CCM_CQM_IFEN 0xd000c
128 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
129 Otherwise 0 is inserted. */
130 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
131 /* [RW 11] Interrupt mask register #0 read/write */
132 #define CCM_REG_CCM_INT_MASK 0xd01e4
133 /* [R 11] Interrupt register #0 read */
134 #define CCM_REG_CCM_INT_STS 0xd01d8
135 /* [R 27] Parity register #0 read */
136 #define CCM_REG_CCM_PRTY_STS 0xd01e8
137 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
138 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
139 Is used to determine the number of the AG context REG-pairs written back;
140 when the input message Reg1WbFlg isn't set. */
141 #define CCM_REG_CCM_REG0_SZ 0xd00c4
142 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
143 disregarded; valid is deasserted; all other signals are treated as usual;
144 if 1 - normal activity. */
145 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
146 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
147 disregarded; valid is deasserted; all other signals are treated as usual;
148 if 1 - normal activity. */
149 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
150 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
151 disregarded; valid output is deasserted; all other signals are treated as
152 usual; if 1 - normal activity. */
153 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
154 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
155 are disregarded; all other signals are treated as usual; if 1 - normal
157 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
158 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
159 disregarded; valid output is deasserted; all other signals are treated as
160 usual; if 1 - normal activity. */
161 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
162 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
163 input is disregarded; all other signals are treated as usual; if 1 -
165 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
166 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
167 the initial credit value; read returns the current value of the credit
168 counter. Must be initialized to 1 at start-up. */
169 #define CCM_REG_CFC_INIT_CRD 0xd0204
170 /* [RW 2] Auxillary counter flag Q number 1. */
171 #define CCM_REG_CNT_AUX1_Q 0xd00c8
172 /* [RW 2] Auxillary counter flag Q number 2. */
173 #define CCM_REG_CNT_AUX2_Q 0xd00cc
174 /* [RW 28] The CM header value for QM request (primary). */
175 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
176 /* [RW 28] The CM header value for QM request (secondary). */
177 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
178 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
179 acknowledge output is deasserted; all other signals are treated as usual;
180 if 1 - normal activity. */
181 #define CCM_REG_CQM_CCM_IFEN 0xd0014
182 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
183 the initial credit value; read returns the current value of the credit
184 counter. Must be initialized to 32 at start-up. */
185 #define CCM_REG_CQM_INIT_CRD 0xd020c
186 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
187 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
188 prioritised); 2 stands for weight 2; tc. */
189 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
190 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
191 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
192 prioritised); 2 stands for weight 2; tc. */
193 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
194 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
195 acknowledge output is deasserted; all other signals are treated as usual;
196 if 1 - normal activity. */
197 #define CCM_REG_CSDM_IFEN 0xd0018
198 /* [RC 1] Set when the message length mismatch (relative to last indication)
199 at the SDM interface is detected. */
200 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
201 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
202 weight 8 (the most prioritised); 1 stands for weight 1(least
203 prioritised); 2 stands for weight 2; tc. */
204 #define CCM_REG_CSDM_WEIGHT 0xd00b4
205 /* [RW 28] The CM header for QM formatting in case of an error in the QM
207 #define CCM_REG_ERR_CCM_HDR 0xd0094
208 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
209 #define CCM_REG_ERR_EVNT_ID 0xd0098
210 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
211 writes the initial credit value; read returns the current value of the
212 credit counter. Must be initialized to 64 at start-up. */
213 #define CCM_REG_FIC0_INIT_CRD 0xd0210
214 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
215 writes the initial credit value; read returns the current value of the
216 credit counter. Must be initialized to 64 at start-up. */
217 #define CCM_REG_FIC1_INIT_CRD 0xd0214
218 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
219 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
220 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
221 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
222 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
223 #define CCM_REG_GR_ARB_TYPE 0xd015c
224 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
225 highest priority is 3. It is supposed; that the Store channel priority is
226 the compliment to 4 of the rest priorities - Aggregation channel; Load
227 (FIC0) channel and Load (FIC1). */
228 #define CCM_REG_GR_LD0_PR 0xd0164
229 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
230 highest priority is 3. It is supposed; that the Store channel priority is
231 the compliment to 4 of the rest priorities - Aggregation channel; Load
232 (FIC0) channel and Load (FIC1). */
233 #define CCM_REG_GR_LD1_PR 0xd0168
234 /* [RW 2] General flags index. */
235 #define CCM_REG_INV_DONE_Q 0xd0108
236 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
237 context and sent to STORM; for a specific connection type. The double
238 REG-pairs are used in order to align to STORM context row size of 128
239 bits. The offset of these data in the STORM context is always 0. Index
240 _(0..15) stands for the connection type (one of 16). */
241 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
242 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
243 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
244 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
245 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
246 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
247 acknowledge output is deasserted; all other signals are treated as usual;
248 if 1 - normal activity. */
249 #define CCM_REG_PBF_IFEN 0xd0028
250 /* [RC 1] Set when the message length mismatch (relative to last indication)
251 at the pbf interface is detected. */
252 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
253 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
254 weight 8 (the most prioritised); 1 stands for weight 1(least
255 prioritised); 2 stands for weight 2; tc. */
256 #define CCM_REG_PBF_WEIGHT 0xd00ac
257 #define CCM_REG_PHYS_QNUM1_0 0xd0134
258 #define CCM_REG_PHYS_QNUM1_1 0xd0138
259 #define CCM_REG_PHYS_QNUM2_0 0xd013c
260 #define CCM_REG_PHYS_QNUM2_1 0xd0140
261 #define CCM_REG_PHYS_QNUM3_0 0xd0144
262 #define CCM_REG_PHYS_QNUM3_1 0xd0148
263 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
264 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
265 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
266 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
267 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
268 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
269 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
270 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
271 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
272 disregarded; acknowledge output is deasserted; all other signals are
273 treated as usual; if 1 - normal activity. */
274 #define CCM_REG_STORM_CCM_IFEN 0xd0010
275 /* [RC 1] Set when the message length mismatch (relative to last indication)
276 at the STORM interface is detected. */
277 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
278 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
279 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
280 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
282 #define CCM_REG_STORM_WEIGHT 0xd009c
283 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
284 disregarded; acknowledge output is deasserted; all other signals are
285 treated as usual; if 1 - normal activity. */
286 #define CCM_REG_TSEM_IFEN 0xd001c
287 /* [RC 1] Set when the message length mismatch (relative to last indication)
288 at the tsem interface is detected. */
289 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
290 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
291 weight 8 (the most prioritised); 1 stands for weight 1(least
292 prioritised); 2 stands for weight 2; tc. */
293 #define CCM_REG_TSEM_WEIGHT 0xd00a0
294 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
295 disregarded; acknowledge output is deasserted; all other signals are
296 treated as usual; if 1 - normal activity. */
297 #define CCM_REG_USEM_IFEN 0xd0024
298 /* [RC 1] Set when message length mismatch (relative to last indication) at
299 the usem interface is detected. */
300 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
301 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
302 weight 8 (the most prioritised); 1 stands for weight 1(least
303 prioritised); 2 stands for weight 2; tc. */
304 #define CCM_REG_USEM_WEIGHT 0xd00a8
305 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
306 disregarded; acknowledge output is deasserted; all other signals are
307 treated as usual; if 1 - normal activity. */
308 #define CCM_REG_XSEM_IFEN 0xd0020
309 /* [RC 1] Set when the message length mismatch (relative to last indication)
310 at the xsem interface is detected. */
311 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
312 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
313 weight 8 (the most prioritised); 1 stands for weight 1(least
314 prioritised); 2 stands for weight 2; tc. */
315 #define CCM_REG_XSEM_WEIGHT 0xd00a4
316 /* [RW 19] Indirect access to the descriptor table of the XX protection
317 mechanism. The fields are: [5:0] - message length; [12:6] - message
318 pointer; 18:13] - next pointer. */
319 #define CCM_REG_XX_DESCR_TABLE 0xd0300
320 #define CCM_REG_XX_DESCR_TABLE_SIZE 36
321 /* [R 7] Used to read the value of XX protection Free counter. */
322 #define CCM_REG_XX_FREE 0xd0184
323 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
324 of the Input Stage XX protection buffer by the XX protection pending
325 messages. Max credit available - 127. Write writes the initial credit
326 value; read returns the current value of the credit counter. Must be
327 initialized to maximum XX protected message size - 2 at start-up. */
328 #define CCM_REG_XX_INIT_CRD 0xd0220
329 /* [RW 7] The maximum number of pending messages; which may be stored in XX
330 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
331 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
333 #define CCM_REG_XX_MSG_NUM 0xd0224
334 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
335 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
336 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
337 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
339 #define CCM_REG_XX_TABLE 0xd0280
340 #define CDU_REG_CDU_CHK_MASK0 0x101000
341 #define CDU_REG_CDU_CHK_MASK1 0x101004
342 #define CDU_REG_CDU_CONTROL0 0x101008
343 #define CDU_REG_CDU_DEBUG 0x101010
344 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
345 /* [RW 7] Interrupt mask register #0 read/write */
346 #define CDU_REG_CDU_INT_MASK 0x10103c
347 /* [R 7] Interrupt register #0 read */
348 #define CDU_REG_CDU_INT_STS 0x101030
349 /* [RW 5] Parity mask register #0 read/write */
350 #define CDU_REG_CDU_PRTY_MASK 0x10104c
351 /* [R 5] Parity register #0 read */
352 #define CDU_REG_CDU_PRTY_STS 0x101040
353 /* [RC 32] logging of error data in case of a CDU load error:
354 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
355 ype_error; ctual_active; ctual_compressed_context}; */
356 #define CDU_REG_ERROR_DATA 0x101014
357 /* [WB 216] L1TT ram access. each entry has the following format :
358 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
359 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
360 #define CDU_REG_L1TT 0x101800
361 /* [WB 24] MATT ram access. each entry has the following
362 format:{RegionLength[11:0]; egionOffset[11:0]} */
363 #define CDU_REG_MATT 0x101100
364 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
365 #define CDU_REG_MF_MODE 0x101050
366 /* [R 1] indication the initializing the activity counter by the hardware
368 #define CFC_REG_AC_INIT_DONE 0x104078
369 /* [RW 13] activity counter ram access */
370 #define CFC_REG_ACTIVITY_COUNTER 0x104400
371 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
372 /* [R 1] indication the initializing the cams by the hardware was done. */
373 #define CFC_REG_CAM_INIT_DONE 0x10407c
374 /* [RW 2] Interrupt mask register #0 read/write */
375 #define CFC_REG_CFC_INT_MASK 0x104108
376 /* [R 2] Interrupt register #0 read */
377 #define CFC_REG_CFC_INT_STS 0x1040fc
378 /* [RC 2] Interrupt register #0 read clear */
379 #define CFC_REG_CFC_INT_STS_CLR 0x104100
380 /* [RW 4] Parity mask register #0 read/write */
381 #define CFC_REG_CFC_PRTY_MASK 0x104118
382 /* [R 4] Parity register #0 read */
383 #define CFC_REG_CFC_PRTY_STS 0x10410c
384 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
385 #define CFC_REG_CID_CAM 0x104800
386 #define CFC_REG_CONTROL0 0x104028
387 #define CFC_REG_DEBUG0 0x104050
388 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
389 vector) whether the cfc should be disabled upon it */
390 #define CFC_REG_DISABLE_ON_ERROR 0x104044
391 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
392 set one of these bits. the bit description can be found in CFC
394 #define CFC_REG_ERROR_VECTOR 0x10403c
395 /* [WB 93] LCID info ram access */
396 #define CFC_REG_INFO_RAM 0x105000
397 #define CFC_REG_INFO_RAM_SIZE 1024
398 #define CFC_REG_INIT_REG 0x10404c
399 #define CFC_REG_INTERFACES 0x104058
400 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
401 field allows changing the priorities of the weighted-round-robin arbiter
402 which selects which CFC load client should be served next */
403 #define CFC_REG_LCREQ_WEIGHTS 0x104084
404 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
405 #define CFC_REG_LINK_LIST 0x104c00
406 #define CFC_REG_LINK_LIST_SIZE 256
407 /* [R 1] indication the initializing the link list by the hardware was done. */
408 #define CFC_REG_LL_INIT_DONE 0x104074
409 /* [R 9] Number of allocated LCIDs which are at empty state */
410 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
411 /* [R 9] Number of Arriving LCIDs in Link List Block */
412 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
413 /* [R 9] Number of Leaving LCIDs in Link List Block */
414 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
415 #define CFC_REG_WEAK_ENABLE_PF 0x104124
416 /* [RW 8] The event id for aggregated interrupt 0 */
417 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
418 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
419 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
420 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
421 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
422 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
423 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
424 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
425 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
426 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
427 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
428 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c
429 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050
430 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054
431 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058
432 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c
433 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
434 or auto-mask-mode (1) */
435 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0
436 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4
437 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8
438 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec
439 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0
440 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4
441 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8
442 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0
443 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4
444 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8
445 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc
446 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
447 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
448 /* [RW 16] The maximum value of the competion counter #0 */
449 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
450 /* [RW 16] The maximum value of the competion counter #1 */
451 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
452 /* [RW 16] The maximum value of the competion counter #2 */
453 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
454 /* [RW 16] The maximum value of the competion counter #3 */
455 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
456 /* [RW 13] The start address in the internal RAM for the completion
458 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
459 /* [RW 32] Interrupt mask register #0 read/write */
460 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
461 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
462 /* [R 32] Interrupt register #0 read */
463 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
464 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
465 /* [RW 11] Parity mask register #0 read/write */
466 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
467 /* [R 11] Parity register #0 read */
468 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
469 #define CSDM_REG_ENABLE_IN1 0xc2238
470 #define CSDM_REG_ENABLE_IN2 0xc223c
471 #define CSDM_REG_ENABLE_OUT1 0xc2240
472 #define CSDM_REG_ENABLE_OUT2 0xc2244
473 /* [RW 4] The initial number of messages that can be sent to the pxp control
474 interface without receiving any ACK. */
475 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
476 /* [ST 32] The number of ACK after placement messages received */
477 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
478 /* [ST 32] The number of packet end messages received from the parser */
479 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
480 /* [ST 32] The number of requests received from the pxp async if */
481 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
482 /* [ST 32] The number of commands received in queue 0 */
483 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
484 /* [ST 32] The number of commands received in queue 10 */
485 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
486 /* [ST 32] The number of commands received in queue 11 */
487 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
488 /* [ST 32] The number of commands received in queue 1 */
489 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
490 /* [ST 32] The number of commands received in queue 3 */
491 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
492 /* [ST 32] The number of commands received in queue 4 */
493 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
494 /* [ST 32] The number of commands received in queue 5 */
495 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
496 /* [ST 32] The number of commands received in queue 6 */
497 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
498 /* [ST 32] The number of commands received in queue 7 */
499 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
500 /* [ST 32] The number of commands received in queue 8 */
501 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
502 /* [ST 32] The number of commands received in queue 9 */
503 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
504 /* [RW 13] The start address in the internal RAM for queue counters */
505 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
506 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
507 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
508 /* [R 1] parser fifo empty in sdm_sync block */
509 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
510 /* [R 1] parser serial fifo empty in sdm_sync block */
511 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
512 /* [RW 32] Tick for timer counter. Applicable only when
513 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
514 #define CSDM_REG_TIMER_TICK 0xc2000
515 /* [RW 5] The number of time_slots in the arbitration cycle */
516 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
517 /* [RW 3] The source that is associated with arbitration element 0. Source
518 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
519 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
520 #define CSEM_REG_ARB_ELEMENT0 0x200020
521 /* [RW 3] The source that is associated with arbitration element 1. Source
522 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
523 sleeping thread with priority 1; 4- sleeping thread with priority 2.
524 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
525 #define CSEM_REG_ARB_ELEMENT1 0x200024
526 /* [RW 3] The source that is associated with arbitration element 2. Source
527 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
528 sleeping thread with priority 1; 4- sleeping thread with priority 2.
529 Could not be equal to register ~csem_registers_arb_element0.arb_element0
530 and ~csem_registers_arb_element1.arb_element1 */
531 #define CSEM_REG_ARB_ELEMENT2 0x200028
532 /* [RW 3] The source that is associated with arbitration element 3. Source
533 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
534 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
535 not be equal to register ~csem_registers_arb_element0.arb_element0 and
536 ~csem_registers_arb_element1.arb_element1 and
537 ~csem_registers_arb_element2.arb_element2 */
538 #define CSEM_REG_ARB_ELEMENT3 0x20002c
539 /* [RW 3] The source that is associated with arbitration element 4. Source
540 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
541 sleeping thread with priority 1; 4- sleeping thread with priority 2.
542 Could not be equal to register ~csem_registers_arb_element0.arb_element0
543 and ~csem_registers_arb_element1.arb_element1 and
544 ~csem_registers_arb_element2.arb_element2 and
545 ~csem_registers_arb_element3.arb_element3 */
546 #define CSEM_REG_ARB_ELEMENT4 0x200030
547 /* [RW 32] Interrupt mask register #0 read/write */
548 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
549 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
550 /* [R 32] Interrupt register #0 read */
551 #define CSEM_REG_CSEM_INT_STS_0 0x200104
552 #define CSEM_REG_CSEM_INT_STS_1 0x200114
553 /* [RW 32] Parity mask register #0 read/write */
554 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
555 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
556 /* [R 32] Parity register #0 read */
557 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
558 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
559 #define CSEM_REG_ENABLE_IN 0x2000a4
560 #define CSEM_REG_ENABLE_OUT 0x2000a8
561 /* [RW 32] This address space contains all registers and memories that are
562 placed in SEM_FAST block. The SEM_FAST registers are described in
563 appendix B. In order to access the sem_fast registers the base address
564 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
565 #define CSEM_REG_FAST_MEMORY 0x220000
566 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
568 #define CSEM_REG_FIC0_DISABLE 0x200224
569 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
571 #define CSEM_REG_FIC1_DISABLE 0x200234
572 /* [RW 15] Interrupt table Read and write access to it is not possible in
573 the middle of the work */
574 #define CSEM_REG_INT_TABLE 0x200400
575 /* [ST 24] Statistics register. The number of messages that entered through
577 #define CSEM_REG_MSG_NUM_FIC0 0x200000
578 /* [ST 24] Statistics register. The number of messages that entered through
580 #define CSEM_REG_MSG_NUM_FIC1 0x200004
581 /* [ST 24] Statistics register. The number of messages that were sent to
583 #define CSEM_REG_MSG_NUM_FOC0 0x200008
584 /* [ST 24] Statistics register. The number of messages that were sent to
586 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
587 /* [ST 24] Statistics register. The number of messages that were sent to
589 #define CSEM_REG_MSG_NUM_FOC2 0x200010
590 /* [ST 24] Statistics register. The number of messages that were sent to
592 #define CSEM_REG_MSG_NUM_FOC3 0x200014
593 /* [RW 1] Disables input messages from the passive buffer May be updated
594 during run_time by the microcode */
595 #define CSEM_REG_PAS_DISABLE 0x20024c
596 /* [WB 128] Debug only. Passive buffer memory */
597 #define CSEM_REG_PASSIVE_BUFFER 0x202000
598 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
599 #define CSEM_REG_PRAM 0x240000
600 /* [R 16] Valid sleeping threads indication have bit per thread */
601 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
602 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
603 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
604 /* [RW 16] List of free threads . There is a bit per thread. */
605 #define CSEM_REG_THREADS_LIST 0x2002e4
606 /* [RW 3] The arbitration scheme of time_slot 0 */
607 #define CSEM_REG_TS_0_AS 0x200038
608 /* [RW 3] The arbitration scheme of time_slot 10 */
609 #define CSEM_REG_TS_10_AS 0x200060
610 /* [RW 3] The arbitration scheme of time_slot 11 */
611 #define CSEM_REG_TS_11_AS 0x200064
612 /* [RW 3] The arbitration scheme of time_slot 12 */
613 #define CSEM_REG_TS_12_AS 0x200068
614 /* [RW 3] The arbitration scheme of time_slot 13 */
615 #define CSEM_REG_TS_13_AS 0x20006c
616 /* [RW 3] The arbitration scheme of time_slot 14 */
617 #define CSEM_REG_TS_14_AS 0x200070
618 /* [RW 3] The arbitration scheme of time_slot 15 */
619 #define CSEM_REG_TS_15_AS 0x200074
620 /* [RW 3] The arbitration scheme of time_slot 16 */
621 #define CSEM_REG_TS_16_AS 0x200078
622 /* [RW 3] The arbitration scheme of time_slot 17 */
623 #define CSEM_REG_TS_17_AS 0x20007c
624 /* [RW 3] The arbitration scheme of time_slot 18 */
625 #define CSEM_REG_TS_18_AS 0x200080
626 /* [RW 3] The arbitration scheme of time_slot 1 */
627 #define CSEM_REG_TS_1_AS 0x20003c
628 /* [RW 3] The arbitration scheme of time_slot 2 */
629 #define CSEM_REG_TS_2_AS 0x200040
630 /* [RW 3] The arbitration scheme of time_slot 3 */
631 #define CSEM_REG_TS_3_AS 0x200044
632 /* [RW 3] The arbitration scheme of time_slot 4 */
633 #define CSEM_REG_TS_4_AS 0x200048
634 /* [RW 3] The arbitration scheme of time_slot 5 */
635 #define CSEM_REG_TS_5_AS 0x20004c
636 /* [RW 3] The arbitration scheme of time_slot 6 */
637 #define CSEM_REG_TS_6_AS 0x200050
638 /* [RW 3] The arbitration scheme of time_slot 7 */
639 #define CSEM_REG_TS_7_AS 0x200054
640 /* [RW 3] The arbitration scheme of time_slot 8 */
641 #define CSEM_REG_TS_8_AS 0x200058
642 /* [RW 3] The arbitration scheme of time_slot 9 */
643 #define CSEM_REG_TS_9_AS 0x20005c
644 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
645 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
646 #define CSEM_REG_VFPF_ERR_NUM 0x200380
647 /* [RW 1] Parity mask register #0 read/write */
648 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
649 /* [R 1] Parity register #0 read */
650 #define DBG_REG_DBG_PRTY_STS 0xc09c
651 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
652 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
653 * 4.Completion function=0; 5.Error handling=0 */
654 #define DMAE_REG_BACKWARD_COMP_EN 0x10207c
655 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
657 #define DMAE_REG_CMD_MEM 0x102400
658 #define DMAE_REG_CMD_MEM_SIZE 224
659 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
660 initial value is all ones. */
661 #define DMAE_REG_CRC16C_INIT 0x10201c
662 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
663 CRC-16 T10 initial value is all ones. */
664 #define DMAE_REG_CRC16T10_INIT 0x102020
665 /* [RW 2] Interrupt mask register #0 read/write */
666 #define DMAE_REG_DMAE_INT_MASK 0x102054
667 /* [RW 4] Parity mask register #0 read/write */
668 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
669 /* [R 4] Parity register #0 read */
670 #define DMAE_REG_DMAE_PRTY_STS 0x102058
671 /* [RW 1] Command 0 go. */
672 #define DMAE_REG_GO_C0 0x102080
673 /* [RW 1] Command 1 go. */
674 #define DMAE_REG_GO_C1 0x102084
675 /* [RW 1] Command 10 go. */
676 #define DMAE_REG_GO_C10 0x102088
677 /* [RW 1] Command 11 go. */
678 #define DMAE_REG_GO_C11 0x10208c
679 /* [RW 1] Command 12 go. */
680 #define DMAE_REG_GO_C12 0x102090
681 /* [RW 1] Command 13 go. */
682 #define DMAE_REG_GO_C13 0x102094
683 /* [RW 1] Command 14 go. */
684 #define DMAE_REG_GO_C14 0x102098
685 /* [RW 1] Command 15 go. */
686 #define DMAE_REG_GO_C15 0x10209c
687 /* [RW 1] Command 2 go. */
688 #define DMAE_REG_GO_C2 0x1020a0
689 /* [RW 1] Command 3 go. */
690 #define DMAE_REG_GO_C3 0x1020a4
691 /* [RW 1] Command 4 go. */
692 #define DMAE_REG_GO_C4 0x1020a8
693 /* [RW 1] Command 5 go. */
694 #define DMAE_REG_GO_C5 0x1020ac
695 /* [RW 1] Command 6 go. */
696 #define DMAE_REG_GO_C6 0x1020b0
697 /* [RW 1] Command 7 go. */
698 #define DMAE_REG_GO_C7 0x1020b4
699 /* [RW 1] Command 8 go. */
700 #define DMAE_REG_GO_C8 0x1020b8
701 /* [RW 1] Command 9 go. */
702 #define DMAE_REG_GO_C9 0x1020bc
703 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
704 input is disregarded; valid is deasserted; all other signals are treated
705 as usual; if 1 - normal activity. */
706 #define DMAE_REG_GRC_IFEN 0x102008
707 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
708 acknowledge input is disregarded; valid is deasserted; full is asserted;
709 all other signals are treated as usual; if 1 - normal activity. */
710 #define DMAE_REG_PCI_IFEN 0x102004
711 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
712 initial value to the credit counter; related to the address. Read returns
713 the current value of the counter. */
714 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
715 /* [RW 8] Aggregation command. */
716 #define DORQ_REG_AGG_CMD0 0x170060
717 /* [RW 8] Aggregation command. */
718 #define DORQ_REG_AGG_CMD1 0x170064
719 /* [RW 8] Aggregation command. */
720 #define DORQ_REG_AGG_CMD2 0x170068
721 /* [RW 8] Aggregation command. */
722 #define DORQ_REG_AGG_CMD3 0x17006c
723 /* [RW 28] UCM Header. */
724 #define DORQ_REG_CMHEAD_RX 0x170050
725 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
726 #define DORQ_REG_DB_ADDR0 0x17008c
727 /* [RW 5] Interrupt mask register #0 read/write */
728 #define DORQ_REG_DORQ_INT_MASK 0x170180
729 /* [R 5] Interrupt register #0 read */
730 #define DORQ_REG_DORQ_INT_STS 0x170174
731 /* [RC 5] Interrupt register #0 read clear */
732 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
733 /* [RW 2] Parity mask register #0 read/write */
734 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
735 /* [R 2] Parity register #0 read */
736 #define DORQ_REG_DORQ_PRTY_STS 0x170184
737 /* [RW 8] The address to write the DPM CID to STORM. */
738 #define DORQ_REG_DPM_CID_ADDR 0x170044
739 /* [RW 5] The DPM mode CID extraction offset. */
740 #define DORQ_REG_DPM_CID_OFST 0x170030
741 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
742 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
743 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
744 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
745 /* [R 13] Current value of the DQ FIFO fill level according to following
746 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
748 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
749 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
750 equal to full threshold; reset on full clear. */
751 #define DORQ_REG_DQ_FULL_ST 0x1700c0
752 /* [RW 28] The value sent to CM header in the case of CFC load error. */
753 #define DORQ_REG_ERR_CMHEAD 0x170058
754 #define DORQ_REG_IF_EN 0x170004
755 #define DORQ_REG_MODE_ACT 0x170008
756 /* [RW 5] The normal mode CID extraction offset. */
757 #define DORQ_REG_NORM_CID_OFST 0x17002c
758 /* [RW 28] TCM Header when only TCP context is loaded. */
759 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
760 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
762 #define DORQ_REG_OUTST_REQ 0x17003c
763 #define DORQ_REG_REGN 0x170038
764 /* [R 4] Current value of response A counter credit. Initial credit is
765 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
767 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
768 /* [R 4] Current value of response B counter credit. Initial credit is
769 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
771 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
772 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
773 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
774 read reads this written value. */
775 #define DORQ_REG_RSP_INIT_CRD 0x170048
776 /* [RW 4] Initial activity counter value on the load request; when the
778 #define DORQ_REG_SHRT_ACT_CNT 0x170070
779 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
780 #define DORQ_REG_SHRT_CMHEAD 0x170054
781 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
782 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
783 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
784 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
785 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
786 #define HC_REG_AGG_INT_0 0x108050
787 #define HC_REG_AGG_INT_1 0x108054
788 #define HC_REG_ATTN_BIT 0x108120
789 #define HC_REG_ATTN_IDX 0x108100
790 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
791 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
792 #define HC_REG_ATTN_NUM_P0 0x108038
793 #define HC_REG_ATTN_NUM_P1 0x10803c
794 #define HC_REG_COMMAND_REG 0x108180
795 #define HC_REG_CONFIG_0 0x108000
796 #define HC_REG_CONFIG_1 0x108004
797 #define HC_REG_FUNC_NUM_P0 0x1080ac
798 #define HC_REG_FUNC_NUM_P1 0x1080b0
799 /* [RW 3] Parity mask register #0 read/write */
800 #define HC_REG_HC_PRTY_MASK 0x1080a0
801 /* [R 3] Parity register #0 read */
802 #define HC_REG_HC_PRTY_STS 0x108094
803 /* [RC 3] Parity register #0 read clear */
804 #define HC_REG_HC_PRTY_STS_CLR 0x108098
805 #define HC_REG_INT_MASK 0x108108
806 #define HC_REG_LEADING_EDGE_0 0x108040
807 #define HC_REG_LEADING_EDGE_1 0x108048
808 #define HC_REG_MAIN_MEMORY 0x108800
809 #define HC_REG_MAIN_MEMORY_SIZE 152
810 #define HC_REG_P0_PROD_CONS 0x108200
811 #define HC_REG_P1_PROD_CONS 0x108400
812 #define HC_REG_PBA_COMMAND 0x108140
813 #define HC_REG_PCI_CONFIG_0 0x108010
814 #define HC_REG_PCI_CONFIG_1 0x108014
815 #define HC_REG_STATISTIC_COUNTERS 0x109000
816 #define HC_REG_TRAILING_EDGE_0 0x108044
817 #define HC_REG_TRAILING_EDGE_1 0x10804c
818 #define HC_REG_UC_RAM_ADDR_0 0x108028
819 #define HC_REG_UC_RAM_ADDR_1 0x108030
820 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
821 #define HC_REG_VQID_0 0x108008
822 #define HC_REG_VQID_1 0x10800c
823 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
824 #define IGU_REG_ATTENTION_ACK_BITS 0x130108
825 /* [R 4] Debug: attn_fsm */
826 #define IGU_REG_ATTN_FSM 0x130054
827 #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
828 #define IGU_REG_ATTN_MSG_ADDR_L 0x130120
829 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
830 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
831 * write done didnt receive. */
832 #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
833 #define IGU_REG_BLOCK_CONFIGURATION 0x130000
834 #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
835 #define IGU_REG_COMMAND_REG_CTRL 0x13012c
836 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
837 * is clear. The bits in this registers are set and clear via the producer
838 * command. Data valid only in addresses 0-4. all the rest are zero. */
839 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
840 /* [R 5] Debug: ctrl_fsm */
841 #define IGU_REG_CTRL_FSM 0x130064
842 /* [R 1] data availble for error memory. If this bit is clear do not red
843 * from error_handling_memory. */
844 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
845 /* [R 11] Parity register #0 read */
846 #define IGU_REG_IGU_PRTY_STS 0x13009c
847 /* [R 4] Debug: int_handle_fsm */
848 #define IGU_REG_INT_HANDLE_FSM 0x130050
849 #define IGU_REG_LEADING_EDGE_LATCH 0x130134
850 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
851 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
852 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
853 #define IGU_REG_MAPPING_MEMORY 0x131000
854 #define IGU_REG_MAPPING_MEMORY_SIZE 136
855 #define IGU_REG_PBA_STATUS_LSB 0x130138
856 #define IGU_REG_PBA_STATUS_MSB 0x13013c
857 #define IGU_REG_PCI_PF_MSI_EN 0x130140
858 #define IGU_REG_PCI_PF_MSIX_EN 0x130144
859 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
860 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
861 * pending; 1 = pending. Pendings means interrupt was asserted; and write
862 * done was not received. Data valid only in addresses 0-4. all the rest are
864 #define IGU_REG_PENDING_BITS_STATUS 0x130300
865 #define IGU_REG_PF_CONFIGURATION 0x130154
866 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
867 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
868 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
869 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
870 * - In backward compatible mode; for non default SB; each even line in the
871 * memory holds the U producer and each odd line hold the C producer. The
872 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
873 * last 20 producers are for the DSB for each PF. each PF has five segments
874 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
875 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
876 #define IGU_REG_PROD_CONS_MEMORY 0x132000
877 /* [R 3] Debug: pxp_arb_fsm */
878 #define IGU_REG_PXP_ARB_FSM 0x130068
879 /* [RW 6] Write one for each bit will reset the appropriate memory. When the
880 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
881 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
882 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
883 #define IGU_REG_RESET_MEMORIES 0x130158
884 /* [R 4] Debug: sb_ctrl_fsm */
885 #define IGU_REG_SB_CTRL_FSM 0x13004c
886 #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
887 #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
888 #define IGU_REG_SB_MASK_LSB 0x130164
889 #define IGU_REG_SB_MASK_MSB 0x130168
890 /* [RW 16] Number of command that were dropped without causing an interrupt
891 * due to: read access for WO BAR address; or write access for RO BAR
892 * address or any access for reserved address or PCI function error is set
893 * and address is not MSIX; PBA or cleanup */
894 #define IGU_REG_SILENT_DROP 0x13016c
895 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
896 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
897 * PF; 68-71 number of ATTN messages per PF */
898 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
899 /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
900 * timer mask command arrives. Value must be bigger than 100. */
901 #define IGU_REG_TIMER_MASKING_VALUE 0x13003c
902 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104
903 #define IGU_REG_VF_CONFIGURATION 0x130170
904 /* [WB_R 32] Each bit represent write done pending bits status for that SB
905 * (MSI/MSIX message was sent and write done was not received yet). 0 =
906 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
907 #define IGU_REG_WRITE_DONE_PENDING 0x130480
908 #define MCP_A_REG_MCPR_SCRATCH 0x3a0000
909 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
910 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
911 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
912 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
913 #define MCP_REG_MCPR_NVM_READ 0x86410
914 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
915 #define MCP_REG_MCPR_NVM_WRITE 0x86408
916 #define MCP_REG_MCPR_SCRATCH 0xa0000
917 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
918 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
919 /* [R 32] read first 32 bit after inversion of function 0. mapped as
920 follows: [0] NIG attention for function0; [1] NIG attention for
921 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
922 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
923 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
924 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
925 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
926 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
927 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
928 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
929 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
930 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
931 Parity error; [31] PBF Hw interrupt; */
932 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
933 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
934 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
935 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
936 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
937 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
938 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
939 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
940 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
941 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
942 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
943 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
944 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
945 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
947 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
948 /* [R 32] read second 32 bit after inversion of function 0. mapped as
949 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
950 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
951 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
952 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
953 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
954 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
955 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
956 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
957 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
958 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
959 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
961 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
962 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
963 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
964 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
965 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
966 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
967 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
968 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
969 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
970 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
971 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
972 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
973 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
974 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
975 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
976 /* [R 32] read third 32 bit after inversion of function 0. mapped as
977 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
978 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
979 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
980 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
981 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
982 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
983 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
984 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
985 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
986 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
987 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
989 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
990 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
991 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
992 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
993 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
994 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
995 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
996 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
997 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
998 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
999 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1000 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1001 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1002 timers attn_4 func1; [30] General attn0; [31] General attn1; */
1003 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
1004 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1005 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1006 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1007 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1008 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1009 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1010 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1011 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1012 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1013 Latched timeout attention; [27] GRC Latched reserved access attention;
1014 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1015 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1016 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
1017 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
1018 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1019 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1020 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1021 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1022 General attn13; [12] General attn14; [13] General attn15; [14] General
1023 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1024 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1025 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1026 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1027 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1028 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1029 ump_tx_parity; [31] MCP Latched scpad_parity; */
1030 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
1031 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1032 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1033 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1034 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1035 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
1036 /* [W 14] write to this register results with the clear of the latched
1037 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1038 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1039 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1040 GRC Latched reserved access attention; one in d7 clears Latched
1041 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
1042 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1043 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1044 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1045 from this register return zero */
1046 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
1047 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1048 as follows: [0] NIG attention for function0; [1] NIG attention for
1049 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1050 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1051 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1052 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1053 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1054 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1055 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1056 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1057 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1058 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1059 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1060 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
1061 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
1062 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
1063 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
1064 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
1065 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
1066 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
1067 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1068 as follows: [0] NIG attention for function0; [1] NIG attention for
1069 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1070 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1071 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1072 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1073 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1074 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1075 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1076 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1077 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1078 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1079 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1080 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
1081 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
1082 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
1083 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
1084 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
1085 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
1086 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
1087 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1088 as follows: [0] NIG attention for function0; [1] NIG attention for
1089 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1090 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1091 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1092 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1093 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1094 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1095 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1096 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1097 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1098 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1099 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1100 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
1101 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
1102 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1103 as follows: [0] NIG attention for function0; [1] NIG attention for
1104 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1105 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1106 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1107 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1108 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1109 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1110 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1111 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1112 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1113 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1114 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1115 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
1116 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
1117 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1118 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1119 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1120 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1121 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1122 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1123 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1124 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1125 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1126 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1127 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1128 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1130 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1131 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1132 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1133 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1134 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1135 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1136 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1137 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1138 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1139 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1140 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1141 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1142 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1143 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1145 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1146 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1147 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1148 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1149 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1150 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1151 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1152 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1153 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1154 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1155 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1156 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1157 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1158 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1160 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1161 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1162 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1163 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1164 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1165 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1166 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1167 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1168 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1169 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1170 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1171 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1172 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1173 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1175 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1176 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1177 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1178 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1179 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1180 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1181 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1182 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1183 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1184 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1185 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1186 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1187 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1188 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1190 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1191 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1192 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1193 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1194 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1195 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1196 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1197 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1198 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1199 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1200 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1201 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1202 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1203 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1205 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1206 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1207 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1208 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1209 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1210 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1211 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1212 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1213 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1214 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1215 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1216 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1217 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1218 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1220 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1221 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1222 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1223 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1224 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1225 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1226 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1227 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1228 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1229 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1230 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1231 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1232 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1233 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1235 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1236 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1237 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1238 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1239 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1240 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1241 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1242 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1243 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1244 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1245 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1246 Latched timeout attention; [27] GRC Latched reserved access attention;
1247 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1248 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1249 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1250 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1251 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1252 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1253 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1254 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1255 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1256 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1257 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1258 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1259 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1260 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1261 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1262 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1263 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1264 Latched timeout attention; [27] GRC Latched reserved access attention;
1265 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1266 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1267 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1268 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1269 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1270 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1271 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1272 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1273 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1274 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1275 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1276 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1277 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1278 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1279 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1280 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1281 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1282 Latched timeout attention; [27] GRC Latched reserved access attention;
1283 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1284 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1285 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1286 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1287 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1288 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1289 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1290 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1291 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1292 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1293 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1294 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1295 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1296 Latched timeout attention; [27] GRC Latched reserved access attention;
1297 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1298 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1299 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1300 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1301 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1303 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1304 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1305 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1306 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1307 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1308 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1309 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1310 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1311 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1312 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1313 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1314 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1315 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1316 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1317 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1318 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1319 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1320 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1321 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1322 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1323 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1324 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1325 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1326 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1327 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1328 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1329 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1330 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1331 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1332 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1333 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1334 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1335 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1336 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1337 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1338 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1339 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1340 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1341 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1342 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1343 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1344 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1345 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1346 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1347 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1348 [9:8] = raserved. Zero = mask; one = unmask */
1349 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1350 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1351 /* [RW 1] If set a system kill occurred */
1352 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1353 /* [RW 32] Represent the status of the input vector to the AEU when a system
1354 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1355 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1356 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1357 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1358 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1359 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1360 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1361 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1362 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1363 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1364 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1365 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1367 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1368 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1369 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1370 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1371 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1373 #define MISC_REG_BOND_ID 0xa400
1374 /* [R 8] These bits indicate the metal revision of the chip. This value
1375 starts at 0x00 for each all-layer tape-out and increments by one for each
1377 #define MISC_REG_CHIP_METAL 0xa404
1378 /* [R 16] These bits indicate the part number for the chip. */
1379 #define MISC_REG_CHIP_NUM 0xa408
1380 /* [R 4] These bits indicate the base revision of the chip. This value
1381 starts at 0x0 for the A0 tape-out and increments by one for each
1382 all-layer tape-out. */
1383 #define MISC_REG_CHIP_REV 0xa40c
1384 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1385 32 clients. Each client can be controlled by one driver only. One in each
1386 bit represent that this driver control the appropriate client (Ex: bit 5
1387 is set means this driver control client number 5). addr1 = set; addr0 =
1388 clear; read from both addresses will give the same result = status. write
1389 to address 1 will set a request to control all the clients that their
1390 appropriate bit (in the write command) is set. if the client is free (the
1391 appropriate bit in all the other drivers is clear) one will be written to
1392 that driver register; if the client isn't free the bit will remain zero.
1393 if the appropriate bit is set (the driver request to gain control on a
1394 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1395 interrupt will be asserted). write to address 0 will set a request to
1396 free all the clients that their appropriate bit (in the write command) is
1397 set. if the appropriate bit is clear (the driver request to free a client
1398 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1400 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1401 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1402 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1404 #define MISC_REG_E1HMF_MODE 0xa5f8
1405 /* [RW 32] Debug only: spare RW register reset by core reset */
1406 #define MISC_REG_GENERIC_CR_0 0xa460
1407 #define MISC_REG_GENERIC_CR_1 0xa464
1408 /* [RW 32] Debug only: spare RW register reset by por reset */
1409 #define MISC_REG_GENERIC_POR_1 0xa474
1410 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1411 these bits is written as a '1'; the corresponding SPIO bit will turn off
1412 it's drivers and become an input. This is the reset state of all GPIO
1413 pins. The read value of these bits will be a '1' if that last command
1414 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1415 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1416 as a '1'; the corresponding GPIO bit will drive low. The read value of
1417 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1418 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1419 SET When any of these bits is written as a '1'; the corresponding GPIO
1420 bit will drive high (if it has that capability). The read value of these
1421 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1422 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1423 RO; These bits indicate the read value of each of the eight GPIO pins.
1424 This is the result value of the pin; not the drive value. Writing these
1425 bits will have not effect. */
1426 #define MISC_REG_GPIO 0xa490
1427 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1428 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1429 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1431 #define MISC_REG_GPIO_EVENT_EN 0xa2bc
1432 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1433 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1434 This will acknowledge an interrupt on the falling edge of corresponding
1435 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1436 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1437 register. This will acknowledge an interrupt on the rising edge of
1438 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1439 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1440 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1441 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1442 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1443 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1444 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1445 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1446 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1447 set when the GPIO input does not match the current value in #OLD_VALUE
1449 #define MISC_REG_GPIO_INT 0xa494
1450 /* [R 28] this field hold the last information that caused reserved
1451 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1452 [27:24] the master that caused the attention - according to the following
1453 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1455 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1456 /* [R 28] this field hold the last information that caused timeout
1457 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1458 [27:24] the master that caused the attention - according to the following
1459 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1461 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1462 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1463 access that does not finish within
1464 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1465 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1466 assert it attention output. */
1467 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1468 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1469 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1470 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1471 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1472 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1473 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1474 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1475 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1476 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1477 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1478 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1479 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1480 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1481 connected to RESET input directly. [15] capRetry_en (reset value 0)
1482 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1483 value 0) bit to continuously monitor vco freq (inverted). [17]
1484 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1485 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1486 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1487 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1488 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1489 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1490 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1491 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1492 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1493 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1494 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1496 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1497 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1498 /* [RW 4] Interrupt mask register #0 read/write */
1499 #define MISC_REG_MISC_INT_MASK 0xa388
1500 /* [RW 1] Parity mask register #0 read/write */
1501 #define MISC_REG_MISC_PRTY_MASK 0xa398
1502 /* [R 1] Parity register #0 read */
1503 #define MISC_REG_MISC_PRTY_STS 0xa38c
1504 #define MISC_REG_NIG_WOL_P0 0xa270
1505 #define MISC_REG_NIG_WOL_P1 0xa274
1506 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1508 #define MISC_REG_PCIE_HOT_RESET 0xa618
1509 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1510 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1511 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1512 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1513 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1514 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1515 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1516 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1517 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1518 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1519 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1520 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1521 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1522 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1523 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1524 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1525 testa_en (reset value 0); */
1526 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1527 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1528 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1529 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1530 /* [R 1] Status of 4 port mode enable input pin. */
1531 #define MISC_REG_PORT4MODE_EN 0xa750
1532 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1533 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1534 * the port4mode_en output is equal to bit[1] of this register; [1] -
1535 * Overwrite value. If bit[0] of this register is 1 this is the value that
1536 * receives the port4mode_en output . */
1537 #define MISC_REG_PORT4MODE_EN_OVWR 0xa720
1538 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1539 write/read zero = the specific block is in reset; addr 0-wr- the write
1540 value will be written to the register; addr 1-set - one will be written
1541 to all the bits that have the value of one in the data written (bits that
1542 have the value of zero will not be change) ; addr 2-clear - zero will be
1543 written to all the bits that have the value of one in the data written
1544 (bits that have the value of zero will not be change); addr 3-ignore;
1545 read ignore from all addr except addr 00; inside order of the bits is:
1546 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1547 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1548 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1549 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1550 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1551 rst_pxp_rq_rd_wr; 31:17] reserved */
1552 #define MISC_REG_RESET_REG_2 0xa590
1553 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1554 shared with the driver resides */
1555 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1556 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1557 the corresponding SPIO bit will turn off it's drivers and become an
1558 input. This is the reset state of all SPIO pins. The read value of these
1559 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1560 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1561 is written as a '1'; the corresponding SPIO bit will drive low. The read
1562 value of these bits will be a '1' if that last command (#SET; #CLR; or
1563 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1564 these bits is written as a '1'; the corresponding SPIO bit will drive
1565 high (if it has that capability). The read value of these bits will be a
1566 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1567 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1568 each of the eight SPIO pins. This is the result value of the pin; not the
1569 drive value. Writing these bits will have not effect. Each 8 bits field
1570 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1571 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1572 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1573 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1574 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1575 select VAUX supply. (This is an output pin only; it is not controlled by
1576 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1577 field is not applicable for this pin; only the VALUE fields is relevant -
1578 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1579 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1580 device ID select; read by UMP firmware. */
1581 #define MISC_REG_SPIO 0xa4fc
1582 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1583 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1585 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1586 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1587 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1588 interrupt on the falling edge of corresponding SPIO input (reset value
1589 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1590 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1591 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1592 RO; These bits indicate the old value of the SPIO input value. When the
1593 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1594 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1595 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1596 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1597 RO; These bits indicate the current SPIO interrupt state for each SPIO
1598 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1599 command bit is written. This bit is set when the SPIO input does not
1600 match the current value in #OLD_VALUE (reset value 0). */
1601 #define MISC_REG_SPIO_INT 0xa500
1602 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1603 the counter reached zero and the reload bit
1604 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1605 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1606 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1607 in this register. addres 0 - timer 1; address 1 - timer 2, ... address 7 -
1609 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1610 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1611 loaded; 0-prepare; -unprepare */
1612 #define MISC_REG_UNPREPARED 0xa424
1613 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1614 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1615 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1616 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1617 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1618 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1619 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
1620 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1621 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1622 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1623 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1624 /* [RW 1] Input enable for RX_BMAC0 IF */
1625 #define NIG_REG_BMAC0_IN_EN 0x100ac
1626 /* [RW 1] output enable for TX_BMAC0 IF */
1627 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1628 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1629 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1630 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1631 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1632 /* [RW 1] output enable for RX BRB1 port0 IF */
1633 #define NIG_REG_BRB0_OUT_EN 0x100f8
1634 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1635 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1636 /* [RW 1] output enable for RX BRB1 port1 IF */
1637 #define NIG_REG_BRB1_OUT_EN 0x100fc
1638 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1639 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1640 /* [RW 1] output enable for RX BRB1 LP IF */
1641 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1642 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1643 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1644 72:73]-vnic_num; 81:74]-sideband_info */
1645 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1646 /* [RW 1] Input enable for TX Debug packet */
1647 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1648 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1649 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1650 First packet may be deleted from the middle. And last packet will be
1651 always deleted till the end. */
1652 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1653 /* [RW 1] Output enable to EMAC0 */
1654 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1655 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1656 to emac for port0; other way to bmac for port0 */
1657 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1658 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1659 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1660 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1661 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1662 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1663 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1664 /* [RW 1] Input enable for RX_EMAC0 IF */
1665 #define NIG_REG_EMAC0_IN_EN 0x100a4
1666 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1667 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1668 /* [R 1] status from emac0. This bit is set when MDINT from either the
1669 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1670 be cleared in the attached PHY device that is driving the MINT pin. */
1671 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1672 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1673 are described in appendix A. In order to access the BMAC0 registers; the
1674 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1675 added to each BMAC register offset */
1676 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1677 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1678 are described in appendix A. In order to access the BMAC0 registers; the
1679 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1680 added to each BMAC register offset */
1681 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1682 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1683 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1684 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1685 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1686 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1687 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
1688 logic for interrupts must be used. Enable per bit of interrupt of
1689 ~latch_status.latch_status */
1690 #define NIG_REG_LATCH_BC_0 0x16210
1691 /* [RW 27] Latch for each interrupt from Unicore.b[0]
1692 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
1693 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
1694 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
1695 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
1696 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
1697 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
1698 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
1699 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
1700 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
1701 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
1702 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
1703 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
1704 #define NIG_REG_LATCH_STATUS_0 0x18000
1705 /* [RW 1] led 10g for port 0 */
1706 #define NIG_REG_LED_10G_P0 0x10320
1707 /* [RW 1] led 10g for port 1 */
1708 #define NIG_REG_LED_10G_P1 0x10324
1709 /* [RW 1] Port0: This bit is set to enable the use of the
1710 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1711 defined below. If this bit is cleared; then the blink rate will be about
1713 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1714 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1715 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1716 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1717 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1718 /* [RW 1] Port0: If set along with the
1719 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1720 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1721 bit; the Traffic LED will blink with the blink rate specified in
1722 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1723 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1725 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1726 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1727 Traffic LED will then be controlled via bit ~nig_registers_
1728 led_control_traffic_p0.led_control_traffic_p0 and bit
1729 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1730 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1731 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1732 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1733 set; the LED will blink with blink rate specified in
1734 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1735 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1737 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1738 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1739 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1740 #define NIG_REG_LED_MODE_P0 0x102f0
1741 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1742 tsdm enable; b2- usdm enable */
1743 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
1744 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
1745 /* [RW 1] SAFC enable for port0. This register may get 1 only when
1746 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1748 #define NIG_REG_LLFC_ENABLE_0 0x16208
1749 #define NIG_REG_LLFC_ENABLE_1 0x1620c
1750 /* [RW 16] classes are high-priority for port0 */
1751 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
1752 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
1753 /* [RW 16] classes are low-priority for port0 */
1754 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
1755 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
1756 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1757 #define NIG_REG_LLFC_OUT_EN_0 0x160c8
1758 #define NIG_REG_LLFC_OUT_EN_1 0x160cc
1759 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1760 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
1761 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1762 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
1763 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1764 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1765 /* [RW 2] Determine the classification participants. 0: no classification.1:
1766 classification upon VLAN id. 2: classification upon MAC address. 3:
1767 classification upon both VLAN id & MAC addr. */
1768 #define NIG_REG_LLH0_CLS_TYPE 0x16080
1769 /* [RW 32] cm header for llh0 */
1770 #define NIG_REG_LLH0_CM_HEADER 0x1007c
1771 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1772 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1773 /* [RW 16] destination TCP address 1. The LLH will look for this address in
1774 all incoming packets. */
1775 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
1776 /* [RW 16] destination UDP address 1 The LLH will look for this address in
1777 all incoming packets. */
1778 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
1779 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
1780 /* [RW 8] event id for llh0 */
1781 #define NIG_REG_LLH0_EVENT_ID 0x10084
1782 #define NIG_REG_LLH0_FUNC_EN 0x160fc
1783 #define NIG_REG_LLH0_FUNC_MEM 0x16180
1784 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
1785 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1786 /* [RW 1] Determine the IP version to look for in
1787 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1788 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1789 /* [RW 1] t bit for llh0 */
1790 #define NIG_REG_LLH0_T_BIT 0x10074
1791 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1792 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
1793 /* [RW 8] init credit counter for port0 in LLH */
1794 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1795 #define NIG_REG_LLH0_XCM_MASK 0x10130
1796 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
1797 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1798 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1799 /* [RW 2] Determine the classification participants. 0: no classification.1:
1800 classification upon VLAN id. 2: classification upon MAC address. 3:
1801 classification upon both VLAN id & MAC addr. */
1802 #define NIG_REG_LLH1_CLS_TYPE 0x16084
1803 /* [RW 32] cm header for llh1 */
1804 #define NIG_REG_LLH1_CM_HEADER 0x10080
1805 #define NIG_REG_LLH1_ERROR_MASK 0x10090
1806 /* [RW 8] event id for llh1 */
1807 #define NIG_REG_LLH1_EVENT_ID 0x10088
1808 #define NIG_REG_LLH1_FUNC_MEM 0x161c0
1809 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
1810 #define NIG_REG_LLH1_FUNC_MEM_SIZE 16
1811 /* [RW 8] init credit counter for port1 in LLH */
1812 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1813 #define NIG_REG_LLH1_XCM_MASK 0x10134
1814 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
1816 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
1817 /* [RW 1] When this bit is set; the LLH will classify the packet before
1818 sending it to the BRB or calculating WoL on it. */
1819 #define NIG_REG_LLH_MF_MODE 0x16024
1820 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1821 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1822 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1823 #define NIG_REG_NIG_EMAC0_EN 0x1003c
1824 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1825 #define NIG_REG_NIG_EMAC1_EN 0x10040
1826 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1827 EMAC0 to strip the CRC from the ingress packets. */
1828 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1829 /* [R 32] Interrupt register #0 read */
1830 #define NIG_REG_NIG_INT_STS_0 0x103b0
1831 #define NIG_REG_NIG_INT_STS_1 0x103c0
1832 /* [R 32] Legacy E1 and E1H location for parity error status register. */
1833 #define NIG_REG_NIG_PRTY_STS 0x103d0
1834 /* [R 32] Parity register #0 read */
1835 #define NIG_REG_NIG_PRTY_STS_0 0x183bc
1836 #define NIG_REG_NIG_PRTY_STS_1 0x183cc
1837 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
1838 * Ethernet header. */
1839 #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
1840 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
1841 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
1842 * disabled when this bit is set. */
1843 #define NIG_REG_P0_HWPFC_ENABLE 0x18078
1844 #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
1845 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
1846 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
1847 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
1848 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
1849 * priority field is extracted from the outer-most VLAN in receive packet.
1850 * Only COS 0 and COS 1 are supported in E2. */
1851 #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
1852 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
1853 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
1854 * than one bit may be set; allowing multiple priorities to be mapped to one
1856 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
1857 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
1858 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
1859 * than one bit may be set; allowing multiple priorities to be mapped to one
1861 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
1862 /* [RW 15] Specify which of the credit registers the client is to be mapped
1863 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
1864 * clients that are not subject to WFQ credit blocking - their
1865 * specifications here are not used. */
1866 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
1867 /* [RW 5] Specify whether the client competes directly in the strict
1868 * priority arbiter. The bits are mapped according to client ID (client IDs
1869 * are defined in tx_arb_priority_client). Default value is set to enable
1870 * strict priorities for clients 0-2 -- management and debug traffic. */
1871 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
1872 /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
1873 * bits are mapped according to client ID (client IDs are defined in
1874 * tx_arb_priority_client). Default value is 0 for not using WFQ credit
1876 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
1877 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
1879 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
1880 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
1881 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
1882 * when it is time to increment. */
1883 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
1884 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
1885 /* [RW 12] Specify the number of strict priority arbitration slots between
1886 * two round-robin arbitration slots to avoid starvation. A value of 0 means
1887 * no strict priority cycles - the strict priority with anti-starvation
1888 * arbiter becomes a round-robin arbiter. */
1889 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
1890 /* [RW 15] Specify the client number to be assigned to each priority of the
1891 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
1892 * are for priority 0 client; bits [14:12] are for priority 4 client. The
1893 * clients are assigned the following IDs: 0-management; 1-debug traffic
1894 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
1895 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
1896 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
1897 * traffic at priority 3; and COS1 traffic at priority 4. */
1898 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
1899 #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
1900 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
1901 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
1902 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
1903 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
1904 * priority field is extracted from the outer-most VLAN in receive packet.
1905 * Only COS 0 and COS 1 are supported in E2. */
1906 #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
1907 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
1908 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
1909 * than one bit may be set; allowing multiple priorities to be mapped to one
1911 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
1912 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
1913 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
1914 * than one bit may be set; allowing multiple priorities to be mapped to one
1916 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
1917 /* [RW 1] Pause enable for port0. This register may get 1 only when
1918 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
1920 #define NIG_REG_PAUSE_ENABLE_0 0x160c0
1921 #define NIG_REG_PAUSE_ENABLE_1 0x160c4
1922 /* [RW 1] Input enable for RX PBF LP IF */
1923 #define NIG_REG_PBF_LB_IN_EN 0x100b4
1924 /* [RW 1] Value of this register will be transmitted to port swap when
1925 ~nig_registers_strap_override.strap_override =1 */
1926 #define NIG_REG_PORT_SWAP 0x10394
1927 /* [RW 1] PPP enable for port0. This register may get 1 only when
1928 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
1930 #define NIG_REG_PPP_ENABLE_0 0x160b0
1931 #define NIG_REG_PPP_ENABLE_1 0x160b4
1932 /* [RW 1] output enable for RX parser descriptor IF */
1933 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
1934 /* [RW 1] Input enable for RX parser request IF */
1935 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
1936 /* [RW 5] control to serdes - CL45 DEVAD */
1937 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
1938 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
1939 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
1940 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1941 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1942 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1943 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1944 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1946 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1947 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
1949 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
1950 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1951 between 1024 and 1522 bytes for port0 */
1952 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
1953 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1954 between 1523 bytes and above for port0 */
1955 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
1956 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1958 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
1959 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1960 between 1024 and 1522 bytes for port1 */
1961 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
1962 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1963 between 1523 bytes and above for port1 */
1964 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
1965 /* [WB_R 64] Rx statistics : User octets received for LP */
1966 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
1967 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1968 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
1969 /* [RW 1] port swap mux selection. If this register equal to 0 then port
1970 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
1971 ort swap is equal to ~nig_registers_port_swap.port_swap */
1972 #define NIG_REG_STRAP_OVERRIDE 0x10398
1973 /* [RW 1] output enable for RX_XCM0 IF */
1974 #define NIG_REG_XCM0_OUT_EN 0x100f0
1975 /* [RW 1] output enable for RX_XCM1 IF */
1976 #define NIG_REG_XCM1_OUT_EN 0x100f4
1977 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
1978 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
1979 /* [RW 5] control to xgxs - CL45 DEVAD */
1980 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
1981 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
1982 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
1983 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1984 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1985 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
1986 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
1987 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
1988 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
1989 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
1990 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
1991 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
1992 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
1993 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
1994 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
1995 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
1996 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
1997 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
1998 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
1999 #define PBF_REG_COS0_UPPER_BOUND 0x15c05c
2000 /* [RW 31] The weight of COS0 in the ETS command arbiter. */
2001 #define PBF_REG_COS0_WEIGHT 0x15c054
2002 /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2003 #define PBF_REG_COS1_UPPER_BOUND 0x15c060
2004 /* [RW 31] The weight of COS1 in the ETS command arbiter. */
2005 #define PBF_REG_COS1_WEIGHT 0x15c058
2006 /* [RW 1] Disable processing further tasks from port 0 (after ending the
2007 current task in process). */
2008 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
2009 /* [RW 1] Disable processing further tasks from port 1 (after ending the
2010 current task in process). */
2011 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
2012 /* [RW 1] Disable processing further tasks from port 4 (after ending the
2013 current task in process). */
2014 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
2015 #define PBF_REG_DISABLE_PF 0x1402e8
2016 /* [RW 1] Indicates that ETS is performed between the COSes in the command
2017 * arbiter. If reset strict priority w/ anti-starvation will be performed
2019 #define PBF_REG_ETS_ENABLED 0x15c050
2020 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2021 * Ethernet header. */
2022 #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
2023 /* [RW 1] Indicates which COS is conncted to the highest priority in the
2024 * command arbiter. */
2025 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
2026 #define PBF_REG_IF_ENABLE_REG 0x140044
2027 /* [RW 1] Init bit. When set the initial credits are copied to the credit
2028 registers (except the port credits). Should be set and then reset after
2029 the configuration of the block has ended. */
2030 #define PBF_REG_INIT 0x140000
2031 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2032 copied to the credit register. Should be set and then reset after the
2033 configuration of the port has ended. */
2034 #define PBF_REG_INIT_P0 0x140004
2035 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2036 copied to the credit register. Should be set and then reset after the
2037 configuration of the port has ended. */
2038 #define PBF_REG_INIT_P1 0x140008
2039 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2040 copied to the credit register. Should be set and then reset after the
2041 configuration of the port has ended. */
2042 #define PBF_REG_INIT_P4 0x14000c
2043 /* [RW 1] Enable for mac interface 0. */
2044 #define PBF_REG_MAC_IF0_ENABLE 0x140030
2045 /* [RW 1] Enable for mac interface 1. */
2046 #define PBF_REG_MAC_IF1_ENABLE 0x140034
2047 /* [RW 1] Enable for the loopback interface. */
2048 #define PBF_REG_MAC_LB_ENABLE 0x140040
2049 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2050 #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
2051 /* [RW 16] The number of strict priority arbitration slots between 2 RR
2052 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2053 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2054 #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
2055 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2057 #define PBF_REG_P0_ARB_THRSH 0x1400e4
2058 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2059 #define PBF_REG_P0_CREDIT 0x140200
2060 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2062 #define PBF_REG_P0_INIT_CRD 0x1400d0
2063 /* [RW 1] Indication that pause is enabled for port 0. */
2064 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
2065 /* [R 8] Number of tasks in port 0 task queue. */
2066 #define PBF_REG_P0_TASK_CNT 0x140204
2067 /* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
2068 #define PBF_REG_P1_CREDIT 0x140208
2069 /* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
2071 #define PBF_REG_P1_INIT_CRD 0x1400d4
2072 /* [R 8] Number of tasks in port 1 task queue. */
2073 #define PBF_REG_P1_TASK_CNT 0x14020c
2074 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2075 #define PBF_REG_P4_CREDIT 0x140210
2076 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2078 #define PBF_REG_P4_INIT_CRD 0x1400e0
2079 /* [R 8] Number of tasks in port 4 task queue. */
2080 #define PBF_REG_P4_TASK_CNT 0x140214
2081 /* [RW 5] Interrupt mask register #0 read/write */
2082 #define PBF_REG_PBF_INT_MASK 0x1401d4
2083 /* [R 5] Interrupt register #0 read */
2084 #define PBF_REG_PBF_INT_STS 0x1401c8
2085 #define PB_REG_CONTROL 0
2086 /* [RW 2] Interrupt mask register #0 read/write */
2087 #define PB_REG_PB_INT_MASK 0x28
2088 /* [R 2] Interrupt register #0 read */
2089 #define PB_REG_PB_INT_STS 0x1c
2090 /* [RW 4] Parity mask register #0 read/write */
2091 #define PB_REG_PB_PRTY_MASK 0x38
2092 /* [R 4] Parity register #0 read */
2093 #define PB_REG_PB_PRTY_STS 0x2c
2094 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2095 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
2096 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
2097 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
2098 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
2099 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
2100 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2101 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
2102 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
2103 /* [R 8] Config space A attention dirty bits. Each bit indicates that the
2104 * corresponding PF generates config space A attention. Set by PXP. Reset by
2105 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2106 * from both paths. */
2107 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
2108 /* [R 8] Config space B attention dirty bits. Each bit indicates that the
2109 * corresponding PF generates config space B attention. Set by PXP. Reset by
2110 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2111 * from both paths. */
2112 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
2113 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2115 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
2116 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
2117 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
2118 #define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
2119 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
2121 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
2122 /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
2123 #define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
2124 /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
2125 #define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
2126 /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
2127 #define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
2128 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2129 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
2130 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
2131 * that the FLR register of the corresponding PF was set. Set by PXP. Reset
2132 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
2133 * from both paths. */
2134 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
2135 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
2136 * to a bit in this register in order to clear the corresponding bit in
2137 * flr_request_pf_7_0 register. Note: register contains bits from both
2139 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
2140 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
2141 * indicates that the FLR register of the corresponding VF was set. Set by
2142 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
2143 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
2144 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
2145 * indicates that the FLR register of the corresponding VF was set. Set by
2146 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
2147 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
2148 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
2149 * indicates that the FLR register of the corresponding VF was set. Set by
2150 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
2151 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
2152 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
2153 * indicates that the FLR register of the corresponding VF was set. Set by
2154 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
2155 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
2156 /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
2157 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
2158 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
2159 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
2160 * an uncorrectable error. Bit 4 - Completion with Configuration Request
2161 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
2162 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
2163 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
2164 * and pcie_rx_last not asserted. */
2165 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
2166 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
2167 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
2168 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
2169 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
2170 /* [R 9] Interrupt register #0 read */
2171 #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
2172 /* [RC 9] Interrupt register #0 read clear */
2173 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
2174 /* [R 2] Parity register #0 read */
2175 #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
2176 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
2177 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
2178 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
2179 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
2180 * if there was a completion error since the last time this register was
2182 #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
2183 /* [R 18] Details of first ATS Translation Completion request received with
2184 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
2185 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
2186 * unsupported request. 2 - completer abort. 3 - Illegal value for this
2187 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
2188 * completion error since the last time this register was cleared. */
2189 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
2190 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
2191 * a bit in this register in order to clear the corresponding bit in
2192 * shadow_bme_pf_7_0 register. MCP should never use this unless a
2193 * work-around is needed. Note: register contains bits from both paths. */
2194 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
2195 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
2196 * VF enable register of the corresponding PF is written to 0 and was
2197 * previously 1. Set by PXP. Reset by MCP writing 1 to
2198 * sr_iov_disabled_request_clr. Note: register contains bits from both
2200 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
2201 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
2202 * completion did not return yet. 1 - tag is unused. Same functionality as
2203 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
2204 #define PGLUE_B_REG_TAGS_63_32 0x9244
2205 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
2207 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
2208 /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
2209 #define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
2210 /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
2211 #define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
2212 /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
2213 #define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
2214 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2215 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
2216 /* [R 32] Address [31:0] of first read request not submitted due to error */
2217 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
2218 /* [R 32] Address [63:32] of first read request not submitted due to error */
2219 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
2220 /* [R 31] Details of first read request not submitted due to error. [4:0]
2221 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
2222 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
2224 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
2225 /* [R 26] Details of first read request not submitted due to error. [15:0]
2226 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2227 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2228 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2229 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2230 * indicates if there was a request not submitted due to error since the
2231 * last time this register was cleared. */
2232 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
2233 /* [R 32] Address [31:0] of first write request not submitted due to error */
2234 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
2235 /* [R 32] Address [63:32] of first write request not submitted due to error */
2236 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
2237 /* [R 31] Details of first write request not submitted due to error. [4:0]
2238 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
2240 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
2241 /* [R 26] Details of first write request not submitted due to error. [15:0]
2242 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2243 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2244 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2245 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2246 * indicates if there was a request not submitted due to error since the
2247 * last time this register was cleared. */
2248 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
2249 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
2250 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
2251 * value (Byte resolution address). */
2252 #define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
2253 #define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
2254 #define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
2255 #define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
2256 #define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
2257 #define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
2258 #define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
2259 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
2261 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
2262 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
2264 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
2265 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
2267 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
2268 /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
2269 #define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
2270 /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
2271 #define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
2272 /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
2273 #define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
2274 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2275 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
2276 /* [R 26] Details of first target VF request accessing VF GRC space that
2277 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
2278 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
2279 * request accessing VF GRC space that failed permission check since the
2280 * last time this register was cleared. Permission checks are: function
2281 * permission; R/W permission; address range permission. */
2282 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
2283 /* [R 31] Details of first target VF request with length violation (too many
2284 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
2285 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
2286 * valid - indicates if there was a request with length violation since the
2287 * last time this register was cleared. Length violations: length of more
2288 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
2289 * length is more than 1 DW. */
2290 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
2291 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
2292 * that there was a completion with uncorrectable error for the
2293 * corresponding PF. Set by PXP. Reset by MCP writing 1 to
2294 * was_error_pf_7_0_clr. */
2295 #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
2296 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
2297 * to a bit in this register in order to clear the corresponding bit in
2298 * flr_request_pf_7_0 register. */
2299 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
2300 /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
2301 * indicates that there was a completion with uncorrectable error for the
2302 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2303 * was_error_vf_127_96_clr. */
2304 #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
2305 /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
2306 * writes 1 to a bit in this register in order to clear the corresponding
2307 * bit in was_error_vf_127_96 register. */
2308 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
2309 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
2310 * indicates that there was a completion with uncorrectable error for the
2311 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2312 * was_error_vf_31_0_clr. */
2313 #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
2314 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
2315 * 1 to a bit in this register in order to clear the corresponding bit in
2316 * was_error_vf_31_0 register. */
2317 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
2318 /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
2319 * indicates that there was a completion with uncorrectable error for the
2320 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2321 * was_error_vf_63_32_clr. */
2322 #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
2323 /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
2324 * 1 to a bit in this register in order to clear the corresponding bit in
2325 * was_error_vf_63_32 register. */
2326 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
2327 /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
2328 * indicates that there was a completion with uncorrectable error for the
2329 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2330 * was_error_vf_95_64_clr. */
2331 #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
2332 /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
2333 * 1 to a bit in this register in order to clear the corresponding bit in
2334 * was_error_vf_95_64 register. */
2335 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
2336 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
2338 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
2339 /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
2340 #define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
2341 /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
2342 #define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
2343 /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
2344 #define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
2345 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2346 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
2347 #define PRS_REG_A_PRSU_20 0x40134
2348 /* [R 8] debug only: CFC load request current credit. Transaction based. */
2349 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
2350 /* [R 8] debug only: CFC search request current credit. Transaction based. */
2351 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
2352 /* [RW 6] The initial credit for the search message to the CFC interface.
2353 Credit is transaction based. */
2354 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
2355 /* [RW 24] CID for port 0 if no match */
2356 #define PRS_REG_CID_PORT_0 0x400fc
2357 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2358 load response is reset and packet type is 0. Used in packet start message
2360 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
2361 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
2362 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
2363 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
2364 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
2365 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
2366 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2367 load response is set and packet type is 0. Used in packet start message
2369 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
2370 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
2371 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
2372 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
2373 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
2374 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
2375 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
2376 Used in packet start message to TCM. */
2377 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
2378 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
2379 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
2380 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
2381 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
2383 #define PRS_REG_CM_HDR_TYPE_0 0x40078
2384 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
2385 #define PRS_REG_CM_HDR_TYPE_2 0x40080
2386 #define PRS_REG_CM_HDR_TYPE_3 0x40084
2387 #define PRS_REG_CM_HDR_TYPE_4 0x40088
2388 /* [RW 32] The CM header in case there was not a match on the connection */
2389 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
2390 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
2391 #define PRS_REG_E1HOV_MODE 0x401c8
2392 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
2393 start message to TCM. */
2394 #define PRS_REG_EVENT_ID_1 0x40054
2395 #define PRS_REG_EVENT_ID_2 0x40058
2396 #define PRS_REG_EVENT_ID_3 0x4005c
2397 /* [RW 16] The Ethernet type value for FCoE */
2398 #define PRS_REG_FCOE_TYPE 0x401d0
2399 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
2400 load request message. */
2401 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
2402 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
2403 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
2404 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
2405 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
2406 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
2407 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
2408 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
2409 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2410 * Ethernet header. */
2411 #define PRS_REG_HDRS_AFTER_BASIC 0x40238
2412 /* [RW 4] The increment value to send in the CFC load request message */
2413 #define PRS_REG_INC_VALUE 0x40048
2414 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2415 #define PRS_REG_MUST_HAVE_HDRS 0x40254
2416 #define PRS_REG_NIC_MODE 0x40138
2417 /* [RW 8] The 8-bit event ID for cases where there is no match on the
2418 connection. Used in packet start message to TCM. */
2419 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
2420 /* [ST 24] The number of input CFC flush packets */
2421 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
2422 /* [ST 32] The number of cycles the Parser halted its operation since it
2423 could not allocate the next serial number */
2424 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
2425 /* [ST 24] The number of input packets */
2426 #define PRS_REG_NUM_OF_PACKETS 0x40124
2427 /* [ST 24] The number of input transparent flush packets */
2428 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
2429 /* [RW 8] Context region for received Ethernet packet with a match and
2430 packet type 0. Used in CFC load request message */
2431 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
2432 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
2433 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
2434 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
2435 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
2436 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
2437 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
2438 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
2439 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
2440 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
2441 /* [R 2] debug only: Number of pending requests for header parsing. */
2442 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
2443 /* [R 1] Interrupt register #0 read */
2444 #define PRS_REG_PRS_INT_STS 0x40188
2445 /* [RW 8] Parity mask register #0 read/write */
2446 #define PRS_REG_PRS_PRTY_MASK 0x401a4
2447 /* [R 8] Parity register #0 read */
2448 #define PRS_REG_PRS_PRTY_STS 0x40198
2449 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
2451 #define PRS_REG_PURE_REGIONS 0x40024
2452 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
2453 serail number was released by SDM but cannot be used because a previous
2454 serial number was not released. */
2455 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
2456 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
2457 serail number was released by SDM but cannot be used because a previous
2458 serial number was not released. */
2459 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
2460 /* [R 4] debug only: SRC current credit. Transaction based. */
2461 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
2462 /* [R 8] debug only: TCM current credit. Cycle based. */
2463 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
2464 /* [R 8] debug only: TSDM current credit. Transaction based. */
2465 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
2466 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
2467 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
2468 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
2469 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
2470 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
2471 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
2472 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
2473 /* [R 6] Debug only: Number of used entries in the data FIFO */
2474 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
2475 /* [R 7] Debug only: Number of used entries in the header FIFO */
2476 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
2477 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
2478 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
2479 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
2480 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
2481 #define PXP2_REG_PGL_CONTROL0 0x120490
2482 #define PXP2_REG_PGL_CONTROL1 0x120514
2483 #define PXP2_REG_PGL_DEBUG 0x120520
2484 /* [RW 32] third dword data of expansion rom request. this register is
2485 special. reading from it provides a vector outstanding read requests. if
2486 a bit is zero it means that a read request on the corresponding tag did
2487 not finish yet (not all completions have arrived for it) */
2488 #define PXP2_REG_PGL_EXP_ROM2 0x120808
2489 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
2490 its[15:0]-address */
2491 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
2492 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
2493 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
2494 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
2495 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
2496 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
2497 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
2498 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
2499 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
2500 its[15:0]-address */
2501 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
2502 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
2503 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
2504 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
2505 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
2506 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
2507 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
2508 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
2509 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
2510 its[15:0]-address */
2511 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
2512 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
2513 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
2514 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
2515 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
2516 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
2517 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
2518 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
2519 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
2520 its[15:0]-address */
2521 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
2522 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
2523 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
2524 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
2525 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
2526 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
2527 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
2528 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
2529 /* [RW 3] this field allows one function to pretend being another function
2530 when accessing any BAR mapped resource within the device. the value of
2531 the field is the number of the function that will be accessed
2532 effectively. after software write to this bit it must read it in order to
2533 know that the new value is updated */
2534 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
2535 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
2536 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
2537 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
2538 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
2539 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
2540 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
2541 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
2542 /* [R 1] this bit indicates that a read request was blocked because of
2543 bus_master_en was deasserted */
2544 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
2545 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
2546 /* [R 18] debug only */
2547 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
2548 /* [R 1] this bit indicates that a write request was blocked because of
2549 bus_master_en was deasserted */
2550 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
2551 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
2552 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2553 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2554 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
2555 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2556 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
2557 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
2558 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
2559 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
2560 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
2561 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
2562 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
2563 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2564 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2565 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
2566 #define PXP2_REG_PSWRQ_BW_L28 0x120318
2567 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
2568 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
2569 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
2570 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
2571 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
2572 #define PXP2_REG_PSWRQ_BW_RD 0x120324
2573 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
2574 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2575 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
2576 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
2577 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2578 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
2579 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
2580 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
2581 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
2582 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
2583 #define PXP2_REG_PSWRQ_BW_WR 0x120328
2584 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
2585 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
2586 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
2587 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
2588 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
2589 /* [RW 32] Interrupt mask register #0 read/write */
2590 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
2591 /* [R 32] Interrupt register #0 read */
2592 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
2593 #define PXP2_REG_PXP2_INT_STS_1 0x120608
2594 /* [RC 32] Interrupt register #0 read clear */
2595 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
2596 /* [RW 32] Parity mask register #0 read/write */
2597 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
2598 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
2599 /* [R 32] Parity register #0 read */
2600 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
2601 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
2602 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
2603 indication about backpressure) */
2604 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
2605 /* [R 8] Debug only: The blocks counter - number of unused block ids */
2606 #define PXP2_REG_RD_BLK_CNT 0x120418
2607 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
2608 Must be bigger than 6. Normally should not be changed. */
2609 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
2610 /* [RW 2] CDU byte swapping mode configuration for master read requests */
2611 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
2612 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
2613 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
2614 /* [R 1] PSWRD internal memories initialization is done */
2615 #define PXP2_REG_RD_INIT_DONE 0x120370
2616 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2617 allocated for vq10 */
2618 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
2619 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2620 allocated for vq11 */
2621 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
2622 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2623 allocated for vq17 */
2624 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
2625 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2626 allocated for vq18 */
2627 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
2628 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2629 allocated for vq19 */
2630 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
2631 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2632 allocated for vq22 */
2633 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
2634 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2635 allocated for vq25 */
2636 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
2637 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2638 allocated for vq6 */
2639 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
2640 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2641 allocated for vq9 */
2642 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
2643 /* [RW 2] PBF byte swapping mode configuration for master read requests */
2644 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
2645 /* [R 1] Debug only: Indication if delivery ports are idle */
2646 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
2647 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
2648 /* [RW 2] QM byte swapping mode configuration for master read requests */
2649 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
2650 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
2651 #define PXP2_REG_RD_SR_CNT 0x120414
2652 /* [RW 2] SRC byte swapping mode configuration for master read requests */
2653 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
2654 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
2655 be bigger than 1. Normally should not be changed. */
2656 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
2657 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
2658 #define PXP2_REG_RD_START_INIT 0x12036c
2659 /* [RW 2] TM byte swapping mode configuration for master read requests */
2660 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
2661 /* [RW 10] Bandwidth addition to VQ0 write requests */
2662 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
2663 /* [RW 10] Bandwidth addition to VQ12 read requests */
2664 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
2665 /* [RW 10] Bandwidth addition to VQ13 read requests */
2666 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
2667 /* [RW 10] Bandwidth addition to VQ14 read requests */
2668 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
2669 /* [RW 10] Bandwidth addition to VQ15 read requests */
2670 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
2671 /* [RW 10] Bandwidth addition to VQ16 read requests */
2672 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
2673 /* [RW 10] Bandwidth addition to VQ17 read requests */
2674 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
2675 /* [RW 10] Bandwidth addition to VQ18 read requests */
2676 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
2677 /* [RW 10] Bandwidth addition to VQ19 read requests */
2678 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
2679 /* [RW 10] Bandwidth addition to VQ20 read requests */
2680 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
2681 /* [RW 10] Bandwidth addition to VQ22 read requests */
2682 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
2683 /* [RW 10] Bandwidth addition to VQ23 read requests */
2684 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
2685 /* [RW 10] Bandwidth addition to VQ24 read requests */
2686 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
2687 /* [RW 10] Bandwidth addition to VQ25 read requests */
2688 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
2689 /* [RW 10] Bandwidth addition to VQ26 read requests */
2690 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
2691 /* [RW 10] Bandwidth addition to VQ27 read requests */
2692 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
2693 /* [RW 10] Bandwidth addition to VQ4 read requests */
2694 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
2695 /* [RW 10] Bandwidth addition to VQ5 read requests */
2696 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
2697 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
2698 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
2699 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
2700 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
2701 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
2702 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
2703 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
2704 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
2705 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
2706 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
2707 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
2708 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
2709 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
2710 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
2711 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
2712 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
2713 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
2714 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
2715 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
2716 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
2717 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
2718 #define PXP2_REG_RQ_BW_RD_L22 0x120300
2719 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
2720 #define PXP2_REG_RQ_BW_RD_L23 0x120304
2721 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
2722 #define PXP2_REG_RQ_BW_RD_L24 0x120308
2723 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
2724 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
2725 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
2726 #define PXP2_REG_RQ_BW_RD_L26 0x120310
2727 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
2728 #define PXP2_REG_RQ_BW_RD_L27 0x120314
2729 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
2730 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
2731 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
2732 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
2733 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
2734 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
2735 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
2736 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
2737 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
2738 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
2739 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
2740 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
2741 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
2742 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
2743 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
2744 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
2745 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
2746 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
2747 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
2748 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
2749 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
2750 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
2751 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
2752 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
2753 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
2754 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
2755 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
2756 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
2757 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
2758 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
2759 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
2760 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
2761 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
2762 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
2763 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
2764 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
2765 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
2766 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
2767 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
2768 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
2769 /* [RW 10] Bandwidth addition to VQ29 write requests */
2770 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
2771 /* [RW 10] Bandwidth addition to VQ30 write requests */
2772 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
2773 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
2774 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
2775 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
2776 #define PXP2_REG_RQ_BW_WR_L30 0x120320
2777 /* [RW 7] Bandwidth upper bound for VQ29 */
2778 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2779 /* [RW 7] Bandwidth upper bound for VQ30 */
2780 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
2781 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
2782 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
2783 /* [RW 2] Endian mode for cdu */
2784 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
2785 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
2786 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
2787 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2789 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
2790 /* [R 1] 1' indicates that the requester has finished its internal
2792 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
2793 /* [RW 2] Endian mode for debug */
2794 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
2795 /* [RW 1] When '1'; requests will enter input buffers but wont get out
2797 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
2798 /* [RW 4] Determines alignment of write SRs when a request is split into
2799 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
2800 * aligned. 4 - 512B aligned. */
2801 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
2802 /* [RW 4] Determines alignment of read SRs when a request is split into
2803 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
2804 * aligned. 4 - 512B aligned. */
2805 #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
2806 /* [RW 1] when set the new alignment method (E2) will be applied; when reset
2807 * the original alignment method (E1 E1H) will be applied */
2808 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
2809 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
2811 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
2812 /* [RW 2] Endian mode for hc */
2813 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
2814 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
2815 compatibility needs; Note that different registers are used per mode */
2816 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
2817 /* [WB 53] Onchip address table */
2818 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
2819 /* [WB 53] Onchip address table - B0 */
2820 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
2821 /* [RW 13] Pending read limiter threshold; in Dwords */
2822 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
2823 /* [RW 2] Endian mode for qm */
2824 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
2825 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
2826 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
2827 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2829 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
2830 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
2831 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
2832 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2833 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2834 #define PXP2_REG_RQ_RD_MBS0 0x120160
2835 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
2836 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2837 #define PXP2_REG_RQ_RD_MBS1 0x120168
2838 /* [RW 2] Endian mode for src */
2839 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
2840 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
2841 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
2842 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2844 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2845 /* [RW 2] Endian mode for tm */
2846 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
2847 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
2848 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
2849 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2851 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
2852 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2853 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
2854 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
2855 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
2856 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2857 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2858 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
2859 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
2860 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
2861 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
2862 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
2863 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
2864 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
2865 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
2866 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
2867 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
2868 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
2869 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
2870 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
2871 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
2872 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
2873 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
2874 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
2875 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
2876 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
2877 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
2878 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
2879 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
2880 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
2881 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
2882 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
2883 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
2884 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
2885 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
2886 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
2887 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
2888 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
2889 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
2890 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
2891 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
2892 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
2893 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
2894 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
2895 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
2896 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
2897 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
2898 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
2899 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
2900 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
2901 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
2902 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
2903 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
2904 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
2905 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
2906 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
2907 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
2908 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
2909 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
2910 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
2911 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
2912 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
2913 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
2914 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
2915 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
2916 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
2917 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
2918 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
2919 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2920 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2921 001:256B; 010: 512B; */
2922 #define PXP2_REG_RQ_WR_MBS0 0x12015c
2923 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2924 001:256B; 010: 512B; */
2925 #define PXP2_REG_RQ_WR_MBS1 0x120164
2926 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2927 buffer reaches this number has_payload will be asserted */
2928 #define PXP2_REG_WR_CDU_MPS 0x1205f0
2929 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2930 buffer reaches this number has_payload will be asserted */
2931 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
2932 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2933 buffer reaches this number has_payload will be asserted */
2934 #define PXP2_REG_WR_DBG_MPS 0x1205e8
2935 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2936 buffer reaches this number has_payload will be asserted */
2937 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
2938 /* [RW 10] if Number of entries in dmae fifo will be higher than this
2939 threshold then has_payload indication will be asserted; the default value
2940 should be equal to > write MBS size! */
2941 #define PXP2_REG_WR_DMAE_TH 0x120368
2942 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2943 buffer reaches this number has_payload will be asserted */
2944 #define PXP2_REG_WR_HC_MPS 0x1205c8
2945 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2946 buffer reaches this number has_payload will be asserted */
2947 #define PXP2_REG_WR_QM_MPS 0x1205dc
2948 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
2949 #define PXP2_REG_WR_REV_MODE 0x120670
2950 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2951 buffer reaches this number has_payload will be asserted */
2952 #define PXP2_REG_WR_SRC_MPS 0x1205e4
2953 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2954 buffer reaches this number has_payload will be asserted */
2955 #define PXP2_REG_WR_TM_MPS 0x1205e0
2956 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2957 buffer reaches this number has_payload will be asserted */
2958 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
2959 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
2960 threshold then has_payload indication will be asserted; the default value
2961 should be equal to > write MBS size! */
2962 #define PXP2_REG_WR_USDMDP_TH 0x120348
2963 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2964 buffer reaches this number has_payload will be asserted */
2965 #define PXP2_REG_WR_USDM_MPS 0x1205cc
2966 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2967 buffer reaches this number has_payload will be asserted */
2968 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
2969 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
2970 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
2971 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2972 this client is waiting for the arbiter. */
2973 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
2974 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
2975 block. Should be used for close the gates. */
2976 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
2977 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
2978 should update accoring to 'hst_discard_doorbells' register when the state
2980 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
2981 /* [RW 1] When 1; new internal writes arriving to the block are discarded.
2982 Should be used for close the gates. */
2983 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
2984 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
2985 means this PSWHST is discarding inputs from this client. Each bit should
2986 update accoring to 'hst_discard_internal_writes' register when the state
2988 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
2989 /* [WB 160] Used for initialization of the inbound interrupts memory */
2990 #define PXP_REG_HST_INBOUND_INT 0x103800
2991 /* [RW 32] Interrupt mask register #0 read/write */
2992 #define PXP_REG_PXP_INT_MASK_0 0x103074
2993 #define PXP_REG_PXP_INT_MASK_1 0x103084
2994 /* [R 32] Interrupt register #0 read */
2995 #define PXP_REG_PXP_INT_STS_0 0x103068
2996 #define PXP_REG_PXP_INT_STS_1 0x103078
2997 /* [RC 32] Interrupt register #0 read clear */
2998 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
2999 #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
3000 /* [RW 27] Parity mask register #0 read/write */
3001 #define PXP_REG_PXP_PRTY_MASK 0x103094
3002 /* [R 26] Parity register #0 read */
3003 #define PXP_REG_PXP_PRTY_STS 0x103088
3004 /* [RW 4] The activity counter initial increment value sent in the load
3006 #define QM_REG_ACTCTRINITVAL_0 0x168040
3007 #define QM_REG_ACTCTRINITVAL_1 0x168044
3008 #define QM_REG_ACTCTRINITVAL_2 0x168048
3009 #define QM_REG_ACTCTRINITVAL_3 0x16804c
3010 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3011 index I represents the physical queue number. The 12 lsbs are ignore and
3012 considered zero so practically there are only 20 bits in this register;
3014 #define QM_REG_BASEADDR 0x168900
3015 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3016 index I represents the physical queue number. The 12 lsbs are ignore and
3017 considered zero so practically there are only 20 bits in this register;
3019 #define QM_REG_BASEADDR_EXT_A 0x16e100
3020 /* [RW 16] The byte credit cost for each task. This value is for both ports */
3021 #define QM_REG_BYTECRDCOST 0x168234
3022 /* [RW 16] The initial byte credit value for both ports. */
3023 #define QM_REG_BYTECRDINITVAL 0x168238
3024 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3025 queue uses port 0 else it uses port 1; queues 31-0 */
3026 #define QM_REG_BYTECRDPORT_LSB 0x168228
3027 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3028 queue uses port 0 else it uses port 1; queues 95-64 */
3029 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
3030 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3031 queue uses port 0 else it uses port 1; queues 63-32 */
3032 #define QM_REG_BYTECRDPORT_MSB 0x168224
3033 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3034 queue uses port 0 else it uses port 1; queues 127-96 */
3035 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
3036 /* [RW 16] The byte credit value that if above the QM is considered almost
3038 #define QM_REG_BYTECREDITAFULLTHR 0x168094
3039 /* [RW 4] The initial credit for interface */
3040 #define QM_REG_CMINITCRD_0 0x1680cc
3041 #define QM_REG_CMINITCRD_1 0x1680d0
3042 #define QM_REG_CMINITCRD_2 0x1680d4
3043 #define QM_REG_CMINITCRD_3 0x1680d8
3044 #define QM_REG_CMINITCRD_4 0x1680dc
3045 #define QM_REG_CMINITCRD_5 0x1680e0
3046 #define QM_REG_CMINITCRD_6 0x1680e4
3047 #define QM_REG_CMINITCRD_7 0x1680e8
3048 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
3050 #define QM_REG_CMINTEN 0x1680ec
3051 /* [RW 12] A bit vector which indicates which one of the queues are tied to
3053 #define QM_REG_CMINTVOQMASK_0 0x1681f4
3054 #define QM_REG_CMINTVOQMASK_1 0x1681f8
3055 #define QM_REG_CMINTVOQMASK_2 0x1681fc
3056 #define QM_REG_CMINTVOQMASK_3 0x168200
3057 #define QM_REG_CMINTVOQMASK_4 0x168204
3058 #define QM_REG_CMINTVOQMASK_5 0x168208
3059 #define QM_REG_CMINTVOQMASK_6 0x16820c
3060 #define QM_REG_CMINTVOQMASK_7 0x168210
3061 /* [RW 20] The number of connections divided by 16 which dictates the size
3062 of each queue which belongs to even function number. */
3063 #define QM_REG_CONNNUM_0 0x168020
3064 /* [R 6] Keep the fill level of the fifo from write client 4 */
3065 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
3066 /* [RW 8] The context regions sent in the CFC load request */
3067 #define QM_REG_CTXREG_0 0x168030
3068 #define QM_REG_CTXREG_1 0x168034
3069 #define QM_REG_CTXREG_2 0x168038
3070 #define QM_REG_CTXREG_3 0x16803c
3071 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
3073 #define QM_REG_ENBYPVOQMASK 0x16823c
3074 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3075 physical queue uses the byte credit; queues 31-0 */
3076 #define QM_REG_ENBYTECRD_LSB 0x168220
3077 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3078 physical queue uses the byte credit; queues 95-64 */
3079 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
3080 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3081 physical queue uses the byte credit; queues 63-32 */
3082 #define QM_REG_ENBYTECRD_MSB 0x16821c
3083 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3084 physical queue uses the byte credit; queues 127-96 */
3085 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
3086 /* [RW 4] If cleared then the secondary interface will not be served by the
3088 #define QM_REG_ENSEC 0x1680f0
3090 #define QM_REG_FUNCNUMSEL_LSB 0x168230
3092 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
3093 /* [RW 32] A mask register to mask the Almost empty signals which will not
3094 be use for the almost empty indication to the HW block; queues 31:0 */
3095 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
3096 /* [RW 32] A mask register to mask the Almost empty signals which will not
3097 be use for the almost empty indication to the HW block; queues 95-64 */
3098 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
3099 /* [RW 32] A mask register to mask the Almost empty signals which will not
3100 be use for the almost empty indication to the HW block; queues 63:32 */
3101 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
3102 /* [RW 32] A mask register to mask the Almost empty signals which will not
3103 be use for the almost empty indication to the HW block; queues 127-96 */
3104 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
3105 /* [RW 4] The number of outstanding request to CFC */
3106 #define QM_REG_OUTLDREQ 0x168804
3107 /* [RC 1] A flag to indicate that overflow error occurred in one of the
3109 #define QM_REG_OVFERROR 0x16805c
3110 /* [RC 7] the Q where the overflow occurs */
3111 #define QM_REG_OVFQNUM 0x168058
3112 /* [R 16] Pause state for physical queues 15-0 */
3113 #define QM_REG_PAUSESTATE0 0x168410
3114 /* [R 16] Pause state for physical queues 31-16 */
3115 #define QM_REG_PAUSESTATE1 0x168414
3116 /* [R 16] Pause state for physical queues 47-32 */
3117 #define QM_REG_PAUSESTATE2 0x16e684
3118 /* [R 16] Pause state for physical queues 63-48 */
3119 #define QM_REG_PAUSESTATE3 0x16e688
3120 /* [R 16] Pause state for physical queues 79-64 */
3121 #define QM_REG_PAUSESTATE4 0x16e68c
3122 /* [R 16] Pause state for physical queues 95-80 */
3123 #define QM_REG_PAUSESTATE5 0x16e690
3124 /* [R 16] Pause state for physical queues 111-96 */
3125 #define QM_REG_PAUSESTATE6 0x16e694
3126 /* [R 16] Pause state for physical queues 127-112 */
3127 #define QM_REG_PAUSESTATE7 0x16e698
3128 /* [RW 2] The PCI attributes field used in the PCI request. */
3129 #define QM_REG_PCIREQAT 0x168054
3130 #define QM_REG_PF_EN 0x16e70c
3131 /* [R 16] The byte credit of port 0 */
3132 #define QM_REG_PORT0BYTECRD 0x168300
3133 /* [R 16] The byte credit of port 1 */
3134 #define QM_REG_PORT1BYTECRD 0x168304
3135 /* [RW 3] pci function number of queues 15-0 */
3136 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
3137 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
3138 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
3139 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
3140 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
3141 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
3142 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
3143 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
3144 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
3145 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3146 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3147 #define QM_REG_PTRTBL 0x168a00
3148 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
3149 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3150 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3151 #define QM_REG_PTRTBL_EXT_A 0x16e200
3152 /* [RW 2] Interrupt mask register #0 read/write */
3153 #define QM_REG_QM_INT_MASK 0x168444
3154 /* [R 2] Interrupt register #0 read */
3155 #define QM_REG_QM_INT_STS 0x168438
3156 /* [RW 12] Parity mask register #0 read/write */
3157 #define QM_REG_QM_PRTY_MASK 0x168454
3158 /* [R 12] Parity register #0 read */
3159 #define QM_REG_QM_PRTY_STS 0x168448
3160 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
3161 #define QM_REG_QSTATUS_HIGH 0x16802c
3162 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
3163 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
3164 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
3165 #define QM_REG_QSTATUS_LOW 0x168028
3166 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
3167 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
3168 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
3169 #define QM_REG_QTASKCTR_0 0x168308
3170 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
3171 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
3172 /* [RW 4] Queue tied to VOQ */
3173 #define QM_REG_QVOQIDX_0 0x1680f4
3174 #define QM_REG_QVOQIDX_10 0x16811c
3175 #define QM_REG_QVOQIDX_100 0x16e49c
3176 #define QM_REG_QVOQIDX_101 0x16e4a0
3177 #define QM_REG_QVOQIDX_102 0x16e4a4
3178 #define QM_REG_QVOQIDX_103 0x16e4a8
3179 #define QM_REG_QVOQIDX_104 0x16e4ac
3180 #define QM_REG_QVOQIDX_105 0x16e4b0
3181 #define QM_REG_QVOQIDX_106 0x16e4b4
3182 #define QM_REG_QVOQIDX_107 0x16e4b8
3183 #define QM_REG_QVOQIDX_108 0x16e4bc
3184 #define QM_REG_QVOQIDX_109 0x16e4c0
3185 #define QM_REG_QVOQIDX_11 0x168120
3186 #define QM_REG_QVOQIDX_110 0x16e4c4
3187 #define QM_REG_QVOQIDX_111 0x16e4c8
3188 #define QM_REG_QVOQIDX_112 0x16e4cc
3189 #define QM_REG_QVOQIDX_113 0x16e4d0
3190 #define QM_REG_QVOQIDX_114 0x16e4d4
3191 #define QM_REG_QVOQIDX_115 0x16e4d8
3192 #define QM_REG_QVOQIDX_116 0x16e4dc
3193 #define QM_REG_QVOQIDX_117 0x16e4e0
3194 #define QM_REG_QVOQIDX_118 0x16e4e4
3195 #define QM_REG_QVOQIDX_119 0x16e4e8
3196 #define QM_REG_QVOQIDX_12 0x168124
3197 #define QM_REG_QVOQIDX_120 0x16e4ec
3198 #define QM_REG_QVOQIDX_121 0x16e4f0
3199 #define QM_REG_QVOQIDX_122 0x16e4f4
3200 #define QM_REG_QVOQIDX_123 0x16e4f8
3201 #define QM_REG_QVOQIDX_124 0x16e4fc
3202 #define QM_REG_QVOQIDX_125 0x16e500
3203 #define QM_REG_QVOQIDX_126 0x16e504
3204 #define QM_REG_QVOQIDX_127 0x16e508
3205 #define QM_REG_QVOQIDX_13 0x168128
3206 #define QM_REG_QVOQIDX_14 0x16812c
3207 #define QM_REG_QVOQIDX_15 0x168130
3208 #define QM_REG_QVOQIDX_16 0x168134
3209 #define QM_REG_QVOQIDX_17 0x168138
3210 #define QM_REG_QVOQIDX_21 0x168148
3211 #define QM_REG_QVOQIDX_22 0x16814c
3212 #define QM_REG_QVOQIDX_23 0x168150
3213 #define QM_REG_QVOQIDX_24 0x168154
3214 #define QM_REG_QVOQIDX_25 0x168158
3215 #define QM_REG_QVOQIDX_26 0x16815c
3216 #define QM_REG_QVOQIDX_27 0x168160
3217 #define QM_REG_QVOQIDX_28 0x168164
3218 #define QM_REG_QVOQIDX_29 0x168168
3219 #define QM_REG_QVOQIDX_30 0x16816c
3220 #define QM_REG_QVOQIDX_31 0x168170
3221 #define QM_REG_QVOQIDX_32 0x168174
3222 #define QM_REG_QVOQIDX_33 0x168178
3223 #define QM_REG_QVOQIDX_34 0x16817c
3224 #define QM_REG_QVOQIDX_35 0x168180
3225 #define QM_REG_QVOQIDX_36 0x168184
3226 #define QM_REG_QVOQIDX_37 0x168188
3227 #define QM_REG_QVOQIDX_38 0x16818c
3228 #define QM_REG_QVOQIDX_39 0x168190
3229 #define QM_REG_QVOQIDX_40 0x168194
3230 #define QM_REG_QVOQIDX_41 0x168198
3231 #define QM_REG_QVOQIDX_42 0x16819c
3232 #define QM_REG_QVOQIDX_43 0x1681a0
3233 #define QM_REG_QVOQIDX_44 0x1681a4
3234 #define QM_REG_QVOQIDX_45 0x1681a8
3235 #define QM_REG_QVOQIDX_46 0x1681ac
3236 #define QM_REG_QVOQIDX_47 0x1681b0
3237 #define QM_REG_QVOQIDX_48 0x1681b4
3238 #define QM_REG_QVOQIDX_49 0x1681b8
3239 #define QM_REG_QVOQIDX_5 0x168108
3240 #define QM_REG_QVOQIDX_50 0x1681bc
3241 #define QM_REG_QVOQIDX_51 0x1681c0
3242 #define QM_REG_QVOQIDX_52 0x1681c4
3243 #define QM_REG_QVOQIDX_53 0x1681c8
3244 #define QM_REG_QVOQIDX_54 0x1681cc
3245 #define QM_REG_QVOQIDX_55 0x1681d0
3246 #define QM_REG_QVOQIDX_56 0x1681d4
3247 #define QM_REG_QVOQIDX_57 0x1681d8
3248 #define QM_REG_QVOQIDX_58 0x1681dc
3249 #define QM_REG_QVOQIDX_59 0x1681e0
3250 #define QM_REG_QVOQIDX_6 0x16810c
3251 #define QM_REG_QVOQIDX_60 0x1681e4
3252 #define QM_REG_QVOQIDX_61 0x1681e8
3253 #define QM_REG_QVOQIDX_62 0x1681ec
3254 #define QM_REG_QVOQIDX_63 0x1681f0
3255 #define QM_REG_QVOQIDX_64 0x16e40c
3256 #define QM_REG_QVOQIDX_65 0x16e410
3257 #define QM_REG_QVOQIDX_69 0x16e420
3258 #define QM_REG_QVOQIDX_7 0x168110
3259 #define QM_REG_QVOQIDX_70 0x16e424
3260 #define QM_REG_QVOQIDX_71 0x16e428
3261 #define QM_REG_QVOQIDX_72 0x16e42c
3262 #define QM_REG_QVOQIDX_73 0x16e430
3263 #define QM_REG_QVOQIDX_74 0x16e434
3264 #define QM_REG_QVOQIDX_75 0x16e438
3265 #define QM_REG_QVOQIDX_76 0x16e43c
3266 #define QM_REG_QVOQIDX_77 0x16e440
3267 #define QM_REG_QVOQIDX_78 0x16e444
3268 #define QM_REG_QVOQIDX_79 0x16e448
3269 #define QM_REG_QVOQIDX_8 0x168114
3270 #define QM_REG_QVOQIDX_80 0x16e44c
3271 #define QM_REG_QVOQIDX_81 0x16e450
3272 #define QM_REG_QVOQIDX_85 0x16e460
3273 #define QM_REG_QVOQIDX_86 0x16e464
3274 #define QM_REG_QVOQIDX_87 0x16e468
3275 #define QM_REG_QVOQIDX_88 0x16e46c
3276 #define QM_REG_QVOQIDX_89 0x16e470
3277 #define QM_REG_QVOQIDX_9 0x168118
3278 #define QM_REG_QVOQIDX_90 0x16e474
3279 #define QM_REG_QVOQIDX_91 0x16e478
3280 #define QM_REG_QVOQIDX_92 0x16e47c
3281 #define QM_REG_QVOQIDX_93 0x16e480
3282 #define QM_REG_QVOQIDX_94 0x16e484
3283 #define QM_REG_QVOQIDX_95 0x16e488
3284 #define QM_REG_QVOQIDX_96 0x16e48c
3285 #define QM_REG_QVOQIDX_97 0x16e490
3286 #define QM_REG_QVOQIDX_98 0x16e494
3287 #define QM_REG_QVOQIDX_99 0x16e498
3288 /* [RW 1] Initialization bit command */
3289 #define QM_REG_SOFT_RESET 0x168428
3290 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
3291 #define QM_REG_TASKCRDCOST_0 0x16809c
3292 #define QM_REG_TASKCRDCOST_1 0x1680a0
3293 #define QM_REG_TASKCRDCOST_2 0x1680a4
3294 #define QM_REG_TASKCRDCOST_4 0x1680ac
3295 #define QM_REG_TASKCRDCOST_5 0x1680b0
3296 /* [R 6] Keep the fill level of the fifo from write client 3 */
3297 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
3298 /* [R 6] Keep the fill level of the fifo from write client 2 */
3299 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
3300 /* [RC 32] Credit update error register */
3301 #define QM_REG_VOQCRDERRREG 0x168408
3302 /* [R 16] The credit value for each VOQ */
3303 #define QM_REG_VOQCREDIT_0 0x1682d0
3304 #define QM_REG_VOQCREDIT_1 0x1682d4
3305 #define QM_REG_VOQCREDIT_4 0x1682e0
3306 /* [RW 16] The credit value that if above the QM is considered almost full */
3307 #define QM_REG_VOQCREDITAFULLTHR 0x168090
3308 /* [RW 16] The init and maximum credit for each VoQ */
3309 #define QM_REG_VOQINITCREDIT_0 0x168060
3310 #define QM_REG_VOQINITCREDIT_1 0x168064
3311 #define QM_REG_VOQINITCREDIT_2 0x168068
3312 #define QM_REG_VOQINITCREDIT_4 0x168070
3313 #define QM_REG_VOQINITCREDIT_5 0x168074
3314 /* [RW 1] The port of which VOQ belongs */
3315 #define QM_REG_VOQPORT_0 0x1682a0
3316 #define QM_REG_VOQPORT_1 0x1682a4
3317 #define QM_REG_VOQPORT_2 0x1682a8
3318 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3319 #define QM_REG_VOQQMASK_0_LSB 0x168240
3320 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3321 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
3322 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3323 #define QM_REG_VOQQMASK_0_MSB 0x168244
3324 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3325 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
3326 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3327 #define QM_REG_VOQQMASK_10_LSB 0x168290
3328 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3329 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
3330 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3331 #define QM_REG_VOQQMASK_10_MSB 0x168294
3332 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3333 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
3334 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3335 #define QM_REG_VOQQMASK_11_LSB 0x168298
3336 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3337 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
3338 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3339 #define QM_REG_VOQQMASK_11_MSB 0x16829c
3340 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3341 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
3342 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3343 #define QM_REG_VOQQMASK_1_LSB 0x168248
3344 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3345 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
3346 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3347 #define QM_REG_VOQQMASK_1_MSB 0x16824c
3348 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3349 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
3350 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3351 #define QM_REG_VOQQMASK_2_LSB 0x168250
3352 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3353 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
3354 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3355 #define QM_REG_VOQQMASK_2_MSB 0x168254
3356 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3357 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
3358 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3359 #define QM_REG_VOQQMASK_3_LSB 0x168258
3360 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3361 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
3362 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3363 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
3364 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3365 #define QM_REG_VOQQMASK_4_LSB 0x168260
3366 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3367 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
3368 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3369 #define QM_REG_VOQQMASK_4_MSB 0x168264
3370 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3371 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
3372 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3373 #define QM_REG_VOQQMASK_5_LSB 0x168268
3374 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3375 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
3376 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3377 #define QM_REG_VOQQMASK_5_MSB 0x16826c
3378 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3379 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
3380 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3381 #define QM_REG_VOQQMASK_6_LSB 0x168270
3382 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3383 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
3384 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3385 #define QM_REG_VOQQMASK_6_MSB 0x168274
3386 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3387 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
3388 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3389 #define QM_REG_VOQQMASK_7_LSB 0x168278
3390 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3391 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
3392 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3393 #define QM_REG_VOQQMASK_7_MSB 0x16827c
3394 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3395 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
3396 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3397 #define QM_REG_VOQQMASK_8_LSB 0x168280
3398 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3399 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
3400 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3401 #define QM_REG_VOQQMASK_8_MSB 0x168284
3402 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3403 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
3404 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3405 #define QM_REG_VOQQMASK_9_LSB 0x168288
3406 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3407 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
3408 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3409 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
3410 /* [RW 32] Wrr weights */
3411 #define QM_REG_WRRWEIGHTS_0 0x16880c
3412 #define QM_REG_WRRWEIGHTS_1 0x168810
3413 #define QM_REG_WRRWEIGHTS_10 0x168814
3414 #define QM_REG_WRRWEIGHTS_11 0x168818
3415 #define QM_REG_WRRWEIGHTS_12 0x16881c
3416 #define QM_REG_WRRWEIGHTS_13 0x168820
3417 #define QM_REG_WRRWEIGHTS_14 0x168824
3418 #define QM_REG_WRRWEIGHTS_15 0x168828
3419 #define QM_REG_WRRWEIGHTS_16 0x16e000
3420 #define QM_REG_WRRWEIGHTS_17 0x16e004
3421 #define QM_REG_WRRWEIGHTS_18 0x16e008
3422 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3423 #define QM_REG_WRRWEIGHTS_2 0x16882c
3424 #define QM_REG_WRRWEIGHTS_20 0x16e010
3425 #define QM_REG_WRRWEIGHTS_21 0x16e014
3426 #define QM_REG_WRRWEIGHTS_22 0x16e018
3427 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3428 #define QM_REG_WRRWEIGHTS_24 0x16e020
3429 #define QM_REG_WRRWEIGHTS_25 0x16e024
3430 #define QM_REG_WRRWEIGHTS_26 0x16e028
3431 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3432 #define QM_REG_WRRWEIGHTS_28 0x16e030
3433 #define QM_REG_WRRWEIGHTS_29 0x16e034
3434 #define QM_REG_WRRWEIGHTS_3 0x168830
3435 #define QM_REG_WRRWEIGHTS_30 0x16e038
3436 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3437 #define QM_REG_WRRWEIGHTS_4 0x168834
3438 #define QM_REG_WRRWEIGHTS_5 0x168838
3439 #define QM_REG_WRRWEIGHTS_6 0x16883c
3440 #define QM_REG_WRRWEIGHTS_7 0x168840
3441 #define QM_REG_WRRWEIGHTS_8 0x168844
3442 #define QM_REG_WRRWEIGHTS_9 0x168848
3443 /* [R 6] Keep the fill level of the fifo from write client 1 */
3444 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
3445 #define SRC_REG_COUNTFREE0 0x40500
3446 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3447 ports. If set the searcher support 8 functions. */
3448 #define SRC_REG_E1HMF_ENABLE 0x404cc
3449 #define SRC_REG_FIRSTFREE0 0x40510
3450 #define SRC_REG_KEYRSS0_0 0x40408
3451 #define SRC_REG_KEYRSS0_7 0x40424
3452 #define SRC_REG_KEYRSS1_9 0x40454
3453 #define SRC_REG_KEYSEARCH_0 0x40458
3454 #define SRC_REG_KEYSEARCH_1 0x4045c
3455 #define SRC_REG_KEYSEARCH_2 0x40460
3456 #define SRC_REG_KEYSEARCH_3 0x40464
3457 #define SRC_REG_KEYSEARCH_4 0x40468
3458 #define SRC_REG_KEYSEARCH_5 0x4046c
3459 #define SRC_REG_KEYSEARCH_6 0x40470
3460 #define SRC_REG_KEYSEARCH_7 0x40474
3461 #define SRC_REG_KEYSEARCH_8 0x40478
3462 #define SRC_REG_KEYSEARCH_9 0x4047c
3463 #define SRC_REG_LASTFREE0 0x40530
3464 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
3465 /* [RW 1] Reset internal state machines. */
3466 #define SRC_REG_SOFT_RST 0x4049c
3467 /* [R 3] Interrupt register #0 read */
3468 #define SRC_REG_SRC_INT_STS 0x404ac
3469 /* [RW 3] Parity mask register #0 read/write */
3470 #define SRC_REG_SRC_PRTY_MASK 0x404c8
3471 /* [R 3] Parity register #0 read */
3472 #define SRC_REG_SRC_PRTY_STS 0x404bc
3473 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
3474 #define TCM_REG_CAM_OCCUP 0x5017c
3475 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3476 disregarded; valid output is deasserted; all other signals are treated as
3477 usual; if 1 - normal activity. */
3478 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
3479 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3480 are disregarded; all other signals are treated as usual; if 1 - normal
3482 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
3483 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3484 disregarded; valid output is deasserted; all other signals are treated as
3485 usual; if 1 - normal activity. */
3486 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
3487 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3488 input is disregarded; all other signals are treated as usual; if 1 -
3490 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
3491 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3492 the initial credit value; read returns the current value of the credit
3493 counter. Must be initialized to 1 at start-up. */
3494 #define TCM_REG_CFC_INIT_CRD 0x50204
3495 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3496 weight 8 (the most prioritised); 1 stands for weight 1(least
3497 prioritised); 2 stands for weight 2; tc. */
3498 #define TCM_REG_CP_WEIGHT 0x500c0
3499 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3500 disregarded; acknowledge output is deasserted; all other signals are
3501 treated as usual; if 1 - normal activity. */
3502 #define TCM_REG_CSEM_IFEN 0x5002c
3503 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
3505 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
3506 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3507 weight 8 (the most prioritised); 1 stands for weight 1(least
3508 prioritised); 2 stands for weight 2; tc. */
3509 #define TCM_REG_CSEM_WEIGHT 0x500bc
3510 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
3511 #define TCM_REG_ERR_EVNT_ID 0x500a0
3512 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3513 #define TCM_REG_ERR_TCM_HDR 0x5009c
3514 /* [RW 8] The Event ID for Timers expiration. */
3515 #define TCM_REG_EXPR_EVNT_ID 0x500a4
3516 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3517 writes the initial credit value; read returns the current value of the
3518 credit counter. Must be initialized to 64 at start-up. */
3519 #define TCM_REG_FIC0_INIT_CRD 0x5020c
3520 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3521 writes the initial credit value; read returns the current value of the
3522 credit counter. Must be initialized to 64 at start-up. */
3523 #define TCM_REG_FIC1_INIT_CRD 0x50210
3524 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3525 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
3526 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
3527 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
3528 #define TCM_REG_GR_ARB_TYPE 0x50114
3529 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3530 highest priority is 3. It is supposed that the Store channel is the
3531 compliment of the other 3 groups. */
3532 #define TCM_REG_GR_LD0_PR 0x5011c
3533 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3534 highest priority is 3. It is supposed that the Store channel is the
3535 compliment of the other 3 groups. */
3536 #define TCM_REG_GR_LD1_PR 0x50120
3537 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
3538 sent to STORM; for a specific connection type. The double REG-pairs are
3539 used to align to STORM context row size of 128 bits. The offset of these
3540 data in the STORM context is always 0. Index _i stands for the connection
3541 type (one of 16). */
3542 #define TCM_REG_N_SM_CTX_LD_0 0x50050
3543 #define TCM_REG_N_SM_CTX_LD_1 0x50054
3544 #define TCM_REG_N_SM_CTX_LD_2 0x50058
3545 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
3546 #define TCM_REG_N_SM_CTX_LD_4 0x50060
3547 #define TCM_REG_N_SM_CTX_LD_5 0x50064
3548 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3549 acknowledge output is deasserted; all other signals are treated as usual;
3550 if 1 - normal activity. */
3551 #define TCM_REG_PBF_IFEN 0x50024
3552 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
3554 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
3555 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3556 weight 8 (the most prioritised); 1 stands for weight 1(least
3557 prioritised); 2 stands for weight 2; tc. */
3558 #define TCM_REG_PBF_WEIGHT 0x500b4
3559 #define TCM_REG_PHYS_QNUM0_0 0x500e0
3560 #define TCM_REG_PHYS_QNUM0_1 0x500e4
3561 #define TCM_REG_PHYS_QNUM1_0 0x500e8
3562 #define TCM_REG_PHYS_QNUM1_1 0x500ec
3563 #define TCM_REG_PHYS_QNUM2_0 0x500f0
3564 #define TCM_REG_PHYS_QNUM2_1 0x500f4
3565 #define TCM_REG_PHYS_QNUM3_0 0x500f8
3566 #define TCM_REG_PHYS_QNUM3_1 0x500fc
3567 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
3568 acknowledge output is deasserted; all other signals are treated as usual;
3569 if 1 - normal activity. */
3570 #define TCM_REG_PRS_IFEN 0x50020
3571 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
3573 #define TCM_REG_PRS_LENGTH_MIS 0x50168
3574 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
3575 weight 8 (the most prioritised); 1 stands for weight 1(least
3576 prioritised); 2 stands for weight 2; tc. */
3577 #define TCM_REG_PRS_WEIGHT 0x500b0
3578 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3579 #define TCM_REG_STOP_EVNT_ID 0x500a8
3580 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
3582 #define TCM_REG_STORM_LENGTH_MIS 0x50160
3583 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3584 disregarded; acknowledge output is deasserted; all other signals are
3585 treated as usual; if 1 - normal activity. */
3586 #define TCM_REG_STORM_TCM_IFEN 0x50010
3587 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3588 weight 8 (the most prioritised); 1 stands for weight 1(least
3589 prioritised); 2 stands for weight 2; tc. */
3590 #define TCM_REG_STORM_WEIGHT 0x500ac
3591 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3592 acknowledge output is deasserted; all other signals are treated as usual;
3593 if 1 - normal activity. */
3594 #define TCM_REG_TCM_CFC_IFEN 0x50040
3595 /* [RW 11] Interrupt mask register #0 read/write */
3596 #define TCM_REG_TCM_INT_MASK 0x501dc
3597 /* [R 11] Interrupt register #0 read */
3598 #define TCM_REG_TCM_INT_STS 0x501d0
3599 /* [R 27] Parity register #0 read */
3600 #define TCM_REG_TCM_PRTY_STS 0x501e0
3601 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
3602 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3603 Is used to determine the number of the AG context REG-pairs written back;
3604 when the input message Reg1WbFlg isn't set. */
3605 #define TCM_REG_TCM_REG0_SZ 0x500d8
3606 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3607 disregarded; valid is deasserted; all other signals are treated as usual;
3608 if 1 - normal activity. */
3609 #define TCM_REG_TCM_STORM0_IFEN 0x50004
3610 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3611 disregarded; valid is deasserted; all other signals are treated as usual;
3612 if 1 - normal activity. */
3613 #define TCM_REG_TCM_STORM1_IFEN 0x50008
3614 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3615 disregarded; valid is deasserted; all other signals are treated as usual;
3616 if 1 - normal activity. */
3617 #define TCM_REG_TCM_TQM_IFEN 0x5000c
3618 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3619 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
3620 /* [RW 28] The CM header for Timers expiration command. */
3621 #define TCM_REG_TM_TCM_HDR 0x50098
3622 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3623 disregarded; acknowledge output is deasserted; all other signals are
3624 treated as usual; if 1 - normal activity. */
3625 #define TCM_REG_TM_TCM_IFEN 0x5001c
3626 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
3627 weight 8 (the most prioritised); 1 stands for weight 1(least
3628 prioritised); 2 stands for weight 2; tc. */
3629 #define TCM_REG_TM_WEIGHT 0x500d0
3630 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3631 the initial credit value; read returns the current value of the credit
3632 counter. Must be initialized to 32 at start-up. */
3633 #define TCM_REG_TQM_INIT_CRD 0x5021c
3634 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3635 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3636 prioritised); 2 stands for weight 2; tc. */
3637 #define TCM_REG_TQM_P_WEIGHT 0x500c8
3638 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
3639 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3640 prioritised); 2 stands for weight 2; tc. */
3641 #define TCM_REG_TQM_S_WEIGHT 0x500cc
3642 /* [RW 28] The CM header value for QM request (primary). */
3643 #define TCM_REG_TQM_TCM_HDR_P 0x50090
3644 /* [RW 28] The CM header value for QM request (secondary). */
3645 #define TCM_REG_TQM_TCM_HDR_S 0x50094
3646 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3647 acknowledge output is deasserted; all other signals are treated as usual;
3648 if 1 - normal activity. */
3649 #define TCM_REG_TQM_TCM_IFEN 0x50014
3650 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3651 acknowledge output is deasserted; all other signals are treated as usual;
3652 if 1 - normal activity. */
3653 #define TCM_REG_TSDM_IFEN 0x50018
3654 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
3656 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
3657 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3658 weight 8 (the most prioritised); 1 stands for weight 1(least
3659 prioritised); 2 stands for weight 2; tc. */
3660 #define TCM_REG_TSDM_WEIGHT 0x500c4
3661 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
3662 disregarded; acknowledge output is deasserted; all other signals are
3663 treated as usual; if 1 - normal activity. */
3664 #define TCM_REG_USEM_IFEN 0x50028
3665 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
3667 #define TCM_REG_USEM_LENGTH_MIS 0x50170
3668 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3669 weight 8 (the most prioritised); 1 stands for weight 1(least
3670 prioritised); 2 stands for weight 2; tc. */
3671 #define TCM_REG_USEM_WEIGHT 0x500b8
3672 /* [RW 21] Indirect access to the descriptor table of the XX protection
3673 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
3674 pointer; 20:16] - next pointer. */
3675 #define TCM_REG_XX_DESCR_TABLE 0x50280
3676 #define TCM_REG_XX_DESCR_TABLE_SIZE 32
3677 /* [R 6] Use to read the value of XX protection Free counter. */
3678 #define TCM_REG_XX_FREE 0x50178
3679 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3680 of the Input Stage XX protection buffer by the XX protection pending
3681 messages. Max credit available - 127.Write writes the initial credit
3682 value; read returns the current value of the credit counter. Must be
3683 initialized to 19 at start-up. */
3684 #define TCM_REG_XX_INIT_CRD 0x50220
3685 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
3687 #define TCM_REG_XX_MAX_LL_SZ 0x50044
3688 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3689 protection. ~tcm_registers_xx_free.xx_free is read on read. */
3690 #define TCM_REG_XX_MSG_NUM 0x50224
3691 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3692 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
3693 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3694 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
3696 #define TCM_REG_XX_TABLE 0x50240
3697 /* [RW 4] Load value for cfc ac credit cnt. */
3698 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
3699 /* [RW 4] Load value for cfc cld credit cnt. */
3700 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
3701 /* [RW 8] Client0 context region. */
3702 #define TM_REG_CL0_CONT_REGION 0x164030
3703 /* [RW 8] Client1 context region. */
3704 #define TM_REG_CL1_CONT_REGION 0x164034
3705 /* [RW 8] Client2 context region. */
3706 #define TM_REG_CL2_CONT_REGION 0x164038
3707 /* [RW 2] Client in High priority client number. */
3708 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
3709 /* [RW 4] Load value for clout0 cred cnt. */
3710 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
3711 /* [RW 4] Load value for clout1 cred cnt. */
3712 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
3713 /* [RW 4] Load value for clout2 cred cnt. */
3714 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
3715 /* [RW 1] Enable client0 input. */
3716 #define TM_REG_EN_CL0_INPUT 0x164008
3717 /* [RW 1] Enable client1 input. */
3718 #define TM_REG_EN_CL1_INPUT 0x16400c
3719 /* [RW 1] Enable client2 input. */
3720 #define TM_REG_EN_CL2_INPUT 0x164010
3721 #define TM_REG_EN_LINEAR0_TIMER 0x164014
3722 /* [RW 1] Enable real time counter. */
3723 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
3724 /* [RW 1] Enable for Timers state machines. */
3725 #define TM_REG_EN_TIMERS 0x164000
3726 /* [RW 4] Load value for expiration credit cnt. CFC max number of
3727 outstanding load requests for timers (expiration) context loading. */
3728 #define TM_REG_EXP_CRDCNT_VAL 0x164238
3729 /* [RW 32] Linear0 logic address. */
3730 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
3731 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
3732 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
3733 /* [WB 64] Linear0 phy address. */
3734 #define TM_REG_LIN0_PHY_ADDR 0x164270
3735 /* [RW 1] Linear0 physical address valid. */
3736 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
3737 #define TM_REG_LIN0_SCAN_ON 0x1640d0
3738 /* [RW 24] Linear0 array scan timeout. */
3739 #define TM_REG_LIN0_SCAN_TIME 0x16403c
3740 /* [RW 32] Linear1 logic address. */
3741 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
3742 /* [WB 64] Linear1 phy address. */
3743 #define TM_REG_LIN1_PHY_ADDR 0x164280
3744 /* [RW 1] Linear1 physical address valid. */
3745 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
3746 /* [RW 6] Linear timer set_clear fifo threshold. */
3747 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
3748 /* [RW 2] Load value for pci arbiter credit cnt. */
3749 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
3750 /* [RW 20] The amount of hardware cycles for each timer tick. */
3751 #define TM_REG_TIMER_TICK_SIZE 0x16401c
3752 /* [RW 8] Timers Context region. */
3753 #define TM_REG_TM_CONTEXT_REGION 0x164044
3754 /* [RW 1] Interrupt mask register #0 read/write */
3755 #define TM_REG_TM_INT_MASK 0x1640fc
3756 /* [R 1] Interrupt register #0 read */
3757 #define TM_REG_TM_INT_STS 0x1640f0
3758 /* [RW 8] The event id for aggregated interrupt 0 */
3759 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
3760 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
3761 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
3762 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
3763 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
3764 /* [RW 1] The T bit for aggregated interrupt 0 */
3765 #define TSDM_REG_AGG_INT_T_0 0x420b8
3766 #define TSDM_REG_AGG_INT_T_1 0x420bc
3767 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3768 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
3769 /* [RW 16] The maximum value of the competion counter #0 */
3770 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
3771 /* [RW 16] The maximum value of the competion counter #1 */
3772 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
3773 /* [RW 16] The maximum value of the competion counter #2 */
3774 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
3775 /* [RW 16] The maximum value of the competion counter #3 */
3776 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
3777 /* [RW 13] The start address in the internal RAM for the completion
3779 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
3780 #define TSDM_REG_ENABLE_IN1 0x42238
3781 #define TSDM_REG_ENABLE_IN2 0x4223c
3782 #define TSDM_REG_ENABLE_OUT1 0x42240
3783 #define TSDM_REG_ENABLE_OUT2 0x42244
3784 /* [RW 4] The initial number of messages that can be sent to the pxp control
3785 interface without receiving any ACK. */
3786 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
3787 /* [ST 32] The number of ACK after placement messages received */
3788 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
3789 /* [ST 32] The number of packet end messages received from the parser */
3790 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
3791 /* [ST 32] The number of requests received from the pxp async if */
3792 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
3793 /* [ST 32] The number of commands received in queue 0 */
3794 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
3795 /* [ST 32] The number of commands received in queue 10 */
3796 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
3797 /* [ST 32] The number of commands received in queue 11 */
3798 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
3799 /* [ST 32] The number of commands received in queue 1 */
3800 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
3801 /* [ST 32] The number of commands received in queue 3 */
3802 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
3803 /* [ST 32] The number of commands received in queue 4 */
3804 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
3805 /* [ST 32] The number of commands received in queue 5 */
3806 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
3807 /* [ST 32] The number of commands received in queue 6 */
3808 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
3809 /* [ST 32] The number of commands received in queue 7 */
3810 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
3811 /* [ST 32] The number of commands received in queue 8 */
3812 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
3813 /* [ST 32] The number of commands received in queue 9 */
3814 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
3815 /* [RW 13] The start address in the internal RAM for the packet end message */
3816 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
3817 /* [RW 13] The start address in the internal RAM for queue counters */
3818 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
3819 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3820 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
3821 /* [R 1] parser fifo empty in sdm_sync block */
3822 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
3823 /* [R 1] parser serial fifo empty in sdm_sync block */
3824 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
3825 /* [RW 32] Tick for timer counter. Applicable only when
3826 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3827 #define TSDM_REG_TIMER_TICK 0x42000
3828 /* [RW 32] Interrupt mask register #0 read/write */
3829 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
3830 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
3831 /* [R 32] Interrupt register #0 read */
3832 #define TSDM_REG_TSDM_INT_STS_0 0x42290
3833 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
3834 /* [RW 11] Parity mask register #0 read/write */
3835 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
3836 /* [R 11] Parity register #0 read */
3837 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
3838 /* [RW 5] The number of time_slots in the arbitration cycle */
3839 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
3840 /* [RW 3] The source that is associated with arbitration element 0. Source
3841 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3842 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3843 #define TSEM_REG_ARB_ELEMENT0 0x180020
3844 /* [RW 3] The source that is associated with arbitration element 1. Source
3845 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3846 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3847 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
3848 #define TSEM_REG_ARB_ELEMENT1 0x180024
3849 /* [RW 3] The source that is associated with arbitration element 2. Source
3850 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3851 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3852 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3853 and ~tsem_registers_arb_element1.arb_element1 */
3854 #define TSEM_REG_ARB_ELEMENT2 0x180028
3855 /* [RW 3] The source that is associated with arbitration element 3. Source
3856 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3857 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3858 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
3859 ~tsem_registers_arb_element1.arb_element1 and
3860 ~tsem_registers_arb_element2.arb_element2 */
3861 #define TSEM_REG_ARB_ELEMENT3 0x18002c
3862 /* [RW 3] The source that is associated with arbitration element 4. Source
3863 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3864 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3865 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3866 and ~tsem_registers_arb_element1.arb_element1 and
3867 ~tsem_registers_arb_element2.arb_element2 and
3868 ~tsem_registers_arb_element3.arb_element3 */
3869 #define TSEM_REG_ARB_ELEMENT4 0x180030
3870 #define TSEM_REG_ENABLE_IN 0x1800a4
3871 #define TSEM_REG_ENABLE_OUT 0x1800a8
3872 /* [RW 32] This address space contains all registers and memories that are
3873 placed in SEM_FAST block. The SEM_FAST registers are described in
3874 appendix B. In order to access the sem_fast registers the base address
3875 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
3876 #define TSEM_REG_FAST_MEMORY 0x1a0000
3877 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3879 #define TSEM_REG_FIC0_DISABLE 0x180224
3880 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3882 #define TSEM_REG_FIC1_DISABLE 0x180234
3883 /* [RW 15] Interrupt table Read and write access to it is not possible in
3884 the middle of the work */
3885 #define TSEM_REG_INT_TABLE 0x180400
3886 /* [ST 24] Statistics register. The number of messages that entered through
3888 #define TSEM_REG_MSG_NUM_FIC0 0x180000
3889 /* [ST 24] Statistics register. The number of messages that entered through
3891 #define TSEM_REG_MSG_NUM_FIC1 0x180004
3892 /* [ST 24] Statistics register. The number of messages that were sent to
3894 #define TSEM_REG_MSG_NUM_FOC0 0x180008
3895 /* [ST 24] Statistics register. The number of messages that were sent to
3897 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
3898 /* [ST 24] Statistics register. The number of messages that were sent to
3900 #define TSEM_REG_MSG_NUM_FOC2 0x180010
3901 /* [ST 24] Statistics register. The number of messages that were sent to
3903 #define TSEM_REG_MSG_NUM_FOC3 0x180014
3904 /* [RW 1] Disables input messages from the passive buffer May be updated
3905 during run_time by the microcode */
3906 #define TSEM_REG_PAS_DISABLE 0x18024c
3907 /* [WB 128] Debug only. Passive buffer memory */
3908 #define TSEM_REG_PASSIVE_BUFFER 0x181000
3909 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3910 #define TSEM_REG_PRAM 0x1c0000
3911 /* [R 8] Valid sleeping threads indication have bit per thread */
3912 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
3913 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3914 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
3915 /* [RW 8] List of free threads . There is a bit per thread. */
3916 #define TSEM_REG_THREADS_LIST 0x1802e4
3917 /* [RW 3] The arbitration scheme of time_slot 0 */
3918 #define TSEM_REG_TS_0_AS 0x180038
3919 /* [RW 3] The arbitration scheme of time_slot 10 */
3920 #define TSEM_REG_TS_10_AS 0x180060
3921 /* [RW 3] The arbitration scheme of time_slot 11 */
3922 #define TSEM_REG_TS_11_AS 0x180064
3923 /* [RW 3] The arbitration scheme of time_slot 12 */
3924 #define TSEM_REG_TS_12_AS 0x180068
3925 /* [RW 3] The arbitration scheme of time_slot 13 */
3926 #define TSEM_REG_TS_13_AS 0x18006c
3927 /* [RW 3] The arbitration scheme of time_slot 14 */
3928 #define TSEM_REG_TS_14_AS 0x180070
3929 /* [RW 3] The arbitration scheme of time_slot 15 */
3930 #define TSEM_REG_TS_15_AS 0x180074
3931 /* [RW 3] The arbitration scheme of time_slot 16 */
3932 #define TSEM_REG_TS_16_AS 0x180078
3933 /* [RW 3] The arbitration scheme of time_slot 17 */
3934 #define TSEM_REG_TS_17_AS 0x18007c
3935 /* [RW 3] The arbitration scheme of time_slot 18 */
3936 #define TSEM_REG_TS_18_AS 0x180080
3937 /* [RW 3] The arbitration scheme of time_slot 1 */
3938 #define TSEM_REG_TS_1_AS 0x18003c
3939 /* [RW 3] The arbitration scheme of time_slot 2 */
3940 #define TSEM_REG_TS_2_AS 0x180040
3941 /* [RW 3] The arbitration scheme of time_slot 3 */
3942 #define TSEM_REG_TS_3_AS 0x180044
3943 /* [RW 3] The arbitration scheme of time_slot 4 */
3944 #define TSEM_REG_TS_4_AS 0x180048
3945 /* [RW 3] The arbitration scheme of time_slot 5 */
3946 #define TSEM_REG_TS_5_AS 0x18004c
3947 /* [RW 3] The arbitration scheme of time_slot 6 */
3948 #define TSEM_REG_TS_6_AS 0x180050
3949 /* [RW 3] The arbitration scheme of time_slot 7 */
3950 #define TSEM_REG_TS_7_AS 0x180054
3951 /* [RW 3] The arbitration scheme of time_slot 8 */
3952 #define TSEM_REG_TS_8_AS 0x180058
3953 /* [RW 3] The arbitration scheme of time_slot 9 */
3954 #define TSEM_REG_TS_9_AS 0x18005c
3955 /* [RW 32] Interrupt mask register #0 read/write */
3956 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
3957 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
3958 /* [R 32] Interrupt register #0 read */
3959 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
3960 #define TSEM_REG_TSEM_INT_STS_1 0x180104
3961 /* [RW 32] Parity mask register #0 read/write */
3962 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
3963 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
3964 /* [R 32] Parity register #0 read */
3965 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
3966 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
3967 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
3968 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
3969 #define TSEM_REG_VFPF_ERR_NUM 0x180380
3970 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
3971 * [10:8] of the address should be the offset within the accessed LCID
3972 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
3973 * LCID100. The RBC address should be 12'ha64. */
3974 #define UCM_REG_AG_CTX 0xe2000
3975 /* [R 5] Used to read the XX protection CAM occupancy counter. */
3976 #define UCM_REG_CAM_OCCUP 0xe0170
3977 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3978 disregarded; valid output is deasserted; all other signals are treated as
3979 usual; if 1 - normal activity. */
3980 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
3981 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3982 are disregarded; all other signals are treated as usual; if 1 - normal
3984 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
3985 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3986 disregarded; valid output is deasserted; all other signals are treated as
3987 usual; if 1 - normal activity. */
3988 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
3989 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3990 input is disregarded; all other signals are treated as usual; if 1 -
3992 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
3993 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3994 the initial credit value; read returns the current value of the credit
3995 counter. Must be initialized to 1 at start-up. */
3996 #define UCM_REG_CFC_INIT_CRD 0xe0204
3997 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3998 weight 8 (the most prioritised); 1 stands for weight 1(least
3999 prioritised); 2 stands for weight 2; tc. */
4000 #define UCM_REG_CP_WEIGHT 0xe00c4
4001 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4002 disregarded; acknowledge output is deasserted; all other signals are
4003 treated as usual; if 1 - normal activity. */
4004 #define UCM_REG_CSEM_IFEN 0xe0028
4005 /* [RC 1] Set when the message length mismatch (relative to last indication)
4006 at the csem interface is detected. */
4007 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4008 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4009 weight 8 (the most prioritised); 1 stands for weight 1(least
4010 prioritised); 2 stands for weight 2; tc. */
4011 #define UCM_REG_CSEM_WEIGHT 0xe00b8
4012 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4013 disregarded; acknowledge output is deasserted; all other signals are
4014 treated as usual; if 1 - normal activity. */
4015 #define UCM_REG_DORQ_IFEN 0xe0030
4016 /* [RC 1] Set when the message length mismatch (relative to last indication)
4017 at the dorq interface is detected. */
4018 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
4019 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4020 weight 8 (the most prioritised); 1 stands for weight 1(least
4021 prioritised); 2 stands for weight 2; tc. */
4022 #define UCM_REG_DORQ_WEIGHT 0xe00c0
4023 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4024 #define UCM_REG_ERR_EVNT_ID 0xe00a4
4025 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4026 #define UCM_REG_ERR_UCM_HDR 0xe00a0
4027 /* [RW 8] The Event ID for Timers expiration. */
4028 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
4029 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4030 writes the initial credit value; read returns the current value of the
4031 credit counter. Must be initialized to 64 at start-up. */
4032 #define UCM_REG_FIC0_INIT_CRD 0xe020c
4033 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4034 writes the initial credit value; read returns the current value of the
4035 credit counter. Must be initialized to 64 at start-up. */
4036 #define UCM_REG_FIC1_INIT_CRD 0xe0210
4037 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4038 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4039 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4040 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4041 #define UCM_REG_GR_ARB_TYPE 0xe0144
4042 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4043 highest priority is 3. It is supposed that the Store channel group is
4044 compliment to the others. */
4045 #define UCM_REG_GR_LD0_PR 0xe014c
4046 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4047 highest priority is 3. It is supposed that the Store channel group is
4048 compliment to the others. */
4049 #define UCM_REG_GR_LD1_PR 0xe0150
4050 /* [RW 2] The queue index for invalidate counter flag decision. */
4051 #define UCM_REG_INV_CFLG_Q 0xe00e4
4052 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4053 sent to STORM; for a specific connection type. the double REG-pairs are
4054 used in order to align to STORM context row size of 128 bits. The offset
4055 of these data in the STORM context is always 0. Index _i stands for the
4056 connection type (one of 16). */
4057 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
4058 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
4059 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
4060 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
4061 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
4062 #define UCM_REG_N_SM_CTX_LD_5 0xe0068
4063 #define UCM_REG_PHYS_QNUM0_0 0xe0110
4064 #define UCM_REG_PHYS_QNUM0_1 0xe0114
4065 #define UCM_REG_PHYS_QNUM1_0 0xe0118
4066 #define UCM_REG_PHYS_QNUM1_1 0xe011c
4067 #define UCM_REG_PHYS_QNUM2_0 0xe0120
4068 #define UCM_REG_PHYS_QNUM2_1 0xe0124
4069 #define UCM_REG_PHYS_QNUM3_0 0xe0128
4070 #define UCM_REG_PHYS_QNUM3_1 0xe012c
4071 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4072 #define UCM_REG_STOP_EVNT_ID 0xe00ac
4073 /* [RC 1] Set when the message length mismatch (relative to last indication)
4074 at the STORM interface is detected. */
4075 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
4076 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4077 disregarded; acknowledge output is deasserted; all other signals are
4078 treated as usual; if 1 - normal activity. */
4079 #define UCM_REG_STORM_UCM_IFEN 0xe0010
4080 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4081 weight 8 (the most prioritised); 1 stands for weight 1(least
4082 prioritised); 2 stands for weight 2; tc. */
4083 #define UCM_REG_STORM_WEIGHT 0xe00b0
4084 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4085 writes the initial credit value; read returns the current value of the
4086 credit counter. Must be initialized to 4 at start-up. */
4087 #define UCM_REG_TM_INIT_CRD 0xe021c
4088 /* [RW 28] The CM header for Timers expiration command. */
4089 #define UCM_REG_TM_UCM_HDR 0xe009c
4090 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4091 disregarded; acknowledge output is deasserted; all other signals are
4092 treated as usual; if 1 - normal activity. */
4093 #define UCM_REG_TM_UCM_IFEN 0xe001c
4094 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4095 weight 8 (the most prioritised); 1 stands for weight 1(least
4096 prioritised); 2 stands for weight 2; tc. */
4097 #define UCM_REG_TM_WEIGHT 0xe00d4
4098 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4099 disregarded; acknowledge output is deasserted; all other signals are
4100 treated as usual; if 1 - normal activity. */
4101 #define UCM_REG_TSEM_IFEN 0xe0024
4102 /* [RC 1] Set when the message length mismatch (relative to last indication)
4103 at the tsem interface is detected. */
4104 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4105 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4106 weight 8 (the most prioritised); 1 stands for weight 1(least
4107 prioritised); 2 stands for weight 2; tc. */
4108 #define UCM_REG_TSEM_WEIGHT 0xe00b4
4109 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4110 acknowledge output is deasserted; all other signals are treated as usual;
4111 if 1 - normal activity. */
4112 #define UCM_REG_UCM_CFC_IFEN 0xe0044
4113 /* [RW 11] Interrupt mask register #0 read/write */
4114 #define UCM_REG_UCM_INT_MASK 0xe01d4
4115 /* [R 11] Interrupt register #0 read */
4116 #define UCM_REG_UCM_INT_STS 0xe01c8
4117 /* [R 27] Parity register #0 read */
4118 #define UCM_REG_UCM_PRTY_STS 0xe01d8
4119 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4120 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4121 Is used to determine the number of the AG context REG-pairs written back;
4122 when the Reg1WbFlg isn't set. */
4123 #define UCM_REG_UCM_REG0_SZ 0xe00dc
4124 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4125 disregarded; valid is deasserted; all other signals are treated as usual;
4126 if 1 - normal activity. */
4127 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
4128 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4129 disregarded; valid is deasserted; all other signals are treated as usual;
4130 if 1 - normal activity. */
4131 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
4132 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4133 disregarded; acknowledge output is deasserted; all other signals are
4134 treated as usual; if 1 - normal activity. */
4135 #define UCM_REG_UCM_TM_IFEN 0xe0020
4136 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4137 disregarded; valid is deasserted; all other signals are treated as usual;
4138 if 1 - normal activity. */
4139 #define UCM_REG_UCM_UQM_IFEN 0xe000c
4140 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4141 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4142 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4143 the initial credit value; read returns the current value of the credit
4144 counter. Must be initialized to 32 at start-up. */
4145 #define UCM_REG_UQM_INIT_CRD 0xe0220
4146 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4147 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4148 prioritised); 2 stands for weight 2; tc. */
4149 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
4150 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4151 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4152 prioritised); 2 stands for weight 2; tc. */
4153 #define UCM_REG_UQM_S_WEIGHT 0xe00d0
4154 /* [RW 28] The CM header value for QM request (primary). */
4155 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
4156 /* [RW 28] The CM header value for QM request (secondary). */
4157 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
4158 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4159 acknowledge output is deasserted; all other signals are treated as usual;
4160 if 1 - normal activity. */
4161 #define UCM_REG_UQM_UCM_IFEN 0xe0014
4162 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4163 acknowledge output is deasserted; all other signals are treated as usual;
4164 if 1 - normal activity. */
4165 #define UCM_REG_USDM_IFEN 0xe0018
4166 /* [RC 1] Set when the message length mismatch (relative to last indication)
4167 at the SDM interface is detected. */
4168 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
4169 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4170 weight 8 (the most prioritised); 1 stands for weight 1(least
4171 prioritised); 2 stands for weight 2; tc. */
4172 #define UCM_REG_USDM_WEIGHT 0xe00c8
4173 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4174 disregarded; acknowledge output is deasserted; all other signals are
4175 treated as usual; if 1 - normal activity. */
4176 #define UCM_REG_XSEM_IFEN 0xe002c
4177 /* [RC 1] Set when the message length mismatch (relative to last indication)
4178 at the xsem interface isdetected. */
4179 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
4180 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4181 weight 8 (the most prioritised); 1 stands for weight 1(least
4182 prioritised); 2 stands for weight 2; tc. */
4183 #define UCM_REG_XSEM_WEIGHT 0xe00bc
4184 /* [RW 20] Indirect access to the descriptor table of the XX protection
4185 mechanism. The fields are:[5:0] - message length; 14:6] - message
4186 pointer; 19:15] - next pointer. */
4187 #define UCM_REG_XX_DESCR_TABLE 0xe0280
4188 #define UCM_REG_XX_DESCR_TABLE_SIZE 32
4189 /* [R 6] Use to read the XX protection Free counter. */
4190 #define UCM_REG_XX_FREE 0xe016c
4191 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4192 of the Input Stage XX protection buffer by the XX protection pending
4193 messages. Write writes the initial credit value; read returns the current
4194 value of the credit counter. Must be initialized to 12 at start-up. */
4195 #define UCM_REG_XX_INIT_CRD 0xe0224
4196 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4197 protection. ~ucm_registers_xx_free.xx_free read on read. */
4198 #define UCM_REG_XX_MSG_NUM 0xe0228
4199 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4200 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4201 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4202 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4204 #define UCM_REG_XX_TABLE 0xe0300
4205 /* [RW 8] The event id for aggregated interrupt 0 */
4206 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
4207 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
4208 #define USDM_REG_AGG_INT_EVENT_2 0xc4040
4209 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
4210 #define USDM_REG_AGG_INT_EVENT_5 0xc404c
4211 #define USDM_REG_AGG_INT_EVENT_6 0xc4050
4212 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4213 or auto-mask-mode (1) */
4214 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
4215 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
4216 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
4217 #define USDM_REG_AGG_INT_MODE_5 0xc41cc
4218 #define USDM_REG_AGG_INT_MODE_6 0xc41d0
4219 /* [RW 1] The T bit for aggregated interrupt 5 */
4220 #define USDM_REG_AGG_INT_T_5 0xc40cc
4221 #define USDM_REG_AGG_INT_T_6 0xc40d0
4222 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4223 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
4224 /* [RW 16] The maximum value of the competion counter #0 */
4225 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
4226 /* [RW 16] The maximum value of the competion counter #1 */
4227 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
4228 /* [RW 16] The maximum value of the competion counter #2 */
4229 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
4230 /* [RW 16] The maximum value of the competion counter #3 */
4231 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4232 /* [RW 13] The start address in the internal RAM for the completion
4234 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4235 #define USDM_REG_ENABLE_IN1 0xc4238
4236 #define USDM_REG_ENABLE_IN2 0xc423c
4237 #define USDM_REG_ENABLE_OUT1 0xc4240
4238 #define USDM_REG_ENABLE_OUT2 0xc4244
4239 /* [RW 4] The initial number of messages that can be sent to the pxp control
4240 interface without receiving any ACK. */
4241 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4242 /* [ST 32] The number of ACK after placement messages received */
4243 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4244 /* [ST 32] The number of packet end messages received from the parser */
4245 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4246 /* [ST 32] The number of requests received from the pxp async if */
4247 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4248 /* [ST 32] The number of commands received in queue 0 */
4249 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4250 /* [ST 32] The number of commands received in queue 10 */
4251 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4252 /* [ST 32] The number of commands received in queue 11 */
4253 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4254 /* [ST 32] The number of commands received in queue 1 */
4255 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4256 /* [ST 32] The number of commands received in queue 2 */
4257 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4258 /* [ST 32] The number of commands received in queue 3 */
4259 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4260 /* [ST 32] The number of commands received in queue 4 */
4261 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4262 /* [ST 32] The number of commands received in queue 5 */
4263 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4264 /* [ST 32] The number of commands received in queue 6 */
4265 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4266 /* [ST 32] The number of commands received in queue 7 */
4267 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4268 /* [ST 32] The number of commands received in queue 8 */
4269 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4270 /* [ST 32] The number of commands received in queue 9 */
4271 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4272 /* [RW 13] The start address in the internal RAM for the packet end message */
4273 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4274 /* [RW 13] The start address in the internal RAM for queue counters */
4275 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4276 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4277 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4278 /* [R 1] parser fifo empty in sdm_sync block */
4279 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4280 /* [R 1] parser serial fifo empty in sdm_sync block */
4281 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4282 /* [RW 32] Tick for timer counter. Applicable only when
4283 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4284 #define USDM_REG_TIMER_TICK 0xc4000
4285 /* [RW 32] Interrupt mask register #0 read/write */
4286 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
4287 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
4288 /* [R 32] Interrupt register #0 read */
4289 #define USDM_REG_USDM_INT_STS_0 0xc4294
4290 #define USDM_REG_USDM_INT_STS_1 0xc42a4
4291 /* [RW 11] Parity mask register #0 read/write */
4292 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
4293 /* [R 11] Parity register #0 read */
4294 #define USDM_REG_USDM_PRTY_STS 0xc42b4
4295 /* [RW 5] The number of time_slots in the arbitration cycle */
4296 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
4297 /* [RW 3] The source that is associated with arbitration element 0. Source
4298 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4299 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4300 #define USEM_REG_ARB_ELEMENT0 0x300020
4301 /* [RW 3] The source that is associated with arbitration element 1. Source
4302 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4303 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4304 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4305 #define USEM_REG_ARB_ELEMENT1 0x300024
4306 /* [RW 3] The source that is associated with arbitration element 2. Source
4307 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4308 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4309 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4310 and ~usem_registers_arb_element1.arb_element1 */
4311 #define USEM_REG_ARB_ELEMENT2 0x300028
4312 /* [RW 3] The source that is associated with arbitration element 3. Source
4313 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4314 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4315 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4316 ~usem_registers_arb_element1.arb_element1 and
4317 ~usem_registers_arb_element2.arb_element2 */
4318 #define USEM_REG_ARB_ELEMENT3 0x30002c
4319 /* [RW 3] The source that is associated with arbitration element 4. Source
4320 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4321 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4322 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4323 and ~usem_registers_arb_element1.arb_element1 and
4324 ~usem_registers_arb_element2.arb_element2 and
4325 ~usem_registers_arb_element3.arb_element3 */
4326 #define USEM_REG_ARB_ELEMENT4 0x300030
4327 #define USEM_REG_ENABLE_IN 0x3000a4
4328 #define USEM_REG_ENABLE_OUT 0x3000a8
4329 /* [RW 32] This address space contains all registers and memories that are
4330 placed in SEM_FAST block. The SEM_FAST registers are described in
4331 appendix B. In order to access the sem_fast registers the base address
4332 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4333 #define USEM_REG_FAST_MEMORY 0x320000
4334 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4336 #define USEM_REG_FIC0_DISABLE 0x300224
4337 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4339 #define USEM_REG_FIC1_DISABLE 0x300234
4340 /* [RW 15] Interrupt table Read and write access to it is not possible in
4341 the middle of the work */
4342 #define USEM_REG_INT_TABLE 0x300400
4343 /* [ST 24] Statistics register. The number of messages that entered through
4345 #define USEM_REG_MSG_NUM_FIC0 0x300000
4346 /* [ST 24] Statistics register. The number of messages that entered through
4348 #define USEM_REG_MSG_NUM_FIC1 0x300004
4349 /* [ST 24] Statistics register. The number of messages that were sent to
4351 #define USEM_REG_MSG_NUM_FOC0 0x300008
4352 /* [ST 24] Statistics register. The number of messages that were sent to
4354 #define USEM_REG_MSG_NUM_FOC1 0x30000c
4355 /* [ST 24] Statistics register. The number of messages that were sent to
4357 #define USEM_REG_MSG_NUM_FOC2 0x300010
4358 /* [ST 24] Statistics register. The number of messages that were sent to
4360 #define USEM_REG_MSG_NUM_FOC3 0x300014
4361 /* [RW 1] Disables input messages from the passive buffer May be updated
4362 during run_time by the microcode */
4363 #define USEM_REG_PAS_DISABLE 0x30024c
4364 /* [WB 128] Debug only. Passive buffer memory */
4365 #define USEM_REG_PASSIVE_BUFFER 0x302000
4366 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4367 #define USEM_REG_PRAM 0x340000
4368 /* [R 16] Valid sleeping threads indication have bit per thread */
4369 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
4370 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4371 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
4372 /* [RW 16] List of free threads . There is a bit per thread. */
4373 #define USEM_REG_THREADS_LIST 0x3002e4
4374 /* [RW 3] The arbitration scheme of time_slot 0 */
4375 #define USEM_REG_TS_0_AS 0x300038
4376 /* [RW 3] The arbitration scheme of time_slot 10 */
4377 #define USEM_REG_TS_10_AS 0x300060
4378 /* [RW 3] The arbitration scheme of time_slot 11 */
4379 #define USEM_REG_TS_11_AS 0x300064
4380 /* [RW 3] The arbitration scheme of time_slot 12 */
4381 #define USEM_REG_TS_12_AS 0x300068
4382 /* [RW 3] The arbitration scheme of time_slot 13 */
4383 #define USEM_REG_TS_13_AS 0x30006c
4384 /* [RW 3] The arbitration scheme of time_slot 14 */
4385 #define USEM_REG_TS_14_AS 0x300070
4386 /* [RW 3] The arbitration scheme of time_slot 15 */
4387 #define USEM_REG_TS_15_AS 0x300074
4388 /* [RW 3] The arbitration scheme of time_slot 16 */
4389 #define USEM_REG_TS_16_AS 0x300078
4390 /* [RW 3] The arbitration scheme of time_slot 17 */
4391 #define USEM_REG_TS_17_AS 0x30007c
4392 /* [RW 3] The arbitration scheme of time_slot 18 */
4393 #define USEM_REG_TS_18_AS 0x300080
4394 /* [RW 3] The arbitration scheme of time_slot 1 */
4395 #define USEM_REG_TS_1_AS 0x30003c
4396 /* [RW 3] The arbitration scheme of time_slot 2 */
4397 #define USEM_REG_TS_2_AS 0x300040
4398 /* [RW 3] The arbitration scheme of time_slot 3 */
4399 #define USEM_REG_TS_3_AS 0x300044
4400 /* [RW 3] The arbitration scheme of time_slot 4 */
4401 #define USEM_REG_TS_4_AS 0x300048
4402 /* [RW 3] The arbitration scheme of time_slot 5 */
4403 #define USEM_REG_TS_5_AS 0x30004c
4404 /* [RW 3] The arbitration scheme of time_slot 6 */
4405 #define USEM_REG_TS_6_AS 0x300050
4406 /* [RW 3] The arbitration scheme of time_slot 7 */
4407 #define USEM_REG_TS_7_AS 0x300054
4408 /* [RW 3] The arbitration scheme of time_slot 8 */
4409 #define USEM_REG_TS_8_AS 0x300058
4410 /* [RW 3] The arbitration scheme of time_slot 9 */
4411 #define USEM_REG_TS_9_AS 0x30005c
4412 /* [RW 32] Interrupt mask register #0 read/write */
4413 #define USEM_REG_USEM_INT_MASK_0 0x300110
4414 #define USEM_REG_USEM_INT_MASK_1 0x300120
4415 /* [R 32] Interrupt register #0 read */
4416 #define USEM_REG_USEM_INT_STS_0 0x300104
4417 #define USEM_REG_USEM_INT_STS_1 0x300114
4418 /* [RW 32] Parity mask register #0 read/write */
4419 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
4420 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
4421 /* [R 32] Parity register #0 read */
4422 #define USEM_REG_USEM_PRTY_STS_0 0x300124
4423 #define USEM_REG_USEM_PRTY_STS_1 0x300134
4424 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4425 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4426 #define USEM_REG_VFPF_ERR_NUM 0x300380
4427 #define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
4428 #define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
4429 #define VFC_REG_MEMORIES_RST 0x1943c
4430 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4431 * [12:8] of the address should be the offset within the accessed LCID
4432 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4433 * LCID100. The RBC address should be 13'ha64. */
4434 #define XCM_REG_AG_CTX 0x28000
4435 /* [RW 2] The queue index for registration on Aux1 counter flag. */
4436 #define XCM_REG_AUX1_Q 0x20134
4437 /* [RW 2] Per each decision rule the queue index to register to. */
4438 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
4439 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4440 #define XCM_REG_CAM_OCCUP 0x20244
4441 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4442 disregarded; valid output is deasserted; all other signals are treated as
4443 usual; if 1 - normal activity. */
4444 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
4445 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4446 are disregarded; all other signals are treated as usual; if 1 - normal
4448 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
4449 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4450 disregarded; valid output is deasserted; all other signals are treated as
4451 usual; if 1 - normal activity. */
4452 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
4453 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4454 input is disregarded; all other signals are treated as usual; if 1 -
4456 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
4457 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4458 the initial credit value; read returns the current value of the credit
4459 counter. Must be initialized to 1 at start-up. */
4460 #define XCM_REG_CFC_INIT_CRD 0x20404
4461 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4462 weight 8 (the most prioritised); 1 stands for weight 1(least
4463 prioritised); 2 stands for weight 2; tc. */
4464 #define XCM_REG_CP_WEIGHT 0x200dc
4465 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4466 disregarded; acknowledge output is deasserted; all other signals are
4467 treated as usual; if 1 - normal activity. */
4468 #define XCM_REG_CSEM_IFEN 0x20028
4469 /* [RC 1] Set at message length mismatch (relative to last indication) at
4470 the csem interface. */
4471 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
4472 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4473 weight 8 (the most prioritised); 1 stands for weight 1(least
4474 prioritised); 2 stands for weight 2; tc. */
4475 #define XCM_REG_CSEM_WEIGHT 0x200c4
4476 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4477 disregarded; acknowledge output is deasserted; all other signals are
4478 treated as usual; if 1 - normal activity. */
4479 #define XCM_REG_DORQ_IFEN 0x20030
4480 /* [RC 1] Set at message length mismatch (relative to last indication) at
4481 the dorq interface. */
4482 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
4483 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4484 weight 8 (the most prioritised); 1 stands for weight 1(least
4485 prioritised); 2 stands for weight 2; tc. */
4486 #define XCM_REG_DORQ_WEIGHT 0x200cc
4487 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
4488 #define XCM_REG_ERR_EVNT_ID 0x200b0
4489 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4490 #define XCM_REG_ERR_XCM_HDR 0x200ac
4491 /* [RW 8] The Event ID for Timers expiration. */
4492 #define XCM_REG_EXPR_EVNT_ID 0x200b4
4493 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4494 writes the initial credit value; read returns the current value of the
4495 credit counter. Must be initialized to 64 at start-up. */
4496 #define XCM_REG_FIC0_INIT_CRD 0x2040c
4497 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4498 writes the initial credit value; read returns the current value of the
4499 credit counter. Must be initialized to 64 at start-up. */
4500 #define XCM_REG_FIC1_INIT_CRD 0x20410
4501 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
4502 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
4503 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
4504 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
4505 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
4506 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
4507 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
4508 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
4509 #define XCM_REG_GR_ARB_TYPE 0x2020c
4510 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4511 highest priority is 3. It is supposed that the Channel group is the
4512 compliment of the other 3 groups. */
4513 #define XCM_REG_GR_LD0_PR 0x20214
4514 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4515 highest priority is 3. It is supposed that the Channel group is the
4516 compliment of the other 3 groups. */
4517 #define XCM_REG_GR_LD1_PR 0x20218
4518 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
4519 disregarded; acknowledge output is deasserted; all other signals are
4520 treated as usual; if 1 - normal activity. */
4521 #define XCM_REG_NIG0_IFEN 0x20038
4522 /* [RC 1] Set at message length mismatch (relative to last indication) at
4523 the nig0 interface. */
4524 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
4525 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
4526 weight 8 (the most prioritised); 1 stands for weight 1(least
4527 prioritised); 2 stands for weight 2; tc. */
4528 #define XCM_REG_NIG0_WEIGHT 0x200d4
4529 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
4530 disregarded; acknowledge output is deasserted; all other signals are
4531 treated as usual; if 1 - normal activity. */
4532 #define XCM_REG_NIG1_IFEN 0x2003c
4533 /* [RC 1] Set at message length mismatch (relative to last indication) at
4534 the nig1 interface. */
4535 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
4536 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4537 sent to STORM; for a specific connection type. The double REG-pairs are
4538 used in order to align to STORM context row size of 128 bits. The offset
4539 of these data in the STORM context is always 0. Index _i stands for the
4540 connection type (one of 16). */
4541 #define XCM_REG_N_SM_CTX_LD_0 0x20060
4542 #define XCM_REG_N_SM_CTX_LD_1 0x20064
4543 #define XCM_REG_N_SM_CTX_LD_2 0x20068
4544 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
4545 #define XCM_REG_N_SM_CTX_LD_4 0x20070
4546 #define XCM_REG_N_SM_CTX_LD_5 0x20074
4547 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4548 acknowledge output is deasserted; all other signals are treated as usual;
4549 if 1 - normal activity. */
4550 #define XCM_REG_PBF_IFEN 0x20034
4551 /* [RC 1] Set at message length mismatch (relative to last indication) at
4552 the pbf interface. */
4553 #define XCM_REG_PBF_LENGTH_MIS 0x20234
4554 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4555 weight 8 (the most prioritised); 1 stands for weight 1(least
4556 prioritised); 2 stands for weight 2; tc. */
4557 #define XCM_REG_PBF_WEIGHT 0x200d0
4558 #define XCM_REG_PHYS_QNUM3_0 0x20100
4559 #define XCM_REG_PHYS_QNUM3_1 0x20104
4560 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4561 #define XCM_REG_STOP_EVNT_ID 0x200b8
4562 /* [RC 1] Set at message length mismatch (relative to last indication) at
4563 the STORM interface. */
4564 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
4565 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4566 weight 8 (the most prioritised); 1 stands for weight 1(least
4567 prioritised); 2 stands for weight 2; tc. */
4568 #define XCM_REG_STORM_WEIGHT 0x200bc
4569 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4570 disregarded; acknowledge output is deasserted; all other signals are
4571 treated as usual; if 1 - normal activity. */
4572 #define XCM_REG_STORM_XCM_IFEN 0x20010
4573 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4574 writes the initial credit value; read returns the current value of the
4575 credit counter. Must be initialized to 4 at start-up. */
4576 #define XCM_REG_TM_INIT_CRD 0x2041c
4577 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4578 weight 8 (the most prioritised); 1 stands for weight 1(least
4579 prioritised); 2 stands for weight 2; tc. */
4580 #define XCM_REG_TM_WEIGHT 0x200ec
4581 /* [RW 28] The CM header for Timers expiration command. */
4582 #define XCM_REG_TM_XCM_HDR 0x200a8
4583 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4584 disregarded; acknowledge output is deasserted; all other signals are
4585 treated as usual; if 1 - normal activity. */
4586 #define XCM_REG_TM_XCM_IFEN 0x2001c
4587 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4588 disregarded; acknowledge output is deasserted; all other signals are
4589 treated as usual; if 1 - normal activity. */
4590 #define XCM_REG_TSEM_IFEN 0x20024
4591 /* [RC 1] Set at message length mismatch (relative to last indication) at
4592 the tsem interface. */
4593 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
4594 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4595 weight 8 (the most prioritised); 1 stands for weight 1(least
4596 prioritised); 2 stands for weight 2; tc. */
4597 #define XCM_REG_TSEM_WEIGHT 0x200c0
4598 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
4599 #define XCM_REG_UNA_GT_NXT_Q 0x20120
4600 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4601 disregarded; acknowledge output is deasserted; all other signals are
4602 treated as usual; if 1 - normal activity. */
4603 #define XCM_REG_USEM_IFEN 0x2002c
4604 /* [RC 1] Message length mismatch (relative to last indication) at the usem
4606 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
4607 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4608 weight 8 (the most prioritised); 1 stands for weight 1(least
4609 prioritised); 2 stands for weight 2; tc. */
4610 #define XCM_REG_USEM_WEIGHT 0x200c8
4611 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
4612 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
4613 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
4614 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
4615 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
4616 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
4617 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
4618 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
4619 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
4620 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
4621 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
4622 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
4623 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4624 acknowledge output is deasserted; all other signals are treated as usual;
4625 if 1 - normal activity. */
4626 #define XCM_REG_XCM_CFC_IFEN 0x20050
4627 /* [RW 14] Interrupt mask register #0 read/write */
4628 #define XCM_REG_XCM_INT_MASK 0x202b4
4629 /* [R 14] Interrupt register #0 read */
4630 #define XCM_REG_XCM_INT_STS 0x202a8
4631 /* [R 30] Parity register #0 read */
4632 #define XCM_REG_XCM_PRTY_STS 0x202b8
4633 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
4634 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4635 Is used to determine the number of the AG context REG-pairs written back;
4636 when the Reg1WbFlg isn't set. */
4637 #define XCM_REG_XCM_REG0_SZ 0x200f4
4638 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4639 disregarded; valid is deasserted; all other signals are treated as usual;
4640 if 1 - normal activity. */
4641 #define XCM_REG_XCM_STORM0_IFEN 0x20004
4642 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4643 disregarded; valid is deasserted; all other signals are treated as usual;
4644 if 1 - normal activity. */
4645 #define XCM_REG_XCM_STORM1_IFEN 0x20008
4646 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4647 disregarded; acknowledge output is deasserted; all other signals are
4648 treated as usual; if 1 - normal activity. */
4649 #define XCM_REG_XCM_TM_IFEN 0x20020
4650 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4651 disregarded; valid is deasserted; all other signals are treated as usual;
4652 if 1 - normal activity. */
4653 #define XCM_REG_XCM_XQM_IFEN 0x2000c
4654 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4655 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
4656 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
4657 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
4658 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4659 the initial credit value; read returns the current value of the credit
4660 counter. Must be initialized to 32 at start-up. */
4661 #define XCM_REG_XQM_INIT_CRD 0x20420
4662 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4663 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4664 prioritised); 2 stands for weight 2; tc. */
4665 #define XCM_REG_XQM_P_WEIGHT 0x200e4
4666 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4667 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4668 prioritised); 2 stands for weight 2; tc. */
4669 #define XCM_REG_XQM_S_WEIGHT 0x200e8
4670 /* [RW 28] The CM header value for QM request (primary). */
4671 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
4672 /* [RW 28] The CM header value for QM request (secondary). */
4673 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
4674 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4675 acknowledge output is deasserted; all other signals are treated as usual;
4676 if 1 - normal activity. */
4677 #define XCM_REG_XQM_XCM_IFEN 0x20014
4678 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4679 acknowledge output is deasserted; all other signals are treated as usual;
4680 if 1 - normal activity. */
4681 #define XCM_REG_XSDM_IFEN 0x20018
4682 /* [RC 1] Set at message length mismatch (relative to last indication) at
4683 the SDM interface. */
4684 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
4685 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4686 weight 8 (the most prioritised); 1 stands for weight 1(least
4687 prioritised); 2 stands for weight 2; tc. */
4688 #define XCM_REG_XSDM_WEIGHT 0x200e0
4689 /* [RW 17] Indirect access to the descriptor table of the XX protection
4690 mechanism. The fields are: [5:0] - message length; 11:6] - message
4691 pointer; 16:12] - next pointer. */
4692 #define XCM_REG_XX_DESCR_TABLE 0x20480
4693 #define XCM_REG_XX_DESCR_TABLE_SIZE 32
4694 /* [R 6] Used to read the XX protection Free counter. */
4695 #define XCM_REG_XX_FREE 0x20240
4696 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4697 of the Input Stage XX protection buffer by the XX protection pending
4698 messages. Max credit available - 3.Write writes the initial credit value;
4699 read returns the current value of the credit counter. Must be initialized
4700 to 2 at start-up. */
4701 #define XCM_REG_XX_INIT_CRD 0x20424
4702 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4703 protection. ~xcm_registers_xx_free.xx_free read on read. */
4704 #define XCM_REG_XX_MSG_NUM 0x20428
4705 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4706 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
4707 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4708 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
4710 #define XCM_REG_XX_TABLE 0x20500
4711 /* [RW 8] The event id for aggregated interrupt 0 */
4712 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
4713 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
4714 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
4715 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
4716 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
4717 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4718 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
4719 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
4720 #define XSDM_REG_AGG_INT_EVENT_3 0x166044
4721 #define XSDM_REG_AGG_INT_EVENT_4 0x166048
4722 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4723 #define XSDM_REG_AGG_INT_EVENT_6 0x166050
4724 #define XSDM_REG_AGG_INT_EVENT_7 0x166054
4725 #define XSDM_REG_AGG_INT_EVENT_8 0x166058
4726 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c
4727 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4728 or auto-mask-mode (1) */
4729 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
4730 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
4731 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4732 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
4733 /* [RW 16] The maximum value of the competion counter #0 */
4734 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
4735 /* [RW 16] The maximum value of the competion counter #1 */
4736 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
4737 /* [RW 16] The maximum value of the competion counter #2 */
4738 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
4739 /* [RW 16] The maximum value of the competion counter #3 */
4740 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
4741 /* [RW 13] The start address in the internal RAM for the completion
4743 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
4744 #define XSDM_REG_ENABLE_IN1 0x166238
4745 #define XSDM_REG_ENABLE_IN2 0x16623c
4746 #define XSDM_REG_ENABLE_OUT1 0x166240
4747 #define XSDM_REG_ENABLE_OUT2 0x166244
4748 /* [RW 4] The initial number of messages that can be sent to the pxp control
4749 interface without receiving any ACK. */
4750 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
4751 /* [ST 32] The number of ACK after placement messages received */
4752 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
4753 /* [ST 32] The number of packet end messages received from the parser */
4754 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
4755 /* [ST 32] The number of requests received from the pxp async if */
4756 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
4757 /* [ST 32] The number of commands received in queue 0 */
4758 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
4759 /* [ST 32] The number of commands received in queue 10 */
4760 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
4761 /* [ST 32] The number of commands received in queue 11 */
4762 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
4763 /* [ST 32] The number of commands received in queue 1 */
4764 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
4765 /* [ST 32] The number of commands received in queue 3 */
4766 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
4767 /* [ST 32] The number of commands received in queue 4 */
4768 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
4769 /* [ST 32] The number of commands received in queue 5 */
4770 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
4771 /* [ST 32] The number of commands received in queue 6 */
4772 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
4773 /* [ST 32] The number of commands received in queue 7 */
4774 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
4775 /* [ST 32] The number of commands received in queue 8 */
4776 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
4777 /* [ST 32] The number of commands received in queue 9 */
4778 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
4779 /* [RW 13] The start address in the internal RAM for queue counters */
4780 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
4781 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4782 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
4783 /* [R 1] parser fifo empty in sdm_sync block */
4784 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
4785 /* [R 1] parser serial fifo empty in sdm_sync block */
4786 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
4787 /* [RW 32] Tick for timer counter. Applicable only when
4788 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4789 #define XSDM_REG_TIMER_TICK 0x166000
4790 /* [RW 32] Interrupt mask register #0 read/write */
4791 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
4792 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
4793 /* [R 32] Interrupt register #0 read */
4794 #define XSDM_REG_XSDM_INT_STS_0 0x166290
4795 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0
4796 /* [RW 11] Parity mask register #0 read/write */
4797 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
4798 /* [R 11] Parity register #0 read */
4799 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
4800 /* [RW 5] The number of time_slots in the arbitration cycle */
4801 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
4802 /* [RW 3] The source that is associated with arbitration element 0. Source
4803 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4804 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4805 #define XSEM_REG_ARB_ELEMENT0 0x280020
4806 /* [RW 3] The source that is associated with arbitration element 1. Source
4807 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4808 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4809 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
4810 #define XSEM_REG_ARB_ELEMENT1 0x280024
4811 /* [RW 3] The source that is associated with arbitration element 2. Source
4812 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4813 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4814 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4815 and ~xsem_registers_arb_element1.arb_element1 */
4816 #define XSEM_REG_ARB_ELEMENT2 0x280028
4817 /* [RW 3] The source that is associated with arbitration element 3. Source
4818 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4819 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4820 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
4821 ~xsem_registers_arb_element1.arb_element1 and
4822 ~xsem_registers_arb_element2.arb_element2 */
4823 #define XSEM_REG_ARB_ELEMENT3 0x28002c
4824 /* [RW 3] The source that is associated with arbitration element 4. Source
4825 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4826 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4827 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
4828 and ~xsem_registers_arb_element1.arb_element1 and
4829 ~xsem_registers_arb_element2.arb_element2 and
4830 ~xsem_registers_arb_element3.arb_element3 */
4831 #define XSEM_REG_ARB_ELEMENT4 0x280030
4832 #define XSEM_REG_ENABLE_IN 0x2800a4
4833 #define XSEM_REG_ENABLE_OUT 0x2800a8
4834 /* [RW 32] This address space contains all registers and memories that are
4835 placed in SEM_FAST block. The SEM_FAST registers are described in
4836 appendix B. In order to access the sem_fast registers the base address
4837 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4838 #define XSEM_REG_FAST_MEMORY 0x2a0000
4839 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4841 #define XSEM_REG_FIC0_DISABLE 0x280224
4842 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4844 #define XSEM_REG_FIC1_DISABLE 0x280234
4845 /* [RW 15] Interrupt table Read and write access to it is not possible in
4846 the middle of the work */
4847 #define XSEM_REG_INT_TABLE 0x280400
4848 /* [ST 24] Statistics register. The number of messages that entered through
4850 #define XSEM_REG_MSG_NUM_FIC0 0x280000
4851 /* [ST 24] Statistics register. The number of messages that entered through
4853 #define XSEM_REG_MSG_NUM_FIC1 0x280004
4854 /* [ST 24] Statistics register. The number of messages that were sent to
4856 #define XSEM_REG_MSG_NUM_FOC0 0x280008
4857 /* [ST 24] Statistics register. The number of messages that were sent to
4859 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
4860 /* [ST 24] Statistics register. The number of messages that were sent to
4862 #define XSEM_REG_MSG_NUM_FOC2 0x280010
4863 /* [ST 24] Statistics register. The number of messages that were sent to
4865 #define XSEM_REG_MSG_NUM_FOC3 0x280014
4866 /* [RW 1] Disables input messages from the passive buffer May be updated
4867 during run_time by the microcode */
4868 #define XSEM_REG_PAS_DISABLE 0x28024c
4869 /* [WB 128] Debug only. Passive buffer memory */
4870 #define XSEM_REG_PASSIVE_BUFFER 0x282000
4871 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4872 #define XSEM_REG_PRAM 0x2c0000
4873 /* [R 16] Valid sleeping threads indication have bit per thread */
4874 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
4875 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4876 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
4877 /* [RW 16] List of free threads . There is a bit per thread. */
4878 #define XSEM_REG_THREADS_LIST 0x2802e4
4879 /* [RW 3] The arbitration scheme of time_slot 0 */
4880 #define XSEM_REG_TS_0_AS 0x280038
4881 /* [RW 3] The arbitration scheme of time_slot 10 */
4882 #define XSEM_REG_TS_10_AS 0x280060
4883 /* [RW 3] The arbitration scheme of time_slot 11 */
4884 #define XSEM_REG_TS_11_AS 0x280064
4885 /* [RW 3] The arbitration scheme of time_slot 12 */
4886 #define XSEM_REG_TS_12_AS 0x280068
4887 /* [RW 3] The arbitration scheme of time_slot 13 */
4888 #define XSEM_REG_TS_13_AS 0x28006c
4889 /* [RW 3] The arbitration scheme of time_slot 14 */
4890 #define XSEM_REG_TS_14_AS 0x280070
4891 /* [RW 3] The arbitration scheme of time_slot 15 */
4892 #define XSEM_REG_TS_15_AS 0x280074
4893 /* [RW 3] The arbitration scheme of time_slot 16 */
4894 #define XSEM_REG_TS_16_AS 0x280078
4895 /* [RW 3] The arbitration scheme of time_slot 17 */
4896 #define XSEM_REG_TS_17_AS 0x28007c
4897 /* [RW 3] The arbitration scheme of time_slot 18 */
4898 #define XSEM_REG_TS_18_AS 0x280080
4899 /* [RW 3] The arbitration scheme of time_slot 1 */
4900 #define XSEM_REG_TS_1_AS 0x28003c
4901 /* [RW 3] The arbitration scheme of time_slot 2 */
4902 #define XSEM_REG_TS_2_AS 0x280040
4903 /* [RW 3] The arbitration scheme of time_slot 3 */
4904 #define XSEM_REG_TS_3_AS 0x280044
4905 /* [RW 3] The arbitration scheme of time_slot 4 */
4906 #define XSEM_REG_TS_4_AS 0x280048
4907 /* [RW 3] The arbitration scheme of time_slot 5 */
4908 #define XSEM_REG_TS_5_AS 0x28004c
4909 /* [RW 3] The arbitration scheme of time_slot 6 */
4910 #define XSEM_REG_TS_6_AS 0x280050
4911 /* [RW 3] The arbitration scheme of time_slot 7 */
4912 #define XSEM_REG_TS_7_AS 0x280054
4913 /* [RW 3] The arbitration scheme of time_slot 8 */
4914 #define XSEM_REG_TS_8_AS 0x280058
4915 /* [RW 3] The arbitration scheme of time_slot 9 */
4916 #define XSEM_REG_TS_9_AS 0x28005c
4917 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4918 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4919 #define XSEM_REG_VFPF_ERR_NUM 0x280380
4920 /* [RW 32] Interrupt mask register #0 read/write */
4921 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
4922 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
4923 /* [R 32] Interrupt register #0 read */
4924 #define XSEM_REG_XSEM_INT_STS_0 0x280104
4925 #define XSEM_REG_XSEM_INT_STS_1 0x280114
4926 /* [RW 32] Parity mask register #0 read/write */
4927 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
4928 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
4929 /* [R 32] Parity register #0 read */
4930 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
4931 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
4932 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
4933 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
4934 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
4935 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
4936 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
4937 #define MCPR_NVM_COMMAND_DONE (1L<<3)
4938 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
4939 #define MCPR_NVM_COMMAND_LAST (1L<<8)
4940 #define MCPR_NVM_COMMAND_WR (1L<<5)
4941 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
4942 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
4943 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
4944 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
4945 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
4946 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
4947 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
4948 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
4949 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
4950 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
4951 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
4952 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
4953 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
4954 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
4955 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
4956 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
4957 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
4958 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
4959 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
4960 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
4961 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
4962 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
4963 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
4964 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
4965 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
4966 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
4967 #define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)
4968 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
4969 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
4970 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
4971 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
4972 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
4973 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
4974 #define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)
4975 #define EMAC_LED_1000MB_OVERRIDE (1L<<1)
4976 #define EMAC_LED_100MB_OVERRIDE (1L<<2)
4977 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
4978 #define EMAC_LED_2500MB_OVERRIDE (1L<<12)
4979 #define EMAC_LED_OVERRIDE (1L<<0)
4980 #define EMAC_LED_TRAFFIC (1L<<6)
4981 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
4982 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
4983 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
4984 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
4985 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
4986 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
4987 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
4988 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
4989 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
4990 #define EMAC_MODE_25G_MODE (1L<<5)
4991 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
4992 #define EMAC_MODE_PORT_GMII (2L<<2)
4993 #define EMAC_MODE_PORT_MII (1L<<2)
4994 #define EMAC_MODE_PORT_MII_10M (3L<<2)
4995 #define EMAC_MODE_RESET (1L<<0)
4996 #define EMAC_REG_EMAC_LED 0xc
4997 #define EMAC_REG_EMAC_MAC_MATCH 0x10
4998 #define EMAC_REG_EMAC_MDIO_COMM 0xac
4999 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
5000 #define EMAC_REG_EMAC_MODE 0x0
5001 #define EMAC_REG_EMAC_RX_MODE 0xc8
5002 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5003 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
5004 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5005 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5006 #define EMAC_REG_EMAC_TX_MODE 0xbc
5007 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
5008 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
5009 #define EMAC_REG_RX_PFC_MODE 0x320
5010 #define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
5011 #define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
5012 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
5013 #define EMAC_REG_RX_PFC_PARAM 0x324
5014 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
5015 #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
5016 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
5017 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
5018 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
5019 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
5020 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
5021 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
5022 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
5023 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
5024 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
5025 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
5026 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5027 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
5028 #define EMAC_RX_MODE_RESET (1L<<0)
5029 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5030 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
5031 #define EMAC_TX_MODE_FLOW_EN (1L<<4)
5032 #define EMAC_TX_MODE_RESET (1L<<0)
5033 #define MISC_REGISTERS_GPIO_0 0
5034 #define MISC_REGISTERS_GPIO_1 1
5035 #define MISC_REGISTERS_GPIO_2 2
5036 #define MISC_REGISTERS_GPIO_3 3
5037 #define MISC_REGISTERS_GPIO_CLR_POS 16
5038 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5039 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
5040 #define MISC_REGISTERS_GPIO_HIGH 1
5041 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
5042 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24
5043 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
5044 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
5045 #define MISC_REGISTERS_GPIO_INT_SET_POS 16
5046 #define MISC_REGISTERS_GPIO_LOW 0
5047 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5048 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5049 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5050 #define MISC_REGISTERS_GPIO_SET_POS 8
5051 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
5052 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
5053 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
5054 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
5055 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
5056 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
5057 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
5058 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5059 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
5060 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
5061 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
5062 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
5063 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
5064 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
5065 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
5066 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
5067 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
5068 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5069 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5070 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5071 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5072 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5073 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5074 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5075 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5076 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5077 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5078 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
5079 #define MISC_REGISTERS_SPIO_4 4
5080 #define MISC_REGISTERS_SPIO_5 5
5081 #define MISC_REGISTERS_SPIO_7 7
5082 #define MISC_REGISTERS_SPIO_CLR_POS 16
5083 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
5084 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
5085 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5086 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5087 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5088 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5089 #define MISC_REGISTERS_SPIO_SET_POS 8
5090 #define HW_LOCK_MAX_RESOURCE_VALUE 31
5091 #define HW_LOCK_RESOURCE_GPIO 1
5092 #define HW_LOCK_RESOURCE_MDIO 0
5093 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5094 #define HW_LOCK_RESOURCE_RESERVED_08 8
5095 #define HW_LOCK_RESOURCE_SPIO 2
5096 #define HW_LOCK_RESOURCE_UNDI 5
5097 #define PRS_FLAG_OVERETH_IPV4 1
5098 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
5099 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
5100 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
5101 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
5102 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
5103 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
5104 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
5105 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
5106 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
5107 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
5108 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
5109 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
5110 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
5111 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
5112 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
5113 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
5114 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5)
5115 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9)
5116 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
5117 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (1<<28)
5118 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (1<<31)
5119 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (1<<29)
5120 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (1<<30)
5121 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
5122 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
5123 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
5124 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
5125 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
5126 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
5127 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
5128 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
5129 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
5130 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
5131 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
5132 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
5133 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
5134 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
5135 #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
5136 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
5137 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
5138 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
5139 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
5140 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
5141 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
5142 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
5143 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
5144 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
5145 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
5146 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
5147 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
5148 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
5149 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
5150 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
5151 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
5152 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
5153 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
5154 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
5155 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
5157 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
5158 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5160 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
5161 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
5162 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
5163 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
5164 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
5165 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
5166 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
5167 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
5168 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
5169 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
5170 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
5171 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
5172 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
5173 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
5174 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
5175 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
5177 /* storm asserts attention bits */
5178 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5179 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5180 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5181 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5183 /* mcp error attention bit */
5184 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5186 /*E1H NIG status sync attention mapped to group 4-7*/
5187 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5188 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5189 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5190 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5191 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5192 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5193 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5194 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5197 #define LATCHED_ATTN_RBCR 23
5198 #define LATCHED_ATTN_RBCT 24
5199 #define LATCHED_ATTN_RBCN 25
5200 #define LATCHED_ATTN_RBCU 26
5201 #define LATCHED_ATTN_RBCP 27
5202 #define LATCHED_ATTN_TIMEOUT_GRC 28
5203 #define LATCHED_ATTN_RSVD_GRC 29
5204 #define LATCHED_ATTN_ROM_PARITY_MCP 30
5205 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5206 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5207 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5209 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
5210 #define GENERAL_ATTEN_OFFSET(atten_name)\
5211 (1UL << ((94 + atten_name) % 32))
5213 * This file defines GRC base address for every block.
5214 * This file is included by chipsim, asm microcode and cpp microcode.
5215 * These values are used in Design.xml on regBase attribute
5216 * Use the base with the generated offsets of specific registers.
5219 #define GRCBASE_PXPCS 0x000000
5220 #define GRCBASE_PCICONFIG 0x002000
5221 #define GRCBASE_PCIREG 0x002400
5222 #define GRCBASE_EMAC0 0x008000
5223 #define GRCBASE_EMAC1 0x008400
5224 #define GRCBASE_DBU 0x008800
5225 #define GRCBASE_MISC 0x00A000
5226 #define GRCBASE_DBG 0x00C000
5227 #define GRCBASE_NIG 0x010000
5228 #define GRCBASE_XCM 0x020000
5229 #define GRCBASE_PRS 0x040000
5230 #define GRCBASE_SRCH 0x040400
5231 #define GRCBASE_TSDM 0x042000
5232 #define GRCBASE_TCM 0x050000
5233 #define GRCBASE_BRB1 0x060000
5234 #define GRCBASE_MCP 0x080000
5235 #define GRCBASE_UPB 0x0C1000
5236 #define GRCBASE_CSDM 0x0C2000
5237 #define GRCBASE_USDM 0x0C4000
5238 #define GRCBASE_CCM 0x0D0000
5239 #define GRCBASE_UCM 0x0E0000
5240 #define GRCBASE_CDU 0x101000
5241 #define GRCBASE_DMAE 0x102000
5242 #define GRCBASE_PXP 0x103000
5243 #define GRCBASE_CFC 0x104000
5244 #define GRCBASE_HC 0x108000
5245 #define GRCBASE_PXP2 0x120000
5246 #define GRCBASE_PBF 0x140000
5247 #define GRCBASE_XPB 0x161000
5248 #define GRCBASE_TIMERS 0x164000
5249 #define GRCBASE_XSDM 0x166000
5250 #define GRCBASE_QM 0x168000
5251 #define GRCBASE_DQ 0x170000
5252 #define GRCBASE_TSEM 0x180000
5253 #define GRCBASE_CSEM 0x200000
5254 #define GRCBASE_XSEM 0x280000
5255 #define GRCBASE_USEM 0x300000
5256 #define GRCBASE_MISC_AEU GRCBASE_MISC
5259 /* offset of configuration space in the pci core register */
5260 #define PCICFG_OFFSET 0x2000
5261 #define PCICFG_VENDOR_ID_OFFSET 0x00
5262 #define PCICFG_DEVICE_ID_OFFSET 0x02
5263 #define PCICFG_COMMAND_OFFSET 0x04
5264 #define PCICFG_COMMAND_IO_SPACE (1<<0)
5265 #define PCICFG_COMMAND_MEM_SPACE (1<<1)
5266 #define PCICFG_COMMAND_BUS_MASTER (1<<2)
5267 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5268 #define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5269 #define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5270 #define PCICFG_COMMAND_PERR_ENA (1<<6)
5271 #define PCICFG_COMMAND_STEPPING (1<<7)
5272 #define PCICFG_COMMAND_SERR_ENA (1<<8)
5273 #define PCICFG_COMMAND_FAST_B2B (1<<9)
5274 #define PCICFG_COMMAND_INT_DISABLE (1<<10)
5275 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
5276 #define PCICFG_STATUS_OFFSET 0x06
5277 #define PCICFG_REVESION_ID_OFFSET 0x08
5278 #define PCICFG_CACHE_LINE_SIZE 0x0c
5279 #define PCICFG_LATENCY_TIMER 0x0d
5280 #define PCICFG_BAR_1_LOW 0x10
5281 #define PCICFG_BAR_1_HIGH 0x14
5282 #define PCICFG_BAR_2_LOW 0x18
5283 #define PCICFG_BAR_2_HIGH 0x1c
5284 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5285 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5286 #define PCICFG_INT_LINE 0x3c
5287 #define PCICFG_INT_PIN 0x3d
5288 #define PCICFG_PM_CAPABILITY 0x48
5289 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5290 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5291 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5292 #define PCICFG_PM_CAPABILITY_DSI (1<<21)
5293 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5294 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5295 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5296 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5297 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5298 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5299 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5300 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5301 #define PCICFG_PM_CSR_OFFSET 0x4c
5302 #define PCICFG_PM_CSR_STATE (0x3<<0)
5303 #define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5304 #define PCICFG_PM_CSR_PME_STATUS (1<<15)
5305 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
5306 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
5307 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
5308 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
5309 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
5310 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
5311 #define PCICFG_GRC_ADDRESS 0x78
5312 #define PCICFG_GRC_DATA 0x80
5313 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
5314 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
5315 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
5316 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
5317 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
5319 #define PCICFG_DEVICE_CONTROL 0xb4
5320 #define PCICFG_DEVICE_STATUS 0xb6
5321 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
5322 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
5323 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
5324 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
5325 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
5326 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
5327 #define PCICFG_LINK_CONTROL 0xbc
5330 #define BAR_USTRORM_INTMEM 0x400000
5331 #define BAR_CSTRORM_INTMEM 0x410000
5332 #define BAR_XSTRORM_INTMEM 0x420000
5333 #define BAR_TSTRORM_INTMEM 0x430000
5335 /* for accessing the IGU in case of status block ACK */
5336 #define BAR_IGU_INTMEM 0x440000
5338 #define BAR_DOORBELL_OFFSET 0x800000
5340 #define BAR_ME_REGISTER 0x450000
5342 /* config_2 offset */
5343 #define GRC_CONFIG_2_SIZE_REG 0x408
5344 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
5345 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5346 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5347 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
5348 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
5349 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
5350 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
5351 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
5352 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
5353 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
5354 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
5355 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
5356 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
5357 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
5358 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5359 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5360 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5361 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5362 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5363 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5364 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5365 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
5366 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5367 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5368 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
5369 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
5370 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
5371 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
5372 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
5373 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
5374 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
5375 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
5376 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
5377 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
5378 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
5379 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5380 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5381 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5382 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5383 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
5385 /* config_3 offset */
5386 #define GRC_CONFIG_3_SIZE_REG 0x40c
5387 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5388 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
5389 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
5390 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5391 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5392 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5393 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
5395 #define GRC_BAR2_CONFIG 0x4e0
5396 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5397 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5398 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5399 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5400 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5401 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5402 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5403 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5404 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5405 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5406 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5407 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5408 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5409 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5410 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5411 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5412 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5413 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5415 #define PCI_PM_DATA_A 0x410
5416 #define PCI_PM_DATA_B 0x414
5417 #define PCI_ID_VAL1 0x434
5418 #define PCI_ID_VAL2 0x438
5420 #define PXPCS_TL_CONTROL_5 0x814
5421 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/
5422 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/
5423 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/
5424 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/
5425 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/
5426 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/
5427 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/
5428 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/
5429 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/
5430 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/
5431 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/
5432 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/
5433 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/
5434 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/
5435 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/
5436 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/
5437 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/
5438 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/
5439 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/
5440 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/
5441 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/
5442 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/
5443 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/
5444 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/
5445 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/
5446 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/
5447 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
5448 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/
5449 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/
5450 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
5453 #define PXPCS_TL_FUNC345_STAT 0x854
5454 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */
5455 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\
5456 (1 << 28) /* Unsupported Request Error Status in function4, if \
5457 set, generate pcie_err_attn output when this error is seen. WC */
5458 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\
5459 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
5460 generate pcie_err_attn output when this error is seen.. WC */
5461 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\
5462 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
5463 generate pcie_err_attn output when this error is seen.. WC */
5464 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\
5465 (1 << 25) /* Receiver Overflow Status Status in function 4, if \
5466 set, generate pcie_err_attn output when this error is seen.. WC \
5468 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\
5469 (1 << 24) /* Unexpected Completion Status Status in function 4, \
5470 if set, generate pcie_err_attn output when this error is seen. WC \
5472 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\
5473 (1 << 23) /* Receive UR Statusin function 4. If set, generate \
5474 pcie_err_attn output when this error is seen. WC */
5475 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\
5476 (1 << 22) /* Completer Timeout Status Status in function 4, if \
5477 set, generate pcie_err_attn output when this error is seen. WC */
5478 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\
5479 (1 << 21) /* Flow Control Protocol Error Status Status in \
5480 function 4, if set, generate pcie_err_attn output when this error \
5482 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\
5483 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
5484 generate pcie_err_attn output when this error is seen.. WC */
5485 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */
5486 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\
5487 (1 << 18) /* Unsupported Request Error Status in function3, if \
5488 set, generate pcie_err_attn output when this error is seen. WC */
5489 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\
5490 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
5491 generate pcie_err_attn output when this error is seen.. WC */
5492 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\
5493 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
5494 generate pcie_err_attn output when this error is seen.. WC */
5495 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\
5496 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
5497 set, generate pcie_err_attn output when this error is seen.. WC \
5499 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\
5500 (1 << 14) /* Unexpected Completion Status Status in function 3, \
5501 if set, generate pcie_err_attn output when this error is seen. WC \
5503 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\
5504 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
5505 pcie_err_attn output when this error is seen. WC */
5506 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\
5507 (1 << 12) /* Completer Timeout Status Status in function 3, if \
5508 set, generate pcie_err_attn output when this error is seen. WC */
5509 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\
5510 (1 << 11) /* Flow Control Protocol Error Status Status in \
5511 function 3, if set, generate pcie_err_attn output when this error \
5513 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\
5514 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
5515 generate pcie_err_attn output when this error is seen.. WC */
5516 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */
5517 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\
5518 (1 << 8) /* Unsupported Request Error Status for Function 2, if \
5519 set, generate pcie_err_attn output when this error is seen. WC */
5520 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\
5521 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
5522 generate pcie_err_attn output when this error is seen.. WC */
5523 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\
5524 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
5525 generate pcie_err_attn output when this error is seen.. WC */
5526 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\
5527 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
5528 set, generate pcie_err_attn output when this error is seen.. WC \
5530 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\
5531 (1 << 4) /* Unexpected Completion Status Status for Function 2, \
5532 if set, generate pcie_err_attn output when this error is seen. WC \
5534 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\
5535 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
5536 pcie_err_attn output when this error is seen. WC */
5537 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\
5538 (1 << 2) /* Completer Timeout Status Status for Function 2, if \
5539 set, generate pcie_err_attn output when this error is seen. WC */
5540 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\
5541 (1 << 1) /* Flow Control Protocol Error Status Status for \
5542 Function 2, if set, generate pcie_err_attn output when this error \
5544 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\
5545 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
5546 generate pcie_err_attn output when this error is seen.. WC */
5549 #define PXPCS_TL_FUNC678_STAT 0x85C
5550 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */
5551 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\
5552 (1 << 28) /* Unsupported Request Error Status in function7, if \
5553 set, generate pcie_err_attn output when this error is seen. WC */
5554 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\
5555 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
5556 generate pcie_err_attn output when this error is seen.. WC */
5557 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\
5558 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
5559 generate pcie_err_attn output when this error is seen.. WC */
5560 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\
5561 (1 << 25) /* Receiver Overflow Status Status in function 7, if \
5562 set, generate pcie_err_attn output when this error is seen.. WC \
5564 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\
5565 (1 << 24) /* Unexpected Completion Status Status in function 7, \
5566 if set, generate pcie_err_attn output when this error is seen. WC \
5568 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\
5569 (1 << 23) /* Receive UR Statusin function 7. If set, generate \
5570 pcie_err_attn output when this error is seen. WC */
5571 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\
5572 (1 << 22) /* Completer Timeout Status Status in function 7, if \
5573 set, generate pcie_err_attn output when this error is seen. WC */
5574 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\
5575 (1 << 21) /* Flow Control Protocol Error Status Status in \
5576 function 7, if set, generate pcie_err_attn output when this error \
5578 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\
5579 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
5580 generate pcie_err_attn output when this error is seen.. WC */
5581 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */
5582 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\
5583 (1 << 18) /* Unsupported Request Error Status in function6, if \
5584 set, generate pcie_err_attn output when this error is seen. WC */
5585 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\
5586 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
5587 generate pcie_err_attn output when this error is seen.. WC */
5588 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\
5589 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
5590 generate pcie_err_attn output when this error is seen.. WC */
5591 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\
5592 (1 << 15) /* Receiver Overflow Status Status in function 6, if \
5593 set, generate pcie_err_attn output when this error is seen.. WC \
5595 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\
5596 (1 << 14) /* Unexpected Completion Status Status in function 6, \
5597 if set, generate pcie_err_attn output when this error is seen. WC \
5599 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\
5600 (1 << 13) /* Receive UR Statusin function 6. If set, generate \
5601 pcie_err_attn output when this error is seen. WC */
5602 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\
5603 (1 << 12) /* Completer Timeout Status Status in function 6, if \
5604 set, generate pcie_err_attn output when this error is seen. WC */
5605 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\
5606 (1 << 11) /* Flow Control Protocol Error Status Status in \
5607 function 6, if set, generate pcie_err_attn output when this error \
5609 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\
5610 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
5611 generate pcie_err_attn output when this error is seen.. WC */
5612 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */
5613 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\
5614 (1 << 8) /* Unsupported Request Error Status for Function 5, if \
5615 set, generate pcie_err_attn output when this error is seen. WC */
5616 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\
5617 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
5618 generate pcie_err_attn output when this error is seen.. WC */
5619 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\
5620 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
5621 generate pcie_err_attn output when this error is seen.. WC */
5622 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\
5623 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
5624 set, generate pcie_err_attn output when this error is seen.. WC \
5626 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\
5627 (1 << 4) /* Unexpected Completion Status Status for Function 5, \
5628 if set, generate pcie_err_attn output when this error is seen. WC \
5630 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\
5631 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
5632 pcie_err_attn output when this error is seen. WC */
5633 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\
5634 (1 << 2) /* Completer Timeout Status Status for Function 5, if \
5635 set, generate pcie_err_attn output when this error is seen. WC */
5636 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\
5637 (1 << 1) /* Flow Control Protocol Error Status Status for \
5638 Function 5, if set, generate pcie_err_attn output when this error \
5640 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\
5641 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
5642 generate pcie_err_attn output when this error is seen.. WC */
5645 #define BAR_USTRORM_INTMEM 0x400000
5646 #define BAR_CSTRORM_INTMEM 0x410000
5647 #define BAR_XSTRORM_INTMEM 0x420000
5648 #define BAR_TSTRORM_INTMEM 0x430000
5650 /* for accessing the IGU in case of status block ACK */
5651 #define BAR_IGU_INTMEM 0x440000
5653 #define BAR_DOORBELL_OFFSET 0x800000
5655 #define BAR_ME_REGISTER 0x450000
5656 #define ME_REG_PF_NUM_SHIFT 0
5657 #define ME_REG_PF_NUM\
5658 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
5659 #define ME_REG_VF_VALID (1<<8)
5660 #define ME_REG_VF_NUM_SHIFT 9
5661 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
5662 #define ME_REG_VF_ERR (0x1<<3)
5663 #define ME_REG_ABS_PF_NUM_SHIFT 16
5664 #define ME_REG_ABS_PF_NUM\
5665 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
5668 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
5669 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
5670 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
5671 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
5672 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
5674 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
5675 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
5676 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
5677 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
5678 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
5679 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
5680 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
5681 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
5682 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
5683 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
5684 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
5685 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
5686 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
5687 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
5688 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
5689 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
5691 #define MDIO_REG_BANK_RX0 0x80b0
5692 #define MDIO_RX0_RX_STATUS 0x10
5693 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
5694 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
5695 #define MDIO_RX0_RX_EQ_BOOST 0x1c
5696 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5697 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
5699 #define MDIO_REG_BANK_RX1 0x80c0
5700 #define MDIO_RX1_RX_EQ_BOOST 0x1c
5701 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5702 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
5704 #define MDIO_REG_BANK_RX2 0x80d0
5705 #define MDIO_RX2_RX_EQ_BOOST 0x1c
5706 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5707 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
5709 #define MDIO_REG_BANK_RX3 0x80e0
5710 #define MDIO_RX3_RX_EQ_BOOST 0x1c
5711 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5712 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
5714 #define MDIO_REG_BANK_RX_ALL 0x80f0
5715 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
5716 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5717 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
5719 #define MDIO_REG_BANK_TX0 0x8060
5720 #define MDIO_TX0_TX_DRIVER 0x17
5721 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5722 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5723 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5724 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5725 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5726 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5727 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5728 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5729 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5731 #define MDIO_REG_BANK_TX1 0x8070
5732 #define MDIO_TX1_TX_DRIVER 0x17
5733 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5734 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5735 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5736 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5737 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5738 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5739 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5740 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5741 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5743 #define MDIO_REG_BANK_TX2 0x8080
5744 #define MDIO_TX2_TX_DRIVER 0x17
5745 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5746 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5747 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5748 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5749 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5750 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5751 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5752 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5753 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5755 #define MDIO_REG_BANK_TX3 0x8090
5756 #define MDIO_TX3_TX_DRIVER 0x17
5757 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5758 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5759 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5760 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5761 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5762 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5763 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5764 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5765 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5767 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
5768 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
5770 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
5771 #define MDIO_BLOCK1_LANE_CTRL0 0x15
5772 #define MDIO_BLOCK1_LANE_CTRL1 0x16
5773 #define MDIO_BLOCK1_LANE_CTRL2 0x17
5774 #define MDIO_BLOCK1_LANE_PRBS 0x19
5776 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
5777 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
5778 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
5779 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
5780 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
5781 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
5782 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
5783 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
5784 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
5785 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
5787 #define MDIO_REG_BANK_GP_STATUS 0x8120
5788 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
5789 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
5790 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
5791 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
5792 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
5793 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
5794 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
5795 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
5796 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
5797 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
5798 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
5799 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
5800 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
5801 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
5802 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
5803 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
5804 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
5805 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
5806 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
5807 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
5808 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
5809 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
5810 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
5811 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
5812 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
5815 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
5816 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
5817 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
5818 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
5819 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
5820 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
5821 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
5823 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
5824 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
5825 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
5826 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
5827 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
5828 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
5829 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
5830 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
5831 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
5832 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
5833 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
5834 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
5835 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
5836 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
5837 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
5838 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
5839 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
5840 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
5841 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
5842 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
5843 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
5844 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
5845 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
5846 #define MDIO_SERDES_DIGITAL_MISC1 0x18
5847 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
5848 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
5849 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
5850 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
5851 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
5852 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
5853 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
5854 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
5855 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
5856 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
5857 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
5858 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
5859 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
5860 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
5861 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
5862 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
5863 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
5864 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
5866 #define MDIO_REG_BANK_OVER_1G 0x8320
5867 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
5868 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
5869 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
5870 #define MDIO_OVER_1G_UP1 0x19
5871 #define MDIO_OVER_1G_UP1_2_5G 0x0001
5872 #define MDIO_OVER_1G_UP1_5G 0x0002
5873 #define MDIO_OVER_1G_UP1_6G 0x0004
5874 #define MDIO_OVER_1G_UP1_10G 0x0010
5875 #define MDIO_OVER_1G_UP1_10GH 0x0008
5876 #define MDIO_OVER_1G_UP1_12G 0x0020
5877 #define MDIO_OVER_1G_UP1_12_5G 0x0040
5878 #define MDIO_OVER_1G_UP1_13G 0x0080
5879 #define MDIO_OVER_1G_UP1_15G 0x0100
5880 #define MDIO_OVER_1G_UP1_16G 0x0200
5881 #define MDIO_OVER_1G_UP2 0x1A
5882 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
5883 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
5884 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
5885 #define MDIO_OVER_1G_UP3 0x1B
5886 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
5887 #define MDIO_OVER_1G_LP_UP1 0x1C
5888 #define MDIO_OVER_1G_LP_UP2 0x1D
5889 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
5890 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
5891 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
5892 #define MDIO_OVER_1G_LP_UP3 0x1E
5894 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
5895 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
5896 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
5897 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
5899 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
5900 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
5901 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
5902 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
5904 #define MDIO_REG_BANK_CL73_USERB0 0x8370
5905 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
5906 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
5907 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
5908 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
5909 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
5910 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
5911 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
5912 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
5913 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
5914 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
5915 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
5917 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
5918 #define MDIO_AER_BLOCK_AER_REG 0x1E
5920 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
5921 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
5922 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
5923 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
5924 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
5925 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
5926 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
5927 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
5928 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
5929 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
5930 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
5931 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
5932 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
5933 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
5934 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
5935 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
5936 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
5937 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
5938 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
5939 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
5940 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
5941 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
5942 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
5943 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
5944 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
5945 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
5946 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
5947 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
5948 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
5949 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
5950 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
5951 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
5952 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
5953 Theotherbitsarereservedandshouldbezero*/
5954 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
5957 #define MDIO_PMA_DEVAD 0x1
5959 #define MDIO_PMA_REG_CTRL 0x0
5960 #define MDIO_PMA_REG_STATUS 0x1
5961 #define MDIO_PMA_REG_10G_CTRL2 0x7
5962 #define MDIO_PMA_REG_RX_SD 0xa
5964 #define MDIO_PMA_REG_BCM_CTRL 0x0096
5965 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
5966 #define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
5967 #define MDIO_PMA_REG_LASI_CTRL 0x9002
5968 #define MDIO_PMA_REG_RX_ALARM 0x9003
5969 #define MDIO_PMA_REG_TX_ALARM 0x9004
5970 #define MDIO_PMA_REG_LASI_STATUS 0x9005
5971 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
5972 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
5973 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
5974 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
5975 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
5976 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
5977 #define MDIO_PMA_REG_GEN_CTRL 0xca10
5978 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
5979 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
5980 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
5981 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
5982 #define MDIO_PMA_REG_ROM_VER1 0xca19
5983 #define MDIO_PMA_REG_ROM_VER2 0xca1a
5984 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
5985 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
5986 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
5987 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
5988 #define MDIO_PMA_REG_LRM_MODE 0xca3f
5989 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
5990 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
5992 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
5993 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
5994 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
5995 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
5996 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
5997 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
5998 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
5999 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
6000 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
6001 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
6002 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
6003 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
6005 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
6006 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
6007 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
6008 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
6009 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
6010 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
6011 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
6012 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
6014 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
6016 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
6017 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
6018 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
6019 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
6021 #define MDIO_PMA_REG_7101_RESET 0xc000
6022 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
6023 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
6024 #define MDIO_PMA_REG_7101_VER1 0xc026
6025 #define MDIO_PMA_REG_7101_VER2 0xc027
6027 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
6028 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
6029 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
6030 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
6031 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
6032 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
6033 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
6034 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
6035 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
6036 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
6039 #define MDIO_WIS_DEVAD 0x2
6041 #define MDIO_WIS_REG_LASI_CNTL 0x9002
6042 #define MDIO_WIS_REG_LASI_STATUS 0x9005
6044 #define MDIO_PCS_DEVAD 0x3
6045 #define MDIO_PCS_REG_STATUS 0x0020
6046 #define MDIO_PCS_REG_LASI_STATUS 0x9005
6047 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
6048 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
6049 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
6050 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
6051 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
6052 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
6053 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
6054 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
6055 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
6058 #define MDIO_XS_DEVAD 0x4
6059 #define MDIO_XS_PLL_SEQUENCER 0x8000
6060 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
6062 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
6063 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
6064 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
6065 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
6066 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
6068 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
6070 #define MDIO_AN_DEVAD 0x7
6072 #define MDIO_AN_REG_CTRL 0x0000
6073 #define MDIO_AN_REG_STATUS 0x0001
6074 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
6075 #define MDIO_AN_REG_ADV_PAUSE 0x0010
6076 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
6077 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
6078 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
6079 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
6080 #define MDIO_AN_REG_ADV 0x0011
6081 #define MDIO_AN_REG_ADV2 0x0012
6082 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
6083 #define MDIO_AN_REG_MASTER_STATUS 0x0021
6085 #define MDIO_AN_REG_LINK_STATUS 0x8304
6086 #define MDIO_AN_REG_CL37_CL73 0x8370
6087 #define MDIO_AN_REG_CL37_AN 0xffe0
6088 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
6089 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
6091 #define MDIO_AN_REG_8073_2_5G 0x8329
6092 #define MDIO_AN_REG_8073_BAM 0x8350
6094 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
6095 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
6096 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
6097 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
6098 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
6099 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
6100 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
6101 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
6102 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
6103 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
6106 #define MDIO_CTL_DEVAD 0x1e
6107 #define MDIO_CTL_REG_84823_MEDIA 0x401a
6108 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
6109 /* These pins configure the BCM84823 interface to MAC after reset. */
6110 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
6111 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
6112 /* These pins configure the BCM84823 interface to Line after reset. */
6113 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
6114 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
6115 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
6116 /* When this pin is active high during reset, 10GBASE-T core is power
6117 * down, When it is active low the 10GBASE-T is power up
6119 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
6120 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
6121 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
6122 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
6123 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
6126 #define IGU_FUNC_BASE 0x0400
6128 #define IGU_ADDR_MSIX 0x0000
6129 #define IGU_ADDR_INT_ACK 0x0200
6130 #define IGU_ADDR_PROD_UPD 0x0201
6131 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
6132 #define IGU_ADDR_ATTN_BITS_SET 0x0203
6133 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
6134 #define IGU_ADDR_COALESCE_NOW 0x0205
6135 #define IGU_ADDR_SIMD_MASK 0x0206
6136 #define IGU_ADDR_SIMD_NOMASK 0x0207
6137 #define IGU_ADDR_MSI_CTL 0x0210
6138 #define IGU_ADDR_MSI_ADDR_LO 0x0211
6139 #define IGU_ADDR_MSI_ADDR_HI 0x0212
6140 #define IGU_ADDR_MSI_DATA 0x0213
6142 #define IGU_INT_ENABLE 0
6143 #define IGU_INT_DISABLE 1
6144 #define IGU_INT_NOP 2
6145 #define IGU_INT_NOP2 3
6147 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
6148 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
6149 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
6150 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
6152 #define COMMAND_REG_INT_ACK 0x0
6153 #define COMMAND_REG_PROD_UPD 0x4
6154 #define COMMAND_REG_ATTN_BITS_UPD 0x8
6155 #define COMMAND_REG_ATTN_BITS_SET 0xc
6156 #define COMMAND_REG_ATTN_BITS_CLR 0x10
6157 #define COMMAND_REG_COALESCE_NOW 0x14
6158 #define COMMAND_REG_SIMD_MASK 0x18
6159 #define COMMAND_REG_SIMD_NOMASK 0x1c
6162 #define IGU_MEM_BASE 0x0000
6164 #define IGU_MEM_MSIX_BASE 0x0000
6165 #define IGU_MEM_MSIX_UPPER 0x007f
6166 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
6168 #define IGU_MEM_PBA_MSIX_BASE 0x0200
6169 #define IGU_MEM_PBA_MSIX_UPPER 0x0200
6171 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
6172 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
6174 #define IGU_CMD_INT_ACK_BASE 0x0400
6175 #define IGU_CMD_INT_ACK_UPPER\
6176 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
6177 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
6179 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500
6180 #define IGU_CMD_E2_PROD_UPD_UPPER\
6181 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
6182 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
6184 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
6185 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
6186 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
6188 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
6189 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
6190 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
6191 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
6193 #define IGU_REG_RESERVED_UPPER 0x05ff
6194 /* Fields of IGU PF CONFIGRATION REGISTER */
6195 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
6196 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
6197 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
6198 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
6199 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
6200 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
6202 /* Fields of IGU VF CONFIGRATION REGISTER */
6203 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
6204 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
6205 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
6206 #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
6207 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
6210 #define IGU_BC_DSB_NUM_SEGS 5
6211 #define IGU_BC_NDSB_NUM_SEGS 2
6212 #define IGU_NORM_DSB_NUM_SEGS 2
6213 #define IGU_NORM_NDSB_NUM_SEGS 1
6214 #define IGU_BC_BASE_DSB_PROD 128
6215 #define IGU_NORM_BASE_DSB_PROD 136
6217 #define IGU_CTRL_CMD_TYPE_WR\
6219 #define IGU_CTRL_CMD_TYPE_RD\
6222 #define IGU_SEG_ACCESS_NORM 0
6223 #define IGU_SEG_ACCESS_DEF 1
6224 #define IGU_SEG_ACCESS_ATTN 2
6226 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
6227 [5:2] = 0; [1:0] = PF number) */
6228 #define IGU_FID_ENCODE_IS_PF (0x1<<6)
6229 #define IGU_FID_ENCODE_IS_PF_SHIFT 6
6230 #define IGU_FID_VF_NUM_MASK (0x3f)
6231 #define IGU_FID_PF_NUM_MASK (0x7)
6233 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
6234 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
6235 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
6236 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
6237 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7
6240 #define CDU_REGION_NUMBER_XCM_AG 2
6241 #define CDU_REGION_NUMBER_UCM_AG 4
6245 * String-to-compress [31:8] = CID (all 24 bits)
6246 * String-to-compress [7:4] = Region
6247 * String-to-compress [3:0] = Type
6249 #define CDU_VALID_DATA(_cid, _region, _type)\
6250 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
6251 #define CDU_CRC8(_cid, _region, _type)\
6252 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
6253 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
6254 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
6255 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
6256 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
6257 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
6259 /******************************************************************************
6261 * Calculates crc 8 on a word value: polynomial 0-1-2-8
6262 * Code was translated from Verilog.
6264 *****************************************************************************/
6265 static inline u8 calc_crc8(u32 data, u8 crc)
6273 /* split the data into 31 bits */
6274 for (i = 0; i < 32; i++) {
6275 D[i] = (u8)(data & 1);
6279 /* split the crc into 8 bits */
6280 for (i = 0; i < 8; i++) {
6285 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
6286 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
6288 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
6289 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
6290 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
6292 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
6293 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
6294 C[0] ^ C[1] ^ C[4] ^ C[5];
6295 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
6296 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
6297 C[1] ^ C[2] ^ C[5] ^ C[6];
6298 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
6299 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
6300 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
6301 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
6302 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
6304 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
6305 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
6307 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
6308 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
6312 for (i = 0; i < 8; i++)
6313 crc_res |= (NewCRC[i] << i);
git.openpandora.org / pandora-kernel.git / blob