drivers/net/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2011 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30
  31 /********************************************************/
  32 #define ETH_HLEN                        14
  33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  34 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  35 #define ETH_MIN_PACKET_SIZE             60
  36 #define ETH_MAX_PACKET_SIZE             1500
  37 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  38 #define MDIO_ACCESS_TIMEOUT             1000
  39 #define BMAC_CONTROL_RX_ENABLE          2
  40 #define WC_LANE_MAX                     4
  41 #define I2C_SWITCH_WIDTH                2
  42 #define I2C_BSC0                        0
  43 #define I2C_BSC1                        1
  44 #define I2C_WA_RETRY_CNT                3
  45 #define MCPR_IMC_COMMAND_READ_OP        1
  46 #define MCPR_IMC_COMMAND_WRITE_OP       2
  47
  48 /***********************************************************/
  49 /*                      Shortcut definitions               */
  50 /***********************************************************/
  51
  52 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  53
  54 #define NIG_STATUS_EMAC0_MI_INT \
  55                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  56 #define NIG_STATUS_XGXS0_LINK10G \
  57                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  58 #define NIG_STATUS_XGXS0_LINK_STATUS \
  59                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  60 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  62 #define NIG_STATUS_SERDES0_LINK_STATUS \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  64 #define NIG_MASK_MI_INT \
  65                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  66 #define NIG_MASK_XGXS0_LINK10G \
  67                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  68 #define NIG_MASK_XGXS0_LINK_STATUS \
  69                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  70 #define NIG_MASK_SERDES0_LINK_STATUS \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  72
  73 #define MDIO_AN_CL73_OR_37_COMPLETE \
  74                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  75                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  76
  77 #define XGXS_RESET_BITS \
  78         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  79          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  80          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  83
  84 #define SERDES_RESET_BITS \
  85         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  89
  90 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  91 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  92 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  93 #define AUTONEG_PARALLEL \
  94                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  95 #define AUTONEG_SGMII_FIBER_AUTODET \
  96                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  97 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  98
  99 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 100                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 101 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 102                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 103 #define GP_STATUS_SPEED_MASK \
 104                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 105 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 106 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 107 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 108 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 109 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 110 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 111 #define GP_STATUS_10G_HIG \
 112                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 113 #define GP_STATUS_10G_CX4 \
 114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 115 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 116 #define GP_STATUS_10G_KX4 \
 117                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 118 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 119 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 120 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 121 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 122 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 123 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 124 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 125 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 126 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 127 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 128 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 129 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 130 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 131 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 132 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 133 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 134 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 135 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 136 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 137
 138
 139
 140 /* */
 141 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 142         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 143         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 144
 145
 146 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 147         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 148         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 149         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 150
 151 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 152         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 153         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 154
 155 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 156         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 157 #define SFP_EEPROM_OPTIONS_SIZE                 2
 158
 159 #define EDC_MODE_LINEAR                         0x0022
 160 #define EDC_MODE_LIMITING                               0x0044
 161 #define EDC_MODE_PASSIVE_DAC                    0x0055
 162
 163
 164 /* BRB thresholds for E2*/
 165 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE             170
 166 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE         0
 167
 168 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE              250
 169 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE          0
 170
 171 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE              10
 172 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE          90
 173
 174 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                       50
 175 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE           250
 176
 177 /* BRB thresholds for E3A0 */
 178 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE           290
 179 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE               0
 180
 181 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE            410
 182 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE                0
 183
 184 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE            10
 185 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE                170
 186
 187 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE             50
 188 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE         410
 189
 190
 191 /* BRB thresholds for E3B0 2 port mode*/
 192 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                1025
 193 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 194
 195 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE         1025
 196 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 197
 198 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 199 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     1025
 200
 201 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE          50
 202 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE      1025
 203
 204 /* only for E3B0*/
 205 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                        1025
 206 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                 1025
 207
 208 /* Lossy +Lossless GUARANTIED == GUART */
 209 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                  284
 210 /* Lossless +Lossless*/
 211 #define PFC_E3B0_2P_PAUSE_LB_GUART                      236
 212 /* Lossy +Lossy*/
 213 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART                  342
 214
 215 /* Lossy +Lossless*/
 216 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART               284
 217 /* Lossless +Lossless*/
 218 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART           236
 219 /* Lossy +Lossy*/
 220 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART               336
 221 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 222
 223 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART             0
 224 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST                0
 225
 226 /* BRB thresholds for E3B0 4 port mode */
 227 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                304
 228 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 229
 230 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE         384
 231 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 232
 233 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 234 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     304
 235
 236 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE          50
 237 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE      384
 238
 239
 240 /* only for E3B0*/
 241 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                        304
 242 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                 384
 243 #define PFC_E3B0_4P_LB_GUART                            120
 244
 245 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART             120
 246 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 247
 248 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART             80
 249 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST                120
 250
 251 #define DCBX_INVALID_COS                                        (0xFF)
 252
 253 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 254 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 255 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 256 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 257 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 258
 259 #define MAX_PACKET_SIZE                                 (9700)
 260 #define WC_UC_TIMEOUT                                   100
 261
 262 /**********************************************************/
 263 /*                     INTERFACE                          */
 264 /**********************************************************/
 265
 266 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 267         bnx2x_cl45_write(_bp, _phy, \
 268                 (_phy)->def_md_devad, \
 269                 (_bank + (_addr & 0xf)), \
 270                 _val)
 271
 272 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 273         bnx2x_cl45_read(_bp, _phy, \
 274                 (_phy)->def_md_devad, \
 275                 (_bank + (_addr & 0xf)), \
 276                 _val)
 277
 278 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 279 {
 280         u32 val = REG_RD(bp, reg);
 281
 282         val |= bits;
 283         REG_WR(bp, reg, val);
 284         return val;
 285 }
 286
 287 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 288 {
 289         u32 val = REG_RD(bp, reg);
 290
 291         val &= ~bits;
 292         REG_WR(bp, reg, val);
 293         return val;
 294 }
 295
 296 /******************************************************************/
 297 /*                      EPIO/GPIO section                         */
 298 /******************************************************************/
 299 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 300 {
 301         u32 epio_mask, gp_oenable;
 302         *en = 0;
 303         /* Sanity check */
 304         if (epio_pin > 31) {
 305                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 306                 return;
 307         }
 308
 309         epio_mask = 1 << epio_pin;
 310         /* Set this EPIO to output */
 311         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 312         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 313
 314         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 315 }
 316 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 317 {
 318         u32 epio_mask, gp_output, gp_oenable;
 319
 320         /* Sanity check */
 321         if (epio_pin > 31) {
 322                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 323                 return;
 324         }
 325         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 326         epio_mask = 1 << epio_pin;
 327         /* Set this EPIO to output */
 328         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 329         if (en)
 330                 gp_output |= epio_mask;
 331         else
 332                 gp_output &= ~epio_mask;
 333
 334         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 335
 336         /* Set the value for this EPIO */
 337         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 338         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 339 }
 340
 341 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 342 {
 343         if (pin_cfg == PIN_CFG_NA)
 344                 return;
 345         if (pin_cfg >= PIN_CFG_EPIO0) {
 346                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 347         } else {
 348                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 349                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 350                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 351         }
 352 }
 353
 354 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 355 {
 356         if (pin_cfg == PIN_CFG_NA)
 357                 return -EINVAL;
 358         if (pin_cfg >= PIN_CFG_EPIO0) {
 359                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 360         } else {
 361                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 362                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 363                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 364         }
 365         return 0;
 366
 367 }
 368 /******************************************************************/
 369 /*                              ETS section                       */
 370 /******************************************************************/
 371 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 372 {
 373         /* ETS disabled configuration*/
 374         struct bnx2x *bp = params->bp;
 375
 376         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 377
 378         /*
 379          * mapping between entry  priority to client number (0,1,2 -debug and
 380          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 381          * 3bits client num.
 382          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 383          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 384          */
 385
 386         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 387         /*
 388          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 389          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 390          * COS0 entry, 4 - COS1 entry.
 391          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 392          * bit4   bit3    bit2   bit1     bit0
 393          * MCP and debug are strict
 394          */
 395
 396         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 397         /* defines which entries (clients) are subjected to WFQ arbitration */
 398         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 399         /*
 400          * For strict priority entries defines the number of consecutive
 401          * slots for the highest priority.
 402          */
 403         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 404         /*
 405          * mapping between the CREDIT_WEIGHT registers and actual client
 406          * numbers
 407          */
 408         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 409         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 410         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 411
 412         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 413         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 414         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 415         /* ETS mode disable */
 416         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 417         /*
 418          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 419          * weight for COS0/COS1.
 420          */
 421         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 422         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 423         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 424         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 425         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 426         /* Defines the number of consecutive slots for the strict priority */
 427         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 428 }
 429 /******************************************************************************
 430 * Description:
 431 *       Getting min_w_val will be set according to line speed .
 432 *.
 433 ******************************************************************************/
 434 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 435 {
 436         u32 min_w_val = 0;
 437         /* Calculate min_w_val.*/
 438         if (vars->link_up) {
 439                 if (SPEED_20000 == vars->line_speed)
 440                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 441                 else
 442                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 443         } else
 444                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 445         /**
 446          *  If the link isn't up (static configuration for example ) The
 447          *  link will be according to 20GBPS.
 448         */
 449         return min_w_val;
 450 }
 451 /******************************************************************************
 452 * Description:
 453 *       Getting credit upper bound form min_w_val.
 454 *.
 455 ******************************************************************************/
 456 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 457 {
 458         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 459                                                 MAX_PACKET_SIZE);
 460         return credit_upper_bound;
 461 }
 462 /******************************************************************************
 463 * Description:
 464 *       Set credit upper bound for NIG.
 465 *.
 466 ******************************************************************************/
 467 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 468         const struct link_params *params,
 469         const u32 min_w_val)
 470 {
 471         struct bnx2x *bp = params->bp;
 472         const u8 port = params->port;
 473         const u32 credit_upper_bound =
 474             bnx2x_ets_get_credit_upper_bound(min_w_val);
 475
 476         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 477                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 478         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 479                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 480         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 481                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 482         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 483                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 484         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 485                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 486         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 487                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 488
 489         if (0 == port) {
 490                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 491                         credit_upper_bound);
 492                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 493                         credit_upper_bound);
 494                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 495                         credit_upper_bound);
 496         }
 497 }
 498 /******************************************************************************
 499 * Description:
 500 *       Will return the NIG ETS registers to init values.Except
 501 *       credit_upper_bound.
 502 *       That isn't used in this configuration (No WFQ is enabled) and will be
 503 *       configured acording to spec
 504 *.
 505 ******************************************************************************/
 506 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 507                                         const struct link_vars *vars)
 508 {
 509         struct bnx2x *bp = params->bp;
 510         const u8 port = params->port;
 511         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 512         /**
 513          * mapping between entry  priority to client number (0,1,2 -debug and
 514          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 515          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 516          * reset value or init tool
 517          */
 518         if (port) {
 519                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 520                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 521         } else {
 522                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 523                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 524         }
 525         /**
 526         * For strict priority entries defines the number of consecutive
 527         * slots for the highest priority.
 528         */
 529         /* TODO_ETS - Should be done by reset value or init tool */
 530         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 531                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 532         /**
 533          * mapping between the CREDIT_WEIGHT registers and actual client
 534          * numbers
 535          */
 536         /* TODO_ETS - Should be done by reset value or init tool */
 537         if (port) {
 538                 /*Port 1 has 6 COS*/
 539                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 540                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 541         } else {
 542                 /*Port 0 has 9 COS*/
 543                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 544                        0x43210876);
 545                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 546         }
 547
 548         /**
 549          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 550          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 551          * COS0 entry, 4 - COS1 entry.
 552          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 553          * bit4   bit3    bit2   bit1     bit0
 554          * MCP and debug are strict
 555          */
 556         if (port)
 557                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 558         else
 559                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 560         /* defines which entries (clients) are subjected to WFQ arbitration */
 561         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 562                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 563
 564         /**
 565         * Please notice the register address are note continuous and a
 566         * for here is note appropriate.In 2 port mode port0 only COS0-5
 567         * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 568         * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 569         * are never used for WFQ
 570         */
 571         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 572                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 573         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 574                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 575         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 576                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 578                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 579         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 580                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 581         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 582                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 583         if (0 == port) {
 584                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 585                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 586                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 587         }
 588
 589         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 590 }
 591 /******************************************************************************
 592 * Description:
 593 *       Set credit upper bound for PBF.
 594 *.
 595 ******************************************************************************/
 596 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 597         const struct link_params *params,
 598         const u32 min_w_val)
 599 {
 600         struct bnx2x *bp = params->bp;
 601         const u32 credit_upper_bound =
 602             bnx2x_ets_get_credit_upper_bound(min_w_val);
 603         const u8 port = params->port;
 604         u32 base_upper_bound = 0;
 605         u8 max_cos = 0;
 606         u8 i = 0;
 607         /**
 608         * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 609         * port mode port1 has COS0-2 that can be used for WFQ.
 610         */
 611         if (0 == port) {
 612                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 613                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 614         } else {
 615                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 616                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 617         }
 618
 619         for (i = 0; i < max_cos; i++)
 620                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 621 }
 622
 623 /******************************************************************************
 624 * Description:
 625 *       Will return the PBF ETS registers to init values.Except
 626 *       credit_upper_bound.
 627 *       That isn't used in this configuration (No WFQ is enabled) and will be
 628 *       configured acording to spec
 629 *.
 630 ******************************************************************************/
 631 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 632 {
 633         struct bnx2x *bp = params->bp;
 634         const u8 port = params->port;
 635         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 636         u8 i = 0;
 637         u32 base_weight = 0;
 638         u8 max_cos = 0;
 639
 640         /**
 641          * mapping between entry  priority to client number 0 - COS0
 642          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 643          * TODO_ETS - Should be done by reset value or init tool
 644          */
 645         if (port)
 646                 /*  0x688 (|011|0 10|00 1|000) */
 647                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 648         else
 649                 /*  (10 1|100 |011|0 10|00 1|000) */
 650                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 651
 652         /* TODO_ETS - Should be done by reset value or init tool */
 653         if (port)
 654                 /* 0x688 (|011|0 10|00 1|000)*/
 655                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 656         else
 657         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 658         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 659
 660         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 661                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 662
 663
 664         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 665                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 666
 667         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 668                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 669         /**
 670         * In 2 port mode port0 has COS0-5 that can be used for WFQ.
 671         * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 672         */
 673         if (0 == port) {
 674                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 675                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 676         } else {
 677                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 678                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 679         }
 680
 681         for (i = 0; i < max_cos; i++)
 682                 REG_WR(bp, base_weight + (0x4 * i), 0);
 683
 684         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 685 }
 686 /******************************************************************************
 687 * Description:
 688 *       E3B0 disable will return basicly the values to init values.
 689 *.
 690 ******************************************************************************/
 691 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 692                                    const struct link_vars *vars)
 693 {
 694         struct bnx2x *bp = params->bp;
 695
 696         if (!CHIP_IS_E3B0(bp)) {
 697                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
 698                                    "\n");
 699                 return -EINVAL;
 700         }
 701
 702         bnx2x_ets_e3b0_nig_disabled(params, vars);
 703
 704         bnx2x_ets_e3b0_pbf_disabled(params);
 705
 706         return 0;
 707 }
 708
 709 /******************************************************************************
 710 * Description:
 711 *       Disable will return basicly the values to init values.
 712 *.
 713 ******************************************************************************/
 714 int bnx2x_ets_disabled(struct link_params *params,
 715                       struct link_vars *vars)
 716 {
 717         struct bnx2x *bp = params->bp;
 718         int bnx2x_status = 0;
 719
 720         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 721                 bnx2x_ets_e2e3a0_disabled(params);
 722         else if (CHIP_IS_E3B0(bp))
 723                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 724         else {
 725                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 726                 return -EINVAL;
 727         }
 728
 729         return bnx2x_status;
 730 }
 731
 732 /******************************************************************************
 733 * Description
 734 *       Set the COS mappimg to SP and BW until this point all the COS are not
 735 *       set as SP or BW.
 736 ******************************************************************************/
 737 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 738                                   const struct bnx2x_ets_params *ets_params,
 739                                   const u8 cos_sp_bitmap,
 740                                   const u8 cos_bw_bitmap)
 741 {
 742         struct bnx2x *bp = params->bp;
 743         const u8 port = params->port;
 744         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 745         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 746         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 747         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 748
 749         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 750                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 751
 752         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 753                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 754
 755         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 756                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 757                nig_cli_subject2wfq_bitmap);
 758
 759         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 760                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 761                pbf_cli_subject2wfq_bitmap);
 762
 763         return 0;
 764 }
 765
 766 /******************************************************************************
 767 * Description:
 768 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 769 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 770 ******************************************************************************/
 771 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 772                                      const u8 cos_entry,
 773                                      const u32 min_w_val_nig,
 774                                      const u32 min_w_val_pbf,
 775                                      const u16 total_bw,
 776                                      const u8 bw,
 777                                      const u8 port)
 778 {
 779         u32 nig_reg_adress_crd_weight = 0;
 780         u32 pbf_reg_adress_crd_weight = 0;
 781         /* Calculate and set BW for this COS*/
 782         const u32 cos_bw_nig = (bw * min_w_val_nig) / total_bw;
 783         const u32 cos_bw_pbf = (bw * min_w_val_pbf) / total_bw;
 784
 785         switch (cos_entry) {
 786         case 0:
 787             nig_reg_adress_crd_weight =
 788                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 789                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 790              pbf_reg_adress_crd_weight = (port) ?
 791                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 792              break;
 793         case 1:
 794              nig_reg_adress_crd_weight = (port) ?
 795                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 796                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 797              pbf_reg_adress_crd_weight = (port) ?
 798                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 799              break;
 800         case 2:
 801              nig_reg_adress_crd_weight = (port) ?
 802                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 803                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 804
 805                  pbf_reg_adress_crd_weight = (port) ?
 806                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 807              break;
 808         case 3:
 809             if (port)
 810                         return -EINVAL;
 811              nig_reg_adress_crd_weight =
 812                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 813              pbf_reg_adress_crd_weight =
 814                  PBF_REG_COS3_WEIGHT_P0;
 815              break;
 816         case 4:
 817             if (port)
 818                 return -EINVAL;
 819              nig_reg_adress_crd_weight =
 820                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 821              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 822              break;
 823         case 5:
 824             if (port)
 825                 return -EINVAL;
 826              nig_reg_adress_crd_weight =
 827                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 828              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 829              break;
 830         }
 831
 832         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 833
 834         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 835
 836         return 0;
 837 }
 838 /******************************************************************************
 839 * Description:
 840 *       Calculate the total BW.A value of 0 isn't legal.
 841 *.
 842 ******************************************************************************/
 843 static int bnx2x_ets_e3b0_get_total_bw(
 844         const struct link_params *params,
 845         const struct bnx2x_ets_params *ets_params,
 846         u16 *total_bw)
 847 {
 848         struct bnx2x *bp = params->bp;
 849         u8 cos_idx = 0;
 850
 851         *total_bw = 0 ;
 852         /* Calculate total BW requested */
 853         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 854                 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
 855
 856                         if (0 == ets_params->cos[cos_idx].params.bw_params.bw) {
 857                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 858                                                    "was set to 0\n");
 859                         return -EINVAL;
 860                 }
 861                 *total_bw +=
 862                     ets_params->cos[cos_idx].params.bw_params.bw;
 863             }
 864         }
 865
 866         /*Check taotl BW is valid */
 867         if ((100 != *total_bw) || (0 == *total_bw)) {
 868                 if (0 == *total_bw) {
 869                         DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW"
 870                                            "shouldn't be 0\n");
 871                         return -EINVAL;
 872                 }
 873                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW should be"
 874                                    "100\n");
 875                 /**
 876                 *   We can handle a case whre the BW isn't 100 this can happen
 877                 *   if the TC are joined.
 878                 */
 879         }
 880         return 0;
 881 }
 882
 883 /******************************************************************************
 884 * Description:
 885 *       Invalidate all the sp_pri_to_cos.
 886 *.
 887 ******************************************************************************/
 888 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 889 {
 890         u8 pri = 0;
 891         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 892                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 893 }
 894 /******************************************************************************
 895 * Description:
 896 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 897 *       according to sp_pri_to_cos.
 898 *.
 899 ******************************************************************************/
 900 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 901                                             u8 *sp_pri_to_cos, const u8 pri,
 902                                             const u8 cos_entry)
 903 {
 904         struct bnx2x *bp = params->bp;
 905         const u8 port = params->port;
 906         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 907                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 908
 909         if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
 910                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 911                                    "parameter There can't be two COS's with"
 912                                    "the same strict pri\n");
 913                 return -EINVAL;
 914         }
 915
 916         if (pri > max_num_of_cos) {
 917                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid"
 918                                "parameter Illegal strict priority\n");
 919             return -EINVAL;
 920         }
 921
 922         sp_pri_to_cos[pri] = cos_entry;
 923         return 0;
 924
 925 }
 926
 927 /******************************************************************************
 928 * Description:
 929 *       Returns the correct value according to COS and priority in
 930 *       the sp_pri_cli register.
 931 *.
 932 ******************************************************************************/
 933 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 934                                          const u8 pri_set,
 935                                          const u8 pri_offset,
 936                                          const u8 entry_size)
 937 {
 938         u64 pri_cli_nig = 0;
 939         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 940                                                     (pri_set + pri_offset));
 941
 942         return pri_cli_nig;
 943 }
 944 /******************************************************************************
 945 * Description:
 946 *       Returns the correct value according to COS and priority in the
 947 *       sp_pri_cli register for NIG.
 948 *.
 949 ******************************************************************************/
 950 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 951 {
 952         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 953         const u8 nig_cos_offset = 3;
 954         const u8 nig_pri_offset = 3;
 955
 956         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
 957                 nig_pri_offset, 4);
 958
 959 }
 960 /******************************************************************************
 961 * Description:
 962 *       Returns the correct value according to COS and priority in the
 963 *       sp_pri_cli register for PBF.
 964 *.
 965 ******************************************************************************/
 966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
 967 {
 968         const u8 pbf_cos_offset = 0;
 969         const u8 pbf_pri_offset = 0;
 970
 971         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
 972                 pbf_pri_offset, 3);
 973
 974 }
 975
 976 /******************************************************************************
 977 * Description:
 978 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 979 *       according to sp_pri_to_cos.(which COS has higher priority)
 980 *.
 981 ******************************************************************************/
 982 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
 983                                              u8 *sp_pri_to_cos)
 984 {
 985         struct bnx2x *bp = params->bp;
 986         u8 i = 0;
 987         const u8 port = params->port;
 988         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 989         u64 pri_cli_nig = 0x210;
 990         u32 pri_cli_pbf = 0x0;
 991         u8 pri_set = 0;
 992         u8 pri_bitmask = 0;
 993         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 994                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 995
 996         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
 997
 998         /* Set all the strict priority first */
 999         for (i = 0; i < max_num_of_cos; i++) {
1000                 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
1001                         if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
1002                                 DP(NETIF_MSG_LINK,
1003                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1004                                            "invalid cos entry\n");
1005                                 return -EINVAL;
1006                         }
1007
1008                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1009                             sp_pri_to_cos[i], pri_set);
1010
1011                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1012                             sp_pri_to_cos[i], pri_set);
1013                         pri_bitmask = 1 << sp_pri_to_cos[i];
1014                         /* COS is used remove it from bitmap.*/
1015                         if (0 == (pri_bitmask & cos_bit_to_set)) {
1016                                 DP(NETIF_MSG_LINK,
1017                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1018                                         "invalid There can't be two COS's with"
1019                                         " the same strict pri\n");
1020                                 return -EINVAL;
1021                         }
1022                         cos_bit_to_set &= ~pri_bitmask;
1023                         pri_set++;
1024                 }
1025         }
1026
1027         /* Set all the Non strict priority i= COS*/
1028         for (i = 0; i < max_num_of_cos; i++) {
1029                 pri_bitmask = 1 << i;
1030                 /* Check if COS was already used for SP */
1031                 if (pri_bitmask & cos_bit_to_set) {
1032                         /* COS wasn't used for SP */
1033                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1034                             i, pri_set);
1035
1036                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1037                             i, pri_set);
1038                         /* COS is used remove it from bitmap.*/
1039                         cos_bit_to_set &= ~pri_bitmask;
1040                         pri_set++;
1041                 }
1042         }
1043
1044         if (pri_set != max_num_of_cos) {
1045                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1046                                    "entries were set\n");
1047                 return -EINVAL;
1048         }
1049
1050         if (port) {
1051                 /* Only 6 usable clients*/
1052                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1053                        (u32)pri_cli_nig);
1054
1055                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1056         } else {
1057                 /* Only 9 usable clients*/
1058                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1059                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1060
1061                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1062                        pri_cli_nig_lsb);
1063                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1064                        pri_cli_nig_msb);
1065
1066                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1067         }
1068         return 0;
1069 }
1070
1071 /******************************************************************************
1072 * Description:
1073 *       Configure the COS to ETS according to BW and SP settings.
1074 ******************************************************************************/
1075 int bnx2x_ets_e3b0_config(const struct link_params *params,
1076                          const struct link_vars *vars,
1077                          const struct bnx2x_ets_params *ets_params)
1078 {
1079         struct bnx2x *bp = params->bp;
1080         int bnx2x_status = 0;
1081         const u8 port = params->port;
1082         u16 total_bw = 0;
1083         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1084         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1085         u8 cos_bw_bitmap = 0;
1086         u8 cos_sp_bitmap = 0;
1087         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1088         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1089                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1090         u8 cos_entry = 0;
1091
1092         if (!CHIP_IS_E3B0(bp)) {
1093                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
1094                                    "\n");
1095                 return -EINVAL;
1096         }
1097
1098         if ((ets_params->num_of_cos > max_num_of_cos)) {
1099                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1100                                    "isn't supported\n");
1101                 return -EINVAL;
1102         }
1103
1104         /* Prepare sp strict priority parameters*/
1105         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1106
1107         /* Prepare BW parameters*/
1108         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1109                                                    &total_bw);
1110         if (0 != bnx2x_status) {
1111                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config get_total_bw failed "
1112                                    "\n");
1113                 return -EINVAL;
1114         }
1115
1116         /**
1117          *  Upper bound is set according to current link speed (min_w_val
1118          *  should be the same for upper bound and COS credit val).
1119          */
1120         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1121         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1122
1123
1124         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1125                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1126                         cos_bw_bitmap |= (1 << cos_entry);
1127                         /**
1128                          * The function also sets the BW in HW(not the mappin
1129                          * yet)
1130                          */
1131                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1132                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1133                                 total_bw,
1134                                 ets_params->cos[cos_entry].params.bw_params.bw,
1135                                  port);
1136                 } else if (bnx2x_cos_state_strict ==
1137                         ets_params->cos[cos_entry].state){
1138                         cos_sp_bitmap |= (1 << cos_entry);
1139
1140                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1141                                 params,
1142                                 sp_pri_to_cos,
1143                                 ets_params->cos[cos_entry].params.sp_params.pri,
1144                                 cos_entry);
1145
1146                 } else {
1147                         DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config cos state not"
1148                                            " valid\n");
1149                         return -EINVAL;
1150                 }
1151                 if (0 != bnx2x_status) {
1152                         DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config set cos bw "
1153                                            "failed\n");
1154                         return bnx2x_status;
1155                 }
1156         }
1157
1158         /* Set SP register (which COS has higher priority) */
1159         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1160                                                          sp_pri_to_cos);
1161
1162         if (0 != bnx2x_status) {
1163                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config set_pri_cli_reg "
1164                                    "failed\n");
1165                 return bnx2x_status;
1166         }
1167
1168         /* Set client mapping of BW and strict */
1169         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1170                                               cos_sp_bitmap,
1171                                               cos_bw_bitmap);
1172
1173         if (0 != bnx2x_status) {
1174                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1175                 return bnx2x_status;
1176         }
1177         return 0;
1178 }
1179 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1180 {
1181         /* ETS disabled configuration */
1182         struct bnx2x *bp = params->bp;
1183         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1184         /*
1185          * defines which entries (clients) are subjected to WFQ arbitration
1186          * COS0 0x8
1187          * COS1 0x10
1188          */
1189         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1190         /*
1191          * mapping between the ARB_CREDIT_WEIGHT registers and actual
1192          * client numbers (WEIGHT_0 does not actually have to represent
1193          * client 0)
1194          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1195          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1196          */
1197         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1198
1199         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1200                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1201         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1202                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1203
1204         /* ETS mode enabled*/
1205         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1206
1207         /* Defines the number of consecutive slots for the strict priority */
1208         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1209         /*
1210          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1211          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1212          * entry, 4 - COS1 entry.
1213          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1214          * bit4   bit3    bit2     bit1    bit0
1215          * MCP and debug are strict
1216          */
1217         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1218
1219         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1220         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1221                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1222         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1223                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1224 }
1225
1226 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1227                         const u32 cos1_bw)
1228 {
1229         /* ETS disabled configuration*/
1230         struct bnx2x *bp = params->bp;
1231         const u32 total_bw = cos0_bw + cos1_bw;
1232         u32 cos0_credit_weight = 0;
1233         u32 cos1_credit_weight = 0;
1234
1235         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1236
1237         if ((0 == total_bw) ||
1238             (0 == cos0_bw) ||
1239             (0 == cos1_bw)) {
1240                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1241                 return;
1242         }
1243
1244         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1245                 total_bw;
1246         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1247                 total_bw;
1248
1249         bnx2x_ets_bw_limit_common(params);
1250
1251         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1252         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1253
1254         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1255         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1256 }
1257
1258 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1259 {
1260         /* ETS disabled configuration*/
1261         struct bnx2x *bp = params->bp;
1262         u32 val = 0;
1263
1264         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1265         /*
1266          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1267          * as strict.  Bits 0,1,2 - debug and management entries,
1268          * 3 - COS0 entry, 4 - COS1 entry.
1269          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1270          *  bit4   bit3   bit2      bit1     bit0
1271          * MCP and debug are strict
1272          */
1273         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1274         /*
1275          * For strict priority entries defines the number of consecutive slots
1276          * for the highest priority.
1277          */
1278         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1279         /* ETS mode disable */
1280         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1281         /* Defines the number of consecutive slots for the strict priority */
1282         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1283
1284         /* Defines the number of consecutive slots for the strict priority */
1285         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1286
1287         /*
1288          * mapping between entry  priority to client number (0,1,2 -debug and
1289          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1290          * 3bits client num.
1291          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1292          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1293          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1294          */
1295         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1296         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1297
1298         return 0;
1299 }
1300 /******************************************************************/
1301 /*                      PFC section                               */
1302 /******************************************************************/
1303
1304 static void bnx2x_update_pfc_xmac(struct link_params *params,
1305                                   struct link_vars *vars,
1306                                   u8 is_lb)
1307 {
1308         struct bnx2x *bp = params->bp;
1309         u32 xmac_base;
1310         u32 pause_val, pfc0_val, pfc1_val;
1311
1312         /* XMAC base adrr */
1313         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1314
1315         /* Initialize pause and pfc registers */
1316         pause_val = 0x18000;
1317         pfc0_val = 0xFFFF8000;
1318         pfc1_val = 0x2;
1319
1320         /* No PFC support */
1321         if (!(params->feature_config_flags &
1322               FEATURE_CONFIG_PFC_ENABLED)) {
1323
1324                 /*
1325                  * RX flow control - Process pause frame in receive direction
1326                  */
1327                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1328                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1329
1330                 /*
1331                  * TX flow control - Send pause packet when buffer is full
1332                  */
1333                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1334                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1335         } else {/* PFC support */
1336                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1337                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1338                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1339                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1340         }
1341
1342         /* Write pause and PFC registers */
1343         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1344         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1345         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1346
1347
1348         /* Set MAC address for source TX Pause/PFC frames */
1349         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1350                ((params->mac_addr[2] << 24) |
1351                 (params->mac_addr[3] << 16) |
1352                 (params->mac_addr[4] << 8) |
1353                 (params->mac_addr[5])));
1354         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1355                ((params->mac_addr[0] << 8) |
1356                 (params->mac_addr[1])));
1357
1358         udelay(30);
1359 }
1360
1361
1362 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1363                                     u32 pfc_frames_sent[2],
1364                                     u32 pfc_frames_received[2])
1365 {
1366         /* Read pfc statistic */
1367         struct bnx2x *bp = params->bp;
1368         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1369         u32 val_xon = 0;
1370         u32 val_xoff = 0;
1371
1372         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1373
1374         /* PFC received frames */
1375         val_xoff = REG_RD(bp, emac_base +
1376                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1377         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1378         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1379         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1380
1381         pfc_frames_received[0] = val_xon + val_xoff;
1382
1383         /* PFC received sent */
1384         val_xoff = REG_RD(bp, emac_base +
1385                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1386         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1387         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1388         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1389
1390         pfc_frames_sent[0] = val_xon + val_xoff;
1391 }
1392
1393 /* Read pfc statistic*/
1394 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1395                          u32 pfc_frames_sent[2],
1396                          u32 pfc_frames_received[2])
1397 {
1398         /* Read pfc statistic */
1399         struct bnx2x *bp = params->bp;
1400
1401         DP(NETIF_MSG_LINK, "pfc statistic\n");
1402
1403         if (!vars->link_up)
1404                 return;
1405
1406         if (MAC_TYPE_EMAC == vars->mac_type) {
1407                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1408                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1409                                         pfc_frames_received);
1410         }
1411 }
1412 /******************************************************************/
1413 /*                      MAC/PBF section                           */
1414 /******************************************************************/
1415 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1416 {
1417         u32 mode, emac_base;
1418         /**
1419          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1420          * (a value of 49==0x31) and make sure that the AUTO poll is off
1421          */
1422
1423         if (CHIP_IS_E2(bp))
1424                 emac_base = GRCBASE_EMAC0;
1425         else
1426                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1427         mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1428         mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1429                   EMAC_MDIO_MODE_CLOCK_CNT);
1430         if (USES_WARPCORE(bp))
1431                 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1432         else
1433                 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1434
1435         mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1436         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1437
1438         udelay(40);
1439 }
1440
1441 static void bnx2x_emac_init(struct link_params *params,
1442                             struct link_vars *vars)
1443 {
1444         /* reset and unreset the emac core */
1445         struct bnx2x *bp = params->bp;
1446         u8 port = params->port;
1447         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1448         u32 val;
1449         u16 timeout;
1450
1451         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1452                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1453         udelay(5);
1454         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1455                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1456
1457         /* init emac - use read-modify-write */
1458         /* self clear reset */
1459         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1460         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1461
1462         timeout = 200;
1463         do {
1464                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1465                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1466                 if (!timeout) {
1467                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1468                         return;
1469                 }
1470                 timeout--;
1471         } while (val & EMAC_MODE_RESET);
1472         bnx2x_set_mdio_clk(bp, params->chip_id, port);
1473         /* Set mac address */
1474         val = ((params->mac_addr[0] << 8) |
1475                 params->mac_addr[1]);
1476         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1477
1478         val = ((params->mac_addr[2] << 24) |
1479                (params->mac_addr[3] << 16) |
1480                (params->mac_addr[4] << 8) |
1481                 params->mac_addr[5]);
1482         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1483 }
1484
1485 static void bnx2x_set_xumac_nig(struct link_params *params,
1486                                 u16 tx_pause_en,
1487                                 u8 enable)
1488 {
1489         struct bnx2x *bp = params->bp;
1490
1491         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1492                enable);
1493         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1494                enable);
1495         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1496                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1497 }
1498
1499 static void bnx2x_umac_enable(struct link_params *params,
1500                             struct link_vars *vars, u8 lb)
1501 {
1502         u32 val;
1503         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1504         struct bnx2x *bp = params->bp;
1505         /* Reset UMAC */
1506         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1507                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1508         usleep_range(1000, 1000);
1509
1510         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1511                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1512
1513         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1514
1515         /**
1516          * This register determines on which events the MAC will assert
1517          * error on the i/f to the NIG along w/ EOP.
1518          */
1519
1520         /**
1521          * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1522          * params->port*0x14,      0xfffff.
1523          */
1524         /* This register opens the gate for the UMAC despite its name */
1525         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1526
1527         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1528                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1529                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1530                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1531         switch (vars->line_speed) {
1532         case SPEED_10:
1533                 val |= (0<<2);
1534                 break;
1535         case SPEED_100:
1536                 val |= (1<<2);
1537                 break;
1538         case SPEED_1000:
1539                 val |= (2<<2);
1540                 break;
1541         case SPEED_2500:
1542                 val |= (3<<2);
1543                 break;
1544         default:
1545                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1546                                vars->line_speed);
1547                 break;
1548         }
1549         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1550                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1551
1552         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1553                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1554
1555         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1556         udelay(50);
1557
1558         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1559         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1560                ((params->mac_addr[2] << 24) |
1561                 (params->mac_addr[3] << 16) |
1562                 (params->mac_addr[4] << 8) |
1563                 (params->mac_addr[5])));
1564         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1565                ((params->mac_addr[0] << 8) |
1566                 (params->mac_addr[1])));
1567
1568         /* Enable RX and TX */
1569         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1570         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1571                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1572         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1573         udelay(50);
1574
1575         /* Remove SW Reset */
1576         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1577
1578         /* Check loopback mode */
1579         if (lb)
1580                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1581         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1582
1583         /*
1584          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1585          * length used by the MAC receive logic to check frames.
1586          */
1587         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1588         bnx2x_set_xumac_nig(params,
1589                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1590         vars->mac_type = MAC_TYPE_UMAC;
1591
1592 }
1593
1594 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1595 {
1596         u32 port4mode_ovwr_val;
1597         /* Check 4-port override enabled */
1598         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1599         if (port4mode_ovwr_val & (1<<0)) {
1600                 /* Return 4-port mode override value */
1601                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1602         }
1603         /* Return 4-port mode from input pin */
1604         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1605 }
1606
1607 /* Define the XMAC mode */
1608 static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
1609 {
1610         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1611
1612         /**
1613         * In 4-port mode, need to set the mode only once, so if XMAC is
1614         * already out of reset, it means the mode has already been set,
1615         * and it must not* reset the XMAC again, since it controls both
1616         * ports of the path
1617         **/
1618
1619         if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
1620              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1621                 DP(NETIF_MSG_LINK, "XMAC already out of reset"
1622                                    " in 4-port mode\n");
1623                 return;
1624         }
1625
1626         /* Hard reset */
1627         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1628                MISC_REGISTERS_RESET_REG_2_XMAC);
1629         usleep_range(1000, 1000);
1630
1631         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1632                MISC_REGISTERS_RESET_REG_2_XMAC);
1633         if (is_port4mode) {
1634                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1635
1636                 /*  Set the number of ports on the system side to up to 2 */
1637                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1638
1639                 /* Set the number of ports on the Warp Core to 10G */
1640                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1641         } else {
1642                 /*  Set the number of ports on the system side to 1 */
1643                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1644                 if (max_speed == SPEED_10000) {
1645                         DP(NETIF_MSG_LINK, "Init XMAC to 10G x 1"
1646                                            " port per path\n");
1647                         /* Set the number of ports on the Warp Core to 10G */
1648                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1649                 } else {
1650                         DP(NETIF_MSG_LINK, "Init XMAC to 20G x 2 ports"
1651                                            " per path\n");
1652                         /* Set the number of ports on the Warp Core to 20G */
1653                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1654                 }
1655         }
1656         /* Soft reset */
1657         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1658                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1659         usleep_range(1000, 1000);
1660
1661         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1662                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1663
1664 }
1665
1666 static void bnx2x_xmac_disable(struct link_params *params)
1667 {
1668         u8 port = params->port;
1669         struct bnx2x *bp = params->bp;
1670         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1671
1672         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1673             MISC_REGISTERS_RESET_REG_2_XMAC) {
1674                 /*
1675                  * Send an indication to change the state in the NIG back to XON
1676                  * Clearing this bit enables the next set of this bit to get
1677                  * rising edge
1678                  */
1679                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1680                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1681                        (pfc_ctrl & ~(1<<1)));
1682                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1683                        (pfc_ctrl | (1<<1)));
1684                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1685                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1686                 usleep_range(1000, 1000);
1687                 bnx2x_set_xumac_nig(params, 0, 0);
1688                 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
1689                        XMAC_CTRL_REG_SOFT_RESET);
1690         }
1691 }
1692
1693 static int bnx2x_xmac_enable(struct link_params *params,
1694                              struct link_vars *vars, u8 lb)
1695 {
1696         u32 val, xmac_base;
1697         struct bnx2x *bp = params->bp;
1698         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1699
1700         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1701
1702         bnx2x_xmac_init(bp, vars->line_speed);
1703
1704         /*
1705          * This register determines on which events the MAC will assert
1706          * error on the i/f to the NIG along w/ EOP.
1707          */
1708
1709         /*
1710          * This register tells the NIG whether to send traffic to UMAC
1711          * or XMAC
1712          */
1713         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1714
1715         /* Set Max packet size */
1716         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1717
1718         /* CRC append for Tx packets */
1719         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1720
1721         /* update PFC */
1722         bnx2x_update_pfc_xmac(params, vars, 0);
1723
1724         /* Enable TX and RX */
1725         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1726
1727         /* Check loopback mode */
1728         if (lb)
1729                 val |= XMAC_CTRL_REG_CORE_LOCAL_LPBK;
1730         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1731         bnx2x_set_xumac_nig(params,
1732                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1733
1734         vars->mac_type = MAC_TYPE_XMAC;
1735
1736         return 0;
1737 }
1738 static int bnx2x_emac_enable(struct link_params *params,
1739                              struct link_vars *vars, u8 lb)
1740 {
1741         struct bnx2x *bp = params->bp;
1742         u8 port = params->port;
1743         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1744         u32 val;
1745
1746         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1747
1748         /* Disable BMAC */
1749         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1750                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1751
1752         /* enable emac and not bmac */
1753         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1754
1755         /* ASIC */
1756         if (vars->phy_flags & PHY_XGXS_FLAG) {
1757                 u32 ser_lane = ((params->lane_config &
1758                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1759                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1760
1761                 DP(NETIF_MSG_LINK, "XGXS\n");
1762                 /* select the master lanes (out of 0-3) */
1763                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1764                 /* select XGXS */
1765                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1766
1767         } else { /* SerDes */
1768                 DP(NETIF_MSG_LINK, "SerDes\n");
1769                 /* select SerDes */
1770                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1771         }
1772
1773         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1774                       EMAC_RX_MODE_RESET);
1775         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1776                       EMAC_TX_MODE_RESET);
1777
1778         if (CHIP_REV_IS_SLOW(bp)) {
1779                 /* config GMII mode */
1780                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1781                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1782         } else { /* ASIC */
1783                 /* pause enable/disable */
1784                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1785                                EMAC_RX_MODE_FLOW_EN);
1786
1787                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1788                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1789                                 EMAC_TX_MODE_FLOW_EN));
1790                 if (!(params->feature_config_flags &
1791                       FEATURE_CONFIG_PFC_ENABLED)) {
1792                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1793                                 bnx2x_bits_en(bp, emac_base +
1794                                               EMAC_REG_EMAC_RX_MODE,
1795                                               EMAC_RX_MODE_FLOW_EN);
1796
1797                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1798                                 bnx2x_bits_en(bp, emac_base +
1799                                               EMAC_REG_EMAC_TX_MODE,
1800                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1801                                                EMAC_TX_MODE_FLOW_EN));
1802                 } else
1803                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1804                                       EMAC_TX_MODE_FLOW_EN);
1805         }
1806
1807         /* KEEP_VLAN_TAG, promiscuous */
1808         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1809         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1810
1811         /*
1812          * Setting this bit causes MAC control frames (except for pause
1813          * frames) to be passed on for processing. This setting has no
1814          * affect on the operation of the pause frames. This bit effects
1815          * all packets regardless of RX Parser packet sorting logic.
1816          * Turn the PFC off to make sure we are in Xon state before
1817          * enabling it.
1818          */
1819         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1820         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1821                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1822                 /* Enable PFC again */
1823                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1824                         EMAC_REG_RX_PFC_MODE_RX_EN |
1825                         EMAC_REG_RX_PFC_MODE_TX_EN |
1826                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1827
1828                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1829                         ((0x0101 <<
1830                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1831                          (0x00ff <<
1832                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1833                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1834         }
1835         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1836
1837         /* Set Loopback */
1838         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1839         if (lb)
1840                 val |= 0x810;
1841         else
1842                 val &= ~0x810;
1843         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1844
1845         /* enable emac */
1846         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1847
1848         /* enable emac for jumbo packets */
1849         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1850                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1851                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1852
1853         /* strip CRC */
1854         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1855
1856         /* disable the NIG in/out to the bmac */
1857         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1858         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1859         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1860
1861         /* enable the NIG in/out to the emac */
1862         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1863         val = 0;
1864         if ((params->feature_config_flags &
1865               FEATURE_CONFIG_PFC_ENABLED) ||
1866             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1867                 val = 1;
1868
1869         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1870         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1871
1872         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1873
1874         vars->mac_type = MAC_TYPE_EMAC;
1875         return 0;
1876 }
1877
1878 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1879                                    struct link_vars *vars)
1880 {
1881         u32 wb_data[2];
1882         struct bnx2x *bp = params->bp;
1883         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1884                 NIG_REG_INGRESS_BMAC0_MEM;
1885
1886         u32 val = 0x14;
1887         if ((!(params->feature_config_flags &
1888               FEATURE_CONFIG_PFC_ENABLED)) &&
1889                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1890                 /* Enable BigMAC to react on received Pause packets */
1891                 val |= (1<<5);
1892         wb_data[0] = val;
1893         wb_data[1] = 0;
1894         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1895
1896         /* tx control */
1897         val = 0xc0;
1898         if (!(params->feature_config_flags &
1899               FEATURE_CONFIG_PFC_ENABLED) &&
1900                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1901                 val |= 0x800000;
1902         wb_data[0] = val;
1903         wb_data[1] = 0;
1904         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1905 }
1906
1907 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1908                                    struct link_vars *vars,
1909                                    u8 is_lb)
1910 {
1911         /*
1912          * Set rx control: Strip CRC and enable BigMAC to relay
1913          * control packets to the system as well
1914          */
1915         u32 wb_data[2];
1916         struct bnx2x *bp = params->bp;
1917         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1918                 NIG_REG_INGRESS_BMAC0_MEM;
1919         u32 val = 0x14;
1920
1921         if ((!(params->feature_config_flags &
1922               FEATURE_CONFIG_PFC_ENABLED)) &&
1923                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1924                 /* Enable BigMAC to react on received Pause packets */
1925                 val |= (1<<5);
1926         wb_data[0] = val;
1927         wb_data[1] = 0;
1928         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1929         udelay(30);
1930
1931         /* Tx control */
1932         val = 0xc0;
1933         if (!(params->feature_config_flags &
1934                                 FEATURE_CONFIG_PFC_ENABLED) &&
1935             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1936                 val |= 0x800000;
1937         wb_data[0] = val;
1938         wb_data[1] = 0;
1939         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1940
1941         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1942                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1943                 /* Enable PFC RX & TX & STATS and set 8 COS  */
1944                 wb_data[0] = 0x0;
1945                 wb_data[0] |= (1<<0);  /* RX */
1946                 wb_data[0] |= (1<<1);  /* TX */
1947                 wb_data[0] |= (1<<2);  /* Force initial Xon */
1948                 wb_data[0] |= (1<<3);  /* 8 cos */
1949                 wb_data[0] |= (1<<5);  /* STATS */
1950                 wb_data[1] = 0;
1951                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1952                             wb_data, 2);
1953                 /* Clear the force Xon */
1954                 wb_data[0] &= ~(1<<2);
1955         } else {
1956                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1957                 /* disable PFC RX & TX & STATS and set 8 COS */
1958                 wb_data[0] = 0x8;
1959                 wb_data[1] = 0;
1960         }
1961
1962         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1963
1964         /*
1965          * Set Time (based unit is 512 bit time) between automatic
1966          * re-sending of PP packets amd enable automatic re-send of
1967          * Per-Priroity Packet as long as pp_gen is asserted and
1968          * pp_disable is low.
1969          */
1970         val = 0x8000;
1971         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1972                 val |= (1<<16); /* enable automatic re-send */
1973
1974         wb_data[0] = val;
1975         wb_data[1] = 0;
1976         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1977                     wb_data, 2);
1978
1979         /* mac control */
1980         val = 0x3; /* Enable RX and TX */
1981         if (is_lb) {
1982                 val |= 0x4; /* Local loopback */
1983                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1984         }
1985         /* When PFC enabled, Pass pause frames towards the NIG. */
1986         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1987                 val |= ((1<<6)|(1<<5));
1988
1989         wb_data[0] = val;
1990         wb_data[1] = 0;
1991         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1992 }
1993
1994
1995 /* PFC BRB internal port configuration params */
1996 struct bnx2x_pfc_brb_threshold_val {
1997         u32 pause_xoff;
1998         u32 pause_xon;
1999         u32 full_xoff;
2000         u32 full_xon;
2001 };
2002
2003 struct bnx2x_pfc_brb_e3b0_val {
2004         u32 full_lb_xoff_th;
2005         u32 full_lb_xon_threshold;
2006         u32 lb_guarantied;
2007         u32 mac_0_class_t_guarantied;
2008         u32 mac_0_class_t_guarantied_hyst;
2009         u32 mac_1_class_t_guarantied;
2010         u32 mac_1_class_t_guarantied_hyst;
2011 };
2012
2013 struct bnx2x_pfc_brb_th_val {
2014         struct bnx2x_pfc_brb_threshold_val pauseable_th;
2015         struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2016 };
2017 static int bnx2x_pfc_brb_get_config_params(
2018                                 struct link_params *params,
2019                                 struct bnx2x_pfc_brb_th_val *config_val)
2020 {
2021         struct bnx2x *bp = params->bp;
2022         DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2023         if (CHIP_IS_E2(bp)) {
2024                 config_val->pauseable_th.pause_xoff =
2025                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2026                 config_val->pauseable_th.pause_xon =
2027                     PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2028                 config_val->pauseable_th.full_xoff =
2029                     PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2030                 config_val->pauseable_th.full_xon =
2031                     PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2032                 /* non pause able*/
2033                 config_val->non_pauseable_th.pause_xoff =
2034                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2035                 config_val->non_pauseable_th.pause_xon =
2036                     PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2037                 config_val->non_pauseable_th.full_xoff =
2038                     PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2039                 config_val->non_pauseable_th.full_xon =
2040                     PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2041         } else if (CHIP_IS_E3A0(bp)) {
2042                 config_val->pauseable_th.pause_xoff =
2043                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2044                 config_val->pauseable_th.pause_xon =
2045                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2046                 config_val->pauseable_th.full_xoff =
2047                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2048                 config_val->pauseable_th.full_xon =
2049                     PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2050                 /* non pause able*/
2051                 config_val->non_pauseable_th.pause_xoff =
2052                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2053                 config_val->non_pauseable_th.pause_xon =
2054                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2055                 config_val->non_pauseable_th.full_xoff =
2056                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2057                 config_val->non_pauseable_th.full_xon =
2058                     PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2059         } else if (CHIP_IS_E3B0(bp)) {
2060                 if (params->phy[INT_PHY].flags &
2061                     FLAGS_4_PORT_MODE) {
2062                         config_val->pauseable_th.pause_xoff =
2063                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2064                         config_val->pauseable_th.pause_xon =
2065                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2066                         config_val->pauseable_th.full_xoff =
2067                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2068                         config_val->pauseable_th.full_xon =
2069                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2070                         /* non pause able*/
2071                         config_val->non_pauseable_th.pause_xoff =
2072                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2073                         config_val->non_pauseable_th.pause_xon =
2074                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2075                         config_val->non_pauseable_th.full_xoff =
2076                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2077                         config_val->non_pauseable_th.full_xon =
2078                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2079             } else {
2080                 config_val->pauseable_th.pause_xoff =
2081                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2082                 config_val->pauseable_th.pause_xon =
2083                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2084                 config_val->pauseable_th.full_xoff =
2085                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2086                 config_val->pauseable_th.full_xon =
2087                         PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2088                 /* non pause able*/
2089                 config_val->non_pauseable_th.pause_xoff =
2090                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2091                 config_val->non_pauseable_th.pause_xon =
2092                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2093                 config_val->non_pauseable_th.full_xoff =
2094                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2095                 config_val->non_pauseable_th.full_xon =
2096                     PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2097             }
2098         } else
2099             return -EINVAL;
2100
2101         return 0;
2102 }
2103
2104
2105 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
2106                                                  struct bnx2x_pfc_brb_e3b0_val
2107                                                  *e3b0_val,
2108                                                  u32 cos0_pauseable,
2109                                                  u32 cos1_pauseable)
2110 {
2111         if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
2112                 e3b0_val->full_lb_xoff_th =
2113                     PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2114                 e3b0_val->full_lb_xon_threshold =
2115                     PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2116                 e3b0_val->lb_guarantied =
2117                     PFC_E3B0_4P_LB_GUART;
2118                 e3b0_val->mac_0_class_t_guarantied =
2119                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2120                 e3b0_val->mac_0_class_t_guarantied_hyst =
2121                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2122                 e3b0_val->mac_1_class_t_guarantied =
2123                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2124                 e3b0_val->mac_1_class_t_guarantied_hyst =
2125                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2126         } else {
2127                 e3b0_val->full_lb_xoff_th =
2128                     PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2129                 e3b0_val->full_lb_xon_threshold =
2130                     PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2131                 e3b0_val->mac_0_class_t_guarantied_hyst =
2132                     PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2133                 e3b0_val->mac_1_class_t_guarantied =
2134                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2135                 e3b0_val->mac_1_class_t_guarantied_hyst =
2136                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2137
2138                 if (cos0_pauseable != cos1_pauseable) {
2139                         /* nonpauseable= Lossy + pauseable = Lossless*/
2140                         e3b0_val->lb_guarantied =
2141                             PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2142                         e3b0_val->mac_0_class_t_guarantied =
2143                             PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2144                 } else if (cos0_pauseable) {
2145                         /* Lossless +Lossless*/
2146                         e3b0_val->lb_guarantied =
2147                             PFC_E3B0_2P_PAUSE_LB_GUART;
2148                         e3b0_val->mac_0_class_t_guarantied =
2149                             PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2150                 } else {
2151                         /* Lossy +Lossy*/
2152                         e3b0_val->lb_guarantied =
2153                             PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2154                         e3b0_val->mac_0_class_t_guarantied =
2155                             PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2156                 }
2157         }
2158 }
2159 static int bnx2x_update_pfc_brb(struct link_params *params,
2160                                 struct link_vars *vars,
2161                                 struct bnx2x_nig_brb_pfc_port_params
2162                                 *pfc_params)
2163 {
2164         struct bnx2x *bp = params->bp;
2165         struct bnx2x_pfc_brb_th_val config_val = { {0} };
2166         struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2167             &config_val.pauseable_th;
2168         struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2169         int set_pfc = params->feature_config_flags &
2170                 FEATURE_CONFIG_PFC_ENABLED;
2171         int bnx2x_status = 0;
2172         u8 port = params->port;
2173
2174         /* default - pause configuration */
2175         reg_th_config = &config_val.pauseable_th;
2176         bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2177         if (0 != bnx2x_status)
2178                 return bnx2x_status;
2179
2180         if (set_pfc && pfc_params)
2181                 /* First COS */
2182                 if (!pfc_params->cos0_pauseable)
2183                         reg_th_config = &config_val.non_pauseable_th;
2184         /*
2185          * The number of free blocks below which the pause signal to class 0
2186          * of MAC #n is asserted. n=0,1
2187          */
2188         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2189                BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2190                reg_th_config->pause_xoff);
2191         /*
2192          * The number of free blocks above which the pause signal to class 0
2193          * of MAC #n is de-asserted. n=0,1
2194          */
2195         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2196                BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2197         /*
2198          * The number of free blocks below which the full signal to class 0
2199          * of MAC #n is asserted. n=0,1
2200          */
2201         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2202                BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2203         /*
2204          * The number of free blocks above which the full signal to class 0
2205          * of MAC #n is de-asserted. n=0,1
2206          */
2207         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2208                BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2209
2210         if (set_pfc && pfc_params) {
2211                 /* Second COS */
2212                 if (pfc_params->cos1_pauseable)
2213                         reg_th_config = &config_val.pauseable_th;
2214                 else
2215                         reg_th_config = &config_val.non_pauseable_th;
2216                 /*
2217                  * The number of free blocks below which the pause signal to
2218                  * class 1 of MAC #n is asserted. n=0,1
2219                 **/
2220                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2221                        BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2222                        reg_th_config->pause_xoff);
2223                 /*
2224                  * The number of free blocks above which the pause signal to
2225                  * class 1 of MAC #n is de-asserted. n=0,1
2226                  */
2227                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2228                        BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2229                        reg_th_config->pause_xon);
2230                 /*
2231                  * The number of free blocks below which the full signal to
2232                  * class 1 of MAC #n is asserted. n=0,1
2233                  */
2234                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2235                        BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2236                        reg_th_config->full_xoff);
2237                 /*
2238                  * The number of free blocks above which the full signal to
2239                  * class 1 of MAC #n is de-asserted. n=0,1
2240                  */
2241                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2242                        BRB1_REG_FULL_1_XON_THRESHOLD_0,
2243                        reg_th_config->full_xon);
2244
2245
2246                 if (CHIP_IS_E3B0(bp)) {
2247                         /*Should be done by init tool */
2248                         /*
2249                         * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2250                         * reset value
2251                         * 944
2252                         */
2253
2254                         /**
2255                          * The hysteresis on the guarantied buffer space for the Lb port
2256                          * before signaling XON.
2257                          **/
2258                         REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
2259
2260                         bnx2x_pfc_brb_get_e3b0_config_params(
2261                             params,
2262                             &e3b0_val,
2263                             pfc_params->cos0_pauseable,
2264                             pfc_params->cos1_pauseable);
2265                         /**
2266                          * The number of free blocks below which the full signal to the
2267                          * LB port is asserted.
2268                         */
2269                         REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2270                                    e3b0_val.full_lb_xoff_th);
2271                         /**
2272                          * The number of free blocks above which the full signal to the
2273                          * LB port is de-asserted.
2274                         */
2275                         REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2276                                    e3b0_val.full_lb_xon_threshold);
2277                         /**
2278                         * The number of blocks guarantied for the MAC #n port. n=0,1
2279                         */
2280
2281                         /*The number of blocks guarantied for the LB port.*/
2282                         REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2283                                e3b0_val.lb_guarantied);
2284
2285                         /**
2286                          * The number of blocks guarantied for the MAC #n port.
2287                         */
2288                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2289                                    2 * e3b0_val.mac_0_class_t_guarantied);
2290                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2291                                    2 * e3b0_val.mac_1_class_t_guarantied);
2292                         /**
2293                          * The number of blocks guarantied for class #t in MAC0. t=0,1
2294                         */
2295                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2296                                e3b0_val.mac_0_class_t_guarantied);
2297                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2298                                e3b0_val.mac_0_class_t_guarantied);
2299                         /**
2300                          * The hysteresis on the guarantied buffer space for class in
2301                          * MAC0.  t=0,1
2302                         */
2303                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2304                                e3b0_val.mac_0_class_t_guarantied_hyst);
2305                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2306                                e3b0_val.mac_0_class_t_guarantied_hyst);
2307
2308                         /**
2309                          * The number of blocks guarantied for class #t in MAC1.t=0,1
2310                         */
2311                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2312                                e3b0_val.mac_1_class_t_guarantied);
2313                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2314                                e3b0_val.mac_1_class_t_guarantied);
2315                         /**
2316                          * The hysteresis on the guarantied buffer space for class #t
2317                         * in MAC1.  t=0,1
2318                         */
2319                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2320                                e3b0_val.mac_1_class_t_guarantied_hyst);
2321                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2322                                e3b0_val.mac_1_class_t_guarantied_hyst);
2323
2324             }
2325
2326         }
2327
2328         return bnx2x_status;
2329 }
2330
2331 /******************************************************************************
2332 * Description:
2333 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2334 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2335 ******************************************************************************/
2336 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2337                                               u8 cos_entry,
2338                                               u32 priority_mask, u8 port)
2339 {
2340         u32 nig_reg_rx_priority_mask_add = 0;
2341
2342         switch (cos_entry) {
2343         case 0:
2344              nig_reg_rx_priority_mask_add = (port) ?
2345                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2346                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2347              break;
2348         case 1:
2349             nig_reg_rx_priority_mask_add = (port) ?
2350                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2351                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2352             break;
2353         case 2:
2354             nig_reg_rx_priority_mask_add = (port) ?
2355                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2356                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2357             break;
2358         case 3:
2359             if (port)
2360                 return -EINVAL;
2361             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2362             break;
2363         case 4:
2364             if (port)
2365                 return -EINVAL;
2366             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2367             break;
2368         case 5:
2369             if (port)
2370                 return -EINVAL;
2371             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2372             break;
2373         }
2374
2375         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2376
2377         return 0;
2378 }
2379 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2380 {
2381         struct bnx2x *bp = params->bp;
2382
2383         REG_WR(bp, params->shmem_base +
2384                offsetof(struct shmem_region,
2385                         port_mb[params->port].link_status), link_status);
2386 }
2387
2388 static void bnx2x_update_pfc_nig(struct link_params *params,
2389                 struct link_vars *vars,
2390                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2391 {
2392         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2393         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2394         u32 pkt_priority_to_cos = 0;
2395         struct bnx2x *bp = params->bp;
2396         u8 port = params->port;
2397
2398         int set_pfc = params->feature_config_flags &
2399                 FEATURE_CONFIG_PFC_ENABLED;
2400         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2401
2402         /*
2403          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2404          * MAC control frames (that are not pause packets)
2405          * will be forwarded to the XCM.
2406          */
2407         xcm_mask = REG_RD(bp,
2408                                 port ? NIG_REG_LLH1_XCM_MASK :
2409                                 NIG_REG_LLH0_XCM_MASK);
2410         /*
2411          * nig params will override non PFC params, since it's possible to
2412          * do transition from PFC to SAFC
2413          */
2414         if (set_pfc) {
2415                 pause_enable = 0;
2416                 llfc_out_en = 0;
2417                 llfc_enable = 0;
2418                 if (CHIP_IS_E3(bp))
2419                         ppp_enable = 0;
2420                 else
2421                 ppp_enable = 1;
2422                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2423                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2424                 xcm0_out_en = 0;
2425                 p0_hwpfc_enable = 1;
2426         } else  {
2427                 if (nig_params) {
2428                         llfc_out_en = nig_params->llfc_out_en;
2429                         llfc_enable = nig_params->llfc_enable;
2430                         pause_enable = nig_params->pause_enable;
2431                 } else  /*defaul non PFC mode - PAUSE */
2432                         pause_enable = 1;
2433
2434                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2435                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2436                 xcm0_out_en = 1;
2437         }
2438
2439         if (CHIP_IS_E3(bp))
2440                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2441                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2442         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2443                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2444         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2445                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2446         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2447                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2448
2449         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2450                NIG_REG_PPP_ENABLE_0, ppp_enable);
2451
2452         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2453                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2454
2455         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2456
2457         /* output enable for RX_XCM # IF */
2458         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2459
2460         /* HW PFC TX enable */
2461         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2462
2463         if (nig_params) {
2464                 u8 i = 0;
2465                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2466
2467                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2468                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2469                 nig_params->rx_cos_priority_mask[i], port);
2470
2471                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2472                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2473                        nig_params->llfc_high_priority_classes);
2474
2475                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2476                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2477                        nig_params->llfc_low_priority_classes);
2478         }
2479         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2480                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2481                pkt_priority_to_cos);
2482 }
2483
2484 int bnx2x_update_pfc(struct link_params *params,
2485                       struct link_vars *vars,
2486                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2487 {
2488         /*
2489          * The PFC and pause are orthogonal to one another, meaning when
2490          * PFC is enabled, the pause are disabled, and when PFC is
2491          * disabled, pause are set according to the pause result.
2492          */
2493         u32 val;
2494         struct bnx2x *bp = params->bp;
2495         int bnx2x_status = 0;
2496         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2497
2498         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2499                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2500         else
2501                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2502
2503         bnx2x_update_mng(params, vars->link_status);
2504
2505         /* update NIG params */
2506         bnx2x_update_pfc_nig(params, vars, pfc_params);
2507
2508         /* update BRB params */
2509         bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2510         if (0 != bnx2x_status)
2511                 return bnx2x_status;
2512
2513         if (!vars->link_up)
2514                 return bnx2x_status;
2515
2516         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2517         if (CHIP_IS_E3(bp))
2518                 bnx2x_update_pfc_xmac(params, vars, 0);
2519         else {
2520                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2521                 if ((val &
2522                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2523                     == 0) {
2524                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2525                         bnx2x_emac_enable(params, vars, 0);
2526                         return bnx2x_status;
2527                 }
2528
2529                 if (CHIP_IS_E2(bp))
2530                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2531                 else
2532                         bnx2x_update_pfc_bmac1(params, vars);
2533
2534                 val = 0;
2535                 if ((params->feature_config_flags &
2536                      FEATURE_CONFIG_PFC_ENABLED) ||
2537                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2538                         val = 1;
2539                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2540         }
2541         return bnx2x_status;
2542 }
2543
2544
2545 static int bnx2x_bmac1_enable(struct link_params *params,
2546                               struct link_vars *vars,
2547                               u8 is_lb)
2548 {
2549         struct bnx2x *bp = params->bp;
2550         u8 port = params->port;
2551         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2552                                NIG_REG_INGRESS_BMAC0_MEM;
2553         u32 wb_data[2];
2554         u32 val;
2555
2556         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2557
2558         /* XGXS control */
2559         wb_data[0] = 0x3c;
2560         wb_data[1] = 0;
2561         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2562                     wb_data, 2);
2563
2564         /* tx MAC SA */
2565         wb_data[0] = ((params->mac_addr[2] << 24) |
2566                        (params->mac_addr[3] << 16) |
2567                        (params->mac_addr[4] << 8) |
2568                         params->mac_addr[5]);
2569         wb_data[1] = ((params->mac_addr[0] << 8) |
2570                         params->mac_addr[1]);
2571         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2572
2573         /* mac control */
2574         val = 0x3;
2575         if (is_lb) {
2576                 val |= 0x4;
2577                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2578         }
2579         wb_data[0] = val;
2580         wb_data[1] = 0;
2581         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2582
2583         /* set rx mtu */
2584         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2585         wb_data[1] = 0;
2586         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2587
2588         bnx2x_update_pfc_bmac1(params, vars);
2589
2590         /* set tx mtu */
2591         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2592         wb_data[1] = 0;
2593         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2594
2595         /* set cnt max size */
2596         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2597         wb_data[1] = 0;
2598         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2599
2600         /* configure safc */
2601         wb_data[0] = 0x1000200;
2602         wb_data[1] = 0;
2603         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2604                     wb_data, 2);
2605
2606         return 0;
2607 }
2608
2609 static int bnx2x_bmac2_enable(struct link_params *params,
2610                               struct link_vars *vars,
2611                               u8 is_lb)
2612 {
2613         struct bnx2x *bp = params->bp;
2614         u8 port = params->port;
2615         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2616                                NIG_REG_INGRESS_BMAC0_MEM;
2617         u32 wb_data[2];
2618
2619         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2620
2621         wb_data[0] = 0;
2622         wb_data[1] = 0;
2623         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2624         udelay(30);
2625
2626         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2627         wb_data[0] = 0x3c;
2628         wb_data[1] = 0;
2629         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2630                     wb_data, 2);
2631
2632         udelay(30);
2633
2634         /* tx MAC SA */
2635         wb_data[0] = ((params->mac_addr[2] << 24) |
2636                        (params->mac_addr[3] << 16) |
2637                        (params->mac_addr[4] << 8) |
2638                         params->mac_addr[5]);
2639         wb_data[1] = ((params->mac_addr[0] << 8) |
2640                         params->mac_addr[1]);
2641         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2642                     wb_data, 2);
2643
2644         udelay(30);
2645
2646         /* Configure SAFC */
2647         wb_data[0] = 0x1000200;
2648         wb_data[1] = 0;
2649         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2650                     wb_data, 2);
2651         udelay(30);
2652
2653         /* set rx mtu */
2654         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2655         wb_data[1] = 0;
2656         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2657         udelay(30);
2658
2659         /* set tx mtu */
2660         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2661         wb_data[1] = 0;
2662         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2663         udelay(30);
2664         /* set cnt max size */
2665         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2666         wb_data[1] = 0;
2667         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2668         udelay(30);
2669         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2670
2671         return 0;
2672 }
2673
2674 static int bnx2x_bmac_enable(struct link_params *params,
2675                              struct link_vars *vars,
2676                              u8 is_lb)
2677 {
2678         int rc = 0;
2679         u8 port = params->port;
2680         struct bnx2x *bp = params->bp;
2681         u32 val;
2682         /* reset and unreset the BigMac */
2683         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2684                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2685         msleep(1);
2686
2687         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2688                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2689
2690         /* enable access for bmac registers */
2691         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2692
2693         /* Enable BMAC according to BMAC type*/
2694         if (CHIP_IS_E2(bp))
2695                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2696         else
2697                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2698         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2699         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2700         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2701         val = 0;
2702         if ((params->feature_config_flags &
2703               FEATURE_CONFIG_PFC_ENABLED) ||
2704             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2705                 val = 1;
2706         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2707         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2708         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2709         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2710         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2711         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2712
2713         vars->mac_type = MAC_TYPE_BMAC;
2714         return rc;
2715 }
2716
2717 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2718 {
2719         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2720                         NIG_REG_INGRESS_BMAC0_MEM;
2721         u32 wb_data[2];
2722         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2723
2724         /* Only if the bmac is out of reset */
2725         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2726                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2727             nig_bmac_enable) {
2728
2729                 if (CHIP_IS_E2(bp)) {
2730                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2731                         REG_RD_DMAE(bp, bmac_addr +
2732                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2733                                     wb_data, 2);
2734                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2735                         REG_WR_DMAE(bp, bmac_addr +
2736                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2737                                     wb_data, 2);
2738                 } else {
2739                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2740                         REG_RD_DMAE(bp, bmac_addr +
2741                                         BIGMAC_REGISTER_BMAC_CONTROL,
2742                                         wb_data, 2);
2743                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2744                         REG_WR_DMAE(bp, bmac_addr +
2745                                         BIGMAC_REGISTER_BMAC_CONTROL,
2746                                         wb_data, 2);
2747                 }
2748                 msleep(1);
2749         }
2750 }
2751
2752 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2753                             u32 line_speed)
2754 {
2755         struct bnx2x *bp = params->bp;
2756         u8 port = params->port;
2757         u32 init_crd, crd;
2758         u32 count = 1000;
2759
2760         /* disable port */
2761         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2762
2763         /* wait for init credit */
2764         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2765         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2766         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2767
2768         while ((init_crd != crd) && count) {
2769                 msleep(5);
2770
2771                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2772                 count--;
2773         }
2774         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2775         if (init_crd != crd) {
2776                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2777                           init_crd, crd);
2778                 return -EINVAL;
2779         }
2780
2781         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2782             line_speed == SPEED_10 ||
2783             line_speed == SPEED_100 ||
2784             line_speed == SPEED_1000 ||
2785             line_speed == SPEED_2500) {
2786                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2787                 /* update threshold */
2788                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2789                 /* update init credit */
2790                 init_crd = 778;         /* (800-18-4) */
2791
2792         } else {
2793                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2794                               ETH_OVREHEAD)/16;
2795                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2796                 /* update threshold */
2797                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2798                 /* update init credit */
2799                 switch (line_speed) {
2800                 case SPEED_10000:
2801                         init_crd = thresh + 553 - 22;
2802                         break;
2803                 default:
2804                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2805                                   line_speed);
2806                         return -EINVAL;
2807                 }
2808         }
2809         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2810         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2811                  line_speed, init_crd);
2812
2813         /* probe the credit changes */
2814         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2815         msleep(5);
2816         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2817
2818         /* enable port */
2819         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2820         return 0;
2821 }
2822
2823 /**
2824  * bnx2x_get_emac_base - retrive emac base address
2825  *
2826  * @bp:                 driver handle
2827  * @mdc_mdio_access:    access type
2828  * @port:               port id
2829  *
2830  * This function selects the MDC/MDIO access (through emac0 or
2831  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2832  * phy has a default access mode, which could also be overridden
2833  * by nvram configuration. This parameter, whether this is the
2834  * default phy configuration, or the nvram overrun
2835  * configuration, is passed here as mdc_mdio_access and selects
2836  * the emac_base for the CL45 read/writes operations
2837  */
2838 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2839                                u32 mdc_mdio_access, u8 port)
2840 {
2841         u32 emac_base = 0;
2842         switch (mdc_mdio_access) {
2843         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2844                 break;
2845         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2846                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2847                         emac_base = GRCBASE_EMAC1;
2848                 else
2849                         emac_base = GRCBASE_EMAC0;
2850                 break;
2851         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2852                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2853                         emac_base = GRCBASE_EMAC0;
2854                 else
2855                         emac_base = GRCBASE_EMAC1;
2856                 break;
2857         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2858                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2859                 break;
2860         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2861                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2862                 break;
2863         default:
2864                 break;
2865         }
2866         return emac_base;
2867
2868 }
2869
2870 /******************************************************************/
2871 /*                      CL22 access functions                     */
2872 /******************************************************************/
2873 static int bnx2x_cl22_write(struct bnx2x *bp,
2874                                        struct bnx2x_phy *phy,
2875                                        u16 reg, u16 val)
2876 {
2877         u32 tmp, mode;
2878         u8 i;
2879         int rc = 0;
2880         /* Switch to CL22 */
2881         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2882         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2883                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2884
2885         /* address */
2886         tmp = ((phy->addr << 21) | (reg << 16) | val |
2887                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2888                EMAC_MDIO_COMM_START_BUSY);
2889         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2890
2891         for (i = 0; i < 50; i++) {
2892                 udelay(10);
2893
2894                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2895                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2896                         udelay(5);
2897                         break;
2898                 }
2899         }
2900         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2901                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2902                 rc = -EFAULT;
2903         }
2904         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2905         return rc;
2906 }
2907
2908 static int bnx2x_cl22_read(struct bnx2x *bp,
2909                                       struct bnx2x_phy *phy,
2910                                       u16 reg, u16 *ret_val)
2911 {
2912         u32 val, mode;
2913         u16 i;
2914         int rc = 0;
2915
2916         /* Switch to CL22 */
2917         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2918         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2919                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2920
2921         /* address */
2922         val = ((phy->addr << 21) | (reg << 16) |
2923                EMAC_MDIO_COMM_COMMAND_READ_22 |
2924                EMAC_MDIO_COMM_START_BUSY);
2925         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2926
2927         for (i = 0; i < 50; i++) {
2928                 udelay(10);
2929
2930                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2931                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2932                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2933                         udelay(5);
2934                         break;
2935                 }
2936         }
2937         if (val & EMAC_MDIO_COMM_START_BUSY) {
2938                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2939
2940                 *ret_val = 0;
2941                 rc = -EFAULT;
2942         }
2943         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2944         return rc;
2945 }
2946
2947 /******************************************************************/
2948 /*                      CL45 access functions                     */
2949 /******************************************************************/
2950 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2951                            u8 devad, u16 reg, u16 *ret_val)
2952 {
2953         u32 val;
2954         u16 i;
2955         int rc = 0;
2956         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2957                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2958                               EMAC_MDIO_STATUS_10MB);
2959         /* address */
2960         val = ((phy->addr << 21) | (devad << 16) | reg |
2961                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2962                EMAC_MDIO_COMM_START_BUSY);
2963         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2964
2965         for (i = 0; i < 50; i++) {
2966                 udelay(10);
2967
2968                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2969                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2970                         udelay(5);
2971                         break;
2972                 }
2973         }
2974         if (val & EMAC_MDIO_COMM_START_BUSY) {
2975                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2976                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2977                 *ret_val = 0;
2978                 rc = -EFAULT;
2979         } else {
2980                 /* data */
2981                 val = ((phy->addr << 21) | (devad << 16) |
2982                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2983                        EMAC_MDIO_COMM_START_BUSY);
2984                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2985
2986                 for (i = 0; i < 50; i++) {
2987                         udelay(10);
2988
2989                         val = REG_RD(bp, phy->mdio_ctrl +
2990                                      EMAC_REG_EMAC_MDIO_COMM);
2991                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2992                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2993                                 break;
2994                         }
2995                 }
2996                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2997                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2998                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2999                         *ret_val = 0;
3000                         rc = -EFAULT;
3001                 }
3002         }
3003         /* Work around for E3 A0 */
3004         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3005                 phy->flags ^= FLAGS_DUMMY_READ;
3006                 if (phy->flags & FLAGS_DUMMY_READ) {
3007                         u16 temp_val;
3008                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3009                 }
3010         }
3011
3012         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3013                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3014                                EMAC_MDIO_STATUS_10MB);
3015         return rc;
3016 }
3017
3018 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3019                             u8 devad, u16 reg, u16 val)
3020 {
3021         u32 tmp;
3022         u8 i;
3023         int rc = 0;
3024         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3025                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3026                               EMAC_MDIO_STATUS_10MB);
3027
3028         /* address */
3029
3030         tmp = ((phy->addr << 21) | (devad << 16) | reg |
3031                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3032                EMAC_MDIO_COMM_START_BUSY);
3033         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3034
3035         for (i = 0; i < 50; i++) {
3036                 udelay(10);
3037
3038                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3039                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3040                         udelay(5);
3041                         break;
3042                 }
3043         }
3044         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3045                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3046                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3047                 rc = -EFAULT;
3048
3049         } else {
3050                 /* data */
3051                 tmp = ((phy->addr << 21) | (devad << 16) | val |
3052                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3053                        EMAC_MDIO_COMM_START_BUSY);
3054                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3055
3056                 for (i = 0; i < 50; i++) {
3057                         udelay(10);
3058
3059                         tmp = REG_RD(bp, phy->mdio_ctrl +
3060                                      EMAC_REG_EMAC_MDIO_COMM);
3061                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3062                                 udelay(5);
3063                                 break;
3064                         }
3065                 }
3066                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3067                         DP(NETIF_MSG_LINK, "write phy register failed\n");
3068                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3069                         rc = -EFAULT;
3070                 }
3071         }
3072         /* Work around for E3 A0 */
3073         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3074                 phy->flags ^= FLAGS_DUMMY_READ;
3075                 if (phy->flags & FLAGS_DUMMY_READ) {
3076                         u16 temp_val;
3077                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3078                 }
3079         }
3080         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3081                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3082                                EMAC_MDIO_STATUS_10MB);
3083         return rc;
3084 }
3085
3086
3087 /******************************************************************/
3088 /*                      BSC access functions from E3              */
3089 /******************************************************************/
3090 static void bnx2x_bsc_module_sel(struct link_params *params)
3091 {
3092         int idx;
3093         u32 board_cfg, sfp_ctrl;
3094         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3095         struct bnx2x *bp = params->bp;
3096         u8 port = params->port;
3097         /* Read I2C output PINs */
3098         board_cfg = REG_RD(bp, params->shmem_base +
3099                            offsetof(struct shmem_region,
3100                                     dev_info.shared_hw_config.board));
3101         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3102         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3103                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3104
3105         /* Read I2C output value */
3106         sfp_ctrl = REG_RD(bp, params->shmem_base +
3107                           offsetof(struct shmem_region,
3108                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3109         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3110         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3111         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3112         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3113                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3114 }
3115
3116 static int bnx2x_bsc_read(struct link_params *params,
3117                           struct bnx2x_phy *phy,
3118                           u8 sl_devid,
3119                           u16 sl_addr,
3120                           u8 lc_addr,
3121                           u8 xfer_cnt,
3122                           u32 *data_array)
3123 {
3124         u32 val, i;
3125         int rc = 0;
3126         struct bnx2x *bp = params->bp;
3127
3128         if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3129                 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3130                 return -EINVAL;
3131         }
3132
3133         if (xfer_cnt > 16) {
3134                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3135                                         xfer_cnt);
3136                 return -EINVAL;
3137         }
3138         bnx2x_bsc_module_sel(params);
3139
3140         xfer_cnt = 16 - lc_addr;
3141
3142         /* enable the engine */
3143         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3144         val |= MCPR_IMC_COMMAND_ENABLE;
3145         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3146
3147         /* program slave device ID */
3148         val = (sl_devid << 16) | sl_addr;
3149         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3150
3151         /* start xfer with 0 byte to update the address pointer ???*/
3152         val = (MCPR_IMC_COMMAND_ENABLE) |
3153               (MCPR_IMC_COMMAND_WRITE_OP <<
3154                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3155                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3156         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3157
3158         /* poll for completion */
3159         i = 0;
3160         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3161         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3162                 udelay(10);
3163                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3164                 if (i++ > 1000) {
3165                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3166                                                                 i);
3167                         rc = -EFAULT;
3168                         break;
3169                 }
3170         }
3171         if (rc == -EFAULT)
3172                 return rc;
3173
3174         /* start xfer with read op */
3175         val = (MCPR_IMC_COMMAND_ENABLE) |
3176                 (MCPR_IMC_COMMAND_READ_OP <<
3177                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3178                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3179                   (xfer_cnt);
3180         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3181
3182         /* poll for completion */
3183         i = 0;
3184         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3185         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3186                 udelay(10);
3187                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3188                 if (i++ > 1000) {
3189                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3190                         rc = -EFAULT;
3191                         break;
3192                 }
3193         }
3194         if (rc == -EFAULT)
3195                 return rc;
3196
3197         for (i = (lc_addr >> 2); i < 4; i++) {
3198                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3199 #ifdef __BIG_ENDIAN
3200                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3201                                 ((data_array[i] & 0x0000ff00) << 8) |
3202                                 ((data_array[i] & 0x00ff0000) >> 8) |
3203                                 ((data_array[i] & 0xff000000) >> 24);
3204 #endif
3205         }
3206         return rc;
3207 }
3208
3209 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3210                                      u8 devad, u16 reg, u16 or_val)
3211 {
3212         u16 val;
3213         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3214         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3215 }
3216
3217 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3218                    u8 devad, u16 reg, u16 *ret_val)
3219 {
3220         u8 phy_index;
3221         /*
3222          * Probe for the phy according to the given phy_addr, and execute
3223          * the read request on it
3224          */
3225         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3226                 if (params->phy[phy_index].addr == phy_addr) {
3227                         return bnx2x_cl45_read(params->bp,
3228                                                &params->phy[phy_index], devad,
3229                                                reg, ret_val);
3230                 }
3231         }
3232         return -EINVAL;
3233 }
3234
3235 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3236                     u8 devad, u16 reg, u16 val)
3237 {
3238         u8 phy_index;
3239         /*
3240          * Probe for the phy according to the given phy_addr, and execute
3241          * the write request on it
3242          */
3243         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3244                 if (params->phy[phy_index].addr == phy_addr) {
3245                         return bnx2x_cl45_write(params->bp,
3246                                                 &params->phy[phy_index], devad,
3247                                                 reg, val);
3248                 }
3249         }
3250         return -EINVAL;
3251 }
3252 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3253                                   struct link_params *params)
3254 {
3255         u8 lane = 0;
3256         struct bnx2x *bp = params->bp;
3257         u32 path_swap, path_swap_ovr;
3258         u8 path, port;
3259
3260         path = BP_PATH(bp);
3261         port = params->port;
3262
3263         if (bnx2x_is_4_port_mode(bp)) {
3264                 u32 port_swap, port_swap_ovr;
3265
3266                 /*figure out path swap value */
3267                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3268                 if (path_swap_ovr & 0x1)
3269                         path_swap = (path_swap_ovr & 0x2);
3270                 else
3271                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3272
3273                 if (path_swap)
3274                         path = path ^ 1;
3275
3276                 /*figure out port swap value */
3277                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3278                 if (port_swap_ovr & 0x1)
3279                         port_swap = (port_swap_ovr & 0x2);
3280                 else
3281                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3282
3283                 if (port_swap)
3284                         port = port ^ 1;
3285
3286                 lane = (port<<1) + path;
3287         } else { /* two port mode - no port swap */
3288
3289                 /*figure out path swap value */
3290                 path_swap_ovr =
3291                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3292                 if (path_swap_ovr & 0x1) {
3293                         path_swap = (path_swap_ovr & 0x2);
3294                 } else {
3295                         path_swap =
3296                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3297                 }
3298                 if (path_swap)
3299                         path = path ^ 1;
3300
3301                 lane = path << 1 ;
3302         }
3303         return lane;
3304 }
3305
3306 static void bnx2x_set_aer_mmd(struct link_params *params,
3307                               struct bnx2x_phy *phy)
3308 {
3309         u32 ser_lane;
3310         u16 offset, aer_val;
3311         struct bnx2x *bp = params->bp;
3312         ser_lane = ((params->lane_config &
3313                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3314                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3315
3316         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3317                 (phy->addr + ser_lane) : 0;
3318
3319         if (USES_WARPCORE(bp)) {
3320                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3321                 /*
3322                  * In Dual-lane mode, two lanes are joined together,
3323                  * so in order to configure them, the AER broadcast method is
3324                  * used here.
3325                  * 0x200 is the broadcast address for lanes 0,1
3326                  * 0x201 is the broadcast address for lanes 2,3
3327                  */
3328                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3329                         aer_val = (aer_val >> 1) | 0x200;
3330         } else if (CHIP_IS_E2(bp))
3331                 aer_val = 0x3800 + offset - 1;
3332         else
3333                 aer_val = 0x3800 + offset;
3334         DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3335         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3336                           MDIO_AER_BLOCK_AER_REG, aer_val);
3337
3338 }
3339
3340 /******************************************************************/
3341 /*                      Internal phy section                      */
3342 /******************************************************************/
3343
3344 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3345 {
3346         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3347
3348         /* Set Clause 22 */
3349         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3350         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3351         udelay(500);
3352         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3353         udelay(500);
3354          /* Set Clause 45 */
3355         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3356 }
3357
3358 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3359 {
3360         u32 val;
3361
3362         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3363
3364         val = SERDES_RESET_BITS << (port*16);
3365
3366         /* reset and unreset the SerDes/XGXS */
3367         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3368         udelay(500);
3369         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3370
3371         bnx2x_set_serdes_access(bp, port);
3372
3373         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3374                DEFAULT_PHY_DEV_ADDR);
3375 }
3376
3377 static void bnx2x_xgxs_deassert(struct link_params *params)
3378 {
3379         struct bnx2x *bp = params->bp;
3380         u8 port;
3381         u32 val;
3382         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3383         port = params->port;
3384
3385         val = XGXS_RESET_BITS << (port*16);
3386
3387         /* reset and unreset the SerDes/XGXS */
3388         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3389         udelay(500);
3390         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3391
3392         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3393         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3394                params->phy[INT_PHY].def_md_devad);
3395 }
3396
3397 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3398                                      struct link_params *params, u16 *ieee_fc)
3399 {
3400         struct bnx2x *bp = params->bp;
3401         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3402         /**
3403          * resolve pause mode and advertisement Please refer to Table
3404          * 28B-3 of the 802.3ab-1999 spec
3405          */
3406
3407         switch (phy->req_flow_ctrl) {
3408         case BNX2X_FLOW_CTRL_AUTO:
3409                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3410                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3411                 else
3412                         *ieee_fc |=
3413                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3414                 break;
3415
3416         case BNX2X_FLOW_CTRL_TX:
3417                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3418                 break;
3419
3420         case BNX2X_FLOW_CTRL_RX:
3421         case BNX2X_FLOW_CTRL_BOTH:
3422                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3423                 break;
3424
3425         case BNX2X_FLOW_CTRL_NONE:
3426         default:
3427                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3428                 break;
3429         }
3430         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3431 }
3432
3433 static void set_phy_vars(struct link_params *params,
3434                          struct link_vars *vars)
3435 {
3436         struct bnx2x *bp = params->bp;
3437         u8 actual_phy_idx, phy_index, link_cfg_idx;
3438         u8 phy_config_swapped = params->multi_phy_config &
3439                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3440         for (phy_index = INT_PHY; phy_index < params->num_phys;
3441               phy_index++) {
3442                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3443                 actual_phy_idx = phy_index;
3444                 if (phy_config_swapped) {
3445                         if (phy_index == EXT_PHY1)
3446                                 actual_phy_idx = EXT_PHY2;
3447                         else if (phy_index == EXT_PHY2)
3448                                 actual_phy_idx = EXT_PHY1;
3449                 }
3450                 params->phy[actual_phy_idx].req_flow_ctrl =
3451                         params->req_flow_ctrl[link_cfg_idx];
3452
3453                 params->phy[actual_phy_idx].req_line_speed =
3454                         params->req_line_speed[link_cfg_idx];
3455
3456                 params->phy[actual_phy_idx].speed_cap_mask =
3457                         params->speed_cap_mask[link_cfg_idx];
3458
3459                 params->phy[actual_phy_idx].req_duplex =
3460                         params->req_duplex[link_cfg_idx];
3461
3462                 if (params->req_line_speed[link_cfg_idx] ==
3463                     SPEED_AUTO_NEG)
3464                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3465
3466                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3467                            " speed_cap_mask %x\n",
3468                            params->phy[actual_phy_idx].req_flow_ctrl,
3469                            params->phy[actual_phy_idx].req_line_speed,
3470                            params->phy[actual_phy_idx].speed_cap_mask);
3471         }
3472 }
3473
3474 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3475                                     struct bnx2x_phy *phy,
3476                                     struct link_vars *vars)
3477 {
3478         u16 val;
3479         struct bnx2x *bp = params->bp;
3480         /* read modify write pause advertizing */
3481         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3482
3483         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3484
3485         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3486         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3487         if ((vars->ieee_fc &
3488             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3489             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3490                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3491         }
3492         if ((vars->ieee_fc &
3493             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3494             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3495                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3496         }
3497         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3498         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3499 }
3500
3501 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3502 {                                               /*  LD      LP   */
3503         switch (pause_result) {                 /* ASYM P ASYM P */
3504         case 0xb:                               /*   1  0   1  1 */
3505                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3506                 break;
3507
3508         case 0xe:                               /*   1  1   1  0 */
3509                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3510                 break;
3511
3512         case 0x5:                               /*   0  1   0  1 */
3513         case 0x7:                               /*   0  1   1  1 */
3514         case 0xd:                               /*   1  1   0  1 */
3515         case 0xf:                               /*   1  1   1  1 */
3516                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3517                 break;
3518
3519         default:
3520                 break;
3521         }
3522         if (pause_result & (1<<0))
3523                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3524         if (pause_result & (1<<1))
3525                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3526 }
3527
3528 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3529                                    struct link_params *params,
3530                                    struct link_vars *vars)
3531 {
3532         struct bnx2x *bp = params->bp;
3533         u16 ld_pause;           /* local */
3534         u16 lp_pause;           /* link partner */
3535         u16 pause_result;
3536         u8 ret = 0;
3537         /* read twice */
3538
3539         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3540
3541         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3542                 vars->flow_ctrl = phy->req_flow_ctrl;
3543         else if (phy->req_line_speed != SPEED_AUTO_NEG)
3544                 vars->flow_ctrl = params->req_fc_auto_adv;
3545         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3546                 ret = 1;
3547                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3548                         bnx2x_cl22_read(bp, phy,
3549                                         0x4, &ld_pause);
3550                         bnx2x_cl22_read(bp, phy,
3551                                         0x5, &lp_pause);
3552                 } else {
3553                         bnx2x_cl45_read(bp, phy,
3554                                         MDIO_AN_DEVAD,
3555                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3556                         bnx2x_cl45_read(bp, phy,
3557                                         MDIO_AN_DEVAD,
3558                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3559                 }
3560                 pause_result = (ld_pause &
3561                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3562                 pause_result |= (lp_pause &
3563                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3564                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3565                    pause_result);
3566                 bnx2x_pause_resolve(vars, pause_result);
3567         }
3568         return ret;
3569 }
3570 /******************************************************************/
3571 /*                      Warpcore section                          */
3572 /******************************************************************/
3573 /* The init_internal_warpcore should mirror the xgxs,
3574  * i.e. reset the lane (if needed), set aer for the
3575  * init configuration, and set/clear SGMII flag. Internal
3576  * phy init is done purely in phy_init stage.
3577  */
3578 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3579                                         struct link_params *params,
3580                                         struct link_vars *vars) {
3581         u16 val16 = 0, lane, bam37 = 0;
3582         struct bnx2x *bp = params->bp;
3583         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3584         /* Check adding advertisement for 1G KX */
3585         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3586              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3587             (vars->line_speed == SPEED_1000)) {
3588                 u16 sd_digital;
3589                 val16 |= (1<<5);
3590
3591                 /* Enable CL37 1G Parallel Detect */
3592                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3593                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3594                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3595                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3596                                  (sd_digital | 0x1));
3597
3598                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3599         }
3600         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3601              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3602             (vars->line_speed ==  SPEED_10000)) {
3603                 /* Check adding advertisement for 10G KR */
3604                 val16 |= (1<<7);
3605                 /* Enable 10G Parallel Detect */
3606                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3607                                 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3608
3609                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3610         }
3611
3612         /* Set Transmit PMD settings */
3613         lane = bnx2x_get_warpcore_lane(phy, params);
3614         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3615                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3616                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3617                       (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3618                       (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3619         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3620                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3621                          0x03f0);
3622         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3623                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3624                          0x03f0);
3625         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3626                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3627                          0x383f);
3628
3629         /* Advertised speeds */
3630         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3631                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3632
3633         /* Enable CL37 BAM */
3634         if (REG_RD(bp, params->shmem_base +
3635                    offsetof(struct shmem_region, dev_info.
3636                             port_hw_config[params->port].default_cfg)) &
3637             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3638                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3639                                 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3640                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3641                         MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3642                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3643         }
3644
3645         /* Advertise pause */
3646         bnx2x_ext_phy_set_pause(params, phy, vars);
3647
3648         /* Enable Autoneg */
3649         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3650                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3651
3652         /* Over 1G - AN local device user page 1 */
3653         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3654                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3655
3656         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3657                         MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3658
3659         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3660                          MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3661 }
3662
3663 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3664                                       struct link_params *params,
3665                                       struct link_vars *vars)
3666 {
3667         struct bnx2x *bp = params->bp;
3668         u16 val;
3669
3670         /* Disable Autoneg */
3671         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3672                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3673
3674         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3675                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3676
3677         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3678                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3679
3680         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3681                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3682
3683         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3684                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3685
3686         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3687                         MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3688
3689         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3690                          MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3691
3692         /* Disable CL36 PCS Tx */
3693         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3694                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3695
3696         /* Double Wide Single Data Rate @ pll rate */
3697         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3698                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3699
3700         /* Leave cl72 training enable, needed for KR */
3701         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3702                 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3703                 0x2);
3704
3705         /* Leave CL72 enabled */
3706         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3707                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3708                          &val);
3709         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3710                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3711                          val | 0x3800);
3712
3713         /* Set speed via PMA/PMD register */
3714         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3715                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3716
3717         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3718                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3719
3720         /*Enable encoded forced speed */
3721         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3722                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3723
3724         /* Turn TX scramble payload only the 64/66 scrambler */
3725         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3726                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3727
3728         /* Turn RX scramble payload only the 64/66 scrambler */
3729         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3730                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3731
3732         /* set and clear loopback to cause a reset to 64/66 decoder */
3733         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3734                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3735         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3736                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3737
3738 }
3739
3740 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3741                                        struct link_params *params,
3742                                        u8 is_xfi)
3743 {
3744         struct bnx2x *bp = params->bp;
3745         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3746         /* Hold rxSeqStart */
3747         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3748                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3749         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3750                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3751
3752         /* Hold tx_fifo_reset */
3753         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3754                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3755         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3756                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3757
3758         /* Disable CL73 AN */
3759         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3760
3761         /* Disable 100FX Enable and Auto-Detect */
3762         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3763                         MDIO_WC_REG_FX100_CTRL1, &val);
3764         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3765                          MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3766
3767         /* Disable 100FX Idle detect */
3768         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3769                         MDIO_WC_REG_FX100_CTRL3, &val);
3770         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3771                          MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3772
3773         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3774         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3775                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3776         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3777                          MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3778
3779         /* Turn off auto-detect & fiber mode */
3780         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3781                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3782         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3783                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3784                          (val & 0xFFEE));
3785
3786         /* Set filter_force_link, disable_false_link and parallel_detect */
3787         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3788                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3789         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3790                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3791                          ((val | 0x0006) & 0xFFFE));
3792
3793         /* Set XFI / SFI */
3794         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3795                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3796
3797         misc1_val &= ~(0x1f);
3798
3799         if (is_xfi) {
3800                 misc1_val |= 0x5;
3801                 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3802                            (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3803                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3804                 tx_driver_val =
3805                       ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3806                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3807                        (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3808
3809         } else {
3810                 misc1_val |= 0x9;
3811                 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3812                            (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3813                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3814                 tx_driver_val =
3815                       ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3816                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3817                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3818         }
3819         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3820                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3821
3822         /* Set Transmit PMD settings */
3823         lane = bnx2x_get_warpcore_lane(phy, params);
3824         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3825                          MDIO_WC_REG_TX_FIR_TAP,
3826                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3827         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3828                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3829                          tx_driver_val);
3830
3831         /* Enable fiber mode, enable and invert sig_det */
3832         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3833                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3834         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3835                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3836
3837         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3838         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3839                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3840         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3841                          MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3842
3843         /* 10G XFI Full Duplex */
3844         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3845                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3846
3847         /* Release tx_fifo_reset */
3848         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3849                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3850         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3851                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3852
3853         /* Release rxSeqStart */
3854         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3855                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3856         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3857                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3858 }
3859
3860 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3861                                        struct bnx2x_phy *phy)
3862 {
3863         DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3864 }
3865
3866 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3867                                          struct bnx2x_phy *phy,
3868                                          u16 lane)
3869 {
3870         /* Rx0 anaRxControl1G */
3871         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3872                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3873
3874         /* Rx2 anaRxControl1G */
3875         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3876                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3877
3878         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3879                          MDIO_WC_REG_RX66_SCW0, 0xE070);
3880
3881         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3882                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3883
3884         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3885                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3886
3887         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3888                          MDIO_WC_REG_RX66_SCW3, 0x8090);
3889
3890         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3891                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3892
3893         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3894                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3895
3896         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3897                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3898
3899         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3900                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3901
3902         /* Serdes Digital Misc1 */
3903         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3904                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3905
3906         /* Serdes Digital4 Misc3 */
3907         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3908                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3909
3910         /* Set Transmit PMD settings */
3911         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3912                          MDIO_WC_REG_TX_FIR_TAP,
3913                         ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3914                          (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3915                          (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
3916                          MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3917         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3918                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3919                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3920                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3921                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3922 }
3923
3924 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
3925                                            struct link_params *params,
3926                                            u8 fiber_mode)
3927 {
3928         struct bnx2x *bp = params->bp;
3929         u16 val16, digctrl_kx1, digctrl_kx2;
3930         u8 lane;
3931
3932         lane = bnx2x_get_warpcore_lane(phy, params);
3933
3934         /* Clear XFI clock comp in non-10G single lane mode. */
3935         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3936                         MDIO_WC_REG_RX66_CONTROL, &val16);
3937         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3938                          MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
3939
3940         if (phy->req_line_speed == SPEED_AUTO_NEG) {
3941                 /* SGMII Autoneg */
3942                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3943                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3944                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3945                                  MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3946                                  val16 | 0x1000);
3947                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
3948         } else {
3949                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3950                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3951                 val16 &= 0xcfbf;
3952                 switch (phy->req_line_speed) {
3953                 case SPEED_10:
3954                         break;
3955                 case SPEED_100:
3956                         val16 |= 0x2000;
3957                         break;
3958                 case SPEED_1000:
3959                         val16 |= 0x0040;
3960                         break;
3961                 default:
3962                         DP(NETIF_MSG_LINK, "Speed not supported: 0x%x"
3963                                            "\n", phy->req_line_speed);
3964                         return;
3965                 }
3966
3967                 if (phy->req_duplex == DUPLEX_FULL)
3968                         val16 |= 0x0100;
3969
3970                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3971                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3972
3973                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
3974                                phy->req_line_speed);
3975                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3976                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3977                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
3978         }
3979
3980         /* SGMII Slave mode and disable signal detect */
3981         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3982                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3983         if (fiber_mode)
3984                 digctrl_kx1 = 1;
3985         else
3986                 digctrl_kx1 &= 0xff4a;
3987
3988         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3989                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3990                         digctrl_kx1);
3991
3992         /* Turn off parallel detect */
3993         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3994                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3995         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3996                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3997                         (digctrl_kx2 & ~(1<<2)));
3998
3999         /* Re-enable parallel detect */
4000         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4001                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4002                         (digctrl_kx2 | (1<<2)));
4003
4004         /* Enable autodet */
4005         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4006                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4007                         (digctrl_kx1 | 0x10));
4008 }
4009
4010 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4011                                       struct bnx2x_phy *phy,
4012                                       u8 reset)
4013 {
4014         u16 val;
4015         /* Take lane out of reset after configuration is finished */
4016         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4017                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4018         if (reset)
4019                 val |= 0xC000;
4020         else
4021                 val &= 0x3FFF;
4022         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4023                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4024         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4025                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4026 }
4027
4028
4029         /* Clear SFI/XFI link settings registers */
4030 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4031                                       struct link_params *params,
4032                                       u16 lane)
4033 {
4034         struct bnx2x *bp = params->bp;
4035         u16 val16;
4036
4037         /* Set XFI clock comp as default. */
4038         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4039                         MDIO_WC_REG_RX66_CONTROL, &val16);
4040         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4041                          MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4042
4043         bnx2x_warpcore_reset_lane(bp, phy, 1);
4044         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4045         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4046                          MDIO_WC_REG_FX100_CTRL1, 0x014a);
4047         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4048                          MDIO_WC_REG_FX100_CTRL3, 0x0800);
4049         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4050                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4051         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4052                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4053         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4054                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4055         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4056                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4057         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4058                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4059         lane = bnx2x_get_warpcore_lane(phy, params);
4060         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4061                          MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4062         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4063                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4064         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4065                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4066         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4067                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4068         bnx2x_warpcore_reset_lane(bp, phy, 0);
4069 }
4070
4071 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4072                                                 u32 chip_id,
4073                                                 u32 shmem_base, u8 port,
4074                                                 u8 *gpio_num, u8 *gpio_port)
4075 {
4076         u32 cfg_pin;
4077         *gpio_num = 0;
4078         *gpio_port = 0;
4079         if (CHIP_IS_E3(bp)) {
4080                 cfg_pin = (REG_RD(bp, shmem_base +
4081                                 offsetof(struct shmem_region,
4082                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4083                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4084                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4085
4086                 /*
4087                  * Should not happen. This function called upon interrupt
4088                  * triggered by GPIO ( since EPIO can only generate interrupts
4089                  * to MCP).
4090                  * So if this function was called and none of the GPIOs was set,
4091                  * it means the shit hit the fan.
4092                  */
4093                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4094                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4095                         DP(NETIF_MSG_LINK, "ERROR: Invalid cfg pin %x for "
4096                                            "module detect indication\n",
4097                                        cfg_pin);
4098                         return -EINVAL;
4099                 }
4100
4101                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4102                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4103         } else {
4104                 *gpio_num = MISC_REGISTERS_GPIO_3;
4105                 *gpio_port = port;
4106         }
4107         DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4108         return 0;
4109 }
4110
4111 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4112                                        struct link_params *params)
4113 {
4114         struct bnx2x *bp = params->bp;
4115         u8 gpio_num, gpio_port;
4116         u32 gpio_val;
4117         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4118                                       params->shmem_base, params->port,
4119                                       &gpio_num, &gpio_port) != 0)
4120                 return 0;
4121         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4122
4123         /* Call the handling function in case module is detected */
4124         if (gpio_val == 0)
4125                 return 1;
4126         else
4127                 return 0;
4128 }
4129
4130 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4131                                        struct link_params *params,
4132                                        struct link_vars *vars)
4133 {
4134         struct bnx2x *bp = params->bp;
4135         u32 serdes_net_if;
4136         u8 fiber_mode;
4137         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4138         serdes_net_if = (REG_RD(bp, params->shmem_base +
4139                          offsetof(struct shmem_region, dev_info.
4140                                   port_hw_config[params->port].default_cfg)) &
4141                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4142         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4143                            "serdes_net_if = 0x%x\n",
4144                        vars->line_speed, serdes_net_if);
4145         bnx2x_set_aer_mmd(params, phy);
4146
4147         vars->phy_flags |= PHY_XGXS_FLAG;
4148         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4149             (phy->req_line_speed &&
4150              ((phy->req_line_speed == SPEED_100) ||
4151               (phy->req_line_speed == SPEED_10)))) {
4152                 vars->phy_flags |= PHY_SGMII_FLAG;
4153                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4154                 bnx2x_warpcore_clear_regs(phy, params, lane);
4155                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
4156         } else {
4157                 switch (serdes_net_if) {
4158                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4159                         /* Enable KR Auto Neg */
4160                         if (params->loopback_mode == LOOPBACK_NONE)
4161                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4162                         else {
4163                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4164                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4165                         }
4166                         break;
4167
4168                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4169                         bnx2x_warpcore_clear_regs(phy, params, lane);
4170                         if (vars->line_speed == SPEED_10000) {
4171                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4172                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4173                         } else {
4174                                 if (SINGLE_MEDIA_DIRECT(params)) {
4175                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4176                                         fiber_mode = 1;
4177                                 } else {
4178                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4179                                         fiber_mode = 0;
4180                                 }
4181                                 bnx2x_warpcore_set_sgmii_speed(phy,
4182                                                                 params,
4183                                                                 fiber_mode);
4184                         }
4185
4186                         break;
4187
4188                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4189
4190                         bnx2x_warpcore_clear_regs(phy, params, lane);
4191                         if (vars->line_speed == SPEED_10000) {
4192                                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4193                                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4194                         } else if (vars->line_speed == SPEED_1000) {
4195                                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4196                                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
4197                         }
4198                         /* Issue Module detection */
4199                         if (bnx2x_is_sfp_module_plugged(phy, params))
4200                                 bnx2x_sfp_module_detection(phy, params);
4201                         break;
4202
4203                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4204                         if (vars->line_speed != SPEED_20000) {
4205                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4206                                 return;
4207                         }
4208                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4209                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4210                         /* Issue Module detection */
4211
4212                         bnx2x_sfp_module_detection(phy, params);
4213                         break;
4214
4215                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4216                         if (vars->line_speed != SPEED_20000) {
4217                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4218                                 return;
4219                         }
4220                         DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4221                         bnx2x_warpcore_set_20G_KR2(bp, phy);
4222                         break;
4223
4224                 default:
4225                         DP(NETIF_MSG_LINK, "Unsupported Serdes Net Interface "
4226                                            "0x%x\n", serdes_net_if);
4227                         return;
4228                 }
4229         }
4230
4231         /* Take lane out of reset after configuration is finished */
4232         bnx2x_warpcore_reset_lane(bp, phy, 0);
4233         DP(NETIF_MSG_LINK, "Exit config init\n");
4234 }
4235
4236 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4237                                          struct bnx2x_phy *phy,
4238                                          u8 tx_en)
4239 {
4240         struct bnx2x *bp = params->bp;
4241         u32 cfg_pin;
4242         u8 port = params->port;
4243
4244         cfg_pin = REG_RD(bp, params->shmem_base +
4245                                 offsetof(struct shmem_region,
4246                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4247                                 PORT_HW_CFG_TX_LASER_MASK;
4248         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4249         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4250         /* For 20G, the expected pin to be used is 3 pins after the current */
4251
4252         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4253         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4254                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4255 }
4256
4257 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4258                                       struct link_params *params)
4259 {
4260         struct bnx2x *bp = params->bp;
4261         u16 val16;
4262         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4263         bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4264         bnx2x_set_aer_mmd(params, phy);
4265         /* Global register */
4266         bnx2x_warpcore_reset_lane(bp, phy, 1);
4267
4268         /* Clear loopback settings (if any) */
4269         /* 10G & 20G */
4270         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4271                         MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4272         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4273                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4274                          0xBFFF);
4275
4276         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4277                         MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4278         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4279                         MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4280
4281         /* Update those 1-copy registers */
4282         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4283                           MDIO_AER_BLOCK_AER_REG, 0);
4284                 /* Enable 1G MDIO (1-copy) */
4285         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4286                         MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4287                         &val16);
4288         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4289                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4290                          val16 & ~0x10);
4291
4292         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4293                         MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4294         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4295                          MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4296                          val16 & 0xff00);
4297
4298 }
4299
4300 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4301                                         struct link_params *params)
4302 {
4303         struct bnx2x *bp = params->bp;
4304         u16 val16;
4305         u32 lane;
4306         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4307                        params->loopback_mode, phy->req_line_speed);
4308
4309         if (phy->req_line_speed < SPEED_10000) {
4310                 /* 10/100/1000 */
4311
4312                 /* Update those 1-copy registers */
4313                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4314                                   MDIO_AER_BLOCK_AER_REG, 0);
4315                 /* Enable 1G MDIO (1-copy) */
4316                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4317                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4318                                 &val16);
4319                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4320                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4321                                 val16 | 0x10);
4322                 /* Set 1G loopback based on lane (1-copy) */
4323                 lane = bnx2x_get_warpcore_lane(phy, params);
4324                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4325                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4326                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4327                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4328                                 val16 | (1<<lane));
4329
4330                 /* Switch back to 4-copy registers */
4331                 bnx2x_set_aer_mmd(params, phy);
4332                 /* Global loopback, not recommended. */
4333                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4334                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4335                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4336                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4337                                 0x4000);
4338         } else {
4339                 /* 10G & 20G */
4340                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4341                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4342                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4343                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4344                                  0x4000);
4345
4346                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4347                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4348                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4349                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4350         }
4351 }
4352
4353
4354 void bnx2x_link_status_update(struct link_params *params,
4355                               struct link_vars *vars)
4356 {
4357         struct bnx2x *bp = params->bp;
4358         u8 link_10g_plus;
4359         u8 port = params->port;
4360         u32 sync_offset, media_types;
4361         /* Update PHY configuration */
4362         set_phy_vars(params, vars);
4363
4364         vars->link_status = REG_RD(bp, params->shmem_base +
4365                                    offsetof(struct shmem_region,
4366                                             port_mb[port].link_status));
4367
4368         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4369         vars->phy_flags = PHY_XGXS_FLAG;
4370         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4371                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4372
4373         if (vars->link_up) {
4374                 DP(NETIF_MSG_LINK, "phy link up\n");
4375
4376                 vars->phy_link_up = 1;
4377                 vars->duplex = DUPLEX_FULL;
4378                 switch (vars->link_status &
4379                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4380                         case LINK_10THD:
4381                                 vars->duplex = DUPLEX_HALF;
4382                                 /* fall thru */
4383                         case LINK_10TFD:
4384                                 vars->line_speed = SPEED_10;
4385                                 break;
4386
4387                         case LINK_100TXHD:
4388                                 vars->duplex = DUPLEX_HALF;
4389                                 /* fall thru */
4390                         case LINK_100T4:
4391                         case LINK_100TXFD:
4392                                 vars->line_speed = SPEED_100;
4393                                 break;
4394
4395                         case LINK_1000THD:
4396                                 vars->duplex = DUPLEX_HALF;
4397                                 /* fall thru */
4398                         case LINK_1000TFD:
4399                                 vars->line_speed = SPEED_1000;
4400                                 break;
4401
4402                         case LINK_2500THD:
4403                                 vars->duplex = DUPLEX_HALF;
4404                                 /* fall thru */
4405                         case LINK_2500TFD:
4406                                 vars->line_speed = SPEED_2500;
4407                                 break;
4408
4409                         case LINK_10GTFD:
4410                                 vars->line_speed = SPEED_10000;
4411                                 break;
4412                         case LINK_20GTFD:
4413                                 vars->line_speed = SPEED_20000;
4414                                 break;
4415                         default:
4416                                 break;
4417                 }
4418                 vars->flow_ctrl = 0;
4419                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4420                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4421
4422                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4423                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4424
4425                 if (!vars->flow_ctrl)
4426                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4427
4428                 if (vars->line_speed &&
4429                     ((vars->line_speed == SPEED_10) ||
4430                      (vars->line_speed == SPEED_100))) {
4431                         vars->phy_flags |= PHY_SGMII_FLAG;
4432                 } else {
4433                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4434                 }
4435                 if (vars->line_speed &&
4436                     USES_WARPCORE(bp) &&
4437                     (vars->line_speed == SPEED_1000))
4438                         vars->phy_flags |= PHY_SGMII_FLAG;
4439                 /* anything 10 and over uses the bmac */
4440                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4441
4442                 if (link_10g_plus) {
4443                         if (USES_WARPCORE(bp))
4444                                 vars->mac_type = MAC_TYPE_XMAC;
4445                         else
4446                                 vars->mac_type = MAC_TYPE_BMAC;
4447                 } else {
4448                         if (USES_WARPCORE(bp))
4449                                 vars->mac_type = MAC_TYPE_UMAC;
4450                         else
4451                                 vars->mac_type = MAC_TYPE_EMAC;
4452                 }
4453         } else { /* link down */
4454                 DP(NETIF_MSG_LINK, "phy link down\n");
4455
4456                 vars->phy_link_up = 0;
4457
4458                 vars->line_speed = 0;
4459                 vars->duplex = DUPLEX_FULL;
4460                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4461
4462                 /* indicate no mac active */
4463                 vars->mac_type = MAC_TYPE_NONE;
4464                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4465                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4466         }
4467
4468         /* Sync media type */
4469         sync_offset = params->shmem_base +
4470                         offsetof(struct shmem_region,
4471                                  dev_info.port_hw_config[port].media_type);
4472         media_types = REG_RD(bp, sync_offset);
4473
4474         params->phy[INT_PHY].media_type =
4475                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4476                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4477         params->phy[EXT_PHY1].media_type =
4478                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4479                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4480         params->phy[EXT_PHY2].media_type =
4481                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4482                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4483         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4484
4485         /* Sync AEU offset */
4486         sync_offset = params->shmem_base +
4487                         offsetof(struct shmem_region,
4488                                  dev_info.port_hw_config[port].aeu_int_mask);
4489
4490         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4491
4492         /* Sync PFC status */
4493         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4494                 params->feature_config_flags |=
4495                                         FEATURE_CONFIG_PFC_ENABLED;
4496         else
4497                 params->feature_config_flags &=
4498                                         ~FEATURE_CONFIG_PFC_ENABLED;
4499
4500         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4501                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4502         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4503                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4504 }
4505
4506
4507 static void bnx2x_set_master_ln(struct link_params *params,
4508                                 struct bnx2x_phy *phy)
4509 {
4510         struct bnx2x *bp = params->bp;
4511         u16 new_master_ln, ser_lane;
4512         ser_lane = ((params->lane_config &
4513                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4514                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4515
4516         /* set the master_ln for AN */
4517         CL22_RD_OVER_CL45(bp, phy,
4518                           MDIO_REG_BANK_XGXS_BLOCK2,
4519                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4520                           &new_master_ln);
4521
4522         CL22_WR_OVER_CL45(bp, phy,
4523                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4524                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4525                           (new_master_ln | ser_lane));
4526 }
4527
4528 static int bnx2x_reset_unicore(struct link_params *params,
4529                                struct bnx2x_phy *phy,
4530                                u8 set_serdes)
4531 {
4532         struct bnx2x *bp = params->bp;
4533         u16 mii_control;
4534         u16 i;
4535         CL22_RD_OVER_CL45(bp, phy,
4536                           MDIO_REG_BANK_COMBO_IEEE0,
4537                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4538
4539         /* reset the unicore */
4540         CL22_WR_OVER_CL45(bp, phy,
4541                           MDIO_REG_BANK_COMBO_IEEE0,
4542                           MDIO_COMBO_IEEE0_MII_CONTROL,
4543                           (mii_control |
4544                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4545         if (set_serdes)
4546                 bnx2x_set_serdes_access(bp, params->port);
4547
4548         /* wait for the reset to self clear */
4549         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4550                 udelay(5);
4551
4552                 /* the reset erased the previous bank value */
4553                 CL22_RD_OVER_CL45(bp, phy,
4554                                   MDIO_REG_BANK_COMBO_IEEE0,
4555                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4556                                   &mii_control);
4557
4558                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4559                         udelay(5);
4560                         return 0;
4561                 }
4562         }
4563
4564         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4565                               " Port %d\n",
4566                          params->port);
4567         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4568         return -EINVAL;
4569
4570 }
4571
4572 static void bnx2x_set_swap_lanes(struct link_params *params,
4573                                  struct bnx2x_phy *phy)
4574 {
4575         struct bnx2x *bp = params->bp;
4576         /*
4577          *  Each two bits represents a lane number:
4578          *  No swap is 0123 => 0x1b no need to enable the swap
4579          */
4580         u16 ser_lane, rx_lane_swap, tx_lane_swap;
4581
4582         ser_lane = ((params->lane_config &
4583                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4584                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4585         rx_lane_swap = ((params->lane_config &
4586                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4587                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4588         tx_lane_swap = ((params->lane_config &
4589                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4590                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4591
4592         if (rx_lane_swap != 0x1b) {
4593                 CL22_WR_OVER_CL45(bp, phy,
4594                                   MDIO_REG_BANK_XGXS_BLOCK2,
4595                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4596                                   (rx_lane_swap |
4597                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4598                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4599         } else {
4600                 CL22_WR_OVER_CL45(bp, phy,
4601                                   MDIO_REG_BANK_XGXS_BLOCK2,
4602                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4603         }
4604
4605         if (tx_lane_swap != 0x1b) {
4606                 CL22_WR_OVER_CL45(bp, phy,
4607                                   MDIO_REG_BANK_XGXS_BLOCK2,
4608                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4609                                   (tx_lane_swap |
4610                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4611         } else {
4612                 CL22_WR_OVER_CL45(bp, phy,
4613                                   MDIO_REG_BANK_XGXS_BLOCK2,
4614                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4615         }
4616 }
4617
4618 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4619                                          struct link_params *params)
4620 {
4621         struct bnx2x *bp = params->bp;
4622         u16 control2;
4623         CL22_RD_OVER_CL45(bp, phy,
4624                           MDIO_REG_BANK_SERDES_DIGITAL,
4625                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4626                           &control2);
4627         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4628                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4629         else
4630                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4631         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4632                 phy->speed_cap_mask, control2);
4633         CL22_WR_OVER_CL45(bp, phy,
4634                           MDIO_REG_BANK_SERDES_DIGITAL,
4635                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4636                           control2);
4637
4638         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4639              (phy->speed_cap_mask &
4640                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4641                 DP(NETIF_MSG_LINK, "XGXS\n");
4642
4643                 CL22_WR_OVER_CL45(bp, phy,
4644                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4645                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4646                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4647
4648                 CL22_RD_OVER_CL45(bp, phy,
4649                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4650                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4651                                   &control2);
4652
4653
4654                 control2 |=
4655                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4656
4657                 CL22_WR_OVER_CL45(bp, phy,
4658                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4659                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4660                                   control2);
4661
4662                 /* Disable parallel detection of HiG */
4663                 CL22_WR_OVER_CL45(bp, phy,
4664                                   MDIO_REG_BANK_XGXS_BLOCK2,
4665                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4666                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4667                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4668         }
4669 }
4670
4671 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4672                               struct link_params *params,
4673                               struct link_vars *vars,
4674                               u8 enable_cl73)
4675 {
4676         struct bnx2x *bp = params->bp;
4677         u16 reg_val;
4678
4679         /* CL37 Autoneg */
4680         CL22_RD_OVER_CL45(bp, phy,
4681                           MDIO_REG_BANK_COMBO_IEEE0,
4682                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4683
4684         /* CL37 Autoneg Enabled */
4685         if (vars->line_speed == SPEED_AUTO_NEG)
4686                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4687         else /* CL37 Autoneg Disabled */
4688                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4689                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4690
4691         CL22_WR_OVER_CL45(bp, phy,
4692                           MDIO_REG_BANK_COMBO_IEEE0,
4693                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4694
4695         /* Enable/Disable Autodetection */
4696
4697         CL22_RD_OVER_CL45(bp, phy,
4698                           MDIO_REG_BANK_SERDES_DIGITAL,
4699                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4700         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4701                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4702         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4703         if (vars->line_speed == SPEED_AUTO_NEG)
4704                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4705         else
4706                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4707
4708         CL22_WR_OVER_CL45(bp, phy,
4709                           MDIO_REG_BANK_SERDES_DIGITAL,
4710                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4711
4712         /* Enable TetonII and BAM autoneg */
4713         CL22_RD_OVER_CL45(bp, phy,
4714                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4715                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4716                           &reg_val);
4717         if (vars->line_speed == SPEED_AUTO_NEG) {
4718                 /* Enable BAM aneg Mode and TetonII aneg Mode */
4719                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4720                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4721         } else {
4722                 /* TetonII and BAM Autoneg Disabled */
4723                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4724                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4725         }
4726         CL22_WR_OVER_CL45(bp, phy,
4727                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4728                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4729                           reg_val);
4730
4731         if (enable_cl73) {
4732                 /* Enable Cl73 FSM status bits */
4733                 CL22_WR_OVER_CL45(bp, phy,
4734                                   MDIO_REG_BANK_CL73_USERB0,
4735                                   MDIO_CL73_USERB0_CL73_UCTRL,
4736                                   0xe);
4737
4738                 /* Enable BAM Station Manager*/
4739                 CL22_WR_OVER_CL45(bp, phy,
4740                         MDIO_REG_BANK_CL73_USERB0,
4741                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4742                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4743                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4744                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4745
4746                 /* Advertise CL73 link speeds */
4747                 CL22_RD_OVER_CL45(bp, phy,
4748                                   MDIO_REG_BANK_CL73_IEEEB1,
4749                                   MDIO_CL73_IEEEB1_AN_ADV2,
4750                                   &reg_val);
4751                 if (phy->speed_cap_mask &
4752                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4753                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4754                 if (phy->speed_cap_mask &
4755                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4756                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4757
4758                 CL22_WR_OVER_CL45(bp, phy,
4759                                   MDIO_REG_BANK_CL73_IEEEB1,
4760                                   MDIO_CL73_IEEEB1_AN_ADV2,
4761                                   reg_val);
4762
4763                 /* CL73 Autoneg Enabled */
4764                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4765
4766         } else /* CL73 Autoneg Disabled */
4767                 reg_val = 0;
4768
4769         CL22_WR_OVER_CL45(bp, phy,
4770                           MDIO_REG_BANK_CL73_IEEEB0,
4771                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4772 }
4773
4774 /* program SerDes, forced speed */
4775 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4776                                  struct link_params *params,
4777                                  struct link_vars *vars)
4778 {
4779         struct bnx2x *bp = params->bp;
4780         u16 reg_val;
4781
4782         /* program duplex, disable autoneg and sgmii*/
4783         CL22_RD_OVER_CL45(bp, phy,
4784                           MDIO_REG_BANK_COMBO_IEEE0,
4785                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4786         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4787                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4788                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4789         if (phy->req_duplex == DUPLEX_FULL)
4790                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4791         CL22_WR_OVER_CL45(bp, phy,
4792                           MDIO_REG_BANK_COMBO_IEEE0,
4793                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4794
4795         /*
4796          * program speed
4797          *  - needed only if the speed is greater than 1G (2.5G or 10G)
4798          */
4799         CL22_RD_OVER_CL45(bp, phy,
4800                           MDIO_REG_BANK_SERDES_DIGITAL,
4801                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
4802         /* clearing the speed value before setting the right speed */
4803         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4804
4805         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4806                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4807
4808         if (!((vars->line_speed == SPEED_1000) ||
4809               (vars->line_speed == SPEED_100) ||
4810               (vars->line_speed == SPEED_10))) {
4811
4812                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4813                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4814                 if (vars->line_speed == SPEED_10000)
4815                         reg_val |=
4816                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4817         }
4818
4819         CL22_WR_OVER_CL45(bp, phy,
4820                           MDIO_REG_BANK_SERDES_DIGITAL,
4821                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
4822
4823 }
4824
4825 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
4826                                               struct link_params *params)
4827 {
4828         struct bnx2x *bp = params->bp;
4829         u16 val = 0;
4830
4831         /* configure the 48 bits for BAM AN */
4832
4833         /* set extended capabilities */
4834         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4835                 val |= MDIO_OVER_1G_UP1_2_5G;
4836         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4837                 val |= MDIO_OVER_1G_UP1_10G;
4838         CL22_WR_OVER_CL45(bp, phy,
4839                           MDIO_REG_BANK_OVER_1G,
4840                           MDIO_OVER_1G_UP1, val);
4841
4842         CL22_WR_OVER_CL45(bp, phy,
4843                           MDIO_REG_BANK_OVER_1G,
4844                           MDIO_OVER_1G_UP3, 0x400);
4845 }
4846
4847 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
4848                                               struct link_params *params,
4849                                               u16 ieee_fc)
4850 {
4851         struct bnx2x *bp = params->bp;
4852         u16 val;
4853         /* for AN, we are always publishing full duplex */
4854
4855         CL22_WR_OVER_CL45(bp, phy,
4856                           MDIO_REG_BANK_COMBO_IEEE0,
4857                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4858         CL22_RD_OVER_CL45(bp, phy,
4859                           MDIO_REG_BANK_CL73_IEEEB1,
4860                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
4861         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4862         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4863         CL22_WR_OVER_CL45(bp, phy,
4864                           MDIO_REG_BANK_CL73_IEEEB1,
4865                           MDIO_CL73_IEEEB1_AN_ADV1, val);
4866 }
4867
4868 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
4869                                   struct link_params *params,
4870                                   u8 enable_cl73)
4871 {
4872         struct bnx2x *bp = params->bp;
4873         u16 mii_control;
4874
4875         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
4876         /* Enable and restart BAM/CL37 aneg */
4877
4878         if (enable_cl73) {
4879                 CL22_RD_OVER_CL45(bp, phy,
4880                                   MDIO_REG_BANK_CL73_IEEEB0,
4881                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4882                                   &mii_control);
4883
4884                 CL22_WR_OVER_CL45(bp, phy,
4885                                   MDIO_REG_BANK_CL73_IEEEB0,
4886                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4887                                   (mii_control |
4888                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4889                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4890         } else {
4891
4892                 CL22_RD_OVER_CL45(bp, phy,
4893                                   MDIO_REG_BANK_COMBO_IEEE0,
4894                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4895                                   &mii_control);
4896                 DP(NETIF_MSG_LINK,
4897                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
4898                          mii_control);
4899                 CL22_WR_OVER_CL45(bp, phy,
4900                                   MDIO_REG_BANK_COMBO_IEEE0,
4901                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4902                                   (mii_control |
4903                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4904                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4905         }
4906 }
4907
4908 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
4909                                            struct link_params *params,
4910                                            struct link_vars *vars)
4911 {
4912         struct bnx2x *bp = params->bp;
4913         u16 control1;
4914
4915         /* in SGMII mode, the unicore is always slave */
4916
4917         CL22_RD_OVER_CL45(bp, phy,
4918                           MDIO_REG_BANK_SERDES_DIGITAL,
4919                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4920                           &control1);
4921         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4922         /* set sgmii mode (and not fiber) */
4923         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4924                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4925                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4926         CL22_WR_OVER_CL45(bp, phy,
4927                           MDIO_REG_BANK_SERDES_DIGITAL,
4928                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4929                           control1);
4930
4931         /* if forced speed */
4932         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
4933                 /* set speed, disable autoneg */
4934                 u16 mii_control;
4935
4936                 CL22_RD_OVER_CL45(bp, phy,
4937                                   MDIO_REG_BANK_COMBO_IEEE0,
4938                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4939                                   &mii_control);
4940                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4941                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
4942                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4943
4944                 switch (vars->line_speed) {
4945                 case SPEED_100:
4946                         mii_control |=
4947                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4948                         break;
4949                 case SPEED_1000:
4950                         mii_control |=
4951                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4952                         break;
4953                 case SPEED_10:
4954                         /* there is nothing to set for 10M */
4955                         break;
4956                 default:
4957                         /* invalid speed for SGMII */
4958                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
4959                                   vars->line_speed);
4960                         break;
4961                 }
4962
4963                 /* setting the full duplex */
4964                 if (phy->req_duplex == DUPLEX_FULL)
4965                         mii_control |=
4966                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4967                 CL22_WR_OVER_CL45(bp, phy,
4968                                   MDIO_REG_BANK_COMBO_IEEE0,
4969                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4970                                   mii_control);
4971
4972         } else { /* AN mode */
4973                 /* enable and restart AN */
4974                 bnx2x_restart_autoneg(phy, params, 0);
4975         }
4976 }
4977
4978
4979 /*
4980  * link management
4981  */
4982
4983 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
4984                                              struct link_params *params)
4985 {
4986         struct bnx2x *bp = params->bp;
4987         u16 pd_10g, status2_1000x;
4988         if (phy->req_line_speed != SPEED_AUTO_NEG)
4989                 return 0;
4990         CL22_RD_OVER_CL45(bp, phy,
4991                           MDIO_REG_BANK_SERDES_DIGITAL,
4992                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4993                           &status2_1000x);
4994         CL22_RD_OVER_CL45(bp, phy,
4995                           MDIO_REG_BANK_SERDES_DIGITAL,
4996                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4997                           &status2_1000x);
4998         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4999                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5000                          params->port);
5001                 return 1;
5002         }
5003
5004         CL22_RD_OVER_CL45(bp, phy,
5005                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5006                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5007                           &pd_10g);
5008
5009         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5010                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5011                          params->port);
5012                 return 1;
5013         }
5014         return 0;
5015 }
5016
5017 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5018                                     struct link_params *params,
5019                                     struct link_vars *vars,
5020                                     u32 gp_status)
5021 {
5022         struct bnx2x *bp = params->bp;
5023         u16 ld_pause;   /* local driver */
5024         u16 lp_pause;   /* link partner */
5025         u16 pause_result;
5026
5027         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5028
5029         /* resolve from gp_status in case of AN complete and not sgmii */
5030         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
5031                 vars->flow_ctrl = phy->req_flow_ctrl;
5032         else if (phy->req_line_speed != SPEED_AUTO_NEG)
5033                 vars->flow_ctrl = params->req_fc_auto_adv;
5034         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5035                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5036                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5037                         vars->flow_ctrl = params->req_fc_auto_adv;
5038                         return;
5039                 }
5040                 if ((gp_status &
5041                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5042                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5043                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5044                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5045
5046                         CL22_RD_OVER_CL45(bp, phy,
5047                                           MDIO_REG_BANK_CL73_IEEEB1,
5048                                           MDIO_CL73_IEEEB1_AN_ADV1,
5049                                           &ld_pause);
5050                         CL22_RD_OVER_CL45(bp, phy,
5051                                           MDIO_REG_BANK_CL73_IEEEB1,
5052                                           MDIO_CL73_IEEEB1_AN_LP_ADV1,
5053                                           &lp_pause);
5054                         pause_result = (ld_pause &
5055                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5056                                         >> 8;
5057                         pause_result |= (lp_pause &
5058                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5059                                         >> 10;
5060                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5061                                  pause_result);
5062                 } else {
5063                         CL22_RD_OVER_CL45(bp, phy,
5064                                           MDIO_REG_BANK_COMBO_IEEE0,
5065                                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5066                                           &ld_pause);
5067                         CL22_RD_OVER_CL45(bp, phy,
5068                                 MDIO_REG_BANK_COMBO_IEEE0,
5069                                 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5070                                 &lp_pause);
5071                         pause_result = (ld_pause &
5072                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5073                         pause_result |= (lp_pause &
5074                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5075                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5076                                  pause_result);
5077                 }
5078                 bnx2x_pause_resolve(vars, pause_result);
5079         }
5080         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5081 }
5082
5083 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5084                                          struct link_params *params)
5085 {
5086         struct bnx2x *bp = params->bp;
5087         u16 rx_status, ustat_val, cl37_fsm_received;
5088         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5089         /* Step 1: Make sure signal is detected */
5090         CL22_RD_OVER_CL45(bp, phy,
5091                           MDIO_REG_BANK_RX0,
5092                           MDIO_RX0_RX_STATUS,
5093                           &rx_status);
5094         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5095             (MDIO_RX0_RX_STATUS_SIGDET)) {
5096                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5097                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5098                 CL22_WR_OVER_CL45(bp, phy,
5099                                   MDIO_REG_BANK_CL73_IEEEB0,
5100                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5101                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5102                 return;
5103         }
5104         /* Step 2: Check CL73 state machine */
5105         CL22_RD_OVER_CL45(bp, phy,
5106                           MDIO_REG_BANK_CL73_USERB0,
5107                           MDIO_CL73_USERB0_CL73_USTAT1,
5108                           &ustat_val);
5109         if ((ustat_val &
5110              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5111               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5112             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5113               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5114                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5115                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5116                 return;
5117         }
5118         /*
5119          * Step 3: Check CL37 Message Pages received to indicate LP
5120          * supports only CL37
5121          */
5122         CL22_RD_OVER_CL45(bp, phy,
5123                           MDIO_REG_BANK_REMOTE_PHY,
5124                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5125                           &cl37_fsm_received);
5126         if ((cl37_fsm_received &
5127              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5128              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5129             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5130               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5131                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5132                              "misc_rx_status(0x8330) = 0x%x\n",
5133                          cl37_fsm_received);
5134                 return;
5135         }
5136         /*
5137          * The combined cl37/cl73 fsm state information indicating that
5138          * we are connected to a device which does not support cl73, but
5139          * does support cl37 BAM. In this case we disable cl73 and
5140          * restart cl37 auto-neg
5141          */
5142
5143         /* Disable CL73 */
5144         CL22_WR_OVER_CL45(bp, phy,
5145                           MDIO_REG_BANK_CL73_IEEEB0,
5146                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5147                           0);
5148         /* Restart CL37 autoneg */
5149         bnx2x_restart_autoneg(phy, params, 0);
5150         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5151 }
5152
5153 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5154                                   struct link_params *params,
5155                                   struct link_vars *vars,
5156                                   u32 gp_status)
5157 {
5158         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5159                 vars->link_status |=
5160                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5161
5162         if (bnx2x_direct_parallel_detect_used(phy, params))
5163                 vars->link_status |=
5164                         LINK_STATUS_PARALLEL_DETECTION_USED;
5165 }
5166 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5167                                      struct link_params *params,
5168                                       struct link_vars *vars,
5169                                       u16 is_link_up,
5170                                       u16 speed_mask,
5171                                       u16 is_duplex)
5172 {
5173         struct bnx2x *bp = params->bp;
5174         if (phy->req_line_speed == SPEED_AUTO_NEG)
5175                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5176         if (is_link_up) {
5177                 DP(NETIF_MSG_LINK, "phy link up\n");
5178
5179                 vars->phy_link_up = 1;
5180                 vars->link_status |= LINK_STATUS_LINK_UP;
5181
5182                 switch (speed_mask) {
5183                 case GP_STATUS_10M:
5184                         vars->line_speed = SPEED_10;
5185                         if (vars->duplex == DUPLEX_FULL)
5186                                 vars->link_status |= LINK_10TFD;
5187                         else
5188                                 vars->link_status |= LINK_10THD;
5189                         break;
5190
5191                 case GP_STATUS_100M:
5192                         vars->line_speed = SPEED_100;
5193                         if (vars->duplex == DUPLEX_FULL)
5194                                 vars->link_status |= LINK_100TXFD;
5195                         else
5196                                 vars->link_status |= LINK_100TXHD;
5197                         break;
5198
5199                 case GP_STATUS_1G:
5200                 case GP_STATUS_1G_KX:
5201                         vars->line_speed = SPEED_1000;
5202                         if (vars->duplex == DUPLEX_FULL)
5203                                 vars->link_status |= LINK_1000TFD;
5204                         else
5205                                 vars->link_status |= LINK_1000THD;
5206                         break;
5207
5208                 case GP_STATUS_2_5G:
5209                         vars->line_speed = SPEED_2500;
5210                         if (vars->duplex == DUPLEX_FULL)
5211                                 vars->link_status |= LINK_2500TFD;
5212                         else
5213                                 vars->link_status |= LINK_2500THD;
5214                         break;
5215
5216                 case GP_STATUS_5G:
5217                 case GP_STATUS_6G:
5218                         DP(NETIF_MSG_LINK,
5219                                  "link speed unsupported  gp_status 0x%x\n",
5220                                   speed_mask);
5221                         return -EINVAL;
5222
5223                 case GP_STATUS_10G_KX4:
5224                 case GP_STATUS_10G_HIG:
5225                 case GP_STATUS_10G_CX4:
5226                 case GP_STATUS_10G_KR:
5227                 case GP_STATUS_10G_SFI:
5228                 case GP_STATUS_10G_XFI:
5229                         vars->line_speed = SPEED_10000;
5230                         vars->link_status |= LINK_10GTFD;
5231                         break;
5232                 case GP_STATUS_20G_DXGXS:
5233                         vars->line_speed = SPEED_20000;
5234                         vars->link_status |= LINK_20GTFD;
5235                         break;
5236                 default:
5237                         DP(NETIF_MSG_LINK,
5238                                   "link speed unsupported gp_status 0x%x\n",
5239                                   speed_mask);
5240                         return -EINVAL;
5241                 }
5242         } else { /* link_down */
5243                 DP(NETIF_MSG_LINK, "phy link down\n");
5244
5245                 vars->phy_link_up = 0;
5246
5247                 vars->duplex = DUPLEX_FULL;
5248                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5249                 vars->mac_type = MAC_TYPE_NONE;
5250         }
5251         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5252                     vars->phy_link_up, vars->line_speed);
5253         return 0;
5254 }
5255
5256 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5257                                       struct link_params *params,
5258                                       struct link_vars *vars)
5259 {
5260
5261         struct bnx2x *bp = params->bp;
5262
5263         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5264         int rc = 0;
5265
5266         /* Read gp_status */
5267         CL22_RD_OVER_CL45(bp, phy,
5268                           MDIO_REG_BANK_GP_STATUS,
5269                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5270                           &gp_status);
5271         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5272                 duplex = DUPLEX_FULL;
5273         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5274                 link_up = 1;
5275         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5276         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5277                        gp_status, link_up, speed_mask);
5278         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5279                                          duplex);
5280         if (rc == -EINVAL)
5281                 return rc;
5282
5283         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5284                 if (SINGLE_MEDIA_DIRECT(params)) {
5285                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5286                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5287                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5288                                                       gp_status);
5289                 }
5290         } else { /* link_down */
5291                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5292                     SINGLE_MEDIA_DIRECT(params)) {
5293                         /* Check signal is detected */
5294                         bnx2x_check_fallback_to_cl37(phy, params);
5295                 }
5296         }
5297
5298         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5299                    vars->duplex, vars->flow_ctrl, vars->link_status);
5300         return rc;
5301 }
5302
5303 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5304                                      struct link_params *params,
5305                                      struct link_vars *vars)
5306 {
5307
5308         struct bnx2x *bp = params->bp;
5309
5310         u8 lane;
5311         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5312         int rc = 0;
5313         lane = bnx2x_get_warpcore_lane(phy, params);
5314         /* Read gp_status */
5315         if (phy->req_line_speed > SPEED_10000) {
5316                 u16 temp_link_up;
5317                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5318                                 1, &temp_link_up);
5319                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5320                                 1, &link_up);
5321                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5322                                temp_link_up, link_up);
5323                 link_up &= (1<<2);
5324                 if (link_up)
5325                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5326         } else {
5327                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5328                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5329                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5330                 /* Check for either KR or generic link up. */
5331                 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5332                         ((gp_status1 >> 12) & 0xf);
5333                 link_up = gp_status1 & (1 << lane);
5334                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5335                         u16 pd, gp_status4;
5336                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5337                                 /* Check Autoneg complete */
5338                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5339                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5340                                                 &gp_status4);
5341                                 if (gp_status4 & ((1<<12)<<lane))
5342                                         vars->link_status |=
5343                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5344
5345                                 /* Check parallel detect used */
5346                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5347                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5348                                                 &pd);
5349                                 if (pd & (1<<15))
5350                                         vars->link_status |=
5351                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5352                         }
5353                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5354                 }
5355         }
5356
5357         if (lane < 2) {
5358                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5359                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5360         } else {
5361                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5362                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5363         }
5364         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5365
5366         if ((lane & 1) == 0)
5367                 gp_speed <<= 8;
5368         gp_speed &= 0x3f00;
5369
5370
5371         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5372                                          duplex);
5373
5374         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5375                    vars->duplex, vars->flow_ctrl, vars->link_status);
5376         return rc;
5377 }
5378 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5379 {
5380         struct bnx2x *bp = params->bp;
5381         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5382         u16 lp_up2;
5383         u16 tx_driver;
5384         u16 bank;
5385
5386         /* read precomp */
5387         CL22_RD_OVER_CL45(bp, phy,
5388                           MDIO_REG_BANK_OVER_1G,
5389                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5390
5391         /* bits [10:7] at lp_up2, positioned at [15:12] */
5392         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5393                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5394                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5395
5396         if (lp_up2 == 0)
5397                 return;
5398
5399         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5400               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5401                 CL22_RD_OVER_CL45(bp, phy,
5402                                   bank,
5403                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5404
5405                 /* replace tx_driver bits [15:12] */
5406                 if (lp_up2 !=
5407                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5408                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5409                         tx_driver |= lp_up2;
5410                         CL22_WR_OVER_CL45(bp, phy,
5411                                           bank,
5412                                           MDIO_TX0_TX_DRIVER, tx_driver);
5413                 }
5414         }
5415 }
5416
5417 static int bnx2x_emac_program(struct link_params *params,
5418                               struct link_vars *vars)
5419 {
5420         struct bnx2x *bp = params->bp;
5421         u8 port = params->port;
5422         u16 mode = 0;
5423
5424         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5425         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5426                        EMAC_REG_EMAC_MODE,
5427                        (EMAC_MODE_25G_MODE |
5428                         EMAC_MODE_PORT_MII_10M |
5429                         EMAC_MODE_HALF_DUPLEX));
5430         switch (vars->line_speed) {
5431         case SPEED_10:
5432                 mode |= EMAC_MODE_PORT_MII_10M;
5433                 break;
5434
5435         case SPEED_100:
5436                 mode |= EMAC_MODE_PORT_MII;
5437                 break;
5438
5439         case SPEED_1000:
5440                 mode |= EMAC_MODE_PORT_GMII;
5441                 break;
5442
5443         case SPEED_2500:
5444                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5445                 break;
5446
5447         default:
5448                 /* 10G not valid for EMAC */
5449                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5450                            vars->line_speed);
5451                 return -EINVAL;
5452         }
5453
5454         if (vars->duplex == DUPLEX_HALF)
5455                 mode |= EMAC_MODE_HALF_DUPLEX;
5456         bnx2x_bits_en(bp,
5457                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5458                       mode);
5459
5460         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5461         return 0;
5462 }
5463
5464 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5465                                   struct link_params *params)
5466 {
5467
5468         u16 bank, i = 0;
5469         struct bnx2x *bp = params->bp;
5470
5471         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5472               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5473                         CL22_WR_OVER_CL45(bp, phy,
5474                                           bank,
5475                                           MDIO_RX0_RX_EQ_BOOST,
5476                                           phy->rx_preemphasis[i]);
5477         }
5478
5479         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5480                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5481                         CL22_WR_OVER_CL45(bp, phy,
5482                                           bank,
5483                                           MDIO_TX0_TX_DRIVER,
5484                                           phy->tx_preemphasis[i]);
5485         }
5486 }
5487
5488 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5489                                    struct link_params *params,
5490                                    struct link_vars *vars)
5491 {
5492         struct bnx2x *bp = params->bp;
5493         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5494                           (params->loopback_mode == LOOPBACK_XGXS));
5495         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5496                 if (SINGLE_MEDIA_DIRECT(params) &&
5497                     (params->feature_config_flags &
5498                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5499                         bnx2x_set_preemphasis(phy, params);
5500
5501                 /* forced speed requested? */
5502                 if (vars->line_speed != SPEED_AUTO_NEG ||
5503                     (SINGLE_MEDIA_DIRECT(params) &&
5504                      params->loopback_mode == LOOPBACK_EXT)) {
5505                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5506
5507                         /* disable autoneg */
5508                         bnx2x_set_autoneg(phy, params, vars, 0);
5509
5510                         /* program speed and duplex */
5511                         bnx2x_program_serdes(phy, params, vars);
5512
5513                 } else { /* AN_mode */
5514                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5515
5516                         /* AN enabled */
5517                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5518
5519                         /* program duplex & pause advertisement (for aneg) */
5520                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5521                                                           vars->ieee_fc);
5522
5523                         /* enable autoneg */
5524                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5525
5526                         /* enable and restart AN */
5527                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5528                 }
5529
5530         } else { /* SGMII mode */
5531                 DP(NETIF_MSG_LINK, "SGMII\n");
5532
5533                 bnx2x_initialize_sgmii_process(phy, params, vars);
5534         }
5535 }
5536
5537 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5538                           struct link_params *params,
5539                           struct link_vars *vars)
5540 {
5541         int rc;
5542         vars->phy_flags |= PHY_XGXS_FLAG;
5543         if ((phy->req_line_speed &&
5544              ((phy->req_line_speed == SPEED_100) ||
5545               (phy->req_line_speed == SPEED_10))) ||
5546             (!phy->req_line_speed &&
5547              (phy->speed_cap_mask >=
5548               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5549              (phy->speed_cap_mask <
5550               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5551             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5552                 vars->phy_flags |= PHY_SGMII_FLAG;
5553         else
5554                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5555
5556         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5557         bnx2x_set_aer_mmd(params, phy);
5558         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5559                 bnx2x_set_master_ln(params, phy);
5560
5561         rc = bnx2x_reset_unicore(params, phy, 0);
5562         /* reset the SerDes and wait for reset bit return low */
5563         if (rc != 0)
5564                 return rc;
5565
5566         bnx2x_set_aer_mmd(params, phy);
5567         /* setting the masterLn_def again after the reset */
5568         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5569                 bnx2x_set_master_ln(params, phy);
5570                 bnx2x_set_swap_lanes(params, phy);
5571         }
5572
5573         return rc;
5574 }
5575
5576 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5577                                      struct bnx2x_phy *phy,
5578                                      struct link_params *params)
5579 {
5580         u16 cnt, ctrl;
5581         /* Wait for soft reset to get cleared up to 1 sec */
5582         for (cnt = 0; cnt < 1000; cnt++) {
5583                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5584                         bnx2x_cl22_read(bp, phy,
5585                                 MDIO_PMA_REG_CTRL, &ctrl);
5586                 else
5587                         bnx2x_cl45_read(bp, phy,
5588                                 MDIO_PMA_DEVAD,
5589                                 MDIO_PMA_REG_CTRL, &ctrl);
5590                 if (!(ctrl & (1<<15)))
5591                         break;
5592                 msleep(1);
5593         }
5594
5595         if (cnt == 1000)
5596                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5597                                       " Port %d\n",
5598                          params->port);
5599         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5600         return cnt;
5601 }
5602
5603 static void bnx2x_link_int_enable(struct link_params *params)
5604 {
5605         u8 port = params->port;
5606         u32 mask;
5607         struct bnx2x *bp = params->bp;
5608
5609         /* Setting the status to report on link up for either XGXS or SerDes */
5610         if (CHIP_IS_E3(bp)) {
5611                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5612                 if (!(SINGLE_MEDIA_DIRECT(params)))
5613                         mask |= NIG_MASK_MI_INT;
5614         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5615                 mask = (NIG_MASK_XGXS0_LINK10G |
5616                         NIG_MASK_XGXS0_LINK_STATUS);
5617                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5618                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5619                         params->phy[INT_PHY].type !=
5620                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5621                         mask |= NIG_MASK_MI_INT;
5622                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5623                 }
5624
5625         } else { /* SerDes */
5626                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5627                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5628                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5629                         params->phy[INT_PHY].type !=
5630                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5631                         mask |= NIG_MASK_MI_INT;
5632                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5633                 }
5634         }
5635         bnx2x_bits_en(bp,
5636                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5637                       mask);
5638
5639         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5640                  (params->switch_cfg == SWITCH_CFG_10G),
5641                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5642         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5643                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5644                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5645                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5646         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5647            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5648            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5649 }
5650
5651 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5652                                      u8 exp_mi_int)
5653 {
5654         u32 latch_status = 0;
5655
5656         /*
5657          * Disable the MI INT ( external phy int ) by writing 1 to the
5658          * status register. Link down indication is high-active-signal,
5659          * so in this case we need to write the status to clear the XOR
5660          */
5661         /* Read Latched signals */
5662         latch_status = REG_RD(bp,
5663                                     NIG_REG_LATCH_STATUS_0 + port*8);
5664         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5665         /* Handle only those with latched-signal=up.*/
5666         if (exp_mi_int)
5667                 bnx2x_bits_en(bp,
5668                               NIG_REG_STATUS_INTERRUPT_PORT0
5669                               + port*4,
5670                               NIG_STATUS_EMAC0_MI_INT);
5671         else
5672                 bnx2x_bits_dis(bp,
5673                                NIG_REG_STATUS_INTERRUPT_PORT0
5674                                + port*4,
5675                                NIG_STATUS_EMAC0_MI_INT);
5676
5677         if (latch_status & 1) {
5678
5679                 /* For all latched-signal=up : Re-Arm Latch signals */
5680                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5681                        (latch_status & 0xfffe) | (latch_status & 1));
5682         }
5683         /* For all latched-signal=up,Write original_signal to status */
5684 }
5685
5686 static void bnx2x_link_int_ack(struct link_params *params,
5687                                struct link_vars *vars, u8 is_10g_plus)
5688 {
5689         struct bnx2x *bp = params->bp;
5690         u8 port = params->port;
5691         u32 mask;
5692         /*
5693          * First reset all status we assume only one line will be
5694          * change at a time
5695          */
5696         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5697                        (NIG_STATUS_XGXS0_LINK10G |
5698                         NIG_STATUS_XGXS0_LINK_STATUS |
5699                         NIG_STATUS_SERDES0_LINK_STATUS));
5700         if (vars->phy_link_up) {
5701                 if (USES_WARPCORE(bp))
5702                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
5703                 else {
5704                         if (is_10g_plus)
5705                                 mask = NIG_STATUS_XGXS0_LINK10G;
5706                         else if (params->switch_cfg == SWITCH_CFG_10G) {
5707                                 /*
5708                                  * Disable the link interrupt by writing 1 to
5709                                  * the relevant lane in the status register
5710                                  */
5711                                 u32 ser_lane =
5712                                         ((params->lane_config &
5713                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5714                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5715                                 mask = ((1 << ser_lane) <<
5716                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5717                         } else
5718                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5719                 }
5720                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5721                                mask);
5722                 bnx2x_bits_en(bp,
5723                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5724                               mask);
5725         }
5726 }
5727
5728 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5729 {
5730         u8 *str_ptr = str;
5731         u32 mask = 0xf0000000;
5732         u8 shift = 8*4;
5733         u8 digit;
5734         u8 remove_leading_zeros = 1;
5735         if (*len < 10) {
5736                 /* Need more than 10chars for this format */
5737                 *str_ptr = '\0';
5738                 (*len)--;
5739                 return -EINVAL;
5740         }
5741         while (shift > 0) {
5742
5743                 shift -= 4;
5744                 digit = ((num & mask) >> shift);
5745                 if (digit == 0 && remove_leading_zeros) {
5746                         mask = mask >> 4;
5747                         continue;
5748                 } else if (digit < 0xa)
5749                         *str_ptr = digit + '0';
5750                 else
5751                         *str_ptr = digit - 0xa + 'a';
5752                 remove_leading_zeros = 0;
5753                 str_ptr++;
5754                 (*len)--;
5755                 mask = mask >> 4;
5756                 if (shift == 4*4) {
5757                         *str_ptr = '.';
5758                         str_ptr++;
5759                         (*len)--;
5760                         remove_leading_zeros = 1;
5761                 }
5762         }
5763         return 0;
5764 }
5765
5766
5767 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5768 {
5769         str[0] = '\0';
5770         (*len)--;
5771         return 0;
5772 }
5773
5774 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5775                                  u8 *version, u16 len)
5776 {
5777         struct bnx2x *bp;
5778         u32 spirom_ver = 0;
5779         int status = 0;
5780         u8 *ver_p = version;
5781         u16 remain_len = len;
5782         if (version == NULL || params == NULL)
5783                 return -EINVAL;
5784         bp = params->bp;
5785
5786         /* Extract first external phy*/
5787         version[0] = '\0';
5788         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5789
5790         if (params->phy[EXT_PHY1].format_fw_ver) {
5791                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5792                                                               ver_p,
5793                                                               &remain_len);
5794                 ver_p += (len - remain_len);
5795         }
5796         if ((params->num_phys == MAX_PHYS) &&
5797             (params->phy[EXT_PHY2].ver_addr != 0)) {
5798                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5799                 if (params->phy[EXT_PHY2].format_fw_ver) {
5800                         *ver_p = '/';
5801                         ver_p++;
5802                         remain_len--;
5803                         status |= params->phy[EXT_PHY2].format_fw_ver(
5804                                 spirom_ver,
5805                                 ver_p,
5806                                 &remain_len);
5807                         ver_p = version + (len - remain_len);
5808                 }
5809         }
5810         *ver_p = '\0';
5811         return status;
5812 }
5813
5814 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5815                                     struct link_params *params)
5816 {
5817         u8 port = params->port;
5818         struct bnx2x *bp = params->bp;
5819
5820         if (phy->req_line_speed != SPEED_1000) {
5821                 u32 md_devad = 0;
5822
5823                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5824
5825                 if (!CHIP_IS_E3(bp)) {
5826                         /* change the uni_phy_addr in the nig */
5827                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5828                                                port*0x18));
5829
5830                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5831                                0x5);
5832                 }
5833
5834                 bnx2x_cl45_write(bp, phy,
5835                                  5,
5836                                  (MDIO_REG_BANK_AER_BLOCK +
5837                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
5838                                  0x2800);
5839
5840                 bnx2x_cl45_write(bp, phy,
5841                                  5,
5842                                  (MDIO_REG_BANK_CL73_IEEEB0 +
5843                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5844                                  0x6041);
5845                 msleep(200);
5846                 /* set aer mmd back */
5847                 bnx2x_set_aer_mmd(params, phy);
5848
5849                 if (!CHIP_IS_E3(bp)) {
5850                         /* and md_devad */
5851                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5852                                md_devad);
5853                 }
5854         } else {
5855                 u16 mii_ctrl;
5856                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5857                 bnx2x_cl45_read(bp, phy, 5,
5858                                 (MDIO_REG_BANK_COMBO_IEEE0 +
5859                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5860                                 &mii_ctrl);
5861                 bnx2x_cl45_write(bp, phy, 5,
5862                                  (MDIO_REG_BANK_COMBO_IEEE0 +
5863                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5864                                  mii_ctrl |
5865                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5866         }
5867 }
5868
5869 int bnx2x_set_led(struct link_params *params,
5870                   struct link_vars *vars, u8 mode, u32 speed)
5871 {
5872         u8 port = params->port;
5873         u16 hw_led_mode = params->hw_led_mode;
5874         int rc = 0;
5875         u8 phy_idx;
5876         u32 tmp;
5877         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5878         struct bnx2x *bp = params->bp;
5879         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5880         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5881                  speed, hw_led_mode);
5882         /* In case */
5883         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
5884                 if (params->phy[phy_idx].set_link_led) {
5885                         params->phy[phy_idx].set_link_led(
5886                                 &params->phy[phy_idx], params, mode);
5887                 }
5888         }
5889
5890         switch (mode) {
5891         case LED_MODE_FRONT_PANEL_OFF:
5892         case LED_MODE_OFF:
5893                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5894                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5895                        SHARED_HW_CFG_LED_MAC1);
5896
5897                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5898                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5899                 break;
5900
5901         case LED_MODE_OPER:
5902                 /*
5903                  * For all other phys, OPER mode is same as ON, so in case
5904                  * link is down, do nothing
5905                  */
5906                 if (!vars->link_up)
5907                         break;
5908         case LED_MODE_ON:
5909                 if (((params->phy[EXT_PHY1].type ==
5910                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
5911                          (params->phy[EXT_PHY1].type ==
5912                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
5913                     CHIP_IS_E2(bp) && params->num_phys == 2) {
5914                         /*
5915                          * This is a work-around for E2+8727 Configurations
5916                          */
5917                         if (mode == LED_MODE_ON ||
5918                                 speed == SPEED_10000){
5919                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5920                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5921
5922                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5923                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5924                                         (tmp | EMAC_LED_OVERRIDE));
5925                                 /*
5926                                  * return here without enabling traffic
5927                                  * LED blink andsetting rate in ON mode.
5928                                  * In oper mode, enabling LED blink
5929                                  * and setting rate is needed.
5930                                  */
5931                                 if (mode == LED_MODE_ON)
5932                                         return rc;
5933                         }
5934                 } else if (SINGLE_MEDIA_DIRECT(params)) {
5935                         /*
5936                          * This is a work-around for HW issue found when link
5937                          * is up in CL73
5938                          */
5939                         REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5940                         if (CHIP_IS_E1x(bp) ||
5941                             CHIP_IS_E2(bp) ||
5942                             (mode == LED_MODE_ON))
5943                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5944                         else
5945                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5946                                        hw_led_mode);
5947                 } else
5948                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5949
5950                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
5951                 /* Set blinking rate to ~15.9Hz */
5952                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5953                        LED_BLINK_RATE_VAL);
5954                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5955                        port*4, 1);
5956                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5957                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
5958
5959                 if (CHIP_IS_E1(bp) &&
5960                     ((speed == SPEED_2500) ||
5961                      (speed == SPEED_1000) ||
5962                      (speed == SPEED_100) ||
5963                      (speed == SPEED_10))) {
5964                         /*
5965                          * On Everest 1 Ax chip versions for speeds less than
5966                          * 10G LED scheme is different
5967                          */
5968                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5969                                + port*4, 1);
5970                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5971                                port*4, 0);
5972                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5973                                port*4, 1);
5974                 }
5975                 break;
5976
5977         default:
5978                 rc = -EINVAL;
5979                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5980                          mode);
5981                 break;
5982         }
5983         return rc;
5984
5985 }
5986
5987 /*
5988  * This function comes to reflect the actual link state read DIRECTLY from the
5989  * HW
5990  */
5991 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
5992                     u8 is_serdes)
5993 {
5994         struct bnx2x *bp = params->bp;
5995         u16 gp_status = 0, phy_index = 0;
5996         u8 ext_phy_link_up = 0, serdes_phy_type;
5997         struct link_vars temp_vars;
5998         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
5999
6000         if (CHIP_IS_E3(bp)) {
6001                 u16 link_up;
6002                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6003                     > SPEED_10000) {
6004                         /* Check 20G link */
6005                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6006                                         1, &link_up);
6007                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6008                                         1, &link_up);
6009                         link_up &= (1<<2);
6010                 } else {
6011                         /* Check 10G link and below*/
6012                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6013                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6014                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6015                                         &gp_status);
6016                         gp_status = ((gp_status >> 8) & 0xf) |
6017                                 ((gp_status >> 12) & 0xf);
6018                         link_up = gp_status & (1 << lane);
6019                 }
6020                 if (!link_up)
6021                         return -ESRCH;
6022         } else {
6023                 CL22_RD_OVER_CL45(bp, int_phy,
6024                           MDIO_REG_BANK_GP_STATUS,
6025                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6026                           &gp_status);
6027         /* link is up only if both local phy and external phy are up */
6028         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6029                 return -ESRCH;
6030         }
6031         /* In XGXS loopback mode, do not check external PHY */
6032         if (params->loopback_mode == LOOPBACK_XGXS)
6033                 return 0;
6034
6035         switch (params->num_phys) {
6036         case 1:
6037                 /* No external PHY */
6038                 return 0;
6039         case 2:
6040                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6041                         &params->phy[EXT_PHY1],
6042                         params, &temp_vars);
6043                 break;
6044         case 3: /* Dual Media */
6045                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6046                       phy_index++) {
6047                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6048                                             ETH_PHY_SFP_FIBER) ||
6049                                            (params->phy[phy_index].media_type ==
6050                                             ETH_PHY_XFP_FIBER) ||
6051                                            (params->phy[phy_index].media_type ==
6052                                             ETH_PHY_DA_TWINAX));
6053
6054                         if (is_serdes != serdes_phy_type)
6055                                 continue;
6056                         if (params->phy[phy_index].read_status) {
6057                                 ext_phy_link_up |=
6058                                         params->phy[phy_index].read_status(
6059                                                 &params->phy[phy_index],
6060                                                 params, &temp_vars);
6061                         }
6062                 }
6063                 break;
6064         }
6065         if (ext_phy_link_up)
6066                 return 0;
6067         return -ESRCH;
6068 }
6069
6070 static int bnx2x_link_initialize(struct link_params *params,
6071                                  struct link_vars *vars)
6072 {
6073         int rc = 0;
6074         u8 phy_index, non_ext_phy;
6075         struct bnx2x *bp = params->bp;
6076         /*
6077          * In case of external phy existence, the line speed would be the
6078          * line speed linked up by the external phy. In case it is direct
6079          * only, then the line_speed during initialization will be
6080          * equal to the req_line_speed
6081          */
6082         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6083
6084         /*
6085          * Initialize the internal phy in case this is a direct board
6086          * (no external phys), or this board has external phy which requires
6087          * to first.
6088          */
6089         if (!USES_WARPCORE(bp))
6090                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6091         /* init ext phy and enable link state int */
6092         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6093                        (params->loopback_mode == LOOPBACK_XGXS));
6094
6095         if (non_ext_phy ||
6096             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6097             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6098                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6099                 if (vars->line_speed == SPEED_AUTO_NEG &&
6100                     (CHIP_IS_E1x(bp) ||
6101                      CHIP_IS_E2(bp)))
6102                         bnx2x_set_parallel_detection(phy, params);
6103                         if (params->phy[INT_PHY].config_init)
6104                                 params->phy[INT_PHY].config_init(phy,
6105                                                                  params,
6106                                                                  vars);
6107         }
6108
6109         /* Init external phy*/
6110         if (non_ext_phy) {
6111                 if (params->phy[INT_PHY].supported &
6112                     SUPPORTED_FIBRE)
6113                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6114         } else {
6115                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6116                       phy_index++) {
6117                         /*
6118                          * No need to initialize second phy in case of first
6119                          * phy only selection. In case of second phy, we do
6120                          * need to initialize the first phy, since they are
6121                          * connected.
6122                          */
6123                         if (params->phy[phy_index].supported &
6124                             SUPPORTED_FIBRE)
6125                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6126
6127                         if (phy_index == EXT_PHY2 &&
6128                             (bnx2x_phy_selection(params) ==
6129                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6130                                 DP(NETIF_MSG_LINK, "Not initializing"
6131                                                 " second phy\n");
6132                                 continue;
6133                         }
6134                         params->phy[phy_index].config_init(
6135                                 &params->phy[phy_index],
6136                                 params, vars);
6137                 }
6138         }
6139         /* Reset the interrupt indication after phy was initialized */
6140         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6141                        params->port*4,
6142                        (NIG_STATUS_XGXS0_LINK10G |
6143                         NIG_STATUS_XGXS0_LINK_STATUS |
6144                         NIG_STATUS_SERDES0_LINK_STATUS |
6145                         NIG_MASK_MI_INT));
6146         bnx2x_update_mng(params, vars->link_status);
6147         return rc;
6148 }
6149
6150 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6151                                  struct link_params *params)
6152 {
6153         /* reset the SerDes/XGXS */
6154         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6155                (0x1ff << (params->port*16)));
6156 }
6157
6158 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6159                                         struct link_params *params)
6160 {
6161         struct bnx2x *bp = params->bp;
6162         u8 gpio_port;
6163         /* HW reset */
6164         if (CHIP_IS_E2(bp))
6165                 gpio_port = BP_PATH(bp);
6166         else
6167                 gpio_port = params->port;
6168         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6169                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6170                        gpio_port);
6171         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6172                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6173                        gpio_port);
6174         DP(NETIF_MSG_LINK, "reset external PHY\n");
6175 }
6176
6177 static int bnx2x_update_link_down(struct link_params *params,
6178                                   struct link_vars *vars)
6179 {
6180         struct bnx2x *bp = params->bp;
6181         u8 port = params->port;
6182
6183         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6184         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6185         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6186         /* indicate no mac active */
6187         vars->mac_type = MAC_TYPE_NONE;
6188
6189         /* update shared memory */
6190         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6191                                LINK_STATUS_LINK_UP |
6192                                LINK_STATUS_PHYSICAL_LINK_FLAG |
6193                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6194                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6195                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6196                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6197         vars->line_speed = 0;
6198         bnx2x_update_mng(params, vars->link_status);
6199
6200         /* activate nig drain */
6201         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6202
6203         /* disable emac */
6204         if (!CHIP_IS_E3(bp))
6205                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6206
6207         msleep(10);
6208         /* reset BigMac/Xmac */
6209         if (CHIP_IS_E1x(bp) ||
6210             CHIP_IS_E2(bp)) {
6211                 bnx2x_bmac_rx_disable(bp, params->port);
6212                 REG_WR(bp, GRCBASE_MISC +
6213                        MISC_REGISTERS_RESET_REG_2_CLEAR,
6214                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6215         }
6216         if (CHIP_IS_E3(bp))
6217                 bnx2x_xmac_disable(params);
6218
6219         return 0;
6220 }
6221
6222 static int bnx2x_update_link_up(struct link_params *params,
6223                                 struct link_vars *vars,
6224                                 u8 link_10g)
6225 {
6226         struct bnx2x *bp = params->bp;
6227         u8 port = params->port;
6228         int rc = 0;
6229
6230         vars->link_status |= (LINK_STATUS_LINK_UP |
6231                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6232         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6233
6234         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6235                 vars->link_status |=
6236                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6237
6238         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6239                 vars->link_status |=
6240                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6241         if (USES_WARPCORE(bp)) {
6242                 if (link_10g) {
6243                         if (bnx2x_xmac_enable(params, vars, 0) ==
6244                             -ESRCH) {
6245                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6246                                 vars->link_up = 0;
6247                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6248                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6249                         }
6250                 } else
6251                         bnx2x_umac_enable(params, vars, 0);
6252                 bnx2x_set_led(params, vars,
6253                               LED_MODE_OPER, vars->line_speed);
6254         }
6255         if ((CHIP_IS_E1x(bp) ||
6256              CHIP_IS_E2(bp))) {
6257                 if (link_10g) {
6258                         if (bnx2x_bmac_enable(params, vars, 0) ==
6259                             -ESRCH) {
6260                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6261                                 vars->link_up = 0;
6262                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6263                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6264                         }
6265
6266                         bnx2x_set_led(params, vars,
6267                                       LED_MODE_OPER, SPEED_10000);
6268                 } else {
6269                         rc = bnx2x_emac_program(params, vars);
6270                         bnx2x_emac_enable(params, vars, 0);
6271
6272                         /* AN complete? */
6273                         if ((vars->link_status &
6274                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6275                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6276                             SINGLE_MEDIA_DIRECT(params))
6277                                 bnx2x_set_gmii_tx_driver(params);
6278                 }
6279         }
6280
6281         /* PBF - link up */
6282         if (CHIP_IS_E1x(bp))
6283                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6284                                        vars->line_speed);
6285
6286         /* disable drain */
6287         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6288
6289         /* update shared memory */
6290         bnx2x_update_mng(params, vars->link_status);
6291         msleep(20);
6292         return rc;
6293 }
6294 /*
6295  * The bnx2x_link_update function should be called upon link
6296  * interrupt.
6297  * Link is considered up as follows:
6298  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6299  *   to be up
6300  * - SINGLE_MEDIA - The link between the 577xx and the external
6301  *   phy (XGXS) need to up as well as the external link of the
6302  *   phy (PHY_EXT1)
6303  * - DUAL_MEDIA - The link between the 577xx and the first
6304  *   external phy needs to be up, and at least one of the 2
6305  *   external phy link must be up.
6306  */
6307 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6308 {
6309         struct bnx2x *bp = params->bp;
6310         struct link_vars phy_vars[MAX_PHYS];
6311         u8 port = params->port;
6312         u8 link_10g_plus, phy_index;
6313         u8 ext_phy_link_up = 0, cur_link_up;
6314         int rc = 0;
6315         u8 is_mi_int = 0;
6316         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6317         u8 active_external_phy = INT_PHY;
6318         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6319         for (phy_index = INT_PHY; phy_index < params->num_phys;
6320               phy_index++) {
6321                 phy_vars[phy_index].flow_ctrl = 0;
6322                 phy_vars[phy_index].link_status = 0;
6323                 phy_vars[phy_index].line_speed = 0;
6324                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6325                 phy_vars[phy_index].phy_link_up = 0;
6326                 phy_vars[phy_index].link_up = 0;
6327                 phy_vars[phy_index].fault_detected = 0;
6328         }
6329
6330         if (USES_WARPCORE(bp))
6331                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6332
6333         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6334                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6335                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6336
6337         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6338                                 port*0x18) > 0);
6339         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6340                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6341                  is_mi_int,
6342                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6343
6344         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6345           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6346           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6347
6348         /* disable emac */
6349         if (!CHIP_IS_E3(bp))
6350                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6351
6352         /*
6353          * Step 1:
6354          * Check external link change only for external phys, and apply
6355          * priority selection between them in case the link on both phys
6356          * is up. Note that instead of the common vars, a temporary
6357          * vars argument is used since each phy may have different link/
6358          * speed/duplex result
6359          */
6360         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6361               phy_index++) {
6362                 struct bnx2x_phy *phy = &params->phy[phy_index];
6363                 if (!phy->read_status)
6364                         continue;
6365                 /* Read link status and params of this ext phy */
6366                 cur_link_up = phy->read_status(phy, params,
6367                                                &phy_vars[phy_index]);
6368                 if (cur_link_up) {
6369                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6370                                    phy_index);
6371                 } else {
6372                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6373                                    phy_index);
6374                         continue;
6375                 }
6376
6377                 if (!ext_phy_link_up) {
6378                         ext_phy_link_up = 1;
6379                         active_external_phy = phy_index;
6380                 } else {
6381                         switch (bnx2x_phy_selection(params)) {
6382                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6383                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6384                         /*
6385                          * In this option, the first PHY makes sure to pass the
6386                          * traffic through itself only.
6387                          * Its not clear how to reset the link on the second phy
6388                          */
6389                                 active_external_phy = EXT_PHY1;
6390                                 break;
6391                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6392                         /*
6393                          * In this option, the first PHY makes sure to pass the
6394                          * traffic through the second PHY.
6395                          */
6396                                 active_external_phy = EXT_PHY2;
6397                                 break;
6398                         default:
6399                         /*
6400                          * Link indication on both PHYs with the following cases
6401                          * is invalid:
6402                          * - FIRST_PHY means that second phy wasn't initialized,
6403                          * hence its link is expected to be down
6404                          * - SECOND_PHY means that first phy should not be able
6405                          * to link up by itself (using configuration)
6406                          * - DEFAULT should be overriden during initialiazation
6407                          */
6408                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6409                                            "mpc=0x%x. DISABLING LINK !!!\n",
6410                                            params->multi_phy_config);
6411                                 ext_phy_link_up = 0;
6412                                 break;
6413                         }
6414                 }
6415         }
6416         prev_line_speed = vars->line_speed;
6417         /*
6418          * Step 2:
6419          * Read the status of the internal phy. In case of
6420          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6421          * otherwise this is the link between the 577xx and the first
6422          * external phy
6423          */
6424         if (params->phy[INT_PHY].read_status)
6425                 params->phy[INT_PHY].read_status(
6426                         &params->phy[INT_PHY],
6427                         params, vars);
6428         /*
6429          * The INT_PHY flow control reside in the vars. This include the
6430          * case where the speed or flow control are not set to AUTO.
6431          * Otherwise, the active external phy flow control result is set
6432          * to the vars. The ext_phy_line_speed is needed to check if the
6433          * speed is different between the internal phy and external phy.
6434          * This case may be result of intermediate link speed change.
6435          */
6436         if (active_external_phy > INT_PHY) {
6437                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6438                 /*
6439                  * Link speed is taken from the XGXS. AN and FC result from
6440                  * the external phy.
6441                  */
6442                 vars->link_status |= phy_vars[active_external_phy].link_status;
6443
6444                 /*
6445                  * if active_external_phy is first PHY and link is up - disable
6446                  * disable TX on second external PHY
6447                  */
6448                 if (active_external_phy == EXT_PHY1) {
6449                         if (params->phy[EXT_PHY2].phy_specific_func) {
6450                                 DP(NETIF_MSG_LINK, "Disabling TX on"
6451                                                    " EXT_PHY2\n");
6452                                 params->phy[EXT_PHY2].phy_specific_func(
6453                                         &params->phy[EXT_PHY2],
6454                                         params, DISABLE_TX);
6455                         }
6456                 }
6457
6458                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6459                 vars->duplex = phy_vars[active_external_phy].duplex;
6460                 if (params->phy[active_external_phy].supported &
6461                     SUPPORTED_FIBRE)
6462                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6463                 else
6464                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6465                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6466                            active_external_phy);
6467         }
6468
6469         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6470               phy_index++) {
6471                 if (params->phy[phy_index].flags &
6472                     FLAGS_REARM_LATCH_SIGNAL) {
6473                         bnx2x_rearm_latch_signal(bp, port,
6474                                                  phy_index ==
6475                                                  active_external_phy);
6476                         break;
6477                 }
6478         }
6479         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6480                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6481                    vars->link_status, ext_phy_line_speed);
6482         /*
6483          * Upon link speed change set the NIG into drain mode. Comes to
6484          * deals with possible FIFO glitch due to clk change when speed
6485          * is decreased without link down indicator
6486          */
6487
6488         if (vars->phy_link_up) {
6489                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6490                     (ext_phy_line_speed != vars->line_speed)) {
6491                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6492                                    " different than the external"
6493                                    " link speed %d\n", vars->line_speed,
6494                                    ext_phy_line_speed);
6495                         vars->phy_link_up = 0;
6496                 } else if (prev_line_speed != vars->line_speed) {
6497                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6498                                0);
6499                         msleep(1);
6500                 }
6501         }
6502
6503         /* anything 10 and over uses the bmac */
6504         link_10g_plus = (vars->line_speed >= SPEED_10000);
6505
6506         bnx2x_link_int_ack(params, vars, link_10g_plus);
6507
6508         /*
6509          * In case external phy link is up, and internal link is down
6510          * (not initialized yet probably after link initialization, it
6511          * needs to be initialized.
6512          * Note that after link down-up as result of cable plug, the xgxs
6513          * link would probably become up again without the need
6514          * initialize it
6515          */
6516         if (!(SINGLE_MEDIA_DIRECT(params))) {
6517                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6518                            " init_preceding = %d\n", ext_phy_link_up,
6519                            vars->phy_link_up,
6520                            params->phy[EXT_PHY1].flags &
6521                            FLAGS_INIT_XGXS_FIRST);
6522                 if (!(params->phy[EXT_PHY1].flags &
6523                       FLAGS_INIT_XGXS_FIRST)
6524                     && ext_phy_link_up && !vars->phy_link_up) {
6525                         vars->line_speed = ext_phy_line_speed;
6526                         if (vars->line_speed < SPEED_1000)
6527                                 vars->phy_flags |= PHY_SGMII_FLAG;
6528                         else
6529                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6530
6531                         if (params->phy[INT_PHY].config_init)
6532                                 params->phy[INT_PHY].config_init(
6533                                         &params->phy[INT_PHY], params,
6534                                                 vars);
6535                 }
6536         }
6537         /*
6538          * Link is up only if both local phy and external phy (in case of
6539          * non-direct board) are up and no fault detected on active PHY.
6540          */
6541         vars->link_up = (vars->phy_link_up &&
6542                          (ext_phy_link_up ||
6543                           SINGLE_MEDIA_DIRECT(params)) &&
6544                          (phy_vars[active_external_phy].fault_detected == 0));
6545
6546         if (vars->link_up)
6547                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6548         else
6549                 rc = bnx2x_update_link_down(params, vars);
6550
6551         return rc;
6552 }
6553
6554
6555 /*****************************************************************************/
6556 /*                          External Phy section                             */
6557 /*****************************************************************************/
6558 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6559 {
6560         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6561                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6562         msleep(1);
6563         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6564                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6565 }
6566
6567 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6568                                       u32 spirom_ver, u32 ver_addr)
6569 {
6570         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6571                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6572
6573         if (ver_addr)
6574                 REG_WR(bp, ver_addr, spirom_ver);
6575 }
6576
6577 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6578                                       struct bnx2x_phy *phy,
6579                                       u8 port)
6580 {
6581         u16 fw_ver1, fw_ver2;
6582
6583         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6584                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6585         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6586                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6587         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6588                                   phy->ver_addr);
6589 }
6590
6591 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6592                                        struct bnx2x_phy *phy,
6593                                        struct link_vars *vars)
6594 {
6595         u16 val;
6596         bnx2x_cl45_read(bp, phy,
6597                         MDIO_AN_DEVAD,
6598                         MDIO_AN_REG_STATUS, &val);
6599         bnx2x_cl45_read(bp, phy,
6600                         MDIO_AN_DEVAD,
6601                         MDIO_AN_REG_STATUS, &val);
6602         if (val & (1<<5))
6603                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6604         if ((val & (1<<0)) == 0)
6605                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6606 }
6607
6608 /******************************************************************/
6609 /*              common BCM8073/BCM8727 PHY SECTION                */
6610 /******************************************************************/
6611 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6612                                   struct link_params *params,
6613                                   struct link_vars *vars)
6614 {
6615         struct bnx2x *bp = params->bp;
6616         if (phy->req_line_speed == SPEED_10 ||
6617             phy->req_line_speed == SPEED_100) {
6618                 vars->flow_ctrl = phy->req_flow_ctrl;
6619                 return;
6620         }
6621
6622         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6623             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6624                 u16 pause_result;
6625                 u16 ld_pause;           /* local */
6626                 u16 lp_pause;           /* link partner */
6627                 bnx2x_cl45_read(bp, phy,
6628                                 MDIO_AN_DEVAD,
6629                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6630
6631                 bnx2x_cl45_read(bp, phy,
6632                                 MDIO_AN_DEVAD,
6633                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6634                 pause_result = (ld_pause &
6635                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6636                 pause_result |= (lp_pause &
6637                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6638
6639                 bnx2x_pause_resolve(vars, pause_result);
6640                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6641                            pause_result);
6642         }
6643 }
6644 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6645                                              struct bnx2x_phy *phy,
6646                                              u8 port)
6647 {
6648         u32 count = 0;
6649         u16 fw_ver1, fw_msgout;
6650         int rc = 0;
6651
6652         /* Boot port from external ROM  */
6653         /* EDC grst */
6654         bnx2x_cl45_write(bp, phy,
6655                          MDIO_PMA_DEVAD,
6656                          MDIO_PMA_REG_GEN_CTRL,
6657                          0x0001);
6658
6659         /* ucode reboot and rst */
6660         bnx2x_cl45_write(bp, phy,
6661                          MDIO_PMA_DEVAD,
6662                          MDIO_PMA_REG_GEN_CTRL,
6663                          0x008c);
6664
6665         bnx2x_cl45_write(bp, phy,
6666                          MDIO_PMA_DEVAD,
6667                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6668
6669         /* Reset internal microprocessor */
6670         bnx2x_cl45_write(bp, phy,
6671                          MDIO_PMA_DEVAD,
6672                          MDIO_PMA_REG_GEN_CTRL,
6673                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6674
6675         /* Release srst bit */
6676         bnx2x_cl45_write(bp, phy,
6677                          MDIO_PMA_DEVAD,
6678                          MDIO_PMA_REG_GEN_CTRL,
6679                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6680
6681         /* Delay 100ms per the PHY specifications */
6682         msleep(100);
6683
6684         /* 8073 sometimes taking longer to download */
6685         do {
6686                 count++;
6687                 if (count > 300) {
6688                         DP(NETIF_MSG_LINK,
6689                                  "bnx2x_8073_8727_external_rom_boot port %x:"
6690                                  "Download failed. fw version = 0x%x\n",
6691                                  port, fw_ver1);
6692                         rc = -EINVAL;
6693                         break;
6694                 }
6695
6696                 bnx2x_cl45_read(bp, phy,
6697                                 MDIO_PMA_DEVAD,
6698                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6699                 bnx2x_cl45_read(bp, phy,
6700                                 MDIO_PMA_DEVAD,
6701                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6702
6703                 msleep(1);
6704         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6705                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6706                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6707
6708         /* Clear ser_boot_ctl bit */
6709         bnx2x_cl45_write(bp, phy,
6710                          MDIO_PMA_DEVAD,
6711                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6712         bnx2x_save_bcm_spirom_ver(bp, phy, port);
6713
6714         DP(NETIF_MSG_LINK,
6715                  "bnx2x_8073_8727_external_rom_boot port %x:"
6716                  "Download complete. fw version = 0x%x\n",
6717                  port, fw_ver1);
6718
6719         return rc;
6720 }
6721
6722 /******************************************************************/
6723 /*                      BCM8073 PHY SECTION                       */
6724 /******************************************************************/
6725 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6726 {
6727         /* This is only required for 8073A1, version 102 only */
6728         u16 val;
6729
6730         /* Read 8073 HW revision*/
6731         bnx2x_cl45_read(bp, phy,
6732                         MDIO_PMA_DEVAD,
6733                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6734
6735         if (val != 1) {
6736                 /* No need to workaround in 8073 A1 */
6737                 return 0;
6738         }
6739
6740         bnx2x_cl45_read(bp, phy,
6741                         MDIO_PMA_DEVAD,
6742                         MDIO_PMA_REG_ROM_VER2, &val);
6743
6744         /* SNR should be applied only for version 0x102 */
6745         if (val != 0x102)
6746                 return 0;
6747
6748         return 1;
6749 }
6750
6751 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6752 {
6753         u16 val, cnt, cnt1 ;
6754
6755         bnx2x_cl45_read(bp, phy,
6756                         MDIO_PMA_DEVAD,
6757                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6758
6759         if (val > 0) {
6760                 /* No need to workaround in 8073 A1 */
6761                 return 0;
6762         }
6763         /* XAUI workaround in 8073 A0: */
6764
6765         /*
6766          * After loading the boot ROM and restarting Autoneg, poll
6767          * Dev1, Reg $C820:
6768          */
6769
6770         for (cnt = 0; cnt < 1000; cnt++) {
6771                 bnx2x_cl45_read(bp, phy,
6772                                 MDIO_PMA_DEVAD,
6773                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
6774                                 &val);
6775                   /*
6776                    * If bit [14] = 0 or bit [13] = 0, continue on with
6777                    * system initialization (XAUI work-around not required, as
6778                    * these bits indicate 2.5G or 1G link up).
6779                    */
6780                 if (!(val & (1<<14)) || !(val & (1<<13))) {
6781                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
6782                         return 0;
6783                 } else if (!(val & (1<<15))) {
6784                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
6785                         /*
6786                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6787                          * MSB (bit15) goes to 1 (indicating that the XAUI
6788                          * workaround has completed), then continue on with
6789                          * system initialization.
6790                          */
6791                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6792                                 bnx2x_cl45_read(bp, phy,
6793                                         MDIO_PMA_DEVAD,
6794                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
6795                                 if (val & (1<<15)) {
6796                                         DP(NETIF_MSG_LINK,
6797                                           "XAUI workaround has completed\n");
6798                                         return 0;
6799                                  }
6800                                  msleep(3);
6801                         }
6802                         break;
6803                 }
6804                 msleep(3);
6805         }
6806         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
6807         return -EINVAL;
6808 }
6809
6810 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6811 {
6812         /* Force KR or KX */
6813         bnx2x_cl45_write(bp, phy,
6814                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6815         bnx2x_cl45_write(bp, phy,
6816                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6817         bnx2x_cl45_write(bp, phy,
6818                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
6819         bnx2x_cl45_write(bp, phy,
6820                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6821 }
6822
6823 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
6824                                       struct bnx2x_phy *phy,
6825                                       struct link_vars *vars)
6826 {
6827         u16 cl37_val;
6828         struct bnx2x *bp = params->bp;
6829         bnx2x_cl45_read(bp, phy,
6830                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6831
6832         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6833         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6834         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6835         if ((vars->ieee_fc &
6836             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6837             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6838                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6839         }
6840         if ((vars->ieee_fc &
6841             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6842             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6843                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6844         }
6845         if ((vars->ieee_fc &
6846             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6847             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6848                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6849         }
6850         DP(NETIF_MSG_LINK,
6851                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
6852
6853         bnx2x_cl45_write(bp, phy,
6854                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6855         msleep(500);
6856 }
6857
6858 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
6859                                   struct link_params *params,
6860                                   struct link_vars *vars)
6861 {
6862         struct bnx2x *bp = params->bp;
6863         u16 val = 0, tmp1;
6864         u8 gpio_port;
6865         DP(NETIF_MSG_LINK, "Init 8073\n");
6866
6867         if (CHIP_IS_E2(bp))
6868                 gpio_port = BP_PATH(bp);
6869         else
6870                 gpio_port = params->port;
6871         /* Restore normal power mode*/
6872         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6873                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6874
6875         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6876                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6877
6878         /* enable LASI */
6879         bnx2x_cl45_write(bp, phy,
6880                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
6881         bnx2x_cl45_write(bp, phy,
6882                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
6883
6884         bnx2x_8073_set_pause_cl37(params, phy, vars);
6885
6886         bnx2x_cl45_read(bp, phy,
6887                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6888
6889         bnx2x_cl45_read(bp, phy,
6890                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6891
6892         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
6893
6894         /* Swap polarity if required - Must be done only in non-1G mode */
6895         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6896                 /* Configure the 8073 to swap _P and _N of the KR lines */
6897                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
6898                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6899                 bnx2x_cl45_read(bp, phy,
6900                                 MDIO_PMA_DEVAD,
6901                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6902                 bnx2x_cl45_write(bp, phy,
6903                                  MDIO_PMA_DEVAD,
6904                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6905                                  (val | (3<<9)));
6906         }
6907
6908
6909         /* Enable CL37 BAM */
6910         if (REG_RD(bp, params->shmem_base +
6911                          offsetof(struct shmem_region, dev_info.
6912                                   port_hw_config[params->port].default_cfg)) &
6913             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6914
6915                 bnx2x_cl45_read(bp, phy,
6916                                 MDIO_AN_DEVAD,
6917                                 MDIO_AN_REG_8073_BAM, &val);
6918                 bnx2x_cl45_write(bp, phy,
6919                                  MDIO_AN_DEVAD,
6920                                  MDIO_AN_REG_8073_BAM, val | 1);
6921                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
6922         }
6923         if (params->loopback_mode == LOOPBACK_EXT) {
6924                 bnx2x_807x_force_10G(bp, phy);
6925                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
6926                 return 0;
6927         } else {
6928                 bnx2x_cl45_write(bp, phy,
6929                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
6930         }
6931         if (phy->req_line_speed != SPEED_AUTO_NEG) {
6932                 if (phy->req_line_speed == SPEED_10000) {
6933                         val = (1<<7);
6934                 } else if (phy->req_line_speed ==  SPEED_2500) {
6935                         val = (1<<5);
6936                         /*
6937                          * Note that 2.5G works only when used with 1G
6938                          * advertisement
6939                          */
6940                 } else
6941                         val = (1<<5);
6942         } else {
6943                 val = 0;
6944                 if (phy->speed_cap_mask &
6945                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6946                         val |= (1<<7);
6947
6948                 /* Note that 2.5G works only when used with 1G advertisement */
6949                 if (phy->speed_cap_mask &
6950                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6951                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6952                         val |= (1<<5);
6953                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
6954         }
6955
6956         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6957         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6958
6959         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6960              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
6961             (phy->req_line_speed == SPEED_2500)) {
6962                 u16 phy_ver;
6963                 /* Allow 2.5G for A1 and above */
6964                 bnx2x_cl45_read(bp, phy,
6965                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6966                                 &phy_ver);
6967                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
6968                 if (phy_ver > 0)
6969                         tmp1 |= 1;
6970                 else
6971                         tmp1 &= 0xfffe;
6972         } else {
6973                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
6974                 tmp1 &= 0xfffe;
6975         }
6976
6977         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6978         /* Add support for CL37 (passive mode) II */
6979
6980         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6981         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6982                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6983                                   0x20 : 0x40)));
6984
6985         /* Add support for CL37 (passive mode) III */
6986         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6987
6988         /*
6989          * The SNR will improve about 2db by changing BW and FEE main
6990          * tap. Rest commands are executed after link is up
6991          * Change FFE main cursor to 5 in EDC register
6992          */
6993         if (bnx2x_8073_is_snr_needed(bp, phy))
6994                 bnx2x_cl45_write(bp, phy,
6995                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6996                                  0xFB0C);
6997
6998         /* Enable FEC (Forware Error Correction) Request in the AN */
6999         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7000         tmp1 |= (1<<15);
7001         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7002
7003         bnx2x_ext_phy_set_pause(params, phy, vars);
7004
7005         /* Restart autoneg */
7006         msleep(500);
7007         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7008         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7009                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7010         return 0;
7011 }
7012
7013 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7014                                  struct link_params *params,
7015                                  struct link_vars *vars)
7016 {
7017         struct bnx2x *bp = params->bp;
7018         u8 link_up = 0;
7019         u16 val1, val2;
7020         u16 link_status = 0;
7021         u16 an1000_status = 0;
7022
7023         bnx2x_cl45_read(bp, phy,
7024                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7025
7026         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7027
7028         /* clear the interrupt LASI status register */
7029         bnx2x_cl45_read(bp, phy,
7030                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7031         bnx2x_cl45_read(bp, phy,
7032                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7033         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7034         /* Clear MSG-OUT */
7035         bnx2x_cl45_read(bp, phy,
7036                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7037
7038         /* Check the LASI */
7039         bnx2x_cl45_read(bp, phy,
7040                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7041
7042         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7043
7044         /* Check the link status */
7045         bnx2x_cl45_read(bp, phy,
7046                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7047         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7048
7049         bnx2x_cl45_read(bp, phy,
7050                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7051         bnx2x_cl45_read(bp, phy,
7052                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7053         link_up = ((val1 & 4) == 4);
7054         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7055
7056         if (link_up &&
7057              ((phy->req_line_speed != SPEED_10000))) {
7058                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7059                         return 0;
7060         }
7061         bnx2x_cl45_read(bp, phy,
7062                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7063         bnx2x_cl45_read(bp, phy,
7064                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7065
7066         /* Check the link status on 1.1.2 */
7067         bnx2x_cl45_read(bp, phy,
7068                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7069         bnx2x_cl45_read(bp, phy,
7070                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7071         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7072                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7073
7074         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7075         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7076                 /*
7077                  * The SNR will improve about 2dbby changing the BW and FEE main
7078                  * tap. The 1st write to change FFE main tap is set before
7079                  * restart AN. Change PLL Bandwidth in EDC register
7080                  */
7081                 bnx2x_cl45_write(bp, phy,
7082                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7083                                  0x26BC);
7084
7085                 /* Change CDR Bandwidth in EDC register */
7086                 bnx2x_cl45_write(bp, phy,
7087                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7088                                  0x0333);
7089         }
7090         bnx2x_cl45_read(bp, phy,
7091                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7092                         &link_status);
7093
7094         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7095         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7096                 link_up = 1;
7097                 vars->line_speed = SPEED_10000;
7098                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7099                            params->port);
7100         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7101                 link_up = 1;
7102                 vars->line_speed = SPEED_2500;
7103                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7104                            params->port);
7105         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7106                 link_up = 1;
7107                 vars->line_speed = SPEED_1000;
7108                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7109                            params->port);
7110         } else {
7111                 link_up = 0;
7112                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7113                            params->port);
7114         }
7115
7116         if (link_up) {
7117                 /* Swap polarity if required */
7118                 if (params->lane_config &
7119                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7120                         /* Configure the 8073 to swap P and N of the KR lines */
7121                         bnx2x_cl45_read(bp, phy,
7122                                         MDIO_XS_DEVAD,
7123                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7124                         /*
7125                          * Set bit 3 to invert Rx in 1G mode and clear this bit
7126                          * when it`s in 10G mode.
7127                          */
7128                         if (vars->line_speed == SPEED_1000) {
7129                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7130                                               "the 8073\n");
7131                                 val1 |= (1<<3);
7132                         } else
7133                                 val1 &= ~(1<<3);
7134
7135                         bnx2x_cl45_write(bp, phy,
7136                                          MDIO_XS_DEVAD,
7137                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7138                                          val1);
7139                 }
7140                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7141                 bnx2x_8073_resolve_fc(phy, params, vars);
7142                 vars->duplex = DUPLEX_FULL;
7143         }
7144         return link_up;
7145 }
7146
7147 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7148                                   struct link_params *params)
7149 {
7150         struct bnx2x *bp = params->bp;
7151         u8 gpio_port;
7152         if (CHIP_IS_E2(bp))
7153                 gpio_port = BP_PATH(bp);
7154         else
7155                 gpio_port = params->port;
7156         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7157            gpio_port);
7158         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7159                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7160                        gpio_port);
7161 }
7162
7163 /******************************************************************/
7164 /*                      BCM8705 PHY SECTION                       */
7165 /******************************************************************/
7166 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7167                                   struct link_params *params,
7168                                   struct link_vars *vars)
7169 {
7170         struct bnx2x *bp = params->bp;
7171         DP(NETIF_MSG_LINK, "init 8705\n");
7172         /* Restore normal power mode*/
7173         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7174                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7175         /* HW reset */
7176         bnx2x_ext_phy_hw_reset(bp, params->port);
7177         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7178         bnx2x_wait_reset_complete(bp, phy, params);
7179
7180         bnx2x_cl45_write(bp, phy,
7181                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7182         bnx2x_cl45_write(bp, phy,
7183                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7184         bnx2x_cl45_write(bp, phy,
7185                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7186         bnx2x_cl45_write(bp, phy,
7187                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7188         /* BCM8705 doesn't have microcode, hence the 0 */
7189         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7190         return 0;
7191 }
7192
7193 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7194                                  struct link_params *params,
7195                                  struct link_vars *vars)
7196 {
7197         u8 link_up = 0;
7198         u16 val1, rx_sd;
7199         struct bnx2x *bp = params->bp;
7200         DP(NETIF_MSG_LINK, "read status 8705\n");
7201         bnx2x_cl45_read(bp, phy,
7202                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7203         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7204
7205         bnx2x_cl45_read(bp, phy,
7206                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7207         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7208
7209         bnx2x_cl45_read(bp, phy,
7210                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7211
7212         bnx2x_cl45_read(bp, phy,
7213                       MDIO_PMA_DEVAD, 0xc809, &val1);
7214         bnx2x_cl45_read(bp, phy,
7215                       MDIO_PMA_DEVAD, 0xc809, &val1);
7216
7217         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7218         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7219         if (link_up) {
7220                 vars->line_speed = SPEED_10000;
7221                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7222         }
7223         return link_up;
7224 }
7225
7226 /******************************************************************/
7227 /*                      SFP+ module Section                       */
7228 /******************************************************************/
7229 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7230                                            struct bnx2x_phy *phy,
7231                                            u8 pmd_dis)
7232 {
7233         struct bnx2x *bp = params->bp;
7234         /*
7235          * Disable transmitter only for bootcodes which can enable it afterwards
7236          * (for D3 link)
7237          */
7238         if (pmd_dis) {
7239                 if (params->feature_config_flags &
7240                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7241                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7242                 else {
7243                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7244                         return;
7245                 }
7246         } else
7247                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7248         bnx2x_cl45_write(bp, phy,
7249                          MDIO_PMA_DEVAD,
7250                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7251 }
7252
7253 static u8 bnx2x_get_gpio_port(struct link_params *params)
7254 {
7255         u8 gpio_port;
7256         u32 swap_val, swap_override;
7257         struct bnx2x *bp = params->bp;
7258         if (CHIP_IS_E2(bp))
7259                 gpio_port = BP_PATH(bp);
7260         else
7261                 gpio_port = params->port;
7262         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7263         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7264         return gpio_port ^ (swap_val && swap_override);
7265 }
7266
7267 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7268                                            struct bnx2x_phy *phy,
7269                                            u8 tx_en)
7270 {
7271         u16 val;
7272         u8 port = params->port;
7273         struct bnx2x *bp = params->bp;
7274         u32 tx_en_mode;
7275
7276         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7277         tx_en_mode = REG_RD(bp, params->shmem_base +
7278                             offsetof(struct shmem_region,
7279                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7280                 PORT_HW_CFG_TX_LASER_MASK;
7281         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7282                            "mode = %x\n", tx_en, port, tx_en_mode);
7283         switch (tx_en_mode) {
7284         case PORT_HW_CFG_TX_LASER_MDIO:
7285
7286                 bnx2x_cl45_read(bp, phy,
7287                                 MDIO_PMA_DEVAD,
7288                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7289                                 &val);
7290
7291                 if (tx_en)
7292                         val &= ~(1<<15);
7293                 else
7294                         val |= (1<<15);
7295
7296                 bnx2x_cl45_write(bp, phy,
7297                                  MDIO_PMA_DEVAD,
7298                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7299                                  val);
7300         break;
7301         case PORT_HW_CFG_TX_LASER_GPIO0:
7302         case PORT_HW_CFG_TX_LASER_GPIO1:
7303         case PORT_HW_CFG_TX_LASER_GPIO2:
7304         case PORT_HW_CFG_TX_LASER_GPIO3:
7305         {
7306                 u16 gpio_pin;
7307                 u8 gpio_port, gpio_mode;
7308                 if (tx_en)
7309                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7310                 else
7311                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7312
7313                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7314                 gpio_port = bnx2x_get_gpio_port(params);
7315                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7316                 break;
7317         }
7318         default:
7319                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7320                 break;
7321         }
7322 }
7323
7324 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7325                                       struct bnx2x_phy *phy,
7326                                       u8 tx_en)
7327 {
7328         struct bnx2x *bp = params->bp;
7329         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7330         if (CHIP_IS_E3(bp))
7331                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7332         else
7333                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7334 }
7335
7336 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7337                                              struct link_params *params,
7338                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7339 {
7340         struct bnx2x *bp = params->bp;
7341         u16 val = 0;
7342         u16 i;
7343         if (byte_cnt > 16) {
7344                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7345                             " is limited to 0xf\n");
7346                 return -EINVAL;
7347         }
7348         /* Set the read command byte count */
7349         bnx2x_cl45_write(bp, phy,
7350                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7351                          (byte_cnt | 0xa000));
7352
7353         /* Set the read command address */
7354         bnx2x_cl45_write(bp, phy,
7355                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7356                          addr);
7357
7358         /* Activate read command */
7359         bnx2x_cl45_write(bp, phy,
7360                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7361                          0x2c0f);
7362
7363         /* Wait up to 500us for command complete status */
7364         for (i = 0; i < 100; i++) {
7365                 bnx2x_cl45_read(bp, phy,
7366                                 MDIO_PMA_DEVAD,
7367                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7368                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7369                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7370                         break;
7371                 udelay(5);
7372         }
7373
7374         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7375                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7376                 DP(NETIF_MSG_LINK,
7377                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7378                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7379                 return -EINVAL;
7380         }
7381
7382         /* Read the buffer */
7383         for (i = 0; i < byte_cnt; i++) {
7384                 bnx2x_cl45_read(bp, phy,
7385                                 MDIO_PMA_DEVAD,
7386                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7387                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7388         }
7389
7390         for (i = 0; i < 100; i++) {
7391                 bnx2x_cl45_read(bp, phy,
7392                                 MDIO_PMA_DEVAD,
7393                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7394                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7395                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7396                         return 0;
7397                 msleep(1);
7398         }
7399         return -EINVAL;
7400 }
7401
7402 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7403                                                  struct link_params *params,
7404                                                  u16 addr, u8 byte_cnt,
7405                                                  u8 *o_buf)
7406 {
7407         int rc = 0;
7408         u8 i, j = 0, cnt = 0;
7409         u32 data_array[4];
7410         u16 addr32;
7411         struct bnx2x *bp = params->bp;
7412         /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7413                                         " addr %d, cnt %d\n",
7414                                         addr, byte_cnt);*/
7415         if (byte_cnt > 16) {
7416                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7417                             " is limited to 16 bytes\n");
7418                 return -EINVAL;
7419         }
7420
7421         /* 4 byte aligned address */
7422         addr32 = addr & (~0x3);
7423         do {
7424                 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7425                                     data_array);
7426         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7427
7428         if (rc == 0) {
7429                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7430                         o_buf[j] = *((u8 *)data_array + i);
7431                         j++;
7432                 }
7433         }
7434
7435         return rc;
7436 }
7437
7438 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7439                                              struct link_params *params,
7440                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7441 {
7442         struct bnx2x *bp = params->bp;
7443         u16 val, i;
7444
7445         if (byte_cnt > 16) {
7446                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7447                             " is limited to 0xf\n");
7448                 return -EINVAL;
7449         }
7450
7451         /* Need to read from 1.8000 to clear it */
7452         bnx2x_cl45_read(bp, phy,
7453                         MDIO_PMA_DEVAD,
7454                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7455                         &val);
7456
7457         /* Set the read command byte count */
7458         bnx2x_cl45_write(bp, phy,
7459                          MDIO_PMA_DEVAD,
7460                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7461                          ((byte_cnt < 2) ? 2 : byte_cnt));
7462
7463         /* Set the read command address */
7464         bnx2x_cl45_write(bp, phy,
7465                          MDIO_PMA_DEVAD,
7466                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7467                          addr);
7468         /* Set the destination address */
7469         bnx2x_cl45_write(bp, phy,
7470                          MDIO_PMA_DEVAD,
7471                          0x8004,
7472                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7473
7474         /* Activate read command */
7475         bnx2x_cl45_write(bp, phy,
7476                          MDIO_PMA_DEVAD,
7477                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7478                          0x8002);
7479         /*
7480          * Wait appropriate time for two-wire command to finish before
7481          * polling the status register
7482          */
7483         msleep(1);
7484
7485         /* Wait up to 500us for command complete status */
7486         for (i = 0; i < 100; i++) {
7487                 bnx2x_cl45_read(bp, phy,
7488                                 MDIO_PMA_DEVAD,
7489                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7490                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7491                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7492                         break;
7493                 udelay(5);
7494         }
7495
7496         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7497                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7498                 DP(NETIF_MSG_LINK,
7499                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7500                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7501                 return -EFAULT;
7502         }
7503
7504         /* Read the buffer */
7505         for (i = 0; i < byte_cnt; i++) {
7506                 bnx2x_cl45_read(bp, phy,
7507                                 MDIO_PMA_DEVAD,
7508                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7509                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7510         }
7511
7512         for (i = 0; i < 100; i++) {
7513                 bnx2x_cl45_read(bp, phy,
7514                                 MDIO_PMA_DEVAD,
7515                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7516                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7517                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7518                         return 0;
7519                 msleep(1);
7520         }
7521
7522         return -EINVAL;
7523 }
7524
7525 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7526                                  struct link_params *params, u16 addr,
7527                                  u8 byte_cnt, u8 *o_buf)
7528 {
7529         int rc = -EINVAL;
7530         switch (phy->type) {
7531         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7532                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7533                                                        byte_cnt, o_buf);
7534         break;
7535         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7536         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7537                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7538                                                        byte_cnt, o_buf);
7539         break;
7540         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7541                 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7542                                                            byte_cnt, o_buf);
7543         break;
7544         }
7545         return rc;
7546 }
7547
7548 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7549                               struct link_params *params,
7550                               u16 *edc_mode)
7551 {
7552         struct bnx2x *bp = params->bp;
7553         u32 sync_offset = 0, phy_idx, media_types;
7554         u8 val, check_limiting_mode = 0;
7555         *edc_mode = EDC_MODE_LIMITING;
7556
7557         phy->media_type = ETH_PHY_UNSPECIFIED;
7558         /* First check for copper cable */
7559         if (bnx2x_read_sfp_module_eeprom(phy,
7560                                          params,
7561                                          SFP_EEPROM_CON_TYPE_ADDR,
7562                                          1,
7563                                          &val) != 0) {
7564                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7565                 return -EINVAL;
7566         }
7567
7568         switch (val) {
7569         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7570         {
7571                 u8 copper_module_type;
7572                 phy->media_type = ETH_PHY_DA_TWINAX;
7573                 /*
7574                  * Check if its active cable (includes SFP+ module)
7575                  * of passive cable
7576                  */
7577                 if (bnx2x_read_sfp_module_eeprom(phy,
7578                                                params,
7579                                                SFP_EEPROM_FC_TX_TECH_ADDR,
7580                                                1,
7581                                                &copper_module_type) != 0) {
7582                         DP(NETIF_MSG_LINK,
7583                                 "Failed to read copper-cable-type"
7584                                 " from SFP+ EEPROM\n");
7585                         return -EINVAL;
7586                 }
7587
7588                 if (copper_module_type &
7589                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7590                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7591                         check_limiting_mode = 1;
7592                 } else if (copper_module_type &
7593                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7594                                 DP(NETIF_MSG_LINK, "Passive Copper"
7595                                             " cable detected\n");
7596                                 *edc_mode =
7597                                       EDC_MODE_PASSIVE_DAC;
7598                 } else {
7599                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
7600                                      "type 0x%x !!!\n", copper_module_type);
7601                         return -EINVAL;
7602                 }
7603                 break;
7604         }
7605         case SFP_EEPROM_CON_TYPE_VAL_LC:
7606                 phy->media_type = ETH_PHY_SFP_FIBER;
7607                 DP(NETIF_MSG_LINK, "Optic module detected\n");
7608                 check_limiting_mode = 1;
7609                 break;
7610         default:
7611                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7612                          val);
7613                 return -EINVAL;
7614         }
7615         sync_offset = params->shmem_base +
7616                 offsetof(struct shmem_region,
7617                          dev_info.port_hw_config[params->port].media_type);
7618         media_types = REG_RD(bp, sync_offset);
7619         /* Update media type for non-PMF sync */
7620         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7621                 if (&(params->phy[phy_idx]) == phy) {
7622                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7623                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7624                         media_types |= ((phy->media_type &
7625                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7626                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7627                         break;
7628                 }
7629         }
7630         REG_WR(bp, sync_offset, media_types);
7631         if (check_limiting_mode) {
7632                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7633                 if (bnx2x_read_sfp_module_eeprom(phy,
7634                                                  params,
7635                                                  SFP_EEPROM_OPTIONS_ADDR,
7636                                                  SFP_EEPROM_OPTIONS_SIZE,
7637                                                  options) != 0) {
7638                         DP(NETIF_MSG_LINK, "Failed to read Option"
7639                                 " field from module EEPROM\n");
7640                         return -EINVAL;
7641                 }
7642                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7643                         *edc_mode = EDC_MODE_LINEAR;
7644                 else
7645                         *edc_mode = EDC_MODE_LIMITING;
7646         }
7647         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7648         return 0;
7649 }
7650 /*
7651  * This function read the relevant field from the module (SFP+), and verify it
7652  * is compliant with this board
7653  */
7654 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7655                                    struct link_params *params)
7656 {
7657         struct bnx2x *bp = params->bp;
7658         u32 val, cmd;
7659         u32 fw_resp, fw_cmd_param;
7660         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7661         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7662         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7663         val = REG_RD(bp, params->shmem_base +
7664                          offsetof(struct shmem_region, dev_info.
7665                                   port_feature_config[params->port].config));
7666         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7667             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7668                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7669                 return 0;
7670         }
7671
7672         if (params->feature_config_flags &
7673             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7674                 /* Use specific phy request */
7675                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7676         } else if (params->feature_config_flags &
7677                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7678                 /* Use first phy request only in case of non-dual media*/
7679                 if (DUAL_MEDIA(params)) {
7680                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7681                            "verification\n");
7682                         return -EINVAL;
7683                 }
7684                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7685         } else {
7686                 /* No support in OPT MDL detection */
7687                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7688                           "verification\n");
7689                 return -EINVAL;
7690         }
7691
7692         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7693         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7694         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7695                 DP(NETIF_MSG_LINK, "Approved module\n");
7696                 return 0;
7697         }
7698
7699         /* format the warning message */
7700         if (bnx2x_read_sfp_module_eeprom(phy,
7701                                          params,
7702                                          SFP_EEPROM_VENDOR_NAME_ADDR,
7703                                          SFP_EEPROM_VENDOR_NAME_SIZE,
7704                                          (u8 *)vendor_name))
7705                 vendor_name[0] = '\0';
7706         else
7707                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7708         if (bnx2x_read_sfp_module_eeprom(phy,
7709                                          params,
7710                                          SFP_EEPROM_PART_NO_ADDR,
7711                                          SFP_EEPROM_PART_NO_SIZE,
7712                                          (u8 *)vendor_pn))
7713                 vendor_pn[0] = '\0';
7714         else
7715                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7716
7717         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
7718                               " Port %d from %s part number %s\n",
7719                          params->port, vendor_name, vendor_pn);
7720         phy->flags |= FLAGS_SFP_NOT_APPROVED;
7721         return -EINVAL;
7722 }
7723
7724 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7725                                                  struct link_params *params)
7726
7727 {
7728         u8 val;
7729         struct bnx2x *bp = params->bp;
7730         u16 timeout;
7731         /*
7732          * Initialization time after hot-plug may take up to 300ms for
7733          * some phys type ( e.g. JDSU )
7734          */
7735
7736         for (timeout = 0; timeout < 60; timeout++) {
7737                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7738                     == 0) {
7739                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
7740                                      "took %d ms\n", timeout * 5);
7741                         return 0;
7742                 }
7743                 msleep(5);
7744         }
7745         return -EINVAL;
7746 }
7747
7748 static void bnx2x_8727_power_module(struct bnx2x *bp,
7749                                     struct bnx2x_phy *phy,
7750                                     u8 is_power_up) {
7751         /* Make sure GPIOs are not using for LED mode */
7752         u16 val;
7753         /*
7754          * In the GPIO register, bit 4 is use to determine if the GPIOs are
7755          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7756          * output
7757          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7758          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7759          * where the 1st bit is the over-current(only input), and 2nd bit is
7760          * for power( only output )
7761          *
7762          * In case of NOC feature is disabled and power is up, set GPIO control
7763          *  as input to enable listening of over-current indication
7764          */
7765         if (phy->flags & FLAGS_NOC)
7766                 return;
7767         if (is_power_up)
7768                 val = (1<<4);
7769         else
7770                 /*
7771                  * Set GPIO control to OUTPUT, and set the power bit
7772                  * to according to the is_power_up
7773                  */
7774                 val = (1<<1);
7775
7776         bnx2x_cl45_write(bp, phy,
7777                          MDIO_PMA_DEVAD,
7778                          MDIO_PMA_REG_8727_GPIO_CTRL,
7779                          val);
7780 }
7781
7782 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
7783                                         struct bnx2x_phy *phy,
7784                                         u16 edc_mode)
7785 {
7786         u16 cur_limiting_mode;
7787
7788         bnx2x_cl45_read(bp, phy,
7789                         MDIO_PMA_DEVAD,
7790                         MDIO_PMA_REG_ROM_VER2,
7791                         &cur_limiting_mode);
7792         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
7793                  cur_limiting_mode);
7794
7795         if (edc_mode == EDC_MODE_LIMITING) {
7796                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
7797                 bnx2x_cl45_write(bp, phy,
7798                                  MDIO_PMA_DEVAD,
7799                                  MDIO_PMA_REG_ROM_VER2,
7800                                  EDC_MODE_LIMITING);
7801         } else { /* LRM mode ( default )*/
7802
7803                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
7804
7805                 /*
7806                  * Changing to LRM mode takes quite few seconds. So do it only
7807                  * if current mode is limiting (default is LRM)
7808                  */
7809                 if (cur_limiting_mode != EDC_MODE_LIMITING)
7810                         return 0;
7811
7812                 bnx2x_cl45_write(bp, phy,
7813                                  MDIO_PMA_DEVAD,
7814                                  MDIO_PMA_REG_LRM_MODE,
7815                                  0);
7816                 bnx2x_cl45_write(bp, phy,
7817                                  MDIO_PMA_DEVAD,
7818                                  MDIO_PMA_REG_ROM_VER2,
7819                                  0x128);
7820                 bnx2x_cl45_write(bp, phy,
7821                                  MDIO_PMA_DEVAD,
7822                                  MDIO_PMA_REG_MISC_CTRL0,
7823                                  0x4008);
7824                 bnx2x_cl45_write(bp, phy,
7825                                  MDIO_PMA_DEVAD,
7826                                  MDIO_PMA_REG_LRM_MODE,
7827                                  0xaaaa);
7828         }
7829         return 0;
7830 }
7831
7832 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
7833                                         struct bnx2x_phy *phy,
7834                                         u16 edc_mode)
7835 {
7836         u16 phy_identifier;
7837         u16 rom_ver2_val;
7838         bnx2x_cl45_read(bp, phy,
7839                         MDIO_PMA_DEVAD,
7840                         MDIO_PMA_REG_PHY_IDENTIFIER,
7841                         &phy_identifier);
7842
7843         bnx2x_cl45_write(bp, phy,
7844                          MDIO_PMA_DEVAD,
7845                          MDIO_PMA_REG_PHY_IDENTIFIER,
7846                          (phy_identifier & ~(1<<9)));
7847
7848         bnx2x_cl45_read(bp, phy,
7849                         MDIO_PMA_DEVAD,
7850                         MDIO_PMA_REG_ROM_VER2,
7851                         &rom_ver2_val);
7852         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7853         bnx2x_cl45_write(bp, phy,
7854                          MDIO_PMA_DEVAD,
7855                          MDIO_PMA_REG_ROM_VER2,
7856                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7857
7858         bnx2x_cl45_write(bp, phy,
7859                          MDIO_PMA_DEVAD,
7860                          MDIO_PMA_REG_PHY_IDENTIFIER,
7861                          (phy_identifier | (1<<9)));
7862
7863         return 0;
7864 }
7865
7866 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
7867                                      struct link_params *params,
7868                                      u32 action)
7869 {
7870         struct bnx2x *bp = params->bp;
7871
7872         switch (action) {
7873         case DISABLE_TX:
7874                 bnx2x_sfp_set_transmitter(params, phy, 0);
7875                 break;
7876         case ENABLE_TX:
7877                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7878                         bnx2x_sfp_set_transmitter(params, phy, 1);
7879                 break;
7880         default:
7881                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
7882                    action);
7883                 return;
7884         }
7885 }
7886
7887 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7888                                            u8 gpio_mode)
7889 {
7890         struct bnx2x *bp = params->bp;
7891
7892         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
7893                             offsetof(struct shmem_region,
7894                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
7895                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7896         switch (fault_led_gpio) {
7897         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7898                 return;
7899         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7900         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7901         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7902         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7903         {
7904                 u8 gpio_port = bnx2x_get_gpio_port(params);
7905                 u16 gpio_pin = fault_led_gpio -
7906                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7907                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
7908                                    "pin %x port %x mode %x\n",
7909                                gpio_pin, gpio_port, gpio_mode);
7910                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7911         }
7912         break;
7913         default:
7914                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
7915                                fault_led_gpio);
7916         }
7917 }
7918
7919 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
7920                                           u8 gpio_mode)
7921 {
7922         u32 pin_cfg;
7923         u8 port = params->port;
7924         struct bnx2x *bp = params->bp;
7925         pin_cfg = (REG_RD(bp, params->shmem_base +
7926                          offsetof(struct shmem_region,
7927                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7928                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7929                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7930         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
7931                        gpio_mode, pin_cfg);
7932         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
7933 }
7934
7935 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
7936                                            u8 gpio_mode)
7937 {
7938         struct bnx2x *bp = params->bp;
7939         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
7940         if (CHIP_IS_E3(bp)) {
7941                 /*
7942                  * Low ==> if SFP+ module is supported otherwise
7943                  * High ==> if SFP+ module is not on the approved vendor list
7944                  */
7945                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
7946         } else
7947                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
7948 }
7949
7950 static void bnx2x_warpcore_power_module(struct link_params *params,
7951                                         struct bnx2x_phy *phy,
7952                                         u8 power)
7953 {
7954         u32 pin_cfg;
7955         struct bnx2x *bp = params->bp;
7956
7957         pin_cfg = (REG_RD(bp, params->shmem_base +
7958                           offsetof(struct shmem_region,
7959                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7960                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7961                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7962
7963         if (pin_cfg == PIN_CFG_NA)
7964                 return;
7965         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7966                        power, pin_cfg);
7967         /*
7968          * Low ==> corresponding SFP+ module is powered
7969          * high ==> the SFP+ module is powered down
7970          */
7971         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7972 }
7973
7974 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
7975                                     struct link_params *params)
7976 {
7977         bnx2x_warpcore_power_module(params, phy, 0);
7978 }
7979
7980 static void bnx2x_power_sfp_module(struct link_params *params,
7981                                    struct bnx2x_phy *phy,
7982                                    u8 power)
7983 {
7984         struct bnx2x *bp = params->bp;
7985         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
7986
7987         switch (phy->type) {
7988         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7989         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7990                 bnx2x_8727_power_module(params->bp, phy, power);
7991                 break;
7992         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7993                 bnx2x_warpcore_power_module(params, phy, power);
7994                 break;
7995         default:
7996                 break;
7997         }
7998 }
7999 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8000                                              struct bnx2x_phy *phy,
8001                                              u16 edc_mode)
8002 {
8003         u16 val = 0;
8004         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8005         struct bnx2x *bp = params->bp;
8006
8007         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8008         /* This is a global register which controls all lanes */
8009         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8010                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8011         val &= ~(0xf << (lane << 2));
8012
8013         switch (edc_mode) {
8014         case EDC_MODE_LINEAR:
8015         case EDC_MODE_LIMITING:
8016                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8017                 break;
8018         case EDC_MODE_PASSIVE_DAC:
8019                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8020                 break;
8021         default:
8022                 break;
8023         }
8024
8025         val |= (mode << (lane << 2));
8026         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8027                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8028         /* A must read */
8029         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8030                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8031
8032         /* Restart microcode to re-read the new mode */
8033         bnx2x_warpcore_reset_lane(bp, phy, 1);
8034         bnx2x_warpcore_reset_lane(bp, phy, 0);
8035
8036 }
8037
8038 static void bnx2x_set_limiting_mode(struct link_params *params,
8039                                     struct bnx2x_phy *phy,
8040                                     u16 edc_mode)
8041 {
8042         switch (phy->type) {
8043         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8044                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8045                 break;
8046         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8047         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8048                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8049                 break;
8050         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8051                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8052                 break;
8053         }
8054 }
8055
8056 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8057                                struct link_params *params)
8058 {
8059         struct bnx2x *bp = params->bp;
8060         u16 edc_mode;
8061         int rc = 0;
8062
8063         u32 val = REG_RD(bp, params->shmem_base +
8064                              offsetof(struct shmem_region, dev_info.
8065                                      port_feature_config[params->port].config));
8066
8067         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8068                  params->port);
8069         /* Power up module */
8070         bnx2x_power_sfp_module(params, phy, 1);
8071         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8072                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8073                 return -EINVAL;
8074         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8075                 /* check SFP+ module compatibility */
8076                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8077                 rc = -EINVAL;
8078                 /* Turn on fault module-detected led */
8079                 bnx2x_set_sfp_module_fault_led(params,
8080                                                MISC_REGISTERS_GPIO_HIGH);
8081
8082                 /* Check if need to power down the SFP+ module */
8083                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8084                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8085                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8086                         bnx2x_power_sfp_module(params, phy, 0);
8087                         return rc;
8088                 }
8089         } else {
8090                 /* Turn off fault module-detected led */
8091                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8092         }
8093
8094         /*
8095          * Check and set limiting mode / LRM mode on 8726. On 8727 it
8096          * is done automatically
8097          */
8098         bnx2x_set_limiting_mode(params, phy, edc_mode);
8099
8100         /*
8101          * Enable transmit for this module if the module is approved, or
8102          * if unapproved modules should also enable the Tx laser
8103          */
8104         if (rc == 0 ||
8105             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8106             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8107                 bnx2x_sfp_set_transmitter(params, phy, 1);
8108         else
8109                 bnx2x_sfp_set_transmitter(params, phy, 0);
8110
8111         return rc;
8112 }
8113
8114 void bnx2x_handle_module_detect_int(struct link_params *params)
8115 {
8116         struct bnx2x *bp = params->bp;
8117         struct bnx2x_phy *phy;
8118         u32 gpio_val;
8119         u8 gpio_num, gpio_port;
8120         if (CHIP_IS_E3(bp))
8121                 phy = &params->phy[INT_PHY];
8122         else
8123                 phy = &params->phy[EXT_PHY1];
8124
8125         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8126                                       params->port, &gpio_num, &gpio_port) ==
8127             -EINVAL) {
8128                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8129                 return;
8130         }
8131
8132         /* Set valid module led off */
8133         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8134
8135         /* Get current gpio val reflecting module plugged in / out*/
8136         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8137
8138         /* Call the handling function in case module is detected */
8139         if (gpio_val == 0) {
8140                 bnx2x_power_sfp_module(params, phy, 1);
8141                 bnx2x_set_gpio_int(bp, gpio_num,
8142                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8143                                    gpio_port);
8144                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8145                         bnx2x_sfp_module_detection(phy, params);
8146                 else
8147                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8148         } else {
8149                 u32 val = REG_RD(bp, params->shmem_base +
8150                                  offsetof(struct shmem_region, dev_info.
8151                                           port_feature_config[params->port].
8152                                           config));
8153                 bnx2x_set_gpio_int(bp, gpio_num,
8154                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8155                                    gpio_port);
8156                 /*
8157                  * Module was plugged out.
8158                  * Disable transmit for this module
8159                  */
8160                 phy->media_type = ETH_PHY_NOT_PRESENT;
8161                 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8162                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8163                     CHIP_IS_E3(bp))
8164                         bnx2x_sfp_set_transmitter(params, phy, 0);
8165         }
8166 }
8167
8168 /******************************************************************/
8169 /*              Used by 8706 and 8727                             */
8170 /******************************************************************/
8171 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8172                                  struct bnx2x_phy *phy,
8173                                  u16 alarm_status_offset,
8174                                  u16 alarm_ctrl_offset)
8175 {
8176         u16 alarm_status, val;
8177         bnx2x_cl45_read(bp, phy,
8178                         MDIO_PMA_DEVAD, alarm_status_offset,
8179                         &alarm_status);
8180         bnx2x_cl45_read(bp, phy,
8181                         MDIO_PMA_DEVAD, alarm_status_offset,
8182                         &alarm_status);
8183         /* Mask or enable the fault event. */
8184         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8185         if (alarm_status & (1<<0))
8186                 val &= ~(1<<0);
8187         else
8188                 val |= (1<<0);
8189         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8190 }
8191 /******************************************************************/
8192 /*              common BCM8706/BCM8726 PHY SECTION                */
8193 /******************************************************************/
8194 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8195                                       struct link_params *params,
8196                                       struct link_vars *vars)
8197 {
8198         u8 link_up = 0;
8199         u16 val1, val2, rx_sd, pcs_status;
8200         struct bnx2x *bp = params->bp;
8201         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8202         /* Clear RX Alarm*/
8203         bnx2x_cl45_read(bp, phy,
8204                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8205
8206         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8207                              MDIO_PMA_LASI_TXCTRL);
8208
8209         /* clear LASI indication*/
8210         bnx2x_cl45_read(bp, phy,
8211                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8212         bnx2x_cl45_read(bp, phy,
8213                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8214         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8215
8216         bnx2x_cl45_read(bp, phy,
8217                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8218         bnx2x_cl45_read(bp, phy,
8219                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8220         bnx2x_cl45_read(bp, phy,
8221                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8222         bnx2x_cl45_read(bp, phy,
8223                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8224
8225         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8226                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8227         /*
8228          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8229          * are set, or if the autoneg bit 1 is set
8230          */
8231         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8232         if (link_up) {
8233                 if (val2 & (1<<1))
8234                         vars->line_speed = SPEED_1000;
8235                 else
8236                         vars->line_speed = SPEED_10000;
8237                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8238                 vars->duplex = DUPLEX_FULL;
8239         }
8240
8241         /* Capture 10G link fault. Read twice to clear stale value. */
8242         if (vars->line_speed == SPEED_10000) {
8243                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8244                             MDIO_PMA_LASI_TXSTAT, &val1);
8245                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8246                             MDIO_PMA_LASI_TXSTAT, &val1);
8247                 if (val1 & (1<<0))
8248                         vars->fault_detected = 1;
8249         }
8250
8251         return link_up;
8252 }
8253
8254 /******************************************************************/
8255 /*                      BCM8706 PHY SECTION                       */
8256 /******************************************************************/
8257 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8258                                  struct link_params *params,
8259                                  struct link_vars *vars)
8260 {
8261         u32 tx_en_mode;
8262         u16 cnt, val, tmp1;
8263         struct bnx2x *bp = params->bp;
8264
8265         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8266                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8267         /* HW reset */
8268         bnx2x_ext_phy_hw_reset(bp, params->port);
8269         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8270         bnx2x_wait_reset_complete(bp, phy, params);
8271
8272         /* Wait until fw is loaded */
8273         for (cnt = 0; cnt < 100; cnt++) {
8274                 bnx2x_cl45_read(bp, phy,
8275                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8276                 if (val)
8277                         break;
8278                 msleep(10);
8279         }
8280         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8281         if ((params->feature_config_flags &
8282              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8283                 u8 i;
8284                 u16 reg;
8285                 for (i = 0; i < 4; i++) {
8286                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8287                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8288                                    MDIO_XS_8706_REG_BANK_RX0);
8289                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8290                         /* Clear first 3 bits of the control */
8291                         val &= ~0x7;
8292                         /* Set control bits according to configuration */
8293                         val |= (phy->rx_preemphasis[i] & 0x7);
8294                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8295                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8296                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8297                 }
8298         }
8299         /* Force speed */
8300         if (phy->req_line_speed == SPEED_10000) {
8301                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8302
8303                 bnx2x_cl45_write(bp, phy,
8304                                  MDIO_PMA_DEVAD,
8305                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8306                 bnx2x_cl45_write(bp, phy,
8307                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8308                                  0);
8309                 /* Arm LASI for link and Tx fault. */
8310                 bnx2x_cl45_write(bp, phy,
8311                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8312         } else {
8313                 /* Force 1Gbps using autoneg with 1G advertisement */
8314
8315                 /* Allow CL37 through CL73 */
8316                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8317                 bnx2x_cl45_write(bp, phy,
8318                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8319
8320                 /* Enable Full-Duplex advertisement on CL37 */
8321                 bnx2x_cl45_write(bp, phy,
8322                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8323                 /* Enable CL37 AN */
8324                 bnx2x_cl45_write(bp, phy,
8325                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8326                 /* 1G support */
8327                 bnx2x_cl45_write(bp, phy,
8328                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8329
8330                 /* Enable clause 73 AN */
8331                 bnx2x_cl45_write(bp, phy,
8332                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8333                 bnx2x_cl45_write(bp, phy,
8334                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8335                                  0x0400);
8336                 bnx2x_cl45_write(bp, phy,
8337                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8338                                  0x0004);
8339         }
8340         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8341
8342         /*
8343          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8344          * power mode, if TX Laser is disabled
8345          */
8346
8347         tx_en_mode = REG_RD(bp, params->shmem_base +
8348                             offsetof(struct shmem_region,
8349                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8350                         & PORT_HW_CFG_TX_LASER_MASK;
8351
8352         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8353                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8354                 bnx2x_cl45_read(bp, phy,
8355                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8356                 tmp1 |= 0x1;
8357                 bnx2x_cl45_write(bp, phy,
8358                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8359         }
8360
8361         return 0;
8362 }
8363
8364 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8365                                   struct link_params *params,
8366                                   struct link_vars *vars)
8367 {
8368         return bnx2x_8706_8726_read_status(phy, params, vars);
8369 }
8370
8371 /******************************************************************/
8372 /*                      BCM8726 PHY SECTION                       */
8373 /******************************************************************/
8374 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8375                                        struct link_params *params)
8376 {
8377         struct bnx2x *bp = params->bp;
8378         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8379         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8380 }
8381
8382 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8383                                          struct link_params *params)
8384 {
8385         struct bnx2x *bp = params->bp;
8386         /* Need to wait 100ms after reset */
8387         msleep(100);
8388
8389         /* Micro controller re-boot */
8390         bnx2x_cl45_write(bp, phy,
8391                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8392
8393         /* Set soft reset */
8394         bnx2x_cl45_write(bp, phy,
8395                          MDIO_PMA_DEVAD,
8396                          MDIO_PMA_REG_GEN_CTRL,
8397                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8398
8399         bnx2x_cl45_write(bp, phy,
8400                          MDIO_PMA_DEVAD,
8401                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8402
8403         bnx2x_cl45_write(bp, phy,
8404                          MDIO_PMA_DEVAD,
8405                          MDIO_PMA_REG_GEN_CTRL,
8406                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8407
8408         /* wait for 150ms for microcode load */
8409         msleep(150);
8410
8411         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8412         bnx2x_cl45_write(bp, phy,
8413                          MDIO_PMA_DEVAD,
8414                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8415
8416         msleep(200);
8417         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8418 }
8419
8420 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8421                                  struct link_params *params,
8422                                  struct link_vars *vars)
8423 {
8424         struct bnx2x *bp = params->bp;
8425         u16 val1;
8426         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8427         if (link_up) {
8428                 bnx2x_cl45_read(bp, phy,
8429                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8430                                 &val1);
8431                 if (val1 & (1<<15)) {
8432                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8433                         link_up = 0;
8434                         vars->line_speed = 0;
8435                 }
8436         }
8437         return link_up;
8438 }
8439
8440
8441 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8442                                   struct link_params *params,
8443                                   struct link_vars *vars)
8444 {
8445         struct bnx2x *bp = params->bp;
8446         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8447
8448         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8449         bnx2x_wait_reset_complete(bp, phy, params);
8450
8451         bnx2x_8726_external_rom_boot(phy, params);
8452
8453         /*
8454          * Need to call module detected on initialization since the module
8455          * detection triggered by actual module insertion might occur before
8456          * driver is loaded, and when driver is loaded, it reset all
8457          * registers, including the transmitter
8458          */
8459         bnx2x_sfp_module_detection(phy, params);
8460
8461         if (phy->req_line_speed == SPEED_1000) {
8462                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8463                 bnx2x_cl45_write(bp, phy,
8464                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8465                 bnx2x_cl45_write(bp, phy,
8466                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8467                 bnx2x_cl45_write(bp, phy,
8468                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8469                 bnx2x_cl45_write(bp, phy,
8470                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8471                                  0x400);
8472         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8473                    (phy->speed_cap_mask &
8474                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8475                    ((phy->speed_cap_mask &
8476                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8477                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8478                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8479                 /* Set Flow control */
8480                 bnx2x_ext_phy_set_pause(params, phy, vars);
8481                 bnx2x_cl45_write(bp, phy,
8482                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8483                 bnx2x_cl45_write(bp, phy,
8484                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8485                 bnx2x_cl45_write(bp, phy,
8486                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8487                 bnx2x_cl45_write(bp, phy,
8488                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8489                 bnx2x_cl45_write(bp, phy,
8490                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8491                 /*
8492                  * Enable RX-ALARM control to receive interrupt for 1G speed
8493                  * change
8494                  */
8495                 bnx2x_cl45_write(bp, phy,
8496                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8497                 bnx2x_cl45_write(bp, phy,
8498                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8499                                  0x400);
8500
8501         } else { /* Default 10G. Set only LASI control */
8502                 bnx2x_cl45_write(bp, phy,
8503                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8504         }
8505
8506         /* Set TX PreEmphasis if needed */
8507         if ((params->feature_config_flags &
8508              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8509                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
8510                          "TX_CTRL2 0x%x\n",
8511                          phy->tx_preemphasis[0],
8512                          phy->tx_preemphasis[1]);
8513                 bnx2x_cl45_write(bp, phy,
8514                                  MDIO_PMA_DEVAD,
8515                                  MDIO_PMA_REG_8726_TX_CTRL1,
8516                                  phy->tx_preemphasis[0]);
8517
8518                 bnx2x_cl45_write(bp, phy,
8519                                  MDIO_PMA_DEVAD,
8520                                  MDIO_PMA_REG_8726_TX_CTRL2,
8521                                  phy->tx_preemphasis[1]);
8522         }
8523
8524         return 0;
8525
8526 }
8527
8528 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8529                                   struct link_params *params)
8530 {
8531         struct bnx2x *bp = params->bp;
8532         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8533         /* Set serial boot control for external load */
8534         bnx2x_cl45_write(bp, phy,
8535                          MDIO_PMA_DEVAD,
8536                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
8537 }
8538
8539 /******************************************************************/
8540 /*                      BCM8727 PHY SECTION                       */
8541 /******************************************************************/
8542
8543 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8544                                     struct link_params *params, u8 mode)
8545 {
8546         struct bnx2x *bp = params->bp;
8547         u16 led_mode_bitmask = 0;
8548         u16 gpio_pins_bitmask = 0;
8549         u16 val;
8550         /* Only NOC flavor requires to set the LED specifically */
8551         if (!(phy->flags & FLAGS_NOC))
8552                 return;
8553         switch (mode) {
8554         case LED_MODE_FRONT_PANEL_OFF:
8555         case LED_MODE_OFF:
8556                 led_mode_bitmask = 0;
8557                 gpio_pins_bitmask = 0x03;
8558                 break;
8559         case LED_MODE_ON:
8560                 led_mode_bitmask = 0;
8561                 gpio_pins_bitmask = 0x02;
8562                 break;
8563         case LED_MODE_OPER:
8564                 led_mode_bitmask = 0x60;
8565                 gpio_pins_bitmask = 0x11;
8566                 break;
8567         }
8568         bnx2x_cl45_read(bp, phy,
8569                         MDIO_PMA_DEVAD,
8570                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8571                         &val);
8572         val &= 0xff8f;
8573         val |= led_mode_bitmask;
8574         bnx2x_cl45_write(bp, phy,
8575                          MDIO_PMA_DEVAD,
8576                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8577                          val);
8578         bnx2x_cl45_read(bp, phy,
8579                         MDIO_PMA_DEVAD,
8580                         MDIO_PMA_REG_8727_GPIO_CTRL,
8581                         &val);
8582         val &= 0xffe0;
8583         val |= gpio_pins_bitmask;
8584         bnx2x_cl45_write(bp, phy,
8585                          MDIO_PMA_DEVAD,
8586                          MDIO_PMA_REG_8727_GPIO_CTRL,
8587                          val);
8588 }
8589 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8590                                 struct link_params *params) {
8591         u32 swap_val, swap_override;
8592         u8 port;
8593         /*
8594          * The PHY reset is controlled by GPIO 1. Fake the port number
8595          * to cancel the swap done in set_gpio()
8596          */
8597         struct bnx2x *bp = params->bp;
8598         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8599         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8600         port = (swap_val && swap_override) ^ 1;
8601         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8602                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8603 }
8604
8605 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8606                                   struct link_params *params,
8607                                   struct link_vars *vars)
8608 {
8609         u32 tx_en_mode;
8610         u16 tmp1, val, mod_abs, tmp2;
8611         u16 rx_alarm_ctrl_val;
8612         u16 lasi_ctrl_val;
8613         struct bnx2x *bp = params->bp;
8614         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8615
8616         bnx2x_wait_reset_complete(bp, phy, params);
8617         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8618         /* Should be 0x6 to enable XS on Tx side. */
8619         lasi_ctrl_val = 0x0006;
8620
8621         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8622         /* enable LASI */
8623         bnx2x_cl45_write(bp, phy,
8624                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8625                          rx_alarm_ctrl_val);
8626         bnx2x_cl45_write(bp, phy,
8627                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8628                          0);
8629         bnx2x_cl45_write(bp, phy,
8630                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8631
8632         /*
8633          * Initially configure MOD_ABS to interrupt when module is
8634          * presence( bit 8)
8635          */
8636         bnx2x_cl45_read(bp, phy,
8637                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8638         /*
8639          * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8640          * When the EDC is off it locks onto a reference clock and avoids
8641          * becoming 'lost'
8642          */
8643         mod_abs &= ~(1<<8);
8644         if (!(phy->flags & FLAGS_NOC))
8645                 mod_abs &= ~(1<<9);
8646         bnx2x_cl45_write(bp, phy,
8647                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8648
8649
8650         /* Enable/Disable PHY transmitter output */
8651         bnx2x_set_disable_pmd_transmit(params, phy, 0);
8652
8653         /* Make MOD_ABS give interrupt on change */
8654         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8655                         &val);
8656         val |= (1<<12);
8657         if (phy->flags & FLAGS_NOC)
8658                 val |= (3<<5);
8659
8660         /*
8661          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8662          * status which reflect SFP+ module over-current
8663          */
8664         if (!(phy->flags & FLAGS_NOC))
8665                 val &= 0xff8f; /* Reset bits 4-6 */
8666         bnx2x_cl45_write(bp, phy,
8667                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8668
8669         bnx2x_8727_power_module(bp, phy, 1);
8670
8671         bnx2x_cl45_read(bp, phy,
8672                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8673
8674         bnx2x_cl45_read(bp, phy,
8675                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8676
8677         /* Set option 1G speed */
8678         if (phy->req_line_speed == SPEED_1000) {
8679                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8680                 bnx2x_cl45_write(bp, phy,
8681                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8682                 bnx2x_cl45_write(bp, phy,
8683                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8684                 bnx2x_cl45_read(bp, phy,
8685                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8686                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8687                 /*
8688                  * Power down the XAUI until link is up in case of dual-media
8689                  * and 1G
8690                  */
8691                 if (DUAL_MEDIA(params)) {
8692                         bnx2x_cl45_read(bp, phy,
8693                                         MDIO_PMA_DEVAD,
8694                                         MDIO_PMA_REG_8727_PCS_GP, &val);
8695                         val |= (3<<10);
8696                         bnx2x_cl45_write(bp, phy,
8697                                          MDIO_PMA_DEVAD,
8698                                          MDIO_PMA_REG_8727_PCS_GP, val);
8699                 }
8700         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8701                    ((phy->speed_cap_mask &
8702                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8703                    ((phy->speed_cap_mask &
8704                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8705                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8706
8707                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8708                 bnx2x_cl45_write(bp, phy,
8709                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8710                 bnx2x_cl45_write(bp, phy,
8711                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8712         } else {
8713                 /*
8714                  * Since the 8727 has only single reset pin, need to set the 10G
8715                  * registers although it is default
8716                  */
8717                 bnx2x_cl45_write(bp, phy,
8718                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8719                                  0x0020);
8720                 bnx2x_cl45_write(bp, phy,
8721                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8722                 bnx2x_cl45_write(bp, phy,
8723                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8724                 bnx2x_cl45_write(bp, phy,
8725                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8726                                  0x0008);
8727         }
8728
8729         /*
8730          * Set 2-wire transfer rate of SFP+ module EEPROM
8731          * to 100Khz since some DACs(direct attached cables) do
8732          * not work at 400Khz.
8733          */
8734         bnx2x_cl45_write(bp, phy,
8735                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8736                          0xa001);
8737
8738         /* Set TX PreEmphasis if needed */
8739         if ((params->feature_config_flags &
8740              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8741                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8742                            phy->tx_preemphasis[0],
8743                            phy->tx_preemphasis[1]);
8744                 bnx2x_cl45_write(bp, phy,
8745                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8746                                  phy->tx_preemphasis[0]);
8747
8748                 bnx2x_cl45_write(bp, phy,
8749                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8750                                  phy->tx_preemphasis[1]);
8751         }
8752
8753         /*
8754          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8755          * power mode, if TX Laser is disabled
8756          */
8757         tx_en_mode = REG_RD(bp, params->shmem_base +
8758                             offsetof(struct shmem_region,
8759                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8760                         & PORT_HW_CFG_TX_LASER_MASK;
8761
8762         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8763
8764                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8765                 bnx2x_cl45_read(bp, phy,
8766                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
8767                 tmp2 |= 0x1000;
8768                 tmp2 &= 0xFFEF;
8769                 bnx2x_cl45_write(bp, phy,
8770                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
8771         }
8772
8773         return 0;
8774 }
8775
8776 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
8777                                       struct link_params *params)
8778 {
8779         struct bnx2x *bp = params->bp;
8780         u16 mod_abs, rx_alarm_status;
8781         u32 val = REG_RD(bp, params->shmem_base +
8782                              offsetof(struct shmem_region, dev_info.
8783                                       port_feature_config[params->port].
8784                                       config));
8785         bnx2x_cl45_read(bp, phy,
8786                         MDIO_PMA_DEVAD,
8787                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8788         if (mod_abs & (1<<8)) {
8789
8790                 /* Module is absent */
8791                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8792                             "show module is absent\n");
8793                 phy->media_type = ETH_PHY_NOT_PRESENT;
8794                 /*
8795                  * 1. Set mod_abs to detect next module
8796                  *    presence event
8797                  * 2. Set EDC off by setting OPTXLOS signal input to low
8798                  *    (bit 9).
8799                  *    When the EDC is off it locks onto a reference clock and
8800                  *    avoids becoming 'lost'.
8801                  */
8802                 mod_abs &= ~(1<<8);
8803                 if (!(phy->flags & FLAGS_NOC))
8804                         mod_abs &= ~(1<<9);
8805                 bnx2x_cl45_write(bp, phy,
8806                                  MDIO_PMA_DEVAD,
8807                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8808
8809                 /*
8810                  * Clear RX alarm since it stays up as long as
8811                  * the mod_abs wasn't changed
8812                  */
8813                 bnx2x_cl45_read(bp, phy,
8814                                 MDIO_PMA_DEVAD,
8815                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8816
8817         } else {
8818                 /* Module is present */
8819                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8820                             "show module is present\n");
8821                 /*
8822                  * First disable transmitter, and if the module is ok, the
8823                  * module_detection will enable it
8824                  * 1. Set mod_abs to detect next module absent event ( bit 8)
8825                  * 2. Restore the default polarity of the OPRXLOS signal and
8826                  * this signal will then correctly indicate the presence or
8827                  * absence of the Rx signal. (bit 9)
8828                  */
8829                 mod_abs |= (1<<8);
8830                 if (!(phy->flags & FLAGS_NOC))
8831                         mod_abs |= (1<<9);
8832                 bnx2x_cl45_write(bp, phy,
8833                                  MDIO_PMA_DEVAD,
8834                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8835
8836                 /*
8837                  * Clear RX alarm since it stays up as long as the mod_abs
8838                  * wasn't changed. This is need to be done before calling the
8839                  * module detection, otherwise it will clear* the link update
8840                  * alarm
8841                  */
8842                 bnx2x_cl45_read(bp, phy,
8843                                 MDIO_PMA_DEVAD,
8844                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8845
8846
8847                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8848                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8849                         bnx2x_sfp_set_transmitter(params, phy, 0);
8850
8851                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8852                         bnx2x_sfp_module_detection(phy, params);
8853                 else
8854                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8855         }
8856
8857         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8858                    rx_alarm_status);
8859         /* No need to check link status in case of module plugged in/out */
8860 }
8861
8862 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
8863                                  struct link_params *params,
8864                                  struct link_vars *vars)
8865
8866 {
8867         struct bnx2x *bp = params->bp;
8868         u8 link_up = 0, oc_port = params->port;
8869         u16 link_status = 0;
8870         u16 rx_alarm_status, lasi_ctrl, val1;
8871
8872         /* If PHY is not initialized, do not check link status */
8873         bnx2x_cl45_read(bp, phy,
8874                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8875                         &lasi_ctrl);
8876         if (!lasi_ctrl)
8877                 return 0;
8878
8879         /* Check the LASI on Rx */
8880         bnx2x_cl45_read(bp, phy,
8881                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
8882                         &rx_alarm_status);
8883         vars->line_speed = 0;
8884         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
8885
8886         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8887                              MDIO_PMA_LASI_TXCTRL);
8888
8889         bnx2x_cl45_read(bp, phy,
8890                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8891
8892         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
8893
8894         /* Clear MSG-OUT */
8895         bnx2x_cl45_read(bp, phy,
8896                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8897
8898         /*
8899          * If a module is present and there is need to check
8900          * for over current
8901          */
8902         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
8903                 /* Check over-current using 8727 GPIO0 input*/
8904                 bnx2x_cl45_read(bp, phy,
8905                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8906                                 &val1);
8907
8908                 if ((val1 & (1<<8)) == 0) {
8909                         if (!CHIP_IS_E1x(bp))
8910                                 oc_port = BP_PATH(bp) + (params->port << 1);
8911                         DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
8912                                        " on port %d\n", oc_port);
8913                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
8914                                             " been detected and the power to "
8915                                             "that SFP+ module has been removed"
8916                                             " to prevent failure of the card."
8917                                             " Please remove the SFP+ module and"
8918                                             " restart the system to clear this"
8919                                             " error.\n",
8920                          oc_port);
8921                         /* Disable all RX_ALARMs except for mod_abs */
8922                         bnx2x_cl45_write(bp, phy,
8923                                          MDIO_PMA_DEVAD,
8924                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
8925
8926                         bnx2x_cl45_read(bp, phy,
8927                                         MDIO_PMA_DEVAD,
8928                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8929                         /* Wait for module_absent_event */
8930                         val1 |= (1<<8);
8931                         bnx2x_cl45_write(bp, phy,
8932                                          MDIO_PMA_DEVAD,
8933                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8934                         /* Clear RX alarm */
8935                         bnx2x_cl45_read(bp, phy,
8936                                 MDIO_PMA_DEVAD,
8937                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8938                         return 0;
8939                 }
8940         } /* Over current check */
8941
8942         /* When module absent bit is set, check module */
8943         if (rx_alarm_status & (1<<5)) {
8944                 bnx2x_8727_handle_mod_abs(phy, params);
8945                 /* Enable all mod_abs and link detection bits */
8946                 bnx2x_cl45_write(bp, phy,
8947                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8948                                  ((1<<5) | (1<<2)));
8949         }
8950         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
8951         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
8952         /* If transmitter is disabled, ignore false link up indication */
8953         bnx2x_cl45_read(bp, phy,
8954                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8955         if (val1 & (1<<15)) {
8956                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8957                 return 0;
8958         }
8959
8960         bnx2x_cl45_read(bp, phy,
8961                         MDIO_PMA_DEVAD,
8962                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8963
8964         /*
8965          * Bits 0..2 --> speed detected,
8966          * Bits 13..15--> link is down
8967          */
8968         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8969                 link_up = 1;
8970                 vars->line_speed = SPEED_10000;
8971                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
8972                            params->port);
8973         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8974                 link_up = 1;
8975                 vars->line_speed = SPEED_1000;
8976                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
8977                            params->port);
8978         } else {
8979                 link_up = 0;
8980                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
8981                            params->port);
8982         }
8983
8984         /* Capture 10G link fault. */
8985         if (vars->line_speed == SPEED_10000) {
8986                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8987                             MDIO_PMA_LASI_TXSTAT, &val1);
8988
8989                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8990                             MDIO_PMA_LASI_TXSTAT, &val1);
8991
8992                 if (val1 & (1<<0)) {
8993                         vars->fault_detected = 1;
8994                 }
8995         }
8996
8997         if (link_up) {
8998                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8999                 vars->duplex = DUPLEX_FULL;
9000                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9001         }
9002
9003         if ((DUAL_MEDIA(params)) &&
9004             (phy->req_line_speed == SPEED_1000)) {
9005                 bnx2x_cl45_read(bp, phy,
9006                                 MDIO_PMA_DEVAD,
9007                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9008                 /*
9009                  * In case of dual-media board and 1G, power up the XAUI side,
9010                  * otherwise power it down. For 10G it is done automatically
9011                  */
9012                 if (link_up)
9013                         val1 &= ~(3<<10);
9014                 else
9015                         val1 |= (3<<10);
9016                 bnx2x_cl45_write(bp, phy,
9017                                  MDIO_PMA_DEVAD,
9018                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9019         }
9020         return link_up;
9021 }
9022
9023 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9024                                   struct link_params *params)
9025 {
9026         struct bnx2x *bp = params->bp;
9027
9028         /* Enable/Disable PHY transmitter output */
9029         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9030
9031         /* Disable Transmitter */
9032         bnx2x_sfp_set_transmitter(params, phy, 0);
9033         /* Clear LASI */
9034         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9035
9036 }
9037
9038 /******************************************************************/
9039 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9040 /******************************************************************/
9041 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9042                                            struct link_params *params)
9043 {
9044         u16 val, fw_ver1, fw_ver2, cnt;
9045         u8 port;
9046         struct bnx2x *bp = params->bp;
9047
9048         port = params->port;
9049
9050         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
9051         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9052         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9053         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9054         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9055         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9056         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9057
9058         for (cnt = 0; cnt < 100; cnt++) {
9059                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9060                 if (val & 1)
9061                         break;
9062                 udelay(5);
9063         }
9064         if (cnt == 100) {
9065                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
9066                 bnx2x_save_spirom_version(bp, port, 0,
9067                                           phy->ver_addr);
9068                 return;
9069         }
9070
9071
9072         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9073         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9074         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9075         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9076         for (cnt = 0; cnt < 100; cnt++) {
9077                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9078                 if (val & 1)
9079                         break;
9080                 udelay(5);
9081         }
9082         if (cnt == 100) {
9083                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
9084                 bnx2x_save_spirom_version(bp, port, 0,
9085                                           phy->ver_addr);
9086                 return;
9087         }
9088
9089         /* lower 16 bits of the register SPI_FW_STATUS */
9090         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9091         /* upper 16 bits of register SPI_FW_STATUS */
9092         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9093
9094         bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9095                                   phy->ver_addr);
9096 }
9097
9098 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9099                                 struct bnx2x_phy *phy)
9100 {
9101         u16 val;
9102
9103         /* PHYC_CTL_LED_CTL */
9104         bnx2x_cl45_read(bp, phy,
9105                         MDIO_PMA_DEVAD,
9106                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9107         val &= 0xFE00;
9108         val |= 0x0092;
9109
9110         bnx2x_cl45_write(bp, phy,
9111                          MDIO_PMA_DEVAD,
9112                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9113
9114         bnx2x_cl45_write(bp, phy,
9115                          MDIO_PMA_DEVAD,
9116                          MDIO_PMA_REG_8481_LED1_MASK,
9117                          0x80);
9118
9119         bnx2x_cl45_write(bp, phy,
9120                          MDIO_PMA_DEVAD,
9121                          MDIO_PMA_REG_8481_LED2_MASK,
9122                          0x18);
9123
9124         /* Select activity source by Tx and Rx, as suggested by PHY AE */
9125         bnx2x_cl45_write(bp, phy,
9126                          MDIO_PMA_DEVAD,
9127                          MDIO_PMA_REG_8481_LED3_MASK,
9128                          0x0006);
9129
9130         /* Select the closest activity blink rate to that in 10/100/1000 */
9131         bnx2x_cl45_write(bp, phy,
9132                         MDIO_PMA_DEVAD,
9133                         MDIO_PMA_REG_8481_LED3_BLINK,
9134                         0);
9135
9136         bnx2x_cl45_read(bp, phy,
9137                         MDIO_PMA_DEVAD,
9138                         MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
9139         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9140
9141         bnx2x_cl45_write(bp, phy,
9142                          MDIO_PMA_DEVAD,
9143                          MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
9144
9145         /* 'Interrupt Mask' */
9146         bnx2x_cl45_write(bp, phy,
9147                          MDIO_AN_DEVAD,
9148                          0xFFFB, 0xFFFD);
9149 }
9150
9151 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9152                                        struct link_params *params,
9153                                        struct link_vars *vars)
9154 {
9155         struct bnx2x *bp = params->bp;
9156         u16 autoneg_val, an_1000_val, an_10_100_val;
9157         u16 tmp_req_line_speed;
9158
9159         tmp_req_line_speed = phy->req_line_speed;
9160         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9161                 if (phy->req_line_speed == SPEED_10000)
9162                         phy->req_line_speed = SPEED_AUTO_NEG;
9163
9164         /*
9165          * This phy uses the NIG latch mechanism since link indication
9166          * arrives through its LED4 and not via its LASI signal, so we
9167          * get steady signal instead of clear on read
9168          */
9169         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9170                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
9171
9172         bnx2x_cl45_write(bp, phy,
9173                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9174
9175         bnx2x_848xx_set_led(bp, phy);
9176
9177         /* set 1000 speed advertisement */
9178         bnx2x_cl45_read(bp, phy,
9179                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9180                         &an_1000_val);
9181
9182         bnx2x_ext_phy_set_pause(params, phy, vars);
9183         bnx2x_cl45_read(bp, phy,
9184                         MDIO_AN_DEVAD,
9185                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9186                         &an_10_100_val);
9187         bnx2x_cl45_read(bp, phy,
9188                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9189                         &autoneg_val);
9190         /* Disable forced speed */
9191         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9192         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9193
9194         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9195              (phy->speed_cap_mask &
9196              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9197             (phy->req_line_speed == SPEED_1000)) {
9198                 an_1000_val |= (1<<8);
9199                 autoneg_val |= (1<<9 | 1<<12);
9200                 if (phy->req_duplex == DUPLEX_FULL)
9201                         an_1000_val |= (1<<9);
9202                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9203         } else
9204                 an_1000_val &= ~((1<<8) | (1<<9));
9205
9206         bnx2x_cl45_write(bp, phy,
9207                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9208                          an_1000_val);
9209
9210         /* set 100 speed advertisement */
9211         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9212              (phy->speed_cap_mask &
9213               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9214                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
9215              (phy->supported &
9216               (SUPPORTED_100baseT_Half |
9217                SUPPORTED_100baseT_Full)))) {
9218                 an_10_100_val |= (1<<7);
9219                 /* Enable autoneg and restart autoneg for legacy speeds */
9220                 autoneg_val |= (1<<9 | 1<<12);
9221
9222                 if (phy->req_duplex == DUPLEX_FULL)
9223                         an_10_100_val |= (1<<8);
9224                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9225         }
9226         /* set 10 speed advertisement */
9227         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9228              (phy->speed_cap_mask &
9229               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9230                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9231              (phy->supported &
9232               (SUPPORTED_10baseT_Half |
9233                SUPPORTED_10baseT_Full)))) {
9234                 an_10_100_val |= (1<<5);
9235                 autoneg_val |= (1<<9 | 1<<12);
9236                 if (phy->req_duplex == DUPLEX_FULL)
9237                         an_10_100_val |= (1<<6);
9238                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9239         }
9240
9241         /* Only 10/100 are allowed to work in FORCE mode */
9242         if ((phy->req_line_speed == SPEED_100) &&
9243             (phy->supported &
9244              (SUPPORTED_100baseT_Half |
9245               SUPPORTED_100baseT_Full))) {
9246                 autoneg_val |= (1<<13);
9247                 /* Enabled AUTO-MDIX when autoneg is disabled */
9248                 bnx2x_cl45_write(bp, phy,
9249                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9250                                  (1<<15 | 1<<9 | 7<<0));
9251                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9252         }
9253         if ((phy->req_line_speed == SPEED_10) &&
9254             (phy->supported &
9255              (SUPPORTED_10baseT_Half |
9256               SUPPORTED_10baseT_Full))) {
9257                 /* Enabled AUTO-MDIX when autoneg is disabled */
9258                 bnx2x_cl45_write(bp, phy,
9259                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9260                                  (1<<15 | 1<<9 | 7<<0));
9261                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9262         }
9263
9264         bnx2x_cl45_write(bp, phy,
9265                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9266                          an_10_100_val);
9267
9268         if (phy->req_duplex == DUPLEX_FULL)
9269                 autoneg_val |= (1<<8);
9270
9271         /*
9272          * Always write this if this is not 84833.
9273          * For 84833, write it only when it's a forced speed.
9274          */
9275         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9276                 ((autoneg_val & (1<<12)) == 0))
9277                 bnx2x_cl45_write(bp, phy,
9278                          MDIO_AN_DEVAD,
9279                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9280
9281         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9282             (phy->speed_cap_mask &
9283              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9284                 (phy->req_line_speed == SPEED_10000)) {
9285                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9286                         /* Restart autoneg for 10G*/
9287
9288                         bnx2x_cl45_write(bp, phy,
9289                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9290                                  0x3200);
9291         } else
9292                 bnx2x_cl45_write(bp, phy,
9293                                  MDIO_AN_DEVAD,
9294                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9295                                  1);
9296
9297         /* Save spirom version */
9298         bnx2x_save_848xx_spirom_version(phy, params);
9299
9300         phy->req_line_speed = tmp_req_line_speed;
9301
9302         return 0;
9303 }
9304
9305 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9306                                   struct link_params *params,
9307                                   struct link_vars *vars)
9308 {
9309         struct bnx2x *bp = params->bp;
9310         /* Restore normal power mode*/
9311         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9312                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9313
9314         /* HW reset */
9315         bnx2x_ext_phy_hw_reset(bp, params->port);
9316         bnx2x_wait_reset_complete(bp, phy, params);
9317
9318         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9319         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9320 }
9321
9322
9323 #define PHY84833_HDSHK_WAIT 300
9324 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9325                                    struct link_params *params,
9326                                    struct link_vars *vars)
9327 {
9328         u32 idx;
9329         u32 pair_swap;
9330         u16 val;
9331         u16 data;
9332         struct bnx2x *bp = params->bp;
9333         /* Do pair swap */
9334
9335         /* Check for configuration. */
9336         pair_swap = REG_RD(bp, params->shmem_base +
9337                            offsetof(struct shmem_region,
9338                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9339                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9340
9341         if (pair_swap == 0)
9342                 return 0;
9343
9344         data = (u16)pair_swap;
9345
9346         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9347         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9348                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9349                         PHY84833_CMD_OPEN_OVERRIDE);
9350         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9351                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9352                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9353                 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9354                         break;
9355                 msleep(1);
9356         }
9357         if (idx >= PHY84833_HDSHK_WAIT) {
9358                 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
9359                 return -EINVAL;
9360         }
9361
9362         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9363                         MDIO_84833_TOP_CFG_SCRATCH_REG4,
9364                         data);
9365         /* Issue pair swap command */
9366         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9367                         MDIO_84833_TOP_CFG_SCRATCH_REG0,
9368                         PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
9369         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9370                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9371                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9372                 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9373                         (val == PHY84833_CMD_COMPLETE_ERROR))
9374                         break;
9375                 msleep(1);
9376         }
9377         if ((idx >= PHY84833_HDSHK_WAIT) ||
9378                 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9379                 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
9380                 return -EINVAL;
9381         }
9382         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9383                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9384                         PHY84833_CMD_CLEAR_COMPLETE);
9385         DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
9386         return 0;
9387 }
9388
9389
9390 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9391                                       u32 shmem_base_path[],
9392                                       u32 chip_id)
9393 {
9394         u32 reset_pin[2];
9395         u32 idx;
9396         u8 reset_gpios;
9397         if (CHIP_IS_E3(bp)) {
9398                 /* Assume that these will be GPIOs, not EPIOs. */
9399                 for (idx = 0; idx < 2; idx++) {
9400                         /* Map config param to register bit. */
9401                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9402                                 offsetof(struct shmem_region,
9403                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9404                         reset_pin[idx] = (reset_pin[idx] &
9405                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9406                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9407                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9408                         reset_pin[idx] = (1 << reset_pin[idx]);
9409                 }
9410                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9411         } else {
9412                 /* E2, look from diff place of shmem. */
9413                 for (idx = 0; idx < 2; idx++) {
9414                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9415                                 offsetof(struct shmem_region,
9416                                 dev_info.port_hw_config[0].default_cfg));
9417                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9418                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9419                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9420                         reset_pin[idx] = (1 << reset_pin[idx]);
9421                 }
9422                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9423         }
9424
9425         return reset_gpios;
9426 }
9427
9428 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9429                                 struct link_params *params)
9430 {
9431         struct bnx2x *bp = params->bp;
9432         u8 reset_gpios;
9433         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9434                                 offsetof(struct shmem2_region,
9435                                 other_shmem_base_addr));
9436
9437         u32 shmem_base_path[2];
9438         shmem_base_path[0] = params->shmem_base;
9439         shmem_base_path[1] = other_shmem_base_addr;
9440
9441         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9442                                                   params->chip_id);
9443
9444         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9445         udelay(10);
9446         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9447                 reset_gpios);
9448
9449         return 0;
9450 }
9451
9452 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
9453                                                 u32 shmem_base_path[],
9454                                                 u32 chip_id)
9455 {
9456         u8 reset_gpios;
9457
9458         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
9459
9460         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9461         udelay(10);
9462         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
9463         msleep(800);
9464         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
9465                 reset_gpios);
9466
9467         return 0;
9468 }
9469
9470 #define PHY84833_CONSTANT_LATENCY 1193
9471 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9472                                    struct link_params *params,
9473                                    struct link_vars *vars)
9474 {
9475         struct bnx2x *bp = params->bp;
9476         u8 port, initialize = 1;
9477         u16 val;
9478         u16 temp;
9479         u32 actual_phy_selection, cms_enable, idx;
9480         int rc = 0;
9481
9482         msleep(1);
9483
9484         if (!(CHIP_IS_E1(bp)))
9485                 port = BP_PATH(bp);
9486         else
9487                 port = params->port;
9488
9489         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9490                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9491                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9492                                port);
9493         } else {
9494                 /* MDIO reset */
9495                 bnx2x_cl45_write(bp, phy,
9496                                 MDIO_PMA_DEVAD,
9497                                 MDIO_PMA_REG_CTRL, 0x8000);
9498                 /* Bring PHY out of super isolate mode */
9499                 bnx2x_cl45_read(bp, phy,
9500                                 MDIO_CTL_DEVAD,
9501                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9502                 val &= ~MDIO_84833_SUPER_ISOLATE;
9503                 bnx2x_cl45_write(bp, phy,
9504                                 MDIO_CTL_DEVAD,
9505                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9506         }
9507
9508         bnx2x_wait_reset_complete(bp, phy, params);
9509
9510         /* Wait for GPHY to come out of reset */
9511         msleep(50);
9512
9513         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9514                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9515
9516         /*
9517          * BCM84823 requires that XGXS links up first @ 10G for normal behavior
9518          */
9519         temp = vars->line_speed;
9520         vars->line_speed = SPEED_10000;
9521         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9522         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9523         vars->line_speed = temp;
9524
9525         /* Set dual-media configuration according to configuration */
9526
9527         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9528                         MDIO_CTL_REG_84823_MEDIA, &val);
9529         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9530                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9531                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9532                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9533                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9534
9535         if (CHIP_IS_E3(bp)) {
9536                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9537                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9538         } else {
9539                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9540                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9541         }
9542
9543         actual_phy_selection = bnx2x_phy_selection(params);
9544
9545         switch (actual_phy_selection) {
9546         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9547                 /* Do nothing. Essentially this is like the priority copper */
9548                 break;
9549         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9550                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9551                 break;
9552         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9553                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9554                 break;
9555         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9556                 /* Do nothing here. The first PHY won't be initialized at all */
9557                 break;
9558         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9559                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9560                 initialize = 0;
9561                 break;
9562         }
9563         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9564                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9565
9566         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9567                          MDIO_CTL_REG_84823_MEDIA, val);
9568         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9569                    params->multi_phy_config, val);
9570
9571         /* AutogrEEEn */
9572         if (params->feature_config_flags &
9573                 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
9574                 /* Ensure that f/w is ready */
9575                 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9576                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9577                                         MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9578                         if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9579                                 break;
9580                         usleep_range(1000, 1000);
9581                 }
9582                 if (idx >= PHY84833_HDSHK_WAIT) {
9583                         DP(NETIF_MSG_LINK, "AutogrEEEn: FW not ready.\n");
9584                         return -EINVAL;
9585                 }
9586
9587                 /* Select EEE mode */
9588                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9589                                 MDIO_84833_TOP_CFG_SCRATCH_REG3,
9590                                 0x2);
9591
9592                 /* Set Idle and Latency */
9593                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9594                                 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9595                                 PHY84833_CONSTANT_LATENCY + 1);
9596
9597                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9598                                 MDIO_84833_TOP_CFG_DATA3_REG,
9599                                 PHY84833_CONSTANT_LATENCY + 1);
9600
9601                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9602                                 MDIO_84833_TOP_CFG_DATA4_REG,
9603                                 PHY84833_CONSTANT_LATENCY);
9604
9605                 /* Send EEE instruction to command register */
9606                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9607                                 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9608                                 PHY84833_DIAG_CMD_SET_EEE_MODE);
9609
9610                 /* Ensure that the command has completed */
9611                 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9612                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9613                                         MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9614                         if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9615                                 (val == PHY84833_CMD_COMPLETE_ERROR))
9616                                 break;
9617                         usleep_range(1000, 1000);
9618                 }
9619                 if ((idx >= PHY84833_HDSHK_WAIT) ||
9620                         (val == PHY84833_CMD_COMPLETE_ERROR)) {
9621                         DP(NETIF_MSG_LINK, "AutogrEEEn: command failed.\n");
9622                         return -EINVAL;
9623                 }
9624
9625                 /* Reset command handler */
9626                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9627                             MDIO_84833_TOP_CFG_SCRATCH_REG2,
9628                             PHY84833_CMD_CLEAR_COMPLETE);
9629         }
9630
9631         if (initialize)
9632                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9633         else
9634                 bnx2x_save_848xx_spirom_version(phy, params);
9635         /* 84833 PHY has a better feature and doesn't need to support this. */
9636         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9637                 cms_enable = REG_RD(bp, params->shmem_base +
9638                         offsetof(struct shmem_region,
9639                         dev_info.port_hw_config[params->port].default_cfg)) &
9640                         PORT_HW_CFG_ENABLE_CMS_MASK;
9641
9642                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9643                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9644                 if (cms_enable)
9645                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9646                 else
9647                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9648                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9649                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9650         }
9651
9652         return rc;
9653 }
9654
9655 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9656                                   struct link_params *params,
9657                                   struct link_vars *vars)
9658 {
9659         struct bnx2x *bp = params->bp;
9660         u16 val, val1, val2;
9661         u8 link_up = 0;
9662
9663
9664         /* Check 10G-BaseT link status */
9665         /* Check PMD signal ok */
9666         bnx2x_cl45_read(bp, phy,
9667                         MDIO_AN_DEVAD, 0xFFFA, &val1);
9668         bnx2x_cl45_read(bp, phy,
9669                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9670                         &val2);
9671         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9672
9673         /* Check link 10G */
9674         if (val2 & (1<<11)) {
9675                 vars->line_speed = SPEED_10000;
9676                 vars->duplex = DUPLEX_FULL;
9677                 link_up = 1;
9678                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9679         } else { /* Check Legacy speed link */
9680                 u16 legacy_status, legacy_speed;
9681
9682                 /* Enable expansion register 0x42 (Operation mode status) */
9683                 bnx2x_cl45_write(bp, phy,
9684                                  MDIO_AN_DEVAD,
9685                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9686
9687                 /* Get legacy speed operation status */
9688                 bnx2x_cl45_read(bp, phy,
9689                                 MDIO_AN_DEVAD,
9690                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9691                                 &legacy_status);
9692
9693                 DP(NETIF_MSG_LINK, "Legacy speed status"
9694                              " = 0x%x\n", legacy_status);
9695                 link_up = ((legacy_status & (1<<11)) == (1<<11));
9696                 if (link_up) {
9697                         legacy_speed = (legacy_status & (3<<9));
9698                         if (legacy_speed == (0<<9))
9699                                 vars->line_speed = SPEED_10;
9700                         else if (legacy_speed == (1<<9))
9701                                 vars->line_speed = SPEED_100;
9702                         else if (legacy_speed == (2<<9))
9703                                 vars->line_speed = SPEED_1000;
9704                         else /* Should not happen */
9705                                 vars->line_speed = 0;
9706
9707                         if (legacy_status & (1<<8))
9708                                 vars->duplex = DUPLEX_FULL;
9709                         else
9710                                 vars->duplex = DUPLEX_HALF;
9711
9712                         DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
9713                                    " is_duplex_full= %d\n", vars->line_speed,
9714                                    (vars->duplex == DUPLEX_FULL));
9715                         /* Check legacy speed AN resolution */
9716                         bnx2x_cl45_read(bp, phy,
9717                                         MDIO_AN_DEVAD,
9718                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9719                                         &val);
9720                         if (val & (1<<5))
9721                                 vars->link_status |=
9722                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9723                         bnx2x_cl45_read(bp, phy,
9724                                         MDIO_AN_DEVAD,
9725                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9726                                         &val);
9727                         if ((val & (1<<0)) == 0)
9728                                 vars->link_status |=
9729                                         LINK_STATUS_PARALLEL_DETECTION_USED;
9730                 }
9731         }
9732         if (link_up) {
9733                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9734                            vars->line_speed);
9735                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9736         }
9737
9738         return link_up;
9739 }
9740
9741
9742 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9743 {
9744         int status = 0;
9745         u32 spirom_ver;
9746         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9747         status = bnx2x_format_ver(spirom_ver, str, len);
9748         return status;
9749 }
9750
9751 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9752                                 struct link_params *params)
9753 {
9754         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9755                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9756         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9757                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9758 }
9759
9760 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9761                                         struct link_params *params)
9762 {
9763         bnx2x_cl45_write(params->bp, phy,
9764                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9765         bnx2x_cl45_write(params->bp, phy,
9766                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9767 }
9768
9769 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9770                                    struct link_params *params)
9771 {
9772         struct bnx2x *bp = params->bp;
9773         u8 port;
9774         u16 val16;
9775
9776         if (!(CHIP_IS_E1(bp)))
9777                 port = BP_PATH(bp);
9778         else
9779                 port = params->port;
9780
9781         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9782                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9783                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
9784                                port);
9785         } else {
9786                 bnx2x_cl45_read(bp, phy,
9787                                 MDIO_CTL_DEVAD,
9788                                 0x400f, &val16);
9789                 bnx2x_cl45_write(bp, phy,
9790                                 MDIO_PMA_DEVAD,
9791                                 MDIO_PMA_REG_CTRL, 0x800);
9792         }
9793 }
9794
9795 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
9796                                      struct link_params *params, u8 mode)
9797 {
9798         struct bnx2x *bp = params->bp;
9799         u16 val;
9800         u8 port;
9801
9802         if (!(CHIP_IS_E1(bp)))
9803                 port = BP_PATH(bp);
9804         else
9805                 port = params->port;
9806
9807         switch (mode) {
9808         case LED_MODE_OFF:
9809
9810                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9811
9812                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9813                     SHARED_HW_CFG_LED_EXTPHY1) {
9814
9815                         /* Set LED masks */
9816                         bnx2x_cl45_write(bp, phy,
9817                                         MDIO_PMA_DEVAD,
9818                                         MDIO_PMA_REG_8481_LED1_MASK,
9819                                         0x0);
9820
9821                         bnx2x_cl45_write(bp, phy,
9822                                         MDIO_PMA_DEVAD,
9823                                         MDIO_PMA_REG_8481_LED2_MASK,
9824                                         0x0);
9825
9826                         bnx2x_cl45_write(bp, phy,
9827                                         MDIO_PMA_DEVAD,
9828                                         MDIO_PMA_REG_8481_LED3_MASK,
9829                                         0x0);
9830
9831                         bnx2x_cl45_write(bp, phy,
9832                                         MDIO_PMA_DEVAD,
9833                                         MDIO_PMA_REG_8481_LED5_MASK,
9834                                         0x0);
9835
9836                 } else {
9837                         bnx2x_cl45_write(bp, phy,
9838                                          MDIO_PMA_DEVAD,
9839                                          MDIO_PMA_REG_8481_LED1_MASK,
9840                                          0x0);
9841                 }
9842                 break;
9843         case LED_MODE_FRONT_PANEL_OFF:
9844
9845                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
9846                    port);
9847
9848                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9849                     SHARED_HW_CFG_LED_EXTPHY1) {
9850
9851                         /* Set LED masks */
9852                         bnx2x_cl45_write(bp, phy,
9853                                          MDIO_PMA_DEVAD,
9854                                          MDIO_PMA_REG_8481_LED1_MASK,
9855                                          0x0);
9856
9857                         bnx2x_cl45_write(bp, phy,
9858                                          MDIO_PMA_DEVAD,
9859                                          MDIO_PMA_REG_8481_LED2_MASK,
9860                                          0x0);
9861
9862                         bnx2x_cl45_write(bp, phy,
9863                                          MDIO_PMA_DEVAD,
9864                                          MDIO_PMA_REG_8481_LED3_MASK,
9865                                          0x0);
9866
9867                         bnx2x_cl45_write(bp, phy,
9868                                          MDIO_PMA_DEVAD,
9869                                          MDIO_PMA_REG_8481_LED5_MASK,
9870                                          0x20);
9871
9872                 } else {
9873                         bnx2x_cl45_write(bp, phy,
9874                                          MDIO_PMA_DEVAD,
9875                                          MDIO_PMA_REG_8481_LED1_MASK,
9876                                          0x0);
9877                 }
9878                 break;
9879         case LED_MODE_ON:
9880
9881                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9882
9883                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9884                     SHARED_HW_CFG_LED_EXTPHY1) {
9885                         /* Set control reg */
9886                         bnx2x_cl45_read(bp, phy,
9887                                         MDIO_PMA_DEVAD,
9888                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9889                                         &val);
9890                         val &= 0x8000;
9891                         val |= 0x2492;
9892
9893                         bnx2x_cl45_write(bp, phy,
9894                                          MDIO_PMA_DEVAD,
9895                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
9896                                          val);
9897
9898                         /* Set LED masks */
9899                         bnx2x_cl45_write(bp, phy,
9900                                          MDIO_PMA_DEVAD,
9901                                          MDIO_PMA_REG_8481_LED1_MASK,
9902                                          0x0);
9903
9904                         bnx2x_cl45_write(bp, phy,
9905                                          MDIO_PMA_DEVAD,
9906                                          MDIO_PMA_REG_8481_LED2_MASK,
9907                                          0x20);
9908
9909                         bnx2x_cl45_write(bp, phy,
9910                                          MDIO_PMA_DEVAD,
9911                                          MDIO_PMA_REG_8481_LED3_MASK,
9912                                          0x20);
9913
9914                         bnx2x_cl45_write(bp, phy,
9915                                          MDIO_PMA_DEVAD,
9916                                          MDIO_PMA_REG_8481_LED5_MASK,
9917                                          0x0);
9918                 } else {
9919                         bnx2x_cl45_write(bp, phy,
9920                                          MDIO_PMA_DEVAD,
9921                                          MDIO_PMA_REG_8481_LED1_MASK,
9922                                          0x20);
9923                 }
9924                 break;
9925
9926         case LED_MODE_OPER:
9927
9928                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
9929
9930                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9931                     SHARED_HW_CFG_LED_EXTPHY1) {
9932
9933                         /* Set control reg */
9934                         bnx2x_cl45_read(bp, phy,
9935                                         MDIO_PMA_DEVAD,
9936                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9937                                         &val);
9938
9939                         if (!((val &
9940                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
9941                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
9942                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
9943                                 bnx2x_cl45_write(bp, phy,
9944                                                  MDIO_PMA_DEVAD,
9945                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
9946                                                  0xa492);
9947                         }
9948
9949                         /* Set LED masks */
9950                         bnx2x_cl45_write(bp, phy,
9951                                          MDIO_PMA_DEVAD,
9952                                          MDIO_PMA_REG_8481_LED1_MASK,
9953                                          0x10);
9954
9955                         bnx2x_cl45_write(bp, phy,
9956                                          MDIO_PMA_DEVAD,
9957                                          MDIO_PMA_REG_8481_LED2_MASK,
9958                                          0x80);
9959
9960                         bnx2x_cl45_write(bp, phy,
9961                                          MDIO_PMA_DEVAD,
9962                                          MDIO_PMA_REG_8481_LED3_MASK,
9963                                          0x98);
9964
9965                         bnx2x_cl45_write(bp, phy,
9966                                          MDIO_PMA_DEVAD,
9967                                          MDIO_PMA_REG_8481_LED5_MASK,
9968                                          0x40);
9969
9970                 } else {
9971                         bnx2x_cl45_write(bp, phy,
9972                                          MDIO_PMA_DEVAD,
9973                                          MDIO_PMA_REG_8481_LED1_MASK,
9974                                          0x80);
9975
9976                         /* Tell LED3 to blink on source */
9977                         bnx2x_cl45_read(bp, phy,
9978                                         MDIO_PMA_DEVAD,
9979                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9980                                         &val);
9981                         val &= ~(7<<6);
9982                         val |= (1<<6); /* A83B[8:6]= 1 */
9983                         bnx2x_cl45_write(bp, phy,
9984                                          MDIO_PMA_DEVAD,
9985                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
9986                                          val);
9987                 }
9988                 break;
9989         }
9990
9991         /*
9992          * This is a workaround for E3+84833 until autoneg
9993          * restart is fixed in f/w
9994          */
9995         if (CHIP_IS_E3(bp)) {
9996                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
9997                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
9998         }
9999 }
10000
10001 /******************************************************************/
10002 /*                      54618SE PHY SECTION                       */
10003 /******************************************************************/
10004 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10005                                                struct link_params *params,
10006                                                struct link_vars *vars)
10007 {
10008         struct bnx2x *bp = params->bp;
10009         u8 port;
10010         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10011         u32 cfg_pin;
10012
10013         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10014         usleep_range(1000, 1000);
10015
10016         /* This works with E3 only, no need to check the chip
10017            before determining the port. */
10018         port = params->port;
10019
10020         cfg_pin = (REG_RD(bp, params->shmem_base +
10021                         offsetof(struct shmem_region,
10022                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10023                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10024                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10025
10026         /* Drive pin high to bring the GPHY out of reset. */
10027         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10028
10029         /* wait for GPHY to reset */
10030         msleep(50);
10031
10032         /* reset phy */
10033         bnx2x_cl22_write(bp, phy,
10034                          MDIO_PMA_REG_CTRL, 0x8000);
10035         bnx2x_wait_reset_complete(bp, phy, params);
10036
10037         /*wait for GPHY to reset */
10038         msleep(50);
10039
10040         /* Configure LED4: set to INTR (0x6). */
10041         /* Accessing shadow register 0xe. */
10042         bnx2x_cl22_write(bp, phy,
10043                         MDIO_REG_GPHY_SHADOW,
10044                         MDIO_REG_GPHY_SHADOW_LED_SEL2);
10045         bnx2x_cl22_read(bp, phy,
10046                         MDIO_REG_GPHY_SHADOW,
10047                         &temp);
10048         temp &= ~(0xf << 4);
10049         temp |= (0x6 << 4);
10050         bnx2x_cl22_write(bp, phy,
10051                         MDIO_REG_GPHY_SHADOW,
10052                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10053         /* Configure INTR based on link status change. */
10054         bnx2x_cl22_write(bp, phy,
10055                         MDIO_REG_INTR_MASK,
10056                         ~MDIO_REG_INTR_MASK_LINK_STATUS);
10057
10058         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10059         bnx2x_cl22_write(bp, phy,
10060                         MDIO_REG_GPHY_SHADOW,
10061                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10062         bnx2x_cl22_read(bp, phy,
10063                         MDIO_REG_GPHY_SHADOW,
10064                         &temp);
10065         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10066         bnx2x_cl22_write(bp, phy,
10067                         MDIO_REG_GPHY_SHADOW,
10068                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10069
10070         /* Set up fc */
10071         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10072         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10073         fc_val = 0;
10074         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10075                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10076                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10077
10078         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10079                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10080                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10081
10082         /* read all advertisement */
10083         bnx2x_cl22_read(bp, phy,
10084                         0x09,
10085                         &an_1000_val);
10086
10087         bnx2x_cl22_read(bp, phy,
10088                         0x04,
10089                         &an_10_100_val);
10090
10091         bnx2x_cl22_read(bp, phy,
10092                         MDIO_PMA_REG_CTRL,
10093                         &autoneg_val);
10094
10095         /* Disable forced speed */
10096         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10097         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10098                            (1<<11));
10099
10100         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10101                         (phy->speed_cap_mask &
10102                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10103                         (phy->req_line_speed == SPEED_1000)) {
10104                 an_1000_val |= (1<<8);
10105                 autoneg_val |= (1<<9 | 1<<12);
10106                 if (phy->req_duplex == DUPLEX_FULL)
10107                         an_1000_val |= (1<<9);
10108                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10109         } else
10110                 an_1000_val &= ~((1<<8) | (1<<9));
10111
10112         bnx2x_cl22_write(bp, phy,
10113                         0x09,
10114                         an_1000_val);
10115         bnx2x_cl22_read(bp, phy,
10116                         0x09,
10117                         &an_1000_val);
10118
10119         /* set 100 speed advertisement */
10120         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10121                         (phy->speed_cap_mask &
10122                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10123                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10124                 an_10_100_val |= (1<<7);
10125                 /* Enable autoneg and restart autoneg for legacy speeds */
10126                 autoneg_val |= (1<<9 | 1<<12);
10127
10128                 if (phy->req_duplex == DUPLEX_FULL)
10129                         an_10_100_val |= (1<<8);
10130                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10131         }
10132
10133         /* set 10 speed advertisement */
10134         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10135                         (phy->speed_cap_mask &
10136                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10137                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10138                 an_10_100_val |= (1<<5);
10139                 autoneg_val |= (1<<9 | 1<<12);
10140                 if (phy->req_duplex == DUPLEX_FULL)
10141                         an_10_100_val |= (1<<6);
10142                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10143         }
10144
10145         /* Only 10/100 are allowed to work in FORCE mode */
10146         if (phy->req_line_speed == SPEED_100) {
10147                 autoneg_val |= (1<<13);
10148                 /* Enabled AUTO-MDIX when autoneg is disabled */
10149                 bnx2x_cl22_write(bp, phy,
10150                                 0x18,
10151                                 (1<<15 | 1<<9 | 7<<0));
10152                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10153         }
10154         if (phy->req_line_speed == SPEED_10) {
10155                 /* Enabled AUTO-MDIX when autoneg is disabled */
10156                 bnx2x_cl22_write(bp, phy,
10157                                 0x18,
10158                                 (1<<15 | 1<<9 | 7<<0));
10159                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10160         }
10161
10162         /* Check if we should turn on Auto-GrEEEn */
10163         bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10164         if (temp == MDIO_REG_GPHY_ID_54618SE) {
10165                 if (params->feature_config_flags &
10166                     FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10167                         temp = 6;
10168                         DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10169                 } else {
10170                         temp = 0;
10171                         DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10172                 }
10173                 bnx2x_cl22_write(bp, phy,
10174                                  MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10175                 bnx2x_cl22_write(bp, phy,
10176                                  MDIO_REG_GPHY_CL45_DATA_REG,
10177                                  MDIO_REG_GPHY_EEE_ADV);
10178                 bnx2x_cl22_write(bp, phy,
10179                                  MDIO_REG_GPHY_CL45_ADDR_REG,
10180                                  (0x1 << 14) | MDIO_AN_DEVAD);
10181                 bnx2x_cl22_write(bp, phy,
10182                                  MDIO_REG_GPHY_CL45_DATA_REG,
10183                                  temp);
10184         }
10185
10186         bnx2x_cl22_write(bp, phy,
10187                         0x04,
10188                         an_10_100_val | fc_val);
10189
10190         if (phy->req_duplex == DUPLEX_FULL)
10191                 autoneg_val |= (1<<8);
10192
10193         bnx2x_cl22_write(bp, phy,
10194                         MDIO_PMA_REG_CTRL, autoneg_val);
10195
10196         return 0;
10197 }
10198
10199 static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
10200                                        struct link_params *params, u8 mode)
10201 {
10202         struct bnx2x *bp = params->bp;
10203         DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
10204         switch (mode) {
10205         case LED_MODE_FRONT_PANEL_OFF:
10206         case LED_MODE_OFF:
10207         case LED_MODE_OPER:
10208         case LED_MODE_ON:
10209         default:
10210                 break;
10211         }
10212         return;
10213 }
10214
10215 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10216                                      struct link_params *params)
10217 {
10218         struct bnx2x *bp = params->bp;
10219         u32 cfg_pin;
10220         u8 port;
10221
10222         /*
10223          * In case of no EPIO routed to reset the GPHY, put it
10224          * in low power mode.
10225          */
10226         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10227         /*
10228          * This works with E3 only, no need to check the chip
10229          * before determining the port.
10230          */
10231         port = params->port;
10232         cfg_pin = (REG_RD(bp, params->shmem_base +
10233                         offsetof(struct shmem_region,
10234                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10235                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10236                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10237
10238         /* Drive pin low to put GPHY in reset. */
10239         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10240 }
10241
10242 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10243                                     struct link_params *params,
10244                                     struct link_vars *vars)
10245 {
10246         struct bnx2x *bp = params->bp;
10247         u16 val;
10248         u8 link_up = 0;
10249         u16 legacy_status, legacy_speed;
10250
10251         /* Get speed operation status */
10252         bnx2x_cl22_read(bp, phy,
10253                         0x19,
10254                         &legacy_status);
10255         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10256
10257         /* Read status to clear the PHY interrupt. */
10258         bnx2x_cl22_read(bp, phy,
10259                         MDIO_REG_INTR_STATUS,
10260                         &val);
10261
10262         link_up = ((legacy_status & (1<<2)) == (1<<2));
10263
10264         if (link_up) {
10265                 legacy_speed = (legacy_status & (7<<8));
10266                 if (legacy_speed == (7<<8)) {
10267                         vars->line_speed = SPEED_1000;
10268                         vars->duplex = DUPLEX_FULL;
10269                 } else if (legacy_speed == (6<<8)) {
10270                         vars->line_speed = SPEED_1000;
10271                         vars->duplex = DUPLEX_HALF;
10272                 } else if (legacy_speed == (5<<8)) {
10273                         vars->line_speed = SPEED_100;
10274                         vars->duplex = DUPLEX_FULL;
10275                 }
10276                 /* Omitting 100Base-T4 for now */
10277                 else if (legacy_speed == (3<<8)) {
10278                         vars->line_speed = SPEED_100;
10279                         vars->duplex = DUPLEX_HALF;
10280                 } else if (legacy_speed == (2<<8)) {
10281                         vars->line_speed = SPEED_10;
10282                         vars->duplex = DUPLEX_FULL;
10283                 } else if (legacy_speed == (1<<8)) {
10284                         vars->line_speed = SPEED_10;
10285                         vars->duplex = DUPLEX_HALF;
10286                 } else /* Should not happen */
10287                         vars->line_speed = 0;
10288
10289                 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
10290                            " is_duplex_full= %d\n", vars->line_speed,
10291                            (vars->duplex == DUPLEX_FULL));
10292
10293                 /* Check legacy speed AN resolution */
10294                 bnx2x_cl22_read(bp, phy,
10295                                 0x01,
10296                                 &val);
10297                 if (val & (1<<5))
10298                         vars->link_status |=
10299                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10300                 bnx2x_cl22_read(bp, phy,
10301                                 0x06,
10302                                 &val);
10303                 if ((val & (1<<0)) == 0)
10304                         vars->link_status |=
10305                                 LINK_STATUS_PARALLEL_DETECTION_USED;
10306
10307                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10308                            vars->line_speed);
10309
10310                 /* Report whether EEE is resolved. */
10311                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10312                 if (val == MDIO_REG_GPHY_ID_54618SE) {
10313                         if (vars->link_status &
10314                             LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10315                                 val = 0;
10316                         else {
10317                                 bnx2x_cl22_write(bp, phy,
10318                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10319                                         MDIO_AN_DEVAD);
10320                                 bnx2x_cl22_write(bp, phy,
10321                                         MDIO_REG_GPHY_CL45_DATA_REG,
10322                                         MDIO_REG_GPHY_EEE_RESOLVED);
10323                                 bnx2x_cl22_write(bp, phy,
10324                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10325                                         (0x1 << 14) | MDIO_AN_DEVAD);
10326                                 bnx2x_cl22_read(bp, phy,
10327                                         MDIO_REG_GPHY_CL45_DATA_REG,
10328                                         &val);
10329                         }
10330                         DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10331                 }
10332
10333                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10334         }
10335         return link_up;
10336 }
10337
10338 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10339                                           struct link_params *params)
10340 {
10341         struct bnx2x *bp = params->bp;
10342         u16 val;
10343         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10344
10345         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10346
10347         /* Enable master/slave manual mmode and set to master */
10348         /* mii write 9 [bits set 11 12] */
10349         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10350
10351         /* forced 1G and disable autoneg */
10352         /* set val [mii read 0] */
10353         /* set val [expr $val & [bits clear 6 12 13]] */
10354         /* set val [expr $val | [bits set 6 8]] */
10355         /* mii write 0 $val */
10356         bnx2x_cl22_read(bp, phy, 0x00, &val);
10357         val &= ~((1<<6) | (1<<12) | (1<<13));
10358         val |= (1<<6) | (1<<8);
10359         bnx2x_cl22_write(bp, phy, 0x00, val);
10360
10361         /* Set external loopback and Tx using 6dB coding */
10362         /* mii write 0x18 7 */
10363         /* set val [mii read 0x18] */
10364         /* mii write 0x18 [expr $val | [bits set 10 15]] */
10365         bnx2x_cl22_write(bp, phy, 0x18, 7);
10366         bnx2x_cl22_read(bp, phy, 0x18, &val);
10367         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10368
10369         /* This register opens the gate for the UMAC despite its name */
10370         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10371
10372         /*
10373          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10374          * length used by the MAC receive logic to check frames.
10375          */
10376         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10377 }
10378
10379 /******************************************************************/
10380 /*                      SFX7101 PHY SECTION                       */
10381 /******************************************************************/
10382 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10383                                        struct link_params *params)
10384 {
10385         struct bnx2x *bp = params->bp;
10386         /* SFX7101_XGXS_TEST1 */
10387         bnx2x_cl45_write(bp, phy,
10388                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10389 }
10390
10391 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10392                                   struct link_params *params,
10393                                   struct link_vars *vars)
10394 {
10395         u16 fw_ver1, fw_ver2, val;
10396         struct bnx2x *bp = params->bp;
10397         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10398
10399         /* Restore normal power mode*/
10400         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10401                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10402         /* HW reset */
10403         bnx2x_ext_phy_hw_reset(bp, params->port);
10404         bnx2x_wait_reset_complete(bp, phy, params);
10405
10406         bnx2x_cl45_write(bp, phy,
10407                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10408         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10409         bnx2x_cl45_write(bp, phy,
10410                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10411
10412         bnx2x_ext_phy_set_pause(params, phy, vars);
10413         /* Restart autoneg */
10414         bnx2x_cl45_read(bp, phy,
10415                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10416         val |= 0x200;
10417         bnx2x_cl45_write(bp, phy,
10418                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10419
10420         /* Save spirom version */
10421         bnx2x_cl45_read(bp, phy,
10422                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10423
10424         bnx2x_cl45_read(bp, phy,
10425                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10426         bnx2x_save_spirom_version(bp, params->port,
10427                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10428         return 0;
10429 }
10430
10431 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10432                                  struct link_params *params,
10433                                  struct link_vars *vars)
10434 {
10435         struct bnx2x *bp = params->bp;
10436         u8 link_up;
10437         u16 val1, val2;
10438         bnx2x_cl45_read(bp, phy,
10439                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10440         bnx2x_cl45_read(bp, phy,
10441                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10442         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10443                    val2, val1);
10444         bnx2x_cl45_read(bp, phy,
10445                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10446         bnx2x_cl45_read(bp, phy,
10447                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10448         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10449                    val2, val1);
10450         link_up = ((val1 & 4) == 4);
10451         /* if link is up print the AN outcome of the SFX7101 PHY */
10452         if (link_up) {
10453                 bnx2x_cl45_read(bp, phy,
10454                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10455                                 &val2);
10456                 vars->line_speed = SPEED_10000;
10457                 vars->duplex = DUPLEX_FULL;
10458                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10459                            val2, (val2 & (1<<14)));
10460                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10461                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10462         }
10463         return link_up;
10464 }
10465
10466 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10467 {
10468         if (*len < 5)
10469                 return -EINVAL;
10470         str[0] = (spirom_ver & 0xFF);
10471         str[1] = (spirom_ver & 0xFF00) >> 8;
10472         str[2] = (spirom_ver & 0xFF0000) >> 16;
10473         str[3] = (spirom_ver & 0xFF000000) >> 24;
10474         str[4] = '\0';
10475         *len -= 5;
10476         return 0;
10477 }
10478
10479 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10480 {
10481         u16 val, cnt;
10482
10483         bnx2x_cl45_read(bp, phy,
10484                         MDIO_PMA_DEVAD,
10485                         MDIO_PMA_REG_7101_RESET, &val);
10486
10487         for (cnt = 0; cnt < 10; cnt++) {
10488                 msleep(50);
10489                 /* Writes a self-clearing reset */
10490                 bnx2x_cl45_write(bp, phy,
10491                                  MDIO_PMA_DEVAD,
10492                                  MDIO_PMA_REG_7101_RESET,
10493                                  (val | (1<<15)));
10494                 /* Wait for clear */
10495                 bnx2x_cl45_read(bp, phy,
10496                                 MDIO_PMA_DEVAD,
10497                                 MDIO_PMA_REG_7101_RESET, &val);
10498
10499                 if ((val & (1<<15)) == 0)
10500                         break;
10501         }
10502 }
10503
10504 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10505                                 struct link_params *params) {
10506         /* Low power mode is controlled by GPIO 2 */
10507         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10508                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10509         /* The PHY reset is controlled by GPIO 1 */
10510         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10511                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10512 }
10513
10514 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10515                                     struct link_params *params, u8 mode)
10516 {
10517         u16 val = 0;
10518         struct bnx2x *bp = params->bp;
10519         switch (mode) {
10520         case LED_MODE_FRONT_PANEL_OFF:
10521         case LED_MODE_OFF:
10522                 val = 2;
10523                 break;
10524         case LED_MODE_ON:
10525                 val = 1;
10526                 break;
10527         case LED_MODE_OPER:
10528                 val = 0;
10529                 break;
10530         }
10531         bnx2x_cl45_write(bp, phy,
10532                          MDIO_PMA_DEVAD,
10533                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
10534                          val);
10535 }
10536
10537 /******************************************************************/
10538 /*                      STATIC PHY DECLARATION                    */
10539 /******************************************************************/
10540
10541 static struct bnx2x_phy phy_null = {
10542         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10543         .addr           = 0,
10544         .def_md_devad   = 0,
10545         .flags          = FLAGS_INIT_XGXS_FIRST,
10546         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10547         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10548         .mdio_ctrl      = 0,
10549         .supported      = 0,
10550         .media_type     = ETH_PHY_NOT_PRESENT,
10551         .ver_addr       = 0,
10552         .req_flow_ctrl  = 0,
10553         .req_line_speed = 0,
10554         .speed_cap_mask = 0,
10555         .req_duplex     = 0,
10556         .rsrv           = 0,
10557         .config_init    = (config_init_t)NULL,
10558         .read_status    = (read_status_t)NULL,
10559         .link_reset     = (link_reset_t)NULL,
10560         .config_loopback = (config_loopback_t)NULL,
10561         .format_fw_ver  = (format_fw_ver_t)NULL,
10562         .hw_reset       = (hw_reset_t)NULL,
10563         .set_link_led   = (set_link_led_t)NULL,
10564         .phy_specific_func = (phy_specific_func_t)NULL
10565 };
10566
10567 static struct bnx2x_phy phy_serdes = {
10568         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10569         .addr           = 0xff,
10570         .def_md_devad   = 0,
10571         .flags          = 0,
10572         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10573         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10574         .mdio_ctrl      = 0,
10575         .supported      = (SUPPORTED_10baseT_Half |
10576                            SUPPORTED_10baseT_Full |
10577                            SUPPORTED_100baseT_Half |
10578                            SUPPORTED_100baseT_Full |
10579                            SUPPORTED_1000baseT_Full |
10580                            SUPPORTED_2500baseX_Full |
10581                            SUPPORTED_TP |
10582                            SUPPORTED_Autoneg |
10583                            SUPPORTED_Pause |
10584                            SUPPORTED_Asym_Pause),
10585         .media_type     = ETH_PHY_BASE_T,
10586         .ver_addr       = 0,
10587         .req_flow_ctrl  = 0,
10588         .req_line_speed = 0,
10589         .speed_cap_mask = 0,
10590         .req_duplex     = 0,
10591         .rsrv           = 0,
10592         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10593         .read_status    = (read_status_t)bnx2x_link_settings_status,
10594         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10595         .config_loopback = (config_loopback_t)NULL,
10596         .format_fw_ver  = (format_fw_ver_t)NULL,
10597         .hw_reset       = (hw_reset_t)NULL,
10598         .set_link_led   = (set_link_led_t)NULL,
10599         .phy_specific_func = (phy_specific_func_t)NULL
10600 };
10601
10602 static struct bnx2x_phy phy_xgxs = {
10603         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10604         .addr           = 0xff,
10605         .def_md_devad   = 0,
10606         .flags          = 0,
10607         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10608         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10609         .mdio_ctrl      = 0,
10610         .supported      = (SUPPORTED_10baseT_Half |
10611                            SUPPORTED_10baseT_Full |
10612                            SUPPORTED_100baseT_Half |
10613                            SUPPORTED_100baseT_Full |
10614                            SUPPORTED_1000baseT_Full |
10615                            SUPPORTED_2500baseX_Full |
10616                            SUPPORTED_10000baseT_Full |
10617                            SUPPORTED_FIBRE |
10618                            SUPPORTED_Autoneg |
10619                            SUPPORTED_Pause |
10620                            SUPPORTED_Asym_Pause),
10621         .media_type     = ETH_PHY_CX4,
10622         .ver_addr       = 0,
10623         .req_flow_ctrl  = 0,
10624         .req_line_speed = 0,
10625         .speed_cap_mask = 0,
10626         .req_duplex     = 0,
10627         .rsrv           = 0,
10628         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10629         .read_status    = (read_status_t)bnx2x_link_settings_status,
10630         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10631         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10632         .format_fw_ver  = (format_fw_ver_t)NULL,
10633         .hw_reset       = (hw_reset_t)NULL,
10634         .set_link_led   = (set_link_led_t)NULL,
10635         .phy_specific_func = (phy_specific_func_t)NULL
10636 };
10637 static struct bnx2x_phy phy_warpcore = {
10638         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10639         .addr           = 0xff,
10640         .def_md_devad   = 0,
10641         .flags          = (FLAGS_HW_LOCK_REQUIRED |
10642                            FLAGS_TX_ERROR_CHECK),
10643         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10644         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10645         .mdio_ctrl      = 0,
10646         .supported      = (SUPPORTED_10baseT_Half |
10647                              SUPPORTED_10baseT_Full |
10648                              SUPPORTED_100baseT_Half |
10649                              SUPPORTED_100baseT_Full |
10650                              SUPPORTED_1000baseT_Full |
10651                              SUPPORTED_10000baseT_Full |
10652                              SUPPORTED_20000baseKR2_Full |
10653                              SUPPORTED_20000baseMLD2_Full |
10654                              SUPPORTED_FIBRE |
10655                              SUPPORTED_Autoneg |
10656                              SUPPORTED_Pause |
10657                              SUPPORTED_Asym_Pause),
10658         .media_type     = ETH_PHY_UNSPECIFIED,
10659         .ver_addr       = 0,
10660         .req_flow_ctrl  = 0,
10661         .req_line_speed = 0,
10662         .speed_cap_mask = 0,
10663         /* req_duplex = */0,
10664         /* rsrv = */0,
10665         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
10666         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
10667         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
10668         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10669         .format_fw_ver  = (format_fw_ver_t)NULL,
10670         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
10671         .set_link_led   = (set_link_led_t)NULL,
10672         .phy_specific_func = (phy_specific_func_t)NULL
10673 };
10674
10675
10676 static struct bnx2x_phy phy_7101 = {
10677         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10678         .addr           = 0xff,
10679         .def_md_devad   = 0,
10680         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10681         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10682         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10683         .mdio_ctrl      = 0,
10684         .supported      = (SUPPORTED_10000baseT_Full |
10685                            SUPPORTED_TP |
10686                            SUPPORTED_Autoneg |
10687                            SUPPORTED_Pause |
10688                            SUPPORTED_Asym_Pause),
10689         .media_type     = ETH_PHY_BASE_T,
10690         .ver_addr       = 0,
10691         .req_flow_ctrl  = 0,
10692         .req_line_speed = 0,
10693         .speed_cap_mask = 0,
10694         .req_duplex     = 0,
10695         .rsrv           = 0,
10696         .config_init    = (config_init_t)bnx2x_7101_config_init,
10697         .read_status    = (read_status_t)bnx2x_7101_read_status,
10698         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10699         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10700         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
10701         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
10702         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
10703         .phy_specific_func = (phy_specific_func_t)NULL
10704 };
10705 static struct bnx2x_phy phy_8073 = {
10706         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10707         .addr           = 0xff,
10708         .def_md_devad   = 0,
10709         .flags          = FLAGS_HW_LOCK_REQUIRED,
10710         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10711         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10712         .mdio_ctrl      = 0,
10713         .supported      = (SUPPORTED_10000baseT_Full |
10714                            SUPPORTED_2500baseX_Full |
10715                            SUPPORTED_1000baseT_Full |
10716                            SUPPORTED_FIBRE |
10717                            SUPPORTED_Autoneg |
10718                            SUPPORTED_Pause |
10719                            SUPPORTED_Asym_Pause),
10720         .media_type     = ETH_PHY_KR,
10721         .ver_addr       = 0,
10722         .req_flow_ctrl  = 0,
10723         .req_line_speed = 0,
10724         .speed_cap_mask = 0,
10725         .req_duplex     = 0,
10726         .rsrv           = 0,
10727         .config_init    = (config_init_t)bnx2x_8073_config_init,
10728         .read_status    = (read_status_t)bnx2x_8073_read_status,
10729         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
10730         .config_loopback = (config_loopback_t)NULL,
10731         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10732         .hw_reset       = (hw_reset_t)NULL,
10733         .set_link_led   = (set_link_led_t)NULL,
10734         .phy_specific_func = (phy_specific_func_t)NULL
10735 };
10736 static struct bnx2x_phy phy_8705 = {
10737         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10738         .addr           = 0xff,
10739         .def_md_devad   = 0,
10740         .flags          = FLAGS_INIT_XGXS_FIRST,
10741         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10742         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10743         .mdio_ctrl      = 0,
10744         .supported      = (SUPPORTED_10000baseT_Full |
10745                            SUPPORTED_FIBRE |
10746                            SUPPORTED_Pause |
10747                            SUPPORTED_Asym_Pause),
10748         .media_type     = ETH_PHY_XFP_FIBER,
10749         .ver_addr       = 0,
10750         .req_flow_ctrl  = 0,
10751         .req_line_speed = 0,
10752         .speed_cap_mask = 0,
10753         .req_duplex     = 0,
10754         .rsrv           = 0,
10755         .config_init    = (config_init_t)bnx2x_8705_config_init,
10756         .read_status    = (read_status_t)bnx2x_8705_read_status,
10757         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10758         .config_loopback = (config_loopback_t)NULL,
10759         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
10760         .hw_reset       = (hw_reset_t)NULL,
10761         .set_link_led   = (set_link_led_t)NULL,
10762         .phy_specific_func = (phy_specific_func_t)NULL
10763 };
10764 static struct bnx2x_phy phy_8706 = {
10765         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
10766         .addr           = 0xff,
10767         .def_md_devad   = 0,
10768         .flags          = (FLAGS_INIT_XGXS_FIRST |
10769                            FLAGS_TX_ERROR_CHECK),
10770         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10771         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10772         .mdio_ctrl      = 0,
10773         .supported      = (SUPPORTED_10000baseT_Full |
10774                            SUPPORTED_1000baseT_Full |
10775                            SUPPORTED_FIBRE |
10776                            SUPPORTED_Pause |
10777                            SUPPORTED_Asym_Pause),
10778         .media_type     = ETH_PHY_SFP_FIBER,
10779         .ver_addr       = 0,
10780         .req_flow_ctrl  = 0,
10781         .req_line_speed = 0,
10782         .speed_cap_mask = 0,
10783         .req_duplex     = 0,
10784         .rsrv           = 0,
10785         .config_init    = (config_init_t)bnx2x_8706_config_init,
10786         .read_status    = (read_status_t)bnx2x_8706_read_status,
10787         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10788         .config_loopback = (config_loopback_t)NULL,
10789         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10790         .hw_reset       = (hw_reset_t)NULL,
10791         .set_link_led   = (set_link_led_t)NULL,
10792         .phy_specific_func = (phy_specific_func_t)NULL
10793 };
10794
10795 static struct bnx2x_phy phy_8726 = {
10796         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
10797         .addr           = 0xff,
10798         .def_md_devad   = 0,
10799         .flags          = (FLAGS_HW_LOCK_REQUIRED |
10800                            FLAGS_INIT_XGXS_FIRST |
10801                            FLAGS_TX_ERROR_CHECK),
10802         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10803         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10804         .mdio_ctrl      = 0,
10805         .supported      = (SUPPORTED_10000baseT_Full |
10806                            SUPPORTED_1000baseT_Full |
10807                            SUPPORTED_Autoneg |
10808                            SUPPORTED_FIBRE |
10809                            SUPPORTED_Pause |
10810                            SUPPORTED_Asym_Pause),
10811         .media_type     = ETH_PHY_NOT_PRESENT,
10812         .ver_addr       = 0,
10813         .req_flow_ctrl  = 0,
10814         .req_line_speed = 0,
10815         .speed_cap_mask = 0,
10816         .req_duplex     = 0,
10817         .rsrv           = 0,
10818         .config_init    = (config_init_t)bnx2x_8726_config_init,
10819         .read_status    = (read_status_t)bnx2x_8726_read_status,
10820         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
10821         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
10822         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10823         .hw_reset       = (hw_reset_t)NULL,
10824         .set_link_led   = (set_link_led_t)NULL,
10825         .phy_specific_func = (phy_specific_func_t)NULL
10826 };
10827
10828 static struct bnx2x_phy phy_8727 = {
10829         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
10830         .addr           = 0xff,
10831         .def_md_devad   = 0,
10832         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
10833                            FLAGS_TX_ERROR_CHECK),
10834         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10835         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10836         .mdio_ctrl      = 0,
10837         .supported      = (SUPPORTED_10000baseT_Full |
10838                            SUPPORTED_1000baseT_Full |
10839                            SUPPORTED_FIBRE |
10840                            SUPPORTED_Pause |
10841                            SUPPORTED_Asym_Pause),
10842         .media_type     = ETH_PHY_NOT_PRESENT,
10843         .ver_addr       = 0,
10844         .req_flow_ctrl  = 0,
10845         .req_line_speed = 0,
10846         .speed_cap_mask = 0,
10847         .req_duplex     = 0,
10848         .rsrv           = 0,
10849         .config_init    = (config_init_t)bnx2x_8727_config_init,
10850         .read_status    = (read_status_t)bnx2x_8727_read_status,
10851         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
10852         .config_loopback = (config_loopback_t)NULL,
10853         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10854         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
10855         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
10856         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
10857 };
10858 static struct bnx2x_phy phy_8481 = {
10859         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
10860         .addr           = 0xff,
10861         .def_md_devad   = 0,
10862         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10863                           FLAGS_REARM_LATCH_SIGNAL,
10864         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10865         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10866         .mdio_ctrl      = 0,
10867         .supported      = (SUPPORTED_10baseT_Half |
10868                            SUPPORTED_10baseT_Full |
10869                            SUPPORTED_100baseT_Half |
10870                            SUPPORTED_100baseT_Full |
10871                            SUPPORTED_1000baseT_Full |
10872                            SUPPORTED_10000baseT_Full |
10873                            SUPPORTED_TP |
10874                            SUPPORTED_Autoneg |
10875                            SUPPORTED_Pause |
10876                            SUPPORTED_Asym_Pause),
10877         .media_type     = ETH_PHY_BASE_T,
10878         .ver_addr       = 0,
10879         .req_flow_ctrl  = 0,
10880         .req_line_speed = 0,
10881         .speed_cap_mask = 0,
10882         .req_duplex     = 0,
10883         .rsrv           = 0,
10884         .config_init    = (config_init_t)bnx2x_8481_config_init,
10885         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10886         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
10887         .config_loopback = (config_loopback_t)NULL,
10888         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10889         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
10890         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10891         .phy_specific_func = (phy_specific_func_t)NULL
10892 };
10893
10894 static struct bnx2x_phy phy_84823 = {
10895         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
10896         .addr           = 0xff,
10897         .def_md_devad   = 0,
10898         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10899                           FLAGS_REARM_LATCH_SIGNAL,
10900         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10901         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10902         .mdio_ctrl      = 0,
10903         .supported      = (SUPPORTED_10baseT_Half |
10904                            SUPPORTED_10baseT_Full |
10905                            SUPPORTED_100baseT_Half |
10906                            SUPPORTED_100baseT_Full |
10907                            SUPPORTED_1000baseT_Full |
10908                            SUPPORTED_10000baseT_Full |
10909                            SUPPORTED_TP |
10910                            SUPPORTED_Autoneg |
10911                            SUPPORTED_Pause |
10912                            SUPPORTED_Asym_Pause),
10913         .media_type     = ETH_PHY_BASE_T,
10914         .ver_addr       = 0,
10915         .req_flow_ctrl  = 0,
10916         .req_line_speed = 0,
10917         .speed_cap_mask = 0,
10918         .req_duplex     = 0,
10919         .rsrv           = 0,
10920         .config_init    = (config_init_t)bnx2x_848x3_config_init,
10921         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10922         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
10923         .config_loopback = (config_loopback_t)NULL,
10924         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10925         .hw_reset       = (hw_reset_t)NULL,
10926         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10927         .phy_specific_func = (phy_specific_func_t)NULL
10928 };
10929
10930 static struct bnx2x_phy phy_84833 = {
10931         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
10932         .addr           = 0xff,
10933         .def_md_devad   = 0,
10934         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10935                             FLAGS_REARM_LATCH_SIGNAL,
10936         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10937         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10938         .mdio_ctrl      = 0,
10939         .supported      = (SUPPORTED_100baseT_Half |
10940                            SUPPORTED_100baseT_Full |
10941                            SUPPORTED_1000baseT_Full |
10942                            SUPPORTED_10000baseT_Full |
10943                            SUPPORTED_TP |
10944                            SUPPORTED_Autoneg |
10945                            SUPPORTED_Pause |
10946                            SUPPORTED_Asym_Pause),
10947         .media_type     = ETH_PHY_BASE_T,
10948         .ver_addr       = 0,
10949         .req_flow_ctrl  = 0,
10950         .req_line_speed = 0,
10951         .speed_cap_mask = 0,
10952         .req_duplex     = 0,
10953         .rsrv           = 0,
10954         .config_init    = (config_init_t)bnx2x_848x3_config_init,
10955         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10956         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
10957         .config_loopback = (config_loopback_t)NULL,
10958         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10959         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
10960         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10961         .phy_specific_func = (phy_specific_func_t)NULL
10962 };
10963
10964 static struct bnx2x_phy phy_54618se = {
10965         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
10966         .addr           = 0xff,
10967         .def_md_devad   = 0,
10968         .flags          = FLAGS_INIT_XGXS_FIRST,
10969         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10970         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10971         .mdio_ctrl      = 0,
10972         .supported      = (SUPPORTED_10baseT_Half |
10973                            SUPPORTED_10baseT_Full |
10974                            SUPPORTED_100baseT_Half |
10975                            SUPPORTED_100baseT_Full |
10976                            SUPPORTED_1000baseT_Full |
10977                            SUPPORTED_TP |
10978                            SUPPORTED_Autoneg |
10979                            SUPPORTED_Pause |
10980                            SUPPORTED_Asym_Pause),
10981         .media_type     = ETH_PHY_BASE_T,
10982         .ver_addr       = 0,
10983         .req_flow_ctrl  = 0,
10984         .req_line_speed = 0,
10985         .speed_cap_mask = 0,
10986         /* req_duplex = */0,
10987         /* rsrv = */0,
10988         .config_init    = (config_init_t)bnx2x_54618se_config_init,
10989         .read_status    = (read_status_t)bnx2x_54618se_read_status,
10990         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
10991         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
10992         .format_fw_ver  = (format_fw_ver_t)NULL,
10993         .hw_reset       = (hw_reset_t)NULL,
10994         .set_link_led   = (set_link_led_t)bnx2x_54618se_set_link_led,
10995         .phy_specific_func = (phy_specific_func_t)NULL
10996 };
10997 /*****************************************************************/
10998 /*                                                               */
10999 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11000 /*                                                               */
11001 /*****************************************************************/
11002
11003 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11004                                      struct bnx2x_phy *phy, u8 port,
11005                                      u8 phy_index)
11006 {
11007         /* Get the 4 lanes xgxs config rx and tx */
11008         u32 rx = 0, tx = 0, i;
11009         for (i = 0; i < 2; i++) {
11010                 /*
11011                  * INT_PHY and EXT_PHY1 share the same value location in the
11012                  * shmem. When num_phys is greater than 1, than this value
11013                  * applies only to EXT_PHY1
11014                  */
11015                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11016                         rx = REG_RD(bp, shmem_base +
11017                                     offsetof(struct shmem_region,
11018                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11019
11020                         tx = REG_RD(bp, shmem_base +
11021                                     offsetof(struct shmem_region,
11022                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11023                 } else {
11024                         rx = REG_RD(bp, shmem_base +
11025                                     offsetof(struct shmem_region,
11026                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11027
11028                         tx = REG_RD(bp, shmem_base +
11029                                     offsetof(struct shmem_region,
11030                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11031                 }
11032
11033                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11034                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11035
11036                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11037                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11038         }
11039 }
11040
11041 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11042                                     u8 phy_index, u8 port)
11043 {
11044         u32 ext_phy_config = 0;
11045         switch (phy_index) {
11046         case EXT_PHY1:
11047                 ext_phy_config = REG_RD(bp, shmem_base +
11048                                               offsetof(struct shmem_region,
11049                         dev_info.port_hw_config[port].external_phy_config));
11050                 break;
11051         case EXT_PHY2:
11052                 ext_phy_config = REG_RD(bp, shmem_base +
11053                                               offsetof(struct shmem_region,
11054                         dev_info.port_hw_config[port].external_phy_config2));
11055                 break;
11056         default:
11057                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11058                 return -EINVAL;
11059         }
11060
11061         return ext_phy_config;
11062 }
11063 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11064                                   struct bnx2x_phy *phy)
11065 {
11066         u32 phy_addr;
11067         u32 chip_id;
11068         u32 switch_cfg = (REG_RD(bp, shmem_base +
11069                                        offsetof(struct shmem_region,
11070                         dev_info.port_feature_config[port].link_config)) &
11071                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11072         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
11073         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11074         if (USES_WARPCORE(bp)) {
11075                 u32 serdes_net_if;
11076                 phy_addr = REG_RD(bp,
11077                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11078                 *phy = phy_warpcore;
11079                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11080                         phy->flags |= FLAGS_4_PORT_MODE;
11081                 else
11082                         phy->flags &= ~FLAGS_4_PORT_MODE;
11083                         /* Check Dual mode */
11084                 serdes_net_if = (REG_RD(bp, shmem_base +
11085                                         offsetof(struct shmem_region, dev_info.
11086                                         port_hw_config[port].default_cfg)) &
11087                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11088                 /*
11089                  * Set the appropriate supported and flags indications per
11090                  * interface type of the chip
11091                  */
11092                 switch (serdes_net_if) {
11093                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11094                         phy->supported &= (SUPPORTED_10baseT_Half |
11095                                            SUPPORTED_10baseT_Full |
11096                                            SUPPORTED_100baseT_Half |
11097                                            SUPPORTED_100baseT_Full |
11098                                            SUPPORTED_1000baseT_Full |
11099                                            SUPPORTED_FIBRE |
11100                                            SUPPORTED_Autoneg |
11101                                            SUPPORTED_Pause |
11102                                            SUPPORTED_Asym_Pause);
11103                         phy->media_type = ETH_PHY_BASE_T;
11104                         break;
11105                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11106                         phy->media_type = ETH_PHY_XFP_FIBER;
11107                         break;
11108                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11109                         phy->supported &= (SUPPORTED_1000baseT_Full |
11110                                            SUPPORTED_10000baseT_Full |
11111                                            SUPPORTED_FIBRE |
11112                                            SUPPORTED_Pause |
11113                                            SUPPORTED_Asym_Pause);
11114                         phy->media_type = ETH_PHY_SFP_FIBER;
11115                         break;
11116                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11117                         phy->media_type = ETH_PHY_KR;
11118                         phy->supported &= (SUPPORTED_1000baseT_Full |
11119                                            SUPPORTED_10000baseT_Full |
11120                                            SUPPORTED_FIBRE |
11121                                            SUPPORTED_Autoneg |
11122                                            SUPPORTED_Pause |
11123                                            SUPPORTED_Asym_Pause);
11124                         break;
11125                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11126                         phy->media_type = ETH_PHY_KR;
11127                         phy->flags |= FLAGS_WC_DUAL_MODE;
11128                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11129                                            SUPPORTED_FIBRE |
11130                                            SUPPORTED_Pause |
11131                                            SUPPORTED_Asym_Pause);
11132                         break;
11133                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11134                         phy->media_type = ETH_PHY_KR;
11135                         phy->flags |= FLAGS_WC_DUAL_MODE;
11136                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11137                                            SUPPORTED_FIBRE |
11138                                            SUPPORTED_Pause |
11139                                            SUPPORTED_Asym_Pause);
11140                         break;
11141                 default:
11142                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11143                                        serdes_net_if);
11144                         break;
11145                 }
11146
11147                 /*
11148                  * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11149                  * was not set as expected. For B0, ECO will be enabled so there
11150                  * won't be an issue there
11151                  */
11152                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11153                         phy->flags |= FLAGS_MDC_MDIO_WA;
11154                 else
11155                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11156         } else {
11157                 switch (switch_cfg) {
11158                 case SWITCH_CFG_1G:
11159                         phy_addr = REG_RD(bp,
11160                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11161                                           port * 0x10);
11162                         *phy = phy_serdes;
11163                         break;
11164                 case SWITCH_CFG_10G:
11165                         phy_addr = REG_RD(bp,
11166                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11167                                           port * 0x18);
11168                         *phy = phy_xgxs;
11169                         break;
11170                 default:
11171                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11172                         return -EINVAL;
11173                 }
11174         }
11175         phy->addr = (u8)phy_addr;
11176         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11177                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11178                                             port);
11179         if (CHIP_IS_E2(bp))
11180                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11181         else
11182                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11183
11184         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11185                    port, phy->addr, phy->mdio_ctrl);
11186
11187         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11188         return 0;
11189 }
11190
11191 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11192                                   u8 phy_index,
11193                                   u32 shmem_base,
11194                                   u32 shmem2_base,
11195                                   u8 port,
11196                                   struct bnx2x_phy *phy)
11197 {
11198         u32 ext_phy_config, phy_type, config2;
11199         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11200         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11201                                                   phy_index, port);
11202         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11203         /* Select the phy type */
11204         switch (phy_type) {
11205         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11206                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11207                 *phy = phy_8073;
11208                 break;
11209         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11210                 *phy = phy_8705;
11211                 break;
11212         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11213                 *phy = phy_8706;
11214                 break;
11215         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11216                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11217                 *phy = phy_8726;
11218                 break;
11219         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11220                 /* BCM8727_NOC => BCM8727 no over current */
11221                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11222                 *phy = phy_8727;
11223                 phy->flags |= FLAGS_NOC;
11224                 break;
11225         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11226         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11227                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11228                 *phy = phy_8727;
11229                 break;
11230         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11231                 *phy = phy_8481;
11232                 break;
11233         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11234                 *phy = phy_84823;
11235                 break;
11236         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11237                 *phy = phy_84833;
11238                 break;
11239         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11240                 *phy = phy_54618se;
11241                 break;
11242         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11243                 *phy = phy_7101;
11244                 break;
11245         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11246                 *phy = phy_null;
11247                 return -EINVAL;
11248         default:
11249                 *phy = phy_null;
11250                 return 0;
11251         }
11252
11253         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11254         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11255
11256         /*
11257          * The shmem address of the phy version is located on different
11258          * structures. In case this structure is too old, do not set
11259          * the address
11260          */
11261         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11262                                         dev_info.shared_hw_config.config2));
11263         if (phy_index == EXT_PHY1) {
11264                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11265                                 port_mb[port].ext_phy_fw_version);
11266
11267                 /* Check specific mdc mdio settings */
11268                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11269                         mdc_mdio_access = config2 &
11270                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11271         } else {
11272                 u32 size = REG_RD(bp, shmem2_base);
11273
11274                 if (size >
11275                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11276                         phy->ver_addr = shmem2_base +
11277                             offsetof(struct shmem2_region,
11278                                      ext_phy_fw_version2[port]);
11279                 }
11280                 /* Check specific mdc mdio settings */
11281                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11282                         mdc_mdio_access = (config2 &
11283                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11284                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11285                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11286         }
11287         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11288
11289         /*
11290          * In case mdc/mdio_access of the external phy is different than the
11291          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11292          * to prevent one port interfere with another port's CL45 operations.
11293          */
11294         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11295                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11296         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11297                    phy_type, port, phy_index);
11298         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
11299                    phy->addr, phy->mdio_ctrl);
11300         return 0;
11301 }
11302
11303 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11304                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11305 {
11306         int status = 0;
11307         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11308         if (phy_index == INT_PHY)
11309                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11310         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11311                                         port, phy);
11312         return status;
11313 }
11314
11315 static void bnx2x_phy_def_cfg(struct link_params *params,
11316                               struct bnx2x_phy *phy,
11317                               u8 phy_index)
11318 {
11319         struct bnx2x *bp = params->bp;
11320         u32 link_config;
11321         /* Populate the default phy configuration for MF mode */
11322         if (phy_index == EXT_PHY2) {
11323                 link_config = REG_RD(bp, params->shmem_base +
11324                                      offsetof(struct shmem_region, dev_info.
11325                         port_feature_config[params->port].link_config2));
11326                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11327                                              offsetof(struct shmem_region,
11328                                                       dev_info.
11329                         port_hw_config[params->port].speed_capability_mask2));
11330         } else {
11331                 link_config = REG_RD(bp, params->shmem_base +
11332                                      offsetof(struct shmem_region, dev_info.
11333                                 port_feature_config[params->port].link_config));
11334                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11335                                              offsetof(struct shmem_region,
11336                                                       dev_info.
11337                         port_hw_config[params->port].speed_capability_mask));
11338         }
11339         DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
11340                        " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
11341
11342         phy->req_duplex = DUPLEX_FULL;
11343         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
11344         case PORT_FEATURE_LINK_SPEED_10M_HALF:
11345                 phy->req_duplex = DUPLEX_HALF;
11346         case PORT_FEATURE_LINK_SPEED_10M_FULL:
11347                 phy->req_line_speed = SPEED_10;
11348                 break;
11349         case PORT_FEATURE_LINK_SPEED_100M_HALF:
11350                 phy->req_duplex = DUPLEX_HALF;
11351         case PORT_FEATURE_LINK_SPEED_100M_FULL:
11352                 phy->req_line_speed = SPEED_100;
11353                 break;
11354         case PORT_FEATURE_LINK_SPEED_1G:
11355                 phy->req_line_speed = SPEED_1000;
11356                 break;
11357         case PORT_FEATURE_LINK_SPEED_2_5G:
11358                 phy->req_line_speed = SPEED_2500;
11359                 break;
11360         case PORT_FEATURE_LINK_SPEED_10G_CX4:
11361                 phy->req_line_speed = SPEED_10000;
11362                 break;
11363         default:
11364                 phy->req_line_speed = SPEED_AUTO_NEG;
11365                 break;
11366         }
11367
11368         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
11369         case PORT_FEATURE_FLOW_CONTROL_AUTO:
11370                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11371                 break;
11372         case PORT_FEATURE_FLOW_CONTROL_TX:
11373                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11374                 break;
11375         case PORT_FEATURE_FLOW_CONTROL_RX:
11376                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11377                 break;
11378         case PORT_FEATURE_FLOW_CONTROL_BOTH:
11379                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11380                 break;
11381         default:
11382                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11383                 break;
11384         }
11385 }
11386
11387 u32 bnx2x_phy_selection(struct link_params *params)
11388 {
11389         u32 phy_config_swapped, prio_cfg;
11390         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11391
11392         phy_config_swapped = params->multi_phy_config &
11393                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11394
11395         prio_cfg = params->multi_phy_config &
11396                         PORT_HW_CFG_PHY_SELECTION_MASK;
11397
11398         if (phy_config_swapped) {
11399                 switch (prio_cfg) {
11400                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11401                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11402                      break;
11403                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11404                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11405                      break;
11406                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11407                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11408                      break;
11409                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11410                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11411                      break;
11412                 }
11413         } else
11414                 return_cfg = prio_cfg;
11415
11416         return return_cfg;
11417 }
11418
11419
11420 int bnx2x_phy_probe(struct link_params *params)
11421 {
11422         u8 phy_index, actual_phy_idx, link_cfg_idx;
11423         u32 phy_config_swapped, sync_offset, media_types;
11424         struct bnx2x *bp = params->bp;
11425         struct bnx2x_phy *phy;
11426         params->num_phys = 0;
11427         DP(NETIF_MSG_LINK, "Begin phy probe\n");
11428         phy_config_swapped = params->multi_phy_config &
11429                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11430
11431         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11432               phy_index++) {
11433                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11434                 actual_phy_idx = phy_index;
11435                 if (phy_config_swapped) {
11436                         if (phy_index == EXT_PHY1)
11437                                 actual_phy_idx = EXT_PHY2;
11438                         else if (phy_index == EXT_PHY2)
11439                                 actual_phy_idx = EXT_PHY1;
11440                 }
11441                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11442                                " actual_phy_idx %x\n", phy_config_swapped,
11443                            phy_index, actual_phy_idx);
11444                 phy = &params->phy[actual_phy_idx];
11445                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11446                                        params->shmem2_base, params->port,
11447                                        phy) != 0) {
11448                         params->num_phys = 0;
11449                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11450                                    phy_index);
11451                         for (phy_index = INT_PHY;
11452                               phy_index < MAX_PHYS;
11453                               phy_index++)
11454                                 *phy = phy_null;
11455                         return -EINVAL;
11456                 }
11457                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11458                         break;
11459
11460                 sync_offset = params->shmem_base +
11461                         offsetof(struct shmem_region,
11462                         dev_info.port_hw_config[params->port].media_type);
11463                 media_types = REG_RD(bp, sync_offset);
11464
11465                 /*
11466                  * Update media type for non-PMF sync only for the first time
11467                  * In case the media type changes afterwards, it will be updated
11468                  * using the update_status function
11469                  */
11470                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11471                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11472                                      actual_phy_idx))) == 0) {
11473                         media_types |= ((phy->media_type &
11474                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11475                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11476                                  actual_phy_idx));
11477                 }
11478                 REG_WR(bp, sync_offset, media_types);
11479
11480                 bnx2x_phy_def_cfg(params, phy, phy_index);
11481                 params->num_phys++;
11482         }
11483
11484         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11485         return 0;
11486 }
11487
11488 void bnx2x_init_bmac_loopback(struct link_params *params,
11489                               struct link_vars *vars)
11490 {
11491         struct bnx2x *bp = params->bp;
11492                 vars->link_up = 1;
11493                 vars->line_speed = SPEED_10000;
11494                 vars->duplex = DUPLEX_FULL;
11495                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11496                 vars->mac_type = MAC_TYPE_BMAC;
11497
11498                 vars->phy_flags = PHY_XGXS_FLAG;
11499
11500                 bnx2x_xgxs_deassert(params);
11501
11502                 /* set bmac loopback */
11503                 bnx2x_bmac_enable(params, vars, 1);
11504
11505                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11506 }
11507
11508 void bnx2x_init_emac_loopback(struct link_params *params,
11509                               struct link_vars *vars)
11510 {
11511         struct bnx2x *bp = params->bp;
11512                 vars->link_up = 1;
11513                 vars->line_speed = SPEED_1000;
11514                 vars->duplex = DUPLEX_FULL;
11515                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11516                 vars->mac_type = MAC_TYPE_EMAC;
11517
11518                 vars->phy_flags = PHY_XGXS_FLAG;
11519
11520                 bnx2x_xgxs_deassert(params);
11521                 /* set bmac loopback */
11522                 bnx2x_emac_enable(params, vars, 1);
11523                 bnx2x_emac_program(params, vars);
11524                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11525 }
11526
11527 void bnx2x_init_xmac_loopback(struct link_params *params,
11528                               struct link_vars *vars)
11529 {
11530         struct bnx2x *bp = params->bp;
11531         vars->link_up = 1;
11532         if (!params->req_line_speed[0])
11533                 vars->line_speed = SPEED_10000;
11534         else
11535                 vars->line_speed = params->req_line_speed[0];
11536         vars->duplex = DUPLEX_FULL;
11537         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11538         vars->mac_type = MAC_TYPE_XMAC;
11539         vars->phy_flags = PHY_XGXS_FLAG;
11540         /*
11541          * Set WC to loopback mode since link is required to provide clock
11542          * to the XMAC in 20G mode
11543          */
11544         bnx2x_set_aer_mmd(params, &params->phy[0]);
11545         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
11546         params->phy[INT_PHY].config_loopback(
11547                         &params->phy[INT_PHY],
11548                         params);
11549
11550         bnx2x_xmac_enable(params, vars, 1);
11551         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11552 }
11553
11554 void bnx2x_init_umac_loopback(struct link_params *params,
11555                               struct link_vars *vars)
11556 {
11557         struct bnx2x *bp = params->bp;
11558         vars->link_up = 1;
11559         vars->line_speed = SPEED_1000;
11560         vars->duplex = DUPLEX_FULL;
11561         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11562         vars->mac_type = MAC_TYPE_UMAC;
11563         vars->phy_flags = PHY_XGXS_FLAG;
11564         bnx2x_umac_enable(params, vars, 1);
11565
11566         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11567 }
11568
11569 void bnx2x_init_xgxs_loopback(struct link_params *params,
11570                               struct link_vars *vars)
11571 {
11572         struct bnx2x *bp = params->bp;
11573                 vars->link_up = 1;
11574                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11575                 vars->duplex = DUPLEX_FULL;
11576         if (params->req_line_speed[0] == SPEED_1000)
11577                         vars->line_speed = SPEED_1000;
11578         else
11579                         vars->line_speed = SPEED_10000;
11580
11581         if (!USES_WARPCORE(bp))
11582                 bnx2x_xgxs_deassert(params);
11583         bnx2x_link_initialize(params, vars);
11584
11585         if (params->req_line_speed[0] == SPEED_1000) {
11586                 if (USES_WARPCORE(bp))
11587                         bnx2x_umac_enable(params, vars, 0);
11588                 else {
11589                         bnx2x_emac_program(params, vars);
11590                         bnx2x_emac_enable(params, vars, 0);
11591                 }
11592         } else {
11593                 if (USES_WARPCORE(bp))
11594                         bnx2x_xmac_enable(params, vars, 0);
11595                 else
11596                         bnx2x_bmac_enable(params, vars, 0);
11597         }
11598
11599                 if (params->loopback_mode == LOOPBACK_XGXS) {
11600                         /* set 10G XGXS loopback */
11601                         params->phy[INT_PHY].config_loopback(
11602                                 &params->phy[INT_PHY],
11603                                 params);
11604
11605                 } else {
11606                         /* set external phy loopback */
11607                         u8 phy_index;
11608                         for (phy_index = EXT_PHY1;
11609                               phy_index < params->num_phys; phy_index++) {
11610                                 if (params->phy[phy_index].config_loopback)
11611                                         params->phy[phy_index].config_loopback(
11612                                                 &params->phy[phy_index],
11613                                                 params);
11614                         }
11615                 }
11616                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11617
11618         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11619 }
11620
11621 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11622 {
11623         struct bnx2x *bp = params->bp;
11624         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11625         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11626                    params->req_line_speed[0], params->req_flow_ctrl[0]);
11627         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11628                    params->req_line_speed[1], params->req_flow_ctrl[1]);
11629         vars->link_status = 0;
11630         vars->phy_link_up = 0;
11631         vars->link_up = 0;
11632         vars->line_speed = 0;
11633         vars->duplex = DUPLEX_FULL;
11634         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11635         vars->mac_type = MAC_TYPE_NONE;
11636         vars->phy_flags = 0;
11637
11638         /* disable attentions */
11639         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11640                        (NIG_MASK_XGXS0_LINK_STATUS |
11641                         NIG_MASK_XGXS0_LINK10G |
11642                         NIG_MASK_SERDES0_LINK_STATUS |
11643                         NIG_MASK_MI_INT));
11644
11645         bnx2x_emac_init(params, vars);
11646
11647         if (params->num_phys == 0) {
11648                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11649                 return -EINVAL;
11650         }
11651         set_phy_vars(params, vars);
11652
11653         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11654         switch (params->loopback_mode) {
11655         case LOOPBACK_BMAC:
11656                 bnx2x_init_bmac_loopback(params, vars);
11657                 break;
11658         case LOOPBACK_EMAC:
11659                 bnx2x_init_emac_loopback(params, vars);
11660                 break;
11661         case LOOPBACK_XMAC:
11662                 bnx2x_init_xmac_loopback(params, vars);
11663                 break;
11664         case LOOPBACK_UMAC:
11665                 bnx2x_init_umac_loopback(params, vars);
11666                 break;
11667         case LOOPBACK_XGXS:
11668         case LOOPBACK_EXT_PHY:
11669                 bnx2x_init_xgxs_loopback(params, vars);
11670                 break;
11671         default:
11672                 if (!CHIP_IS_E3(bp)) {
11673                         if (params->switch_cfg == SWITCH_CFG_10G)
11674                                 bnx2x_xgxs_deassert(params);
11675                         else
11676                                 bnx2x_serdes_deassert(bp, params->port);
11677                 }
11678                 bnx2x_link_initialize(params, vars);
11679                 msleep(30);
11680                 bnx2x_link_int_enable(params);
11681                 break;
11682         }
11683         return 0;
11684 }
11685
11686 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11687                      u8 reset_ext_phy)
11688 {
11689         struct bnx2x *bp = params->bp;
11690         u8 phy_index, port = params->port, clear_latch_ind = 0;
11691         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11692         /* disable attentions */
11693         vars->link_status = 0;
11694         bnx2x_update_mng(params, vars->link_status);
11695         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11696                        (NIG_MASK_XGXS0_LINK_STATUS |
11697                         NIG_MASK_XGXS0_LINK10G |
11698                         NIG_MASK_SERDES0_LINK_STATUS |
11699                         NIG_MASK_MI_INT));
11700
11701         /* activate nig drain */
11702         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11703
11704         /* disable nig egress interface */
11705         if (!CHIP_IS_E3(bp)) {
11706                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11707                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11708         }
11709
11710         /* Stop BigMac rx */
11711         if (!CHIP_IS_E3(bp))
11712                 bnx2x_bmac_rx_disable(bp, port);
11713         else
11714                 bnx2x_xmac_disable(params);
11715         /* disable emac */
11716         if (!CHIP_IS_E3(bp))
11717                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11718
11719         msleep(10);
11720         /* The PHY reset is controlled by GPIO 1
11721          * Hold it as vars low
11722          */
11723          /* clear link led */
11724         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11725
11726         if (reset_ext_phy) {
11727                 bnx2x_set_mdio_clk(bp, params->chip_id, port);
11728                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11729                       phy_index++) {
11730                         if (params->phy[phy_index].link_reset) {
11731                                 bnx2x_set_aer_mmd(params,
11732                                                   &params->phy[phy_index]);
11733                                 params->phy[phy_index].link_reset(
11734                                         &params->phy[phy_index],
11735                                         params);
11736                         }
11737                         if (params->phy[phy_index].flags &
11738                             FLAGS_REARM_LATCH_SIGNAL)
11739                                 clear_latch_ind = 1;
11740                 }
11741         }
11742
11743         if (clear_latch_ind) {
11744                 /* Clear latching indication */
11745                 bnx2x_rearm_latch_signal(bp, port, 0);
11746                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11747                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
11748         }
11749         if (params->phy[INT_PHY].link_reset)
11750                 params->phy[INT_PHY].link_reset(
11751                         &params->phy[INT_PHY], params);
11752         /* reset BigMac */
11753         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11754                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11755
11756         /* disable nig ingress interface */
11757         if (!CHIP_IS_E3(bp)) {
11758                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11759                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11760         }
11761         vars->link_up = 0;
11762         vars->phy_flags = 0;
11763         return 0;
11764 }
11765
11766 /****************************************************************************/
11767 /*                              Common function                             */
11768 /****************************************************************************/
11769 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
11770                                       u32 shmem_base_path[],
11771                                       u32 shmem2_base_path[], u8 phy_index,
11772                                       u32 chip_id)
11773 {
11774         struct bnx2x_phy phy[PORT_MAX];
11775         struct bnx2x_phy *phy_blk[PORT_MAX];
11776         u16 val;
11777         s8 port = 0;
11778         s8 port_of_path = 0;
11779         u32 swap_val, swap_override;
11780         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
11781         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
11782         port ^= (swap_val && swap_override);
11783         bnx2x_ext_phy_hw_reset(bp, port);
11784         /* PART1 - Reset both phys */
11785         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11786                 u32 shmem_base, shmem2_base;
11787                 /* In E2, same phy is using for port0 of the two paths */
11788                 if (CHIP_IS_E1x(bp)) {
11789                         shmem_base = shmem_base_path[0];
11790                         shmem2_base = shmem2_base_path[0];
11791                         port_of_path = port;
11792                 } else {
11793                         shmem_base = shmem_base_path[port];
11794                         shmem2_base = shmem2_base_path[port];
11795                         port_of_path = 0;
11796                 }
11797
11798                 /* Extract the ext phy address for the port */
11799                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11800                                        port_of_path, &phy[port]) !=
11801                     0) {
11802                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
11803                         return -EINVAL;
11804                 }
11805                 /* disable attentions */
11806                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11807                                port_of_path*4,
11808                                (NIG_MASK_XGXS0_LINK_STATUS |
11809                                 NIG_MASK_XGXS0_LINK10G |
11810                                 NIG_MASK_SERDES0_LINK_STATUS |
11811                                 NIG_MASK_MI_INT));
11812
11813                 /* Need to take the phy out of low power mode in order
11814                         to write to access its registers */
11815                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11816                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11817                                port);
11818
11819                 /* Reset the phy */
11820                 bnx2x_cl45_write(bp, &phy[port],
11821                                  MDIO_PMA_DEVAD,
11822                                  MDIO_PMA_REG_CTRL,
11823                                  1<<15);
11824         }
11825
11826         /* Add delay of 150ms after reset */
11827         msleep(150);
11828
11829         if (phy[PORT_0].addr & 0x1) {
11830                 phy_blk[PORT_0] = &(phy[PORT_1]);
11831                 phy_blk[PORT_1] = &(phy[PORT_0]);
11832         } else {
11833                 phy_blk[PORT_0] = &(phy[PORT_0]);
11834                 phy_blk[PORT_1] = &(phy[PORT_1]);
11835         }
11836
11837         /* PART2 - Download firmware to both phys */
11838         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11839                 if (CHIP_IS_E1x(bp))
11840                         port_of_path = port;
11841                 else
11842                         port_of_path = 0;
11843
11844                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11845                            phy_blk[port]->addr);
11846                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11847                                                       port_of_path))
11848                         return -EINVAL;
11849
11850                 /* Only set bit 10 = 1 (Tx power down) */
11851                 bnx2x_cl45_read(bp, phy_blk[port],
11852                                 MDIO_PMA_DEVAD,
11853                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11854
11855                 /* Phase1 of TX_POWER_DOWN reset */
11856                 bnx2x_cl45_write(bp, phy_blk[port],
11857                                  MDIO_PMA_DEVAD,
11858                                  MDIO_PMA_REG_TX_POWER_DOWN,
11859                                  (val | 1<<10));
11860         }
11861
11862         /*
11863          * Toggle Transmitter: Power down and then up with 600ms delay
11864          * between
11865          */
11866         msleep(600);
11867
11868         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
11869         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11870                 /* Phase2 of POWER_DOWN_RESET */
11871                 /* Release bit 10 (Release Tx power down) */
11872                 bnx2x_cl45_read(bp, phy_blk[port],
11873                                 MDIO_PMA_DEVAD,
11874                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11875
11876                 bnx2x_cl45_write(bp, phy_blk[port],
11877                                 MDIO_PMA_DEVAD,
11878                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
11879                 msleep(15);
11880
11881                 /* Read modify write the SPI-ROM version select register */
11882                 bnx2x_cl45_read(bp, phy_blk[port],
11883                                 MDIO_PMA_DEVAD,
11884                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
11885                 bnx2x_cl45_write(bp, phy_blk[port],
11886                                  MDIO_PMA_DEVAD,
11887                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
11888
11889                 /* set GPIO2 back to LOW */
11890                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11891                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
11892         }
11893         return 0;
11894 }
11895 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
11896                                       u32 shmem_base_path[],
11897                                       u32 shmem2_base_path[], u8 phy_index,
11898                                       u32 chip_id)
11899 {
11900         u32 val;
11901         s8 port;
11902         struct bnx2x_phy phy;
11903         /* Use port1 because of the static port-swap */
11904         /* Enable the module detection interrupt */
11905         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
11906         val |= ((1<<MISC_REGISTERS_GPIO_3)|
11907                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
11908         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
11909
11910         bnx2x_ext_phy_hw_reset(bp, 0);
11911         msleep(5);
11912         for (port = 0; port < PORT_MAX; port++) {
11913                 u32 shmem_base, shmem2_base;
11914
11915                 /* In E2, same phy is using for port0 of the two paths */
11916                 if (CHIP_IS_E1x(bp)) {
11917                         shmem_base = shmem_base_path[0];
11918                         shmem2_base = shmem2_base_path[0];
11919                 } else {
11920                         shmem_base = shmem_base_path[port];
11921                         shmem2_base = shmem2_base_path[port];
11922                 }
11923                 /* Extract the ext phy address for the port */
11924                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11925                                        port, &phy) !=
11926                     0) {
11927                         DP(NETIF_MSG_LINK, "populate phy failed\n");
11928                         return -EINVAL;
11929                 }
11930
11931                 /* Reset phy*/
11932                 bnx2x_cl45_write(bp, &phy,
11933                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
11934
11935
11936                 /* Set fault module detected LED on */
11937                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
11938                                MISC_REGISTERS_GPIO_HIGH,
11939                                port);
11940         }
11941
11942         return 0;
11943 }
11944 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
11945                                          u8 *io_gpio, u8 *io_port)
11946 {
11947
11948         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
11949                                           offsetof(struct shmem_region,
11950                                 dev_info.port_hw_config[PORT_0].default_cfg));
11951         switch (phy_gpio_reset) {
11952         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
11953                 *io_gpio = 0;
11954                 *io_port = 0;
11955                 break;
11956         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
11957                 *io_gpio = 1;
11958                 *io_port = 0;
11959                 break;
11960         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
11961                 *io_gpio = 2;
11962                 *io_port = 0;
11963                 break;
11964         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
11965                 *io_gpio = 3;
11966                 *io_port = 0;
11967                 break;
11968         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
11969                 *io_gpio = 0;
11970                 *io_port = 1;
11971                 break;
11972         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
11973                 *io_gpio = 1;
11974                 *io_port = 1;
11975                 break;
11976         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
11977                 *io_gpio = 2;
11978                 *io_port = 1;
11979                 break;
11980         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
11981                 *io_gpio = 3;
11982                 *io_port = 1;
11983                 break;
11984         default:
11985                 /* Don't override the io_gpio and io_port */
11986                 break;
11987         }
11988 }
11989
11990 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
11991                                       u32 shmem_base_path[],
11992                                       u32 shmem2_base_path[], u8 phy_index,
11993                                       u32 chip_id)
11994 {
11995         s8 port, reset_gpio;
11996         u32 swap_val, swap_override;
11997         struct bnx2x_phy phy[PORT_MAX];
11998         struct bnx2x_phy *phy_blk[PORT_MAX];
11999         s8 port_of_path;
12000         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12001         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12002
12003         reset_gpio = MISC_REGISTERS_GPIO_1;
12004         port = 1;
12005
12006         /*
12007          * Retrieve the reset gpio/port which control the reset.
12008          * Default is GPIO1, PORT1
12009          */
12010         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12011                                      (u8 *)&reset_gpio, (u8 *)&port);
12012
12013         /* Calculate the port based on port swap */
12014         port ^= (swap_val && swap_override);
12015
12016         /* Initiate PHY reset*/
12017         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12018                        port);
12019         msleep(1);
12020         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12021                        port);
12022
12023         msleep(5);
12024
12025         /* PART1 - Reset both phys */
12026         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12027                 u32 shmem_base, shmem2_base;
12028
12029                 /* In E2, same phy is using for port0 of the two paths */
12030                 if (CHIP_IS_E1x(bp)) {
12031                         shmem_base = shmem_base_path[0];
12032                         shmem2_base = shmem2_base_path[0];
12033                         port_of_path = port;
12034                 } else {
12035                         shmem_base = shmem_base_path[port];
12036                         shmem2_base = shmem2_base_path[port];
12037                         port_of_path = 0;
12038                 }
12039
12040                 /* Extract the ext phy address for the port */
12041                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12042                                        port_of_path, &phy[port]) !=
12043                                        0) {
12044                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12045                         return -EINVAL;
12046                 }
12047                 /* disable attentions */
12048                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12049                                port_of_path*4,
12050                                (NIG_MASK_XGXS0_LINK_STATUS |
12051                                 NIG_MASK_XGXS0_LINK10G |
12052                                 NIG_MASK_SERDES0_LINK_STATUS |
12053                                 NIG_MASK_MI_INT));
12054
12055
12056                 /* Reset the phy */
12057                 bnx2x_cl45_write(bp, &phy[port],
12058                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12059         }
12060
12061         /* Add delay of 150ms after reset */
12062         msleep(150);
12063         if (phy[PORT_0].addr & 0x1) {
12064                 phy_blk[PORT_0] = &(phy[PORT_1]);
12065                 phy_blk[PORT_1] = &(phy[PORT_0]);
12066         } else {
12067                 phy_blk[PORT_0] = &(phy[PORT_0]);
12068                 phy_blk[PORT_1] = &(phy[PORT_1]);
12069         }
12070         /* PART2 - Download firmware to both phys */
12071         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12072                 if (CHIP_IS_E1x(bp))
12073                         port_of_path = port;
12074                 else
12075                         port_of_path = 0;
12076                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12077                            phy_blk[port]->addr);
12078                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12079                                                       port_of_path))
12080                         return -EINVAL;
12081                 /* Disable PHY transmitter output */
12082                 bnx2x_cl45_write(bp, phy_blk[port],
12083                                  MDIO_PMA_DEVAD,
12084                                  MDIO_PMA_REG_TX_DISABLE, 1);
12085
12086         }
12087         return 0;
12088 }
12089
12090 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12091                                      u32 shmem2_base_path[], u8 phy_index,
12092                                      u32 ext_phy_type, u32 chip_id)
12093 {
12094         int rc = 0;
12095
12096         switch (ext_phy_type) {
12097         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12098                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12099                                                 shmem2_base_path,
12100                                                 phy_index, chip_id);
12101                 break;
12102         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12103         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12104         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12105                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12106                                                 shmem2_base_path,
12107                                                 phy_index, chip_id);
12108                 break;
12109
12110         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12111                 /*
12112                  * GPIO1 affects both ports, so there's need to pull
12113                  * it for single port alone
12114                  */
12115                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12116                                                 shmem2_base_path,
12117                                                 phy_index, chip_id);
12118                 break;
12119         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12120                 /*
12121                  * GPIO3's are linked, and so both need to be toggled
12122                  * to obtain required 2us pulse.
12123                  */
12124                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
12125                 break;
12126         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12127                 rc = -EINVAL;
12128                 break;
12129         default:
12130                 DP(NETIF_MSG_LINK,
12131                            "ext_phy 0x%x common init not required\n",
12132                            ext_phy_type);
12133                 break;
12134         }
12135
12136         if (rc != 0)
12137                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
12138                                       " Port %d\n",
12139                          0);
12140         return rc;
12141 }
12142
12143 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12144                           u32 shmem2_base_path[], u32 chip_id)
12145 {
12146         int rc = 0;
12147         u32 phy_ver, val;
12148         u8 phy_index = 0;
12149         u32 ext_phy_type, ext_phy_config;
12150         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12151         bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12152         DP(NETIF_MSG_LINK, "Begin common phy init\n");
12153         if (CHIP_IS_E3(bp)) {
12154                 /* Enable EPIO */
12155                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12156                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12157         }
12158         /* Check if common init was already done */
12159         phy_ver = REG_RD(bp, shmem_base_path[0] +
12160                          offsetof(struct shmem_region,
12161                                   port_mb[PORT_0].ext_phy_fw_version));
12162         if (phy_ver) {
12163                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12164                                phy_ver);
12165                 return 0;
12166         }
12167
12168         /* Read the ext_phy_type for arbitrary port(0) */
12169         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12170               phy_index++) {
12171                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12172                                                           shmem_base_path[0],
12173                                                           phy_index, 0);
12174                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12175                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12176                                                 shmem2_base_path,
12177                                                 phy_index, ext_phy_type,
12178                                                 chip_id);
12179         }
12180         return rc;
12181 }
12182
12183 static void bnx2x_check_over_curr(struct link_params *params,
12184                                   struct link_vars *vars)
12185 {
12186         struct bnx2x *bp = params->bp;
12187         u32 cfg_pin;
12188         u8 port = params->port;
12189         u32 pin_val;
12190
12191         cfg_pin = (REG_RD(bp, params->shmem_base +
12192                           offsetof(struct shmem_region,
12193                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12194                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12195                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12196
12197         /* Ignore check if no external input PIN available */
12198         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12199                 return;
12200
12201         if (!pin_val) {
12202                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12203                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
12204                                             " been detected and the power to "
12205                                             "that SFP+ module has been removed"
12206                                             " to prevent failure of the card."
12207                                             " Please remove the SFP+ module and"
12208                                             " restart the system to clear this"
12209                                             " error.\n",
12210                          params->port);
12211                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12212                 }
12213         } else
12214                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12215 }
12216
12217 static void bnx2x_analyze_link_error(struct link_params *params,
12218                                      struct link_vars *vars, u32 lss_status)
12219 {
12220         struct bnx2x *bp = params->bp;
12221         /* Compare new value with previous value */
12222         u8 led_mode;
12223         u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12224
12225         if ((lss_status ^ half_open_conn) == 0)
12226                 return;
12227
12228         /* If values differ */
12229         DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12230                        half_open_conn, lss_status);
12231
12232         /*
12233          * a. Update shmem->link_status accordingly
12234          * b. Update link_vars->link_up
12235          */
12236         if (lss_status) {
12237                 DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12238                 vars->link_status &= ~LINK_STATUS_LINK_UP;
12239                 vars->link_up = 0;
12240                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12241                 /*
12242                  * Set LED mode to off since the PHY doesn't know about these
12243                  * errors
12244                  */
12245                 led_mode = LED_MODE_OFF;
12246         } else {
12247                 DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12248                 vars->link_status |= LINK_STATUS_LINK_UP;
12249                 vars->link_up = 1;
12250                 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12251                 led_mode = LED_MODE_OPER;
12252         }
12253         /* Update the LED according to the link state */
12254         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12255
12256         /* Update link status in the shared memory */
12257         bnx2x_update_mng(params, vars->link_status);
12258
12259         /* C. Trigger General Attention */
12260         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12261         bnx2x_notify_link_changed(bp);
12262 }
12263
12264 /******************************************************************************
12265 * Description:
12266 *       This function checks for half opened connection change indication.
12267 *       When such change occurs, it calls the bnx2x_analyze_link_error
12268 *       to check if Remote Fault is set or cleared. Reception of remote fault
12269 *       status message in the MAC indicates that the peer's MAC has detected
12270 *       a fault, for example, due to break in the TX side of fiber.
12271 *
12272 ******************************************************************************/
12273 static void bnx2x_check_half_open_conn(struct link_params *params,
12274                                        struct link_vars *vars)
12275 {
12276         struct bnx2x *bp = params->bp;
12277         u32 lss_status = 0;
12278         u32 mac_base;
12279         /* In case link status is physically up @ 10G do */
12280         if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12281                 return;
12282
12283         if (CHIP_IS_E3(bp) &&
12284             (REG_RD(bp, MISC_REG_RESET_REG_2) &
12285               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12286                 /* Check E3 XMAC */
12287                 /*
12288                  * Note that link speed cannot be queried here, since it may be
12289                  * zero while link is down. In case UMAC is active, LSS will
12290                  * simply not be set
12291                  */
12292                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12293
12294                 /* Clear stick bits (Requires rising edge) */
12295                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12296                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12297                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12298                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12299                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
12300                         lss_status = 1;
12301
12302                 bnx2x_analyze_link_error(params, vars, lss_status);
12303         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12304                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12305                 /* Check E1X / E2 BMAC */
12306                 u32 lss_status_reg;
12307                 u32 wb_data[2];
12308                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12309                         NIG_REG_INGRESS_BMAC0_MEM;
12310                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
12311                 if (CHIP_IS_E2(bp))
12312                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12313                 else
12314                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12315
12316                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12317                 lss_status = (wb_data[0] > 0);
12318
12319                 bnx2x_analyze_link_error(params, vars, lss_status);
12320         }
12321 }
12322
12323 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12324 {
12325         struct bnx2x *bp = params->bp;
12326         u16 phy_idx;
12327         if (!params) {
12328                 DP(NETIF_MSG_LINK, "Uninitialized params !\n");
12329                 return;
12330         }
12331
12332         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
12333                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
12334                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
12335                         bnx2x_check_half_open_conn(params, vars);
12336                         break;
12337                 }
12338         }
12339
12340         if (CHIP_IS_E3(bp))
12341                 bnx2x_check_over_curr(params, vars);
12342 }
12343
12344 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12345 {
12346         u8 phy_index;
12347         struct bnx2x_phy phy;
12348         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12349               phy_index++) {
12350                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12351                                        0, &phy) != 0) {
12352                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12353                         return 0;
12354                 }
12355
12356                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12357                         return 1;
12358         }
12359         return 0;
12360 }
12361
12362 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12363                              u32 shmem_base,
12364                              u32 shmem2_base,
12365                              u8 port)
12366 {
12367         u8 phy_index, fan_failure_det_req = 0;
12368         struct bnx2x_phy phy;
12369         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12370               phy_index++) {
12371                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12372                                        port, &phy)
12373                     != 0) {
12374                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12375                         return 0;
12376                 }
12377                 fan_failure_det_req |= (phy.flags &
12378                                         FLAGS_FAN_FAILURE_DET_REQ);
12379         }
12380         return fan_failure_det_req;
12381 }
12382
12383 void bnx2x_hw_reset_phy(struct link_params *params)
12384 {
12385         u8 phy_index;
12386         struct bnx2x *bp = params->bp;
12387         bnx2x_update_mng(params, 0);
12388         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12389                        (NIG_MASK_XGXS0_LINK_STATUS |
12390                         NIG_MASK_XGXS0_LINK10G |
12391                         NIG_MASK_SERDES0_LINK_STATUS |
12392                         NIG_MASK_MI_INT));
12393
12394         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12395               phy_index++) {
12396                 if (params->phy[phy_index].hw_reset) {
12397                         params->phy[phy_index].hw_reset(
12398                                 &params->phy[phy_index],
12399                                 params);
12400                         params->phy[phy_index] = phy_null;
12401                 }
12402         }
12403 }
12404
12405 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12406                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
12407                             u8 port)
12408 {
12409         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12410         u32 val;
12411         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12412         if (CHIP_IS_E3(bp)) {
12413                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12414                                               shmem_base,
12415                                               port,
12416                                               &gpio_num,
12417                                               &gpio_port) != 0)
12418                         return;
12419         } else {
12420                 struct bnx2x_phy phy;
12421                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12422                       phy_index++) {
12423                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12424                                                shmem2_base, port, &phy)
12425                             != 0) {
12426                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
12427                                 return;
12428                         }
12429                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12430                                 gpio_num = MISC_REGISTERS_GPIO_3;
12431                                 gpio_port = port;
12432                                 break;
12433                         }
12434                 }
12435         }
12436
12437         if (gpio_num == 0xff)
12438                 return;
12439
12440         /* Set GPIO3 to trigger SFP+ module insertion/removal */
12441         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12442
12443         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12444         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12445         gpio_port ^= (swap_val && swap_override);
12446
12447         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12448                 (gpio_num + (gpio_port << 2));
12449
12450         sync_offset = shmem_base +
12451                 offsetof(struct shmem_region,
12452                          dev_info.port_hw_config[port].aeu_int_mask);
12453         REG_WR(bp, sync_offset, vars->aeu_int_mask);
12454
12455         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12456                        gpio_num, gpio_port, vars->aeu_int_mask);
12457
12458         if (port == 0)
12459                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12460         else
12461                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12462
12463         /* Open appropriate AEU for interrupts */
12464         aeu_mask = REG_RD(bp, offset);
12465         aeu_mask |= vars->aeu_int_mask;
12466         REG_WR(bp, offset, aeu_mask);
12467
12468         /* Enable the GPIO to trigger interrupt */
12469         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12470         val |= 1 << (gpio_num + (gpio_port << 2));
12471         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12472 }