drivers/net/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2011 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30
  31 /********************************************************/
  32 #define ETH_HLEN                        14
  33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  34 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  35 #define ETH_MIN_PACKET_SIZE             60
  36 #define ETH_MAX_PACKET_SIZE             1500
  37 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  38 #define MDIO_ACCESS_TIMEOUT             1000
  39 #define BMAC_CONTROL_RX_ENABLE          2
  40 #define WC_LANE_MAX                     4
  41 #define I2C_SWITCH_WIDTH                2
  42 #define I2C_BSC0                        0
  43 #define I2C_BSC1                        1
  44 #define I2C_WA_RETRY_CNT                3
  45 #define MCPR_IMC_COMMAND_READ_OP        1
  46 #define MCPR_IMC_COMMAND_WRITE_OP       2
  47
  48 /***********************************************************/
  49 /*                      Shortcut definitions               */
  50 /***********************************************************/
  51
  52 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  53
  54 #define NIG_STATUS_EMAC0_MI_INT \
  55                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  56 #define NIG_STATUS_XGXS0_LINK10G \
  57                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  58 #define NIG_STATUS_XGXS0_LINK_STATUS \
  59                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  60 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  62 #define NIG_STATUS_SERDES0_LINK_STATUS \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  64 #define NIG_MASK_MI_INT \
  65                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  66 #define NIG_MASK_XGXS0_LINK10G \
  67                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  68 #define NIG_MASK_XGXS0_LINK_STATUS \
  69                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  70 #define NIG_MASK_SERDES0_LINK_STATUS \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  72
  73 #define MDIO_AN_CL73_OR_37_COMPLETE \
  74                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  75                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  76
  77 #define XGXS_RESET_BITS \
  78         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  79          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  80          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  83
  84 #define SERDES_RESET_BITS \
  85         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  89
  90 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  91 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  92 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  93 #define AUTONEG_PARALLEL \
  94                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  95 #define AUTONEG_SGMII_FIBER_AUTODET \
  96                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  97 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  98
  99 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 100                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 101 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 102                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 103 #define GP_STATUS_SPEED_MASK \
 104                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 105 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 106 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 107 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 108 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 109 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 110 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 111 #define GP_STATUS_10G_HIG \
 112                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 113 #define GP_STATUS_10G_CX4 \
 114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 115 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 116 #define GP_STATUS_10G_KX4 \
 117                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 118 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 119 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 120 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 121 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 122 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 123 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 124 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 125 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 126 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 127 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 128 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 129 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 130 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 131 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 132 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 133 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 134 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 135 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 136 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 137
 138
 139
 140 /* */
 141 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 142         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 143         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 144
 145
 146 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 147         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 148         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 149         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 150
 151 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 152         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 153         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 154
 155 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 156         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 157 #define SFP_EEPROM_OPTIONS_SIZE                 2
 158
 159 #define EDC_MODE_LINEAR                         0x0022
 160 #define EDC_MODE_LIMITING                               0x0044
 161 #define EDC_MODE_PASSIVE_DAC                    0x0055
 162
 163
 164 /* BRB thresholds for E2*/
 165 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE             170
 166 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE         0
 167
 168 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE              250
 169 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE          0
 170
 171 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE              10
 172 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE          90
 173
 174 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                       50
 175 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE           250
 176
 177 /* BRB thresholds for E3A0 */
 178 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE           290
 179 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE               0
 180
 181 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE            410
 182 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE                0
 183
 184 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE            10
 185 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE                170
 186
 187 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE             50
 188 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE         410
 189
 190
 191 /* BRB thresholds for E3B0 2 port mode*/
 192 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                1025
 193 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 194
 195 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE         1025
 196 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 197
 198 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 199 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     1025
 200
 201 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE          50
 202 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE      1025
 203
 204 /* only for E3B0*/
 205 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                        1025
 206 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                 1025
 207
 208 /* Lossy +Lossless GUARANTIED == GUART */
 209 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                  284
 210 /* Lossless +Lossless*/
 211 #define PFC_E3B0_2P_PAUSE_LB_GUART                      236
 212 /* Lossy +Lossy*/
 213 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART                  342
 214
 215 /* Lossy +Lossless*/
 216 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART               284
 217 /* Lossless +Lossless*/
 218 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART           236
 219 /* Lossy +Lossy*/
 220 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART               336
 221 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 222
 223 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART             0
 224 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST                0
 225
 226 /* BRB thresholds for E3B0 4 port mode */
 227 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                304
 228 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 229
 230 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE         384
 231 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 232
 233 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 234 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     304
 235
 236 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE          50
 237 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE      384
 238
 239
 240 /* only for E3B0*/
 241 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                        304
 242 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                 384
 243 #define PFC_E3B0_4P_LB_GUART                            120
 244
 245 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART             120
 246 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 247
 248 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART             80
 249 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST                120
 250
 251 #define DCBX_INVALID_COS                                        (0xFF)
 252
 253 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 254 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 255 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 256 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 257 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 258
 259 #define MAX_PACKET_SIZE                                 (9700)
 260 #define WC_UC_TIMEOUT                                   100
 261
 262 /**********************************************************/
 263 /*                     INTERFACE                          */
 264 /**********************************************************/
 265
 266 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 267         bnx2x_cl45_write(_bp, _phy, \
 268                 (_phy)->def_md_devad, \
 269                 (_bank + (_addr & 0xf)), \
 270                 _val)
 271
 272 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 273         bnx2x_cl45_read(_bp, _phy, \
 274                 (_phy)->def_md_devad, \
 275                 (_bank + (_addr & 0xf)), \
 276                 _val)
 277
 278 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 279 {
 280         u32 val = REG_RD(bp, reg);
 281
 282         val |= bits;
 283         REG_WR(bp, reg, val);
 284         return val;
 285 }
 286
 287 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 288 {
 289         u32 val = REG_RD(bp, reg);
 290
 291         val &= ~bits;
 292         REG_WR(bp, reg, val);
 293         return val;
 294 }
 295
 296 /******************************************************************/
 297 /*                      EPIO/GPIO section                         */
 298 /******************************************************************/
 299 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 300 {
 301         u32 epio_mask, gp_oenable;
 302         *en = 0;
 303         /* Sanity check */
 304         if (epio_pin > 31) {
 305                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 306                 return;
 307         }
 308
 309         epio_mask = 1 << epio_pin;
 310         /* Set this EPIO to output */
 311         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 312         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 313
 314         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 315 }
 316 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 317 {
 318         u32 epio_mask, gp_output, gp_oenable;
 319
 320         /* Sanity check */
 321         if (epio_pin > 31) {
 322                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 323                 return;
 324         }
 325         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 326         epio_mask = 1 << epio_pin;
 327         /* Set this EPIO to output */
 328         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 329         if (en)
 330                 gp_output |= epio_mask;
 331         else
 332                 gp_output &= ~epio_mask;
 333
 334         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 335
 336         /* Set the value for this EPIO */
 337         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 338         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 339 }
 340
 341 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 342 {
 343         if (pin_cfg == PIN_CFG_NA)
 344                 return;
 345         if (pin_cfg >= PIN_CFG_EPIO0) {
 346                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 347         } else {
 348                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 349                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 350                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 351         }
 352 }
 353
 354 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 355 {
 356         if (pin_cfg == PIN_CFG_NA)
 357                 return -EINVAL;
 358         if (pin_cfg >= PIN_CFG_EPIO0) {
 359                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 360         } else {
 361                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 362                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 363                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 364         }
 365         return 0;
 366
 367 }
 368 /******************************************************************/
 369 /*                              ETS section                       */
 370 /******************************************************************/
 371 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 372 {
 373         /* ETS disabled configuration*/
 374         struct bnx2x *bp = params->bp;
 375
 376         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 377
 378         /*
 379          * mapping between entry  priority to client number (0,1,2 -debug and
 380          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 381          * 3bits client num.
 382          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 383          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 384          */
 385
 386         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 387         /*
 388          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 389          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 390          * COS0 entry, 4 - COS1 entry.
 391          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 392          * bit4   bit3    bit2   bit1     bit0
 393          * MCP and debug are strict
 394          */
 395
 396         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 397         /* defines which entries (clients) are subjected to WFQ arbitration */
 398         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 399         /*
 400          * For strict priority entries defines the number of consecutive
 401          * slots for the highest priority.
 402          */
 403         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 404         /*
 405          * mapping between the CREDIT_WEIGHT registers and actual client
 406          * numbers
 407          */
 408         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 409         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 410         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 411
 412         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 413         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 414         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 415         /* ETS mode disable */
 416         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 417         /*
 418          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 419          * weight for COS0/COS1.
 420          */
 421         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 422         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 423         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 424         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 425         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 426         /* Defines the number of consecutive slots for the strict priority */
 427         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 428 }
 429 /******************************************************************************
 430 * Description:
 431 *       Getting min_w_val will be set according to line speed .
 432 *.
 433 ******************************************************************************/
 434 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 435 {
 436         u32 min_w_val = 0;
 437         /* Calculate min_w_val.*/
 438         if (vars->link_up) {
 439                 if (SPEED_20000 == vars->line_speed)
 440                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 441                 else
 442                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 443         } else
 444                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 445         /**
 446          *  If the link isn't up (static configuration for example ) The
 447          *  link will be according to 20GBPS.
 448         */
 449         return min_w_val;
 450 }
 451 /******************************************************************************
 452 * Description:
 453 *       Getting credit upper bound form min_w_val.
 454 *.
 455 ******************************************************************************/
 456 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 457 {
 458         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 459                                                 MAX_PACKET_SIZE);
 460         return credit_upper_bound;
 461 }
 462 /******************************************************************************
 463 * Description:
 464 *       Set credit upper bound for NIG.
 465 *.
 466 ******************************************************************************/
 467 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 468         const struct link_params *params,
 469         const u32 min_w_val)
 470 {
 471         struct bnx2x *bp = params->bp;
 472         const u8 port = params->port;
 473         const u32 credit_upper_bound =
 474             bnx2x_ets_get_credit_upper_bound(min_w_val);
 475
 476         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 477                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 478         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 479                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 480         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 481                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 482         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 483                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 484         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 485                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 486         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 487                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 488
 489         if (0 == port) {
 490                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 491                         credit_upper_bound);
 492                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 493                         credit_upper_bound);
 494                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 495                         credit_upper_bound);
 496         }
 497 }
 498 /******************************************************************************
 499 * Description:
 500 *       Will return the NIG ETS registers to init values.Except
 501 *       credit_upper_bound.
 502 *       That isn't used in this configuration (No WFQ is enabled) and will be
 503 *       configured acording to spec
 504 *.
 505 ******************************************************************************/
 506 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 507                                         const struct link_vars *vars)
 508 {
 509         struct bnx2x *bp = params->bp;
 510         const u8 port = params->port;
 511         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 512         /**
 513          * mapping between entry  priority to client number (0,1,2 -debug and
 514          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 515          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 516          * reset value or init tool
 517          */
 518         if (port) {
 519                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 520                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 521         } else {
 522                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 523                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 524         }
 525         /**
 526         * For strict priority entries defines the number of consecutive
 527         * slots for the highest priority.
 528         */
 529         /* TODO_ETS - Should be done by reset value or init tool */
 530         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 531                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 532         /**
 533          * mapping between the CREDIT_WEIGHT registers and actual client
 534          * numbers
 535          */
 536         /* TODO_ETS - Should be done by reset value or init tool */
 537         if (port) {
 538                 /*Port 1 has 6 COS*/
 539                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 540                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 541         } else {
 542                 /*Port 0 has 9 COS*/
 543                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 544                        0x43210876);
 545                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 546         }
 547
 548         /**
 549          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 550          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 551          * COS0 entry, 4 - COS1 entry.
 552          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 553          * bit4   bit3    bit2   bit1     bit0
 554          * MCP and debug are strict
 555          */
 556         if (port)
 557                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 558         else
 559                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 560         /* defines which entries (clients) are subjected to WFQ arbitration */
 561         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 562                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 563
 564         /**
 565         * Please notice the register address are note continuous and a
 566         * for here is note appropriate.In 2 port mode port0 only COS0-5
 567         * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 568         * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 569         * are never used for WFQ
 570         */
 571         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 572                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 573         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 574                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 575         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 576                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 578                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 579         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 580                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 581         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 582                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 583         if (0 == port) {
 584                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 585                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 586                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 587         }
 588
 589         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 590 }
 591 /******************************************************************************
 592 * Description:
 593 *       Set credit upper bound for PBF.
 594 *.
 595 ******************************************************************************/
 596 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 597         const struct link_params *params,
 598         const u32 min_w_val)
 599 {
 600         struct bnx2x *bp = params->bp;
 601         const u32 credit_upper_bound =
 602             bnx2x_ets_get_credit_upper_bound(min_w_val);
 603         const u8 port = params->port;
 604         u32 base_upper_bound = 0;
 605         u8 max_cos = 0;
 606         u8 i = 0;
 607         /**
 608         * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 609         * port mode port1 has COS0-2 that can be used for WFQ.
 610         */
 611         if (0 == port) {
 612                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 613                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 614         } else {
 615                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 616                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 617         }
 618
 619         for (i = 0; i < max_cos; i++)
 620                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 621 }
 622
 623 /******************************************************************************
 624 * Description:
 625 *       Will return the PBF ETS registers to init values.Except
 626 *       credit_upper_bound.
 627 *       That isn't used in this configuration (No WFQ is enabled) and will be
 628 *       configured acording to spec
 629 *.
 630 ******************************************************************************/
 631 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 632 {
 633         struct bnx2x *bp = params->bp;
 634         const u8 port = params->port;
 635         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 636         u8 i = 0;
 637         u32 base_weight = 0;
 638         u8 max_cos = 0;
 639
 640         /**
 641          * mapping between entry  priority to client number 0 - COS0
 642          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 643          * TODO_ETS - Should be done by reset value or init tool
 644          */
 645         if (port)
 646                 /*  0x688 (|011|0 10|00 1|000) */
 647                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 648         else
 649                 /*  (10 1|100 |011|0 10|00 1|000) */
 650                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 651
 652         /* TODO_ETS - Should be done by reset value or init tool */
 653         if (port)
 654                 /* 0x688 (|011|0 10|00 1|000)*/
 655                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 656         else
 657         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 658         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 659
 660         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 661                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 662
 663
 664         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 665                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 666
 667         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 668                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 669         /**
 670         * In 2 port mode port0 has COS0-5 that can be used for WFQ.
 671         * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 672         */
 673         if (0 == port) {
 674                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 675                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 676         } else {
 677                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 678                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 679         }
 680
 681         for (i = 0; i < max_cos; i++)
 682                 REG_WR(bp, base_weight + (0x4 * i), 0);
 683
 684         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 685 }
 686 /******************************************************************************
 687 * Description:
 688 *       E3B0 disable will return basicly the values to init values.
 689 *.
 690 ******************************************************************************/
 691 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 692                                    const struct link_vars *vars)
 693 {
 694         struct bnx2x *bp = params->bp;
 695
 696         if (!CHIP_IS_E3B0(bp)) {
 697                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
 698                                    "\n");
 699                 return -EINVAL;
 700         }
 701
 702         bnx2x_ets_e3b0_nig_disabled(params, vars);
 703
 704         bnx2x_ets_e3b0_pbf_disabled(params);
 705
 706         return 0;
 707 }
 708
 709 /******************************************************************************
 710 * Description:
 711 *       Disable will return basicly the values to init values.
 712 *.
 713 ******************************************************************************/
 714 int bnx2x_ets_disabled(struct link_params *params,
 715                       struct link_vars *vars)
 716 {
 717         struct bnx2x *bp = params->bp;
 718         int bnx2x_status = 0;
 719
 720         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 721                 bnx2x_ets_e2e3a0_disabled(params);
 722         else if (CHIP_IS_E3B0(bp))
 723                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 724         else {
 725                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 726                 return -EINVAL;
 727         }
 728
 729         return bnx2x_status;
 730 }
 731
 732 /******************************************************************************
 733 * Description
 734 *       Set the COS mappimg to SP and BW until this point all the COS are not
 735 *       set as SP or BW.
 736 ******************************************************************************/
 737 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 738                                   const struct bnx2x_ets_params *ets_params,
 739                                   const u8 cos_sp_bitmap,
 740                                   const u8 cos_bw_bitmap)
 741 {
 742         struct bnx2x *bp = params->bp;
 743         const u8 port = params->port;
 744         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 745         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 746         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 747         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 748
 749         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 750                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 751
 752         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 753                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 754
 755         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 756                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 757                nig_cli_subject2wfq_bitmap);
 758
 759         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 760                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 761                pbf_cli_subject2wfq_bitmap);
 762
 763         return 0;
 764 }
 765
 766 /******************************************************************************
 767 * Description:
 768 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 769 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 770 ******************************************************************************/
 771 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 772                                      const u8 cos_entry,
 773                                      const u32 min_w_val_nig,
 774                                      const u32 min_w_val_pbf,
 775                                      const u16 total_bw,
 776                                      const u8 bw,
 777                                      const u8 port)
 778 {
 779         u32 nig_reg_adress_crd_weight = 0;
 780         u32 pbf_reg_adress_crd_weight = 0;
 781         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 782         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 783         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 784
 785         switch (cos_entry) {
 786         case 0:
 787             nig_reg_adress_crd_weight =
 788                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 789                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 790              pbf_reg_adress_crd_weight = (port) ?
 791                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 792              break;
 793         case 1:
 794              nig_reg_adress_crd_weight = (port) ?
 795                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 796                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 797              pbf_reg_adress_crd_weight = (port) ?
 798                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 799              break;
 800         case 2:
 801              nig_reg_adress_crd_weight = (port) ?
 802                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 803                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 804
 805                  pbf_reg_adress_crd_weight = (port) ?
 806                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 807              break;
 808         case 3:
 809             if (port)
 810                         return -EINVAL;
 811              nig_reg_adress_crd_weight =
 812                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 813              pbf_reg_adress_crd_weight =
 814                  PBF_REG_COS3_WEIGHT_P0;
 815              break;
 816         case 4:
 817             if (port)
 818                 return -EINVAL;
 819              nig_reg_adress_crd_weight =
 820                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 821              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 822              break;
 823         case 5:
 824             if (port)
 825                 return -EINVAL;
 826              nig_reg_adress_crd_weight =
 827                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 828              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 829              break;
 830         }
 831
 832         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 833
 834         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 835
 836         return 0;
 837 }
 838 /******************************************************************************
 839 * Description:
 840 *       Calculate the total BW.A value of 0 isn't legal.
 841 *.
 842 ******************************************************************************/
 843 static int bnx2x_ets_e3b0_get_total_bw(
 844         const struct link_params *params,
 845         const struct bnx2x_ets_params *ets_params,
 846         u16 *total_bw)
 847 {
 848         struct bnx2x *bp = params->bp;
 849         u8 cos_idx = 0;
 850
 851         *total_bw = 0 ;
 852         /* Calculate total BW requested */
 853         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 854                 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
 855                         *total_bw +=
 856                                 ets_params->cos[cos_idx].params.bw_params.bw;
 857                 }
 858         }
 859
 860         /* Check total BW is valid */
 861         if ((100 != *total_bw) || (0 == *total_bw)) {
 862                 if (0 == *total_bw) {
 863                         DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW"
 864                                            "shouldn't be 0\n");
 865                         return -EINVAL;
 866                 }
 867                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW should be"
 868                                    "100\n");
 869                 /**
 870                 *   We can handle a case whre the BW isn't 100 this can happen
 871                 *   if the TC are joined.
 872                 */
 873         }
 874         return 0;
 875 }
 876
 877 /******************************************************************************
 878 * Description:
 879 *       Invalidate all the sp_pri_to_cos.
 880 *.
 881 ******************************************************************************/
 882 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 883 {
 884         u8 pri = 0;
 885         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 886                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 887 }
 888 /******************************************************************************
 889 * Description:
 890 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 891 *       according to sp_pri_to_cos.
 892 *.
 893 ******************************************************************************/
 894 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 895                                             u8 *sp_pri_to_cos, const u8 pri,
 896                                             const u8 cos_entry)
 897 {
 898         struct bnx2x *bp = params->bp;
 899         const u8 port = params->port;
 900         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 901                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 902
 903         if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
 904                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 905                                    "parameter There can't be two COS's with"
 906                                    "the same strict pri\n");
 907                 return -EINVAL;
 908         }
 909
 910         if (pri > max_num_of_cos) {
 911                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid"
 912                                "parameter Illegal strict priority\n");
 913             return -EINVAL;
 914         }
 915
 916         sp_pri_to_cos[pri] = cos_entry;
 917         return 0;
 918
 919 }
 920
 921 /******************************************************************************
 922 * Description:
 923 *       Returns the correct value according to COS and priority in
 924 *       the sp_pri_cli register.
 925 *.
 926 ******************************************************************************/
 927 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 928                                          const u8 pri_set,
 929                                          const u8 pri_offset,
 930                                          const u8 entry_size)
 931 {
 932         u64 pri_cli_nig = 0;
 933         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 934                                                     (pri_set + pri_offset));
 935
 936         return pri_cli_nig;
 937 }
 938 /******************************************************************************
 939 * Description:
 940 *       Returns the correct value according to COS and priority in the
 941 *       sp_pri_cli register for NIG.
 942 *.
 943 ******************************************************************************/
 944 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 945 {
 946         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 947         const u8 nig_cos_offset = 3;
 948         const u8 nig_pri_offset = 3;
 949
 950         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
 951                 nig_pri_offset, 4);
 952
 953 }
 954 /******************************************************************************
 955 * Description:
 956 *       Returns the correct value according to COS and priority in the
 957 *       sp_pri_cli register for PBF.
 958 *.
 959 ******************************************************************************/
 960 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
 961 {
 962         const u8 pbf_cos_offset = 0;
 963         const u8 pbf_pri_offset = 0;
 964
 965         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
 966                 pbf_pri_offset, 3);
 967
 968 }
 969
 970 /******************************************************************************
 971 * Description:
 972 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 973 *       according to sp_pri_to_cos.(which COS has higher priority)
 974 *.
 975 ******************************************************************************/
 976 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
 977                                              u8 *sp_pri_to_cos)
 978 {
 979         struct bnx2x *bp = params->bp;
 980         u8 i = 0;
 981         const u8 port = params->port;
 982         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 983         u64 pri_cli_nig = 0x210;
 984         u32 pri_cli_pbf = 0x0;
 985         u8 pri_set = 0;
 986         u8 pri_bitmask = 0;
 987         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 988                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 989
 990         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
 991
 992         /* Set all the strict priority first */
 993         for (i = 0; i < max_num_of_cos; i++) {
 994                 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
 995                         if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
 996                                 DP(NETIF_MSG_LINK,
 997                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
 998                                            "invalid cos entry\n");
 999                                 return -EINVAL;
1000                         }
1001
1002                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1003                             sp_pri_to_cos[i], pri_set);
1004
1005                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1006                             sp_pri_to_cos[i], pri_set);
1007                         pri_bitmask = 1 << sp_pri_to_cos[i];
1008                         /* COS is used remove it from bitmap.*/
1009                         if (0 == (pri_bitmask & cos_bit_to_set)) {
1010                                 DP(NETIF_MSG_LINK,
1011                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1012                                         "invalid There can't be two COS's with"
1013                                         " the same strict pri\n");
1014                                 return -EINVAL;
1015                         }
1016                         cos_bit_to_set &= ~pri_bitmask;
1017                         pri_set++;
1018                 }
1019         }
1020
1021         /* Set all the Non strict priority i= COS*/
1022         for (i = 0; i < max_num_of_cos; i++) {
1023                 pri_bitmask = 1 << i;
1024                 /* Check if COS was already used for SP */
1025                 if (pri_bitmask & cos_bit_to_set) {
1026                         /* COS wasn't used for SP */
1027                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1028                             i, pri_set);
1029
1030                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1031                             i, pri_set);
1032                         /* COS is used remove it from bitmap.*/
1033                         cos_bit_to_set &= ~pri_bitmask;
1034                         pri_set++;
1035                 }
1036         }
1037
1038         if (pri_set != max_num_of_cos) {
1039                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1040                                    "entries were set\n");
1041                 return -EINVAL;
1042         }
1043
1044         if (port) {
1045                 /* Only 6 usable clients*/
1046                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1047                        (u32)pri_cli_nig);
1048
1049                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1050         } else {
1051                 /* Only 9 usable clients*/
1052                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1053                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1054
1055                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1056                        pri_cli_nig_lsb);
1057                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1058                        pri_cli_nig_msb);
1059
1060                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1061         }
1062         return 0;
1063 }
1064
1065 /******************************************************************************
1066 * Description:
1067 *       Configure the COS to ETS according to BW and SP settings.
1068 ******************************************************************************/
1069 int bnx2x_ets_e3b0_config(const struct link_params *params,
1070                          const struct link_vars *vars,
1071                          const struct bnx2x_ets_params *ets_params)
1072 {
1073         struct bnx2x *bp = params->bp;
1074         int bnx2x_status = 0;
1075         const u8 port = params->port;
1076         u16 total_bw = 0;
1077         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1078         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1079         u8 cos_bw_bitmap = 0;
1080         u8 cos_sp_bitmap = 0;
1081         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1082         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1083                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1084         u8 cos_entry = 0;
1085
1086         if (!CHIP_IS_E3B0(bp)) {
1087                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
1088                                    "\n");
1089                 return -EINVAL;
1090         }
1091
1092         if ((ets_params->num_of_cos > max_num_of_cos)) {
1093                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1094                                    "isn't supported\n");
1095                 return -EINVAL;
1096         }
1097
1098         /* Prepare sp strict priority parameters*/
1099         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1100
1101         /* Prepare BW parameters*/
1102         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1103                                                    &total_bw);
1104         if (0 != bnx2x_status) {
1105                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config get_total_bw failed "
1106                                    "\n");
1107                 return -EINVAL;
1108         }
1109
1110         /**
1111          *  Upper bound is set according to current link speed (min_w_val
1112          *  should be the same for upper bound and COS credit val).
1113          */
1114         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1115         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1116
1117
1118         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1119                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1120                         cos_bw_bitmap |= (1 << cos_entry);
1121                         /**
1122                          * The function also sets the BW in HW(not the mappin
1123                          * yet)
1124                          */
1125                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1126                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1127                                 total_bw,
1128                                 ets_params->cos[cos_entry].params.bw_params.bw,
1129                                  port);
1130                 } else if (bnx2x_cos_state_strict ==
1131                         ets_params->cos[cos_entry].state){
1132                         cos_sp_bitmap |= (1 << cos_entry);
1133
1134                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1135                                 params,
1136                                 sp_pri_to_cos,
1137                                 ets_params->cos[cos_entry].params.sp_params.pri,
1138                                 cos_entry);
1139
1140                 } else {
1141                         DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config cos state not"
1142                                            " valid\n");
1143                         return -EINVAL;
1144                 }
1145                 if (0 != bnx2x_status) {
1146                         DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config set cos bw "
1147                                            "failed\n");
1148                         return bnx2x_status;
1149                 }
1150         }
1151
1152         /* Set SP register (which COS has higher priority) */
1153         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1154                                                          sp_pri_to_cos);
1155
1156         if (0 != bnx2x_status) {
1157                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config set_pri_cli_reg "
1158                                    "failed\n");
1159                 return bnx2x_status;
1160         }
1161
1162         /* Set client mapping of BW and strict */
1163         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1164                                               cos_sp_bitmap,
1165                                               cos_bw_bitmap);
1166
1167         if (0 != bnx2x_status) {
1168                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1169                 return bnx2x_status;
1170         }
1171         return 0;
1172 }
1173 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1174 {
1175         /* ETS disabled configuration */
1176         struct bnx2x *bp = params->bp;
1177         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1178         /*
1179          * defines which entries (clients) are subjected to WFQ arbitration
1180          * COS0 0x8
1181          * COS1 0x10
1182          */
1183         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1184         /*
1185          * mapping between the ARB_CREDIT_WEIGHT registers and actual
1186          * client numbers (WEIGHT_0 does not actually have to represent
1187          * client 0)
1188          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1189          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1190          */
1191         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1192
1193         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1194                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1195         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1196                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1197
1198         /* ETS mode enabled*/
1199         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1200
1201         /* Defines the number of consecutive slots for the strict priority */
1202         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1203         /*
1204          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1205          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1206          * entry, 4 - COS1 entry.
1207          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1208          * bit4   bit3    bit2     bit1    bit0
1209          * MCP and debug are strict
1210          */
1211         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1212
1213         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1214         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1215                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1216         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1217                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1218 }
1219
1220 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1221                         const u32 cos1_bw)
1222 {
1223         /* ETS disabled configuration*/
1224         struct bnx2x *bp = params->bp;
1225         const u32 total_bw = cos0_bw + cos1_bw;
1226         u32 cos0_credit_weight = 0;
1227         u32 cos1_credit_weight = 0;
1228
1229         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1230
1231         if ((0 == total_bw) ||
1232             (0 == cos0_bw) ||
1233             (0 == cos1_bw)) {
1234                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1235                 return;
1236         }
1237
1238         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1239                 total_bw;
1240         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1241                 total_bw;
1242
1243         bnx2x_ets_bw_limit_common(params);
1244
1245         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1246         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1247
1248         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1249         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1250 }
1251
1252 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1253 {
1254         /* ETS disabled configuration*/
1255         struct bnx2x *bp = params->bp;
1256         u32 val = 0;
1257
1258         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1259         /*
1260          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1261          * as strict.  Bits 0,1,2 - debug and management entries,
1262          * 3 - COS0 entry, 4 - COS1 entry.
1263          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1264          *  bit4   bit3   bit2      bit1     bit0
1265          * MCP and debug are strict
1266          */
1267         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1268         /*
1269          * For strict priority entries defines the number of consecutive slots
1270          * for the highest priority.
1271          */
1272         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1273         /* ETS mode disable */
1274         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1275         /* Defines the number of consecutive slots for the strict priority */
1276         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1277
1278         /* Defines the number of consecutive slots for the strict priority */
1279         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1280
1281         /*
1282          * mapping between entry  priority to client number (0,1,2 -debug and
1283          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1284          * 3bits client num.
1285          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1286          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1287          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1288          */
1289         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1290         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1291
1292         return 0;
1293 }
1294 /******************************************************************/
1295 /*                      PFC section                               */
1296 /******************************************************************/
1297
1298 static void bnx2x_update_pfc_xmac(struct link_params *params,
1299                                   struct link_vars *vars,
1300                                   u8 is_lb)
1301 {
1302         struct bnx2x *bp = params->bp;
1303         u32 xmac_base;
1304         u32 pause_val, pfc0_val, pfc1_val;
1305
1306         /* XMAC base adrr */
1307         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1308
1309         /* Initialize pause and pfc registers */
1310         pause_val = 0x18000;
1311         pfc0_val = 0xFFFF8000;
1312         pfc1_val = 0x2;
1313
1314         /* No PFC support */
1315         if (!(params->feature_config_flags &
1316               FEATURE_CONFIG_PFC_ENABLED)) {
1317
1318                 /*
1319                  * RX flow control - Process pause frame in receive direction
1320                  */
1321                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1322                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1323
1324                 /*
1325                  * TX flow control - Send pause packet when buffer is full
1326                  */
1327                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1328                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1329         } else {/* PFC support */
1330                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1331                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1332                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1333                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1334         }
1335
1336         /* Write pause and PFC registers */
1337         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1338         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1339         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1340
1341
1342         /* Set MAC address for source TX Pause/PFC frames */
1343         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1344                ((params->mac_addr[2] << 24) |
1345                 (params->mac_addr[3] << 16) |
1346                 (params->mac_addr[4] << 8) |
1347                 (params->mac_addr[5])));
1348         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1349                ((params->mac_addr[0] << 8) |
1350                 (params->mac_addr[1])));
1351
1352         udelay(30);
1353 }
1354
1355
1356 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1357                                     u32 pfc_frames_sent[2],
1358                                     u32 pfc_frames_received[2])
1359 {
1360         /* Read pfc statistic */
1361         struct bnx2x *bp = params->bp;
1362         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1363         u32 val_xon = 0;
1364         u32 val_xoff = 0;
1365
1366         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1367
1368         /* PFC received frames */
1369         val_xoff = REG_RD(bp, emac_base +
1370                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1371         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1372         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1373         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1374
1375         pfc_frames_received[0] = val_xon + val_xoff;
1376
1377         /* PFC received sent */
1378         val_xoff = REG_RD(bp, emac_base +
1379                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1380         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1381         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1382         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1383
1384         pfc_frames_sent[0] = val_xon + val_xoff;
1385 }
1386
1387 /* Read pfc statistic*/
1388 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1389                          u32 pfc_frames_sent[2],
1390                          u32 pfc_frames_received[2])
1391 {
1392         /* Read pfc statistic */
1393         struct bnx2x *bp = params->bp;
1394
1395         DP(NETIF_MSG_LINK, "pfc statistic\n");
1396
1397         if (!vars->link_up)
1398                 return;
1399
1400         if (MAC_TYPE_EMAC == vars->mac_type) {
1401                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1402                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1403                                         pfc_frames_received);
1404         }
1405 }
1406 /******************************************************************/
1407 /*                      MAC/PBF section                           */
1408 /******************************************************************/
1409 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1410 {
1411         u32 mode, emac_base;
1412         /**
1413          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1414          * (a value of 49==0x31) and make sure that the AUTO poll is off
1415          */
1416
1417         if (CHIP_IS_E2(bp))
1418                 emac_base = GRCBASE_EMAC0;
1419         else
1420                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1421         mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1422         mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1423                   EMAC_MDIO_MODE_CLOCK_CNT);
1424         if (USES_WARPCORE(bp))
1425                 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1426         else
1427                 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1428
1429         mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1430         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1431
1432         udelay(40);
1433 }
1434
1435 static void bnx2x_emac_init(struct link_params *params,
1436                             struct link_vars *vars)
1437 {
1438         /* reset and unreset the emac core */
1439         struct bnx2x *bp = params->bp;
1440         u8 port = params->port;
1441         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1442         u32 val;
1443         u16 timeout;
1444
1445         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1446                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1447         udelay(5);
1448         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1449                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1450
1451         /* init emac - use read-modify-write */
1452         /* self clear reset */
1453         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1454         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1455
1456         timeout = 200;
1457         do {
1458                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1459                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1460                 if (!timeout) {
1461                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1462                         return;
1463                 }
1464                 timeout--;
1465         } while (val & EMAC_MODE_RESET);
1466         bnx2x_set_mdio_clk(bp, params->chip_id, port);
1467         /* Set mac address */
1468         val = ((params->mac_addr[0] << 8) |
1469                 params->mac_addr[1]);
1470         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1471
1472         val = ((params->mac_addr[2] << 24) |
1473                (params->mac_addr[3] << 16) |
1474                (params->mac_addr[4] << 8) |
1475                 params->mac_addr[5]);
1476         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1477 }
1478
1479 static void bnx2x_set_xumac_nig(struct link_params *params,
1480                                 u16 tx_pause_en,
1481                                 u8 enable)
1482 {
1483         struct bnx2x *bp = params->bp;
1484
1485         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1486                enable);
1487         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1488                enable);
1489         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1490                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1491 }
1492
1493 static void bnx2x_umac_enable(struct link_params *params,
1494                             struct link_vars *vars, u8 lb)
1495 {
1496         u32 val;
1497         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1498         struct bnx2x *bp = params->bp;
1499         /* Reset UMAC */
1500         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1501                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1502         usleep_range(1000, 1000);
1503
1504         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1505                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1506
1507         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1508
1509         /**
1510          * This register determines on which events the MAC will assert
1511          * error on the i/f to the NIG along w/ EOP.
1512          */
1513
1514         /**
1515          * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1516          * params->port*0x14,      0xfffff.
1517          */
1518         /* This register opens the gate for the UMAC despite its name */
1519         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1520
1521         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1522                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1523                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1524                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1525         switch (vars->line_speed) {
1526         case SPEED_10:
1527                 val |= (0<<2);
1528                 break;
1529         case SPEED_100:
1530                 val |= (1<<2);
1531                 break;
1532         case SPEED_1000:
1533                 val |= (2<<2);
1534                 break;
1535         case SPEED_2500:
1536                 val |= (3<<2);
1537                 break;
1538         default:
1539                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1540                                vars->line_speed);
1541                 break;
1542         }
1543         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1544                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1545
1546         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1547                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1548
1549         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1550         udelay(50);
1551
1552         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1553         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1554                ((params->mac_addr[2] << 24) |
1555                 (params->mac_addr[3] << 16) |
1556                 (params->mac_addr[4] << 8) |
1557                 (params->mac_addr[5])));
1558         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1559                ((params->mac_addr[0] << 8) |
1560                 (params->mac_addr[1])));
1561
1562         /* Enable RX and TX */
1563         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1564         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1565                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1566         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1567         udelay(50);
1568
1569         /* Remove SW Reset */
1570         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1571
1572         /* Check loopback mode */
1573         if (lb)
1574                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1575         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1576
1577         /*
1578          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1579          * length used by the MAC receive logic to check frames.
1580          */
1581         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1582         bnx2x_set_xumac_nig(params,
1583                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1584         vars->mac_type = MAC_TYPE_UMAC;
1585
1586 }
1587
1588 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1589 {
1590         u32 port4mode_ovwr_val;
1591         /* Check 4-port override enabled */
1592         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1593         if (port4mode_ovwr_val & (1<<0)) {
1594                 /* Return 4-port mode override value */
1595                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1596         }
1597         /* Return 4-port mode from input pin */
1598         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1599 }
1600
1601 /* Define the XMAC mode */
1602 static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
1603 {
1604         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1605
1606         /**
1607         * In 4-port mode, need to set the mode only once, so if XMAC is
1608         * already out of reset, it means the mode has already been set,
1609         * and it must not* reset the XMAC again, since it controls both
1610         * ports of the path
1611         **/
1612
1613         if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
1614              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1615                 DP(NETIF_MSG_LINK, "XMAC already out of reset"
1616                                    " in 4-port mode\n");
1617                 return;
1618         }
1619
1620         /* Hard reset */
1621         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1622                MISC_REGISTERS_RESET_REG_2_XMAC);
1623         usleep_range(1000, 1000);
1624
1625         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1626                MISC_REGISTERS_RESET_REG_2_XMAC);
1627         if (is_port4mode) {
1628                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1629
1630                 /*  Set the number of ports on the system side to up to 2 */
1631                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1632
1633                 /* Set the number of ports on the Warp Core to 10G */
1634                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1635         } else {
1636                 /*  Set the number of ports on the system side to 1 */
1637                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1638                 if (max_speed == SPEED_10000) {
1639                         DP(NETIF_MSG_LINK, "Init XMAC to 10G x 1"
1640                                            " port per path\n");
1641                         /* Set the number of ports on the Warp Core to 10G */
1642                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1643                 } else {
1644                         DP(NETIF_MSG_LINK, "Init XMAC to 20G x 2 ports"
1645                                            " per path\n");
1646                         /* Set the number of ports on the Warp Core to 20G */
1647                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1648                 }
1649         }
1650         /* Soft reset */
1651         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1652                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1653         usleep_range(1000, 1000);
1654
1655         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1656                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1657
1658 }
1659
1660 static void bnx2x_xmac_disable(struct link_params *params)
1661 {
1662         u8 port = params->port;
1663         struct bnx2x *bp = params->bp;
1664         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1665
1666         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1667             MISC_REGISTERS_RESET_REG_2_XMAC) {
1668                 /*
1669                  * Send an indication to change the state in the NIG back to XON
1670                  * Clearing this bit enables the next set of this bit to get
1671                  * rising edge
1672                  */
1673                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1674                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1675                        (pfc_ctrl & ~(1<<1)));
1676                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1677                        (pfc_ctrl | (1<<1)));
1678                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1679                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1680                 usleep_range(1000, 1000);
1681                 bnx2x_set_xumac_nig(params, 0, 0);
1682                 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
1683                        XMAC_CTRL_REG_SOFT_RESET);
1684         }
1685 }
1686
1687 static int bnx2x_xmac_enable(struct link_params *params,
1688                              struct link_vars *vars, u8 lb)
1689 {
1690         u32 val, xmac_base;
1691         struct bnx2x *bp = params->bp;
1692         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1693
1694         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1695
1696         bnx2x_xmac_init(bp, vars->line_speed);
1697
1698         /*
1699          * This register determines on which events the MAC will assert
1700          * error on the i/f to the NIG along w/ EOP.
1701          */
1702
1703         /*
1704          * This register tells the NIG whether to send traffic to UMAC
1705          * or XMAC
1706          */
1707         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1708
1709         /* Set Max packet size */
1710         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1711
1712         /* CRC append for Tx packets */
1713         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1714
1715         /* update PFC */
1716         bnx2x_update_pfc_xmac(params, vars, 0);
1717
1718         /* Enable TX and RX */
1719         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1720
1721         /* Check loopback mode */
1722         if (lb)
1723                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1724         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1725         bnx2x_set_xumac_nig(params,
1726                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1727
1728         vars->mac_type = MAC_TYPE_XMAC;
1729
1730         return 0;
1731 }
1732 static int bnx2x_emac_enable(struct link_params *params,
1733                              struct link_vars *vars, u8 lb)
1734 {
1735         struct bnx2x *bp = params->bp;
1736         u8 port = params->port;
1737         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1738         u32 val;
1739
1740         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1741
1742         /* Disable BMAC */
1743         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1744                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1745
1746         /* enable emac and not bmac */
1747         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1748
1749         /* ASIC */
1750         if (vars->phy_flags & PHY_XGXS_FLAG) {
1751                 u32 ser_lane = ((params->lane_config &
1752                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1753                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1754
1755                 DP(NETIF_MSG_LINK, "XGXS\n");
1756                 /* select the master lanes (out of 0-3) */
1757                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1758                 /* select XGXS */
1759                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1760
1761         } else { /* SerDes */
1762                 DP(NETIF_MSG_LINK, "SerDes\n");
1763                 /* select SerDes */
1764                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1765         }
1766
1767         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1768                       EMAC_RX_MODE_RESET);
1769         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1770                       EMAC_TX_MODE_RESET);
1771
1772         if (CHIP_REV_IS_SLOW(bp)) {
1773                 /* config GMII mode */
1774                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1775                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1776         } else { /* ASIC */
1777                 /* pause enable/disable */
1778                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1779                                EMAC_RX_MODE_FLOW_EN);
1780
1781                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1782                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1783                                 EMAC_TX_MODE_FLOW_EN));
1784                 if (!(params->feature_config_flags &
1785                       FEATURE_CONFIG_PFC_ENABLED)) {
1786                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1787                                 bnx2x_bits_en(bp, emac_base +
1788                                               EMAC_REG_EMAC_RX_MODE,
1789                                               EMAC_RX_MODE_FLOW_EN);
1790
1791                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1792                                 bnx2x_bits_en(bp, emac_base +
1793                                               EMAC_REG_EMAC_TX_MODE,
1794                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1795                                                EMAC_TX_MODE_FLOW_EN));
1796                 } else
1797                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1798                                       EMAC_TX_MODE_FLOW_EN);
1799         }
1800
1801         /* KEEP_VLAN_TAG, promiscuous */
1802         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1803         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1804
1805         /*
1806          * Setting this bit causes MAC control frames (except for pause
1807          * frames) to be passed on for processing. This setting has no
1808          * affect on the operation of the pause frames. This bit effects
1809          * all packets regardless of RX Parser packet sorting logic.
1810          * Turn the PFC off to make sure we are in Xon state before
1811          * enabling it.
1812          */
1813         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1814         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1815                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1816                 /* Enable PFC again */
1817                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1818                         EMAC_REG_RX_PFC_MODE_RX_EN |
1819                         EMAC_REG_RX_PFC_MODE_TX_EN |
1820                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1821
1822                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1823                         ((0x0101 <<
1824                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1825                          (0x00ff <<
1826                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1827                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1828         }
1829         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1830
1831         /* Set Loopback */
1832         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1833         if (lb)
1834                 val |= 0x810;
1835         else
1836                 val &= ~0x810;
1837         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1838
1839         /* enable emac */
1840         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1841
1842         /* enable emac for jumbo packets */
1843         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1844                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1845                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1846
1847         /* strip CRC */
1848         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1849
1850         /* disable the NIG in/out to the bmac */
1851         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1852         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1853         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1854
1855         /* enable the NIG in/out to the emac */
1856         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1857         val = 0;
1858         if ((params->feature_config_flags &
1859               FEATURE_CONFIG_PFC_ENABLED) ||
1860             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1861                 val = 1;
1862
1863         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1864         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1865
1866         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1867
1868         vars->mac_type = MAC_TYPE_EMAC;
1869         return 0;
1870 }
1871
1872 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1873                                    struct link_vars *vars)
1874 {
1875         u32 wb_data[2];
1876         struct bnx2x *bp = params->bp;
1877         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1878                 NIG_REG_INGRESS_BMAC0_MEM;
1879
1880         u32 val = 0x14;
1881         if ((!(params->feature_config_flags &
1882               FEATURE_CONFIG_PFC_ENABLED)) &&
1883                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1884                 /* Enable BigMAC to react on received Pause packets */
1885                 val |= (1<<5);
1886         wb_data[0] = val;
1887         wb_data[1] = 0;
1888         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1889
1890         /* tx control */
1891         val = 0xc0;
1892         if (!(params->feature_config_flags &
1893               FEATURE_CONFIG_PFC_ENABLED) &&
1894                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1895                 val |= 0x800000;
1896         wb_data[0] = val;
1897         wb_data[1] = 0;
1898         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1899 }
1900
1901 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1902                                    struct link_vars *vars,
1903                                    u8 is_lb)
1904 {
1905         /*
1906          * Set rx control: Strip CRC and enable BigMAC to relay
1907          * control packets to the system as well
1908          */
1909         u32 wb_data[2];
1910         struct bnx2x *bp = params->bp;
1911         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1912                 NIG_REG_INGRESS_BMAC0_MEM;
1913         u32 val = 0x14;
1914
1915         if ((!(params->feature_config_flags &
1916               FEATURE_CONFIG_PFC_ENABLED)) &&
1917                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1918                 /* Enable BigMAC to react on received Pause packets */
1919                 val |= (1<<5);
1920         wb_data[0] = val;
1921         wb_data[1] = 0;
1922         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1923         udelay(30);
1924
1925         /* Tx control */
1926         val = 0xc0;
1927         if (!(params->feature_config_flags &
1928                                 FEATURE_CONFIG_PFC_ENABLED) &&
1929             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1930                 val |= 0x800000;
1931         wb_data[0] = val;
1932         wb_data[1] = 0;
1933         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1934
1935         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1936                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1937                 /* Enable PFC RX & TX & STATS and set 8 COS  */
1938                 wb_data[0] = 0x0;
1939                 wb_data[0] |= (1<<0);  /* RX */
1940                 wb_data[0] |= (1<<1);  /* TX */
1941                 wb_data[0] |= (1<<2);  /* Force initial Xon */
1942                 wb_data[0] |= (1<<3);  /* 8 cos */
1943                 wb_data[0] |= (1<<5);  /* STATS */
1944                 wb_data[1] = 0;
1945                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1946                             wb_data, 2);
1947                 /* Clear the force Xon */
1948                 wb_data[0] &= ~(1<<2);
1949         } else {
1950                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1951                 /* disable PFC RX & TX & STATS and set 8 COS */
1952                 wb_data[0] = 0x8;
1953                 wb_data[1] = 0;
1954         }
1955
1956         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1957
1958         /*
1959          * Set Time (based unit is 512 bit time) between automatic
1960          * re-sending of PP packets amd enable automatic re-send of
1961          * Per-Priroity Packet as long as pp_gen is asserted and
1962          * pp_disable is low.
1963          */
1964         val = 0x8000;
1965         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1966                 val |= (1<<16); /* enable automatic re-send */
1967
1968         wb_data[0] = val;
1969         wb_data[1] = 0;
1970         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1971                     wb_data, 2);
1972
1973         /* mac control */
1974         val = 0x3; /* Enable RX and TX */
1975         if (is_lb) {
1976                 val |= 0x4; /* Local loopback */
1977                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1978         }
1979         /* When PFC enabled, Pass pause frames towards the NIG. */
1980         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1981                 val |= ((1<<6)|(1<<5));
1982
1983         wb_data[0] = val;
1984         wb_data[1] = 0;
1985         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1986 }
1987
1988
1989 /* PFC BRB internal port configuration params */
1990 struct bnx2x_pfc_brb_threshold_val {
1991         u32 pause_xoff;
1992         u32 pause_xon;
1993         u32 full_xoff;
1994         u32 full_xon;
1995 };
1996
1997 struct bnx2x_pfc_brb_e3b0_val {
1998         u32 full_lb_xoff_th;
1999         u32 full_lb_xon_threshold;
2000         u32 lb_guarantied;
2001         u32 mac_0_class_t_guarantied;
2002         u32 mac_0_class_t_guarantied_hyst;
2003         u32 mac_1_class_t_guarantied;
2004         u32 mac_1_class_t_guarantied_hyst;
2005 };
2006
2007 struct bnx2x_pfc_brb_th_val {
2008         struct bnx2x_pfc_brb_threshold_val pauseable_th;
2009         struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2010 };
2011 static int bnx2x_pfc_brb_get_config_params(
2012                                 struct link_params *params,
2013                                 struct bnx2x_pfc_brb_th_val *config_val)
2014 {
2015         struct bnx2x *bp = params->bp;
2016         DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2017         if (CHIP_IS_E2(bp)) {
2018                 config_val->pauseable_th.pause_xoff =
2019                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2020                 config_val->pauseable_th.pause_xon =
2021                     PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2022                 config_val->pauseable_th.full_xoff =
2023                     PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2024                 config_val->pauseable_th.full_xon =
2025                     PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2026                 /* non pause able*/
2027                 config_val->non_pauseable_th.pause_xoff =
2028                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2029                 config_val->non_pauseable_th.pause_xon =
2030                     PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2031                 config_val->non_pauseable_th.full_xoff =
2032                     PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2033                 config_val->non_pauseable_th.full_xon =
2034                     PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2035         } else if (CHIP_IS_E3A0(bp)) {
2036                 config_val->pauseable_th.pause_xoff =
2037                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2038                 config_val->pauseable_th.pause_xon =
2039                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2040                 config_val->pauseable_th.full_xoff =
2041                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2042                 config_val->pauseable_th.full_xon =
2043                     PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2044                 /* non pause able*/
2045                 config_val->non_pauseable_th.pause_xoff =
2046                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2047                 config_val->non_pauseable_th.pause_xon =
2048                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2049                 config_val->non_pauseable_th.full_xoff =
2050                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2051                 config_val->non_pauseable_th.full_xon =
2052                     PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2053         } else if (CHIP_IS_E3B0(bp)) {
2054                 if (params->phy[INT_PHY].flags &
2055                     FLAGS_4_PORT_MODE) {
2056                         config_val->pauseable_th.pause_xoff =
2057                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2058                         config_val->pauseable_th.pause_xon =
2059                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2060                         config_val->pauseable_th.full_xoff =
2061                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2062                         config_val->pauseable_th.full_xon =
2063                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2064                         /* non pause able*/
2065                         config_val->non_pauseable_th.pause_xoff =
2066                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2067                         config_val->non_pauseable_th.pause_xon =
2068                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2069                         config_val->non_pauseable_th.full_xoff =
2070                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2071                         config_val->non_pauseable_th.full_xon =
2072                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2073             } else {
2074                 config_val->pauseable_th.pause_xoff =
2075                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2076                 config_val->pauseable_th.pause_xon =
2077                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2078                 config_val->pauseable_th.full_xoff =
2079                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2080                 config_val->pauseable_th.full_xon =
2081                         PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2082                 /* non pause able*/
2083                 config_val->non_pauseable_th.pause_xoff =
2084                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2085                 config_val->non_pauseable_th.pause_xon =
2086                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2087                 config_val->non_pauseable_th.full_xoff =
2088                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2089                 config_val->non_pauseable_th.full_xon =
2090                     PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2091             }
2092         } else
2093             return -EINVAL;
2094
2095         return 0;
2096 }
2097
2098
2099 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
2100                                                  struct bnx2x_pfc_brb_e3b0_val
2101                                                  *e3b0_val,
2102                                                  u32 cos0_pauseable,
2103                                                  u32 cos1_pauseable)
2104 {
2105         if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
2106                 e3b0_val->full_lb_xoff_th =
2107                     PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2108                 e3b0_val->full_lb_xon_threshold =
2109                     PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2110                 e3b0_val->lb_guarantied =
2111                     PFC_E3B0_4P_LB_GUART;
2112                 e3b0_val->mac_0_class_t_guarantied =
2113                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2114                 e3b0_val->mac_0_class_t_guarantied_hyst =
2115                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2116                 e3b0_val->mac_1_class_t_guarantied =
2117                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2118                 e3b0_val->mac_1_class_t_guarantied_hyst =
2119                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2120         } else {
2121                 e3b0_val->full_lb_xoff_th =
2122                     PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2123                 e3b0_val->full_lb_xon_threshold =
2124                     PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2125                 e3b0_val->mac_0_class_t_guarantied_hyst =
2126                     PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2127                 e3b0_val->mac_1_class_t_guarantied =
2128                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2129                 e3b0_val->mac_1_class_t_guarantied_hyst =
2130                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2131
2132                 if (cos0_pauseable != cos1_pauseable) {
2133                         /* nonpauseable= Lossy + pauseable = Lossless*/
2134                         e3b0_val->lb_guarantied =
2135                             PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2136                         e3b0_val->mac_0_class_t_guarantied =
2137                             PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2138                 } else if (cos0_pauseable) {
2139                         /* Lossless +Lossless*/
2140                         e3b0_val->lb_guarantied =
2141                             PFC_E3B0_2P_PAUSE_LB_GUART;
2142                         e3b0_val->mac_0_class_t_guarantied =
2143                             PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2144                 } else {
2145                         /* Lossy +Lossy*/
2146                         e3b0_val->lb_guarantied =
2147                             PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2148                         e3b0_val->mac_0_class_t_guarantied =
2149                             PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2150                 }
2151         }
2152 }
2153 static int bnx2x_update_pfc_brb(struct link_params *params,
2154                                 struct link_vars *vars,
2155                                 struct bnx2x_nig_brb_pfc_port_params
2156                                 *pfc_params)
2157 {
2158         struct bnx2x *bp = params->bp;
2159         struct bnx2x_pfc_brb_th_val config_val = { {0} };
2160         struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2161             &config_val.pauseable_th;
2162         struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2163         int set_pfc = params->feature_config_flags &
2164                 FEATURE_CONFIG_PFC_ENABLED;
2165         int bnx2x_status = 0;
2166         u8 port = params->port;
2167
2168         /* default - pause configuration */
2169         reg_th_config = &config_val.pauseable_th;
2170         bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2171         if (0 != bnx2x_status)
2172                 return bnx2x_status;
2173
2174         if (set_pfc && pfc_params)
2175                 /* First COS */
2176                 if (!pfc_params->cos0_pauseable)
2177                         reg_th_config = &config_val.non_pauseable_th;
2178         /*
2179          * The number of free blocks below which the pause signal to class 0
2180          * of MAC #n is asserted. n=0,1
2181          */
2182         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2183                BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2184                reg_th_config->pause_xoff);
2185         /*
2186          * The number of free blocks above which the pause signal to class 0
2187          * of MAC #n is de-asserted. n=0,1
2188          */
2189         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2190                BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2191         /*
2192          * The number of free blocks below which the full signal to class 0
2193          * of MAC #n is asserted. n=0,1
2194          */
2195         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2196                BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2197         /*
2198          * The number of free blocks above which the full signal to class 0
2199          * of MAC #n is de-asserted. n=0,1
2200          */
2201         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2202                BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2203
2204         if (set_pfc && pfc_params) {
2205                 /* Second COS */
2206                 if (pfc_params->cos1_pauseable)
2207                         reg_th_config = &config_val.pauseable_th;
2208                 else
2209                         reg_th_config = &config_val.non_pauseable_th;
2210                 /*
2211                  * The number of free blocks below which the pause signal to
2212                  * class 1 of MAC #n is asserted. n=0,1
2213                 **/
2214                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2215                        BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2216                        reg_th_config->pause_xoff);
2217                 /*
2218                  * The number of free blocks above which the pause signal to
2219                  * class 1 of MAC #n is de-asserted. n=0,1
2220                  */
2221                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2222                        BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2223                        reg_th_config->pause_xon);
2224                 /*
2225                  * The number of free blocks below which the full signal to
2226                  * class 1 of MAC #n is asserted. n=0,1
2227                  */
2228                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2229                        BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2230                        reg_th_config->full_xoff);
2231                 /*
2232                  * The number of free blocks above which the full signal to
2233                  * class 1 of MAC #n is de-asserted. n=0,1
2234                  */
2235                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2236                        BRB1_REG_FULL_1_XON_THRESHOLD_0,
2237                        reg_th_config->full_xon);
2238
2239
2240                 if (CHIP_IS_E3B0(bp)) {
2241                         /*Should be done by init tool */
2242                         /*
2243                         * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2244                         * reset value
2245                         * 944
2246                         */
2247
2248                         /**
2249                          * The hysteresis on the guarantied buffer space for the Lb port
2250                          * before signaling XON.
2251                          **/
2252                         REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
2253
2254                         bnx2x_pfc_brb_get_e3b0_config_params(
2255                             params,
2256                             &e3b0_val,
2257                             pfc_params->cos0_pauseable,
2258                             pfc_params->cos1_pauseable);
2259                         /**
2260                          * The number of free blocks below which the full signal to the
2261                          * LB port is asserted.
2262                         */
2263                         REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2264                                    e3b0_val.full_lb_xoff_th);
2265                         /**
2266                          * The number of free blocks above which the full signal to the
2267                          * LB port is de-asserted.
2268                         */
2269                         REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2270                                    e3b0_val.full_lb_xon_threshold);
2271                         /**
2272                         * The number of blocks guarantied for the MAC #n port. n=0,1
2273                         */
2274
2275                         /*The number of blocks guarantied for the LB port.*/
2276                         REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2277                                e3b0_val.lb_guarantied);
2278
2279                         /**
2280                          * The number of blocks guarantied for the MAC #n port.
2281                         */
2282                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2283                                    2 * e3b0_val.mac_0_class_t_guarantied);
2284                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2285                                    2 * e3b0_val.mac_1_class_t_guarantied);
2286                         /**
2287                          * The number of blocks guarantied for class #t in MAC0. t=0,1
2288                         */
2289                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2290                                e3b0_val.mac_0_class_t_guarantied);
2291                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2292                                e3b0_val.mac_0_class_t_guarantied);
2293                         /**
2294                          * The hysteresis on the guarantied buffer space for class in
2295                          * MAC0.  t=0,1
2296                         */
2297                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2298                                e3b0_val.mac_0_class_t_guarantied_hyst);
2299                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2300                                e3b0_val.mac_0_class_t_guarantied_hyst);
2301
2302                         /**
2303                          * The number of blocks guarantied for class #t in MAC1.t=0,1
2304                         */
2305                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2306                                e3b0_val.mac_1_class_t_guarantied);
2307                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2308                                e3b0_val.mac_1_class_t_guarantied);
2309                         /**
2310                          * The hysteresis on the guarantied buffer space for class #t
2311                         * in MAC1.  t=0,1
2312                         */
2313                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2314                                e3b0_val.mac_1_class_t_guarantied_hyst);
2315                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2316                                e3b0_val.mac_1_class_t_guarantied_hyst);
2317
2318             }
2319
2320         }
2321
2322         return bnx2x_status;
2323 }
2324
2325 /******************************************************************************
2326 * Description:
2327 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2328 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2329 ******************************************************************************/
2330 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2331                                               u8 cos_entry,
2332                                               u32 priority_mask, u8 port)
2333 {
2334         u32 nig_reg_rx_priority_mask_add = 0;
2335
2336         switch (cos_entry) {
2337         case 0:
2338              nig_reg_rx_priority_mask_add = (port) ?
2339                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2340                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2341              break;
2342         case 1:
2343             nig_reg_rx_priority_mask_add = (port) ?
2344                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2345                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2346             break;
2347         case 2:
2348             nig_reg_rx_priority_mask_add = (port) ?
2349                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2350                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2351             break;
2352         case 3:
2353             if (port)
2354                 return -EINVAL;
2355             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2356             break;
2357         case 4:
2358             if (port)
2359                 return -EINVAL;
2360             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2361             break;
2362         case 5:
2363             if (port)
2364                 return -EINVAL;
2365             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2366             break;
2367         }
2368
2369         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2370
2371         return 0;
2372 }
2373 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2374 {
2375         struct bnx2x *bp = params->bp;
2376
2377         REG_WR(bp, params->shmem_base +
2378                offsetof(struct shmem_region,
2379                         port_mb[params->port].link_status), link_status);
2380 }
2381
2382 static void bnx2x_update_pfc_nig(struct link_params *params,
2383                 struct link_vars *vars,
2384                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2385 {
2386         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2387         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2388         u32 pkt_priority_to_cos = 0;
2389         struct bnx2x *bp = params->bp;
2390         u8 port = params->port;
2391
2392         int set_pfc = params->feature_config_flags &
2393                 FEATURE_CONFIG_PFC_ENABLED;
2394         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2395
2396         /*
2397          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2398          * MAC control frames (that are not pause packets)
2399          * will be forwarded to the XCM.
2400          */
2401         xcm_mask = REG_RD(bp,
2402                                 port ? NIG_REG_LLH1_XCM_MASK :
2403                                 NIG_REG_LLH0_XCM_MASK);
2404         /*
2405          * nig params will override non PFC params, since it's possible to
2406          * do transition from PFC to SAFC
2407          */
2408         if (set_pfc) {
2409                 pause_enable = 0;
2410                 llfc_out_en = 0;
2411                 llfc_enable = 0;
2412                 if (CHIP_IS_E3(bp))
2413                         ppp_enable = 0;
2414                 else
2415                 ppp_enable = 1;
2416                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2417                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2418                 xcm0_out_en = 0;
2419                 p0_hwpfc_enable = 1;
2420         } else  {
2421                 if (nig_params) {
2422                         llfc_out_en = nig_params->llfc_out_en;
2423                         llfc_enable = nig_params->llfc_enable;
2424                         pause_enable = nig_params->pause_enable;
2425                 } else  /*defaul non PFC mode - PAUSE */
2426                         pause_enable = 1;
2427
2428                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2429                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2430                 xcm0_out_en = 1;
2431         }
2432
2433         if (CHIP_IS_E3(bp))
2434                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2435                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2436         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2437                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2438         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2439                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2440         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2441                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2442
2443         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2444                NIG_REG_PPP_ENABLE_0, ppp_enable);
2445
2446         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2447                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2448
2449         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2450
2451         /* output enable for RX_XCM # IF */
2452         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2453
2454         /* HW PFC TX enable */
2455         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2456
2457         if (nig_params) {
2458                 u8 i = 0;
2459                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2460
2461                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2462                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2463                 nig_params->rx_cos_priority_mask[i], port);
2464
2465                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2466                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2467                        nig_params->llfc_high_priority_classes);
2468
2469                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2470                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2471                        nig_params->llfc_low_priority_classes);
2472         }
2473         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2474                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2475                pkt_priority_to_cos);
2476 }
2477
2478 int bnx2x_update_pfc(struct link_params *params,
2479                       struct link_vars *vars,
2480                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2481 {
2482         /*
2483          * The PFC and pause are orthogonal to one another, meaning when
2484          * PFC is enabled, the pause are disabled, and when PFC is
2485          * disabled, pause are set according to the pause result.
2486          */
2487         u32 val;
2488         struct bnx2x *bp = params->bp;
2489         int bnx2x_status = 0;
2490         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2491
2492         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2493                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2494         else
2495                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2496
2497         bnx2x_update_mng(params, vars->link_status);
2498
2499         /* update NIG params */
2500         bnx2x_update_pfc_nig(params, vars, pfc_params);
2501
2502         /* update BRB params */
2503         bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2504         if (0 != bnx2x_status)
2505                 return bnx2x_status;
2506
2507         if (!vars->link_up)
2508                 return bnx2x_status;
2509
2510         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2511         if (CHIP_IS_E3(bp))
2512                 bnx2x_update_pfc_xmac(params, vars, 0);
2513         else {
2514                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2515                 if ((val &
2516                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2517                     == 0) {
2518                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2519                         bnx2x_emac_enable(params, vars, 0);
2520                         return bnx2x_status;
2521                 }
2522
2523                 if (CHIP_IS_E2(bp))
2524                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2525                 else
2526                         bnx2x_update_pfc_bmac1(params, vars);
2527
2528                 val = 0;
2529                 if ((params->feature_config_flags &
2530                      FEATURE_CONFIG_PFC_ENABLED) ||
2531                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2532                         val = 1;
2533                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2534         }
2535         return bnx2x_status;
2536 }
2537
2538
2539 static int bnx2x_bmac1_enable(struct link_params *params,
2540                               struct link_vars *vars,
2541                               u8 is_lb)
2542 {
2543         struct bnx2x *bp = params->bp;
2544         u8 port = params->port;
2545         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2546                                NIG_REG_INGRESS_BMAC0_MEM;
2547         u32 wb_data[2];
2548         u32 val;
2549
2550         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2551
2552         /* XGXS control */
2553         wb_data[0] = 0x3c;
2554         wb_data[1] = 0;
2555         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2556                     wb_data, 2);
2557
2558         /* tx MAC SA */
2559         wb_data[0] = ((params->mac_addr[2] << 24) |
2560                        (params->mac_addr[3] << 16) |
2561                        (params->mac_addr[4] << 8) |
2562                         params->mac_addr[5]);
2563         wb_data[1] = ((params->mac_addr[0] << 8) |
2564                         params->mac_addr[1]);
2565         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2566
2567         /* mac control */
2568         val = 0x3;
2569         if (is_lb) {
2570                 val |= 0x4;
2571                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2572         }
2573         wb_data[0] = val;
2574         wb_data[1] = 0;
2575         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2576
2577         /* set rx mtu */
2578         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2579         wb_data[1] = 0;
2580         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2581
2582         bnx2x_update_pfc_bmac1(params, vars);
2583
2584         /* set tx mtu */
2585         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2586         wb_data[1] = 0;
2587         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2588
2589         /* set cnt max size */
2590         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2591         wb_data[1] = 0;
2592         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2593
2594         /* configure safc */
2595         wb_data[0] = 0x1000200;
2596         wb_data[1] = 0;
2597         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2598                     wb_data, 2);
2599
2600         return 0;
2601 }
2602
2603 static int bnx2x_bmac2_enable(struct link_params *params,
2604                               struct link_vars *vars,
2605                               u8 is_lb)
2606 {
2607         struct bnx2x *bp = params->bp;
2608         u8 port = params->port;
2609         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2610                                NIG_REG_INGRESS_BMAC0_MEM;
2611         u32 wb_data[2];
2612
2613         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2614
2615         wb_data[0] = 0;
2616         wb_data[1] = 0;
2617         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2618         udelay(30);
2619
2620         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2621         wb_data[0] = 0x3c;
2622         wb_data[1] = 0;
2623         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2624                     wb_data, 2);
2625
2626         udelay(30);
2627
2628         /* tx MAC SA */
2629         wb_data[0] = ((params->mac_addr[2] << 24) |
2630                        (params->mac_addr[3] << 16) |
2631                        (params->mac_addr[4] << 8) |
2632                         params->mac_addr[5]);
2633         wb_data[1] = ((params->mac_addr[0] << 8) |
2634                         params->mac_addr[1]);
2635         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2636                     wb_data, 2);
2637
2638         udelay(30);
2639
2640         /* Configure SAFC */
2641         wb_data[0] = 0x1000200;
2642         wb_data[1] = 0;
2643         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2644                     wb_data, 2);
2645         udelay(30);
2646
2647         /* set rx mtu */
2648         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2649         wb_data[1] = 0;
2650         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2651         udelay(30);
2652
2653         /* set tx mtu */
2654         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2655         wb_data[1] = 0;
2656         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2657         udelay(30);
2658         /* set cnt max size */
2659         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2660         wb_data[1] = 0;
2661         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2662         udelay(30);
2663         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2664
2665         return 0;
2666 }
2667
2668 static int bnx2x_bmac_enable(struct link_params *params,
2669                              struct link_vars *vars,
2670                              u8 is_lb)
2671 {
2672         int rc = 0;
2673         u8 port = params->port;
2674         struct bnx2x *bp = params->bp;
2675         u32 val;
2676         /* reset and unreset the BigMac */
2677         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2678                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2679         msleep(1);
2680
2681         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2682                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2683
2684         /* enable access for bmac registers */
2685         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2686
2687         /* Enable BMAC according to BMAC type*/
2688         if (CHIP_IS_E2(bp))
2689                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2690         else
2691                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2692         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2693         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2694         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2695         val = 0;
2696         if ((params->feature_config_flags &
2697               FEATURE_CONFIG_PFC_ENABLED) ||
2698             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2699                 val = 1;
2700         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2701         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2702         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2703         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2704         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2705         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2706
2707         vars->mac_type = MAC_TYPE_BMAC;
2708         return rc;
2709 }
2710
2711 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2712 {
2713         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2714                         NIG_REG_INGRESS_BMAC0_MEM;
2715         u32 wb_data[2];
2716         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2717
2718         /* Only if the bmac is out of reset */
2719         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2720                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2721             nig_bmac_enable) {
2722
2723                 if (CHIP_IS_E2(bp)) {
2724                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2725                         REG_RD_DMAE(bp, bmac_addr +
2726                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2727                                     wb_data, 2);
2728                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2729                         REG_WR_DMAE(bp, bmac_addr +
2730                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2731                                     wb_data, 2);
2732                 } else {
2733                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2734                         REG_RD_DMAE(bp, bmac_addr +
2735                                         BIGMAC_REGISTER_BMAC_CONTROL,
2736                                         wb_data, 2);
2737                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2738                         REG_WR_DMAE(bp, bmac_addr +
2739                                         BIGMAC_REGISTER_BMAC_CONTROL,
2740                                         wb_data, 2);
2741                 }
2742                 msleep(1);
2743         }
2744 }
2745
2746 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2747                             u32 line_speed)
2748 {
2749         struct bnx2x *bp = params->bp;
2750         u8 port = params->port;
2751         u32 init_crd, crd;
2752         u32 count = 1000;
2753
2754         /* disable port */
2755         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2756
2757         /* wait for init credit */
2758         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2759         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2760         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2761
2762         while ((init_crd != crd) && count) {
2763                 msleep(5);
2764
2765                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2766                 count--;
2767         }
2768         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2769         if (init_crd != crd) {
2770                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2771                           init_crd, crd);
2772                 return -EINVAL;
2773         }
2774
2775         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2776             line_speed == SPEED_10 ||
2777             line_speed == SPEED_100 ||
2778             line_speed == SPEED_1000 ||
2779             line_speed == SPEED_2500) {
2780                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2781                 /* update threshold */
2782                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2783                 /* update init credit */
2784                 init_crd = 778;         /* (800-18-4) */
2785
2786         } else {
2787                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2788                               ETH_OVREHEAD)/16;
2789                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2790                 /* update threshold */
2791                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2792                 /* update init credit */
2793                 switch (line_speed) {
2794                 case SPEED_10000:
2795                         init_crd = thresh + 553 - 22;
2796                         break;
2797                 default:
2798                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2799                                   line_speed);
2800                         return -EINVAL;
2801                 }
2802         }
2803         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2804         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2805                  line_speed, init_crd);
2806
2807         /* probe the credit changes */
2808         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2809         msleep(5);
2810         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2811
2812         /* enable port */
2813         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2814         return 0;
2815 }
2816
2817 /**
2818  * bnx2x_get_emac_base - retrive emac base address
2819  *
2820  * @bp:                 driver handle
2821  * @mdc_mdio_access:    access type
2822  * @port:               port id
2823  *
2824  * This function selects the MDC/MDIO access (through emac0 or
2825  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2826  * phy has a default access mode, which could also be overridden
2827  * by nvram configuration. This parameter, whether this is the
2828  * default phy configuration, or the nvram overrun
2829  * configuration, is passed here as mdc_mdio_access and selects
2830  * the emac_base for the CL45 read/writes operations
2831  */
2832 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2833                                u32 mdc_mdio_access, u8 port)
2834 {
2835         u32 emac_base = 0;
2836         switch (mdc_mdio_access) {
2837         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2838                 break;
2839         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2840                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2841                         emac_base = GRCBASE_EMAC1;
2842                 else
2843                         emac_base = GRCBASE_EMAC0;
2844                 break;
2845         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2846                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2847                         emac_base = GRCBASE_EMAC0;
2848                 else
2849                         emac_base = GRCBASE_EMAC1;
2850                 break;
2851         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2852                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2853                 break;
2854         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2855                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2856                 break;
2857         default:
2858                 break;
2859         }
2860         return emac_base;
2861
2862 }
2863
2864 /******************************************************************/
2865 /*                      CL22 access functions                     */
2866 /******************************************************************/
2867 static int bnx2x_cl22_write(struct bnx2x *bp,
2868                                        struct bnx2x_phy *phy,
2869                                        u16 reg, u16 val)
2870 {
2871         u32 tmp, mode;
2872         u8 i;
2873         int rc = 0;
2874         /* Switch to CL22 */
2875         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2876         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2877                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2878
2879         /* address */
2880         tmp = ((phy->addr << 21) | (reg << 16) | val |
2881                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2882                EMAC_MDIO_COMM_START_BUSY);
2883         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2884
2885         for (i = 0; i < 50; i++) {
2886                 udelay(10);
2887
2888                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2889                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2890                         udelay(5);
2891                         break;
2892                 }
2893         }
2894         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2895                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2896                 rc = -EFAULT;
2897         }
2898         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2899         return rc;
2900 }
2901
2902 static int bnx2x_cl22_read(struct bnx2x *bp,
2903                                       struct bnx2x_phy *phy,
2904                                       u16 reg, u16 *ret_val)
2905 {
2906         u32 val, mode;
2907         u16 i;
2908         int rc = 0;
2909
2910         /* Switch to CL22 */
2911         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2912         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2913                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2914
2915         /* address */
2916         val = ((phy->addr << 21) | (reg << 16) |
2917                EMAC_MDIO_COMM_COMMAND_READ_22 |
2918                EMAC_MDIO_COMM_START_BUSY);
2919         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2920
2921         for (i = 0; i < 50; i++) {
2922                 udelay(10);
2923
2924                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2925                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2926                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2927                         udelay(5);
2928                         break;
2929                 }
2930         }
2931         if (val & EMAC_MDIO_COMM_START_BUSY) {
2932                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2933
2934                 *ret_val = 0;
2935                 rc = -EFAULT;
2936         }
2937         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2938         return rc;
2939 }
2940
2941 /******************************************************************/
2942 /*                      CL45 access functions                     */
2943 /******************************************************************/
2944 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2945                            u8 devad, u16 reg, u16 *ret_val)
2946 {
2947         u32 val;
2948         u16 i;
2949         int rc = 0;
2950         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2951                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2952                               EMAC_MDIO_STATUS_10MB);
2953         /* address */
2954         val = ((phy->addr << 21) | (devad << 16) | reg |
2955                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2956                EMAC_MDIO_COMM_START_BUSY);
2957         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2958
2959         for (i = 0; i < 50; i++) {
2960                 udelay(10);
2961
2962                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2963                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2964                         udelay(5);
2965                         break;
2966                 }
2967         }
2968         if (val & EMAC_MDIO_COMM_START_BUSY) {
2969                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2970                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2971                 *ret_val = 0;
2972                 rc = -EFAULT;
2973         } else {
2974                 /* data */
2975                 val = ((phy->addr << 21) | (devad << 16) |
2976                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2977                        EMAC_MDIO_COMM_START_BUSY);
2978                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2979
2980                 for (i = 0; i < 50; i++) {
2981                         udelay(10);
2982
2983                         val = REG_RD(bp, phy->mdio_ctrl +
2984                                      EMAC_REG_EMAC_MDIO_COMM);
2985                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2986                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2987                                 break;
2988                         }
2989                 }
2990                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2991                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2992                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2993                         *ret_val = 0;
2994                         rc = -EFAULT;
2995                 }
2996         }
2997         /* Work around for E3 A0 */
2998         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2999                 phy->flags ^= FLAGS_DUMMY_READ;
3000                 if (phy->flags & FLAGS_DUMMY_READ) {
3001                         u16 temp_val;
3002                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3003                 }
3004         }
3005
3006         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3007                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3008                                EMAC_MDIO_STATUS_10MB);
3009         return rc;
3010 }
3011
3012 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3013                             u8 devad, u16 reg, u16 val)
3014 {
3015         u32 tmp;
3016         u8 i;
3017         int rc = 0;
3018         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3019                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3020                               EMAC_MDIO_STATUS_10MB);
3021
3022         /* address */
3023
3024         tmp = ((phy->addr << 21) | (devad << 16) | reg |
3025                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3026                EMAC_MDIO_COMM_START_BUSY);
3027         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3028
3029         for (i = 0; i < 50; i++) {
3030                 udelay(10);
3031
3032                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3033                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3034                         udelay(5);
3035                         break;
3036                 }
3037         }
3038         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3039                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3040                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3041                 rc = -EFAULT;
3042
3043         } else {
3044                 /* data */
3045                 tmp = ((phy->addr << 21) | (devad << 16) | val |
3046                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3047                        EMAC_MDIO_COMM_START_BUSY);
3048                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3049
3050                 for (i = 0; i < 50; i++) {
3051                         udelay(10);
3052
3053                         tmp = REG_RD(bp, phy->mdio_ctrl +
3054                                      EMAC_REG_EMAC_MDIO_COMM);
3055                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3056                                 udelay(5);
3057                                 break;
3058                         }
3059                 }
3060                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3061                         DP(NETIF_MSG_LINK, "write phy register failed\n");
3062                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3063                         rc = -EFAULT;
3064                 }
3065         }
3066         /* Work around for E3 A0 */
3067         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3068                 phy->flags ^= FLAGS_DUMMY_READ;
3069                 if (phy->flags & FLAGS_DUMMY_READ) {
3070                         u16 temp_val;
3071                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3072                 }
3073         }
3074         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
3075                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3076                                EMAC_MDIO_STATUS_10MB);
3077         return rc;
3078 }
3079
3080
3081 /******************************************************************/
3082 /*                      BSC access functions from E3              */
3083 /******************************************************************/
3084 static void bnx2x_bsc_module_sel(struct link_params *params)
3085 {
3086         int idx;
3087         u32 board_cfg, sfp_ctrl;
3088         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3089         struct bnx2x *bp = params->bp;
3090         u8 port = params->port;
3091         /* Read I2C output PINs */
3092         board_cfg = REG_RD(bp, params->shmem_base +
3093                            offsetof(struct shmem_region,
3094                                     dev_info.shared_hw_config.board));
3095         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3096         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3097                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3098
3099         /* Read I2C output value */
3100         sfp_ctrl = REG_RD(bp, params->shmem_base +
3101                           offsetof(struct shmem_region,
3102                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3103         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3104         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3105         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3106         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3107                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3108 }
3109
3110 static int bnx2x_bsc_read(struct link_params *params,
3111                           struct bnx2x_phy *phy,
3112                           u8 sl_devid,
3113                           u16 sl_addr,
3114                           u8 lc_addr,
3115                           u8 xfer_cnt,
3116                           u32 *data_array)
3117 {
3118         u32 val, i;
3119         int rc = 0;
3120         struct bnx2x *bp = params->bp;
3121
3122         if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3123                 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3124                 return -EINVAL;
3125         }
3126
3127         if (xfer_cnt > 16) {
3128                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3129                                         xfer_cnt);
3130                 return -EINVAL;
3131         }
3132         bnx2x_bsc_module_sel(params);
3133
3134         xfer_cnt = 16 - lc_addr;
3135
3136         /* enable the engine */
3137         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3138         val |= MCPR_IMC_COMMAND_ENABLE;
3139         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3140
3141         /* program slave device ID */
3142         val = (sl_devid << 16) | sl_addr;
3143         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3144
3145         /* start xfer with 0 byte to update the address pointer ???*/
3146         val = (MCPR_IMC_COMMAND_ENABLE) |
3147               (MCPR_IMC_COMMAND_WRITE_OP <<
3148                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3149                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3150         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3151
3152         /* poll for completion */
3153         i = 0;
3154         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3155         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3156                 udelay(10);
3157                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3158                 if (i++ > 1000) {
3159                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3160                                                                 i);
3161                         rc = -EFAULT;
3162                         break;
3163                 }
3164         }
3165         if (rc == -EFAULT)
3166                 return rc;
3167
3168         /* start xfer with read op */
3169         val = (MCPR_IMC_COMMAND_ENABLE) |
3170                 (MCPR_IMC_COMMAND_READ_OP <<
3171                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3172                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3173                   (xfer_cnt);
3174         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3175
3176         /* poll for completion */
3177         i = 0;
3178         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3179         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3180                 udelay(10);
3181                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3182                 if (i++ > 1000) {
3183                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3184                         rc = -EFAULT;
3185                         break;
3186                 }
3187         }
3188         if (rc == -EFAULT)
3189                 return rc;
3190
3191         for (i = (lc_addr >> 2); i < 4; i++) {
3192                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3193 #ifdef __BIG_ENDIAN
3194                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3195                                 ((data_array[i] & 0x0000ff00) << 8) |
3196                                 ((data_array[i] & 0x00ff0000) >> 8) |
3197                                 ((data_array[i] & 0xff000000) >> 24);
3198 #endif
3199         }
3200         return rc;
3201 }
3202
3203 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3204                                      u8 devad, u16 reg, u16 or_val)
3205 {
3206         u16 val;
3207         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3208         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3209 }
3210
3211 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3212                    u8 devad, u16 reg, u16 *ret_val)
3213 {
3214         u8 phy_index;
3215         /*
3216          * Probe for the phy according to the given phy_addr, and execute
3217          * the read request on it
3218          */
3219         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3220                 if (params->phy[phy_index].addr == phy_addr) {
3221                         return bnx2x_cl45_read(params->bp,
3222                                                &params->phy[phy_index], devad,
3223                                                reg, ret_val);
3224                 }
3225         }
3226         return -EINVAL;
3227 }
3228
3229 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3230                     u8 devad, u16 reg, u16 val)
3231 {
3232         u8 phy_index;
3233         /*
3234          * Probe for the phy according to the given phy_addr, and execute
3235          * the write request on it
3236          */
3237         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3238                 if (params->phy[phy_index].addr == phy_addr) {
3239                         return bnx2x_cl45_write(params->bp,
3240                                                 &params->phy[phy_index], devad,
3241                                                 reg, val);
3242                 }
3243         }
3244         return -EINVAL;
3245 }
3246 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3247                                   struct link_params *params)
3248 {
3249         u8 lane = 0;
3250         struct bnx2x *bp = params->bp;
3251         u32 path_swap, path_swap_ovr;
3252         u8 path, port;
3253
3254         path = BP_PATH(bp);
3255         port = params->port;
3256
3257         if (bnx2x_is_4_port_mode(bp)) {
3258                 u32 port_swap, port_swap_ovr;
3259
3260                 /*figure out path swap value */
3261                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3262                 if (path_swap_ovr & 0x1)
3263                         path_swap = (path_swap_ovr & 0x2);
3264                 else
3265                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3266
3267                 if (path_swap)
3268                         path = path ^ 1;
3269
3270                 /*figure out port swap value */
3271                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3272                 if (port_swap_ovr & 0x1)
3273                         port_swap = (port_swap_ovr & 0x2);
3274                 else
3275                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3276
3277                 if (port_swap)
3278                         port = port ^ 1;
3279
3280                 lane = (port<<1) + path;
3281         } else { /* two port mode - no port swap */
3282
3283                 /*figure out path swap value */
3284                 path_swap_ovr =
3285                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3286                 if (path_swap_ovr & 0x1) {
3287                         path_swap = (path_swap_ovr & 0x2);
3288                 } else {
3289                         path_swap =
3290                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3291                 }
3292                 if (path_swap)
3293                         path = path ^ 1;
3294
3295                 lane = path << 1 ;
3296         }
3297         return lane;
3298 }
3299
3300 static void bnx2x_set_aer_mmd(struct link_params *params,
3301                               struct bnx2x_phy *phy)
3302 {
3303         u32 ser_lane;
3304         u16 offset, aer_val;
3305         struct bnx2x *bp = params->bp;
3306         ser_lane = ((params->lane_config &
3307                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3308                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3309
3310         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3311                 (phy->addr + ser_lane) : 0;
3312
3313         if (USES_WARPCORE(bp)) {
3314                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3315                 /*
3316                  * In Dual-lane mode, two lanes are joined together,
3317                  * so in order to configure them, the AER broadcast method is
3318                  * used here.
3319                  * 0x200 is the broadcast address for lanes 0,1
3320                  * 0x201 is the broadcast address for lanes 2,3
3321                  */
3322                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3323                         aer_val = (aer_val >> 1) | 0x200;
3324         } else if (CHIP_IS_E2(bp))
3325                 aer_val = 0x3800 + offset - 1;
3326         else
3327                 aer_val = 0x3800 + offset;
3328         DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3329         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3330                           MDIO_AER_BLOCK_AER_REG, aer_val);
3331
3332 }
3333
3334 /******************************************************************/
3335 /*                      Internal phy section                      */
3336 /******************************************************************/
3337
3338 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3339 {
3340         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3341
3342         /* Set Clause 22 */
3343         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3344         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3345         udelay(500);
3346         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3347         udelay(500);
3348          /* Set Clause 45 */
3349         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3350 }
3351
3352 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3353 {
3354         u32 val;
3355
3356         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3357
3358         val = SERDES_RESET_BITS << (port*16);
3359
3360         /* reset and unreset the SerDes/XGXS */
3361         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3362         udelay(500);
3363         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3364
3365         bnx2x_set_serdes_access(bp, port);
3366
3367         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3368                DEFAULT_PHY_DEV_ADDR);
3369 }
3370
3371 static void bnx2x_xgxs_deassert(struct link_params *params)
3372 {
3373         struct bnx2x *bp = params->bp;
3374         u8 port;
3375         u32 val;
3376         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3377         port = params->port;
3378
3379         val = XGXS_RESET_BITS << (port*16);
3380
3381         /* reset and unreset the SerDes/XGXS */
3382         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3383         udelay(500);
3384         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3385
3386         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3387         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3388                params->phy[INT_PHY].def_md_devad);
3389 }
3390
3391 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3392                                      struct link_params *params, u16 *ieee_fc)
3393 {
3394         struct bnx2x *bp = params->bp;
3395         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3396         /**
3397          * resolve pause mode and advertisement Please refer to Table
3398          * 28B-3 of the 802.3ab-1999 spec
3399          */
3400
3401         switch (phy->req_flow_ctrl) {
3402         case BNX2X_FLOW_CTRL_AUTO:
3403                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3404                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3405                 else
3406                         *ieee_fc |=
3407                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3408                 break;
3409
3410         case BNX2X_FLOW_CTRL_TX:
3411                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3412                 break;
3413
3414         case BNX2X_FLOW_CTRL_RX:
3415         case BNX2X_FLOW_CTRL_BOTH:
3416                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3417                 break;
3418
3419         case BNX2X_FLOW_CTRL_NONE:
3420         default:
3421                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3422                 break;
3423         }
3424         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3425 }
3426
3427 static void set_phy_vars(struct link_params *params,
3428                          struct link_vars *vars)
3429 {
3430         struct bnx2x *bp = params->bp;
3431         u8 actual_phy_idx, phy_index, link_cfg_idx;
3432         u8 phy_config_swapped = params->multi_phy_config &
3433                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3434         for (phy_index = INT_PHY; phy_index < params->num_phys;
3435               phy_index++) {
3436                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3437                 actual_phy_idx = phy_index;
3438                 if (phy_config_swapped) {
3439                         if (phy_index == EXT_PHY1)
3440                                 actual_phy_idx = EXT_PHY2;
3441                         else if (phy_index == EXT_PHY2)
3442                                 actual_phy_idx = EXT_PHY1;
3443                 }
3444                 params->phy[actual_phy_idx].req_flow_ctrl =
3445                         params->req_flow_ctrl[link_cfg_idx];
3446
3447                 params->phy[actual_phy_idx].req_line_speed =
3448                         params->req_line_speed[link_cfg_idx];
3449
3450                 params->phy[actual_phy_idx].speed_cap_mask =
3451                         params->speed_cap_mask[link_cfg_idx];
3452
3453                 params->phy[actual_phy_idx].req_duplex =
3454                         params->req_duplex[link_cfg_idx];
3455
3456                 if (params->req_line_speed[link_cfg_idx] ==
3457                     SPEED_AUTO_NEG)
3458                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3459
3460                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3461                            " speed_cap_mask %x\n",
3462                            params->phy[actual_phy_idx].req_flow_ctrl,
3463                            params->phy[actual_phy_idx].req_line_speed,
3464                            params->phy[actual_phy_idx].speed_cap_mask);
3465         }
3466 }
3467
3468 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3469                                     struct bnx2x_phy *phy,
3470                                     struct link_vars *vars)
3471 {
3472         u16 val;
3473         struct bnx2x *bp = params->bp;
3474         /* read modify write pause advertizing */
3475         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3476
3477         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3478
3479         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3480         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3481         if ((vars->ieee_fc &
3482             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3483             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3484                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3485         }
3486         if ((vars->ieee_fc &
3487             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3488             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3489                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3490         }
3491         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3492         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3493 }
3494
3495 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3496 {                                               /*  LD      LP   */
3497         switch (pause_result) {                 /* ASYM P ASYM P */
3498         case 0xb:                               /*   1  0   1  1 */
3499                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3500                 break;
3501
3502         case 0xe:                               /*   1  1   1  0 */
3503                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3504                 break;
3505
3506         case 0x5:                               /*   0  1   0  1 */
3507         case 0x7:                               /*   0  1   1  1 */
3508         case 0xd:                               /*   1  1   0  1 */
3509         case 0xf:                               /*   1  1   1  1 */
3510                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3511                 break;
3512
3513         default:
3514                 break;
3515         }
3516         if (pause_result & (1<<0))
3517                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3518         if (pause_result & (1<<1))
3519                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3520 }
3521
3522 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3523                                    struct link_params *params,
3524                                    struct link_vars *vars)
3525 {
3526         struct bnx2x *bp = params->bp;
3527         u16 ld_pause;           /* local */
3528         u16 lp_pause;           /* link partner */
3529         u16 pause_result;
3530         u8 ret = 0;
3531         /* read twice */
3532
3533         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3534
3535         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3536                 vars->flow_ctrl = phy->req_flow_ctrl;
3537         else if (phy->req_line_speed != SPEED_AUTO_NEG)
3538                 vars->flow_ctrl = params->req_fc_auto_adv;
3539         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3540                 ret = 1;
3541                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3542                         bnx2x_cl22_read(bp, phy,
3543                                         0x4, &ld_pause);
3544                         bnx2x_cl22_read(bp, phy,
3545                                         0x5, &lp_pause);
3546                 } else {
3547                         bnx2x_cl45_read(bp, phy,
3548                                         MDIO_AN_DEVAD,
3549                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3550                         bnx2x_cl45_read(bp, phy,
3551                                         MDIO_AN_DEVAD,
3552                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3553                 }
3554                 pause_result = (ld_pause &
3555                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3556                 pause_result |= (lp_pause &
3557                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3558                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3559                    pause_result);
3560                 bnx2x_pause_resolve(vars, pause_result);
3561         }
3562         return ret;
3563 }
3564 /******************************************************************/
3565 /*                      Warpcore section                          */
3566 /******************************************************************/
3567 /* The init_internal_warpcore should mirror the xgxs,
3568  * i.e. reset the lane (if needed), set aer for the
3569  * init configuration, and set/clear SGMII flag. Internal
3570  * phy init is done purely in phy_init stage.
3571  */
3572 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3573                                         struct link_params *params,
3574                                         struct link_vars *vars) {
3575         u16 val16 = 0, lane, bam37 = 0;
3576         struct bnx2x *bp = params->bp;
3577         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3578         /* Check adding advertisement for 1G KX */
3579         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3580              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3581             (vars->line_speed == SPEED_1000)) {
3582                 u16 sd_digital;
3583                 val16 |= (1<<5);
3584
3585                 /* Enable CL37 1G Parallel Detect */
3586                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3587                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3588                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3589                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3590                                  (sd_digital | 0x1));
3591
3592                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3593         }
3594         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3595              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3596             (vars->line_speed ==  SPEED_10000)) {
3597                 /* Check adding advertisement for 10G KR */
3598                 val16 |= (1<<7);
3599                 /* Enable 10G Parallel Detect */
3600                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3601                                 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3602
3603                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3604         }
3605
3606         /* Set Transmit PMD settings */
3607         lane = bnx2x_get_warpcore_lane(phy, params);
3608         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3609                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3610                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3611                       (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3612                       (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3613         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3614                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3615                          0x03f0);
3616         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3617                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3618                          0x03f0);
3619         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3620                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3621                          0x383f);
3622
3623         /* Advertised speeds */
3624         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3625                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3626
3627         /* Advertised and set FEC (Forward Error Correction) */
3628         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3629                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3630                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3631                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3632
3633         /* Enable CL37 BAM */
3634         if (REG_RD(bp, params->shmem_base +
3635                    offsetof(struct shmem_region, dev_info.
3636                             port_hw_config[params->port].default_cfg)) &
3637             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3638                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3639                                 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3640                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3641                         MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3642                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3643         }
3644
3645         /* Advertise pause */
3646         bnx2x_ext_phy_set_pause(params, phy, vars);
3647
3648         /* Enable Autoneg */
3649         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3650                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3651
3652         /* Over 1G - AN local device user page 1 */
3653         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3654                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3655
3656         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3657                         MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3658
3659         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3660                          MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3661 }
3662
3663 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3664                                       struct link_params *params,
3665                                       struct link_vars *vars)
3666 {
3667         struct bnx2x *bp = params->bp;
3668         u16 val;
3669
3670         /* Disable Autoneg */
3671         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3672                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3673
3674         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3675                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3676
3677         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3678                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3679
3680         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3681                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3682
3683         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3684                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3685
3686         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3687                         MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3688
3689         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3690                          MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3691
3692         /* Disable CL36 PCS Tx */
3693         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3694                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3695
3696         /* Double Wide Single Data Rate @ pll rate */
3697         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3698                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3699
3700         /* Leave cl72 training enable, needed for KR */
3701         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3702                 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3703                 0x2);
3704
3705         /* Leave CL72 enabled */
3706         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3707                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3708                          &val);
3709         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3710                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3711                          val | 0x3800);
3712
3713         /* Set speed via PMA/PMD register */
3714         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3715                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3716
3717         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3718                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3719
3720         /*Enable encoded forced speed */
3721         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3722                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3723
3724         /* Turn TX scramble payload only the 64/66 scrambler */
3725         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3726                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3727
3728         /* Turn RX scramble payload only the 64/66 scrambler */
3729         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3730                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3731
3732         /* set and clear loopback to cause a reset to 64/66 decoder */
3733         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3734                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3735         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3736                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3737
3738 }
3739
3740 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3741                                        struct link_params *params,
3742                                        u8 is_xfi)
3743 {
3744         struct bnx2x *bp = params->bp;
3745         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3746         /* Hold rxSeqStart */
3747         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3748                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3749         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3750                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3751
3752         /* Hold tx_fifo_reset */
3753         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3754                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3755         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3756                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3757
3758         /* Disable CL73 AN */
3759         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3760
3761         /* Disable 100FX Enable and Auto-Detect */
3762         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3763                         MDIO_WC_REG_FX100_CTRL1, &val);
3764         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3765                          MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3766
3767         /* Disable 100FX Idle detect */
3768         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3769                         MDIO_WC_REG_FX100_CTRL3, &val);
3770         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3771                          MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3772
3773         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3774         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3775                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3776         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3777                          MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3778
3779         /* Turn off auto-detect & fiber mode */
3780         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3781                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3782         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3783                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3784                          (val & 0xFFEE));
3785
3786         /* Set filter_force_link, disable_false_link and parallel_detect */
3787         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3788                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3789         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3790                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3791                          ((val | 0x0006) & 0xFFFE));
3792
3793         /* Set XFI / SFI */
3794         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3795                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3796
3797         misc1_val &= ~(0x1f);
3798
3799         if (is_xfi) {
3800                 misc1_val |= 0x5;
3801                 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3802                            (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3803                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3804                 tx_driver_val =
3805                       ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3806                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3807                        (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3808
3809         } else {
3810                 misc1_val |= 0x9;
3811                 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3812                            (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3813                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3814                 tx_driver_val =
3815                       ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3816                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3817                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3818         }
3819         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3820                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3821
3822         /* Set Transmit PMD settings */
3823         lane = bnx2x_get_warpcore_lane(phy, params);
3824         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3825                          MDIO_WC_REG_TX_FIR_TAP,
3826                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3827         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3828                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3829                          tx_driver_val);
3830
3831         /* Enable fiber mode, enable and invert sig_det */
3832         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3833                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3834         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3835                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3836
3837         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3838         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3839                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3840         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3841                          MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3842
3843         /* 10G XFI Full Duplex */
3844         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3845                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3846
3847         /* Release tx_fifo_reset */
3848         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3849                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3850         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3851                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3852
3853         /* Release rxSeqStart */
3854         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3855                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3856         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3857                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3858 }
3859
3860 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3861                                        struct bnx2x_phy *phy)
3862 {
3863         DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3864 }
3865
3866 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3867                                          struct bnx2x_phy *phy,
3868                                          u16 lane)
3869 {
3870         /* Rx0 anaRxControl1G */
3871         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3872                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3873
3874         /* Rx2 anaRxControl1G */
3875         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3876                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3877
3878         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3879                          MDIO_WC_REG_RX66_SCW0, 0xE070);
3880
3881         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3882                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3883
3884         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3885                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3886
3887         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3888                          MDIO_WC_REG_RX66_SCW3, 0x8090);
3889
3890         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3891                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3892
3893         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3894                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3895
3896         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3897                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3898
3899         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3900                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3901
3902         /* Serdes Digital Misc1 */
3903         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3904                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3905
3906         /* Serdes Digital4 Misc3 */
3907         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3908                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3909
3910         /* Set Transmit PMD settings */
3911         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3912                          MDIO_WC_REG_TX_FIR_TAP,
3913                         ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3914                          (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3915                          (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
3916                          MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3917         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3918                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3919                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3920                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3921                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3922 }
3923
3924 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
3925                                            struct link_params *params,
3926                                            u8 fiber_mode)
3927 {
3928         struct bnx2x *bp = params->bp;
3929         u16 val16, digctrl_kx1, digctrl_kx2;
3930         u8 lane;
3931
3932         lane = bnx2x_get_warpcore_lane(phy, params);
3933
3934         /* Clear XFI clock comp in non-10G single lane mode. */
3935         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3936                         MDIO_WC_REG_RX66_CONTROL, &val16);
3937         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3938                          MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
3939
3940         if (phy->req_line_speed == SPEED_AUTO_NEG) {
3941                 /* SGMII Autoneg */
3942                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3943                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3944                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3945                                  MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3946                                  val16 | 0x1000);
3947                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
3948         } else {
3949                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3950                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3951                 val16 &= 0xcfbf;
3952                 switch (phy->req_line_speed) {
3953                 case SPEED_10:
3954                         break;
3955                 case SPEED_100:
3956                         val16 |= 0x2000;
3957                         break;
3958                 case SPEED_1000:
3959                         val16 |= 0x0040;
3960                         break;
3961                 default:
3962                         DP(NETIF_MSG_LINK, "Speed not supported: 0x%x"
3963                                            "\n", phy->req_line_speed);
3964                         return;
3965                 }
3966
3967                 if (phy->req_duplex == DUPLEX_FULL)
3968                         val16 |= 0x0100;
3969
3970                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3971                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3972
3973                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
3974                                phy->req_line_speed);
3975                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3976                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3977                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
3978         }
3979
3980         /* SGMII Slave mode and disable signal detect */
3981         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3982                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3983         if (fiber_mode)
3984                 digctrl_kx1 = 1;
3985         else
3986                 digctrl_kx1 &= 0xff4a;
3987
3988         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3989                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3990                         digctrl_kx1);
3991
3992         /* Turn off parallel detect */
3993         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3994                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3995         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3996                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3997                         (digctrl_kx2 & ~(1<<2)));
3998
3999         /* Re-enable parallel detect */
4000         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4001                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4002                         (digctrl_kx2 | (1<<2)));
4003
4004         /* Enable autodet */
4005         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4006                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4007                         (digctrl_kx1 | 0x10));
4008 }
4009
4010 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4011                                       struct bnx2x_phy *phy,
4012                                       u8 reset)
4013 {
4014         u16 val;
4015         /* Take lane out of reset after configuration is finished */
4016         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4017                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4018         if (reset)
4019                 val |= 0xC000;
4020         else
4021                 val &= 0x3FFF;
4022         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4023                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4024         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4025                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4026 }
4027
4028
4029         /* Clear SFI/XFI link settings registers */
4030 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4031                                       struct link_params *params,
4032                                       u16 lane)
4033 {
4034         struct bnx2x *bp = params->bp;
4035         u16 val16;
4036
4037         /* Set XFI clock comp as default. */
4038         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4039                         MDIO_WC_REG_RX66_CONTROL, &val16);
4040         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4041                          MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4042
4043         bnx2x_warpcore_reset_lane(bp, phy, 1);
4044         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4045         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4046                          MDIO_WC_REG_FX100_CTRL1, 0x014a);
4047         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4048                          MDIO_WC_REG_FX100_CTRL3, 0x0800);
4049         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4050                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4051         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4052                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4053         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4054                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4055         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4056                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4057         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4058                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4059         lane = bnx2x_get_warpcore_lane(phy, params);
4060         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4061                          MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4062         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4063                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4064         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4065                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4066         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4067                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4068         bnx2x_warpcore_reset_lane(bp, phy, 0);
4069 }
4070
4071 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4072                                                 u32 chip_id,
4073                                                 u32 shmem_base, u8 port,
4074                                                 u8 *gpio_num, u8 *gpio_port)
4075 {
4076         u32 cfg_pin;
4077         *gpio_num = 0;
4078         *gpio_port = 0;
4079         if (CHIP_IS_E3(bp)) {
4080                 cfg_pin = (REG_RD(bp, shmem_base +
4081                                 offsetof(struct shmem_region,
4082                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4083                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4084                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4085
4086                 /*
4087                  * Should not happen. This function called upon interrupt
4088                  * triggered by GPIO ( since EPIO can only generate interrupts
4089                  * to MCP).
4090                  * So if this function was called and none of the GPIOs was set,
4091                  * it means the shit hit the fan.
4092                  */
4093                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4094                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4095                         DP(NETIF_MSG_LINK, "ERROR: Invalid cfg pin %x for "
4096                                            "module detect indication\n",
4097                                        cfg_pin);
4098                         return -EINVAL;
4099                 }
4100
4101                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4102                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4103         } else {
4104                 *gpio_num = MISC_REGISTERS_GPIO_3;
4105                 *gpio_port = port;
4106         }
4107         DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4108         return 0;
4109 }
4110
4111 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4112                                        struct link_params *params)
4113 {
4114         struct bnx2x *bp = params->bp;
4115         u8 gpio_num, gpio_port;
4116         u32 gpio_val;
4117         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4118                                       params->shmem_base, params->port,
4119                                       &gpio_num, &gpio_port) != 0)
4120                 return 0;
4121         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4122
4123         /* Call the handling function in case module is detected */
4124         if (gpio_val == 0)
4125                 return 1;
4126         else
4127                 return 0;
4128 }
4129
4130 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4131                                        struct link_params *params,
4132                                        struct link_vars *vars)
4133 {
4134         struct bnx2x *bp = params->bp;
4135         u32 serdes_net_if;
4136         u8 fiber_mode;
4137         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4138         serdes_net_if = (REG_RD(bp, params->shmem_base +
4139                          offsetof(struct shmem_region, dev_info.
4140                                   port_hw_config[params->port].default_cfg)) &
4141                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4142         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4143                            "serdes_net_if = 0x%x\n",
4144                        vars->line_speed, serdes_net_if);
4145         bnx2x_set_aer_mmd(params, phy);
4146
4147         vars->phy_flags |= PHY_XGXS_FLAG;
4148         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4149             (phy->req_line_speed &&
4150              ((phy->req_line_speed == SPEED_100) ||
4151               (phy->req_line_speed == SPEED_10)))) {
4152                 vars->phy_flags |= PHY_SGMII_FLAG;
4153                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4154                 bnx2x_warpcore_clear_regs(phy, params, lane);
4155                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
4156         } else {
4157                 switch (serdes_net_if) {
4158                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4159                         /* Enable KR Auto Neg */
4160                         if (params->loopback_mode == LOOPBACK_NONE)
4161                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4162                         else {
4163                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4164                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4165                         }
4166                         break;
4167
4168                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4169                         bnx2x_warpcore_clear_regs(phy, params, lane);
4170                         if (vars->line_speed == SPEED_10000) {
4171                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4172                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4173                         } else {
4174                                 if (SINGLE_MEDIA_DIRECT(params)) {
4175                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4176                                         fiber_mode = 1;
4177                                 } else {
4178                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4179                                         fiber_mode = 0;
4180                                 }
4181                                 bnx2x_warpcore_set_sgmii_speed(phy,
4182                                                                 params,
4183                                                                 fiber_mode);
4184                         }
4185
4186                         break;
4187
4188                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4189
4190                         bnx2x_warpcore_clear_regs(phy, params, lane);
4191                         if (vars->line_speed == SPEED_10000) {
4192                                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4193                                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4194                         } else if (vars->line_speed == SPEED_1000) {
4195                                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4196                                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
4197                         }
4198                         /* Issue Module detection */
4199                         if (bnx2x_is_sfp_module_plugged(phy, params))
4200                                 bnx2x_sfp_module_detection(phy, params);
4201                         break;
4202
4203                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4204                         if (vars->line_speed != SPEED_20000) {
4205                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4206                                 return;
4207                         }
4208                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4209                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4210                         /* Issue Module detection */
4211
4212                         bnx2x_sfp_module_detection(phy, params);
4213                         break;
4214
4215                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4216                         if (vars->line_speed != SPEED_20000) {
4217                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4218                                 return;
4219                         }
4220                         DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4221                         bnx2x_warpcore_set_20G_KR2(bp, phy);
4222                         break;
4223
4224                 default:
4225                         DP(NETIF_MSG_LINK, "Unsupported Serdes Net Interface "
4226                                            "0x%x\n", serdes_net_if);
4227                         return;
4228                 }
4229         }
4230
4231         /* Take lane out of reset after configuration is finished */
4232         bnx2x_warpcore_reset_lane(bp, phy, 0);
4233         DP(NETIF_MSG_LINK, "Exit config init\n");
4234 }
4235
4236 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4237                                          struct bnx2x_phy *phy,
4238                                          u8 tx_en)
4239 {
4240         struct bnx2x *bp = params->bp;
4241         u32 cfg_pin;
4242         u8 port = params->port;
4243
4244         cfg_pin = REG_RD(bp, params->shmem_base +
4245                                 offsetof(struct shmem_region,
4246                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4247                                 PORT_HW_CFG_TX_LASER_MASK;
4248         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4249         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4250         /* For 20G, the expected pin to be used is 3 pins after the current */
4251
4252         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4253         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4254                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4255 }
4256
4257 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4258                                       struct link_params *params)
4259 {
4260         struct bnx2x *bp = params->bp;
4261         u16 val16;
4262         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4263         bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4264         bnx2x_set_aer_mmd(params, phy);
4265         /* Global register */
4266         bnx2x_warpcore_reset_lane(bp, phy, 1);
4267
4268         /* Clear loopback settings (if any) */
4269         /* 10G & 20G */
4270         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4271                         MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4272         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4273                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4274                          0xBFFF);
4275
4276         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4277                         MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4278         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4279                         MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4280
4281         /* Update those 1-copy registers */
4282         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4283                           MDIO_AER_BLOCK_AER_REG, 0);
4284                 /* Enable 1G MDIO (1-copy) */
4285         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4286                         MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4287                         &val16);
4288         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4289                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4290                          val16 & ~0x10);
4291
4292         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4293                         MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4294         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4295                          MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4296                          val16 & 0xff00);
4297
4298 }
4299
4300 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4301                                         struct link_params *params)
4302 {
4303         struct bnx2x *bp = params->bp;
4304         u16 val16;
4305         u32 lane;
4306         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4307                        params->loopback_mode, phy->req_line_speed);
4308
4309         if (phy->req_line_speed < SPEED_10000) {
4310                 /* 10/100/1000 */
4311
4312                 /* Update those 1-copy registers */
4313                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4314                                   MDIO_AER_BLOCK_AER_REG, 0);
4315                 /* Enable 1G MDIO (1-copy) */
4316                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4317                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4318                                 &val16);
4319                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4320                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4321                                 val16 | 0x10);
4322                 /* Set 1G loopback based on lane (1-copy) */
4323                 lane = bnx2x_get_warpcore_lane(phy, params);
4324                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4325                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4326                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4327                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4328                                 val16 | (1<<lane));
4329
4330                 /* Switch back to 4-copy registers */
4331                 bnx2x_set_aer_mmd(params, phy);
4332                 /* Global loopback, not recommended. */
4333                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4334                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4335                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4336                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4337                                 0x4000);
4338         } else {
4339                 /* 10G & 20G */
4340                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4341                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4342                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4343                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4344                                  0x4000);
4345
4346                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4347                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4348                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4349                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4350         }
4351 }
4352
4353
4354 void bnx2x_link_status_update(struct link_params *params,
4355                               struct link_vars *vars)
4356 {
4357         struct bnx2x *bp = params->bp;
4358         u8 link_10g_plus;
4359         u8 port = params->port;
4360         u32 sync_offset, media_types;
4361         /* Update PHY configuration */
4362         set_phy_vars(params, vars);
4363
4364         vars->link_status = REG_RD(bp, params->shmem_base +
4365                                    offsetof(struct shmem_region,
4366                                             port_mb[port].link_status));
4367
4368         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4369         vars->phy_flags = PHY_XGXS_FLAG;
4370         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4371                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4372
4373         if (vars->link_up) {
4374                 DP(NETIF_MSG_LINK, "phy link up\n");
4375
4376                 vars->phy_link_up = 1;
4377                 vars->duplex = DUPLEX_FULL;
4378                 switch (vars->link_status &
4379                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4380                         case LINK_10THD:
4381                                 vars->duplex = DUPLEX_HALF;
4382                                 /* fall thru */
4383                         case LINK_10TFD:
4384                                 vars->line_speed = SPEED_10;
4385                                 break;
4386
4387                         case LINK_100TXHD:
4388                                 vars->duplex = DUPLEX_HALF;
4389                                 /* fall thru */
4390                         case LINK_100T4:
4391                         case LINK_100TXFD:
4392                                 vars->line_speed = SPEED_100;
4393                                 break;
4394
4395                         case LINK_1000THD:
4396                                 vars->duplex = DUPLEX_HALF;
4397                                 /* fall thru */
4398                         case LINK_1000TFD:
4399                                 vars->line_speed = SPEED_1000;
4400                                 break;
4401
4402                         case LINK_2500THD:
4403                                 vars->duplex = DUPLEX_HALF;
4404                                 /* fall thru */
4405                         case LINK_2500TFD:
4406                                 vars->line_speed = SPEED_2500;
4407                                 break;
4408
4409                         case LINK_10GTFD:
4410                                 vars->line_speed = SPEED_10000;
4411                                 break;
4412                         case LINK_20GTFD:
4413                                 vars->line_speed = SPEED_20000;
4414                                 break;
4415                         default:
4416                                 break;
4417                 }
4418                 vars->flow_ctrl = 0;
4419                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4420                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4421
4422                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4423                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4424
4425                 if (!vars->flow_ctrl)
4426                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4427
4428                 if (vars->line_speed &&
4429                     ((vars->line_speed == SPEED_10) ||
4430                      (vars->line_speed == SPEED_100))) {
4431                         vars->phy_flags |= PHY_SGMII_FLAG;
4432                 } else {
4433                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4434                 }
4435                 if (vars->line_speed &&
4436                     USES_WARPCORE(bp) &&
4437                     (vars->line_speed == SPEED_1000))
4438                         vars->phy_flags |= PHY_SGMII_FLAG;
4439                 /* anything 10 and over uses the bmac */
4440                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4441
4442                 if (link_10g_plus) {
4443                         if (USES_WARPCORE(bp))
4444                                 vars->mac_type = MAC_TYPE_XMAC;
4445                         else
4446                                 vars->mac_type = MAC_TYPE_BMAC;
4447                 } else {
4448                         if (USES_WARPCORE(bp))
4449                                 vars->mac_type = MAC_TYPE_UMAC;
4450                         else
4451                                 vars->mac_type = MAC_TYPE_EMAC;
4452                 }
4453         } else { /* link down */
4454                 DP(NETIF_MSG_LINK, "phy link down\n");
4455
4456                 vars->phy_link_up = 0;
4457
4458                 vars->line_speed = 0;
4459                 vars->duplex = DUPLEX_FULL;
4460                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4461
4462                 /* indicate no mac active */
4463                 vars->mac_type = MAC_TYPE_NONE;
4464                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4465                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4466         }
4467
4468         /* Sync media type */
4469         sync_offset = params->shmem_base +
4470                         offsetof(struct shmem_region,
4471                                  dev_info.port_hw_config[port].media_type);
4472         media_types = REG_RD(bp, sync_offset);
4473
4474         params->phy[INT_PHY].media_type =
4475                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4476                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4477         params->phy[EXT_PHY1].media_type =
4478                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4479                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4480         params->phy[EXT_PHY2].media_type =
4481                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4482                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4483         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4484
4485         /* Sync AEU offset */
4486         sync_offset = params->shmem_base +
4487                         offsetof(struct shmem_region,
4488                                  dev_info.port_hw_config[port].aeu_int_mask);
4489
4490         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4491
4492         /* Sync PFC status */
4493         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4494                 params->feature_config_flags |=
4495                                         FEATURE_CONFIG_PFC_ENABLED;
4496         else
4497                 params->feature_config_flags &=
4498                                         ~FEATURE_CONFIG_PFC_ENABLED;
4499
4500         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4501                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4502         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4503                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4504 }
4505
4506
4507 static void bnx2x_set_master_ln(struct link_params *params,
4508                                 struct bnx2x_phy *phy)
4509 {
4510         struct bnx2x *bp = params->bp;
4511         u16 new_master_ln, ser_lane;
4512         ser_lane = ((params->lane_config &
4513                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4514                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4515
4516         /* set the master_ln for AN */
4517         CL22_RD_OVER_CL45(bp, phy,
4518                           MDIO_REG_BANK_XGXS_BLOCK2,
4519                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4520                           &new_master_ln);
4521
4522         CL22_WR_OVER_CL45(bp, phy,
4523                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4524                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4525                           (new_master_ln | ser_lane));
4526 }
4527
4528 static int bnx2x_reset_unicore(struct link_params *params,
4529                                struct bnx2x_phy *phy,
4530                                u8 set_serdes)
4531 {
4532         struct bnx2x *bp = params->bp;
4533         u16 mii_control;
4534         u16 i;
4535         CL22_RD_OVER_CL45(bp, phy,
4536                           MDIO_REG_BANK_COMBO_IEEE0,
4537                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4538
4539         /* reset the unicore */
4540         CL22_WR_OVER_CL45(bp, phy,
4541                           MDIO_REG_BANK_COMBO_IEEE0,
4542                           MDIO_COMBO_IEEE0_MII_CONTROL,
4543                           (mii_control |
4544                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4545         if (set_serdes)
4546                 bnx2x_set_serdes_access(bp, params->port);
4547
4548         /* wait for the reset to self clear */
4549         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4550                 udelay(5);
4551
4552                 /* the reset erased the previous bank value */
4553                 CL22_RD_OVER_CL45(bp, phy,
4554                                   MDIO_REG_BANK_COMBO_IEEE0,
4555                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4556                                   &mii_control);
4557
4558                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4559                         udelay(5);
4560                         return 0;
4561                 }
4562         }
4563
4564         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4565                               " Port %d\n",
4566                          params->port);
4567         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4568         return -EINVAL;
4569
4570 }
4571
4572 static void bnx2x_set_swap_lanes(struct link_params *params,
4573                                  struct bnx2x_phy *phy)
4574 {
4575         struct bnx2x *bp = params->bp;
4576         /*
4577          *  Each two bits represents a lane number:
4578          *  No swap is 0123 => 0x1b no need to enable the swap
4579          */
4580         u16 ser_lane, rx_lane_swap, tx_lane_swap;
4581
4582         ser_lane = ((params->lane_config &
4583                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4584                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4585         rx_lane_swap = ((params->lane_config &
4586                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4587                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4588         tx_lane_swap = ((params->lane_config &
4589                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4590                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4591
4592         if (rx_lane_swap != 0x1b) {
4593                 CL22_WR_OVER_CL45(bp, phy,
4594                                   MDIO_REG_BANK_XGXS_BLOCK2,
4595                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4596                                   (rx_lane_swap |
4597                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4598                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4599         } else {
4600                 CL22_WR_OVER_CL45(bp, phy,
4601                                   MDIO_REG_BANK_XGXS_BLOCK2,
4602                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4603         }
4604
4605         if (tx_lane_swap != 0x1b) {
4606                 CL22_WR_OVER_CL45(bp, phy,
4607                                   MDIO_REG_BANK_XGXS_BLOCK2,
4608                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4609                                   (tx_lane_swap |
4610                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4611         } else {
4612                 CL22_WR_OVER_CL45(bp, phy,
4613                                   MDIO_REG_BANK_XGXS_BLOCK2,
4614                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4615         }
4616 }
4617
4618 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4619                                          struct link_params *params)
4620 {
4621         struct bnx2x *bp = params->bp;
4622         u16 control2;
4623         CL22_RD_OVER_CL45(bp, phy,
4624                           MDIO_REG_BANK_SERDES_DIGITAL,
4625                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4626                           &control2);
4627         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4628                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4629         else
4630                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4631         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4632                 phy->speed_cap_mask, control2);
4633         CL22_WR_OVER_CL45(bp, phy,
4634                           MDIO_REG_BANK_SERDES_DIGITAL,
4635                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4636                           control2);
4637
4638         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4639              (phy->speed_cap_mask &
4640                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4641                 DP(NETIF_MSG_LINK, "XGXS\n");
4642
4643                 CL22_WR_OVER_CL45(bp, phy,
4644                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4645                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4646                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4647
4648                 CL22_RD_OVER_CL45(bp, phy,
4649                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4650                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4651                                   &control2);
4652
4653
4654                 control2 |=
4655                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4656
4657                 CL22_WR_OVER_CL45(bp, phy,
4658                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4659                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4660                                   control2);
4661
4662                 /* Disable parallel detection of HiG */
4663                 CL22_WR_OVER_CL45(bp, phy,
4664                                   MDIO_REG_BANK_XGXS_BLOCK2,
4665                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4666                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4667                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4668         }
4669 }
4670
4671 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4672                               struct link_params *params,
4673                               struct link_vars *vars,
4674                               u8 enable_cl73)
4675 {
4676         struct bnx2x *bp = params->bp;
4677         u16 reg_val;
4678
4679         /* CL37 Autoneg */
4680         CL22_RD_OVER_CL45(bp, phy,
4681                           MDIO_REG_BANK_COMBO_IEEE0,
4682                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4683
4684         /* CL37 Autoneg Enabled */
4685         if (vars->line_speed == SPEED_AUTO_NEG)
4686                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4687         else /* CL37 Autoneg Disabled */
4688                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4689                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4690
4691         CL22_WR_OVER_CL45(bp, phy,
4692                           MDIO_REG_BANK_COMBO_IEEE0,
4693                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4694
4695         /* Enable/Disable Autodetection */
4696
4697         CL22_RD_OVER_CL45(bp, phy,
4698                           MDIO_REG_BANK_SERDES_DIGITAL,
4699                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4700         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4701                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4702         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4703         if (vars->line_speed == SPEED_AUTO_NEG)
4704                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4705         else
4706                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4707
4708         CL22_WR_OVER_CL45(bp, phy,
4709                           MDIO_REG_BANK_SERDES_DIGITAL,
4710                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4711
4712         /* Enable TetonII and BAM autoneg */
4713         CL22_RD_OVER_CL45(bp, phy,
4714                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4715                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4716                           &reg_val);
4717         if (vars->line_speed == SPEED_AUTO_NEG) {
4718                 /* Enable BAM aneg Mode and TetonII aneg Mode */
4719                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4720                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4721         } else {
4722                 /* TetonII and BAM Autoneg Disabled */
4723                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4724                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4725         }
4726         CL22_WR_OVER_CL45(bp, phy,
4727                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4728                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4729                           reg_val);
4730
4731         if (enable_cl73) {
4732                 /* Enable Cl73 FSM status bits */
4733                 CL22_WR_OVER_CL45(bp, phy,
4734                                   MDIO_REG_BANK_CL73_USERB0,
4735                                   MDIO_CL73_USERB0_CL73_UCTRL,
4736                                   0xe);
4737
4738                 /* Enable BAM Station Manager*/
4739                 CL22_WR_OVER_CL45(bp, phy,
4740                         MDIO_REG_BANK_CL73_USERB0,
4741                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4742                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4743                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4744                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4745
4746                 /* Advertise CL73 link speeds */
4747                 CL22_RD_OVER_CL45(bp, phy,
4748                                   MDIO_REG_BANK_CL73_IEEEB1,
4749                                   MDIO_CL73_IEEEB1_AN_ADV2,
4750                                   &reg_val);
4751                 if (phy->speed_cap_mask &
4752                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4753                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4754                 if (phy->speed_cap_mask &
4755                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4756                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4757
4758                 CL22_WR_OVER_CL45(bp, phy,
4759                                   MDIO_REG_BANK_CL73_IEEEB1,
4760                                   MDIO_CL73_IEEEB1_AN_ADV2,
4761                                   reg_val);
4762
4763                 /* CL73 Autoneg Enabled */
4764                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4765
4766         } else /* CL73 Autoneg Disabled */
4767                 reg_val = 0;
4768
4769         CL22_WR_OVER_CL45(bp, phy,
4770                           MDIO_REG_BANK_CL73_IEEEB0,
4771                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4772 }
4773
4774 /* program SerDes, forced speed */
4775 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4776                                  struct link_params *params,
4777                                  struct link_vars *vars)
4778 {
4779         struct bnx2x *bp = params->bp;
4780         u16 reg_val;
4781
4782         /* program duplex, disable autoneg and sgmii*/
4783         CL22_RD_OVER_CL45(bp, phy,
4784                           MDIO_REG_BANK_COMBO_IEEE0,
4785                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4786         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4787                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4788                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4789         if (phy->req_duplex == DUPLEX_FULL)
4790                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4791         CL22_WR_OVER_CL45(bp, phy,
4792                           MDIO_REG_BANK_COMBO_IEEE0,
4793                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4794
4795         /*
4796          * program speed
4797          *  - needed only if the speed is greater than 1G (2.5G or 10G)
4798          */
4799         CL22_RD_OVER_CL45(bp, phy,
4800                           MDIO_REG_BANK_SERDES_DIGITAL,
4801                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
4802         /* clearing the speed value before setting the right speed */
4803         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4804
4805         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4806                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4807
4808         if (!((vars->line_speed == SPEED_1000) ||
4809               (vars->line_speed == SPEED_100) ||
4810               (vars->line_speed == SPEED_10))) {
4811
4812                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4813                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4814                 if (vars->line_speed == SPEED_10000)
4815                         reg_val |=
4816                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4817         }
4818
4819         CL22_WR_OVER_CL45(bp, phy,
4820                           MDIO_REG_BANK_SERDES_DIGITAL,
4821                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
4822
4823 }
4824
4825 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
4826                                               struct link_params *params)
4827 {
4828         struct bnx2x *bp = params->bp;
4829         u16 val = 0;
4830
4831         /* configure the 48 bits for BAM AN */
4832
4833         /* set extended capabilities */
4834         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4835                 val |= MDIO_OVER_1G_UP1_2_5G;
4836         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4837                 val |= MDIO_OVER_1G_UP1_10G;
4838         CL22_WR_OVER_CL45(bp, phy,
4839                           MDIO_REG_BANK_OVER_1G,
4840                           MDIO_OVER_1G_UP1, val);
4841
4842         CL22_WR_OVER_CL45(bp, phy,
4843                           MDIO_REG_BANK_OVER_1G,
4844                           MDIO_OVER_1G_UP3, 0x400);
4845 }
4846
4847 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
4848                                               struct link_params *params,
4849                                               u16 ieee_fc)
4850 {
4851         struct bnx2x *bp = params->bp;
4852         u16 val;
4853         /* for AN, we are always publishing full duplex */
4854
4855         CL22_WR_OVER_CL45(bp, phy,
4856                           MDIO_REG_BANK_COMBO_IEEE0,
4857                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4858         CL22_RD_OVER_CL45(bp, phy,
4859                           MDIO_REG_BANK_CL73_IEEEB1,
4860                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
4861         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4862         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4863         CL22_WR_OVER_CL45(bp, phy,
4864                           MDIO_REG_BANK_CL73_IEEEB1,
4865                           MDIO_CL73_IEEEB1_AN_ADV1, val);
4866 }
4867
4868 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
4869                                   struct link_params *params,
4870                                   u8 enable_cl73)
4871 {
4872         struct bnx2x *bp = params->bp;
4873         u16 mii_control;
4874
4875         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
4876         /* Enable and restart BAM/CL37 aneg */
4877
4878         if (enable_cl73) {
4879                 CL22_RD_OVER_CL45(bp, phy,
4880                                   MDIO_REG_BANK_CL73_IEEEB0,
4881                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4882                                   &mii_control);
4883
4884                 CL22_WR_OVER_CL45(bp, phy,
4885                                   MDIO_REG_BANK_CL73_IEEEB0,
4886                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4887                                   (mii_control |
4888                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4889                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4890         } else {
4891
4892                 CL22_RD_OVER_CL45(bp, phy,
4893                                   MDIO_REG_BANK_COMBO_IEEE0,
4894                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4895                                   &mii_control);
4896                 DP(NETIF_MSG_LINK,
4897                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
4898                          mii_control);
4899                 CL22_WR_OVER_CL45(bp, phy,
4900                                   MDIO_REG_BANK_COMBO_IEEE0,
4901                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4902                                   (mii_control |
4903                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4904                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4905         }
4906 }
4907
4908 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
4909                                            struct link_params *params,
4910                                            struct link_vars *vars)
4911 {
4912         struct bnx2x *bp = params->bp;
4913         u16 control1;
4914
4915         /* in SGMII mode, the unicore is always slave */
4916
4917         CL22_RD_OVER_CL45(bp, phy,
4918                           MDIO_REG_BANK_SERDES_DIGITAL,
4919                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4920                           &control1);
4921         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4922         /* set sgmii mode (and not fiber) */
4923         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4924                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4925                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4926         CL22_WR_OVER_CL45(bp, phy,
4927                           MDIO_REG_BANK_SERDES_DIGITAL,
4928                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4929                           control1);
4930
4931         /* if forced speed */
4932         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
4933                 /* set speed, disable autoneg */
4934                 u16 mii_control;
4935
4936                 CL22_RD_OVER_CL45(bp, phy,
4937                                   MDIO_REG_BANK_COMBO_IEEE0,
4938                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4939                                   &mii_control);
4940                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4941                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
4942                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4943
4944                 switch (vars->line_speed) {
4945                 case SPEED_100:
4946                         mii_control |=
4947                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4948                         break;
4949                 case SPEED_1000:
4950                         mii_control |=
4951                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4952                         break;
4953                 case SPEED_10:
4954                         /* there is nothing to set for 10M */
4955                         break;
4956                 default:
4957                         /* invalid speed for SGMII */
4958                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
4959                                   vars->line_speed);
4960                         break;
4961                 }
4962
4963                 /* setting the full duplex */
4964                 if (phy->req_duplex == DUPLEX_FULL)
4965                         mii_control |=
4966                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4967                 CL22_WR_OVER_CL45(bp, phy,
4968                                   MDIO_REG_BANK_COMBO_IEEE0,
4969                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4970                                   mii_control);
4971
4972         } else { /* AN mode */
4973                 /* enable and restart AN */
4974                 bnx2x_restart_autoneg(phy, params, 0);
4975         }
4976 }
4977
4978
4979 /*
4980  * link management
4981  */
4982
4983 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
4984                                              struct link_params *params)
4985 {
4986         struct bnx2x *bp = params->bp;
4987         u16 pd_10g, status2_1000x;
4988         if (phy->req_line_speed != SPEED_AUTO_NEG)
4989                 return 0;
4990         CL22_RD_OVER_CL45(bp, phy,
4991                           MDIO_REG_BANK_SERDES_DIGITAL,
4992                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4993                           &status2_1000x);
4994         CL22_RD_OVER_CL45(bp, phy,
4995                           MDIO_REG_BANK_SERDES_DIGITAL,
4996                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4997                           &status2_1000x);
4998         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4999                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5000                          params->port);
5001                 return 1;
5002         }
5003
5004         CL22_RD_OVER_CL45(bp, phy,
5005                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5006                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5007                           &pd_10g);
5008
5009         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5010                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5011                          params->port);
5012                 return 1;
5013         }
5014         return 0;
5015 }
5016
5017 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5018                                     struct link_params *params,
5019                                     struct link_vars *vars,
5020                                     u32 gp_status)
5021 {
5022         struct bnx2x *bp = params->bp;
5023         u16 ld_pause;   /* local driver */
5024         u16 lp_pause;   /* link partner */
5025         u16 pause_result;
5026
5027         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5028
5029         /* resolve from gp_status in case of AN complete and not sgmii */
5030         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
5031                 vars->flow_ctrl = phy->req_flow_ctrl;
5032         else if (phy->req_line_speed != SPEED_AUTO_NEG)
5033                 vars->flow_ctrl = params->req_fc_auto_adv;
5034         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5035                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5036                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5037                         vars->flow_ctrl = params->req_fc_auto_adv;
5038                         return;
5039                 }
5040                 if ((gp_status &
5041                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5042                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5043                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5044                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5045
5046                         CL22_RD_OVER_CL45(bp, phy,
5047                                           MDIO_REG_BANK_CL73_IEEEB1,
5048                                           MDIO_CL73_IEEEB1_AN_ADV1,
5049                                           &ld_pause);
5050                         CL22_RD_OVER_CL45(bp, phy,
5051                                           MDIO_REG_BANK_CL73_IEEEB1,
5052                                           MDIO_CL73_IEEEB1_AN_LP_ADV1,
5053                                           &lp_pause);
5054                         pause_result = (ld_pause &
5055                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5056                                         >> 8;
5057                         pause_result |= (lp_pause &
5058                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5059                                         >> 10;
5060                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5061                                  pause_result);
5062                 } else {
5063                         CL22_RD_OVER_CL45(bp, phy,
5064                                           MDIO_REG_BANK_COMBO_IEEE0,
5065                                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5066                                           &ld_pause);
5067                         CL22_RD_OVER_CL45(bp, phy,
5068                                 MDIO_REG_BANK_COMBO_IEEE0,
5069                                 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5070                                 &lp_pause);
5071                         pause_result = (ld_pause &
5072                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5073                         pause_result |= (lp_pause &
5074                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5075                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5076                                  pause_result);
5077                 }
5078                 bnx2x_pause_resolve(vars, pause_result);
5079         }
5080         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5081 }
5082
5083 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5084                                          struct link_params *params)
5085 {
5086         struct bnx2x *bp = params->bp;
5087         u16 rx_status, ustat_val, cl37_fsm_received;
5088         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5089         /* Step 1: Make sure signal is detected */
5090         CL22_RD_OVER_CL45(bp, phy,
5091                           MDIO_REG_BANK_RX0,
5092                           MDIO_RX0_RX_STATUS,
5093                           &rx_status);
5094         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5095             (MDIO_RX0_RX_STATUS_SIGDET)) {
5096                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5097                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5098                 CL22_WR_OVER_CL45(bp, phy,
5099                                   MDIO_REG_BANK_CL73_IEEEB0,
5100                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5101                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5102                 return;
5103         }
5104         /* Step 2: Check CL73 state machine */
5105         CL22_RD_OVER_CL45(bp, phy,
5106                           MDIO_REG_BANK_CL73_USERB0,
5107                           MDIO_CL73_USERB0_CL73_USTAT1,
5108                           &ustat_val);
5109         if ((ustat_val &
5110              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5111               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5112             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5113               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5114                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5115                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5116                 return;
5117         }
5118         /*
5119          * Step 3: Check CL37 Message Pages received to indicate LP
5120          * supports only CL37
5121          */
5122         CL22_RD_OVER_CL45(bp, phy,
5123                           MDIO_REG_BANK_REMOTE_PHY,
5124                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5125                           &cl37_fsm_received);
5126         if ((cl37_fsm_received &
5127              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5128              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5129             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5130               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5131                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5132                              "misc_rx_status(0x8330) = 0x%x\n",
5133                          cl37_fsm_received);
5134                 return;
5135         }
5136         /*
5137          * The combined cl37/cl73 fsm state information indicating that
5138          * we are connected to a device which does not support cl73, but
5139          * does support cl37 BAM. In this case we disable cl73 and
5140          * restart cl37 auto-neg
5141          */
5142
5143         /* Disable CL73 */
5144         CL22_WR_OVER_CL45(bp, phy,
5145                           MDIO_REG_BANK_CL73_IEEEB0,
5146                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5147                           0);
5148         /* Restart CL37 autoneg */
5149         bnx2x_restart_autoneg(phy, params, 0);
5150         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5151 }
5152
5153 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5154                                   struct link_params *params,
5155                                   struct link_vars *vars,
5156                                   u32 gp_status)
5157 {
5158         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5159                 vars->link_status |=
5160                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5161
5162         if (bnx2x_direct_parallel_detect_used(phy, params))
5163                 vars->link_status |=
5164                         LINK_STATUS_PARALLEL_DETECTION_USED;
5165 }
5166 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5167                                      struct link_params *params,
5168                                       struct link_vars *vars,
5169                                       u16 is_link_up,
5170                                       u16 speed_mask,
5171                                       u16 is_duplex)
5172 {
5173         struct bnx2x *bp = params->bp;
5174         if (phy->req_line_speed == SPEED_AUTO_NEG)
5175                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5176         if (is_link_up) {
5177                 DP(NETIF_MSG_LINK, "phy link up\n");
5178
5179                 vars->phy_link_up = 1;
5180                 vars->link_status |= LINK_STATUS_LINK_UP;
5181
5182                 switch (speed_mask) {
5183                 case GP_STATUS_10M:
5184                         vars->line_speed = SPEED_10;
5185                         if (vars->duplex == DUPLEX_FULL)
5186                                 vars->link_status |= LINK_10TFD;
5187                         else
5188                                 vars->link_status |= LINK_10THD;
5189                         break;
5190
5191                 case GP_STATUS_100M:
5192                         vars->line_speed = SPEED_100;
5193                         if (vars->duplex == DUPLEX_FULL)
5194                                 vars->link_status |= LINK_100TXFD;
5195                         else
5196                                 vars->link_status |= LINK_100TXHD;
5197                         break;
5198
5199                 case GP_STATUS_1G:
5200                 case GP_STATUS_1G_KX:
5201                         vars->line_speed = SPEED_1000;
5202                         if (vars->duplex == DUPLEX_FULL)
5203                                 vars->link_status |= LINK_1000TFD;
5204                         else
5205                                 vars->link_status |= LINK_1000THD;
5206                         break;
5207
5208                 case GP_STATUS_2_5G:
5209                         vars->line_speed = SPEED_2500;
5210                         if (vars->duplex == DUPLEX_FULL)
5211                                 vars->link_status |= LINK_2500TFD;
5212                         else
5213                                 vars->link_status |= LINK_2500THD;
5214                         break;
5215
5216                 case GP_STATUS_5G:
5217                 case GP_STATUS_6G:
5218                         DP(NETIF_MSG_LINK,
5219                                  "link speed unsupported  gp_status 0x%x\n",
5220                                   speed_mask);
5221                         return -EINVAL;
5222
5223                 case GP_STATUS_10G_KX4:
5224                 case GP_STATUS_10G_HIG:
5225                 case GP_STATUS_10G_CX4:
5226                 case GP_STATUS_10G_KR:
5227                 case GP_STATUS_10G_SFI:
5228                 case GP_STATUS_10G_XFI:
5229                         vars->line_speed = SPEED_10000;
5230                         vars->link_status |= LINK_10GTFD;
5231                         break;
5232                 case GP_STATUS_20G_DXGXS:
5233                         vars->line_speed = SPEED_20000;
5234                         vars->link_status |= LINK_20GTFD;
5235                         break;
5236                 default:
5237                         DP(NETIF_MSG_LINK,
5238                                   "link speed unsupported gp_status 0x%x\n",
5239                                   speed_mask);
5240                         return -EINVAL;
5241                 }
5242         } else { /* link_down */
5243                 DP(NETIF_MSG_LINK, "phy link down\n");
5244
5245                 vars->phy_link_up = 0;
5246
5247                 vars->duplex = DUPLEX_FULL;
5248                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5249                 vars->mac_type = MAC_TYPE_NONE;
5250         }
5251         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5252                     vars->phy_link_up, vars->line_speed);
5253         return 0;
5254 }
5255
5256 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5257                                       struct link_params *params,
5258                                       struct link_vars *vars)
5259 {
5260
5261         struct bnx2x *bp = params->bp;
5262
5263         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5264         int rc = 0;
5265
5266         /* Read gp_status */
5267         CL22_RD_OVER_CL45(bp, phy,
5268                           MDIO_REG_BANK_GP_STATUS,
5269                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5270                           &gp_status);
5271         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5272                 duplex = DUPLEX_FULL;
5273         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5274                 link_up = 1;
5275         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5276         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5277                        gp_status, link_up, speed_mask);
5278         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5279                                          duplex);
5280         if (rc == -EINVAL)
5281                 return rc;
5282
5283         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5284                 if (SINGLE_MEDIA_DIRECT(params)) {
5285                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5286                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5287                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5288                                                       gp_status);
5289                 }
5290         } else { /* link_down */
5291                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5292                     SINGLE_MEDIA_DIRECT(params)) {
5293                         /* Check signal is detected */
5294                         bnx2x_check_fallback_to_cl37(phy, params);
5295                 }
5296         }
5297
5298         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5299                    vars->duplex, vars->flow_ctrl, vars->link_status);
5300         return rc;
5301 }
5302
5303 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5304                                      struct link_params *params,
5305                                      struct link_vars *vars)
5306 {
5307
5308         struct bnx2x *bp = params->bp;
5309
5310         u8 lane;
5311         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5312         int rc = 0;
5313         lane = bnx2x_get_warpcore_lane(phy, params);
5314         /* Read gp_status */
5315         if (phy->req_line_speed > SPEED_10000) {
5316                 u16 temp_link_up;
5317                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5318                                 1, &temp_link_up);
5319                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5320                                 1, &link_up);
5321                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5322                                temp_link_up, link_up);
5323                 link_up &= (1<<2);
5324                 if (link_up)
5325                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5326         } else {
5327                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5328                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5329                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5330                 /* Check for either KR or generic link up. */
5331                 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5332                         ((gp_status1 >> 12) & 0xf);
5333                 link_up = gp_status1 & (1 << lane);
5334                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5335                         u16 pd, gp_status4;
5336                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5337                                 /* Check Autoneg complete */
5338                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5339                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5340                                                 &gp_status4);
5341                                 if (gp_status4 & ((1<<12)<<lane))
5342                                         vars->link_status |=
5343                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5344
5345                                 /* Check parallel detect used */
5346                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5347                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5348                                                 &pd);
5349                                 if (pd & (1<<15))
5350                                         vars->link_status |=
5351                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5352                         }
5353                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5354                 }
5355         }
5356
5357         if (lane < 2) {
5358                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5359                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5360         } else {
5361                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5362                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5363         }
5364         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5365
5366         if ((lane & 1) == 0)
5367                 gp_speed <<= 8;
5368         gp_speed &= 0x3f00;
5369
5370
5371         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5372                                          duplex);
5373
5374         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5375                    vars->duplex, vars->flow_ctrl, vars->link_status);
5376         return rc;
5377 }
5378 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5379 {
5380         struct bnx2x *bp = params->bp;
5381         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5382         u16 lp_up2;
5383         u16 tx_driver;
5384         u16 bank;
5385
5386         /* read precomp */
5387         CL22_RD_OVER_CL45(bp, phy,
5388                           MDIO_REG_BANK_OVER_1G,
5389                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5390
5391         /* bits [10:7] at lp_up2, positioned at [15:12] */
5392         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5393                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5394                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5395
5396         if (lp_up2 == 0)
5397                 return;
5398
5399         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5400               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5401                 CL22_RD_OVER_CL45(bp, phy,
5402                                   bank,
5403                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5404
5405                 /* replace tx_driver bits [15:12] */
5406                 if (lp_up2 !=
5407                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5408                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5409                         tx_driver |= lp_up2;
5410                         CL22_WR_OVER_CL45(bp, phy,
5411                                           bank,
5412                                           MDIO_TX0_TX_DRIVER, tx_driver);
5413                 }
5414         }
5415 }
5416
5417 static int bnx2x_emac_program(struct link_params *params,
5418                               struct link_vars *vars)
5419 {
5420         struct bnx2x *bp = params->bp;
5421         u8 port = params->port;
5422         u16 mode = 0;
5423
5424         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5425         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5426                        EMAC_REG_EMAC_MODE,
5427                        (EMAC_MODE_25G_MODE |
5428                         EMAC_MODE_PORT_MII_10M |
5429                         EMAC_MODE_HALF_DUPLEX));
5430         switch (vars->line_speed) {
5431         case SPEED_10:
5432                 mode |= EMAC_MODE_PORT_MII_10M;
5433                 break;
5434
5435         case SPEED_100:
5436                 mode |= EMAC_MODE_PORT_MII;
5437                 break;
5438
5439         case SPEED_1000:
5440                 mode |= EMAC_MODE_PORT_GMII;
5441                 break;
5442
5443         case SPEED_2500:
5444                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5445                 break;
5446
5447         default:
5448                 /* 10G not valid for EMAC */
5449                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5450                            vars->line_speed);
5451                 return -EINVAL;
5452         }
5453
5454         if (vars->duplex == DUPLEX_HALF)
5455                 mode |= EMAC_MODE_HALF_DUPLEX;
5456         bnx2x_bits_en(bp,
5457                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5458                       mode);
5459
5460         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5461         return 0;
5462 }
5463
5464 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5465                                   struct link_params *params)
5466 {
5467
5468         u16 bank, i = 0;
5469         struct bnx2x *bp = params->bp;
5470
5471         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5472               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5473                         CL22_WR_OVER_CL45(bp, phy,
5474                                           bank,
5475                                           MDIO_RX0_RX_EQ_BOOST,
5476                                           phy->rx_preemphasis[i]);
5477         }
5478
5479         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5480                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5481                         CL22_WR_OVER_CL45(bp, phy,
5482                                           bank,
5483                                           MDIO_TX0_TX_DRIVER,
5484                                           phy->tx_preemphasis[i]);
5485         }
5486 }
5487
5488 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5489                                    struct link_params *params,
5490                                    struct link_vars *vars)
5491 {
5492         struct bnx2x *bp = params->bp;
5493         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5494                           (params->loopback_mode == LOOPBACK_XGXS));
5495         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5496                 if (SINGLE_MEDIA_DIRECT(params) &&
5497                     (params->feature_config_flags &
5498                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5499                         bnx2x_set_preemphasis(phy, params);
5500
5501                 /* forced speed requested? */
5502                 if (vars->line_speed != SPEED_AUTO_NEG ||
5503                     (SINGLE_MEDIA_DIRECT(params) &&
5504                      params->loopback_mode == LOOPBACK_EXT)) {
5505                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5506
5507                         /* disable autoneg */
5508                         bnx2x_set_autoneg(phy, params, vars, 0);
5509
5510                         /* program speed and duplex */
5511                         bnx2x_program_serdes(phy, params, vars);
5512
5513                 } else { /* AN_mode */
5514                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5515
5516                         /* AN enabled */
5517                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5518
5519                         /* program duplex & pause advertisement (for aneg) */
5520                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5521                                                           vars->ieee_fc);
5522
5523                         /* enable autoneg */
5524                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5525
5526                         /* enable and restart AN */
5527                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5528                 }
5529
5530         } else { /* SGMII mode */
5531                 DP(NETIF_MSG_LINK, "SGMII\n");
5532
5533                 bnx2x_initialize_sgmii_process(phy, params, vars);
5534         }
5535 }
5536
5537 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5538                           struct link_params *params,
5539                           struct link_vars *vars)
5540 {
5541         int rc;
5542         vars->phy_flags |= PHY_XGXS_FLAG;
5543         if ((phy->req_line_speed &&
5544              ((phy->req_line_speed == SPEED_100) ||
5545               (phy->req_line_speed == SPEED_10))) ||
5546             (!phy->req_line_speed &&
5547              (phy->speed_cap_mask >=
5548               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5549              (phy->speed_cap_mask <
5550               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5551             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5552                 vars->phy_flags |= PHY_SGMII_FLAG;
5553         else
5554                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5555
5556         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5557         bnx2x_set_aer_mmd(params, phy);
5558         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5559                 bnx2x_set_master_ln(params, phy);
5560
5561         rc = bnx2x_reset_unicore(params, phy, 0);
5562         /* reset the SerDes and wait for reset bit return low */
5563         if (rc != 0)
5564                 return rc;
5565
5566         bnx2x_set_aer_mmd(params, phy);
5567         /* setting the masterLn_def again after the reset */
5568         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5569                 bnx2x_set_master_ln(params, phy);
5570                 bnx2x_set_swap_lanes(params, phy);
5571         }
5572
5573         return rc;
5574 }
5575
5576 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5577                                      struct bnx2x_phy *phy,
5578                                      struct link_params *params)
5579 {
5580         u16 cnt, ctrl;
5581         /* Wait for soft reset to get cleared up to 1 sec */
5582         for (cnt = 0; cnt < 1000; cnt++) {
5583                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5584                         bnx2x_cl22_read(bp, phy,
5585                                 MDIO_PMA_REG_CTRL, &ctrl);
5586                 else
5587                         bnx2x_cl45_read(bp, phy,
5588                                 MDIO_PMA_DEVAD,
5589                                 MDIO_PMA_REG_CTRL, &ctrl);
5590                 if (!(ctrl & (1<<15)))
5591                         break;
5592                 msleep(1);
5593         }
5594
5595         if (cnt == 1000)
5596                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5597                                       " Port %d\n",
5598                          params->port);
5599         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5600         return cnt;
5601 }
5602
5603 static void bnx2x_link_int_enable(struct link_params *params)
5604 {
5605         u8 port = params->port;
5606         u32 mask;
5607         struct bnx2x *bp = params->bp;
5608
5609         /* Setting the status to report on link up for either XGXS or SerDes */
5610         if (CHIP_IS_E3(bp)) {
5611                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5612                 if (!(SINGLE_MEDIA_DIRECT(params)))
5613                         mask |= NIG_MASK_MI_INT;
5614         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5615                 mask = (NIG_MASK_XGXS0_LINK10G |
5616                         NIG_MASK_XGXS0_LINK_STATUS);
5617                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5618                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5619                         params->phy[INT_PHY].type !=
5620                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5621                         mask |= NIG_MASK_MI_INT;
5622                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5623                 }
5624
5625         } else { /* SerDes */
5626                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5627                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5628                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5629                         params->phy[INT_PHY].type !=
5630                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5631                         mask |= NIG_MASK_MI_INT;
5632                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5633                 }
5634         }
5635         bnx2x_bits_en(bp,
5636                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5637                       mask);
5638
5639         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5640                  (params->switch_cfg == SWITCH_CFG_10G),
5641                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5642         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5643                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5644                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5645                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5646         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5647            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5648            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5649 }
5650
5651 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5652                                      u8 exp_mi_int)
5653 {
5654         u32 latch_status = 0;
5655
5656         /*
5657          * Disable the MI INT ( external phy int ) by writing 1 to the
5658          * status register. Link down indication is high-active-signal,
5659          * so in this case we need to write the status to clear the XOR
5660          */
5661         /* Read Latched signals */
5662         latch_status = REG_RD(bp,
5663                                     NIG_REG_LATCH_STATUS_0 + port*8);
5664         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5665         /* Handle only those with latched-signal=up.*/
5666         if (exp_mi_int)
5667                 bnx2x_bits_en(bp,
5668                               NIG_REG_STATUS_INTERRUPT_PORT0
5669                               + port*4,
5670                               NIG_STATUS_EMAC0_MI_INT);
5671         else
5672                 bnx2x_bits_dis(bp,
5673                                NIG_REG_STATUS_INTERRUPT_PORT0
5674                                + port*4,
5675                                NIG_STATUS_EMAC0_MI_INT);
5676
5677         if (latch_status & 1) {
5678
5679                 /* For all latched-signal=up : Re-Arm Latch signals */
5680                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5681                        (latch_status & 0xfffe) | (latch_status & 1));
5682         }
5683         /* For all latched-signal=up,Write original_signal to status */
5684 }
5685
5686 static void bnx2x_link_int_ack(struct link_params *params,
5687                                struct link_vars *vars, u8 is_10g_plus)
5688 {
5689         struct bnx2x *bp = params->bp;
5690         u8 port = params->port;
5691         u32 mask;
5692         /*
5693          * First reset all status we assume only one line will be
5694          * change at a time
5695          */
5696         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5697                        (NIG_STATUS_XGXS0_LINK10G |
5698                         NIG_STATUS_XGXS0_LINK_STATUS |
5699                         NIG_STATUS_SERDES0_LINK_STATUS));
5700         if (vars->phy_link_up) {
5701                 if (USES_WARPCORE(bp))
5702                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
5703                 else {
5704                         if (is_10g_plus)
5705                                 mask = NIG_STATUS_XGXS0_LINK10G;
5706                         else if (params->switch_cfg == SWITCH_CFG_10G) {
5707                                 /*
5708                                  * Disable the link interrupt by writing 1 to
5709                                  * the relevant lane in the status register
5710                                  */
5711                                 u32 ser_lane =
5712                                         ((params->lane_config &
5713                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5714                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5715                                 mask = ((1 << ser_lane) <<
5716                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5717                         } else
5718                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5719                 }
5720                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5721                                mask);
5722                 bnx2x_bits_en(bp,
5723                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5724                               mask);
5725         }
5726 }
5727
5728 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5729 {
5730         u8 *str_ptr = str;
5731         u32 mask = 0xf0000000;
5732         u8 shift = 8*4;
5733         u8 digit;
5734         u8 remove_leading_zeros = 1;
5735         if (*len < 10) {
5736                 /* Need more than 10chars for this format */
5737                 *str_ptr = '\0';
5738                 (*len)--;
5739                 return -EINVAL;
5740         }
5741         while (shift > 0) {
5742
5743                 shift -= 4;
5744                 digit = ((num & mask) >> shift);
5745                 if (digit == 0 && remove_leading_zeros) {
5746                         mask = mask >> 4;
5747                         continue;
5748                 } else if (digit < 0xa)
5749                         *str_ptr = digit + '0';
5750                 else
5751                         *str_ptr = digit - 0xa + 'a';
5752                 remove_leading_zeros = 0;
5753                 str_ptr++;
5754                 (*len)--;
5755                 mask = mask >> 4;
5756                 if (shift == 4*4) {
5757                         *str_ptr = '.';
5758                         str_ptr++;
5759                         (*len)--;
5760                         remove_leading_zeros = 1;
5761                 }
5762         }
5763         return 0;
5764 }
5765
5766
5767 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5768 {
5769         str[0] = '\0';
5770         (*len)--;
5771         return 0;
5772 }
5773
5774 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5775                                  u8 *version, u16 len)
5776 {
5777         struct bnx2x *bp;
5778         u32 spirom_ver = 0;
5779         int status = 0;
5780         u8 *ver_p = version;
5781         u16 remain_len = len;
5782         if (version == NULL || params == NULL)
5783                 return -EINVAL;
5784         bp = params->bp;
5785
5786         /* Extract first external phy*/
5787         version[0] = '\0';
5788         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5789
5790         if (params->phy[EXT_PHY1].format_fw_ver) {
5791                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5792                                                               ver_p,
5793                                                               &remain_len);
5794                 ver_p += (len - remain_len);
5795         }
5796         if ((params->num_phys == MAX_PHYS) &&
5797             (params->phy[EXT_PHY2].ver_addr != 0)) {
5798                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5799                 if (params->phy[EXT_PHY2].format_fw_ver) {
5800                         *ver_p = '/';
5801                         ver_p++;
5802                         remain_len--;
5803                         status |= params->phy[EXT_PHY2].format_fw_ver(
5804                                 spirom_ver,
5805                                 ver_p,
5806                                 &remain_len);
5807                         ver_p = version + (len - remain_len);
5808                 }
5809         }
5810         *ver_p = '\0';
5811         return status;
5812 }
5813
5814 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5815                                     struct link_params *params)
5816 {
5817         u8 port = params->port;
5818         struct bnx2x *bp = params->bp;
5819
5820         if (phy->req_line_speed != SPEED_1000) {
5821                 u32 md_devad = 0;
5822
5823                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5824
5825                 if (!CHIP_IS_E3(bp)) {
5826                         /* change the uni_phy_addr in the nig */
5827                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5828                                                port*0x18));
5829
5830                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5831                                0x5);
5832                 }
5833
5834                 bnx2x_cl45_write(bp, phy,
5835                                  5,
5836                                  (MDIO_REG_BANK_AER_BLOCK +
5837                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
5838                                  0x2800);
5839
5840                 bnx2x_cl45_write(bp, phy,
5841                                  5,
5842                                  (MDIO_REG_BANK_CL73_IEEEB0 +
5843                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5844                                  0x6041);
5845                 msleep(200);
5846                 /* set aer mmd back */
5847                 bnx2x_set_aer_mmd(params, phy);
5848
5849                 if (!CHIP_IS_E3(bp)) {
5850                         /* and md_devad */
5851                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5852                                md_devad);
5853                 }
5854         } else {
5855                 u16 mii_ctrl;
5856                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5857                 bnx2x_cl45_read(bp, phy, 5,
5858                                 (MDIO_REG_BANK_COMBO_IEEE0 +
5859                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5860                                 &mii_ctrl);
5861                 bnx2x_cl45_write(bp, phy, 5,
5862                                  (MDIO_REG_BANK_COMBO_IEEE0 +
5863                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5864                                  mii_ctrl |
5865                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5866         }
5867 }
5868
5869 int bnx2x_set_led(struct link_params *params,
5870                   struct link_vars *vars, u8 mode, u32 speed)
5871 {
5872         u8 port = params->port;
5873         u16 hw_led_mode = params->hw_led_mode;
5874         int rc = 0;
5875         u8 phy_idx;
5876         u32 tmp;
5877         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5878         struct bnx2x *bp = params->bp;
5879         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5880         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5881                  speed, hw_led_mode);
5882         /* In case */
5883         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
5884                 if (params->phy[phy_idx].set_link_led) {
5885                         params->phy[phy_idx].set_link_led(
5886                                 &params->phy[phy_idx], params, mode);
5887                 }
5888         }
5889
5890         switch (mode) {
5891         case LED_MODE_FRONT_PANEL_OFF:
5892         case LED_MODE_OFF:
5893                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5894                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5895                        SHARED_HW_CFG_LED_MAC1);
5896
5897                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5898                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5899                 break;
5900
5901         case LED_MODE_OPER:
5902                 /*
5903                  * For all other phys, OPER mode is same as ON, so in case
5904                  * link is down, do nothing
5905                  */
5906                 if (!vars->link_up)
5907                         break;
5908         case LED_MODE_ON:
5909                 if (((params->phy[EXT_PHY1].type ==
5910                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
5911                          (params->phy[EXT_PHY1].type ==
5912                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
5913                     CHIP_IS_E2(bp) && params->num_phys == 2) {
5914                         /*
5915                          * This is a work-around for E2+8727 Configurations
5916                          */
5917                         if (mode == LED_MODE_ON ||
5918                                 speed == SPEED_10000){
5919                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5920                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5921
5922                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5923                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5924                                         (tmp | EMAC_LED_OVERRIDE));
5925                                 /*
5926                                  * return here without enabling traffic
5927                                  * LED blink and setting rate in ON mode.
5928                                  * In oper mode, enabling LED blink
5929                                  * and setting rate is needed.
5930                                  */
5931                                 if (mode == LED_MODE_ON)
5932                                         return rc;
5933                         }
5934                 } else if (SINGLE_MEDIA_DIRECT(params)) {
5935                         /*
5936                          * This is a work-around for HW issue found when link
5937                          * is up in CL73
5938                          */
5939                         if ((!CHIP_IS_E3(bp)) ||
5940                             (CHIP_IS_E3(bp) &&
5941                              mode == LED_MODE_ON))
5942                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5943
5944                         if (CHIP_IS_E1x(bp) ||
5945                             CHIP_IS_E2(bp) ||
5946                             (mode == LED_MODE_ON))
5947                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5948                         else
5949                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5950                                        hw_led_mode);
5951                 } else
5952                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5953
5954                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
5955                 /* Set blinking rate to ~15.9Hz */
5956                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5957                        LED_BLINK_RATE_VAL);
5958                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5959                        port*4, 1);
5960                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5961                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
5962
5963                 if (CHIP_IS_E1(bp) &&
5964                     ((speed == SPEED_2500) ||
5965                      (speed == SPEED_1000) ||
5966                      (speed == SPEED_100) ||
5967                      (speed == SPEED_10))) {
5968                         /*
5969                          * On Everest 1 Ax chip versions for speeds less than
5970                          * 10G LED scheme is different
5971                          */
5972                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5973                                + port*4, 1);
5974                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5975                                port*4, 0);
5976                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5977                                port*4, 1);
5978                 }
5979                 break;
5980
5981         default:
5982                 rc = -EINVAL;
5983                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5984                          mode);
5985                 break;
5986         }
5987         return rc;
5988
5989 }
5990
5991 /*
5992  * This function comes to reflect the actual link state read DIRECTLY from the
5993  * HW
5994  */
5995 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
5996                     u8 is_serdes)
5997 {
5998         struct bnx2x *bp = params->bp;
5999         u16 gp_status = 0, phy_index = 0;
6000         u8 ext_phy_link_up = 0, serdes_phy_type;
6001         struct link_vars temp_vars;
6002         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6003
6004         if (CHIP_IS_E3(bp)) {
6005                 u16 link_up;
6006                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6007                     > SPEED_10000) {
6008                         /* Check 20G link */
6009                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6010                                         1, &link_up);
6011                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6012                                         1, &link_up);
6013                         link_up &= (1<<2);
6014                 } else {
6015                         /* Check 10G link and below*/
6016                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6017                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6018                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6019                                         &gp_status);
6020                         gp_status = ((gp_status >> 8) & 0xf) |
6021                                 ((gp_status >> 12) & 0xf);
6022                         link_up = gp_status & (1 << lane);
6023                 }
6024                 if (!link_up)
6025                         return -ESRCH;
6026         } else {
6027                 CL22_RD_OVER_CL45(bp, int_phy,
6028                           MDIO_REG_BANK_GP_STATUS,
6029                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6030                           &gp_status);
6031         /* link is up only if both local phy and external phy are up */
6032         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6033                 return -ESRCH;
6034         }
6035         /* In XGXS loopback mode, do not check external PHY */
6036         if (params->loopback_mode == LOOPBACK_XGXS)
6037                 return 0;
6038
6039         switch (params->num_phys) {
6040         case 1:
6041                 /* No external PHY */
6042                 return 0;
6043         case 2:
6044                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6045                         &params->phy[EXT_PHY1],
6046                         params, &temp_vars);
6047                 break;
6048         case 3: /* Dual Media */
6049                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6050                       phy_index++) {
6051                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6052                                             ETH_PHY_SFP_FIBER) ||
6053                                            (params->phy[phy_index].media_type ==
6054                                             ETH_PHY_XFP_FIBER) ||
6055                                            (params->phy[phy_index].media_type ==
6056                                             ETH_PHY_DA_TWINAX));
6057
6058                         if (is_serdes != serdes_phy_type)
6059                                 continue;
6060                         if (params->phy[phy_index].read_status) {
6061                                 ext_phy_link_up |=
6062                                         params->phy[phy_index].read_status(
6063                                                 &params->phy[phy_index],
6064                                                 params, &temp_vars);
6065                         }
6066                 }
6067                 break;
6068         }
6069         if (ext_phy_link_up)
6070                 return 0;
6071         return -ESRCH;
6072 }
6073
6074 static int bnx2x_link_initialize(struct link_params *params,
6075                                  struct link_vars *vars)
6076 {
6077         int rc = 0;
6078         u8 phy_index, non_ext_phy;
6079         struct bnx2x *bp = params->bp;
6080         /*
6081          * In case of external phy existence, the line speed would be the
6082          * line speed linked up by the external phy. In case it is direct
6083          * only, then the line_speed during initialization will be
6084          * equal to the req_line_speed
6085          */
6086         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6087
6088         /*
6089          * Initialize the internal phy in case this is a direct board
6090          * (no external phys), or this board has external phy which requires
6091          * to first.
6092          */
6093         if (!USES_WARPCORE(bp))
6094                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6095         /* init ext phy and enable link state int */
6096         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6097                        (params->loopback_mode == LOOPBACK_XGXS));
6098
6099         if (non_ext_phy ||
6100             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6101             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6102                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6103                 if (vars->line_speed == SPEED_AUTO_NEG &&
6104                     (CHIP_IS_E1x(bp) ||
6105                      CHIP_IS_E2(bp)))
6106                         bnx2x_set_parallel_detection(phy, params);
6107                         if (params->phy[INT_PHY].config_init)
6108                                 params->phy[INT_PHY].config_init(phy,
6109                                                                  params,
6110                                                                  vars);
6111         }
6112
6113         /* Init external phy*/
6114         if (non_ext_phy) {
6115                 if (params->phy[INT_PHY].supported &
6116                     SUPPORTED_FIBRE)
6117                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6118         } else {
6119                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6120                       phy_index++) {
6121                         /*
6122                          * No need to initialize second phy in case of first
6123                          * phy only selection. In case of second phy, we do
6124                          * need to initialize the first phy, since they are
6125                          * connected.
6126                          */
6127                         if (params->phy[phy_index].supported &
6128                             SUPPORTED_FIBRE)
6129                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6130
6131                         if (phy_index == EXT_PHY2 &&
6132                             (bnx2x_phy_selection(params) ==
6133                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6134                                 DP(NETIF_MSG_LINK, "Not initializing"
6135                                                 " second phy\n");
6136                                 continue;
6137                         }
6138                         params->phy[phy_index].config_init(
6139                                 &params->phy[phy_index],
6140                                 params, vars);
6141                 }
6142         }
6143         /* Reset the interrupt indication after phy was initialized */
6144         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6145                        params->port*4,
6146                        (NIG_STATUS_XGXS0_LINK10G |
6147                         NIG_STATUS_XGXS0_LINK_STATUS |
6148                         NIG_STATUS_SERDES0_LINK_STATUS |
6149                         NIG_MASK_MI_INT));
6150         bnx2x_update_mng(params, vars->link_status);
6151         return rc;
6152 }
6153
6154 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6155                                  struct link_params *params)
6156 {
6157         /* reset the SerDes/XGXS */
6158         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6159                (0x1ff << (params->port*16)));
6160 }
6161
6162 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6163                                         struct link_params *params)
6164 {
6165         struct bnx2x *bp = params->bp;
6166         u8 gpio_port;
6167         /* HW reset */
6168         if (CHIP_IS_E2(bp))
6169                 gpio_port = BP_PATH(bp);
6170         else
6171                 gpio_port = params->port;
6172         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6173                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6174                        gpio_port);
6175         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6176                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6177                        gpio_port);
6178         DP(NETIF_MSG_LINK, "reset external PHY\n");
6179 }
6180
6181 static int bnx2x_update_link_down(struct link_params *params,
6182                                   struct link_vars *vars)
6183 {
6184         struct bnx2x *bp = params->bp;
6185         u8 port = params->port;
6186
6187         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6188         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6189         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6190         /* indicate no mac active */
6191         vars->mac_type = MAC_TYPE_NONE;
6192
6193         /* update shared memory */
6194         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6195                                LINK_STATUS_LINK_UP |
6196                                LINK_STATUS_PHYSICAL_LINK_FLAG |
6197                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6198                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6199                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6200                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6201         vars->line_speed = 0;
6202         bnx2x_update_mng(params, vars->link_status);
6203
6204         /* activate nig drain */
6205         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6206
6207         /* disable emac */
6208         if (!CHIP_IS_E3(bp))
6209                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6210
6211         msleep(10);
6212         /* reset BigMac/Xmac */
6213         if (CHIP_IS_E1x(bp) ||
6214             CHIP_IS_E2(bp)) {
6215                 bnx2x_bmac_rx_disable(bp, params->port);
6216                 REG_WR(bp, GRCBASE_MISC +
6217                        MISC_REGISTERS_RESET_REG_2_CLEAR,
6218                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6219         }
6220         if (CHIP_IS_E3(bp))
6221                 bnx2x_xmac_disable(params);
6222
6223         return 0;
6224 }
6225
6226 static int bnx2x_update_link_up(struct link_params *params,
6227                                 struct link_vars *vars,
6228                                 u8 link_10g)
6229 {
6230         struct bnx2x *bp = params->bp;
6231         u8 port = params->port;
6232         int rc = 0;
6233
6234         vars->link_status |= (LINK_STATUS_LINK_UP |
6235                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6236         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6237
6238         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6239                 vars->link_status |=
6240                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6241
6242         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6243                 vars->link_status |=
6244                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6245         if (USES_WARPCORE(bp)) {
6246                 if (link_10g) {
6247                         if (bnx2x_xmac_enable(params, vars, 0) ==
6248                             -ESRCH) {
6249                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6250                                 vars->link_up = 0;
6251                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6252                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6253                         }
6254                 } else
6255                         bnx2x_umac_enable(params, vars, 0);
6256                 bnx2x_set_led(params, vars,
6257                               LED_MODE_OPER, vars->line_speed);
6258         }
6259         if ((CHIP_IS_E1x(bp) ||
6260              CHIP_IS_E2(bp))) {
6261                 if (link_10g) {
6262                         if (bnx2x_bmac_enable(params, vars, 0) ==
6263                             -ESRCH) {
6264                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6265                                 vars->link_up = 0;
6266                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6267                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6268                         }
6269
6270                         bnx2x_set_led(params, vars,
6271                                       LED_MODE_OPER, SPEED_10000);
6272                 } else {
6273                         rc = bnx2x_emac_program(params, vars);
6274                         bnx2x_emac_enable(params, vars, 0);
6275
6276                         /* AN complete? */
6277                         if ((vars->link_status &
6278                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6279                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6280                             SINGLE_MEDIA_DIRECT(params))
6281                                 bnx2x_set_gmii_tx_driver(params);
6282                 }
6283         }
6284
6285         /* PBF - link up */
6286         if (CHIP_IS_E1x(bp))
6287                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6288                                        vars->line_speed);
6289
6290         /* disable drain */
6291         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6292
6293         /* update shared memory */
6294         bnx2x_update_mng(params, vars->link_status);
6295         msleep(20);
6296         return rc;
6297 }
6298 /*
6299  * The bnx2x_link_update function should be called upon link
6300  * interrupt.
6301  * Link is considered up as follows:
6302  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6303  *   to be up
6304  * - SINGLE_MEDIA - The link between the 577xx and the external
6305  *   phy (XGXS) need to up as well as the external link of the
6306  *   phy (PHY_EXT1)
6307  * - DUAL_MEDIA - The link between the 577xx and the first
6308  *   external phy needs to be up, and at least one of the 2
6309  *   external phy link must be up.
6310  */
6311 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6312 {
6313         struct bnx2x *bp = params->bp;
6314         struct link_vars phy_vars[MAX_PHYS];
6315         u8 port = params->port;
6316         u8 link_10g_plus, phy_index;
6317         u8 ext_phy_link_up = 0, cur_link_up;
6318         int rc = 0;
6319         u8 is_mi_int = 0;
6320         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6321         u8 active_external_phy = INT_PHY;
6322         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6323         for (phy_index = INT_PHY; phy_index < params->num_phys;
6324               phy_index++) {
6325                 phy_vars[phy_index].flow_ctrl = 0;
6326                 phy_vars[phy_index].link_status = 0;
6327                 phy_vars[phy_index].line_speed = 0;
6328                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6329                 phy_vars[phy_index].phy_link_up = 0;
6330                 phy_vars[phy_index].link_up = 0;
6331                 phy_vars[phy_index].fault_detected = 0;
6332         }
6333
6334         if (USES_WARPCORE(bp))
6335                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6336
6337         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6338                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6339                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6340
6341         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6342                                 port*0x18) > 0);
6343         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6344                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6345                  is_mi_int,
6346                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6347
6348         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6349           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6350           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6351
6352         /* disable emac */
6353         if (!CHIP_IS_E3(bp))
6354                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6355
6356         /*
6357          * Step 1:
6358          * Check external link change only for external phys, and apply
6359          * priority selection between them in case the link on both phys
6360          * is up. Note that instead of the common vars, a temporary
6361          * vars argument is used since each phy may have different link/
6362          * speed/duplex result
6363          */
6364         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6365               phy_index++) {
6366                 struct bnx2x_phy *phy = &params->phy[phy_index];
6367                 if (!phy->read_status)
6368                         continue;
6369                 /* Read link status and params of this ext phy */
6370                 cur_link_up = phy->read_status(phy, params,
6371                                                &phy_vars[phy_index]);
6372                 if (cur_link_up) {
6373                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6374                                    phy_index);
6375                 } else {
6376                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6377                                    phy_index);
6378                         continue;
6379                 }
6380
6381                 if (!ext_phy_link_up) {
6382                         ext_phy_link_up = 1;
6383                         active_external_phy = phy_index;
6384                 } else {
6385                         switch (bnx2x_phy_selection(params)) {
6386                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6387                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6388                         /*
6389                          * In this option, the first PHY makes sure to pass the
6390                          * traffic through itself only.
6391                          * Its not clear how to reset the link on the second phy
6392                          */
6393                                 active_external_phy = EXT_PHY1;
6394                                 break;
6395                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6396                         /*
6397                          * In this option, the first PHY makes sure to pass the
6398                          * traffic through the second PHY.
6399                          */
6400                                 active_external_phy = EXT_PHY2;
6401                                 break;
6402                         default:
6403                         /*
6404                          * Link indication on both PHYs with the following cases
6405                          * is invalid:
6406                          * - FIRST_PHY means that second phy wasn't initialized,
6407                          * hence its link is expected to be down
6408                          * - SECOND_PHY means that first phy should not be able
6409                          * to link up by itself (using configuration)
6410                          * - DEFAULT should be overriden during initialiazation
6411                          */
6412                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6413                                            "mpc=0x%x. DISABLING LINK !!!\n",
6414                                            params->multi_phy_config);
6415                                 ext_phy_link_up = 0;
6416                                 break;
6417                         }
6418                 }
6419         }
6420         prev_line_speed = vars->line_speed;
6421         /*
6422          * Step 2:
6423          * Read the status of the internal phy. In case of
6424          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6425          * otherwise this is the link between the 577xx and the first
6426          * external phy
6427          */
6428         if (params->phy[INT_PHY].read_status)
6429                 params->phy[INT_PHY].read_status(
6430                         &params->phy[INT_PHY],
6431                         params, vars);
6432         /*
6433          * The INT_PHY flow control reside in the vars. This include the
6434          * case where the speed or flow control are not set to AUTO.
6435          * Otherwise, the active external phy flow control result is set
6436          * to the vars. The ext_phy_line_speed is needed to check if the
6437          * speed is different between the internal phy and external phy.
6438          * This case may be result of intermediate link speed change.
6439          */
6440         if (active_external_phy > INT_PHY) {
6441                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6442                 /*
6443                  * Link speed is taken from the XGXS. AN and FC result from
6444                  * the external phy.
6445                  */
6446                 vars->link_status |= phy_vars[active_external_phy].link_status;
6447
6448                 /*
6449                  * if active_external_phy is first PHY and link is up - disable
6450                  * disable TX on second external PHY
6451                  */
6452                 if (active_external_phy == EXT_PHY1) {
6453                         if (params->phy[EXT_PHY2].phy_specific_func) {
6454                                 DP(NETIF_MSG_LINK, "Disabling TX on"
6455                                                    " EXT_PHY2\n");
6456                                 params->phy[EXT_PHY2].phy_specific_func(
6457                                         &params->phy[EXT_PHY2],
6458                                         params, DISABLE_TX);
6459                         }
6460                 }
6461
6462                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6463                 vars->duplex = phy_vars[active_external_phy].duplex;
6464                 if (params->phy[active_external_phy].supported &
6465                     SUPPORTED_FIBRE)
6466                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6467                 else
6468                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6469                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6470                            active_external_phy);
6471         }
6472
6473         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6474               phy_index++) {
6475                 if (params->phy[phy_index].flags &
6476                     FLAGS_REARM_LATCH_SIGNAL) {
6477                         bnx2x_rearm_latch_signal(bp, port,
6478                                                  phy_index ==
6479                                                  active_external_phy);
6480                         break;
6481                 }
6482         }
6483         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6484                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6485                    vars->link_status, ext_phy_line_speed);
6486         /*
6487          * Upon link speed change set the NIG into drain mode. Comes to
6488          * deals with possible FIFO glitch due to clk change when speed
6489          * is decreased without link down indicator
6490          */
6491
6492         if (vars->phy_link_up) {
6493                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6494                     (ext_phy_line_speed != vars->line_speed)) {
6495                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6496                                    " different than the external"
6497                                    " link speed %d\n", vars->line_speed,
6498                                    ext_phy_line_speed);
6499                         vars->phy_link_up = 0;
6500                 } else if (prev_line_speed != vars->line_speed) {
6501                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6502                                0);
6503                         msleep(1);
6504                 }
6505         }
6506
6507         /* anything 10 and over uses the bmac */
6508         link_10g_plus = (vars->line_speed >= SPEED_10000);
6509
6510         bnx2x_link_int_ack(params, vars, link_10g_plus);
6511
6512         /*
6513          * In case external phy link is up, and internal link is down
6514          * (not initialized yet probably after link initialization, it
6515          * needs to be initialized.
6516          * Note that after link down-up as result of cable plug, the xgxs
6517          * link would probably become up again without the need
6518          * initialize it
6519          */
6520         if (!(SINGLE_MEDIA_DIRECT(params))) {
6521                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6522                            " init_preceding = %d\n", ext_phy_link_up,
6523                            vars->phy_link_up,
6524                            params->phy[EXT_PHY1].flags &
6525                            FLAGS_INIT_XGXS_FIRST);
6526                 if (!(params->phy[EXT_PHY1].flags &
6527                       FLAGS_INIT_XGXS_FIRST)
6528                     && ext_phy_link_up && !vars->phy_link_up) {
6529                         vars->line_speed = ext_phy_line_speed;
6530                         if (vars->line_speed < SPEED_1000)
6531                                 vars->phy_flags |= PHY_SGMII_FLAG;
6532                         else
6533                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6534
6535                         if (params->phy[INT_PHY].config_init)
6536                                 params->phy[INT_PHY].config_init(
6537                                         &params->phy[INT_PHY], params,
6538                                                 vars);
6539                 }
6540         }
6541         /*
6542          * Link is up only if both local phy and external phy (in case of
6543          * non-direct board) are up and no fault detected on active PHY.
6544          */
6545         vars->link_up = (vars->phy_link_up &&
6546                          (ext_phy_link_up ||
6547                           SINGLE_MEDIA_DIRECT(params)) &&
6548                          (phy_vars[active_external_phy].fault_detected == 0));
6549
6550         if (vars->link_up)
6551                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6552         else
6553                 rc = bnx2x_update_link_down(params, vars);
6554
6555         return rc;
6556 }
6557
6558
6559 /*****************************************************************************/
6560 /*                          External Phy section                             */
6561 /*****************************************************************************/
6562 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6563 {
6564         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6565                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6566         msleep(1);
6567         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6568                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6569 }
6570
6571 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6572                                       u32 spirom_ver, u32 ver_addr)
6573 {
6574         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6575                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6576
6577         if (ver_addr)
6578                 REG_WR(bp, ver_addr, spirom_ver);
6579 }
6580
6581 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6582                                       struct bnx2x_phy *phy,
6583                                       u8 port)
6584 {
6585         u16 fw_ver1, fw_ver2;
6586
6587         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6588                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6589         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6590                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6591         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6592                                   phy->ver_addr);
6593 }
6594
6595 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6596                                        struct bnx2x_phy *phy,
6597                                        struct link_vars *vars)
6598 {
6599         u16 val;
6600         bnx2x_cl45_read(bp, phy,
6601                         MDIO_AN_DEVAD,
6602                         MDIO_AN_REG_STATUS, &val);
6603         bnx2x_cl45_read(bp, phy,
6604                         MDIO_AN_DEVAD,
6605                         MDIO_AN_REG_STATUS, &val);
6606         if (val & (1<<5))
6607                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6608         if ((val & (1<<0)) == 0)
6609                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6610 }
6611
6612 /******************************************************************/
6613 /*              common BCM8073/BCM8727 PHY SECTION                */
6614 /******************************************************************/
6615 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6616                                   struct link_params *params,
6617                                   struct link_vars *vars)
6618 {
6619         struct bnx2x *bp = params->bp;
6620         if (phy->req_line_speed == SPEED_10 ||
6621             phy->req_line_speed == SPEED_100) {
6622                 vars->flow_ctrl = phy->req_flow_ctrl;
6623                 return;
6624         }
6625
6626         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6627             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6628                 u16 pause_result;
6629                 u16 ld_pause;           /* local */
6630                 u16 lp_pause;           /* link partner */
6631                 bnx2x_cl45_read(bp, phy,
6632                                 MDIO_AN_DEVAD,
6633                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6634
6635                 bnx2x_cl45_read(bp, phy,
6636                                 MDIO_AN_DEVAD,
6637                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6638                 pause_result = (ld_pause &
6639                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6640                 pause_result |= (lp_pause &
6641                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6642
6643                 bnx2x_pause_resolve(vars, pause_result);
6644                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6645                            pause_result);
6646         }
6647 }
6648 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6649                                              struct bnx2x_phy *phy,
6650                                              u8 port)
6651 {
6652         u32 count = 0;
6653         u16 fw_ver1, fw_msgout;
6654         int rc = 0;
6655
6656         /* Boot port from external ROM  */
6657         /* EDC grst */
6658         bnx2x_cl45_write(bp, phy,
6659                          MDIO_PMA_DEVAD,
6660                          MDIO_PMA_REG_GEN_CTRL,
6661                          0x0001);
6662
6663         /* ucode reboot and rst */
6664         bnx2x_cl45_write(bp, phy,
6665                          MDIO_PMA_DEVAD,
6666                          MDIO_PMA_REG_GEN_CTRL,
6667                          0x008c);
6668
6669         bnx2x_cl45_write(bp, phy,
6670                          MDIO_PMA_DEVAD,
6671                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6672
6673         /* Reset internal microprocessor */
6674         bnx2x_cl45_write(bp, phy,
6675                          MDIO_PMA_DEVAD,
6676                          MDIO_PMA_REG_GEN_CTRL,
6677                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6678
6679         /* Release srst bit */
6680         bnx2x_cl45_write(bp, phy,
6681                          MDIO_PMA_DEVAD,
6682                          MDIO_PMA_REG_GEN_CTRL,
6683                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6684
6685         /* Delay 100ms per the PHY specifications */
6686         msleep(100);
6687
6688         /* 8073 sometimes taking longer to download */
6689         do {
6690                 count++;
6691                 if (count > 300) {
6692                         DP(NETIF_MSG_LINK,
6693                                  "bnx2x_8073_8727_external_rom_boot port %x:"
6694                                  "Download failed. fw version = 0x%x\n",
6695                                  port, fw_ver1);
6696                         rc = -EINVAL;
6697                         break;
6698                 }
6699
6700                 bnx2x_cl45_read(bp, phy,
6701                                 MDIO_PMA_DEVAD,
6702                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6703                 bnx2x_cl45_read(bp, phy,
6704                                 MDIO_PMA_DEVAD,
6705                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6706
6707                 msleep(1);
6708         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6709                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6710                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6711
6712         /* Clear ser_boot_ctl bit */
6713         bnx2x_cl45_write(bp, phy,
6714                          MDIO_PMA_DEVAD,
6715                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6716         bnx2x_save_bcm_spirom_ver(bp, phy, port);
6717
6718         DP(NETIF_MSG_LINK,
6719                  "bnx2x_8073_8727_external_rom_boot port %x:"
6720                  "Download complete. fw version = 0x%x\n",
6721                  port, fw_ver1);
6722
6723         return rc;
6724 }
6725
6726 /******************************************************************/
6727 /*                      BCM8073 PHY SECTION                       */
6728 /******************************************************************/
6729 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6730 {
6731         /* This is only required for 8073A1, version 102 only */
6732         u16 val;
6733
6734         /* Read 8073 HW revision*/
6735         bnx2x_cl45_read(bp, phy,
6736                         MDIO_PMA_DEVAD,
6737                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6738
6739         if (val != 1) {
6740                 /* No need to workaround in 8073 A1 */
6741                 return 0;
6742         }
6743
6744         bnx2x_cl45_read(bp, phy,
6745                         MDIO_PMA_DEVAD,
6746                         MDIO_PMA_REG_ROM_VER2, &val);
6747
6748         /* SNR should be applied only for version 0x102 */
6749         if (val != 0x102)
6750                 return 0;
6751
6752         return 1;
6753 }
6754
6755 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6756 {
6757         u16 val, cnt, cnt1 ;
6758
6759         bnx2x_cl45_read(bp, phy,
6760                         MDIO_PMA_DEVAD,
6761                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6762
6763         if (val > 0) {
6764                 /* No need to workaround in 8073 A1 */
6765                 return 0;
6766         }
6767         /* XAUI workaround in 8073 A0: */
6768
6769         /*
6770          * After loading the boot ROM and restarting Autoneg, poll
6771          * Dev1, Reg $C820:
6772          */
6773
6774         for (cnt = 0; cnt < 1000; cnt++) {
6775                 bnx2x_cl45_read(bp, phy,
6776                                 MDIO_PMA_DEVAD,
6777                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
6778                                 &val);
6779                   /*
6780                    * If bit [14] = 0 or bit [13] = 0, continue on with
6781                    * system initialization (XAUI work-around not required, as
6782                    * these bits indicate 2.5G or 1G link up).
6783                    */
6784                 if (!(val & (1<<14)) || !(val & (1<<13))) {
6785                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
6786                         return 0;
6787                 } else if (!(val & (1<<15))) {
6788                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
6789                         /*
6790                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6791                          * MSB (bit15) goes to 1 (indicating that the XAUI
6792                          * workaround has completed), then continue on with
6793                          * system initialization.
6794                          */
6795                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6796                                 bnx2x_cl45_read(bp, phy,
6797                                         MDIO_PMA_DEVAD,
6798                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
6799                                 if (val & (1<<15)) {
6800                                         DP(NETIF_MSG_LINK,
6801                                           "XAUI workaround has completed\n");
6802                                         return 0;
6803                                  }
6804                                  msleep(3);
6805                         }
6806                         break;
6807                 }
6808                 msleep(3);
6809         }
6810         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
6811         return -EINVAL;
6812 }
6813
6814 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6815 {
6816         /* Force KR or KX */
6817         bnx2x_cl45_write(bp, phy,
6818                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6819         bnx2x_cl45_write(bp, phy,
6820                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6821         bnx2x_cl45_write(bp, phy,
6822                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
6823         bnx2x_cl45_write(bp, phy,
6824                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6825 }
6826
6827 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
6828                                       struct bnx2x_phy *phy,
6829                                       struct link_vars *vars)
6830 {
6831         u16 cl37_val;
6832         struct bnx2x *bp = params->bp;
6833         bnx2x_cl45_read(bp, phy,
6834                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6835
6836         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6837         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6838         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6839         if ((vars->ieee_fc &
6840             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6841             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6842                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6843         }
6844         if ((vars->ieee_fc &
6845             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6846             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6847                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6848         }
6849         if ((vars->ieee_fc &
6850             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6851             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6852                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6853         }
6854         DP(NETIF_MSG_LINK,
6855                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
6856
6857         bnx2x_cl45_write(bp, phy,
6858                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6859         msleep(500);
6860 }
6861
6862 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
6863                                   struct link_params *params,
6864                                   struct link_vars *vars)
6865 {
6866         struct bnx2x *bp = params->bp;
6867         u16 val = 0, tmp1;
6868         u8 gpio_port;
6869         DP(NETIF_MSG_LINK, "Init 8073\n");
6870
6871         if (CHIP_IS_E2(bp))
6872                 gpio_port = BP_PATH(bp);
6873         else
6874                 gpio_port = params->port;
6875         /* Restore normal power mode*/
6876         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6877                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6878
6879         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6880                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6881
6882         /* enable LASI */
6883         bnx2x_cl45_write(bp, phy,
6884                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
6885         bnx2x_cl45_write(bp, phy,
6886                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
6887
6888         bnx2x_8073_set_pause_cl37(params, phy, vars);
6889
6890         bnx2x_cl45_read(bp, phy,
6891                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6892
6893         bnx2x_cl45_read(bp, phy,
6894                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6895
6896         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
6897
6898         /* Swap polarity if required - Must be done only in non-1G mode */
6899         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6900                 /* Configure the 8073 to swap _P and _N of the KR lines */
6901                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
6902                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6903                 bnx2x_cl45_read(bp, phy,
6904                                 MDIO_PMA_DEVAD,
6905                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6906                 bnx2x_cl45_write(bp, phy,
6907                                  MDIO_PMA_DEVAD,
6908                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6909                                  (val | (3<<9)));
6910         }
6911
6912
6913         /* Enable CL37 BAM */
6914         if (REG_RD(bp, params->shmem_base +
6915                          offsetof(struct shmem_region, dev_info.
6916                                   port_hw_config[params->port].default_cfg)) &
6917             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6918
6919                 bnx2x_cl45_read(bp, phy,
6920                                 MDIO_AN_DEVAD,
6921                                 MDIO_AN_REG_8073_BAM, &val);
6922                 bnx2x_cl45_write(bp, phy,
6923                                  MDIO_AN_DEVAD,
6924                                  MDIO_AN_REG_8073_BAM, val | 1);
6925                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
6926         }
6927         if (params->loopback_mode == LOOPBACK_EXT) {
6928                 bnx2x_807x_force_10G(bp, phy);
6929                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
6930                 return 0;
6931         } else {
6932                 bnx2x_cl45_write(bp, phy,
6933                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
6934         }
6935         if (phy->req_line_speed != SPEED_AUTO_NEG) {
6936                 if (phy->req_line_speed == SPEED_10000) {
6937                         val = (1<<7);
6938                 } else if (phy->req_line_speed ==  SPEED_2500) {
6939                         val = (1<<5);
6940                         /*
6941                          * Note that 2.5G works only when used with 1G
6942                          * advertisement
6943                          */
6944                 } else
6945                         val = (1<<5);
6946         } else {
6947                 val = 0;
6948                 if (phy->speed_cap_mask &
6949                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6950                         val |= (1<<7);
6951
6952                 /* Note that 2.5G works only when used with 1G advertisement */
6953                 if (phy->speed_cap_mask &
6954                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6955                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6956                         val |= (1<<5);
6957                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
6958         }
6959
6960         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6961         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6962
6963         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6964              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
6965             (phy->req_line_speed == SPEED_2500)) {
6966                 u16 phy_ver;
6967                 /* Allow 2.5G for A1 and above */
6968                 bnx2x_cl45_read(bp, phy,
6969                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6970                                 &phy_ver);
6971                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
6972                 if (phy_ver > 0)
6973                         tmp1 |= 1;
6974                 else
6975                         tmp1 &= 0xfffe;
6976         } else {
6977                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
6978                 tmp1 &= 0xfffe;
6979         }
6980
6981         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6982         /* Add support for CL37 (passive mode) II */
6983
6984         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6985         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6986                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6987                                   0x20 : 0x40)));
6988
6989         /* Add support for CL37 (passive mode) III */
6990         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6991
6992         /*
6993          * The SNR will improve about 2db by changing BW and FEE main
6994          * tap. Rest commands are executed after link is up
6995          * Change FFE main cursor to 5 in EDC register
6996          */
6997         if (bnx2x_8073_is_snr_needed(bp, phy))
6998                 bnx2x_cl45_write(bp, phy,
6999                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7000                                  0xFB0C);
7001
7002         /* Enable FEC (Forware Error Correction) Request in the AN */
7003         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7004         tmp1 |= (1<<15);
7005         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7006
7007         bnx2x_ext_phy_set_pause(params, phy, vars);
7008
7009         /* Restart autoneg */
7010         msleep(500);
7011         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7012         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7013                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7014         return 0;
7015 }
7016
7017 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7018                                  struct link_params *params,
7019                                  struct link_vars *vars)
7020 {
7021         struct bnx2x *bp = params->bp;
7022         u8 link_up = 0;
7023         u16 val1, val2;
7024         u16 link_status = 0;
7025         u16 an1000_status = 0;
7026
7027         bnx2x_cl45_read(bp, phy,
7028                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7029
7030         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7031
7032         /* clear the interrupt LASI status register */
7033         bnx2x_cl45_read(bp, phy,
7034                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7035         bnx2x_cl45_read(bp, phy,
7036                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7037         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7038         /* Clear MSG-OUT */
7039         bnx2x_cl45_read(bp, phy,
7040                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7041
7042         /* Check the LASI */
7043         bnx2x_cl45_read(bp, phy,
7044                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7045
7046         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7047
7048         /* Check the link status */
7049         bnx2x_cl45_read(bp, phy,
7050                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7051         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7052
7053         bnx2x_cl45_read(bp, phy,
7054                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7055         bnx2x_cl45_read(bp, phy,
7056                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7057         link_up = ((val1 & 4) == 4);
7058         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7059
7060         if (link_up &&
7061              ((phy->req_line_speed != SPEED_10000))) {
7062                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7063                         return 0;
7064         }
7065         bnx2x_cl45_read(bp, phy,
7066                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7067         bnx2x_cl45_read(bp, phy,
7068                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7069
7070         /* Check the link status on 1.1.2 */
7071         bnx2x_cl45_read(bp, phy,
7072                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7073         bnx2x_cl45_read(bp, phy,
7074                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7075         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7076                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7077
7078         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7079         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7080                 /*
7081                  * The SNR will improve about 2dbby changing the BW and FEE main
7082                  * tap. The 1st write to change FFE main tap is set before
7083                  * restart AN. Change PLL Bandwidth in EDC register
7084                  */
7085                 bnx2x_cl45_write(bp, phy,
7086                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7087                                  0x26BC);
7088
7089                 /* Change CDR Bandwidth in EDC register */
7090                 bnx2x_cl45_write(bp, phy,
7091                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7092                                  0x0333);
7093         }
7094         bnx2x_cl45_read(bp, phy,
7095                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7096                         &link_status);
7097
7098         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7099         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7100                 link_up = 1;
7101                 vars->line_speed = SPEED_10000;
7102                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7103                            params->port);
7104         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7105                 link_up = 1;
7106                 vars->line_speed = SPEED_2500;
7107                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7108                            params->port);
7109         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7110                 link_up = 1;
7111                 vars->line_speed = SPEED_1000;
7112                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7113                            params->port);
7114         } else {
7115                 link_up = 0;
7116                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7117                            params->port);
7118         }
7119
7120         if (link_up) {
7121                 /* Swap polarity if required */
7122                 if (params->lane_config &
7123                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7124                         /* Configure the 8073 to swap P and N of the KR lines */
7125                         bnx2x_cl45_read(bp, phy,
7126                                         MDIO_XS_DEVAD,
7127                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7128                         /*
7129                          * Set bit 3 to invert Rx in 1G mode and clear this bit
7130                          * when it`s in 10G mode.
7131                          */
7132                         if (vars->line_speed == SPEED_1000) {
7133                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7134                                               "the 8073\n");
7135                                 val1 |= (1<<3);
7136                         } else
7137                                 val1 &= ~(1<<3);
7138
7139                         bnx2x_cl45_write(bp, phy,
7140                                          MDIO_XS_DEVAD,
7141                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7142                                          val1);
7143                 }
7144                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7145                 bnx2x_8073_resolve_fc(phy, params, vars);
7146                 vars->duplex = DUPLEX_FULL;
7147         }
7148         return link_up;
7149 }
7150
7151 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7152                                   struct link_params *params)
7153 {
7154         struct bnx2x *bp = params->bp;
7155         u8 gpio_port;
7156         if (CHIP_IS_E2(bp))
7157                 gpio_port = BP_PATH(bp);
7158         else
7159                 gpio_port = params->port;
7160         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7161            gpio_port);
7162         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7163                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7164                        gpio_port);
7165 }
7166
7167 /******************************************************************/
7168 /*                      BCM8705 PHY SECTION                       */
7169 /******************************************************************/
7170 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7171                                   struct link_params *params,
7172                                   struct link_vars *vars)
7173 {
7174         struct bnx2x *bp = params->bp;
7175         DP(NETIF_MSG_LINK, "init 8705\n");
7176         /* Restore normal power mode*/
7177         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7178                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7179         /* HW reset */
7180         bnx2x_ext_phy_hw_reset(bp, params->port);
7181         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7182         bnx2x_wait_reset_complete(bp, phy, params);
7183
7184         bnx2x_cl45_write(bp, phy,
7185                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7186         bnx2x_cl45_write(bp, phy,
7187                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7188         bnx2x_cl45_write(bp, phy,
7189                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7190         bnx2x_cl45_write(bp, phy,
7191                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7192         /* BCM8705 doesn't have microcode, hence the 0 */
7193         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7194         return 0;
7195 }
7196
7197 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7198                                  struct link_params *params,
7199                                  struct link_vars *vars)
7200 {
7201         u8 link_up = 0;
7202         u16 val1, rx_sd;
7203         struct bnx2x *bp = params->bp;
7204         DP(NETIF_MSG_LINK, "read status 8705\n");
7205         bnx2x_cl45_read(bp, phy,
7206                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7207         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7208
7209         bnx2x_cl45_read(bp, phy,
7210                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7211         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7212
7213         bnx2x_cl45_read(bp, phy,
7214                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7215
7216         bnx2x_cl45_read(bp, phy,
7217                       MDIO_PMA_DEVAD, 0xc809, &val1);
7218         bnx2x_cl45_read(bp, phy,
7219                       MDIO_PMA_DEVAD, 0xc809, &val1);
7220
7221         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7222         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7223         if (link_up) {
7224                 vars->line_speed = SPEED_10000;
7225                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7226         }
7227         return link_up;
7228 }
7229
7230 /******************************************************************/
7231 /*                      SFP+ module Section                       */
7232 /******************************************************************/
7233 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7234                                            struct bnx2x_phy *phy,
7235                                            u8 pmd_dis)
7236 {
7237         struct bnx2x *bp = params->bp;
7238         /*
7239          * Disable transmitter only for bootcodes which can enable it afterwards
7240          * (for D3 link)
7241          */
7242         if (pmd_dis) {
7243                 if (params->feature_config_flags &
7244                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7245                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7246                 else {
7247                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7248                         return;
7249                 }
7250         } else
7251                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7252         bnx2x_cl45_write(bp, phy,
7253                          MDIO_PMA_DEVAD,
7254                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7255 }
7256
7257 static u8 bnx2x_get_gpio_port(struct link_params *params)
7258 {
7259         u8 gpio_port;
7260         u32 swap_val, swap_override;
7261         struct bnx2x *bp = params->bp;
7262         if (CHIP_IS_E2(bp))
7263                 gpio_port = BP_PATH(bp);
7264         else
7265                 gpio_port = params->port;
7266         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7267         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7268         return gpio_port ^ (swap_val && swap_override);
7269 }
7270
7271 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7272                                            struct bnx2x_phy *phy,
7273                                            u8 tx_en)
7274 {
7275         u16 val;
7276         u8 port = params->port;
7277         struct bnx2x *bp = params->bp;
7278         u32 tx_en_mode;
7279
7280         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7281         tx_en_mode = REG_RD(bp, params->shmem_base +
7282                             offsetof(struct shmem_region,
7283                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7284                 PORT_HW_CFG_TX_LASER_MASK;
7285         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7286                            "mode = %x\n", tx_en, port, tx_en_mode);
7287         switch (tx_en_mode) {
7288         case PORT_HW_CFG_TX_LASER_MDIO:
7289
7290                 bnx2x_cl45_read(bp, phy,
7291                                 MDIO_PMA_DEVAD,
7292                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7293                                 &val);
7294
7295                 if (tx_en)
7296                         val &= ~(1<<15);
7297                 else
7298                         val |= (1<<15);
7299
7300                 bnx2x_cl45_write(bp, phy,
7301                                  MDIO_PMA_DEVAD,
7302                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7303                                  val);
7304         break;
7305         case PORT_HW_CFG_TX_LASER_GPIO0:
7306         case PORT_HW_CFG_TX_LASER_GPIO1:
7307         case PORT_HW_CFG_TX_LASER_GPIO2:
7308         case PORT_HW_CFG_TX_LASER_GPIO3:
7309         {
7310                 u16 gpio_pin;
7311                 u8 gpio_port, gpio_mode;
7312                 if (tx_en)
7313                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7314                 else
7315                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7316
7317                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7318                 gpio_port = bnx2x_get_gpio_port(params);
7319                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7320                 break;
7321         }
7322         default:
7323                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7324                 break;
7325         }
7326 }
7327
7328 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7329                                       struct bnx2x_phy *phy,
7330                                       u8 tx_en)
7331 {
7332         struct bnx2x *bp = params->bp;
7333         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7334         if (CHIP_IS_E3(bp))
7335                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7336         else
7337                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7338 }
7339
7340 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7341                                              struct link_params *params,
7342                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7343 {
7344         struct bnx2x *bp = params->bp;
7345         u16 val = 0;
7346         u16 i;
7347         if (byte_cnt > 16) {
7348                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7349                             " is limited to 0xf\n");
7350                 return -EINVAL;
7351         }
7352         /* Set the read command byte count */
7353         bnx2x_cl45_write(bp, phy,
7354                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7355                          (byte_cnt | 0xa000));
7356
7357         /* Set the read command address */
7358         bnx2x_cl45_write(bp, phy,
7359                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7360                          addr);
7361
7362         /* Activate read command */
7363         bnx2x_cl45_write(bp, phy,
7364                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7365                          0x2c0f);
7366
7367         /* Wait up to 500us for command complete status */
7368         for (i = 0; i < 100; i++) {
7369                 bnx2x_cl45_read(bp, phy,
7370                                 MDIO_PMA_DEVAD,
7371                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7372                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7373                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7374                         break;
7375                 udelay(5);
7376         }
7377
7378         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7379                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7380                 DP(NETIF_MSG_LINK,
7381                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7382                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7383                 return -EINVAL;
7384         }
7385
7386         /* Read the buffer */
7387         for (i = 0; i < byte_cnt; i++) {
7388                 bnx2x_cl45_read(bp, phy,
7389                                 MDIO_PMA_DEVAD,
7390                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7391                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7392         }
7393
7394         for (i = 0; i < 100; i++) {
7395                 bnx2x_cl45_read(bp, phy,
7396                                 MDIO_PMA_DEVAD,
7397                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7398                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7399                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7400                         return 0;
7401                 msleep(1);
7402         }
7403         return -EINVAL;
7404 }
7405
7406 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7407                                                  struct link_params *params,
7408                                                  u16 addr, u8 byte_cnt,
7409                                                  u8 *o_buf)
7410 {
7411         int rc = 0;
7412         u8 i, j = 0, cnt = 0;
7413         u32 data_array[4];
7414         u16 addr32;
7415         struct bnx2x *bp = params->bp;
7416         /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7417                                         " addr %d, cnt %d\n",
7418                                         addr, byte_cnt);*/
7419         if (byte_cnt > 16) {
7420                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7421                             " is limited to 16 bytes\n");
7422                 return -EINVAL;
7423         }
7424
7425         /* 4 byte aligned address */
7426         addr32 = addr & (~0x3);
7427         do {
7428                 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7429                                     data_array);
7430         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7431
7432         if (rc == 0) {
7433                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7434                         o_buf[j] = *((u8 *)data_array + i);
7435                         j++;
7436                 }
7437         }
7438
7439         return rc;
7440 }
7441
7442 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7443                                              struct link_params *params,
7444                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7445 {
7446         struct bnx2x *bp = params->bp;
7447         u16 val, i;
7448
7449         if (byte_cnt > 16) {
7450                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7451                             " is limited to 0xf\n");
7452                 return -EINVAL;
7453         }
7454
7455         /* Need to read from 1.8000 to clear it */
7456         bnx2x_cl45_read(bp, phy,
7457                         MDIO_PMA_DEVAD,
7458                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7459                         &val);
7460
7461         /* Set the read command byte count */
7462         bnx2x_cl45_write(bp, phy,
7463                          MDIO_PMA_DEVAD,
7464                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7465                          ((byte_cnt < 2) ? 2 : byte_cnt));
7466
7467         /* Set the read command address */
7468         bnx2x_cl45_write(bp, phy,
7469                          MDIO_PMA_DEVAD,
7470                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7471                          addr);
7472         /* Set the destination address */
7473         bnx2x_cl45_write(bp, phy,
7474                          MDIO_PMA_DEVAD,
7475                          0x8004,
7476                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7477
7478         /* Activate read command */
7479         bnx2x_cl45_write(bp, phy,
7480                          MDIO_PMA_DEVAD,
7481                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7482                          0x8002);
7483         /*
7484          * Wait appropriate time for two-wire command to finish before
7485          * polling the status register
7486          */
7487         msleep(1);
7488
7489         /* Wait up to 500us for command complete status */
7490         for (i = 0; i < 100; i++) {
7491                 bnx2x_cl45_read(bp, phy,
7492                                 MDIO_PMA_DEVAD,
7493                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7494                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7495                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7496                         break;
7497                 udelay(5);
7498         }
7499
7500         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7501                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7502                 DP(NETIF_MSG_LINK,
7503                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7504                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7505                 return -EFAULT;
7506         }
7507
7508         /* Read the buffer */
7509         for (i = 0; i < byte_cnt; i++) {
7510                 bnx2x_cl45_read(bp, phy,
7511                                 MDIO_PMA_DEVAD,
7512                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7513                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7514         }
7515
7516         for (i = 0; i < 100; i++) {
7517                 bnx2x_cl45_read(bp, phy,
7518                                 MDIO_PMA_DEVAD,
7519                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7520                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7521                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7522                         return 0;
7523                 msleep(1);
7524         }
7525
7526         return -EINVAL;
7527 }
7528
7529 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7530                                  struct link_params *params, u16 addr,
7531                                  u8 byte_cnt, u8 *o_buf)
7532 {
7533         int rc = -EINVAL;
7534         switch (phy->type) {
7535         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7536                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7537                                                        byte_cnt, o_buf);
7538         break;
7539         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7540         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7541                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7542                                                        byte_cnt, o_buf);
7543         break;
7544         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7545                 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7546                                                            byte_cnt, o_buf);
7547         break;
7548         }
7549         return rc;
7550 }
7551
7552 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7553                               struct link_params *params,
7554                               u16 *edc_mode)
7555 {
7556         struct bnx2x *bp = params->bp;
7557         u32 sync_offset = 0, phy_idx, media_types;
7558         u8 val, check_limiting_mode = 0;
7559         *edc_mode = EDC_MODE_LIMITING;
7560
7561         phy->media_type = ETH_PHY_UNSPECIFIED;
7562         /* First check for copper cable */
7563         if (bnx2x_read_sfp_module_eeprom(phy,
7564                                          params,
7565                                          SFP_EEPROM_CON_TYPE_ADDR,
7566                                          1,
7567                                          &val) != 0) {
7568                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7569                 return -EINVAL;
7570         }
7571
7572         switch (val) {
7573         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7574         {
7575                 u8 copper_module_type;
7576                 phy->media_type = ETH_PHY_DA_TWINAX;
7577                 /*
7578                  * Check if its active cable (includes SFP+ module)
7579                  * of passive cable
7580                  */
7581                 if (bnx2x_read_sfp_module_eeprom(phy,
7582                                                params,
7583                                                SFP_EEPROM_FC_TX_TECH_ADDR,
7584                                                1,
7585                                                &copper_module_type) != 0) {
7586                         DP(NETIF_MSG_LINK,
7587                                 "Failed to read copper-cable-type"
7588                                 " from SFP+ EEPROM\n");
7589                         return -EINVAL;
7590                 }
7591
7592                 if (copper_module_type &
7593                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7594                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7595                         check_limiting_mode = 1;
7596                 } else if (copper_module_type &
7597                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7598                                 DP(NETIF_MSG_LINK, "Passive Copper"
7599                                             " cable detected\n");
7600                                 *edc_mode =
7601                                       EDC_MODE_PASSIVE_DAC;
7602                 } else {
7603                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
7604                                      "type 0x%x !!!\n", copper_module_type);
7605                         return -EINVAL;
7606                 }
7607                 break;
7608         }
7609         case SFP_EEPROM_CON_TYPE_VAL_LC:
7610                 phy->media_type = ETH_PHY_SFP_FIBER;
7611                 DP(NETIF_MSG_LINK, "Optic module detected\n");
7612                 check_limiting_mode = 1;
7613                 break;
7614         default:
7615                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7616                          val);
7617                 return -EINVAL;
7618         }
7619         sync_offset = params->shmem_base +
7620                 offsetof(struct shmem_region,
7621                          dev_info.port_hw_config[params->port].media_type);
7622         media_types = REG_RD(bp, sync_offset);
7623         /* Update media type for non-PMF sync */
7624         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7625                 if (&(params->phy[phy_idx]) == phy) {
7626                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7627                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7628                         media_types |= ((phy->media_type &
7629                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7630                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7631                         break;
7632                 }
7633         }
7634         REG_WR(bp, sync_offset, media_types);
7635         if (check_limiting_mode) {
7636                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7637                 if (bnx2x_read_sfp_module_eeprom(phy,
7638                                                  params,
7639                                                  SFP_EEPROM_OPTIONS_ADDR,
7640                                                  SFP_EEPROM_OPTIONS_SIZE,
7641                                                  options) != 0) {
7642                         DP(NETIF_MSG_LINK, "Failed to read Option"
7643                                 " field from module EEPROM\n");
7644                         return -EINVAL;
7645                 }
7646                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7647                         *edc_mode = EDC_MODE_LINEAR;
7648                 else
7649                         *edc_mode = EDC_MODE_LIMITING;
7650         }
7651         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7652         return 0;
7653 }
7654 /*
7655  * This function read the relevant field from the module (SFP+), and verify it
7656  * is compliant with this board
7657  */
7658 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7659                                    struct link_params *params)
7660 {
7661         struct bnx2x *bp = params->bp;
7662         u32 val, cmd;
7663         u32 fw_resp, fw_cmd_param;
7664         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7665         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7666         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7667         val = REG_RD(bp, params->shmem_base +
7668                          offsetof(struct shmem_region, dev_info.
7669                                   port_feature_config[params->port].config));
7670         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7671             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7672                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7673                 return 0;
7674         }
7675
7676         if (params->feature_config_flags &
7677             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7678                 /* Use specific phy request */
7679                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7680         } else if (params->feature_config_flags &
7681                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7682                 /* Use first phy request only in case of non-dual media*/
7683                 if (DUAL_MEDIA(params)) {
7684                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7685                            "verification\n");
7686                         return -EINVAL;
7687                 }
7688                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7689         } else {
7690                 /* No support in OPT MDL detection */
7691                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7692                           "verification\n");
7693                 return -EINVAL;
7694         }
7695
7696         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7697         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7698         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7699                 DP(NETIF_MSG_LINK, "Approved module\n");
7700                 return 0;
7701         }
7702
7703         /* format the warning message */
7704         if (bnx2x_read_sfp_module_eeprom(phy,
7705                                          params,
7706                                          SFP_EEPROM_VENDOR_NAME_ADDR,
7707                                          SFP_EEPROM_VENDOR_NAME_SIZE,
7708                                          (u8 *)vendor_name))
7709                 vendor_name[0] = '\0';
7710         else
7711                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7712         if (bnx2x_read_sfp_module_eeprom(phy,
7713                                          params,
7714                                          SFP_EEPROM_PART_NO_ADDR,
7715                                          SFP_EEPROM_PART_NO_SIZE,
7716                                          (u8 *)vendor_pn))
7717                 vendor_pn[0] = '\0';
7718         else
7719                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7720
7721         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
7722                               " Port %d from %s part number %s\n",
7723                          params->port, vendor_name, vendor_pn);
7724         phy->flags |= FLAGS_SFP_NOT_APPROVED;
7725         return -EINVAL;
7726 }
7727
7728 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7729                                                  struct link_params *params)
7730
7731 {
7732         u8 val;
7733         struct bnx2x *bp = params->bp;
7734         u16 timeout;
7735         /*
7736          * Initialization time after hot-plug may take up to 300ms for
7737          * some phys type ( e.g. JDSU )
7738          */
7739
7740         for (timeout = 0; timeout < 60; timeout++) {
7741                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7742                     == 0) {
7743                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
7744                                      "took %d ms\n", timeout * 5);
7745                         return 0;
7746                 }
7747                 msleep(5);
7748         }
7749         return -EINVAL;
7750 }
7751
7752 static void bnx2x_8727_power_module(struct bnx2x *bp,
7753                                     struct bnx2x_phy *phy,
7754                                     u8 is_power_up) {
7755         /* Make sure GPIOs are not using for LED mode */
7756         u16 val;
7757         /*
7758          * In the GPIO register, bit 4 is use to determine if the GPIOs are
7759          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7760          * output
7761          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7762          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7763          * where the 1st bit is the over-current(only input), and 2nd bit is
7764          * for power( only output )
7765          *
7766          * In case of NOC feature is disabled and power is up, set GPIO control
7767          *  as input to enable listening of over-current indication
7768          */
7769         if (phy->flags & FLAGS_NOC)
7770                 return;
7771         if (is_power_up)
7772                 val = (1<<4);
7773         else
7774                 /*
7775                  * Set GPIO control to OUTPUT, and set the power bit
7776                  * to according to the is_power_up
7777                  */
7778                 val = (1<<1);
7779
7780         bnx2x_cl45_write(bp, phy,
7781                          MDIO_PMA_DEVAD,
7782                          MDIO_PMA_REG_8727_GPIO_CTRL,
7783                          val);
7784 }
7785
7786 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
7787                                         struct bnx2x_phy *phy,
7788                                         u16 edc_mode)
7789 {
7790         u16 cur_limiting_mode;
7791
7792         bnx2x_cl45_read(bp, phy,
7793                         MDIO_PMA_DEVAD,
7794                         MDIO_PMA_REG_ROM_VER2,
7795                         &cur_limiting_mode);
7796         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
7797                  cur_limiting_mode);
7798
7799         if (edc_mode == EDC_MODE_LIMITING) {
7800                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
7801                 bnx2x_cl45_write(bp, phy,
7802                                  MDIO_PMA_DEVAD,
7803                                  MDIO_PMA_REG_ROM_VER2,
7804                                  EDC_MODE_LIMITING);
7805         } else { /* LRM mode ( default )*/
7806
7807                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
7808
7809                 /*
7810                  * Changing to LRM mode takes quite few seconds. So do it only
7811                  * if current mode is limiting (default is LRM)
7812                  */
7813                 if (cur_limiting_mode != EDC_MODE_LIMITING)
7814                         return 0;
7815
7816                 bnx2x_cl45_write(bp, phy,
7817                                  MDIO_PMA_DEVAD,
7818                                  MDIO_PMA_REG_LRM_MODE,
7819                                  0);
7820                 bnx2x_cl45_write(bp, phy,
7821                                  MDIO_PMA_DEVAD,
7822                                  MDIO_PMA_REG_ROM_VER2,
7823                                  0x128);
7824                 bnx2x_cl45_write(bp, phy,
7825                                  MDIO_PMA_DEVAD,
7826                                  MDIO_PMA_REG_MISC_CTRL0,
7827                                  0x4008);
7828                 bnx2x_cl45_write(bp, phy,
7829                                  MDIO_PMA_DEVAD,
7830                                  MDIO_PMA_REG_LRM_MODE,
7831                                  0xaaaa);
7832         }
7833         return 0;
7834 }
7835
7836 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
7837                                         struct bnx2x_phy *phy,
7838                                         u16 edc_mode)
7839 {
7840         u16 phy_identifier;
7841         u16 rom_ver2_val;
7842         bnx2x_cl45_read(bp, phy,
7843                         MDIO_PMA_DEVAD,
7844                         MDIO_PMA_REG_PHY_IDENTIFIER,
7845                         &phy_identifier);
7846
7847         bnx2x_cl45_write(bp, phy,
7848                          MDIO_PMA_DEVAD,
7849                          MDIO_PMA_REG_PHY_IDENTIFIER,
7850                          (phy_identifier & ~(1<<9)));
7851
7852         bnx2x_cl45_read(bp, phy,
7853                         MDIO_PMA_DEVAD,
7854                         MDIO_PMA_REG_ROM_VER2,
7855                         &rom_ver2_val);
7856         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7857         bnx2x_cl45_write(bp, phy,
7858                          MDIO_PMA_DEVAD,
7859                          MDIO_PMA_REG_ROM_VER2,
7860                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7861
7862         bnx2x_cl45_write(bp, phy,
7863                          MDIO_PMA_DEVAD,
7864                          MDIO_PMA_REG_PHY_IDENTIFIER,
7865                          (phy_identifier | (1<<9)));
7866
7867         return 0;
7868 }
7869
7870 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
7871                                      struct link_params *params,
7872                                      u32 action)
7873 {
7874         struct bnx2x *bp = params->bp;
7875
7876         switch (action) {
7877         case DISABLE_TX:
7878                 bnx2x_sfp_set_transmitter(params, phy, 0);
7879                 break;
7880         case ENABLE_TX:
7881                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7882                         bnx2x_sfp_set_transmitter(params, phy, 1);
7883                 break;
7884         default:
7885                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
7886                    action);
7887                 return;
7888         }
7889 }
7890
7891 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7892                                            u8 gpio_mode)
7893 {
7894         struct bnx2x *bp = params->bp;
7895
7896         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
7897                             offsetof(struct shmem_region,
7898                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
7899                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7900         switch (fault_led_gpio) {
7901         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7902                 return;
7903         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7904         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7905         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7906         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7907         {
7908                 u8 gpio_port = bnx2x_get_gpio_port(params);
7909                 u16 gpio_pin = fault_led_gpio -
7910                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7911                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
7912                                    "pin %x port %x mode %x\n",
7913                                gpio_pin, gpio_port, gpio_mode);
7914                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7915         }
7916         break;
7917         default:
7918                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
7919                                fault_led_gpio);
7920         }
7921 }
7922
7923 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
7924                                           u8 gpio_mode)
7925 {
7926         u32 pin_cfg;
7927         u8 port = params->port;
7928         struct bnx2x *bp = params->bp;
7929         pin_cfg = (REG_RD(bp, params->shmem_base +
7930                          offsetof(struct shmem_region,
7931                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7932                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7933                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7934         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
7935                        gpio_mode, pin_cfg);
7936         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
7937 }
7938
7939 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
7940                                            u8 gpio_mode)
7941 {
7942         struct bnx2x *bp = params->bp;
7943         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
7944         if (CHIP_IS_E3(bp)) {
7945                 /*
7946                  * Low ==> if SFP+ module is supported otherwise
7947                  * High ==> if SFP+ module is not on the approved vendor list
7948                  */
7949                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
7950         } else
7951                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
7952 }
7953
7954 static void bnx2x_warpcore_power_module(struct link_params *params,
7955                                         struct bnx2x_phy *phy,
7956                                         u8 power)
7957 {
7958         u32 pin_cfg;
7959         struct bnx2x *bp = params->bp;
7960
7961         pin_cfg = (REG_RD(bp, params->shmem_base +
7962                           offsetof(struct shmem_region,
7963                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7964                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7965                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7966
7967         if (pin_cfg == PIN_CFG_NA)
7968                 return;
7969         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7970                        power, pin_cfg);
7971         /*
7972          * Low ==> corresponding SFP+ module is powered
7973          * high ==> the SFP+ module is powered down
7974          */
7975         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7976 }
7977
7978 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
7979                                     struct link_params *params)
7980 {
7981         bnx2x_warpcore_power_module(params, phy, 0);
7982 }
7983
7984 static void bnx2x_power_sfp_module(struct link_params *params,
7985                                    struct bnx2x_phy *phy,
7986                                    u8 power)
7987 {
7988         struct bnx2x *bp = params->bp;
7989         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
7990
7991         switch (phy->type) {
7992         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7993         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7994                 bnx2x_8727_power_module(params->bp, phy, power);
7995                 break;
7996         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7997                 bnx2x_warpcore_power_module(params, phy, power);
7998                 break;
7999         default:
8000                 break;
8001         }
8002 }
8003 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8004                                              struct bnx2x_phy *phy,
8005                                              u16 edc_mode)
8006 {
8007         u16 val = 0;
8008         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8009         struct bnx2x *bp = params->bp;
8010
8011         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8012         /* This is a global register which controls all lanes */
8013         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8014                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8015         val &= ~(0xf << (lane << 2));
8016
8017         switch (edc_mode) {
8018         case EDC_MODE_LINEAR:
8019         case EDC_MODE_LIMITING:
8020                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8021                 break;
8022         case EDC_MODE_PASSIVE_DAC:
8023                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8024                 break;
8025         default:
8026                 break;
8027         }
8028
8029         val |= (mode << (lane << 2));
8030         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8031                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8032         /* A must read */
8033         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8034                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8035
8036         /* Restart microcode to re-read the new mode */
8037         bnx2x_warpcore_reset_lane(bp, phy, 1);
8038         bnx2x_warpcore_reset_lane(bp, phy, 0);
8039
8040 }
8041
8042 static void bnx2x_set_limiting_mode(struct link_params *params,
8043                                     struct bnx2x_phy *phy,
8044                                     u16 edc_mode)
8045 {
8046         switch (phy->type) {
8047         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8048                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8049                 break;
8050         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8051         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8052                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8053                 break;
8054         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8055                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8056                 break;
8057         }
8058 }
8059
8060 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8061                                struct link_params *params)
8062 {
8063         struct bnx2x *bp = params->bp;
8064         u16 edc_mode;
8065         int rc = 0;
8066
8067         u32 val = REG_RD(bp, params->shmem_base +
8068                              offsetof(struct shmem_region, dev_info.
8069                                      port_feature_config[params->port].config));
8070
8071         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8072                  params->port);
8073         /* Power up module */
8074         bnx2x_power_sfp_module(params, phy, 1);
8075         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8076                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8077                 return -EINVAL;
8078         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8079                 /* check SFP+ module compatibility */
8080                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8081                 rc = -EINVAL;
8082                 /* Turn on fault module-detected led */
8083                 bnx2x_set_sfp_module_fault_led(params,
8084                                                MISC_REGISTERS_GPIO_HIGH);
8085
8086                 /* Check if need to power down the SFP+ module */
8087                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8088                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8089                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8090                         bnx2x_power_sfp_module(params, phy, 0);
8091                         return rc;
8092                 }
8093         } else {
8094                 /* Turn off fault module-detected led */
8095                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8096         }
8097
8098         /*
8099          * Check and set limiting mode / LRM mode on 8726. On 8727 it
8100          * is done automatically
8101          */
8102         bnx2x_set_limiting_mode(params, phy, edc_mode);
8103
8104         /*
8105          * Enable transmit for this module if the module is approved, or
8106          * if unapproved modules should also enable the Tx laser
8107          */
8108         if (rc == 0 ||
8109             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8110             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8111                 bnx2x_sfp_set_transmitter(params, phy, 1);
8112         else
8113                 bnx2x_sfp_set_transmitter(params, phy, 0);
8114
8115         return rc;
8116 }
8117
8118 void bnx2x_handle_module_detect_int(struct link_params *params)
8119 {
8120         struct bnx2x *bp = params->bp;
8121         struct bnx2x_phy *phy;
8122         u32 gpio_val;
8123         u8 gpio_num, gpio_port;
8124         if (CHIP_IS_E3(bp))
8125                 phy = &params->phy[INT_PHY];
8126         else
8127                 phy = &params->phy[EXT_PHY1];
8128
8129         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8130                                       params->port, &gpio_num, &gpio_port) ==
8131             -EINVAL) {
8132                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8133                 return;
8134         }
8135
8136         /* Set valid module led off */
8137         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8138
8139         /* Get current gpio val reflecting module plugged in / out*/
8140         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8141
8142         /* Call the handling function in case module is detected */
8143         if (gpio_val == 0) {
8144                 bnx2x_power_sfp_module(params, phy, 1);
8145                 bnx2x_set_gpio_int(bp, gpio_num,
8146                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8147                                    gpio_port);
8148                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8149                         bnx2x_sfp_module_detection(phy, params);
8150                 else
8151                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8152         } else {
8153                 u32 val = REG_RD(bp, params->shmem_base +
8154                                  offsetof(struct shmem_region, dev_info.
8155                                           port_feature_config[params->port].
8156                                           config));
8157                 bnx2x_set_gpio_int(bp, gpio_num,
8158                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8159                                    gpio_port);
8160                 /*
8161                  * Module was plugged out.
8162                  * Disable transmit for this module
8163                  */
8164                 phy->media_type = ETH_PHY_NOT_PRESENT;
8165                 if (((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8166                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) ||
8167                     CHIP_IS_E3(bp))
8168                         bnx2x_sfp_set_transmitter(params, phy, 0);
8169         }
8170 }
8171
8172 /******************************************************************/
8173 /*              Used by 8706 and 8727                             */
8174 /******************************************************************/
8175 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8176                                  struct bnx2x_phy *phy,
8177                                  u16 alarm_status_offset,
8178                                  u16 alarm_ctrl_offset)
8179 {
8180         u16 alarm_status, val;
8181         bnx2x_cl45_read(bp, phy,
8182                         MDIO_PMA_DEVAD, alarm_status_offset,
8183                         &alarm_status);
8184         bnx2x_cl45_read(bp, phy,
8185                         MDIO_PMA_DEVAD, alarm_status_offset,
8186                         &alarm_status);
8187         /* Mask or enable the fault event. */
8188         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8189         if (alarm_status & (1<<0))
8190                 val &= ~(1<<0);
8191         else
8192                 val |= (1<<0);
8193         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8194 }
8195 /******************************************************************/
8196 /*              common BCM8706/BCM8726 PHY SECTION                */
8197 /******************************************************************/
8198 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8199                                       struct link_params *params,
8200                                       struct link_vars *vars)
8201 {
8202         u8 link_up = 0;
8203         u16 val1, val2, rx_sd, pcs_status;
8204         struct bnx2x *bp = params->bp;
8205         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8206         /* Clear RX Alarm*/
8207         bnx2x_cl45_read(bp, phy,
8208                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8209
8210         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8211                              MDIO_PMA_LASI_TXCTRL);
8212
8213         /* clear LASI indication*/
8214         bnx2x_cl45_read(bp, phy,
8215                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8216         bnx2x_cl45_read(bp, phy,
8217                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8218         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8219
8220         bnx2x_cl45_read(bp, phy,
8221                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8222         bnx2x_cl45_read(bp, phy,
8223                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8224         bnx2x_cl45_read(bp, phy,
8225                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8226         bnx2x_cl45_read(bp, phy,
8227                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8228
8229         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8230                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8231         /*
8232          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8233          * are set, or if the autoneg bit 1 is set
8234          */
8235         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8236         if (link_up) {
8237                 if (val2 & (1<<1))
8238                         vars->line_speed = SPEED_1000;
8239                 else
8240                         vars->line_speed = SPEED_10000;
8241                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8242                 vars->duplex = DUPLEX_FULL;
8243         }
8244
8245         /* Capture 10G link fault. Read twice to clear stale value. */
8246         if (vars->line_speed == SPEED_10000) {
8247                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8248                             MDIO_PMA_LASI_TXSTAT, &val1);
8249                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8250                             MDIO_PMA_LASI_TXSTAT, &val1);
8251                 if (val1 & (1<<0))
8252                         vars->fault_detected = 1;
8253         }
8254
8255         return link_up;
8256 }
8257
8258 /******************************************************************/
8259 /*                      BCM8706 PHY SECTION                       */
8260 /******************************************************************/
8261 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8262                                  struct link_params *params,
8263                                  struct link_vars *vars)
8264 {
8265         u32 tx_en_mode;
8266         u16 cnt, val, tmp1;
8267         struct bnx2x *bp = params->bp;
8268
8269         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8270                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8271         /* HW reset */
8272         bnx2x_ext_phy_hw_reset(bp, params->port);
8273         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8274         bnx2x_wait_reset_complete(bp, phy, params);
8275
8276         /* Wait until fw is loaded */
8277         for (cnt = 0; cnt < 100; cnt++) {
8278                 bnx2x_cl45_read(bp, phy,
8279                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8280                 if (val)
8281                         break;
8282                 msleep(10);
8283         }
8284         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8285         if ((params->feature_config_flags &
8286              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8287                 u8 i;
8288                 u16 reg;
8289                 for (i = 0; i < 4; i++) {
8290                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8291                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8292                                    MDIO_XS_8706_REG_BANK_RX0);
8293                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8294                         /* Clear first 3 bits of the control */
8295                         val &= ~0x7;
8296                         /* Set control bits according to configuration */
8297                         val |= (phy->rx_preemphasis[i] & 0x7);
8298                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8299                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8300                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8301                 }
8302         }
8303         /* Force speed */
8304         if (phy->req_line_speed == SPEED_10000) {
8305                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8306
8307                 bnx2x_cl45_write(bp, phy,
8308                                  MDIO_PMA_DEVAD,
8309                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8310                 bnx2x_cl45_write(bp, phy,
8311                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8312                                  0);
8313                 /* Arm LASI for link and Tx fault. */
8314                 bnx2x_cl45_write(bp, phy,
8315                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8316         } else {
8317                 /* Force 1Gbps using autoneg with 1G advertisement */
8318
8319                 /* Allow CL37 through CL73 */
8320                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8321                 bnx2x_cl45_write(bp, phy,
8322                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8323
8324                 /* Enable Full-Duplex advertisement on CL37 */
8325                 bnx2x_cl45_write(bp, phy,
8326                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8327                 /* Enable CL37 AN */
8328                 bnx2x_cl45_write(bp, phy,
8329                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8330                 /* 1G support */
8331                 bnx2x_cl45_write(bp, phy,
8332                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8333
8334                 /* Enable clause 73 AN */
8335                 bnx2x_cl45_write(bp, phy,
8336                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8337                 bnx2x_cl45_write(bp, phy,
8338                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8339                                  0x0400);
8340                 bnx2x_cl45_write(bp, phy,
8341                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8342                                  0x0004);
8343         }
8344         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8345
8346         /*
8347          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8348          * power mode, if TX Laser is disabled
8349          */
8350
8351         tx_en_mode = REG_RD(bp, params->shmem_base +
8352                             offsetof(struct shmem_region,
8353                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8354                         & PORT_HW_CFG_TX_LASER_MASK;
8355
8356         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8357                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8358                 bnx2x_cl45_read(bp, phy,
8359                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8360                 tmp1 |= 0x1;
8361                 bnx2x_cl45_write(bp, phy,
8362                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8363         }
8364
8365         return 0;
8366 }
8367
8368 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8369                                   struct link_params *params,
8370                                   struct link_vars *vars)
8371 {
8372         return bnx2x_8706_8726_read_status(phy, params, vars);
8373 }
8374
8375 /******************************************************************/
8376 /*                      BCM8726 PHY SECTION                       */
8377 /******************************************************************/
8378 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8379                                        struct link_params *params)
8380 {
8381         struct bnx2x *bp = params->bp;
8382         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8383         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8384 }
8385
8386 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8387                                          struct link_params *params)
8388 {
8389         struct bnx2x *bp = params->bp;
8390         /* Need to wait 100ms after reset */
8391         msleep(100);
8392
8393         /* Micro controller re-boot */
8394         bnx2x_cl45_write(bp, phy,
8395                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8396
8397         /* Set soft reset */
8398         bnx2x_cl45_write(bp, phy,
8399                          MDIO_PMA_DEVAD,
8400                          MDIO_PMA_REG_GEN_CTRL,
8401                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8402
8403         bnx2x_cl45_write(bp, phy,
8404                          MDIO_PMA_DEVAD,
8405                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8406
8407         bnx2x_cl45_write(bp, phy,
8408                          MDIO_PMA_DEVAD,
8409                          MDIO_PMA_REG_GEN_CTRL,
8410                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8411
8412         /* wait for 150ms for microcode load */
8413         msleep(150);
8414
8415         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8416         bnx2x_cl45_write(bp, phy,
8417                          MDIO_PMA_DEVAD,
8418                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8419
8420         msleep(200);
8421         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8422 }
8423
8424 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8425                                  struct link_params *params,
8426                                  struct link_vars *vars)
8427 {
8428         struct bnx2x *bp = params->bp;
8429         u16 val1;
8430         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8431         if (link_up) {
8432                 bnx2x_cl45_read(bp, phy,
8433                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8434                                 &val1);
8435                 if (val1 & (1<<15)) {
8436                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8437                         link_up = 0;
8438                         vars->line_speed = 0;
8439                 }
8440         }
8441         return link_up;
8442 }
8443
8444
8445 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8446                                   struct link_params *params,
8447                                   struct link_vars *vars)
8448 {
8449         struct bnx2x *bp = params->bp;
8450         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8451
8452         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8453         bnx2x_wait_reset_complete(bp, phy, params);
8454
8455         bnx2x_8726_external_rom_boot(phy, params);
8456
8457         /*
8458          * Need to call module detected on initialization since the module
8459          * detection triggered by actual module insertion might occur before
8460          * driver is loaded, and when driver is loaded, it reset all
8461          * registers, including the transmitter
8462          */
8463         bnx2x_sfp_module_detection(phy, params);
8464
8465         if (phy->req_line_speed == SPEED_1000) {
8466                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8467                 bnx2x_cl45_write(bp, phy,
8468                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8469                 bnx2x_cl45_write(bp, phy,
8470                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8471                 bnx2x_cl45_write(bp, phy,
8472                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8473                 bnx2x_cl45_write(bp, phy,
8474                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8475                                  0x400);
8476         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8477                    (phy->speed_cap_mask &
8478                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8479                    ((phy->speed_cap_mask &
8480                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8481                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8482                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8483                 /* Set Flow control */
8484                 bnx2x_ext_phy_set_pause(params, phy, vars);
8485                 bnx2x_cl45_write(bp, phy,
8486                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8487                 bnx2x_cl45_write(bp, phy,
8488                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8489                 bnx2x_cl45_write(bp, phy,
8490                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8491                 bnx2x_cl45_write(bp, phy,
8492                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8493                 bnx2x_cl45_write(bp, phy,
8494                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8495                 /*
8496                  * Enable RX-ALARM control to receive interrupt for 1G speed
8497                  * change
8498                  */
8499                 bnx2x_cl45_write(bp, phy,
8500                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8501                 bnx2x_cl45_write(bp, phy,
8502                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8503                                  0x400);
8504
8505         } else { /* Default 10G. Set only LASI control */
8506                 bnx2x_cl45_write(bp, phy,
8507                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8508         }
8509
8510         /* Set TX PreEmphasis if needed */
8511         if ((params->feature_config_flags &
8512              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8513                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
8514                          "TX_CTRL2 0x%x\n",
8515                          phy->tx_preemphasis[0],
8516                          phy->tx_preemphasis[1]);
8517                 bnx2x_cl45_write(bp, phy,
8518                                  MDIO_PMA_DEVAD,
8519                                  MDIO_PMA_REG_8726_TX_CTRL1,
8520                                  phy->tx_preemphasis[0]);
8521
8522                 bnx2x_cl45_write(bp, phy,
8523                                  MDIO_PMA_DEVAD,
8524                                  MDIO_PMA_REG_8726_TX_CTRL2,
8525                                  phy->tx_preemphasis[1]);
8526         }
8527
8528         return 0;
8529
8530 }
8531
8532 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8533                                   struct link_params *params)
8534 {
8535         struct bnx2x *bp = params->bp;
8536         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8537         /* Set serial boot control for external load */
8538         bnx2x_cl45_write(bp, phy,
8539                          MDIO_PMA_DEVAD,
8540                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
8541 }
8542
8543 /******************************************************************/
8544 /*                      BCM8727 PHY SECTION                       */
8545 /******************************************************************/
8546
8547 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8548                                     struct link_params *params, u8 mode)
8549 {
8550         struct bnx2x *bp = params->bp;
8551         u16 led_mode_bitmask = 0;
8552         u16 gpio_pins_bitmask = 0;
8553         u16 val;
8554         /* Only NOC flavor requires to set the LED specifically */
8555         if (!(phy->flags & FLAGS_NOC))
8556                 return;
8557         switch (mode) {
8558         case LED_MODE_FRONT_PANEL_OFF:
8559         case LED_MODE_OFF:
8560                 led_mode_bitmask = 0;
8561                 gpio_pins_bitmask = 0x03;
8562                 break;
8563         case LED_MODE_ON:
8564                 led_mode_bitmask = 0;
8565                 gpio_pins_bitmask = 0x02;
8566                 break;
8567         case LED_MODE_OPER:
8568                 led_mode_bitmask = 0x60;
8569                 gpio_pins_bitmask = 0x11;
8570                 break;
8571         }
8572         bnx2x_cl45_read(bp, phy,
8573                         MDIO_PMA_DEVAD,
8574                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8575                         &val);
8576         val &= 0xff8f;
8577         val |= led_mode_bitmask;
8578         bnx2x_cl45_write(bp, phy,
8579                          MDIO_PMA_DEVAD,
8580                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8581                          val);
8582         bnx2x_cl45_read(bp, phy,
8583                         MDIO_PMA_DEVAD,
8584                         MDIO_PMA_REG_8727_GPIO_CTRL,
8585                         &val);
8586         val &= 0xffe0;
8587         val |= gpio_pins_bitmask;
8588         bnx2x_cl45_write(bp, phy,
8589                          MDIO_PMA_DEVAD,
8590                          MDIO_PMA_REG_8727_GPIO_CTRL,
8591                          val);
8592 }
8593 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8594                                 struct link_params *params) {
8595         u32 swap_val, swap_override;
8596         u8 port;
8597         /*
8598          * The PHY reset is controlled by GPIO 1. Fake the port number
8599          * to cancel the swap done in set_gpio()
8600          */
8601         struct bnx2x *bp = params->bp;
8602         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8603         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8604         port = (swap_val && swap_override) ^ 1;
8605         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8606                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8607 }
8608
8609 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8610                                   struct link_params *params,
8611                                   struct link_vars *vars)
8612 {
8613         u32 tx_en_mode;
8614         u16 tmp1, val, mod_abs, tmp2;
8615         u16 rx_alarm_ctrl_val;
8616         u16 lasi_ctrl_val;
8617         struct bnx2x *bp = params->bp;
8618         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8619
8620         bnx2x_wait_reset_complete(bp, phy, params);
8621         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8622         /* Should be 0x6 to enable XS on Tx side. */
8623         lasi_ctrl_val = 0x0006;
8624
8625         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8626         /* enable LASI */
8627         bnx2x_cl45_write(bp, phy,
8628                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8629                          rx_alarm_ctrl_val);
8630         bnx2x_cl45_write(bp, phy,
8631                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8632                          0);
8633         bnx2x_cl45_write(bp, phy,
8634                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8635
8636         /*
8637          * Initially configure MOD_ABS to interrupt when module is
8638          * presence( bit 8)
8639          */
8640         bnx2x_cl45_read(bp, phy,
8641                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8642         /*
8643          * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8644          * When the EDC is off it locks onto a reference clock and avoids
8645          * becoming 'lost'
8646          */
8647         mod_abs &= ~(1<<8);
8648         if (!(phy->flags & FLAGS_NOC))
8649                 mod_abs &= ~(1<<9);
8650         bnx2x_cl45_write(bp, phy,
8651                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8652
8653
8654         /* Enable/Disable PHY transmitter output */
8655         bnx2x_set_disable_pmd_transmit(params, phy, 0);
8656
8657         /* Make MOD_ABS give interrupt on change */
8658         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8659                         &val);
8660         val |= (1<<12);
8661         if (phy->flags & FLAGS_NOC)
8662                 val |= (3<<5);
8663
8664         /*
8665          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8666          * status which reflect SFP+ module over-current
8667          */
8668         if (!(phy->flags & FLAGS_NOC))
8669                 val &= 0xff8f; /* Reset bits 4-6 */
8670         bnx2x_cl45_write(bp, phy,
8671                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8672
8673         bnx2x_8727_power_module(bp, phy, 1);
8674
8675         bnx2x_cl45_read(bp, phy,
8676                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8677
8678         bnx2x_cl45_read(bp, phy,
8679                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8680
8681         /* Set option 1G speed */
8682         if (phy->req_line_speed == SPEED_1000) {
8683                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8684                 bnx2x_cl45_write(bp, phy,
8685                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8686                 bnx2x_cl45_write(bp, phy,
8687                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8688                 bnx2x_cl45_read(bp, phy,
8689                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8690                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8691                 /*
8692                  * Power down the XAUI until link is up in case of dual-media
8693                  * and 1G
8694                  */
8695                 if (DUAL_MEDIA(params)) {
8696                         bnx2x_cl45_read(bp, phy,
8697                                         MDIO_PMA_DEVAD,
8698                                         MDIO_PMA_REG_8727_PCS_GP, &val);
8699                         val |= (3<<10);
8700                         bnx2x_cl45_write(bp, phy,
8701                                          MDIO_PMA_DEVAD,
8702                                          MDIO_PMA_REG_8727_PCS_GP, val);
8703                 }
8704         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8705                    ((phy->speed_cap_mask &
8706                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8707                    ((phy->speed_cap_mask &
8708                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8709                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8710
8711                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8712                 bnx2x_cl45_write(bp, phy,
8713                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8714                 bnx2x_cl45_write(bp, phy,
8715                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8716         } else {
8717                 /*
8718                  * Since the 8727 has only single reset pin, need to set the 10G
8719                  * registers although it is default
8720                  */
8721                 bnx2x_cl45_write(bp, phy,
8722                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8723                                  0x0020);
8724                 bnx2x_cl45_write(bp, phy,
8725                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8726                 bnx2x_cl45_write(bp, phy,
8727                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8728                 bnx2x_cl45_write(bp, phy,
8729                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8730                                  0x0008);
8731         }
8732
8733         /*
8734          * Set 2-wire transfer rate of SFP+ module EEPROM
8735          * to 100Khz since some DACs(direct attached cables) do
8736          * not work at 400Khz.
8737          */
8738         bnx2x_cl45_write(bp, phy,
8739                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8740                          0xa001);
8741
8742         /* Set TX PreEmphasis if needed */
8743         if ((params->feature_config_flags &
8744              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8745                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8746                            phy->tx_preemphasis[0],
8747                            phy->tx_preemphasis[1]);
8748                 bnx2x_cl45_write(bp, phy,
8749                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8750                                  phy->tx_preemphasis[0]);
8751
8752                 bnx2x_cl45_write(bp, phy,
8753                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8754                                  phy->tx_preemphasis[1]);
8755         }
8756
8757         /*
8758          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8759          * power mode, if TX Laser is disabled
8760          */
8761         tx_en_mode = REG_RD(bp, params->shmem_base +
8762                             offsetof(struct shmem_region,
8763                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8764                         & PORT_HW_CFG_TX_LASER_MASK;
8765
8766         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8767
8768                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8769                 bnx2x_cl45_read(bp, phy,
8770                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
8771                 tmp2 |= 0x1000;
8772                 tmp2 &= 0xFFEF;
8773                 bnx2x_cl45_write(bp, phy,
8774                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
8775         }
8776
8777         return 0;
8778 }
8779
8780 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
8781                                       struct link_params *params)
8782 {
8783         struct bnx2x *bp = params->bp;
8784         u16 mod_abs, rx_alarm_status;
8785         u32 val = REG_RD(bp, params->shmem_base +
8786                              offsetof(struct shmem_region, dev_info.
8787                                       port_feature_config[params->port].
8788                                       config));
8789         bnx2x_cl45_read(bp, phy,
8790                         MDIO_PMA_DEVAD,
8791                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8792         if (mod_abs & (1<<8)) {
8793
8794                 /* Module is absent */
8795                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8796                             "show module is absent\n");
8797                 phy->media_type = ETH_PHY_NOT_PRESENT;
8798                 /*
8799                  * 1. Set mod_abs to detect next module
8800                  *    presence event
8801                  * 2. Set EDC off by setting OPTXLOS signal input to low
8802                  *    (bit 9).
8803                  *    When the EDC is off it locks onto a reference clock and
8804                  *    avoids becoming 'lost'.
8805                  */
8806                 mod_abs &= ~(1<<8);
8807                 if (!(phy->flags & FLAGS_NOC))
8808                         mod_abs &= ~(1<<9);
8809                 bnx2x_cl45_write(bp, phy,
8810                                  MDIO_PMA_DEVAD,
8811                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8812
8813                 /*
8814                  * Clear RX alarm since it stays up as long as
8815                  * the mod_abs wasn't changed
8816                  */
8817                 bnx2x_cl45_read(bp, phy,
8818                                 MDIO_PMA_DEVAD,
8819                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8820
8821         } else {
8822                 /* Module is present */
8823                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8824                             "show module is present\n");
8825                 /*
8826                  * First disable transmitter, and if the module is ok, the
8827                  * module_detection will enable it
8828                  * 1. Set mod_abs to detect next module absent event ( bit 8)
8829                  * 2. Restore the default polarity of the OPRXLOS signal and
8830                  * this signal will then correctly indicate the presence or
8831                  * absence of the Rx signal. (bit 9)
8832                  */
8833                 mod_abs |= (1<<8);
8834                 if (!(phy->flags & FLAGS_NOC))
8835                         mod_abs |= (1<<9);
8836                 bnx2x_cl45_write(bp, phy,
8837                                  MDIO_PMA_DEVAD,
8838                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8839
8840                 /*
8841                  * Clear RX alarm since it stays up as long as the mod_abs
8842                  * wasn't changed. This is need to be done before calling the
8843                  * module detection, otherwise it will clear* the link update
8844                  * alarm
8845                  */
8846                 bnx2x_cl45_read(bp, phy,
8847                                 MDIO_PMA_DEVAD,
8848                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8849
8850
8851                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8852                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8853                         bnx2x_sfp_set_transmitter(params, phy, 0);
8854
8855                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8856                         bnx2x_sfp_module_detection(phy, params);
8857                 else
8858                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8859         }
8860
8861         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8862                    rx_alarm_status);
8863         /* No need to check link status in case of module plugged in/out */
8864 }
8865
8866 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
8867                                  struct link_params *params,
8868                                  struct link_vars *vars)
8869
8870 {
8871         struct bnx2x *bp = params->bp;
8872         u8 link_up = 0, oc_port = params->port;
8873         u16 link_status = 0;
8874         u16 rx_alarm_status, lasi_ctrl, val1;
8875
8876         /* If PHY is not initialized, do not check link status */
8877         bnx2x_cl45_read(bp, phy,
8878                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8879                         &lasi_ctrl);
8880         if (!lasi_ctrl)
8881                 return 0;
8882
8883         /* Check the LASI on Rx */
8884         bnx2x_cl45_read(bp, phy,
8885                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
8886                         &rx_alarm_status);
8887         vars->line_speed = 0;
8888         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
8889
8890         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8891                              MDIO_PMA_LASI_TXCTRL);
8892
8893         bnx2x_cl45_read(bp, phy,
8894                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8895
8896         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
8897
8898         /* Clear MSG-OUT */
8899         bnx2x_cl45_read(bp, phy,
8900                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8901
8902         /*
8903          * If a module is present and there is need to check
8904          * for over current
8905          */
8906         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
8907                 /* Check over-current using 8727 GPIO0 input*/
8908                 bnx2x_cl45_read(bp, phy,
8909                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8910                                 &val1);
8911
8912                 if ((val1 & (1<<8)) == 0) {
8913                         if (!CHIP_IS_E1x(bp))
8914                                 oc_port = BP_PATH(bp) + (params->port << 1);
8915                         DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
8916                                        " on port %d\n", oc_port);
8917                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
8918                                             " been detected and the power to "
8919                                             "that SFP+ module has been removed"
8920                                             " to prevent failure of the card."
8921                                             " Please remove the SFP+ module and"
8922                                             " restart the system to clear this"
8923                                             " error.\n",
8924                          oc_port);
8925                         /* Disable all RX_ALARMs except for mod_abs */
8926                         bnx2x_cl45_write(bp, phy,
8927                                          MDIO_PMA_DEVAD,
8928                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
8929
8930                         bnx2x_cl45_read(bp, phy,
8931                                         MDIO_PMA_DEVAD,
8932                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8933                         /* Wait for module_absent_event */
8934                         val1 |= (1<<8);
8935                         bnx2x_cl45_write(bp, phy,
8936                                          MDIO_PMA_DEVAD,
8937                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8938                         /* Clear RX alarm */
8939                         bnx2x_cl45_read(bp, phy,
8940                                 MDIO_PMA_DEVAD,
8941                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8942                         return 0;
8943                 }
8944         } /* Over current check */
8945
8946         /* When module absent bit is set, check module */
8947         if (rx_alarm_status & (1<<5)) {
8948                 bnx2x_8727_handle_mod_abs(phy, params);
8949                 /* Enable all mod_abs and link detection bits */
8950                 bnx2x_cl45_write(bp, phy,
8951                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8952                                  ((1<<5) | (1<<2)));
8953         }
8954         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
8955         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
8956         /* If transmitter is disabled, ignore false link up indication */
8957         bnx2x_cl45_read(bp, phy,
8958                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8959         if (val1 & (1<<15)) {
8960                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8961                 return 0;
8962         }
8963
8964         bnx2x_cl45_read(bp, phy,
8965                         MDIO_PMA_DEVAD,
8966                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8967
8968         /*
8969          * Bits 0..2 --> speed detected,
8970          * Bits 13..15--> link is down
8971          */
8972         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8973                 link_up = 1;
8974                 vars->line_speed = SPEED_10000;
8975                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
8976                            params->port);
8977         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8978                 link_up = 1;
8979                 vars->line_speed = SPEED_1000;
8980                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
8981                            params->port);
8982         } else {
8983                 link_up = 0;
8984                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
8985                            params->port);
8986         }
8987
8988         /* Capture 10G link fault. */
8989         if (vars->line_speed == SPEED_10000) {
8990                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8991                             MDIO_PMA_LASI_TXSTAT, &val1);
8992
8993                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8994                             MDIO_PMA_LASI_TXSTAT, &val1);
8995
8996                 if (val1 & (1<<0)) {
8997                         vars->fault_detected = 1;
8998                 }
8999         }
9000
9001         if (link_up) {
9002                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9003                 vars->duplex = DUPLEX_FULL;
9004                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9005         }
9006
9007         if ((DUAL_MEDIA(params)) &&
9008             (phy->req_line_speed == SPEED_1000)) {
9009                 bnx2x_cl45_read(bp, phy,
9010                                 MDIO_PMA_DEVAD,
9011                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9012                 /*
9013                  * In case of dual-media board and 1G, power up the XAUI side,
9014                  * otherwise power it down. For 10G it is done automatically
9015                  */
9016                 if (link_up)
9017                         val1 &= ~(3<<10);
9018                 else
9019                         val1 |= (3<<10);
9020                 bnx2x_cl45_write(bp, phy,
9021                                  MDIO_PMA_DEVAD,
9022                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9023         }
9024         return link_up;
9025 }
9026
9027 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9028                                   struct link_params *params)
9029 {
9030         struct bnx2x *bp = params->bp;
9031
9032         /* Enable/Disable PHY transmitter output */
9033         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9034
9035         /* Disable Transmitter */
9036         bnx2x_sfp_set_transmitter(params, phy, 0);
9037         /* Clear LASI */
9038         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9039
9040 }
9041
9042 /******************************************************************/
9043 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9044 /******************************************************************/
9045 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9046                                            struct link_params *params)
9047 {
9048         u16 val, fw_ver1, fw_ver2, cnt;
9049         u8 port;
9050         struct bnx2x *bp = params->bp;
9051
9052         port = params->port;
9053
9054         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
9055         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9056         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9057         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9058         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9059         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9060         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9061
9062         for (cnt = 0; cnt < 100; cnt++) {
9063                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9064                 if (val & 1)
9065                         break;
9066                 udelay(5);
9067         }
9068         if (cnt == 100) {
9069                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
9070                 bnx2x_save_spirom_version(bp, port, 0,
9071                                           phy->ver_addr);
9072                 return;
9073         }
9074
9075
9076         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9077         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9078         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9079         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9080         for (cnt = 0; cnt < 100; cnt++) {
9081                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9082                 if (val & 1)
9083                         break;
9084                 udelay(5);
9085         }
9086         if (cnt == 100) {
9087                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
9088                 bnx2x_save_spirom_version(bp, port, 0,
9089                                           phy->ver_addr);
9090                 return;
9091         }
9092
9093         /* lower 16 bits of the register SPI_FW_STATUS */
9094         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9095         /* upper 16 bits of register SPI_FW_STATUS */
9096         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9097
9098         bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9099                                   phy->ver_addr);
9100 }
9101
9102 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9103                                 struct bnx2x_phy *phy)
9104 {
9105         u16 val;
9106
9107         /* PHYC_CTL_LED_CTL */
9108         bnx2x_cl45_read(bp, phy,
9109                         MDIO_PMA_DEVAD,
9110                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9111         val &= 0xFE00;
9112         val |= 0x0092;
9113
9114         bnx2x_cl45_write(bp, phy,
9115                          MDIO_PMA_DEVAD,
9116                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9117
9118         bnx2x_cl45_write(bp, phy,
9119                          MDIO_PMA_DEVAD,
9120                          MDIO_PMA_REG_8481_LED1_MASK,
9121                          0x80);
9122
9123         bnx2x_cl45_write(bp, phy,
9124                          MDIO_PMA_DEVAD,
9125                          MDIO_PMA_REG_8481_LED2_MASK,
9126                          0x18);
9127
9128         /* Select activity source by Tx and Rx, as suggested by PHY AE */
9129         bnx2x_cl45_write(bp, phy,
9130                          MDIO_PMA_DEVAD,
9131                          MDIO_PMA_REG_8481_LED3_MASK,
9132                          0x0006);
9133
9134         /* Select the closest activity blink rate to that in 10/100/1000 */
9135         bnx2x_cl45_write(bp, phy,
9136                         MDIO_PMA_DEVAD,
9137                         MDIO_PMA_REG_8481_LED3_BLINK,
9138                         0);
9139
9140         bnx2x_cl45_read(bp, phy,
9141                         MDIO_PMA_DEVAD,
9142                         MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
9143         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9144
9145         bnx2x_cl45_write(bp, phy,
9146                          MDIO_PMA_DEVAD,
9147                          MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
9148
9149         /* 'Interrupt Mask' */
9150         bnx2x_cl45_write(bp, phy,
9151                          MDIO_AN_DEVAD,
9152                          0xFFFB, 0xFFFD);
9153 }
9154
9155 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9156                                        struct link_params *params,
9157                                        struct link_vars *vars)
9158 {
9159         struct bnx2x *bp = params->bp;
9160         u16 autoneg_val, an_1000_val, an_10_100_val;
9161         u16 tmp_req_line_speed;
9162
9163         tmp_req_line_speed = phy->req_line_speed;
9164         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9165                 if (phy->req_line_speed == SPEED_10000)
9166                         phy->req_line_speed = SPEED_AUTO_NEG;
9167
9168         /*
9169          * This phy uses the NIG latch mechanism since link indication
9170          * arrives through its LED4 and not via its LASI signal, so we
9171          * get steady signal instead of clear on read
9172          */
9173         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9174                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
9175
9176         bnx2x_cl45_write(bp, phy,
9177                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9178
9179         bnx2x_848xx_set_led(bp, phy);
9180
9181         /* set 1000 speed advertisement */
9182         bnx2x_cl45_read(bp, phy,
9183                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9184                         &an_1000_val);
9185
9186         bnx2x_ext_phy_set_pause(params, phy, vars);
9187         bnx2x_cl45_read(bp, phy,
9188                         MDIO_AN_DEVAD,
9189                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9190                         &an_10_100_val);
9191         bnx2x_cl45_read(bp, phy,
9192                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9193                         &autoneg_val);
9194         /* Disable forced speed */
9195         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9196         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9197
9198         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9199              (phy->speed_cap_mask &
9200              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9201             (phy->req_line_speed == SPEED_1000)) {
9202                 an_1000_val |= (1<<8);
9203                 autoneg_val |= (1<<9 | 1<<12);
9204                 if (phy->req_duplex == DUPLEX_FULL)
9205                         an_1000_val |= (1<<9);
9206                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9207         } else
9208                 an_1000_val &= ~((1<<8) | (1<<9));
9209
9210         bnx2x_cl45_write(bp, phy,
9211                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9212                          an_1000_val);
9213
9214         /* set 100 speed advertisement */
9215         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9216              (phy->speed_cap_mask &
9217               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9218                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
9219              (phy->supported &
9220               (SUPPORTED_100baseT_Half |
9221                SUPPORTED_100baseT_Full)))) {
9222                 an_10_100_val |= (1<<7);
9223                 /* Enable autoneg and restart autoneg for legacy speeds */
9224                 autoneg_val |= (1<<9 | 1<<12);
9225
9226                 if (phy->req_duplex == DUPLEX_FULL)
9227                         an_10_100_val |= (1<<8);
9228                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9229         }
9230         /* set 10 speed advertisement */
9231         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9232              (phy->speed_cap_mask &
9233               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9234                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9235              (phy->supported &
9236               (SUPPORTED_10baseT_Half |
9237                SUPPORTED_10baseT_Full)))) {
9238                 an_10_100_val |= (1<<5);
9239                 autoneg_val |= (1<<9 | 1<<12);
9240                 if (phy->req_duplex == DUPLEX_FULL)
9241                         an_10_100_val |= (1<<6);
9242                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9243         }
9244
9245         /* Only 10/100 are allowed to work in FORCE mode */
9246         if ((phy->req_line_speed == SPEED_100) &&
9247             (phy->supported &
9248              (SUPPORTED_100baseT_Half |
9249               SUPPORTED_100baseT_Full))) {
9250                 autoneg_val |= (1<<13);
9251                 /* Enabled AUTO-MDIX when autoneg is disabled */
9252                 bnx2x_cl45_write(bp, phy,
9253                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9254                                  (1<<15 | 1<<9 | 7<<0));
9255                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9256         }
9257         if ((phy->req_line_speed == SPEED_10) &&
9258             (phy->supported &
9259              (SUPPORTED_10baseT_Half |
9260               SUPPORTED_10baseT_Full))) {
9261                 /* Enabled AUTO-MDIX when autoneg is disabled */
9262                 bnx2x_cl45_write(bp, phy,
9263                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9264                                  (1<<15 | 1<<9 | 7<<0));
9265                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9266         }
9267
9268         bnx2x_cl45_write(bp, phy,
9269                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9270                          an_10_100_val);
9271
9272         if (phy->req_duplex == DUPLEX_FULL)
9273                 autoneg_val |= (1<<8);
9274
9275         /*
9276          * Always write this if this is not 84833.
9277          * For 84833, write it only when it's a forced speed.
9278          */
9279         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9280                 ((autoneg_val & (1<<12)) == 0))
9281                 bnx2x_cl45_write(bp, phy,
9282                          MDIO_AN_DEVAD,
9283                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9284
9285         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9286             (phy->speed_cap_mask &
9287              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9288                 (phy->req_line_speed == SPEED_10000)) {
9289                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9290                         /* Restart autoneg for 10G*/
9291
9292                         bnx2x_cl45_write(bp, phy,
9293                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9294                                  0x3200);
9295         } else
9296                 bnx2x_cl45_write(bp, phy,
9297                                  MDIO_AN_DEVAD,
9298                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9299                                  1);
9300
9301         /* Save spirom version */
9302         bnx2x_save_848xx_spirom_version(phy, params);
9303
9304         phy->req_line_speed = tmp_req_line_speed;
9305
9306         return 0;
9307 }
9308
9309 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9310                                   struct link_params *params,
9311                                   struct link_vars *vars)
9312 {
9313         struct bnx2x *bp = params->bp;
9314         /* Restore normal power mode*/
9315         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9316                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9317
9318         /* HW reset */
9319         bnx2x_ext_phy_hw_reset(bp, params->port);
9320         bnx2x_wait_reset_complete(bp, phy, params);
9321
9322         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9323         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9324 }
9325
9326
9327 #define PHY84833_HDSHK_WAIT 300
9328 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9329                                    struct link_params *params,
9330                                    struct link_vars *vars)
9331 {
9332         u32 idx;
9333         u32 pair_swap;
9334         u16 val;
9335         u16 data;
9336         struct bnx2x *bp = params->bp;
9337         /* Do pair swap */
9338
9339         /* Check for configuration. */
9340         pair_swap = REG_RD(bp, params->shmem_base +
9341                            offsetof(struct shmem_region,
9342                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9343                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9344
9345         if (pair_swap == 0)
9346                 return 0;
9347
9348         data = (u16)pair_swap;
9349
9350         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9351         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9352                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9353                         PHY84833_CMD_OPEN_OVERRIDE);
9354         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9355                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9356                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9357                 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9358                         break;
9359                 msleep(1);
9360         }
9361         if (idx >= PHY84833_HDSHK_WAIT) {
9362                 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
9363                 return -EINVAL;
9364         }
9365
9366         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9367                         MDIO_84833_TOP_CFG_SCRATCH_REG4,
9368                         data);
9369         /* Issue pair swap command */
9370         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9371                         MDIO_84833_TOP_CFG_SCRATCH_REG0,
9372                         PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
9373         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9374                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9375                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9376                 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9377                         (val == PHY84833_CMD_COMPLETE_ERROR))
9378                         break;
9379                 msleep(1);
9380         }
9381         if ((idx >= PHY84833_HDSHK_WAIT) ||
9382                 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9383                 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
9384                 return -EINVAL;
9385         }
9386         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9387                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9388                         PHY84833_CMD_CLEAR_COMPLETE);
9389         DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
9390         return 0;
9391 }
9392
9393
9394 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9395                                       u32 shmem_base_path[],
9396                                       u32 chip_id)
9397 {
9398         u32 reset_pin[2];
9399         u32 idx;
9400         u8 reset_gpios;
9401         if (CHIP_IS_E3(bp)) {
9402                 /* Assume that these will be GPIOs, not EPIOs. */
9403                 for (idx = 0; idx < 2; idx++) {
9404                         /* Map config param to register bit. */
9405                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9406                                 offsetof(struct shmem_region,
9407                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9408                         reset_pin[idx] = (reset_pin[idx] &
9409                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9410                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9411                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9412                         reset_pin[idx] = (1 << reset_pin[idx]);
9413                 }
9414                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9415         } else {
9416                 /* E2, look from diff place of shmem. */
9417                 for (idx = 0; idx < 2; idx++) {
9418                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9419                                 offsetof(struct shmem_region,
9420                                 dev_info.port_hw_config[0].default_cfg));
9421                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9422                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9423                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9424                         reset_pin[idx] = (1 << reset_pin[idx]);
9425                 }
9426                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9427         }
9428
9429         return reset_gpios;
9430 }
9431
9432 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9433                                 struct link_params *params)
9434 {
9435         struct bnx2x *bp = params->bp;
9436         u8 reset_gpios;
9437         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9438                                 offsetof(struct shmem2_region,
9439                                 other_shmem_base_addr));
9440
9441         u32 shmem_base_path[2];
9442         shmem_base_path[0] = params->shmem_base;
9443         shmem_base_path[1] = other_shmem_base_addr;
9444
9445         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9446                                                   params->chip_id);
9447
9448         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9449         udelay(10);
9450         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9451                 reset_gpios);
9452
9453         return 0;
9454 }
9455
9456 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
9457                                                 u32 shmem_base_path[],
9458                                                 u32 chip_id)
9459 {
9460         u8 reset_gpios;
9461
9462         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
9463
9464         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9465         udelay(10);
9466         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
9467         msleep(800);
9468         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
9469                 reset_gpios);
9470
9471         return 0;
9472 }
9473
9474 #define PHY84833_CONSTANT_LATENCY 1193
9475 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9476                                    struct link_params *params,
9477                                    struct link_vars *vars)
9478 {
9479         struct bnx2x *bp = params->bp;
9480         u8 port, initialize = 1;
9481         u16 val;
9482         u16 temp;
9483         u32 actual_phy_selection, cms_enable, idx;
9484         int rc = 0;
9485
9486         msleep(1);
9487
9488         if (!(CHIP_IS_E1(bp)))
9489                 port = BP_PATH(bp);
9490         else
9491                 port = params->port;
9492
9493         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9494                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9495                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9496                                port);
9497         } else {
9498                 /* MDIO reset */
9499                 bnx2x_cl45_write(bp, phy,
9500                                 MDIO_PMA_DEVAD,
9501                                 MDIO_PMA_REG_CTRL, 0x8000);
9502                 /* Bring PHY out of super isolate mode */
9503                 bnx2x_cl45_read(bp, phy,
9504                                 MDIO_CTL_DEVAD,
9505                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9506                 val &= ~MDIO_84833_SUPER_ISOLATE;
9507                 bnx2x_cl45_write(bp, phy,
9508                                 MDIO_CTL_DEVAD,
9509                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9510         }
9511
9512         bnx2x_wait_reset_complete(bp, phy, params);
9513
9514         /* Wait for GPHY to come out of reset */
9515         msleep(50);
9516
9517         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9518                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9519
9520         /*
9521          * BCM84823 requires that XGXS links up first @ 10G for normal behavior
9522          */
9523         temp = vars->line_speed;
9524         vars->line_speed = SPEED_10000;
9525         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9526         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9527         vars->line_speed = temp;
9528
9529         /* Set dual-media configuration according to configuration */
9530
9531         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9532                         MDIO_CTL_REG_84823_MEDIA, &val);
9533         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9534                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9535                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9536                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9537                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9538
9539         if (CHIP_IS_E3(bp)) {
9540                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9541                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9542         } else {
9543                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9544                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9545         }
9546
9547         actual_phy_selection = bnx2x_phy_selection(params);
9548
9549         switch (actual_phy_selection) {
9550         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9551                 /* Do nothing. Essentially this is like the priority copper */
9552                 break;
9553         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9554                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9555                 break;
9556         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9557                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9558                 break;
9559         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9560                 /* Do nothing here. The first PHY won't be initialized at all */
9561                 break;
9562         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9563                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9564                 initialize = 0;
9565                 break;
9566         }
9567         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9568                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9569
9570         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9571                          MDIO_CTL_REG_84823_MEDIA, val);
9572         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9573                    params->multi_phy_config, val);
9574
9575         /* AutogrEEEn */
9576         if (params->feature_config_flags &
9577                 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
9578                 /* Ensure that f/w is ready */
9579                 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9580                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9581                                         MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9582                         if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9583                                 break;
9584                         usleep_range(1000, 1000);
9585                 }
9586                 if (idx >= PHY84833_HDSHK_WAIT) {
9587                         DP(NETIF_MSG_LINK, "AutogrEEEn: FW not ready.\n");
9588                         return -EINVAL;
9589                 }
9590
9591                 /* Select EEE mode */
9592                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9593                                 MDIO_84833_TOP_CFG_SCRATCH_REG3,
9594                                 0x2);
9595
9596                 /* Set Idle and Latency */
9597                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9598                                 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9599                                 PHY84833_CONSTANT_LATENCY + 1);
9600
9601                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9602                                 MDIO_84833_TOP_CFG_DATA3_REG,
9603                                 PHY84833_CONSTANT_LATENCY + 1);
9604
9605                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9606                                 MDIO_84833_TOP_CFG_DATA4_REG,
9607                                 PHY84833_CONSTANT_LATENCY);
9608
9609                 /* Send EEE instruction to command register */
9610                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9611                                 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9612                                 PHY84833_DIAG_CMD_SET_EEE_MODE);
9613
9614                 /* Ensure that the command has completed */
9615                 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9616                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9617                                         MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9618                         if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9619                                 (val == PHY84833_CMD_COMPLETE_ERROR))
9620                                 break;
9621                         usleep_range(1000, 1000);
9622                 }
9623                 if ((idx >= PHY84833_HDSHK_WAIT) ||
9624                         (val == PHY84833_CMD_COMPLETE_ERROR)) {
9625                         DP(NETIF_MSG_LINK, "AutogrEEEn: command failed.\n");
9626                         return -EINVAL;
9627                 }
9628
9629                 /* Reset command handler */
9630                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9631                             MDIO_84833_TOP_CFG_SCRATCH_REG2,
9632                             PHY84833_CMD_CLEAR_COMPLETE);
9633         }
9634
9635         if (initialize)
9636                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9637         else
9638                 bnx2x_save_848xx_spirom_version(phy, params);
9639         /* 84833 PHY has a better feature and doesn't need to support this. */
9640         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9641                 cms_enable = REG_RD(bp, params->shmem_base +
9642                         offsetof(struct shmem_region,
9643                         dev_info.port_hw_config[params->port].default_cfg)) &
9644                         PORT_HW_CFG_ENABLE_CMS_MASK;
9645
9646                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9647                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9648                 if (cms_enable)
9649                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9650                 else
9651                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9652                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9653                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9654         }
9655
9656         return rc;
9657 }
9658
9659 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9660                                   struct link_params *params,
9661                                   struct link_vars *vars)
9662 {
9663         struct bnx2x *bp = params->bp;
9664         u16 val, val1, val2;
9665         u8 link_up = 0;
9666
9667
9668         /* Check 10G-BaseT link status */
9669         /* Check PMD signal ok */
9670         bnx2x_cl45_read(bp, phy,
9671                         MDIO_AN_DEVAD, 0xFFFA, &val1);
9672         bnx2x_cl45_read(bp, phy,
9673                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9674                         &val2);
9675         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9676
9677         /* Check link 10G */
9678         if (val2 & (1<<11)) {
9679                 vars->line_speed = SPEED_10000;
9680                 vars->duplex = DUPLEX_FULL;
9681                 link_up = 1;
9682                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9683         } else { /* Check Legacy speed link */
9684                 u16 legacy_status, legacy_speed;
9685
9686                 /* Enable expansion register 0x42 (Operation mode status) */
9687                 bnx2x_cl45_write(bp, phy,
9688                                  MDIO_AN_DEVAD,
9689                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9690
9691                 /* Get legacy speed operation status */
9692                 bnx2x_cl45_read(bp, phy,
9693                                 MDIO_AN_DEVAD,
9694                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9695                                 &legacy_status);
9696
9697                 DP(NETIF_MSG_LINK, "Legacy speed status"
9698                              " = 0x%x\n", legacy_status);
9699                 link_up = ((legacy_status & (1<<11)) == (1<<11));
9700                 if (link_up) {
9701                         legacy_speed = (legacy_status & (3<<9));
9702                         if (legacy_speed == (0<<9))
9703                                 vars->line_speed = SPEED_10;
9704                         else if (legacy_speed == (1<<9))
9705                                 vars->line_speed = SPEED_100;
9706                         else if (legacy_speed == (2<<9))
9707                                 vars->line_speed = SPEED_1000;
9708                         else /* Should not happen */
9709                                 vars->line_speed = 0;
9710
9711                         if (legacy_status & (1<<8))
9712                                 vars->duplex = DUPLEX_FULL;
9713                         else
9714                                 vars->duplex = DUPLEX_HALF;
9715
9716                         DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
9717                                    " is_duplex_full= %d\n", vars->line_speed,
9718                                    (vars->duplex == DUPLEX_FULL));
9719                         /* Check legacy speed AN resolution */
9720                         bnx2x_cl45_read(bp, phy,
9721                                         MDIO_AN_DEVAD,
9722                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9723                                         &val);
9724                         if (val & (1<<5))
9725                                 vars->link_status |=
9726                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9727                         bnx2x_cl45_read(bp, phy,
9728                                         MDIO_AN_DEVAD,
9729                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9730                                         &val);
9731                         if ((val & (1<<0)) == 0)
9732                                 vars->link_status |=
9733                                         LINK_STATUS_PARALLEL_DETECTION_USED;
9734                 }
9735         }
9736         if (link_up) {
9737                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9738                            vars->line_speed);
9739                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9740         }
9741
9742         return link_up;
9743 }
9744
9745
9746 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9747 {
9748         int status = 0;
9749         u32 spirom_ver;
9750         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9751         status = bnx2x_format_ver(spirom_ver, str, len);
9752         return status;
9753 }
9754
9755 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9756                                 struct link_params *params)
9757 {
9758         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9759                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9760         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9761                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9762 }
9763
9764 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9765                                         struct link_params *params)
9766 {
9767         bnx2x_cl45_write(params->bp, phy,
9768                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9769         bnx2x_cl45_write(params->bp, phy,
9770                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9771 }
9772
9773 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9774                                    struct link_params *params)
9775 {
9776         struct bnx2x *bp = params->bp;
9777         u8 port;
9778         u16 val16;
9779
9780         if (!(CHIP_IS_E1(bp)))
9781                 port = BP_PATH(bp);
9782         else
9783                 port = params->port;
9784
9785         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9786                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9787                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
9788                                port);
9789         } else {
9790                 bnx2x_cl45_read(bp, phy,
9791                                 MDIO_CTL_DEVAD,
9792                                 0x400f, &val16);
9793                 bnx2x_cl45_write(bp, phy,
9794                                 MDIO_PMA_DEVAD,
9795                                 MDIO_PMA_REG_CTRL, 0x800);
9796         }
9797 }
9798
9799 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
9800                                      struct link_params *params, u8 mode)
9801 {
9802         struct bnx2x *bp = params->bp;
9803         u16 val;
9804         u8 port;
9805
9806         if (!(CHIP_IS_E1(bp)))
9807                 port = BP_PATH(bp);
9808         else
9809                 port = params->port;
9810
9811         switch (mode) {
9812         case LED_MODE_OFF:
9813
9814                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9815
9816                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9817                     SHARED_HW_CFG_LED_EXTPHY1) {
9818
9819                         /* Set LED masks */
9820                         bnx2x_cl45_write(bp, phy,
9821                                         MDIO_PMA_DEVAD,
9822                                         MDIO_PMA_REG_8481_LED1_MASK,
9823                                         0x0);
9824
9825                         bnx2x_cl45_write(bp, phy,
9826                                         MDIO_PMA_DEVAD,
9827                                         MDIO_PMA_REG_8481_LED2_MASK,
9828                                         0x0);
9829
9830                         bnx2x_cl45_write(bp, phy,
9831                                         MDIO_PMA_DEVAD,
9832                                         MDIO_PMA_REG_8481_LED3_MASK,
9833                                         0x0);
9834
9835                         bnx2x_cl45_write(bp, phy,
9836                                         MDIO_PMA_DEVAD,
9837                                         MDIO_PMA_REG_8481_LED5_MASK,
9838                                         0x0);
9839
9840                 } else {
9841                         bnx2x_cl45_write(bp, phy,
9842                                          MDIO_PMA_DEVAD,
9843                                          MDIO_PMA_REG_8481_LED1_MASK,
9844                                          0x0);
9845                 }
9846                 break;
9847         case LED_MODE_FRONT_PANEL_OFF:
9848
9849                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
9850                    port);
9851
9852                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9853                     SHARED_HW_CFG_LED_EXTPHY1) {
9854
9855                         /* Set LED masks */
9856                         bnx2x_cl45_write(bp, phy,
9857                                          MDIO_PMA_DEVAD,
9858                                          MDIO_PMA_REG_8481_LED1_MASK,
9859                                          0x0);
9860
9861                         bnx2x_cl45_write(bp, phy,
9862                                          MDIO_PMA_DEVAD,
9863                                          MDIO_PMA_REG_8481_LED2_MASK,
9864                                          0x0);
9865
9866                         bnx2x_cl45_write(bp, phy,
9867                                          MDIO_PMA_DEVAD,
9868                                          MDIO_PMA_REG_8481_LED3_MASK,
9869                                          0x0);
9870
9871                         bnx2x_cl45_write(bp, phy,
9872                                          MDIO_PMA_DEVAD,
9873                                          MDIO_PMA_REG_8481_LED5_MASK,
9874                                          0x20);
9875
9876                 } else {
9877                         bnx2x_cl45_write(bp, phy,
9878                                          MDIO_PMA_DEVAD,
9879                                          MDIO_PMA_REG_8481_LED1_MASK,
9880                                          0x0);
9881                 }
9882                 break;
9883         case LED_MODE_ON:
9884
9885                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9886
9887                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9888                     SHARED_HW_CFG_LED_EXTPHY1) {
9889                         /* Set control reg */
9890                         bnx2x_cl45_read(bp, phy,
9891                                         MDIO_PMA_DEVAD,
9892                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9893                                         &val);
9894                         val &= 0x8000;
9895                         val |= 0x2492;
9896
9897                         bnx2x_cl45_write(bp, phy,
9898                                          MDIO_PMA_DEVAD,
9899                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
9900                                          val);
9901
9902                         /* Set LED masks */
9903                         bnx2x_cl45_write(bp, phy,
9904                                          MDIO_PMA_DEVAD,
9905                                          MDIO_PMA_REG_8481_LED1_MASK,
9906                                          0x0);
9907
9908                         bnx2x_cl45_write(bp, phy,
9909                                          MDIO_PMA_DEVAD,
9910                                          MDIO_PMA_REG_8481_LED2_MASK,
9911                                          0x20);
9912
9913                         bnx2x_cl45_write(bp, phy,
9914                                          MDIO_PMA_DEVAD,
9915                                          MDIO_PMA_REG_8481_LED3_MASK,
9916                                          0x20);
9917
9918                         bnx2x_cl45_write(bp, phy,
9919                                          MDIO_PMA_DEVAD,
9920                                          MDIO_PMA_REG_8481_LED5_MASK,
9921                                          0x0);
9922                 } else {
9923                         bnx2x_cl45_write(bp, phy,
9924                                          MDIO_PMA_DEVAD,
9925                                          MDIO_PMA_REG_8481_LED1_MASK,
9926                                          0x20);
9927                 }
9928                 break;
9929
9930         case LED_MODE_OPER:
9931
9932                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
9933
9934                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9935                     SHARED_HW_CFG_LED_EXTPHY1) {
9936
9937                         /* Set control reg */
9938                         bnx2x_cl45_read(bp, phy,
9939                                         MDIO_PMA_DEVAD,
9940                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9941                                         &val);
9942
9943                         if (!((val &
9944                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
9945                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
9946                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
9947                                 bnx2x_cl45_write(bp, phy,
9948                                                  MDIO_PMA_DEVAD,
9949                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
9950                                                  0xa492);
9951                         }
9952
9953                         /* Set LED masks */
9954                         bnx2x_cl45_write(bp, phy,
9955                                          MDIO_PMA_DEVAD,
9956                                          MDIO_PMA_REG_8481_LED1_MASK,
9957                                          0x10);
9958
9959                         bnx2x_cl45_write(bp, phy,
9960                                          MDIO_PMA_DEVAD,
9961                                          MDIO_PMA_REG_8481_LED2_MASK,
9962                                          0x80);
9963
9964                         bnx2x_cl45_write(bp, phy,
9965                                          MDIO_PMA_DEVAD,
9966                                          MDIO_PMA_REG_8481_LED3_MASK,
9967                                          0x98);
9968
9969                         bnx2x_cl45_write(bp, phy,
9970                                          MDIO_PMA_DEVAD,
9971                                          MDIO_PMA_REG_8481_LED5_MASK,
9972                                          0x40);
9973
9974                 } else {
9975                         bnx2x_cl45_write(bp, phy,
9976                                          MDIO_PMA_DEVAD,
9977                                          MDIO_PMA_REG_8481_LED1_MASK,
9978                                          0x80);
9979
9980                         /* Tell LED3 to blink on source */
9981                         bnx2x_cl45_read(bp, phy,
9982                                         MDIO_PMA_DEVAD,
9983                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9984                                         &val);
9985                         val &= ~(7<<6);
9986                         val |= (1<<6); /* A83B[8:6]= 1 */
9987                         bnx2x_cl45_write(bp, phy,
9988                                          MDIO_PMA_DEVAD,
9989                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
9990                                          val);
9991                 }
9992                 break;
9993         }
9994
9995         /*
9996          * This is a workaround for E3+84833 until autoneg
9997          * restart is fixed in f/w
9998          */
9999         if (CHIP_IS_E3(bp)) {
10000                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10001                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10002         }
10003 }
10004
10005 /******************************************************************/
10006 /*                      54618SE PHY SECTION                       */
10007 /******************************************************************/
10008 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10009                                                struct link_params *params,
10010                                                struct link_vars *vars)
10011 {
10012         struct bnx2x *bp = params->bp;
10013         u8 port;
10014         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10015         u32 cfg_pin;
10016
10017         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10018         usleep_range(1000, 1000);
10019
10020         /* This works with E3 only, no need to check the chip
10021            before determining the port. */
10022         port = params->port;
10023
10024         cfg_pin = (REG_RD(bp, params->shmem_base +
10025                         offsetof(struct shmem_region,
10026                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10027                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10028                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10029
10030         /* Drive pin high to bring the GPHY out of reset. */
10031         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10032
10033         /* wait for GPHY to reset */
10034         msleep(50);
10035
10036         /* reset phy */
10037         bnx2x_cl22_write(bp, phy,
10038                          MDIO_PMA_REG_CTRL, 0x8000);
10039         bnx2x_wait_reset_complete(bp, phy, params);
10040
10041         /*wait for GPHY to reset */
10042         msleep(50);
10043
10044         /* Configure LED4: set to INTR (0x6). */
10045         /* Accessing shadow register 0xe. */
10046         bnx2x_cl22_write(bp, phy,
10047                         MDIO_REG_GPHY_SHADOW,
10048                         MDIO_REG_GPHY_SHADOW_LED_SEL2);
10049         bnx2x_cl22_read(bp, phy,
10050                         MDIO_REG_GPHY_SHADOW,
10051                         &temp);
10052         temp &= ~(0xf << 4);
10053         temp |= (0x6 << 4);
10054         bnx2x_cl22_write(bp, phy,
10055                         MDIO_REG_GPHY_SHADOW,
10056                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10057         /* Configure INTR based on link status change. */
10058         bnx2x_cl22_write(bp, phy,
10059                         MDIO_REG_INTR_MASK,
10060                         ~MDIO_REG_INTR_MASK_LINK_STATUS);
10061
10062         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10063         bnx2x_cl22_write(bp, phy,
10064                         MDIO_REG_GPHY_SHADOW,
10065                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10066         bnx2x_cl22_read(bp, phy,
10067                         MDIO_REG_GPHY_SHADOW,
10068                         &temp);
10069         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10070         bnx2x_cl22_write(bp, phy,
10071                         MDIO_REG_GPHY_SHADOW,
10072                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10073
10074         /* Set up fc */
10075         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10076         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10077         fc_val = 0;
10078         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10079                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10080                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10081
10082         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10083                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10084                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10085
10086         /* read all advertisement */
10087         bnx2x_cl22_read(bp, phy,
10088                         0x09,
10089                         &an_1000_val);
10090
10091         bnx2x_cl22_read(bp, phy,
10092                         0x04,
10093                         &an_10_100_val);
10094
10095         bnx2x_cl22_read(bp, phy,
10096                         MDIO_PMA_REG_CTRL,
10097                         &autoneg_val);
10098
10099         /* Disable forced speed */
10100         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10101         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10102                            (1<<11));
10103
10104         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10105                         (phy->speed_cap_mask &
10106                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10107                         (phy->req_line_speed == SPEED_1000)) {
10108                 an_1000_val |= (1<<8);
10109                 autoneg_val |= (1<<9 | 1<<12);
10110                 if (phy->req_duplex == DUPLEX_FULL)
10111                         an_1000_val |= (1<<9);
10112                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10113         } else
10114                 an_1000_val &= ~((1<<8) | (1<<9));
10115
10116         bnx2x_cl22_write(bp, phy,
10117                         0x09,
10118                         an_1000_val);
10119         bnx2x_cl22_read(bp, phy,
10120                         0x09,
10121                         &an_1000_val);
10122
10123         /* set 100 speed advertisement */
10124         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10125                         (phy->speed_cap_mask &
10126                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10127                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10128                 an_10_100_val |= (1<<7);
10129                 /* Enable autoneg and restart autoneg for legacy speeds */
10130                 autoneg_val |= (1<<9 | 1<<12);
10131
10132                 if (phy->req_duplex == DUPLEX_FULL)
10133                         an_10_100_val |= (1<<8);
10134                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10135         }
10136
10137         /* set 10 speed advertisement */
10138         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10139                         (phy->speed_cap_mask &
10140                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10141                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10142                 an_10_100_val |= (1<<5);
10143                 autoneg_val |= (1<<9 | 1<<12);
10144                 if (phy->req_duplex == DUPLEX_FULL)
10145                         an_10_100_val |= (1<<6);
10146                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10147         }
10148
10149         /* Only 10/100 are allowed to work in FORCE mode */
10150         if (phy->req_line_speed == SPEED_100) {
10151                 autoneg_val |= (1<<13);
10152                 /* Enabled AUTO-MDIX when autoneg is disabled */
10153                 bnx2x_cl22_write(bp, phy,
10154                                 0x18,
10155                                 (1<<15 | 1<<9 | 7<<0));
10156                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10157         }
10158         if (phy->req_line_speed == SPEED_10) {
10159                 /* Enabled AUTO-MDIX when autoneg is disabled */
10160                 bnx2x_cl22_write(bp, phy,
10161                                 0x18,
10162                                 (1<<15 | 1<<9 | 7<<0));
10163                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10164         }
10165
10166         /* Check if we should turn on Auto-GrEEEn */
10167         bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10168         if (temp == MDIO_REG_GPHY_ID_54618SE) {
10169                 if (params->feature_config_flags &
10170                     FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10171                         temp = 6;
10172                         DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10173                 } else {
10174                         temp = 0;
10175                         DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10176                 }
10177                 bnx2x_cl22_write(bp, phy,
10178                                  MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10179                 bnx2x_cl22_write(bp, phy,
10180                                  MDIO_REG_GPHY_CL45_DATA_REG,
10181                                  MDIO_REG_GPHY_EEE_ADV);
10182                 bnx2x_cl22_write(bp, phy,
10183                                  MDIO_REG_GPHY_CL45_ADDR_REG,
10184                                  (0x1 << 14) | MDIO_AN_DEVAD);
10185                 bnx2x_cl22_write(bp, phy,
10186                                  MDIO_REG_GPHY_CL45_DATA_REG,
10187                                  temp);
10188         }
10189
10190         bnx2x_cl22_write(bp, phy,
10191                         0x04,
10192                         an_10_100_val | fc_val);
10193
10194         if (phy->req_duplex == DUPLEX_FULL)
10195                 autoneg_val |= (1<<8);
10196
10197         bnx2x_cl22_write(bp, phy,
10198                         MDIO_PMA_REG_CTRL, autoneg_val);
10199
10200         return 0;
10201 }
10202
10203 static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
10204                                        struct link_params *params, u8 mode)
10205 {
10206         struct bnx2x *bp = params->bp;
10207         DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
10208         switch (mode) {
10209         case LED_MODE_FRONT_PANEL_OFF:
10210         case LED_MODE_OFF:
10211         case LED_MODE_OPER:
10212         case LED_MODE_ON:
10213         default:
10214                 break;
10215         }
10216         return;
10217 }
10218
10219 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10220                                      struct link_params *params)
10221 {
10222         struct bnx2x *bp = params->bp;
10223         u32 cfg_pin;
10224         u8 port;
10225
10226         /*
10227          * In case of no EPIO routed to reset the GPHY, put it
10228          * in low power mode.
10229          */
10230         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10231         /*
10232          * This works with E3 only, no need to check the chip
10233          * before determining the port.
10234          */
10235         port = params->port;
10236         cfg_pin = (REG_RD(bp, params->shmem_base +
10237                         offsetof(struct shmem_region,
10238                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10239                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10240                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10241
10242         /* Drive pin low to put GPHY in reset. */
10243         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10244 }
10245
10246 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10247                                     struct link_params *params,
10248                                     struct link_vars *vars)
10249 {
10250         struct bnx2x *bp = params->bp;
10251         u16 val;
10252         u8 link_up = 0;
10253         u16 legacy_status, legacy_speed;
10254
10255         /* Get speed operation status */
10256         bnx2x_cl22_read(bp, phy,
10257                         0x19,
10258                         &legacy_status);
10259         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10260
10261         /* Read status to clear the PHY interrupt. */
10262         bnx2x_cl22_read(bp, phy,
10263                         MDIO_REG_INTR_STATUS,
10264                         &val);
10265
10266         link_up = ((legacy_status & (1<<2)) == (1<<2));
10267
10268         if (link_up) {
10269                 legacy_speed = (legacy_status & (7<<8));
10270                 if (legacy_speed == (7<<8)) {
10271                         vars->line_speed = SPEED_1000;
10272                         vars->duplex = DUPLEX_FULL;
10273                 } else if (legacy_speed == (6<<8)) {
10274                         vars->line_speed = SPEED_1000;
10275                         vars->duplex = DUPLEX_HALF;
10276                 } else if (legacy_speed == (5<<8)) {
10277                         vars->line_speed = SPEED_100;
10278                         vars->duplex = DUPLEX_FULL;
10279                 }
10280                 /* Omitting 100Base-T4 for now */
10281                 else if (legacy_speed == (3<<8)) {
10282                         vars->line_speed = SPEED_100;
10283                         vars->duplex = DUPLEX_HALF;
10284                 } else if (legacy_speed == (2<<8)) {
10285                         vars->line_speed = SPEED_10;
10286                         vars->duplex = DUPLEX_FULL;
10287                 } else if (legacy_speed == (1<<8)) {
10288                         vars->line_speed = SPEED_10;
10289                         vars->duplex = DUPLEX_HALF;
10290                 } else /* Should not happen */
10291                         vars->line_speed = 0;
10292
10293                 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
10294                            " is_duplex_full= %d\n", vars->line_speed,
10295                            (vars->duplex == DUPLEX_FULL));
10296
10297                 /* Check legacy speed AN resolution */
10298                 bnx2x_cl22_read(bp, phy,
10299                                 0x01,
10300                                 &val);
10301                 if (val & (1<<5))
10302                         vars->link_status |=
10303                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10304                 bnx2x_cl22_read(bp, phy,
10305                                 0x06,
10306                                 &val);
10307                 if ((val & (1<<0)) == 0)
10308                         vars->link_status |=
10309                                 LINK_STATUS_PARALLEL_DETECTION_USED;
10310
10311                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10312                            vars->line_speed);
10313
10314                 /* Report whether EEE is resolved. */
10315                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10316                 if (val == MDIO_REG_GPHY_ID_54618SE) {
10317                         if (vars->link_status &
10318                             LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10319                                 val = 0;
10320                         else {
10321                                 bnx2x_cl22_write(bp, phy,
10322                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10323                                         MDIO_AN_DEVAD);
10324                                 bnx2x_cl22_write(bp, phy,
10325                                         MDIO_REG_GPHY_CL45_DATA_REG,
10326                                         MDIO_REG_GPHY_EEE_RESOLVED);
10327                                 bnx2x_cl22_write(bp, phy,
10328                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10329                                         (0x1 << 14) | MDIO_AN_DEVAD);
10330                                 bnx2x_cl22_read(bp, phy,
10331                                         MDIO_REG_GPHY_CL45_DATA_REG,
10332                                         &val);
10333                         }
10334                         DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10335                 }
10336
10337                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10338         }
10339         return link_up;
10340 }
10341
10342 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10343                                           struct link_params *params)
10344 {
10345         struct bnx2x *bp = params->bp;
10346         u16 val;
10347         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10348
10349         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10350
10351         /* Enable master/slave manual mmode and set to master */
10352         /* mii write 9 [bits set 11 12] */
10353         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10354
10355         /* forced 1G and disable autoneg */
10356         /* set val [mii read 0] */
10357         /* set val [expr $val & [bits clear 6 12 13]] */
10358         /* set val [expr $val | [bits set 6 8]] */
10359         /* mii write 0 $val */
10360         bnx2x_cl22_read(bp, phy, 0x00, &val);
10361         val &= ~((1<<6) | (1<<12) | (1<<13));
10362         val |= (1<<6) | (1<<8);
10363         bnx2x_cl22_write(bp, phy, 0x00, val);
10364
10365         /* Set external loopback and Tx using 6dB coding */
10366         /* mii write 0x18 7 */
10367         /* set val [mii read 0x18] */
10368         /* mii write 0x18 [expr $val | [bits set 10 15]] */
10369         bnx2x_cl22_write(bp, phy, 0x18, 7);
10370         bnx2x_cl22_read(bp, phy, 0x18, &val);
10371         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10372
10373         /* This register opens the gate for the UMAC despite its name */
10374         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10375
10376         /*
10377          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10378          * length used by the MAC receive logic to check frames.
10379          */
10380         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10381 }
10382
10383 /******************************************************************/
10384 /*                      SFX7101 PHY SECTION                       */
10385 /******************************************************************/
10386 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10387                                        struct link_params *params)
10388 {
10389         struct bnx2x *bp = params->bp;
10390         /* SFX7101_XGXS_TEST1 */
10391         bnx2x_cl45_write(bp, phy,
10392                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10393 }
10394
10395 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10396                                   struct link_params *params,
10397                                   struct link_vars *vars)
10398 {
10399         u16 fw_ver1, fw_ver2, val;
10400         struct bnx2x *bp = params->bp;
10401         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10402
10403         /* Restore normal power mode*/
10404         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10405                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10406         /* HW reset */
10407         bnx2x_ext_phy_hw_reset(bp, params->port);
10408         bnx2x_wait_reset_complete(bp, phy, params);
10409
10410         bnx2x_cl45_write(bp, phy,
10411                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10412         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10413         bnx2x_cl45_write(bp, phy,
10414                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10415
10416         bnx2x_ext_phy_set_pause(params, phy, vars);
10417         /* Restart autoneg */
10418         bnx2x_cl45_read(bp, phy,
10419                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10420         val |= 0x200;
10421         bnx2x_cl45_write(bp, phy,
10422                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10423
10424         /* Save spirom version */
10425         bnx2x_cl45_read(bp, phy,
10426                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10427
10428         bnx2x_cl45_read(bp, phy,
10429                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10430         bnx2x_save_spirom_version(bp, params->port,
10431                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10432         return 0;
10433 }
10434
10435 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10436                                  struct link_params *params,
10437                                  struct link_vars *vars)
10438 {
10439         struct bnx2x *bp = params->bp;
10440         u8 link_up;
10441         u16 val1, val2;
10442         bnx2x_cl45_read(bp, phy,
10443                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10444         bnx2x_cl45_read(bp, phy,
10445                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10446         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10447                    val2, val1);
10448         bnx2x_cl45_read(bp, phy,
10449                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10450         bnx2x_cl45_read(bp, phy,
10451                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10452         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10453                    val2, val1);
10454         link_up = ((val1 & 4) == 4);
10455         /* if link is up print the AN outcome of the SFX7101 PHY */
10456         if (link_up) {
10457                 bnx2x_cl45_read(bp, phy,
10458                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10459                                 &val2);
10460                 vars->line_speed = SPEED_10000;
10461                 vars->duplex = DUPLEX_FULL;
10462                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10463                            val2, (val2 & (1<<14)));
10464                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10465                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10466         }
10467         return link_up;
10468 }
10469
10470 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10471 {
10472         if (*len < 5)
10473                 return -EINVAL;
10474         str[0] = (spirom_ver & 0xFF);
10475         str[1] = (spirom_ver & 0xFF00) >> 8;
10476         str[2] = (spirom_ver & 0xFF0000) >> 16;
10477         str[3] = (spirom_ver & 0xFF000000) >> 24;
10478         str[4] = '\0';
10479         *len -= 5;
10480         return 0;
10481 }
10482
10483 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10484 {
10485         u16 val, cnt;
10486
10487         bnx2x_cl45_read(bp, phy,
10488                         MDIO_PMA_DEVAD,
10489                         MDIO_PMA_REG_7101_RESET, &val);
10490
10491         for (cnt = 0; cnt < 10; cnt++) {
10492                 msleep(50);
10493                 /* Writes a self-clearing reset */
10494                 bnx2x_cl45_write(bp, phy,
10495                                  MDIO_PMA_DEVAD,
10496                                  MDIO_PMA_REG_7101_RESET,
10497                                  (val | (1<<15)));
10498                 /* Wait for clear */
10499                 bnx2x_cl45_read(bp, phy,
10500                                 MDIO_PMA_DEVAD,
10501                                 MDIO_PMA_REG_7101_RESET, &val);
10502
10503                 if ((val & (1<<15)) == 0)
10504                         break;
10505         }
10506 }
10507
10508 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10509                                 struct link_params *params) {
10510         /* Low power mode is controlled by GPIO 2 */
10511         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10512                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10513         /* The PHY reset is controlled by GPIO 1 */
10514         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10515                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10516 }
10517
10518 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10519                                     struct link_params *params, u8 mode)
10520 {
10521         u16 val = 0;
10522         struct bnx2x *bp = params->bp;
10523         switch (mode) {
10524         case LED_MODE_FRONT_PANEL_OFF:
10525         case LED_MODE_OFF:
10526                 val = 2;
10527                 break;
10528         case LED_MODE_ON:
10529                 val = 1;
10530                 break;
10531         case LED_MODE_OPER:
10532                 val = 0;
10533                 break;
10534         }
10535         bnx2x_cl45_write(bp, phy,
10536                          MDIO_PMA_DEVAD,
10537                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
10538                          val);
10539 }
10540
10541 /******************************************************************/
10542 /*                      STATIC PHY DECLARATION                    */
10543 /******************************************************************/
10544
10545 static struct bnx2x_phy phy_null = {
10546         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10547         .addr           = 0,
10548         .def_md_devad   = 0,
10549         .flags          = FLAGS_INIT_XGXS_FIRST,
10550         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10551         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10552         .mdio_ctrl      = 0,
10553         .supported      = 0,
10554         .media_type     = ETH_PHY_NOT_PRESENT,
10555         .ver_addr       = 0,
10556         .req_flow_ctrl  = 0,
10557         .req_line_speed = 0,
10558         .speed_cap_mask = 0,
10559         .req_duplex     = 0,
10560         .rsrv           = 0,
10561         .config_init    = (config_init_t)NULL,
10562         .read_status    = (read_status_t)NULL,
10563         .link_reset     = (link_reset_t)NULL,
10564         .config_loopback = (config_loopback_t)NULL,
10565         .format_fw_ver  = (format_fw_ver_t)NULL,
10566         .hw_reset       = (hw_reset_t)NULL,
10567         .set_link_led   = (set_link_led_t)NULL,
10568         .phy_specific_func = (phy_specific_func_t)NULL
10569 };
10570
10571 static struct bnx2x_phy phy_serdes = {
10572         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10573         .addr           = 0xff,
10574         .def_md_devad   = 0,
10575         .flags          = 0,
10576         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10577         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10578         .mdio_ctrl      = 0,
10579         .supported      = (SUPPORTED_10baseT_Half |
10580                            SUPPORTED_10baseT_Full |
10581                            SUPPORTED_100baseT_Half |
10582                            SUPPORTED_100baseT_Full |
10583                            SUPPORTED_1000baseT_Full |
10584                            SUPPORTED_2500baseX_Full |
10585                            SUPPORTED_TP |
10586                            SUPPORTED_Autoneg |
10587                            SUPPORTED_Pause |
10588                            SUPPORTED_Asym_Pause),
10589         .media_type     = ETH_PHY_BASE_T,
10590         .ver_addr       = 0,
10591         .req_flow_ctrl  = 0,
10592         .req_line_speed = 0,
10593         .speed_cap_mask = 0,
10594         .req_duplex     = 0,
10595         .rsrv           = 0,
10596         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10597         .read_status    = (read_status_t)bnx2x_link_settings_status,
10598         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10599         .config_loopback = (config_loopback_t)NULL,
10600         .format_fw_ver  = (format_fw_ver_t)NULL,
10601         .hw_reset       = (hw_reset_t)NULL,
10602         .set_link_led   = (set_link_led_t)NULL,
10603         .phy_specific_func = (phy_specific_func_t)NULL
10604 };
10605
10606 static struct bnx2x_phy phy_xgxs = {
10607         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10608         .addr           = 0xff,
10609         .def_md_devad   = 0,
10610         .flags          = 0,
10611         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10612         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10613         .mdio_ctrl      = 0,
10614         .supported      = (SUPPORTED_10baseT_Half |
10615                            SUPPORTED_10baseT_Full |
10616                            SUPPORTED_100baseT_Half |
10617                            SUPPORTED_100baseT_Full |
10618                            SUPPORTED_1000baseT_Full |
10619                            SUPPORTED_2500baseX_Full |
10620                            SUPPORTED_10000baseT_Full |
10621                            SUPPORTED_FIBRE |
10622                            SUPPORTED_Autoneg |
10623                            SUPPORTED_Pause |
10624                            SUPPORTED_Asym_Pause),
10625         .media_type     = ETH_PHY_CX4,
10626         .ver_addr       = 0,
10627         .req_flow_ctrl  = 0,
10628         .req_line_speed = 0,
10629         .speed_cap_mask = 0,
10630         .req_duplex     = 0,
10631         .rsrv           = 0,
10632         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10633         .read_status    = (read_status_t)bnx2x_link_settings_status,
10634         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10635         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10636         .format_fw_ver  = (format_fw_ver_t)NULL,
10637         .hw_reset       = (hw_reset_t)NULL,
10638         .set_link_led   = (set_link_led_t)NULL,
10639         .phy_specific_func = (phy_specific_func_t)NULL
10640 };
10641 static struct bnx2x_phy phy_warpcore = {
10642         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10643         .addr           = 0xff,
10644         .def_md_devad   = 0,
10645         .flags          = FLAGS_HW_LOCK_REQUIRED,
10646         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10647         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10648         .mdio_ctrl      = 0,
10649         .supported      = (SUPPORTED_10baseT_Half |
10650                              SUPPORTED_10baseT_Full |
10651                              SUPPORTED_100baseT_Half |
10652                              SUPPORTED_100baseT_Full |
10653                              SUPPORTED_1000baseT_Full |
10654                              SUPPORTED_10000baseT_Full |
10655                              SUPPORTED_20000baseKR2_Full |
10656                              SUPPORTED_20000baseMLD2_Full |
10657                              SUPPORTED_FIBRE |
10658                              SUPPORTED_Autoneg |
10659                              SUPPORTED_Pause |
10660                              SUPPORTED_Asym_Pause),
10661         .media_type     = ETH_PHY_UNSPECIFIED,
10662         .ver_addr       = 0,
10663         .req_flow_ctrl  = 0,
10664         .req_line_speed = 0,
10665         .speed_cap_mask = 0,
10666         /* req_duplex = */0,
10667         /* rsrv = */0,
10668         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
10669         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
10670         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
10671         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10672         .format_fw_ver  = (format_fw_ver_t)NULL,
10673         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
10674         .set_link_led   = (set_link_led_t)NULL,
10675         .phy_specific_func = (phy_specific_func_t)NULL
10676 };
10677
10678
10679 static struct bnx2x_phy phy_7101 = {
10680         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10681         .addr           = 0xff,
10682         .def_md_devad   = 0,
10683         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10684         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10685         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10686         .mdio_ctrl      = 0,
10687         .supported      = (SUPPORTED_10000baseT_Full |
10688                            SUPPORTED_TP |
10689                            SUPPORTED_Autoneg |
10690                            SUPPORTED_Pause |
10691                            SUPPORTED_Asym_Pause),
10692         .media_type     = ETH_PHY_BASE_T,
10693         .ver_addr       = 0,
10694         .req_flow_ctrl  = 0,
10695         .req_line_speed = 0,
10696         .speed_cap_mask = 0,
10697         .req_duplex     = 0,
10698         .rsrv           = 0,
10699         .config_init    = (config_init_t)bnx2x_7101_config_init,
10700         .read_status    = (read_status_t)bnx2x_7101_read_status,
10701         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10702         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10703         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
10704         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
10705         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
10706         .phy_specific_func = (phy_specific_func_t)NULL
10707 };
10708 static struct bnx2x_phy phy_8073 = {
10709         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10710         .addr           = 0xff,
10711         .def_md_devad   = 0,
10712         .flags          = FLAGS_HW_LOCK_REQUIRED,
10713         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10714         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10715         .mdio_ctrl      = 0,
10716         .supported      = (SUPPORTED_10000baseT_Full |
10717                            SUPPORTED_2500baseX_Full |
10718                            SUPPORTED_1000baseT_Full |
10719                            SUPPORTED_FIBRE |
10720                            SUPPORTED_Autoneg |
10721                            SUPPORTED_Pause |
10722                            SUPPORTED_Asym_Pause),
10723         .media_type     = ETH_PHY_KR,
10724         .ver_addr       = 0,
10725         .req_flow_ctrl  = 0,
10726         .req_line_speed = 0,
10727         .speed_cap_mask = 0,
10728         .req_duplex     = 0,
10729         .rsrv           = 0,
10730         .config_init    = (config_init_t)bnx2x_8073_config_init,
10731         .read_status    = (read_status_t)bnx2x_8073_read_status,
10732         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
10733         .config_loopback = (config_loopback_t)NULL,
10734         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10735         .hw_reset       = (hw_reset_t)NULL,
10736         .set_link_led   = (set_link_led_t)NULL,
10737         .phy_specific_func = (phy_specific_func_t)NULL
10738 };
10739 static struct bnx2x_phy phy_8705 = {
10740         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10741         .addr           = 0xff,
10742         .def_md_devad   = 0,
10743         .flags          = FLAGS_INIT_XGXS_FIRST,
10744         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10745         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10746         .mdio_ctrl      = 0,
10747         .supported      = (SUPPORTED_10000baseT_Full |
10748                            SUPPORTED_FIBRE |
10749                            SUPPORTED_Pause |
10750                            SUPPORTED_Asym_Pause),
10751         .media_type     = ETH_PHY_XFP_FIBER,
10752         .ver_addr       = 0,
10753         .req_flow_ctrl  = 0,
10754         .req_line_speed = 0,
10755         .speed_cap_mask = 0,
10756         .req_duplex     = 0,
10757         .rsrv           = 0,
10758         .config_init    = (config_init_t)bnx2x_8705_config_init,
10759         .read_status    = (read_status_t)bnx2x_8705_read_status,
10760         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10761         .config_loopback = (config_loopback_t)NULL,
10762         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
10763         .hw_reset       = (hw_reset_t)NULL,
10764         .set_link_led   = (set_link_led_t)NULL,
10765         .phy_specific_func = (phy_specific_func_t)NULL
10766 };
10767 static struct bnx2x_phy phy_8706 = {
10768         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
10769         .addr           = 0xff,
10770         .def_md_devad   = 0,
10771         .flags          = FLAGS_INIT_XGXS_FIRST,
10772         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10773         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10774         .mdio_ctrl      = 0,
10775         .supported      = (SUPPORTED_10000baseT_Full |
10776                            SUPPORTED_1000baseT_Full |
10777                            SUPPORTED_FIBRE |
10778                            SUPPORTED_Pause |
10779                            SUPPORTED_Asym_Pause),
10780         .media_type     = ETH_PHY_SFP_FIBER,
10781         .ver_addr       = 0,
10782         .req_flow_ctrl  = 0,
10783         .req_line_speed = 0,
10784         .speed_cap_mask = 0,
10785         .req_duplex     = 0,
10786         .rsrv           = 0,
10787         .config_init    = (config_init_t)bnx2x_8706_config_init,
10788         .read_status    = (read_status_t)bnx2x_8706_read_status,
10789         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10790         .config_loopback = (config_loopback_t)NULL,
10791         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10792         .hw_reset       = (hw_reset_t)NULL,
10793         .set_link_led   = (set_link_led_t)NULL,
10794         .phy_specific_func = (phy_specific_func_t)NULL
10795 };
10796
10797 static struct bnx2x_phy phy_8726 = {
10798         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
10799         .addr           = 0xff,
10800         .def_md_devad   = 0,
10801         .flags          = (FLAGS_HW_LOCK_REQUIRED |
10802                            FLAGS_INIT_XGXS_FIRST),
10803         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10804         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10805         .mdio_ctrl      = 0,
10806         .supported      = (SUPPORTED_10000baseT_Full |
10807                            SUPPORTED_1000baseT_Full |
10808                            SUPPORTED_Autoneg |
10809                            SUPPORTED_FIBRE |
10810                            SUPPORTED_Pause |
10811                            SUPPORTED_Asym_Pause),
10812         .media_type     = ETH_PHY_NOT_PRESENT,
10813         .ver_addr       = 0,
10814         .req_flow_ctrl  = 0,
10815         .req_line_speed = 0,
10816         .speed_cap_mask = 0,
10817         .req_duplex     = 0,
10818         .rsrv           = 0,
10819         .config_init    = (config_init_t)bnx2x_8726_config_init,
10820         .read_status    = (read_status_t)bnx2x_8726_read_status,
10821         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
10822         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
10823         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10824         .hw_reset       = (hw_reset_t)NULL,
10825         .set_link_led   = (set_link_led_t)NULL,
10826         .phy_specific_func = (phy_specific_func_t)NULL
10827 };
10828
10829 static struct bnx2x_phy phy_8727 = {
10830         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
10831         .addr           = 0xff,
10832         .def_md_devad   = 0,
10833         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10834         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10835         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10836         .mdio_ctrl      = 0,
10837         .supported      = (SUPPORTED_10000baseT_Full |
10838                            SUPPORTED_1000baseT_Full |
10839                            SUPPORTED_FIBRE |
10840                            SUPPORTED_Pause |
10841                            SUPPORTED_Asym_Pause),
10842         .media_type     = ETH_PHY_NOT_PRESENT,
10843         .ver_addr       = 0,
10844         .req_flow_ctrl  = 0,
10845         .req_line_speed = 0,
10846         .speed_cap_mask = 0,
10847         .req_duplex     = 0,
10848         .rsrv           = 0,
10849         .config_init    = (config_init_t)bnx2x_8727_config_init,
10850         .read_status    = (read_status_t)bnx2x_8727_read_status,
10851         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
10852         .config_loopback = (config_loopback_t)NULL,
10853         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10854         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
10855         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
10856         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
10857 };
10858 static struct bnx2x_phy phy_8481 = {
10859         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
10860         .addr           = 0xff,
10861         .def_md_devad   = 0,
10862         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10863                           FLAGS_REARM_LATCH_SIGNAL,
10864         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10865         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10866         .mdio_ctrl      = 0,
10867         .supported      = (SUPPORTED_10baseT_Half |
10868                            SUPPORTED_10baseT_Full |
10869                            SUPPORTED_100baseT_Half |
10870                            SUPPORTED_100baseT_Full |
10871                            SUPPORTED_1000baseT_Full |
10872                            SUPPORTED_10000baseT_Full |
10873                            SUPPORTED_TP |
10874                            SUPPORTED_Autoneg |
10875                            SUPPORTED_Pause |
10876                            SUPPORTED_Asym_Pause),
10877         .media_type     = ETH_PHY_BASE_T,
10878         .ver_addr       = 0,
10879         .req_flow_ctrl  = 0,
10880         .req_line_speed = 0,
10881         .speed_cap_mask = 0,
10882         .req_duplex     = 0,
10883         .rsrv           = 0,
10884         .config_init    = (config_init_t)bnx2x_8481_config_init,
10885         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10886         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
10887         .config_loopback = (config_loopback_t)NULL,
10888         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10889         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
10890         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10891         .phy_specific_func = (phy_specific_func_t)NULL
10892 };
10893
10894 static struct bnx2x_phy phy_84823 = {
10895         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
10896         .addr           = 0xff,
10897         .def_md_devad   = 0,
10898         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10899                           FLAGS_REARM_LATCH_SIGNAL,
10900         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10901         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10902         .mdio_ctrl      = 0,
10903         .supported      = (SUPPORTED_10baseT_Half |
10904                            SUPPORTED_10baseT_Full |
10905                            SUPPORTED_100baseT_Half |
10906                            SUPPORTED_100baseT_Full |
10907                            SUPPORTED_1000baseT_Full |
10908                            SUPPORTED_10000baseT_Full |
10909                            SUPPORTED_TP |
10910                            SUPPORTED_Autoneg |
10911                            SUPPORTED_Pause |
10912                            SUPPORTED_Asym_Pause),
10913         .media_type     = ETH_PHY_BASE_T,
10914         .ver_addr       = 0,
10915         .req_flow_ctrl  = 0,
10916         .req_line_speed = 0,
10917         .speed_cap_mask = 0,
10918         .req_duplex     = 0,
10919         .rsrv           = 0,
10920         .config_init    = (config_init_t)bnx2x_848x3_config_init,
10921         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10922         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
10923         .config_loopback = (config_loopback_t)NULL,
10924         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10925         .hw_reset       = (hw_reset_t)NULL,
10926         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10927         .phy_specific_func = (phy_specific_func_t)NULL
10928 };
10929
10930 static struct bnx2x_phy phy_84833 = {
10931         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
10932         .addr           = 0xff,
10933         .def_md_devad   = 0,
10934         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10935                             FLAGS_REARM_LATCH_SIGNAL,
10936         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10937         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10938         .mdio_ctrl      = 0,
10939         .supported      = (SUPPORTED_100baseT_Half |
10940                            SUPPORTED_100baseT_Full |
10941                            SUPPORTED_1000baseT_Full |
10942                            SUPPORTED_10000baseT_Full |
10943                            SUPPORTED_TP |
10944                            SUPPORTED_Autoneg |
10945                            SUPPORTED_Pause |
10946                            SUPPORTED_Asym_Pause),
10947         .media_type     = ETH_PHY_BASE_T,
10948         .ver_addr       = 0,
10949         .req_flow_ctrl  = 0,
10950         .req_line_speed = 0,
10951         .speed_cap_mask = 0,
10952         .req_duplex     = 0,
10953         .rsrv           = 0,
10954         .config_init    = (config_init_t)bnx2x_848x3_config_init,
10955         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10956         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
10957         .config_loopback = (config_loopback_t)NULL,
10958         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10959         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
10960         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10961         .phy_specific_func = (phy_specific_func_t)NULL
10962 };
10963
10964 static struct bnx2x_phy phy_54618se = {
10965         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
10966         .addr           = 0xff,
10967         .def_md_devad   = 0,
10968         .flags          = FLAGS_INIT_XGXS_FIRST,
10969         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10970         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10971         .mdio_ctrl      = 0,
10972         .supported      = (SUPPORTED_10baseT_Half |
10973                            SUPPORTED_10baseT_Full |
10974                            SUPPORTED_100baseT_Half |
10975                            SUPPORTED_100baseT_Full |
10976                            SUPPORTED_1000baseT_Full |
10977                            SUPPORTED_TP |
10978                            SUPPORTED_Autoneg |
10979                            SUPPORTED_Pause |
10980                            SUPPORTED_Asym_Pause),
10981         .media_type     = ETH_PHY_BASE_T,
10982         .ver_addr       = 0,
10983         .req_flow_ctrl  = 0,
10984         .req_line_speed = 0,
10985         .speed_cap_mask = 0,
10986         /* req_duplex = */0,
10987         /* rsrv = */0,
10988         .config_init    = (config_init_t)bnx2x_54618se_config_init,
10989         .read_status    = (read_status_t)bnx2x_54618se_read_status,
10990         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
10991         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
10992         .format_fw_ver  = (format_fw_ver_t)NULL,
10993         .hw_reset       = (hw_reset_t)NULL,
10994         .set_link_led   = (set_link_led_t)bnx2x_54618se_set_link_led,
10995         .phy_specific_func = (phy_specific_func_t)NULL
10996 };
10997 /*****************************************************************/
10998 /*                                                               */
10999 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11000 /*                                                               */
11001 /*****************************************************************/
11002
11003 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11004                                      struct bnx2x_phy *phy, u8 port,
11005                                      u8 phy_index)
11006 {
11007         /* Get the 4 lanes xgxs config rx and tx */
11008         u32 rx = 0, tx = 0, i;
11009         for (i = 0; i < 2; i++) {
11010                 /*
11011                  * INT_PHY and EXT_PHY1 share the same value location in the
11012                  * shmem. When num_phys is greater than 1, than this value
11013                  * applies only to EXT_PHY1
11014                  */
11015                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11016                         rx = REG_RD(bp, shmem_base +
11017                                     offsetof(struct shmem_region,
11018                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11019
11020                         tx = REG_RD(bp, shmem_base +
11021                                     offsetof(struct shmem_region,
11022                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11023                 } else {
11024                         rx = REG_RD(bp, shmem_base +
11025                                     offsetof(struct shmem_region,
11026                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11027
11028                         tx = REG_RD(bp, shmem_base +
11029                                     offsetof(struct shmem_region,
11030                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11031                 }
11032
11033                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11034                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11035
11036                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11037                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11038         }
11039 }
11040
11041 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11042                                     u8 phy_index, u8 port)
11043 {
11044         u32 ext_phy_config = 0;
11045         switch (phy_index) {
11046         case EXT_PHY1:
11047                 ext_phy_config = REG_RD(bp, shmem_base +
11048                                               offsetof(struct shmem_region,
11049                         dev_info.port_hw_config[port].external_phy_config));
11050                 break;
11051         case EXT_PHY2:
11052                 ext_phy_config = REG_RD(bp, shmem_base +
11053                                               offsetof(struct shmem_region,
11054                         dev_info.port_hw_config[port].external_phy_config2));
11055                 break;
11056         default:
11057                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11058                 return -EINVAL;
11059         }
11060
11061         return ext_phy_config;
11062 }
11063 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11064                                   struct bnx2x_phy *phy)
11065 {
11066         u32 phy_addr;
11067         u32 chip_id;
11068         u32 switch_cfg = (REG_RD(bp, shmem_base +
11069                                        offsetof(struct shmem_region,
11070                         dev_info.port_feature_config[port].link_config)) &
11071                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11072         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
11073         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11074         if (USES_WARPCORE(bp)) {
11075                 u32 serdes_net_if;
11076                 phy_addr = REG_RD(bp,
11077                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11078                 *phy = phy_warpcore;
11079                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11080                         phy->flags |= FLAGS_4_PORT_MODE;
11081                 else
11082                         phy->flags &= ~FLAGS_4_PORT_MODE;
11083                         /* Check Dual mode */
11084                 serdes_net_if = (REG_RD(bp, shmem_base +
11085                                         offsetof(struct shmem_region, dev_info.
11086                                         port_hw_config[port].default_cfg)) &
11087                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11088                 /*
11089                  * Set the appropriate supported and flags indications per
11090                  * interface type of the chip
11091                  */
11092                 switch (serdes_net_if) {
11093                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11094                         phy->supported &= (SUPPORTED_10baseT_Half |
11095                                            SUPPORTED_10baseT_Full |
11096                                            SUPPORTED_100baseT_Half |
11097                                            SUPPORTED_100baseT_Full |
11098                                            SUPPORTED_1000baseT_Full |
11099                                            SUPPORTED_FIBRE |
11100                                            SUPPORTED_Autoneg |
11101                                            SUPPORTED_Pause |
11102                                            SUPPORTED_Asym_Pause);
11103                         phy->media_type = ETH_PHY_BASE_T;
11104                         break;
11105                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11106                         phy->media_type = ETH_PHY_XFP_FIBER;
11107                         break;
11108                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11109                         phy->supported &= (SUPPORTED_1000baseT_Full |
11110                                            SUPPORTED_10000baseT_Full |
11111                                            SUPPORTED_FIBRE |
11112                                            SUPPORTED_Pause |
11113                                            SUPPORTED_Asym_Pause);
11114                         phy->media_type = ETH_PHY_SFP_FIBER;
11115                         break;
11116                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11117                         phy->media_type = ETH_PHY_KR;
11118                         phy->supported &= (SUPPORTED_1000baseT_Full |
11119                                            SUPPORTED_10000baseT_Full |
11120                                            SUPPORTED_FIBRE |
11121                                            SUPPORTED_Autoneg |
11122                                            SUPPORTED_Pause |
11123                                            SUPPORTED_Asym_Pause);
11124                         break;
11125                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11126                         phy->media_type = ETH_PHY_KR;
11127                         phy->flags |= FLAGS_WC_DUAL_MODE;
11128                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11129                                            SUPPORTED_FIBRE |
11130                                            SUPPORTED_Pause |
11131                                            SUPPORTED_Asym_Pause);
11132                         break;
11133                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11134                         phy->media_type = ETH_PHY_KR;
11135                         phy->flags |= FLAGS_WC_DUAL_MODE;
11136                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11137                                            SUPPORTED_FIBRE |
11138                                            SUPPORTED_Pause |
11139                                            SUPPORTED_Asym_Pause);
11140                         break;
11141                 default:
11142                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11143                                        serdes_net_if);
11144                         break;
11145                 }
11146
11147                 /*
11148                  * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11149                  * was not set as expected. For B0, ECO will be enabled so there
11150                  * won't be an issue there
11151                  */
11152                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11153                         phy->flags |= FLAGS_MDC_MDIO_WA;
11154                 else
11155                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11156         } else {
11157                 switch (switch_cfg) {
11158                 case SWITCH_CFG_1G:
11159                         phy_addr = REG_RD(bp,
11160                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11161                                           port * 0x10);
11162                         *phy = phy_serdes;
11163                         break;
11164                 case SWITCH_CFG_10G:
11165                         phy_addr = REG_RD(bp,
11166                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11167                                           port * 0x18);
11168                         *phy = phy_xgxs;
11169                         break;
11170                 default:
11171                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11172                         return -EINVAL;
11173                 }
11174         }
11175         phy->addr = (u8)phy_addr;
11176         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11177                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11178                                             port);
11179         if (CHIP_IS_E2(bp))
11180                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11181         else
11182                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11183
11184         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11185                    port, phy->addr, phy->mdio_ctrl);
11186
11187         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11188         return 0;
11189 }
11190
11191 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11192                                   u8 phy_index,
11193                                   u32 shmem_base,
11194                                   u32 shmem2_base,
11195                                   u8 port,
11196                                   struct bnx2x_phy *phy)
11197 {
11198         u32 ext_phy_config, phy_type, config2;
11199         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11200         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11201                                                   phy_index, port);
11202         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11203         /* Select the phy type */
11204         switch (phy_type) {
11205         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11206                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11207                 *phy = phy_8073;
11208                 break;
11209         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11210                 *phy = phy_8705;
11211                 break;
11212         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11213                 *phy = phy_8706;
11214                 break;
11215         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11216                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11217                 *phy = phy_8726;
11218                 break;
11219         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11220                 /* BCM8727_NOC => BCM8727 no over current */
11221                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11222                 *phy = phy_8727;
11223                 phy->flags |= FLAGS_NOC;
11224                 break;
11225         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11226         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11227                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11228                 *phy = phy_8727;
11229                 break;
11230         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11231                 *phy = phy_8481;
11232                 break;
11233         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11234                 *phy = phy_84823;
11235                 break;
11236         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11237                 *phy = phy_84833;
11238                 break;
11239         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11240                 *phy = phy_54618se;
11241                 break;
11242         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11243                 *phy = phy_7101;
11244                 break;
11245         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11246                 *phy = phy_null;
11247                 return -EINVAL;
11248         default:
11249                 *phy = phy_null;
11250                 return 0;
11251         }
11252
11253         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11254         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11255
11256         /*
11257          * The shmem address of the phy version is located on different
11258          * structures. In case this structure is too old, do not set
11259          * the address
11260          */
11261         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11262                                         dev_info.shared_hw_config.config2));
11263         if (phy_index == EXT_PHY1) {
11264                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11265                                 port_mb[port].ext_phy_fw_version);
11266
11267                 /* Check specific mdc mdio settings */
11268                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11269                         mdc_mdio_access = config2 &
11270                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11271         } else {
11272                 u32 size = REG_RD(bp, shmem2_base);
11273
11274                 if (size >
11275                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11276                         phy->ver_addr = shmem2_base +
11277                             offsetof(struct shmem2_region,
11278                                      ext_phy_fw_version2[port]);
11279                 }
11280                 /* Check specific mdc mdio settings */
11281                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11282                         mdc_mdio_access = (config2 &
11283                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11284                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11285                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11286         }
11287         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11288
11289         /*
11290          * In case mdc/mdio_access of the external phy is different than the
11291          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11292          * to prevent one port interfere with another port's CL45 operations.
11293          */
11294         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11295                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11296         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11297                    phy_type, port, phy_index);
11298         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
11299                    phy->addr, phy->mdio_ctrl);
11300         return 0;
11301 }
11302
11303 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11304                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11305 {
11306         int status = 0;
11307         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11308         if (phy_index == INT_PHY)
11309                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11310         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11311                                         port, phy);
11312         return status;
11313 }
11314
11315 static void bnx2x_phy_def_cfg(struct link_params *params,
11316                               struct bnx2x_phy *phy,
11317                               u8 phy_index)
11318 {
11319         struct bnx2x *bp = params->bp;
11320         u32 link_config;
11321         /* Populate the default phy configuration for MF mode */
11322         if (phy_index == EXT_PHY2) {
11323                 link_config = REG_RD(bp, params->shmem_base +
11324                                      offsetof(struct shmem_region, dev_info.
11325                         port_feature_config[params->port].link_config2));
11326                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11327                                              offsetof(struct shmem_region,
11328                                                       dev_info.
11329                         port_hw_config[params->port].speed_capability_mask2));
11330         } else {
11331                 link_config = REG_RD(bp, params->shmem_base +
11332                                      offsetof(struct shmem_region, dev_info.
11333                                 port_feature_config[params->port].link_config));
11334                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11335                                              offsetof(struct shmem_region,
11336                                                       dev_info.
11337                         port_hw_config[params->port].speed_capability_mask));
11338         }
11339         DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
11340                        " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
11341
11342         phy->req_duplex = DUPLEX_FULL;
11343         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
11344         case PORT_FEATURE_LINK_SPEED_10M_HALF:
11345                 phy->req_duplex = DUPLEX_HALF;
11346         case PORT_FEATURE_LINK_SPEED_10M_FULL:
11347                 phy->req_line_speed = SPEED_10;
11348                 break;
11349         case PORT_FEATURE_LINK_SPEED_100M_HALF:
11350                 phy->req_duplex = DUPLEX_HALF;
11351         case PORT_FEATURE_LINK_SPEED_100M_FULL:
11352                 phy->req_line_speed = SPEED_100;
11353                 break;
11354         case PORT_FEATURE_LINK_SPEED_1G:
11355                 phy->req_line_speed = SPEED_1000;
11356                 break;
11357         case PORT_FEATURE_LINK_SPEED_2_5G:
11358                 phy->req_line_speed = SPEED_2500;
11359                 break;
11360         case PORT_FEATURE_LINK_SPEED_10G_CX4:
11361                 phy->req_line_speed = SPEED_10000;
11362                 break;
11363         default:
11364                 phy->req_line_speed = SPEED_AUTO_NEG;
11365                 break;
11366         }
11367
11368         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
11369         case PORT_FEATURE_FLOW_CONTROL_AUTO:
11370                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11371                 break;
11372         case PORT_FEATURE_FLOW_CONTROL_TX:
11373                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11374                 break;
11375         case PORT_FEATURE_FLOW_CONTROL_RX:
11376                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11377                 break;
11378         case PORT_FEATURE_FLOW_CONTROL_BOTH:
11379                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11380                 break;
11381         default:
11382                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11383                 break;
11384         }
11385 }
11386
11387 u32 bnx2x_phy_selection(struct link_params *params)
11388 {
11389         u32 phy_config_swapped, prio_cfg;
11390         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11391
11392         phy_config_swapped = params->multi_phy_config &
11393                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11394
11395         prio_cfg = params->multi_phy_config &
11396                         PORT_HW_CFG_PHY_SELECTION_MASK;
11397
11398         if (phy_config_swapped) {
11399                 switch (prio_cfg) {
11400                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11401                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11402                      break;
11403                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11404                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11405                      break;
11406                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11407                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11408                      break;
11409                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11410                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11411                      break;
11412                 }
11413         } else
11414                 return_cfg = prio_cfg;
11415
11416         return return_cfg;
11417 }
11418
11419
11420 int bnx2x_phy_probe(struct link_params *params)
11421 {
11422         u8 phy_index, actual_phy_idx, link_cfg_idx;
11423         u32 phy_config_swapped, sync_offset, media_types;
11424         struct bnx2x *bp = params->bp;
11425         struct bnx2x_phy *phy;
11426         params->num_phys = 0;
11427         DP(NETIF_MSG_LINK, "Begin phy probe\n");
11428         phy_config_swapped = params->multi_phy_config &
11429                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11430
11431         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11432               phy_index++) {
11433                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11434                 actual_phy_idx = phy_index;
11435                 if (phy_config_swapped) {
11436                         if (phy_index == EXT_PHY1)
11437                                 actual_phy_idx = EXT_PHY2;
11438                         else if (phy_index == EXT_PHY2)
11439                                 actual_phy_idx = EXT_PHY1;
11440                 }
11441                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11442                                " actual_phy_idx %x\n", phy_config_swapped,
11443                            phy_index, actual_phy_idx);
11444                 phy = &params->phy[actual_phy_idx];
11445                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11446                                        params->shmem2_base, params->port,
11447                                        phy) != 0) {
11448                         params->num_phys = 0;
11449                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11450                                    phy_index);
11451                         for (phy_index = INT_PHY;
11452                               phy_index < MAX_PHYS;
11453                               phy_index++)
11454                                 *phy = phy_null;
11455                         return -EINVAL;
11456                 }
11457                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11458                         break;
11459
11460                 sync_offset = params->shmem_base +
11461                         offsetof(struct shmem_region,
11462                         dev_info.port_hw_config[params->port].media_type);
11463                 media_types = REG_RD(bp, sync_offset);
11464
11465                 /*
11466                  * Update media type for non-PMF sync only for the first time
11467                  * In case the media type changes afterwards, it will be updated
11468                  * using the update_status function
11469                  */
11470                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11471                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11472                                      actual_phy_idx))) == 0) {
11473                         media_types |= ((phy->media_type &
11474                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11475                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11476                                  actual_phy_idx));
11477                 }
11478                 REG_WR(bp, sync_offset, media_types);
11479
11480                 bnx2x_phy_def_cfg(params, phy, phy_index);
11481                 params->num_phys++;
11482         }
11483
11484         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11485         return 0;
11486 }
11487
11488 void bnx2x_init_bmac_loopback(struct link_params *params,
11489                               struct link_vars *vars)
11490 {
11491         struct bnx2x *bp = params->bp;
11492                 vars->link_up = 1;
11493                 vars->line_speed = SPEED_10000;
11494                 vars->duplex = DUPLEX_FULL;
11495                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11496                 vars->mac_type = MAC_TYPE_BMAC;
11497
11498                 vars->phy_flags = PHY_XGXS_FLAG;
11499
11500                 bnx2x_xgxs_deassert(params);
11501
11502                 /* set bmac loopback */
11503                 bnx2x_bmac_enable(params, vars, 1);
11504
11505                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11506 }
11507
11508 void bnx2x_init_emac_loopback(struct link_params *params,
11509                               struct link_vars *vars)
11510 {
11511         struct bnx2x *bp = params->bp;
11512                 vars->link_up = 1;
11513                 vars->line_speed = SPEED_1000;
11514                 vars->duplex = DUPLEX_FULL;
11515                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11516                 vars->mac_type = MAC_TYPE_EMAC;
11517
11518                 vars->phy_flags = PHY_XGXS_FLAG;
11519
11520                 bnx2x_xgxs_deassert(params);
11521                 /* set bmac loopback */
11522                 bnx2x_emac_enable(params, vars, 1);
11523                 bnx2x_emac_program(params, vars);
11524                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11525 }
11526
11527 void bnx2x_init_xmac_loopback(struct link_params *params,
11528                               struct link_vars *vars)
11529 {
11530         struct bnx2x *bp = params->bp;
11531         vars->link_up = 1;
11532         if (!params->req_line_speed[0])
11533                 vars->line_speed = SPEED_10000;
11534         else
11535                 vars->line_speed = params->req_line_speed[0];
11536         vars->duplex = DUPLEX_FULL;
11537         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11538         vars->mac_type = MAC_TYPE_XMAC;
11539         vars->phy_flags = PHY_XGXS_FLAG;
11540         /*
11541          * Set WC to loopback mode since link is required to provide clock
11542          * to the XMAC in 20G mode
11543          */
11544         bnx2x_set_aer_mmd(params, &params->phy[0]);
11545         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
11546         params->phy[INT_PHY].config_loopback(
11547                         &params->phy[INT_PHY],
11548                         params);
11549
11550         bnx2x_xmac_enable(params, vars, 1);
11551         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11552 }
11553
11554 void bnx2x_init_umac_loopback(struct link_params *params,
11555                               struct link_vars *vars)
11556 {
11557         struct bnx2x *bp = params->bp;
11558         vars->link_up = 1;
11559         vars->line_speed = SPEED_1000;
11560         vars->duplex = DUPLEX_FULL;
11561         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11562         vars->mac_type = MAC_TYPE_UMAC;
11563         vars->phy_flags = PHY_XGXS_FLAG;
11564         bnx2x_umac_enable(params, vars, 1);
11565
11566         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11567 }
11568
11569 void bnx2x_init_xgxs_loopback(struct link_params *params,
11570                               struct link_vars *vars)
11571 {
11572         struct bnx2x *bp = params->bp;
11573                 vars->link_up = 1;
11574                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11575                 vars->duplex = DUPLEX_FULL;
11576         if (params->req_line_speed[0] == SPEED_1000)
11577                         vars->line_speed = SPEED_1000;
11578         else
11579                         vars->line_speed = SPEED_10000;
11580
11581         if (!USES_WARPCORE(bp))
11582                 bnx2x_xgxs_deassert(params);
11583         bnx2x_link_initialize(params, vars);
11584
11585         if (params->req_line_speed[0] == SPEED_1000) {
11586                 if (USES_WARPCORE(bp))
11587                         bnx2x_umac_enable(params, vars, 0);
11588                 else {
11589                         bnx2x_emac_program(params, vars);
11590                         bnx2x_emac_enable(params, vars, 0);
11591                 }
11592         } else {
11593                 if (USES_WARPCORE(bp))
11594                         bnx2x_xmac_enable(params, vars, 0);
11595                 else
11596                         bnx2x_bmac_enable(params, vars, 0);
11597         }
11598
11599                 if (params->loopback_mode == LOOPBACK_XGXS) {
11600                         /* set 10G XGXS loopback */
11601                         params->phy[INT_PHY].config_loopback(
11602                                 &params->phy[INT_PHY],
11603                                 params);
11604
11605                 } else {
11606                         /* set external phy loopback */
11607                         u8 phy_index;
11608                         for (phy_index = EXT_PHY1;
11609                               phy_index < params->num_phys; phy_index++) {
11610                                 if (params->phy[phy_index].config_loopback)
11611                                         params->phy[phy_index].config_loopback(
11612                                                 &params->phy[phy_index],
11613                                                 params);
11614                         }
11615                 }
11616                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11617
11618         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11619 }
11620
11621 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11622 {
11623         struct bnx2x *bp = params->bp;
11624         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11625         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11626                    params->req_line_speed[0], params->req_flow_ctrl[0]);
11627         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11628                    params->req_line_speed[1], params->req_flow_ctrl[1]);
11629         vars->link_status = 0;
11630         vars->phy_link_up = 0;
11631         vars->link_up = 0;
11632         vars->line_speed = 0;
11633         vars->duplex = DUPLEX_FULL;
11634         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11635         vars->mac_type = MAC_TYPE_NONE;
11636         vars->phy_flags = 0;
11637
11638         /* disable attentions */
11639         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11640                        (NIG_MASK_XGXS0_LINK_STATUS |
11641                         NIG_MASK_XGXS0_LINK10G |
11642                         NIG_MASK_SERDES0_LINK_STATUS |
11643                         NIG_MASK_MI_INT));
11644
11645         bnx2x_emac_init(params, vars);
11646
11647         if (params->num_phys == 0) {
11648                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11649                 return -EINVAL;
11650         }
11651         set_phy_vars(params, vars);
11652
11653         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11654         switch (params->loopback_mode) {
11655         case LOOPBACK_BMAC:
11656                 bnx2x_init_bmac_loopback(params, vars);
11657                 break;
11658         case LOOPBACK_EMAC:
11659                 bnx2x_init_emac_loopback(params, vars);
11660                 break;
11661         case LOOPBACK_XMAC:
11662                 bnx2x_init_xmac_loopback(params, vars);
11663                 break;
11664         case LOOPBACK_UMAC:
11665                 bnx2x_init_umac_loopback(params, vars);
11666                 break;
11667         case LOOPBACK_XGXS:
11668         case LOOPBACK_EXT_PHY:
11669                 bnx2x_init_xgxs_loopback(params, vars);
11670                 break;
11671         default:
11672                 if (!CHIP_IS_E3(bp)) {
11673                         if (params->switch_cfg == SWITCH_CFG_10G)
11674                                 bnx2x_xgxs_deassert(params);
11675                         else
11676                                 bnx2x_serdes_deassert(bp, params->port);
11677                 }
11678                 bnx2x_link_initialize(params, vars);
11679                 msleep(30);
11680                 bnx2x_link_int_enable(params);
11681                 break;
11682         }
11683         return 0;
11684 }
11685
11686 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11687                      u8 reset_ext_phy)
11688 {
11689         struct bnx2x *bp = params->bp;
11690         u8 phy_index, port = params->port, clear_latch_ind = 0;
11691         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11692         /* disable attentions */
11693         vars->link_status = 0;
11694         bnx2x_update_mng(params, vars->link_status);
11695         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11696                        (NIG_MASK_XGXS0_LINK_STATUS |
11697                         NIG_MASK_XGXS0_LINK10G |
11698                         NIG_MASK_SERDES0_LINK_STATUS |
11699                         NIG_MASK_MI_INT));
11700
11701         /* activate nig drain */
11702         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11703
11704         /* disable nig egress interface */
11705         if (!CHIP_IS_E3(bp)) {
11706                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11707                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11708         }
11709
11710         /* Stop BigMac rx */
11711         if (!CHIP_IS_E3(bp))
11712                 bnx2x_bmac_rx_disable(bp, port);
11713         else
11714                 bnx2x_xmac_disable(params);
11715         /* disable emac */
11716         if (!CHIP_IS_E3(bp))
11717                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11718
11719         msleep(10);
11720         /* The PHY reset is controlled by GPIO 1
11721          * Hold it as vars low
11722          */
11723          /* clear link led */
11724         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11725
11726         if (reset_ext_phy) {
11727                 bnx2x_set_mdio_clk(bp, params->chip_id, port);
11728                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11729                       phy_index++) {
11730                         if (params->phy[phy_index].link_reset) {
11731                                 bnx2x_set_aer_mmd(params,
11732                                                   &params->phy[phy_index]);
11733                                 params->phy[phy_index].link_reset(
11734                                         &params->phy[phy_index],
11735                                         params);
11736                         }
11737                         if (params->phy[phy_index].flags &
11738                             FLAGS_REARM_LATCH_SIGNAL)
11739                                 clear_latch_ind = 1;
11740                 }
11741         }
11742
11743         if (clear_latch_ind) {
11744                 /* Clear latching indication */
11745                 bnx2x_rearm_latch_signal(bp, port, 0);
11746                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11747                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
11748         }
11749         if (params->phy[INT_PHY].link_reset)
11750                 params->phy[INT_PHY].link_reset(
11751                         &params->phy[INT_PHY], params);
11752         /* reset BigMac */
11753         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11754                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11755
11756         /* disable nig ingress interface */
11757         if (!CHIP_IS_E3(bp)) {
11758                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11759                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11760         }
11761         vars->link_up = 0;
11762         vars->phy_flags = 0;
11763         return 0;
11764 }
11765
11766 /****************************************************************************/
11767 /*                              Common function                             */
11768 /****************************************************************************/
11769 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
11770                                       u32 shmem_base_path[],
11771                                       u32 shmem2_base_path[], u8 phy_index,
11772                                       u32 chip_id)
11773 {
11774         struct bnx2x_phy phy[PORT_MAX];
11775         struct bnx2x_phy *phy_blk[PORT_MAX];
11776         u16 val;
11777         s8 port = 0;
11778         s8 port_of_path = 0;
11779         u32 swap_val, swap_override;
11780         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
11781         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
11782         port ^= (swap_val && swap_override);
11783         bnx2x_ext_phy_hw_reset(bp, port);
11784         /* PART1 - Reset both phys */
11785         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11786                 u32 shmem_base, shmem2_base;
11787                 /* In E2, same phy is using for port0 of the two paths */
11788                 if (CHIP_IS_E1x(bp)) {
11789                         shmem_base = shmem_base_path[0];
11790                         shmem2_base = shmem2_base_path[0];
11791                         port_of_path = port;
11792                 } else {
11793                         shmem_base = shmem_base_path[port];
11794                         shmem2_base = shmem2_base_path[port];
11795                         port_of_path = 0;
11796                 }
11797
11798                 /* Extract the ext phy address for the port */
11799                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11800                                        port_of_path, &phy[port]) !=
11801                     0) {
11802                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
11803                         return -EINVAL;
11804                 }
11805                 /* disable attentions */
11806                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11807                                port_of_path*4,
11808                                (NIG_MASK_XGXS0_LINK_STATUS |
11809                                 NIG_MASK_XGXS0_LINK10G |
11810                                 NIG_MASK_SERDES0_LINK_STATUS |
11811                                 NIG_MASK_MI_INT));
11812
11813                 /* Need to take the phy out of low power mode in order
11814                         to write to access its registers */
11815                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11816                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11817                                port);
11818
11819                 /* Reset the phy */
11820                 bnx2x_cl45_write(bp, &phy[port],
11821                                  MDIO_PMA_DEVAD,
11822                                  MDIO_PMA_REG_CTRL,
11823                                  1<<15);
11824         }
11825
11826         /* Add delay of 150ms after reset */
11827         msleep(150);
11828
11829         if (phy[PORT_0].addr & 0x1) {
11830                 phy_blk[PORT_0] = &(phy[PORT_1]);
11831                 phy_blk[PORT_1] = &(phy[PORT_0]);
11832         } else {
11833                 phy_blk[PORT_0] = &(phy[PORT_0]);
11834                 phy_blk[PORT_1] = &(phy[PORT_1]);
11835         }
11836
11837         /* PART2 - Download firmware to both phys */
11838         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11839                 if (CHIP_IS_E1x(bp))
11840                         port_of_path = port;
11841                 else
11842                         port_of_path = 0;
11843
11844                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11845                            phy_blk[port]->addr);
11846                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11847                                                       port_of_path))
11848                         return -EINVAL;
11849
11850                 /* Only set bit 10 = 1 (Tx power down) */
11851                 bnx2x_cl45_read(bp, phy_blk[port],
11852                                 MDIO_PMA_DEVAD,
11853                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11854
11855                 /* Phase1 of TX_POWER_DOWN reset */
11856                 bnx2x_cl45_write(bp, phy_blk[port],
11857                                  MDIO_PMA_DEVAD,
11858                                  MDIO_PMA_REG_TX_POWER_DOWN,
11859                                  (val | 1<<10));
11860         }
11861
11862         /*
11863          * Toggle Transmitter: Power down and then up with 600ms delay
11864          * between
11865          */
11866         msleep(600);
11867
11868         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
11869         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11870                 /* Phase2 of POWER_DOWN_RESET */
11871                 /* Release bit 10 (Release Tx power down) */
11872                 bnx2x_cl45_read(bp, phy_blk[port],
11873                                 MDIO_PMA_DEVAD,
11874                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11875
11876                 bnx2x_cl45_write(bp, phy_blk[port],
11877                                 MDIO_PMA_DEVAD,
11878                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
11879                 msleep(15);
11880
11881                 /* Read modify write the SPI-ROM version select register */
11882                 bnx2x_cl45_read(bp, phy_blk[port],
11883                                 MDIO_PMA_DEVAD,
11884                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
11885                 bnx2x_cl45_write(bp, phy_blk[port],
11886                                  MDIO_PMA_DEVAD,
11887                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
11888
11889                 /* set GPIO2 back to LOW */
11890                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11891                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
11892         }
11893         return 0;
11894 }
11895 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
11896                                       u32 shmem_base_path[],
11897                                       u32 shmem2_base_path[], u8 phy_index,
11898                                       u32 chip_id)
11899 {
11900         u32 val;
11901         s8 port;
11902         struct bnx2x_phy phy;
11903         /* Use port1 because of the static port-swap */
11904         /* Enable the module detection interrupt */
11905         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
11906         val |= ((1<<MISC_REGISTERS_GPIO_3)|
11907                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
11908         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
11909
11910         bnx2x_ext_phy_hw_reset(bp, 0);
11911         msleep(5);
11912         for (port = 0; port < PORT_MAX; port++) {
11913                 u32 shmem_base, shmem2_base;
11914
11915                 /* In E2, same phy is using for port0 of the two paths */
11916                 if (CHIP_IS_E1x(bp)) {
11917                         shmem_base = shmem_base_path[0];
11918                         shmem2_base = shmem2_base_path[0];
11919                 } else {
11920                         shmem_base = shmem_base_path[port];
11921                         shmem2_base = shmem2_base_path[port];
11922                 }
11923                 /* Extract the ext phy address for the port */
11924                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11925                                        port, &phy) !=
11926                     0) {
11927                         DP(NETIF_MSG_LINK, "populate phy failed\n");
11928                         return -EINVAL;
11929                 }
11930
11931                 /* Reset phy*/
11932                 bnx2x_cl45_write(bp, &phy,
11933                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
11934
11935
11936                 /* Set fault module detected LED on */
11937                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
11938                                MISC_REGISTERS_GPIO_HIGH,
11939                                port);
11940         }
11941
11942         return 0;
11943 }
11944 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
11945                                          u8 *io_gpio, u8 *io_port)
11946 {
11947
11948         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
11949                                           offsetof(struct shmem_region,
11950                                 dev_info.port_hw_config[PORT_0].default_cfg));
11951         switch (phy_gpio_reset) {
11952         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
11953                 *io_gpio = 0;
11954                 *io_port = 0;
11955                 break;
11956         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
11957                 *io_gpio = 1;
11958                 *io_port = 0;
11959                 break;
11960         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
11961                 *io_gpio = 2;
11962                 *io_port = 0;
11963                 break;
11964         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
11965                 *io_gpio = 3;
11966                 *io_port = 0;
11967                 break;
11968         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
11969                 *io_gpio = 0;
11970                 *io_port = 1;
11971                 break;
11972         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
11973                 *io_gpio = 1;
11974                 *io_port = 1;
11975                 break;
11976         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
11977                 *io_gpio = 2;
11978                 *io_port = 1;
11979                 break;
11980         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
11981                 *io_gpio = 3;
11982                 *io_port = 1;
11983                 break;
11984         default:
11985                 /* Don't override the io_gpio and io_port */
11986                 break;
11987         }
11988 }
11989
11990 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
11991                                       u32 shmem_base_path[],
11992                                       u32 shmem2_base_path[], u8 phy_index,
11993                                       u32 chip_id)
11994 {
11995         s8 port, reset_gpio;
11996         u32 swap_val, swap_override;
11997         struct bnx2x_phy phy[PORT_MAX];
11998         struct bnx2x_phy *phy_blk[PORT_MAX];
11999         s8 port_of_path;
12000         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12001         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12002
12003         reset_gpio = MISC_REGISTERS_GPIO_1;
12004         port = 1;
12005
12006         /*
12007          * Retrieve the reset gpio/port which control the reset.
12008          * Default is GPIO1, PORT1
12009          */
12010         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
12011                                      (u8 *)&reset_gpio, (u8 *)&port);
12012
12013         /* Calculate the port based on port swap */
12014         port ^= (swap_val && swap_override);
12015
12016         /* Initiate PHY reset*/
12017         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12018                        port);
12019         msleep(1);
12020         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12021                        port);
12022
12023         msleep(5);
12024
12025         /* PART1 - Reset both phys */
12026         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12027                 u32 shmem_base, shmem2_base;
12028
12029                 /* In E2, same phy is using for port0 of the two paths */
12030                 if (CHIP_IS_E1x(bp)) {
12031                         shmem_base = shmem_base_path[0];
12032                         shmem2_base = shmem2_base_path[0];
12033                         port_of_path = port;
12034                 } else {
12035                         shmem_base = shmem_base_path[port];
12036                         shmem2_base = shmem2_base_path[port];
12037                         port_of_path = 0;
12038                 }
12039
12040                 /* Extract the ext phy address for the port */
12041                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12042                                        port_of_path, &phy[port]) !=
12043                                        0) {
12044                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12045                         return -EINVAL;
12046                 }
12047                 /* disable attentions */
12048                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12049                                port_of_path*4,
12050                                (NIG_MASK_XGXS0_LINK_STATUS |
12051                                 NIG_MASK_XGXS0_LINK10G |
12052                                 NIG_MASK_SERDES0_LINK_STATUS |
12053                                 NIG_MASK_MI_INT));
12054
12055
12056                 /* Reset the phy */
12057                 bnx2x_cl45_write(bp, &phy[port],
12058                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12059         }
12060
12061         /* Add delay of 150ms after reset */
12062         msleep(150);
12063         if (phy[PORT_0].addr & 0x1) {
12064                 phy_blk[PORT_0] = &(phy[PORT_1]);
12065                 phy_blk[PORT_1] = &(phy[PORT_0]);
12066         } else {
12067                 phy_blk[PORT_0] = &(phy[PORT_0]);
12068                 phy_blk[PORT_1] = &(phy[PORT_1]);
12069         }
12070         /* PART2 - Download firmware to both phys */
12071         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12072                 if (CHIP_IS_E1x(bp))
12073                         port_of_path = port;
12074                 else
12075                         port_of_path = 0;
12076                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12077                            phy_blk[port]->addr);
12078                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12079                                                       port_of_path))
12080                         return -EINVAL;
12081                 /* Disable PHY transmitter output */
12082                 bnx2x_cl45_write(bp, phy_blk[port],
12083                                  MDIO_PMA_DEVAD,
12084                                  MDIO_PMA_REG_TX_DISABLE, 1);
12085
12086         }
12087         return 0;
12088 }
12089
12090 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12091                                      u32 shmem2_base_path[], u8 phy_index,
12092                                      u32 ext_phy_type, u32 chip_id)
12093 {
12094         int rc = 0;
12095
12096         switch (ext_phy_type) {
12097         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12098                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12099                                                 shmem2_base_path,
12100                                                 phy_index, chip_id);
12101                 break;
12102         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12103         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12104         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12105                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12106                                                 shmem2_base_path,
12107                                                 phy_index, chip_id);
12108                 break;
12109
12110         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12111                 /*
12112                  * GPIO1 affects both ports, so there's need to pull
12113                  * it for single port alone
12114                  */
12115                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12116                                                 shmem2_base_path,
12117                                                 phy_index, chip_id);
12118                 break;
12119         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12120                 /*
12121                  * GPIO3's are linked, and so both need to be toggled
12122                  * to obtain required 2us pulse.
12123                  */
12124                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
12125                 break;
12126         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12127                 rc = -EINVAL;
12128                 break;
12129         default:
12130                 DP(NETIF_MSG_LINK,
12131                            "ext_phy 0x%x common init not required\n",
12132                            ext_phy_type);
12133                 break;
12134         }
12135
12136         if (rc != 0)
12137                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
12138                                       " Port %d\n",
12139                          0);
12140         return rc;
12141 }
12142
12143 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12144                           u32 shmem2_base_path[], u32 chip_id)
12145 {
12146         int rc = 0;
12147         u32 phy_ver, val;
12148         u8 phy_index = 0;
12149         u32 ext_phy_type, ext_phy_config;
12150         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12151         bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12152         DP(NETIF_MSG_LINK, "Begin common phy init\n");
12153         if (CHIP_IS_E3(bp)) {
12154                 /* Enable EPIO */
12155                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12156                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12157         }
12158         /* Check if common init was already done */
12159         phy_ver = REG_RD(bp, shmem_base_path[0] +
12160                          offsetof(struct shmem_region,
12161                                   port_mb[PORT_0].ext_phy_fw_version));
12162         if (phy_ver) {
12163                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12164                                phy_ver);
12165                 return 0;
12166         }
12167
12168         /* Read the ext_phy_type for arbitrary port(0) */
12169         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12170               phy_index++) {
12171                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12172                                                           shmem_base_path[0],
12173                                                           phy_index, 0);
12174                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12175                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12176                                                 shmem2_base_path,
12177                                                 phy_index, ext_phy_type,
12178                                                 chip_id);
12179         }
12180         return rc;
12181 }
12182
12183 static void bnx2x_check_over_curr(struct link_params *params,
12184                                   struct link_vars *vars)
12185 {
12186         struct bnx2x *bp = params->bp;
12187         u32 cfg_pin;
12188         u8 port = params->port;
12189         u32 pin_val;
12190
12191         cfg_pin = (REG_RD(bp, params->shmem_base +
12192                           offsetof(struct shmem_region,
12193                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12194                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12195                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12196
12197         /* Ignore check if no external input PIN available */
12198         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12199                 return;
12200
12201         if (!pin_val) {
12202                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12203                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
12204                                             " been detected and the power to "
12205                                             "that SFP+ module has been removed"
12206                                             " to prevent failure of the card."
12207                                             " Please remove the SFP+ module and"
12208                                             " restart the system to clear this"
12209                                             " error.\n",
12210                          params->port);
12211                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12212                 }
12213         } else
12214                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12215 }
12216
12217 static void bnx2x_analyze_link_error(struct link_params *params,
12218                                      struct link_vars *vars, u32 lss_status)
12219 {
12220         struct bnx2x *bp = params->bp;
12221         /* Compare new value with previous value */
12222         u8 led_mode;
12223         u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12224
12225         if ((lss_status ^ half_open_conn) == 0)
12226                 return;
12227
12228         /* If values differ */
12229         DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12230                        half_open_conn, lss_status);
12231
12232         /*
12233          * a. Update shmem->link_status accordingly
12234          * b. Update link_vars->link_up
12235          */
12236         if (lss_status) {
12237                 DP(NETIF_MSG_LINK, "Remote Fault detected !!!\n");
12238                 vars->link_status &= ~LINK_STATUS_LINK_UP;
12239                 vars->link_up = 0;
12240                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12241                 /*
12242                  * Set LED mode to off since the PHY doesn't know about these
12243                  * errors
12244                  */
12245                 led_mode = LED_MODE_OFF;
12246         } else {
12247                 DP(NETIF_MSG_LINK, "Remote Fault cleared\n");
12248                 vars->link_status |= LINK_STATUS_LINK_UP;
12249                 vars->link_up = 1;
12250                 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12251                 led_mode = LED_MODE_OPER;
12252         }
12253         /* Update the LED according to the link state */
12254         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12255
12256         /* Update link status in the shared memory */
12257         bnx2x_update_mng(params, vars->link_status);
12258
12259         /* C. Trigger General Attention */
12260         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12261         bnx2x_notify_link_changed(bp);
12262 }
12263
12264 /******************************************************************************
12265 * Description:
12266 *       This function checks for half opened connection change indication.
12267 *       When such change occurs, it calls the bnx2x_analyze_link_error
12268 *       to check if Remote Fault is set or cleared. Reception of remote fault
12269 *       status message in the MAC indicates that the peer's MAC has detected
12270 *       a fault, for example, due to break in the TX side of fiber.
12271 *
12272 ******************************************************************************/
12273 static void bnx2x_check_half_open_conn(struct link_params *params,
12274                                        struct link_vars *vars)
12275 {
12276         struct bnx2x *bp = params->bp;
12277         u32 lss_status = 0;
12278         u32 mac_base;
12279         /* In case link status is physically up @ 10G do */
12280         if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12281                 return;
12282
12283         if (CHIP_IS_E3(bp) &&
12284             (REG_RD(bp, MISC_REG_RESET_REG_2) &
12285               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12286                 /* Check E3 XMAC */
12287                 /*
12288                  * Note that link speed cannot be queried here, since it may be
12289                  * zero while link is down. In case UMAC is active, LSS will
12290                  * simply not be set
12291                  */
12292                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12293
12294                 /* Clear stick bits (Requires rising edge) */
12295                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12296                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12297                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12298                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12299                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
12300                         lss_status = 1;
12301
12302                 bnx2x_analyze_link_error(params, vars, lss_status);
12303         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12304                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12305                 /* Check E1X / E2 BMAC */
12306                 u32 lss_status_reg;
12307                 u32 wb_data[2];
12308                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12309                         NIG_REG_INGRESS_BMAC0_MEM;
12310                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
12311                 if (CHIP_IS_E2(bp))
12312                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12313                 else
12314                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12315
12316                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12317                 lss_status = (wb_data[0] > 0);
12318
12319                 bnx2x_analyze_link_error(params, vars, lss_status);
12320         }
12321 }
12322
12323 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12324 {
12325         struct bnx2x *bp = params->bp;
12326         u16 phy_idx;
12327         if (!params) {
12328                 DP(NETIF_MSG_LINK, "Uninitialized params !\n");
12329                 return;
12330         }
12331
12332         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
12333                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
12334                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
12335                         bnx2x_check_half_open_conn(params, vars);
12336                         break;
12337                 }
12338         }
12339
12340         if (CHIP_IS_E3(bp))
12341                 bnx2x_check_over_curr(params, vars);
12342 }
12343
12344 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12345 {
12346         u8 phy_index;
12347         struct bnx2x_phy phy;
12348         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12349               phy_index++) {
12350                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12351                                        0, &phy) != 0) {
12352                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12353                         return 0;
12354                 }
12355
12356                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12357                         return 1;
12358         }
12359         return 0;
12360 }
12361
12362 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12363                              u32 shmem_base,
12364                              u32 shmem2_base,
12365                              u8 port)
12366 {
12367         u8 phy_index, fan_failure_det_req = 0;
12368         struct bnx2x_phy phy;
12369         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12370               phy_index++) {
12371                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12372                                        port, &phy)
12373                     != 0) {
12374                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12375                         return 0;
12376                 }
12377                 fan_failure_det_req |= (phy.flags &
12378                                         FLAGS_FAN_FAILURE_DET_REQ);
12379         }
12380         return fan_failure_det_req;
12381 }
12382
12383 void bnx2x_hw_reset_phy(struct link_params *params)
12384 {
12385         u8 phy_index;
12386         struct bnx2x *bp = params->bp;
12387         bnx2x_update_mng(params, 0);
12388         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12389                        (NIG_MASK_XGXS0_LINK_STATUS |
12390                         NIG_MASK_XGXS0_LINK10G |
12391                         NIG_MASK_SERDES0_LINK_STATUS |
12392                         NIG_MASK_MI_INT));
12393
12394         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12395               phy_index++) {
12396                 if (params->phy[phy_index].hw_reset) {
12397                         params->phy[phy_index].hw_reset(
12398                                 &params->phy[phy_index],
12399                                 params);
12400                         params->phy[phy_index] = phy_null;
12401                 }
12402         }
12403 }
12404
12405 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12406                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
12407                             u8 port)
12408 {
12409         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12410         u32 val;
12411         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12412         if (CHIP_IS_E3(bp)) {
12413                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12414                                               shmem_base,
12415                                               port,
12416                                               &gpio_num,
12417                                               &gpio_port) != 0)
12418                         return;
12419         } else {
12420                 struct bnx2x_phy phy;
12421                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12422                       phy_index++) {
12423                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12424                                                shmem2_base, port, &phy)
12425                             != 0) {
12426                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
12427                                 return;
12428                         }
12429                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12430                                 gpio_num = MISC_REGISTERS_GPIO_3;
12431                                 gpio_port = port;
12432                                 break;
12433                         }
12434                 }
12435         }
12436
12437         if (gpio_num == 0xff)
12438                 return;
12439
12440         /* Set GPIO3 to trigger SFP+ module insertion/removal */
12441         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12442
12443         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12444         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12445         gpio_port ^= (swap_val && swap_override);
12446
12447         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12448                 (gpio_num + (gpio_port << 2));
12449
12450         sync_offset = shmem_base +
12451                 offsetof(struct shmem_region,
12452                          dev_info.port_hw_config[port].aeu_int_mask);
12453         REG_WR(bp, sync_offset, vars->aeu_int_mask);
12454
12455         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12456                        gpio_num, gpio_port, vars->aeu_int_mask);
12457
12458         if (port == 0)
12459                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12460         else
12461                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12462
12463         /* Open appropriate AEU for interrupts */
12464         aeu_mask = REG_RD(bp, offset);
12465         aeu_mask |= vars->aeu_int_mask;
12466         REG_WR(bp, offset, aeu_mask);
12467
12468         /* Enable the GPIO to trigger interrupt */
12469         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12470         val |= 1 << (gpio_num + (gpio_port << 2));
12471         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12472 }