drivers/net/bnx2x/bnx2x_hsi.h

   1 /* bnx2x_hsi.h: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2011 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9 #ifndef BNX2X_HSI_H
  10 #define BNX2X_HSI_H
  11
  12 #include "bnx2x_fw_defs.h"
  13
  14 #define FW_ENCODE_32BIT_PATTERN         0x1e1e1e1e
  15
  16 struct license_key {
  17         u32 reserved[6];
  18
  19         u32 max_iscsi_conn;
  20 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK  0xFFFF
  21 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
  22 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK  0xFFFF0000
  23 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
  24
  25         u32 reserved_a;
  26
  27         u32 max_fcoe_conn;
  28 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK   0xFFFF
  29 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT  0
  30 #define BNX2X_MAX_FCOE_INIT_CONN_MASK   0xFFFF0000
  31 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT  16
  32
  33         u32 reserved_b[4];
  34 };
  35
  36
  37 #define PORT_0              0
  38 #define PORT_1              1
  39 #define PORT_MAX            2
  40
  41 /****************************************************************************
  42  * Shared HW configuration                                                  *
  43  ****************************************************************************/
  44 #define PIN_CFG_NA                          0x00000000
  45 #define PIN_CFG_GPIO0_P0                    0x00000001
  46 #define PIN_CFG_GPIO1_P0                    0x00000002
  47 #define PIN_CFG_GPIO2_P0                    0x00000003
  48 #define PIN_CFG_GPIO3_P0                    0x00000004
  49 #define PIN_CFG_GPIO0_P1                    0x00000005
  50 #define PIN_CFG_GPIO1_P1                    0x00000006
  51 #define PIN_CFG_GPIO2_P1                    0x00000007
  52 #define PIN_CFG_GPIO3_P1                    0x00000008
  53 #define PIN_CFG_EPIO0                       0x00000009
  54 #define PIN_CFG_EPIO1                       0x0000000a
  55 #define PIN_CFG_EPIO2                       0x0000000b
  56 #define PIN_CFG_EPIO3                       0x0000000c
  57 #define PIN_CFG_EPIO4                       0x0000000d
  58 #define PIN_CFG_EPIO5                       0x0000000e
  59 #define PIN_CFG_EPIO6                       0x0000000f
  60 #define PIN_CFG_EPIO7                       0x00000010
  61 #define PIN_CFG_EPIO8                       0x00000011
  62 #define PIN_CFG_EPIO9                       0x00000012
  63 #define PIN_CFG_EPIO10                      0x00000013
  64 #define PIN_CFG_EPIO11                      0x00000014
  65 #define PIN_CFG_EPIO12                      0x00000015
  66 #define PIN_CFG_EPIO13                      0x00000016
  67 #define PIN_CFG_EPIO14                      0x00000017
  68 #define PIN_CFG_EPIO15                      0x00000018
  69 #define PIN_CFG_EPIO16                      0x00000019
  70 #define PIN_CFG_EPIO17                      0x0000001a
  71 #define PIN_CFG_EPIO18                      0x0000001b
  72 #define PIN_CFG_EPIO19                      0x0000001c
  73 #define PIN_CFG_EPIO20                      0x0000001d
  74 #define PIN_CFG_EPIO21                      0x0000001e
  75 #define PIN_CFG_EPIO22                      0x0000001f
  76 #define PIN_CFG_EPIO23                      0x00000020
  77 #define PIN_CFG_EPIO24                      0x00000021
  78 #define PIN_CFG_EPIO25                      0x00000022
  79 #define PIN_CFG_EPIO26                      0x00000023
  80 #define PIN_CFG_EPIO27                      0x00000024
  81 #define PIN_CFG_EPIO28                      0x00000025
  82 #define PIN_CFG_EPIO29                      0x00000026
  83 #define PIN_CFG_EPIO30                      0x00000027
  84 #define PIN_CFG_EPIO31                      0x00000028
  85
  86 /* EPIO definition */
  87 #define EPIO_CFG_NA                         0x00000000
  88 #define EPIO_CFG_EPIO0                      0x00000001
  89 #define EPIO_CFG_EPIO1                      0x00000002
  90 #define EPIO_CFG_EPIO2                      0x00000003
  91 #define EPIO_CFG_EPIO3                      0x00000004
  92 #define EPIO_CFG_EPIO4                      0x00000005
  93 #define EPIO_CFG_EPIO5                      0x00000006
  94 #define EPIO_CFG_EPIO6                      0x00000007
  95 #define EPIO_CFG_EPIO7                      0x00000008
  96 #define EPIO_CFG_EPIO8                      0x00000009
  97 #define EPIO_CFG_EPIO9                      0x0000000a
  98 #define EPIO_CFG_EPIO10                     0x0000000b
  99 #define EPIO_CFG_EPIO11                     0x0000000c
 100 #define EPIO_CFG_EPIO12                     0x0000000d
 101 #define EPIO_CFG_EPIO13                     0x0000000e
 102 #define EPIO_CFG_EPIO14                     0x0000000f
 103 #define EPIO_CFG_EPIO15                     0x00000010
 104 #define EPIO_CFG_EPIO16                     0x00000011
 105 #define EPIO_CFG_EPIO17                     0x00000012
 106 #define EPIO_CFG_EPIO18                     0x00000013
 107 #define EPIO_CFG_EPIO19                     0x00000014
 108 #define EPIO_CFG_EPIO20                     0x00000015
 109 #define EPIO_CFG_EPIO21                     0x00000016
 110 #define EPIO_CFG_EPIO22                     0x00000017
 111 #define EPIO_CFG_EPIO23                     0x00000018
 112 #define EPIO_CFG_EPIO24                     0x00000019
 113 #define EPIO_CFG_EPIO25                     0x0000001a
 114 #define EPIO_CFG_EPIO26                     0x0000001b
 115 #define EPIO_CFG_EPIO27                     0x0000001c
 116 #define EPIO_CFG_EPIO28                     0x0000001d
 117 #define EPIO_CFG_EPIO29                     0x0000001e
 118 #define EPIO_CFG_EPIO30                     0x0000001f
 119 #define EPIO_CFG_EPIO31                     0x00000020
 120
 121
 122 struct shared_hw_cfg {                   /* NVRAM Offset */
 123         /* Up to 16 bytes of NULL-terminated string */
 124         u8  part_num[16];                   /* 0x104 */
 125
 126         u32 config;                     /* 0x114 */
 127         #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK             0x00000001
 128                 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT             0
 129                 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V              0x00000000
 130                 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V              0x00000001
 131         #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN        0x00000002
 132
 133         #define SHARED_HW_CFG_PORT_SWAP                     0x00000004
 134
 135         #define SHARED_HW_CFG_BEACON_WOL_EN                 0x00000008
 136
 137         #define SHARED_HW_CFG_PCIE_GEN3_DISABLED            0x00000000
 138         #define SHARED_HW_CFG_PCIE_GEN3_ENABLED             0x00000010
 139
 140         #define SHARED_HW_CFG_MFW_SELECT_MASK               0x00000700
 141                 #define SHARED_HW_CFG_MFW_SELECT_SHIFT               8
 142         /* Whatever MFW found in NVM
 143            (if multiple found, priority order is: NC-SI, UMP, IPMI) */
 144                 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT             0x00000000
 145                 #define SHARED_HW_CFG_MFW_SELECT_NC_SI               0x00000100
 146                 #define SHARED_HW_CFG_MFW_SELECT_UMP                 0x00000200
 147                 #define SHARED_HW_CFG_MFW_SELECT_IPMI                0x00000300
 148         /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
 149           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
 150                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI    0x00000400
 151         /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
 152           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
 153                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI      0x00000500
 154         /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
 155           (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
 156                 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP     0x00000600
 157
 158         #define SHARED_HW_CFG_LED_MODE_MASK                 0x000f0000
 159                 #define SHARED_HW_CFG_LED_MODE_SHIFT                 16
 160                 #define SHARED_HW_CFG_LED_MAC1                       0x00000000
 161                 #define SHARED_HW_CFG_LED_PHY1                       0x00010000
 162                 #define SHARED_HW_CFG_LED_PHY2                       0x00020000
 163                 #define SHARED_HW_CFG_LED_PHY3                       0x00030000
 164                 #define SHARED_HW_CFG_LED_MAC2                       0x00040000
 165                 #define SHARED_HW_CFG_LED_PHY4                       0x00050000
 166                 #define SHARED_HW_CFG_LED_PHY5                       0x00060000
 167                 #define SHARED_HW_CFG_LED_PHY6                       0x00070000
 168                 #define SHARED_HW_CFG_LED_MAC3                       0x00080000
 169                 #define SHARED_HW_CFG_LED_PHY7                       0x00090000
 170                 #define SHARED_HW_CFG_LED_PHY9                       0x000a0000
 171                 #define SHARED_HW_CFG_LED_PHY11                      0x000b0000
 172                 #define SHARED_HW_CFG_LED_MAC4                       0x000c0000
 173                 #define SHARED_HW_CFG_LED_PHY8                       0x000d0000
 174                 #define SHARED_HW_CFG_LED_EXTPHY1                    0x000e0000
 175
 176
 177         #define SHARED_HW_CFG_AN_ENABLE_MASK                0x3f000000
 178                 #define SHARED_HW_CFG_AN_ENABLE_SHIFT                24
 179                 #define SHARED_HW_CFG_AN_ENABLE_CL37                 0x01000000
 180                 #define SHARED_HW_CFG_AN_ENABLE_CL73                 0x02000000
 181                 #define SHARED_HW_CFG_AN_ENABLE_BAM                  0x04000000
 182                 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION   0x08000000
 183                 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT  0x10000000
 184                 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY           0x20000000
 185
 186         #define SHARED_HW_CFG_SRIOV_MASK                    0x40000000
 187                 #define SHARED_HW_CFG_SRIOV_DISABLED                 0x00000000
 188                 #define SHARED_HW_CFG_SRIOV_ENABLED                  0x40000000
 189
 190         #define SHARED_HW_CFG_ATC_MASK                      0x80000000
 191                 #define SHARED_HW_CFG_ATC_DISABLED                   0x00000000
 192                 #define SHARED_HW_CFG_ATC_ENABLED                    0x80000000
 193
 194         u32 config2;                        /* 0x118 */
 195         /* one time auto detect grace period (in sec) */
 196         #define SHARED_HW_CFG_GRACE_PERIOD_MASK             0x000000ff
 197         #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT                     0
 198
 199         #define SHARED_HW_CFG_PCIE_GEN2_ENABLED             0x00000100
 200         #define SHARED_HW_CFG_PCIE_GEN2_DISABLED            0x00000000
 201
 202         /* The default value for the core clock is 250MHz and it is
 203            achieved by setting the clock change to 4 */
 204         #define SHARED_HW_CFG_CLOCK_CHANGE_MASK             0x00000e00
 205         #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT                     9
 206
 207         #define SHARED_HW_CFG_SMBUS_TIMING_MASK             0x00001000
 208                 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ            0x00000000
 209                 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ            0x00001000
 210
 211         #define SHARED_HW_CFG_HIDE_PORT1                    0x00002000
 212
 213         #define SHARED_HW_CFG_WOL_CAPABLE_MASK              0x00004000
 214                 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED           0x00000000
 215                 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED            0x00004000
 216
 217                 /* Output low when PERST is asserted */
 218         #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK       0x00008000
 219                 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED    0x00000000
 220                 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED     0x00008000
 221
 222         #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK    0x00070000
 223                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT    16
 224                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW       0x00000000
 225                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB      0x00010000
 226                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB    0x00020000
 227                 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB    0x00030000
 228
 229         /*  The fan failure mechanism is usually related to the PHY type
 230               since the power consumption of the board is determined by the PHY.
 231               Currently, fan is required for most designs with SFX7101, BCM8727
 232               and BCM8481. If a fan is not required for a board which uses one
 233               of those PHYs, this field should be set to "Disabled". If a fan is
 234               required for a different PHY type, this option should be set to
 235               "Enabled". The fan failure indication is expected on SPIO5 */
 236         #define SHARED_HW_CFG_FAN_FAILURE_MASK              0x00180000
 237                 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT              19
 238                 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE           0x00000000
 239                 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED           0x00080000
 240                 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED            0x00100000
 241
 242                 /* ASPM Power Management support */
 243         #define SHARED_HW_CFG_ASPM_SUPPORT_MASK             0x00600000
 244                 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT             21
 245                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED    0x00000000
 246                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED      0x00200000
 247                 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED       0x00400000
 248                 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED   0x00600000
 249
 250         /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
 251            tl_control_0 (register 0x2800) */
 252         #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK         0x00800000
 253                 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED      0x00000000
 254                 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED       0x00800000
 255
 256         #define SHARED_HW_CFG_PORT_MODE_MASK                0x01000000
 257                 #define SHARED_HW_CFG_PORT_MODE_2                    0x00000000
 258                 #define SHARED_HW_CFG_PORT_MODE_4                    0x01000000
 259
 260         #define SHARED_HW_CFG_PATH_SWAP_MASK                0x02000000
 261                 #define SHARED_HW_CFG_PATH_SWAP_DISABLED             0x00000000
 262                 #define SHARED_HW_CFG_PATH_SWAP_ENABLED              0x02000000
 263
 264         /*  Set the MDC/MDIO access for the first external phy */
 265         #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK         0x1C000000
 266                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT         26
 267                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE      0x00000000
 268                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0         0x04000000
 269                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1         0x08000000
 270                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH          0x0c000000
 271                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED       0x10000000
 272
 273         /*  Set the MDC/MDIO access for the second external phy */
 274         #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK         0xE0000000
 275                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT         29
 276                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE      0x00000000
 277                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0         0x20000000
 278                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1         0x40000000
 279                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH          0x60000000
 280                 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED       0x80000000
 281
 282
 283         u32 power_dissipated;                   /* 0x11c */
 284         #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK         0x00ff0000
 285                 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT         16
 286                 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE       0x00000000
 287                 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT          0x00010000
 288                 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT         0x00020000
 289                 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT        0x00030000
 290
 291         #define SHARED_HW_CFG_POWER_DIS_CMN_MASK            0xff000000
 292         #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT                    24
 293
 294         u32 ump_nc_si_config;                   /* 0x120 */
 295         #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK       0x00000003
 296                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT       0
 297                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC         0x00000000
 298                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY         0x00000001
 299                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII         0x00000000
 300                 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII        0x00000002
 301
 302         #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK       0x00000f00
 303                 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT       8
 304
 305         #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK   0x00ff0000
 306                 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT   16
 307                 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE    0x00000000
 308                 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
 309
 310         u32 board;                      /* 0x124 */
 311         #define SHARED_HW_CFG_E3_I2C_MUX0_MASK              0x0000003F
 312         #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT                      0
 313         #define SHARED_HW_CFG_E3_I2C_MUX1_MASK              0x00000FC0
 314         #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT                      6
 315         /* Use the PIN_CFG_XXX defines on top */
 316         #define SHARED_HW_CFG_BOARD_REV_MASK                0x00ff0000
 317         #define SHARED_HW_CFG_BOARD_REV_SHIFT                        16
 318
 319         #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK          0x0f000000
 320         #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT                  24
 321
 322         #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK          0xf0000000
 323         #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT                  28
 324
 325         u32 wc_lane_config;                                 /* 0x128 */
 326         #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK            0x0000FFFF
 327                 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT            0
 328                 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210         0x00001b1b
 329                 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123         0x00001be4
 330                 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210         0x0000e41b
 331                 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123         0x0000e4e4
 332         #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK         0x000000FF
 333         #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                 0
 334         #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK         0x0000FF00
 335         #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                 8
 336
 337         /* TX lane Polarity swap */
 338         #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED     0x00010000
 339         #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED     0x00020000
 340         #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED     0x00040000
 341         #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED     0x00080000
 342         /* TX lane Polarity swap */
 343         #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED     0x00100000
 344         #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED     0x00200000
 345         #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED     0x00400000
 346         #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED     0x00800000
 347
 348         /*  Selects the port layout of the board */
 349         #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK           0x0F000000
 350                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT           24
 351                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01           0x00000000
 352                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10           0x01000000
 353                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123         0x02000000
 354                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032         0x03000000
 355                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301         0x04000000
 356                 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210         0x05000000
 357 };
 358
 359
 360 /****************************************************************************
 361  * Port HW configuration                                                    *
 362  ****************************************************************************/
 363 struct port_hw_cfg {                /* port 0: 0x12c  port 1: 0x2bc */
 364
 365         u32 pci_id;
 366         #define PORT_HW_CFG_PCI_VENDOR_ID_MASK              0xffff0000
 367         #define PORT_HW_CFG_PCI_DEVICE_ID_MASK              0x0000ffff
 368
 369         u32 pci_sub_id;
 370         #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK       0xffff0000
 371         #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK       0x0000ffff
 372
 373         u32 power_dissipated;
 374         #define PORT_HW_CFG_POWER_DIS_D0_MASK               0x000000ff
 375         #define PORT_HW_CFG_POWER_DIS_D0_SHIFT                       0
 376         #define PORT_HW_CFG_POWER_DIS_D1_MASK               0x0000ff00
 377         #define PORT_HW_CFG_POWER_DIS_D1_SHIFT                       8
 378         #define PORT_HW_CFG_POWER_DIS_D2_MASK               0x00ff0000
 379         #define PORT_HW_CFG_POWER_DIS_D2_SHIFT                       16
 380         #define PORT_HW_CFG_POWER_DIS_D3_MASK               0xff000000
 381         #define PORT_HW_CFG_POWER_DIS_D3_SHIFT                       24
 382
 383         u32 power_consumed;
 384         #define PORT_HW_CFG_POWER_CONS_D0_MASK              0x000000ff
 385         #define PORT_HW_CFG_POWER_CONS_D0_SHIFT                      0
 386         #define PORT_HW_CFG_POWER_CONS_D1_MASK              0x0000ff00
 387         #define PORT_HW_CFG_POWER_CONS_D1_SHIFT                      8
 388         #define PORT_HW_CFG_POWER_CONS_D2_MASK              0x00ff0000
 389         #define PORT_HW_CFG_POWER_CONS_D2_SHIFT                      16
 390         #define PORT_HW_CFG_POWER_CONS_D3_MASK              0xff000000
 391         #define PORT_HW_CFG_POWER_CONS_D3_SHIFT                      24
 392
 393         u32 mac_upper;
 394         #define PORT_HW_CFG_UPPERMAC_MASK                   0x0000ffff
 395         #define PORT_HW_CFG_UPPERMAC_SHIFT                           0
 396         u32 mac_lower;
 397
 398         u32 iscsi_mac_upper;  /* Upper 16 bits are always zeroes */
 399         u32 iscsi_mac_lower;
 400
 401         u32 rdma_mac_upper;   /* Upper 16 bits are always zeroes */
 402         u32 rdma_mac_lower;
 403
 404         u32 serdes_config;
 405         #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
 406         #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT         0
 407
 408         #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK    0xffff0000
 409         #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT            16
 410
 411
 412         /*  Default values: 2P-64, 4P-32 */
 413         u32 pf_config;                                      /* 0x158 */
 414         #define PORT_HW_CFG_PF_NUM_VF_MASK                  0x0000007F
 415         #define PORT_HW_CFG_PF_NUM_VF_SHIFT                          0
 416
 417         /*  Default values: 17 */
 418         #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK        0x00007F00
 419         #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT                8
 420
 421         #define PORT_HW_CFG_ENABLE_FLR_MASK                 0x00010000
 422         #define PORT_HW_CFG_FLR_ENABLED                     0x00010000
 423
 424         u32 vf_config;                                      /* 0x15C */
 425         #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK        0x0000007F
 426         #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT                0
 427
 428         #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK           0xFFFF0000
 429         #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT                   16
 430
 431         u32 mf_pci_id;                                      /* 0x160 */
 432         #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK           0x0000FFFF
 433         #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT                   0
 434
 435         /*  Controls the TX laser of the SFP+ module */
 436         u32 sfp_ctrl;                                       /* 0x164 */
 437         #define PORT_HW_CFG_TX_LASER_MASK                   0x000000FF
 438                 #define PORT_HW_CFG_TX_LASER_SHIFT                   0
 439                 #define PORT_HW_CFG_TX_LASER_MDIO                    0x00000000
 440                 #define PORT_HW_CFG_TX_LASER_GPIO0                   0x00000001
 441                 #define PORT_HW_CFG_TX_LASER_GPIO1                   0x00000002
 442                 #define PORT_HW_CFG_TX_LASER_GPIO2                   0x00000003
 443                 #define PORT_HW_CFG_TX_LASER_GPIO3                   0x00000004
 444
 445         /*  Controls the fault module LED of the SFP+ */
 446         #define PORT_HW_CFG_FAULT_MODULE_LED_MASK           0x0000FF00
 447                 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT           8
 448                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0           0x00000000
 449                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1           0x00000100
 450                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2           0x00000200
 451                 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3           0x00000300
 452                 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED        0x00000400
 453
 454         /*  The output pin TX_DIS that controls the TX laser of the SFP+
 455           module. Use the PIN_CFG_XXX defines on top */
 456         u32 e3_sfp_ctrl;                                    /* 0x168 */
 457         #define PORT_HW_CFG_E3_TX_LASER_MASK                0x000000FF
 458         #define PORT_HW_CFG_E3_TX_LASER_SHIFT                        0
 459
 460         /*  The output pin for SFPP_TYPE which turns on the Fault module LED */
 461         #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK           0x0000FF00
 462         #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT                   8
 463
 464         /*  The input pin MOD_ABS that indicates whether SFP+ module is
 465           present or not. Use the PIN_CFG_XXX defines on top */
 466         #define PORT_HW_CFG_E3_MOD_ABS_MASK                 0x00FF0000
 467         #define PORT_HW_CFG_E3_MOD_ABS_SHIFT                         16
 468
 469         /*  The output pin PWRDIS_SFP_X which disable the power of the SFP+
 470           module. Use the PIN_CFG_XXX defines on top */
 471         #define PORT_HW_CFG_E3_PWR_DIS_MASK                 0xFF000000
 472         #define PORT_HW_CFG_E3_PWR_DIS_SHIFT                         24
 473
 474         /*
 475          * The input pin which signals module transmit fault. Use the
 476          * PIN_CFG_XXX defines on top
 477          */
 478         u32 e3_cmn_pin_cfg;                                 /* 0x16C */
 479         #define PORT_HW_CFG_E3_TX_FAULT_MASK                0x000000FF
 480         #define PORT_HW_CFG_E3_TX_FAULT_SHIFT                        0
 481
 482         /*  The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
 483          top */
 484         #define PORT_HW_CFG_E3_PHY_RESET_MASK               0x0000FF00
 485         #define PORT_HW_CFG_E3_PHY_RESET_SHIFT                       8
 486
 487         /*
 488          * The output pin which powers down the PHY. Use the PIN_CFG_XXX
 489          * defines on top
 490          */
 491         #define PORT_HW_CFG_E3_PWR_DOWN_MASK                0x00FF0000
 492         #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT                        16
 493
 494         /*  The output pin values BSC_SEL which selects the I2C for this port
 495           in the I2C Mux */
 496         #define PORT_HW_CFG_E3_I2C_MUX0_MASK                0x01000000
 497         #define PORT_HW_CFG_E3_I2C_MUX1_MASK                0x02000000
 498
 499
 500         /*
 501          * The input pin I_FAULT which indicate over-current has occurred.
 502          * Use the PIN_CFG_XXX defines on top
 503          */
 504         u32 e3_cmn_pin_cfg1;                                /* 0x170 */
 505         #define PORT_HW_CFG_E3_OVER_CURRENT_MASK            0x000000FF
 506         #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT                    0
 507         u32 reserved0[7];                                   /* 0x174 */
 508
 509         u32 aeu_int_mask;                                   /* 0x190 */
 510
 511         u32 media_type;                                     /* 0x194 */
 512         #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK            0x000000FF
 513         #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT                    0
 514
 515         #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK            0x0000FF00
 516         #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT                    8
 517
 518         #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK            0x00FF0000
 519         #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT                    16
 520
 521         /*  4 times 16 bits for all 4 lanes. In case external PHY is present
 522               (not direct mode), those values will not take effect on the 4 XGXS
 523               lanes. For some external PHYs (such as 8706 and 8726) the values
 524               will be used to configure the external PHY  in those cases, not
 525               all 4 values are needed. */
 526         u16 xgxs_config_rx[4];                  /* 0x198 */
 527         u16 xgxs_config_tx[4];                  /* 0x1A0 */
 528
 529         /* For storing FCOE mac on shared memory */
 530         u32 fcoe_fip_mac_upper;
 531         #define PORT_HW_CFG_FCOE_UPPERMAC_MASK              0x0000ffff
 532         #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT                      0
 533         u32 fcoe_fip_mac_lower;
 534
 535         u32 fcoe_wwn_port_name_upper;
 536         u32 fcoe_wwn_port_name_lower;
 537
 538         u32 fcoe_wwn_node_name_upper;
 539         u32 fcoe_wwn_node_name_lower;
 540
 541         u32 Reserved1[49];                                  /* 0x1C0 */
 542
 543         /*  Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
 544               84833 only */
 545         u32 xgbt_phy_cfg;                                   /* 0x284 */
 546         #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK             0x000000FF
 547         #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT                     0
 548
 549                 u32 default_cfg;                            /* 0x288 */
 550         #define PORT_HW_CFG_GPIO0_CONFIG_MASK               0x00000003
 551                 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT               0
 552                 #define PORT_HW_CFG_GPIO0_CONFIG_NA                  0x00000000
 553                 #define PORT_HW_CFG_GPIO0_CONFIG_LOW                 0x00000001
 554                 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH                0x00000002
 555                 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT               0x00000003
 556
 557         #define PORT_HW_CFG_GPIO1_CONFIG_MASK               0x0000000C
 558                 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT               2
 559                 #define PORT_HW_CFG_GPIO1_CONFIG_NA                  0x00000000
 560                 #define PORT_HW_CFG_GPIO1_CONFIG_LOW                 0x00000004
 561                 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH                0x00000008
 562                 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT               0x0000000c
 563
 564         #define PORT_HW_CFG_GPIO2_CONFIG_MASK               0x00000030
 565                 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT               4
 566                 #define PORT_HW_CFG_GPIO2_CONFIG_NA                  0x00000000
 567                 #define PORT_HW_CFG_GPIO2_CONFIG_LOW                 0x00000010
 568                 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH                0x00000020
 569                 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT               0x00000030
 570
 571         #define PORT_HW_CFG_GPIO3_CONFIG_MASK               0x000000C0
 572                 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT               6
 573                 #define PORT_HW_CFG_GPIO3_CONFIG_NA                  0x00000000
 574                 #define PORT_HW_CFG_GPIO3_CONFIG_LOW                 0x00000040
 575                 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH                0x00000080
 576                 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT               0x000000c0
 577
 578         /*  When KR link is required to be set to force which is not
 579               KR-compliant, this parameter determine what is the trigger for it.
 580               When GPIO is selected, low input will force the speed. Currently
 581               default speed is 1G. In the future, it may be widen to select the
 582               forced speed in with another parameter. Note when force-1G is
 583               enabled, it override option 56: Link Speed option. */
 584         #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK           0x00000F00
 585                 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT           8
 586                 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED      0x00000000
 587                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0        0x00000100
 588                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0        0x00000200
 589                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0        0x00000300
 590                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0        0x00000400
 591                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1        0x00000500
 592                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1        0x00000600
 593                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1        0x00000700
 594                 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1        0x00000800
 595                 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED          0x00000900
 596         /*  Enable to determine with which GPIO to reset the external phy */
 597         #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK           0x000F0000
 598                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT           16
 599                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE        0x00000000
 600                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0        0x00010000
 601                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0        0x00020000
 602                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0        0x00030000
 603                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0        0x00040000
 604                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1        0x00050000
 605                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1        0x00060000
 606                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1        0x00070000
 607                 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1        0x00080000
 608
 609         /*  Enable BAM on KR */
 610         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK           0x00100000
 611         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT                   20
 612         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED                0x00000000
 613         #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED                 0x00100000
 614
 615         /*  Enable Common Mode Sense */
 616         #define PORT_HW_CFG_ENABLE_CMS_MASK                 0x00200000
 617         #define PORT_HW_CFG_ENABLE_CMS_SHIFT                         21
 618         #define PORT_HW_CFG_ENABLE_CMS_DISABLED                      0x00000000
 619         #define PORT_HW_CFG_ENABLE_CMS_ENABLED                       0x00200000
 620
 621         /*  Enable RJ45 magjack pair swapping on 10GBase-T PHY, 84833 only */
 622         #define PORT_HW_CFG_RJ45_PR_SWP_MASK                0x00400000
 623         #define PORT_HW_CFG_RJ45_PR_SWP_SHIFT                        22
 624         #define PORT_HW_CFG_RJ45_PR_SWP_DISABLED                     0x00000000
 625         #define PORT_HW_CFG_RJ45_PR_SWP_ENABLED                      0x00400000
 626
 627         /*  Determine the Serdes electrical interface   */
 628         #define PORT_HW_CFG_NET_SERDES_IF_MASK              0x0F000000
 629         #define PORT_HW_CFG_NET_SERDES_IF_SHIFT                      24
 630         #define PORT_HW_CFG_NET_SERDES_IF_SGMII                      0x00000000
 631         #define PORT_HW_CFG_NET_SERDES_IF_XFI                        0x01000000
 632         #define PORT_HW_CFG_NET_SERDES_IF_SFI                        0x02000000
 633         #define PORT_HW_CFG_NET_SERDES_IF_KR                         0x03000000
 634         #define PORT_HW_CFG_NET_SERDES_IF_DXGXS                      0x04000000
 635         #define PORT_HW_CFG_NET_SERDES_IF_KR2                        0x05000000
 636
 637
 638         u32 speed_capability_mask2;                         /* 0x28C */
 639         #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK       0x0000FFFF
 640                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT       0
 641                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL    0x00000001
 642                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__           0x00000002
 643                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___          0x00000004
 644                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL   0x00000008
 645                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G          0x00000010
 646                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G    0x00000020
 647                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G         0x00000040
 648                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G         0x00000080
 649
 650         #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK       0xFFFF0000
 651                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT       16
 652                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL    0x00010000
 653                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__           0x00020000
 654                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___          0x00040000
 655                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL   0x00080000
 656                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G          0x00100000
 657                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G    0x00200000
 658                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G         0x00400000
 659                 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G         0x00800000
 660
 661
 662         /*  In the case where two media types (e.g. copper and fiber) are
 663               present and electrically active at the same time, PHY Selection
 664               will determine which of the two PHYs will be designated as the
 665               Active PHY and used for a connection to the network.  */
 666         u32 multi_phy_config;                               /* 0x290 */
 667         #define PORT_HW_CFG_PHY_SELECTION_MASK              0x00000007
 668                 #define PORT_HW_CFG_PHY_SELECTION_SHIFT              0
 669                 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT   0x00000000
 670                 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY          0x00000001
 671                 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY         0x00000002
 672                 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
 673                 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
 674
 675         /*  When enabled, all second phy nvram parameters will be swapped
 676               with the first phy parameters */
 677         #define PORT_HW_CFG_PHY_SWAPPED_MASK                0x00000008
 678                 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT                3
 679                 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED             0x00000000
 680                 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED              0x00000008
 681
 682
 683         /*  Address of the second external phy */
 684         u32 external_phy_config2;                           /* 0x294 */
 685         #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK         0x000000FF
 686         #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT                 0
 687
 688         /*  The second XGXS external PHY type */
 689         #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK         0x0000FF00
 690                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT         8
 691                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT        0x00000000
 692                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071       0x00000100
 693                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072       0x00000200
 694                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073       0x00000300
 695                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705       0x00000400
 696                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706       0x00000500
 697                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726       0x00000600
 698                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481       0x00000700
 699                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101       0x00000800
 700                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727       0x00000900
 701                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC   0x00000a00
 702                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823      0x00000b00
 703                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640      0x00000c00
 704                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833      0x00000d00
 705                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE    0x00000e00
 706                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722       0x00000f00
 707                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE       0x0000fd00
 708                 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN      0x0000ff00
 709
 710
 711         /*  4 times 16 bits for all 4 lanes. For some external PHYs (such as
 712               8706, 8726 and 8727) not all 4 values are needed. */
 713         u16 xgxs_config2_rx[4];                             /* 0x296 */
 714         u16 xgxs_config2_tx[4];                             /* 0x2A0 */
 715
 716         u32 lane_config;
 717         #define PORT_HW_CFG_LANE_SWAP_CFG_MASK              0x0000ffff
 718                 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT              0
 719                 /* AN and forced */
 720                 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123           0x00001b1b
 721                 /* forced only */
 722                 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210           0x00001be4
 723                 /* forced only */
 724                 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120           0x0000d8d8
 725                 /* forced only */
 726                 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210           0x0000e4e4
 727         #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK           0x000000ff
 728         #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT                   0
 729         #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK           0x0000ff00
 730         #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT                   8
 731         #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK       0x0000c000
 732         #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT               14
 733
 734         /*  Indicate whether to swap the external phy polarity */
 735         #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK          0x00010000
 736                 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED       0x00000000
 737                 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED        0x00010000
 738
 739
 740         u32 external_phy_config;
 741         #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK          0x000000ff
 742         #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT                  0
 743
 744         #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK          0x0000ff00
 745                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT          8
 746                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT         0x00000000
 747                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071        0x00000100
 748                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072        0x00000200
 749                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073        0x00000300
 750                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705        0x00000400
 751                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706        0x00000500
 752                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726        0x00000600
 753                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481        0x00000700
 754                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101        0x00000800
 755                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727        0x00000900
 756                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC    0x00000a00
 757                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823       0x00000b00
 758                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640       0x00000c00
 759                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833       0x00000d00
 760                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE     0x00000e00
 761                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722        0x00000f00
 762                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC      0x0000fc00
 763                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE        0x0000fd00
 764                 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN       0x0000ff00
 765
 766         #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK        0x00ff0000
 767         #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT                16
 768
 769         #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK        0xff000000
 770                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT        24
 771                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT       0x00000000
 772                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482      0x01000000
 773                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD    0x02000000
 774                 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN     0xff000000
 775
 776         u32 speed_capability_mask;
 777         #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK        0x0000ffff
 778                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT        0
 779                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL     0x00000001
 780                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF     0x00000002
 781                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF    0x00000004
 782                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL    0x00000008
 783                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G           0x00000010
 784                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G         0x00000020
 785                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G          0x00000040
 786                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G          0x00000080
 787                 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED     0x0000f000
 788
 789         #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK        0xffff0000
 790                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT        16
 791                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL     0x00010000
 792                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF     0x00020000
 793                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF    0x00040000
 794                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL    0x00080000
 795                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G           0x00100000
 796                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G         0x00200000
 797                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G          0x00400000
 798                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G          0x00800000
 799                 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED     0xf0000000
 800
 801         /*  A place to hold the original MAC address as a backup */
 802         u32 backup_mac_upper;                   /* 0x2B4 */
 803         u32 backup_mac_lower;                   /* 0x2B8 */
 804
 805 };
 806
 807
 808 /****************************************************************************
 809  * Shared Feature configuration                                             *
 810  ****************************************************************************/
 811 struct shared_feat_cfg {                 /* NVRAM Offset */
 812
 813         u32 config;                     /* 0x450 */
 814         #define SHARED_FEATURE_BMC_ECHO_MODE_EN             0x00000001
 815
 816         /* Use NVRAM values instead of HW default values */
 817         #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
 818                                                             0x00000002
 819                 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
 820                                                                      0x00000000
 821                 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
 822                                                                      0x00000002
 823
 824         #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK         0x00000008
 825                 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO          0x00000000
 826                 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM         0x00000008
 827
 828         #define SHARED_FEAT_CFG_NCSI_ID_MASK                0x00000030
 829         #define SHARED_FEAT_CFG_NCSI_ID_SHIFT                        4
 830
 831         /*  Override the OTP back to single function mode. When using GPIO,
 832               high means only SF, 0 is according to CLP configuration */
 833         #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK          0x00000700
 834                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT          8
 835                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED     0x00000000
 836                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF      0x00000100
 837                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4          0x00000200
 838                 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT  0x00000300
 839
 840         /* The interval in seconds between sending LLDP packets. Set to zero
 841            to disable the feature */
 842         #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK     0x00ff0000
 843         #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT             16
 844
 845         /* The assigned device type ID for LLDP usage */
 846         #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK    0xff000000
 847         #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT            24
 848
 849 };
 850
 851
 852 /****************************************************************************
 853  * Port Feature configuration                                               *
 854  ****************************************************************************/
 855 struct port_feat_cfg {              /* port 0: 0x454  port 1: 0x4c8 */
 856
 857         u32 config;
 858         #define PORT_FEATURE_BAR1_SIZE_MASK                 0x0000000f
 859                 #define PORT_FEATURE_BAR1_SIZE_SHIFT                 0
 860                 #define PORT_FEATURE_BAR1_SIZE_DISABLED              0x00000000
 861                 #define PORT_FEATURE_BAR1_SIZE_64K                   0x00000001
 862                 #define PORT_FEATURE_BAR1_SIZE_128K                  0x00000002
 863                 #define PORT_FEATURE_BAR1_SIZE_256K                  0x00000003
 864                 #define PORT_FEATURE_BAR1_SIZE_512K                  0x00000004
 865                 #define PORT_FEATURE_BAR1_SIZE_1M                    0x00000005
 866                 #define PORT_FEATURE_BAR1_SIZE_2M                    0x00000006
 867                 #define PORT_FEATURE_BAR1_SIZE_4M                    0x00000007
 868                 #define PORT_FEATURE_BAR1_SIZE_8M                    0x00000008
 869                 #define PORT_FEATURE_BAR1_SIZE_16M                   0x00000009
 870                 #define PORT_FEATURE_BAR1_SIZE_32M                   0x0000000a
 871                 #define PORT_FEATURE_BAR1_SIZE_64M                   0x0000000b
 872                 #define PORT_FEATURE_BAR1_SIZE_128M                  0x0000000c
 873                 #define PORT_FEATURE_BAR1_SIZE_256M                  0x0000000d
 874                 #define PORT_FEATURE_BAR1_SIZE_512M                  0x0000000e
 875                 #define PORT_FEATURE_BAR1_SIZE_1G                    0x0000000f
 876         #define PORT_FEATURE_BAR2_SIZE_MASK                 0x000000f0
 877                 #define PORT_FEATURE_BAR2_SIZE_SHIFT                 4
 878                 #define PORT_FEATURE_BAR2_SIZE_DISABLED              0x00000000
 879                 #define PORT_FEATURE_BAR2_SIZE_64K                   0x00000010
 880                 #define PORT_FEATURE_BAR2_SIZE_128K                  0x00000020
 881                 #define PORT_FEATURE_BAR2_SIZE_256K                  0x00000030
 882                 #define PORT_FEATURE_BAR2_SIZE_512K                  0x00000040
 883                 #define PORT_FEATURE_BAR2_SIZE_1M                    0x00000050
 884                 #define PORT_FEATURE_BAR2_SIZE_2M                    0x00000060
 885                 #define PORT_FEATURE_BAR2_SIZE_4M                    0x00000070
 886                 #define PORT_FEATURE_BAR2_SIZE_8M                    0x00000080
 887                 #define PORT_FEATURE_BAR2_SIZE_16M                   0x00000090
 888                 #define PORT_FEATURE_BAR2_SIZE_32M                   0x000000a0
 889                 #define PORT_FEATURE_BAR2_SIZE_64M                   0x000000b0
 890                 #define PORT_FEATURE_BAR2_SIZE_128M                  0x000000c0
 891                 #define PORT_FEATURE_BAR2_SIZE_256M                  0x000000d0
 892                 #define PORT_FEATURE_BAR2_SIZE_512M                  0x000000e0
 893                 #define PORT_FEATURE_BAR2_SIZE_1G                    0x000000f0
 894
 895         #define PORT_FEAT_CFG_DCBX_MASK                     0x00000100
 896                 #define PORT_FEAT_CFG_DCBX_DISABLED                  0x00000000
 897                 #define PORT_FEAT_CFG_DCBX_ENABLED                   0x00000100
 898
 899         #define PORT_FEAT_CFG_AUTOGREEN_MASK                0x00000200
 900         #define PORT_FEAT_CFG_AUTOGREEN_SHIFT                        9
 901         #define PORT_FEAT_CFG_AUTOGREEN_DISABLED                     0x00000000
 902         #define PORT_FEAT_CFG_AUTOGREEN_ENABLED                      0x00000200
 903
 904         #define PORT_FEATURE_EN_SIZE_MASK                   0x0f000000
 905         #define PORT_FEATURE_EN_SIZE_SHIFT                           24
 906         #define PORT_FEATURE_WOL_ENABLED                             0x01000000
 907         #define PORT_FEATURE_MBA_ENABLED                             0x02000000
 908         #define PORT_FEATURE_MFW_ENABLED                             0x04000000
 909
 910         /* Advertise expansion ROM even if MBA is disabled */
 911         #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK        0x08000000
 912                 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED     0x00000000
 913                 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED      0x08000000
 914
 915         /* Check the optic vendor via i2c against a list of approved modules
 916            in a separate nvram image */
 917         #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK         0xe0000000
 918                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT         29
 919                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
 920                                                                      0x00000000
 921                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
 922                                                                      0x20000000
 923                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG   0x40000000
 924                 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN    0x60000000
 925
 926         u32 wol_config;
 927         /* Default is used when driver sets to "auto" mode */
 928         #define PORT_FEATURE_WOL_DEFAULT_MASK               0x00000003
 929                 #define PORT_FEATURE_WOL_DEFAULT_SHIFT               0
 930                 #define PORT_FEATURE_WOL_DEFAULT_DISABLE             0x00000000
 931                 #define PORT_FEATURE_WOL_DEFAULT_MAGIC               0x00000001
 932                 #define PORT_FEATURE_WOL_DEFAULT_ACPI                0x00000002
 933                 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI      0x00000003
 934         #define PORT_FEATURE_WOL_RES_PAUSE_CAP              0x00000004
 935         #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP         0x00000008
 936         #define PORT_FEATURE_WOL_ACPI_UPON_MGMT             0x00000010
 937
 938         u32 mba_config;
 939         #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK       0x00000007
 940                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT       0
 941                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE         0x00000000
 942                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL         0x00000001
 943                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP       0x00000002
 944                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB      0x00000003
 945                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT   0x00000004
 946                 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE        0x00000007
 947
 948         #define PORT_FEATURE_MBA_BOOT_RETRY_MASK            0x00000038
 949         #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT                    3
 950
 951         #define PORT_FEATURE_MBA_RES_PAUSE_CAP              0x00000100
 952         #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP         0x00000200
 953         #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE        0x00000400
 954         #define PORT_FEATURE_MBA_HOTKEY_MASK                0x00000800
 955                 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S               0x00000000
 956                 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B               0x00000800
 957         #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK          0x000ff000
 958                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT          12
 959                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED       0x00000000
 960                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K             0x00001000
 961                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K             0x00002000
 962                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K             0x00003000
 963                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K            0x00004000
 964                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K            0x00005000
 965                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K            0x00006000
 966                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K           0x00007000
 967                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K           0x00008000
 968                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K           0x00009000
 969                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M             0x0000a000
 970                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M             0x0000b000
 971                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M             0x0000c000
 972                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M             0x0000d000
 973                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M            0x0000e000
 974                 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M            0x0000f000
 975         #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK           0x00f00000
 976         #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT                   20
 977         #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK        0x03000000
 978                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT        24
 979                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO         0x00000000
 980                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS          0x01000000
 981                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H       0x02000000
 982                 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H       0x03000000
 983         #define PORT_FEATURE_MBA_LINK_SPEED_MASK            0x3c000000
 984                 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT            26
 985                 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO             0x00000000
 986                 #define PORT_FEATURE_MBA_LINK_SPEED_10HD             0x04000000
 987                 #define PORT_FEATURE_MBA_LINK_SPEED_10FD             0x08000000
 988                 #define PORT_FEATURE_MBA_LINK_SPEED_100HD            0x0c000000
 989                 #define PORT_FEATURE_MBA_LINK_SPEED_100FD            0x10000000
 990                 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS            0x14000000
 991                 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS          0x18000000
 992                 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4       0x1c000000
 993                 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS           0x20000000
 994         u32 bmc_config;
 995         #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK         0x00000001
 996                 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT       0x00000000
 997                 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN            0x00000001
 998
 999         u32 mba_vlan_cfg;
1000         #define PORT_FEATURE_MBA_VLAN_TAG_MASK              0x0000ffff
1001         #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT                      0
1002         #define PORT_FEATURE_MBA_VLAN_EN                    0x00010000
1003
1004         u32 resource_cfg;
1005         #define PORT_FEATURE_RESOURCE_CFG_VALID             0x00000001
1006         #define PORT_FEATURE_RESOURCE_CFG_DIAG              0x00000002
1007         #define PORT_FEATURE_RESOURCE_CFG_L2                0x00000004
1008         #define PORT_FEATURE_RESOURCE_CFG_ISCSI             0x00000008
1009         #define PORT_FEATURE_RESOURCE_CFG_RDMA              0x00000010
1010
1011         u32 smbus_config;
1012         #define PORT_FEATURE_SMBUS_ADDR_MASK                0x000000fe
1013         #define PORT_FEATURE_SMBUS_ADDR_SHIFT                        1
1014
1015         u32 vf_config;
1016         #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK             0x0000000f
1017                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT             0
1018                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED          0x00000000
1019                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K                0x00000001
1020                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K                0x00000002
1021                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K               0x00000003
1022                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K               0x00000004
1023                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K               0x00000005
1024                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K              0x00000006
1025                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K              0x00000007
1026                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K              0x00000008
1027                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M                0x00000009
1028                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M                0x0000000a
1029                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M                0x0000000b
1030                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M                0x0000000c
1031                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M               0x0000000d
1032                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M               0x0000000e
1033                 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M               0x0000000f
1034
1035         u32 link_config;    /* Used as HW defaults for the driver */
1036         #define PORT_FEATURE_CONNECTED_SWITCH_MASK          0x03000000
1037                 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT          24
1038                 /* (forced) low speed switch (< 10G) */
1039                 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH            0x00000000
1040                 /* (forced) high speed switch (>= 10G) */
1041                 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH           0x01000000
1042                 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT          0x02000000
1043                 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT      0x03000000
1044
1045         #define PORT_FEATURE_LINK_SPEED_MASK                0x000f0000
1046                 #define PORT_FEATURE_LINK_SPEED_SHIFT                16
1047                 #define PORT_FEATURE_LINK_SPEED_AUTO                 0x00000000
1048                 #define PORT_FEATURE_LINK_SPEED_10M_FULL             0x00010000
1049                 #define PORT_FEATURE_LINK_SPEED_10M_HALF             0x00020000
1050                 #define PORT_FEATURE_LINK_SPEED_100M_HALF            0x00030000
1051                 #define PORT_FEATURE_LINK_SPEED_100M_FULL            0x00040000
1052                 #define PORT_FEATURE_LINK_SPEED_1G                   0x00050000
1053                 #define PORT_FEATURE_LINK_SPEED_2_5G                 0x00060000
1054                 #define PORT_FEATURE_LINK_SPEED_10G_CX4              0x00070000
1055                 #define PORT_FEATURE_LINK_SPEED_20G                  0x00080000
1056
1057         #define PORT_FEATURE_FLOW_CONTROL_MASK              0x00000700
1058                 #define PORT_FEATURE_FLOW_CONTROL_SHIFT              8
1059                 #define PORT_FEATURE_FLOW_CONTROL_AUTO               0x00000000
1060                 #define PORT_FEATURE_FLOW_CONTROL_TX                 0x00000100
1061                 #define PORT_FEATURE_FLOW_CONTROL_RX                 0x00000200
1062                 #define PORT_FEATURE_FLOW_CONTROL_BOTH               0x00000300
1063                 #define PORT_FEATURE_FLOW_CONTROL_NONE               0x00000400
1064
1065         /* The default for MCP link configuration,
1066            uses the same defines as link_config */
1067         u32 mfw_wol_link_cfg;
1068
1069         /* The default for the driver of the second external phy,
1070            uses the same defines as link_config */
1071         u32 link_config2;                                   /* 0x47C */
1072
1073         /* The default for MCP of the second external phy,
1074            uses the same defines as link_config */
1075         u32 mfw_wol_link_cfg2;                              /* 0x480 */
1076
1077         u32 Reserved2[17];                                  /* 0x484 */
1078
1079 };
1080
1081
1082 /****************************************************************************
1083  * Device Information                                                       *
1084  ****************************************************************************/
1085 struct shm_dev_info {                           /* size */
1086
1087         u32    bc_rev; /* 8 bits each: major, minor, build */          /* 4 */
1088
1089         struct shared_hw_cfg     shared_hw_config;            /* 40 */
1090
1091         struct port_hw_cfg       port_hw_config[PORT_MAX];     /* 400*2=800 */
1092
1093         struct shared_feat_cfg   shared_feature_config;            /* 4 */
1094
1095         struct port_feat_cfg     port_feature_config[PORT_MAX];/* 116*2=232 */
1096
1097 };
1098
1099
1100 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1101         #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1102 #endif
1103
1104 #define FUNC_0              0
1105 #define FUNC_1              1
1106 #define FUNC_2              2
1107 #define FUNC_3              3
1108 #define FUNC_4              4
1109 #define FUNC_5              5
1110 #define FUNC_6              6
1111 #define FUNC_7              7
1112 #define E1_FUNC_MAX         2
1113 #define E1H_FUNC_MAX            8
1114 #define E2_FUNC_MAX         4   /* per path */
1115
1116 #define VN_0                0
1117 #define VN_1                1
1118 #define VN_2                2
1119 #define VN_3                3
1120 #define E1VN_MAX            1
1121 #define E1HVN_MAX           4
1122
1123 #define E2_VF_MAX           64  /* HC_REG_VF_CONFIGURATION_SIZE */
1124 /* This value (in milliseconds) determines the frequency of the driver
1125  * issuing the PULSE message code.  The firmware monitors this periodic
1126  * pulse to determine when to switch to an OS-absent mode. */
1127 #define DRV_PULSE_PERIOD_MS     250
1128
1129 /* This value (in milliseconds) determines how long the driver should
1130  * wait for an acknowledgement from the firmware before timing out.  Once
1131  * the firmware has timed out, the driver will assume there is no firmware
1132  * running and there won't be any firmware-driver synchronization during a
1133  * driver reset. */
1134 #define FW_ACK_TIME_OUT_MS      5000
1135
1136 #define FW_ACK_POLL_TIME_MS     1
1137
1138 #define FW_ACK_NUM_OF_POLL  (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1139
1140 /* LED Blink rate that will achieve ~15.9Hz */
1141 #define LED_BLINK_RATE_VAL      480
1142
1143 /****************************************************************************
1144  * Driver <-> FW Mailbox                                                    *
1145  ****************************************************************************/
1146 struct drv_port_mb {
1147
1148         u32 link_status;
1149         /* Driver should update this field on any link change event */
1150
1151         #define LINK_STATUS_LINK_FLAG_MASK                      0x00000001
1152         #define LINK_STATUS_LINK_UP                             0x00000001
1153         #define LINK_STATUS_SPEED_AND_DUPLEX_MASK               0x0000001E
1154         #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE    (0<<1)
1155         #define LINK_STATUS_SPEED_AND_DUPLEX_10THD              (1<<1)
1156         #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD              (2<<1)
1157         #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD            (3<<1)
1158         #define LINK_STATUS_SPEED_AND_DUPLEX_100T4              (4<<1)
1159         #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD            (5<<1)
1160         #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD            (6<<1)
1161         #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD            (7<<1)
1162         #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD            (7<<1)
1163         #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD            (8<<1)
1164         #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD            (9<<1)
1165         #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD            (9<<1)
1166         #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD             (10<<1)
1167         #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD             (10<<1)
1168         #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD             (11<<1)
1169         #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD             (11<<1)
1170
1171         #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK            0x00000020
1172         #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED              0x00000020
1173
1174         #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE             0x00000040
1175         #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK        0x00000080
1176         #define LINK_STATUS_PARALLEL_DETECTION_USED             0x00000080
1177
1178         #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE        0x00000200
1179         #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE        0x00000400
1180         #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE          0x00000800
1181         #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE        0x00001000
1182         #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE        0x00002000
1183         #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE          0x00004000
1184         #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE          0x00008000
1185
1186         #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK           0x00010000
1187         #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00010000
1188
1189         #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK           0x00020000
1190         #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00020000
1191
1192         #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
1193         #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0<<18)
1194         #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1<<18)
1195         #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2<<18)
1196         #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3<<18)
1197
1198         #define LINK_STATUS_SERDES_LINK                         0x00100000
1199
1200         #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE        0x00200000
1201         #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE        0x00400000
1202         #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE         0x00800000
1203         #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE         0x10000000
1204
1205         #define LINK_STATUS_PFC_ENABLED                         0x20000000
1206
1207         #define LINK_STATUS_PHYSICAL_LINK_FLAG                  0x40000000
1208
1209         u32 port_stx;
1210
1211         u32 stat_nig_timer;
1212
1213         /* MCP firmware does not use this field */
1214         u32 ext_phy_fw_version;
1215
1216 };
1217
1218
1219 struct drv_func_mb {
1220
1221         u32 drv_mb_header;
1222         #define DRV_MSG_CODE_MASK                       0xffff0000
1223         #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
1224         #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
1225         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN          0x20000000
1226         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS         0x20010000
1227         #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP         0x20020000
1228         #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
1229         #define DRV_MSG_CODE_DCC_OK                     0x30000000
1230         #define DRV_MSG_CODE_DCC_FAILURE                0x31000000
1231         #define DRV_MSG_CODE_DIAG_ENTER_REQ             0x50000000
1232         #define DRV_MSG_CODE_DIAG_EXIT_REQ              0x60000000
1233         #define DRV_MSG_CODE_VALIDATE_KEY               0x70000000
1234         #define DRV_MSG_CODE_GET_CURR_KEY               0x80000000
1235         #define DRV_MSG_CODE_GET_UPGRADE_KEY            0x81000000
1236         #define DRV_MSG_CODE_GET_MANUF_KEY              0x82000000
1237         #define DRV_MSG_CODE_LOAD_L2B_PRAM              0x90000000
1238         /*
1239          * The optic module verification command requires bootcode
1240          * v5.0.6 or later, te specific optic module verification command
1241          * requires bootcode v5.2.12 or later
1242          */
1243         #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL     0xa0000000
1244         #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL     0x00050006
1245         #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL  0xa1000000
1246         #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL  0x00050234
1247         #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED   0x00070014
1248
1249         #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG         0xb0000000
1250         #define DRV_MSG_CODE_DCBX_PMF_DRV_OK            0xb2000000
1251
1252         #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
1253
1254         #define DRV_MSG_CODE_SET_MF_BW                  0xe0000000
1255         #define REQ_BC_VER_4_SET_MF_BW                  0x00060202
1256         #define DRV_MSG_CODE_SET_MF_BW_ACK              0xe1000000
1257
1258         #define DRV_MSG_CODE_LINK_STATUS_CHANGED        0x01000000
1259
1260         #define BIOS_MSG_CODE_LIC_CHALLENGE             0xff010000
1261         #define BIOS_MSG_CODE_LIC_RESPONSE              0xff020000
1262         #define BIOS_MSG_CODE_VIRT_MAC_PRIM             0xff030000
1263         #define BIOS_MSG_CODE_VIRT_MAC_ISCSI            0xff040000
1264
1265         #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
1266
1267         u32 drv_mb_param;
1268         #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK         0x00ff0000
1269         #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK         0xff000000
1270
1271         u32 fw_mb_header;
1272         #define FW_MSG_CODE_MASK                        0xffff0000
1273         #define FW_MSG_CODE_DRV_LOAD_COMMON             0x10100000
1274         #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
1275         #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
1276         /* Load common chip is supported from bc 6.0.0  */
1277         #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP       0x00060000
1278         #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP        0x10130000
1279
1280         #define FW_MSG_CODE_DRV_LOAD_REFUSED            0x10200000
1281         #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
1282         #define FW_MSG_CODE_DRV_UNLOAD_COMMON           0x20100000
1283         #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20110000
1284         #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20120000
1285         #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
1286         #define FW_MSG_CODE_DCC_DONE                    0x30100000
1287         #define FW_MSG_CODE_LLDP_DONE                   0x40100000
1288         #define FW_MSG_CODE_DIAG_ENTER_DONE             0x50100000
1289         #define FW_MSG_CODE_DIAG_REFUSE                 0x50200000
1290         #define FW_MSG_CODE_DIAG_EXIT_DONE              0x60100000
1291         #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS        0x70100000
1292         #define FW_MSG_CODE_VALIDATE_KEY_FAILURE        0x70200000
1293         #define FW_MSG_CODE_GET_KEY_DONE                0x80100000
1294         #define FW_MSG_CODE_NO_KEY                      0x80f00000
1295         #define FW_MSG_CODE_LIC_INFO_NOT_READY          0x80f80000
1296         #define FW_MSG_CODE_L2B_PRAM_LOADED             0x90100000
1297         #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE     0x90210000
1298         #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE     0x90220000
1299         #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE     0x90230000
1300         #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE     0x90240000
1301         #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS        0xa0100000
1302         #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG      0xa0200000
1303         #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED     0xa0300000
1304         #define FW_MSG_CODE_VF_DISABLED_DONE            0xb0000000
1305
1306         #define FW_MSG_CODE_SET_MF_BW_SENT              0xe0000000
1307         #define FW_MSG_CODE_SET_MF_BW_DONE              0xe1000000
1308
1309         #define FW_MSG_CODE_LINK_CHANGED_ACK            0x01100000
1310
1311         #define FW_MSG_CODE_LIC_CHALLENGE               0xff010000
1312         #define FW_MSG_CODE_LIC_RESPONSE                0xff020000
1313         #define FW_MSG_CODE_VIRT_MAC_PRIM               0xff030000
1314         #define FW_MSG_CODE_VIRT_MAC_ISCSI              0xff040000
1315
1316         #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
1317
1318         u32 fw_mb_param;
1319
1320         u32 drv_pulse_mb;
1321         #define DRV_PULSE_SEQ_MASK                      0x00007fff
1322         #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
1323         /*
1324          * The system time is in the format of
1325          * (year-2001)*12*32 + month*32 + day.
1326          */
1327         #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
1328         /*
1329          * Indicate to the firmware not to go into the
1330          * OS-absent when it is not getting driver pulse.
1331          * This is used for debugging as well for PXE(MBA).
1332          */
1333
1334         u32 mcp_pulse_mb;
1335         #define MCP_PULSE_SEQ_MASK                      0x00007fff
1336         #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
1337         /* Indicates to the driver not to assert due to lack
1338          * of MCP response */
1339         #define MCP_EVENT_MASK                          0xffff0000
1340         #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
1341
1342         u32 iscsi_boot_signature;
1343         u32 iscsi_boot_block_offset;
1344
1345         u32 drv_status;
1346         #define DRV_STATUS_PMF                          0x00000001
1347         #define DRV_STATUS_VF_DISABLED                  0x00000002
1348         #define DRV_STATUS_SET_MF_BW                    0x00000004
1349         #define DRV_STATUS_LINK_EVENT                   0x00000008
1350
1351         #define DRV_STATUS_DCC_EVENT_MASK               0x0000ff00
1352         #define DRV_STATUS_DCC_DISABLE_ENABLE_PF        0x00000100
1353         #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION     0x00000200
1354         #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS       0x00000400
1355         #define DRV_STATUS_DCC_RESERVED1                0x00000800
1356         #define DRV_STATUS_DCC_SET_PROTOCOL             0x00001000
1357         #define DRV_STATUS_DCC_SET_PRIORITY             0x00002000
1358
1359         #define DRV_STATUS_DCBX_EVENT_MASK              0x000f0000
1360         #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS     0x00010000
1361
1362         u32 virt_mac_upper;
1363         #define VIRT_MAC_SIGN_MASK                      0xffff0000
1364         #define VIRT_MAC_SIGNATURE                      0x564d0000
1365         u32 virt_mac_lower;
1366
1367 };
1368
1369
1370 /****************************************************************************
1371  * Management firmware state                                                *
1372  ****************************************************************************/
1373 /* Allocate 440 bytes for management firmware */
1374 #define MGMTFW_STATE_WORD_SIZE                          110
1375
1376 struct mgmtfw_state {
1377         u32 opaque[MGMTFW_STATE_WORD_SIZE];
1378 };
1379
1380
1381 /****************************************************************************
1382  * Multi-Function configuration                                             *
1383  ****************************************************************************/
1384 struct shared_mf_cfg {
1385
1386         u32 clp_mb;
1387         #define SHARED_MF_CLP_SET_DEFAULT               0x00000000
1388         /* set by CLP */
1389         #define SHARED_MF_CLP_EXIT                      0x00000001
1390         /* set by MCP */
1391         #define SHARED_MF_CLP_EXIT_DONE                 0x00010000
1392
1393 };
1394
1395 struct port_mf_cfg {
1396
1397         u32 dynamic_cfg;    /* device control channel */
1398         #define PORT_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1399         #define PORT_MF_CFG_E1HOV_TAG_SHIFT             0
1400         #define PORT_MF_CFG_E1HOV_TAG_DEFAULT         PORT_MF_CFG_E1HOV_TAG_MASK
1401
1402         u32 reserved[3];
1403
1404 };
1405
1406 struct func_mf_cfg {
1407
1408         u32 config;
1409         /* E/R/I/D */
1410         /* function 0 of each port cannot be hidden */
1411         #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
1412
1413         #define FUNC_MF_CFG_PROTOCOL_MASK               0x00000006
1414         #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000000
1415         #define FUNC_MF_CFG_PROTOCOL_ETHERNET           0x00000002
1416         #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1417         #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000006
1418         #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1419                                 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1420
1421         #define FUNC_MF_CFG_FUNC_DISABLED               0x00000008
1422         #define FUNC_MF_CFG_FUNC_DELETED                0x00000010
1423
1424         /* PRI */
1425         /* 0 - low priority, 3 - high priority */
1426         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK      0x00000300
1427         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT     8
1428         #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT   0x00000000
1429
1430         /* MINBW, MAXBW */
1431         /* value range - 0..100, increments in 100Mbps */
1432         #define FUNC_MF_CFG_MIN_BW_MASK                 0x00ff0000
1433         #define FUNC_MF_CFG_MIN_BW_SHIFT                16
1434         #define FUNC_MF_CFG_MIN_BW_DEFAULT              0x00000000
1435         #define FUNC_MF_CFG_MAX_BW_MASK                 0xff000000
1436         #define FUNC_MF_CFG_MAX_BW_SHIFT                24
1437         #define FUNC_MF_CFG_MAX_BW_DEFAULT              0x64000000
1438
1439         u32 mac_upper;      /* MAC */
1440         #define FUNC_MF_CFG_UPPERMAC_MASK               0x0000ffff
1441         #define FUNC_MF_CFG_UPPERMAC_SHIFT              0
1442         #define FUNC_MF_CFG_UPPERMAC_DEFAULT           FUNC_MF_CFG_UPPERMAC_MASK
1443         u32 mac_lower;
1444         #define FUNC_MF_CFG_LOWERMAC_DEFAULT            0xffffffff
1445
1446         u32 e1hov_tag;  /* VNI */
1447         #define FUNC_MF_CFG_E1HOV_TAG_MASK              0x0000ffff
1448         #define FUNC_MF_CFG_E1HOV_TAG_SHIFT             0
1449         #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT         FUNC_MF_CFG_E1HOV_TAG_MASK
1450
1451         u32 reserved[2];
1452 };
1453
1454 /* This structure is not applicable and should not be accessed on 57711 */
1455 struct func_ext_cfg {
1456         u32 func_cfg;
1457         #define MACP_FUNC_CFG_FLAGS_MASK                0x000000FF
1458         #define MACP_FUNC_CFG_FLAGS_SHIFT               0
1459         #define MACP_FUNC_CFG_FLAGS_ENABLED             0x00000001
1460         #define MACP_FUNC_CFG_FLAGS_ETHERNET            0x00000002
1461         #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD       0x00000004
1462         #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD        0x00000008
1463
1464         u32 iscsi_mac_addr_upper;
1465         u32 iscsi_mac_addr_lower;
1466
1467         u32 fcoe_mac_addr_upper;
1468         u32 fcoe_mac_addr_lower;
1469
1470         u32 fcoe_wwn_port_name_upper;
1471         u32 fcoe_wwn_port_name_lower;
1472
1473         u32 fcoe_wwn_node_name_upper;
1474         u32 fcoe_wwn_node_name_lower;
1475
1476         u32 preserve_data;
1477         #define MF_FUNC_CFG_PRESERVE_L2_MAC             (1<<0)
1478         #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC          (1<<1)
1479         #define MF_FUNC_CFG_PRESERVE_FCOE_MAC           (1<<2)
1480         #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P         (1<<3)
1481         #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N         (1<<4)
1482         #define MF_FUNC_CFG_PRESERVE_TX_BW              (1<<5)
1483 };
1484
1485 struct mf_cfg {
1486
1487         struct shared_mf_cfg    shared_mf_config;       /* 0x4 */
1488         struct port_mf_cfg  port_mf_config[PORT_MAX];   /* 0x10 * 2 = 0x20 */
1489         /* for all chips, there are 8 mf functions */
1490         struct func_mf_cfg  func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1491         /*
1492          * Extended configuration per function  - this array does not exist and
1493          * should not be accessed on 57711
1494          */
1495         struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1496 }; /* 0x224 */
1497
1498 /****************************************************************************
1499  * Shared Memory Region                                                     *
1500  ****************************************************************************/
1501 struct shmem_region {                  /*   SharedMem Offset (size) */
1502
1503         u32         validity_map[PORT_MAX];  /* 0x0 (4*2 = 0x8) */
1504         #define SHR_MEM_FORMAT_REV_MASK                     0xff000000
1505         #define SHR_MEM_FORMAT_REV_ID                       ('A'<<24)
1506         /* validity bits */
1507         #define SHR_MEM_VALIDITY_PCI_CFG                    0x00100000
1508         #define SHR_MEM_VALIDITY_MB                         0x00200000
1509         #define SHR_MEM_VALIDITY_DEV_INFO                   0x00400000
1510         #define SHR_MEM_VALIDITY_RESERVED                   0x00000007
1511         /* One licensing bit should be set */
1512         #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK     0x00000038
1513         #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT    0x00000008
1514         #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT  0x00000010
1515         #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT       0x00000020
1516         /* Active MFW */
1517         #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN         0x00000000
1518         #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK            0x000001c0
1519         #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI            0x00000040
1520         #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP             0x00000080
1521         #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI            0x000000c0
1522         #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE            0x000001c0
1523
1524         struct shm_dev_info dev_info;        /* 0x8     (0x438) */
1525
1526         struct license_key       drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1527
1528         /* FW information (for internal FW use) */
1529         u32         fw_info_fio_offset;         /* 0x4a8       (0x4) */
1530         struct mgmtfw_state mgmtfw_state;       /* 0x4ac     (0x1b8) */
1531
1532         struct drv_port_mb  port_mb[PORT_MAX];  /* 0x664 (16*2=0x20) */
1533
1534 #ifdef BMAPI
1535         /* This is a variable length array */
1536         /* the number of function depends on the chip type */
1537         struct drv_func_mb func_mb[1];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1538 #else
1539         /* the number of function depends on the chip type */
1540         struct drv_func_mb  func_mb[];  /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1541 #endif /* BMAPI */
1542
1543 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1544
1545 /****************************************************************************
1546  * Shared Memory 2 Region                                                   *
1547  ****************************************************************************/
1548 /* The fw_flr_ack is actually built in the following way:                   */
1549 /* 8 bit:  PF ack                                                           */
1550 /* 64 bit: VF ack                                                           */
1551 /* 8 bit:  ios_dis_ack                                                      */
1552 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1553 /* u32. The fw must have the VF right after the PF since this is how it     */
1554 /* access arrays(it expects always the VF to reside after the PF, and that  */
1555 /* makes the calculation much easier for it. )                              */
1556 /* In order to answer both limitations, and keep the struct small, the code */
1557 /* will abuse the structure defined here to achieve the actual partition    */
1558 /* above                                                                    */
1559 /****************************************************************************/
1560 struct fw_flr_ack {
1561         u32         pf_ack;
1562         u32         vf_ack[1];
1563         u32         iov_dis_ack;
1564 };
1565
1566 struct fw_flr_mb {
1567         u32         aggint;
1568         u32         opgen_addr;
1569         struct fw_flr_ack ack;
1570 };
1571
1572 /**** SUPPORT FOR SHMEM ARRRAYS ***
1573  * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1574  * define arrays with storage types smaller then unsigned dwords.
1575  * The macros below add generic support for SHMEM arrays with numeric elements
1576  * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1577  * array with individual bit-filed elements accessed using shifts and masks.
1578  *
1579  */
1580
1581 /* eb is the bitwidth of a single element */
1582 #define SHMEM_ARRAY_MASK(eb)            ((1<<(eb))-1)
1583 #define SHMEM_ARRAY_ENTRY(i, eb)        ((i)/(32/(eb)))
1584
1585 /* the bit-position macro allows the used to flip the order of the arrays
1586  * elements on a per byte or word boundary.
1587  *
1588  * example: an array with 8 entries each 4 bit wide. This array will fit into
1589  * a single dword. The diagrmas below show the array order of the nibbles.
1590  *
1591  * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1592  *
1593  *                |                |                |               |
1594  *   0    |   1   |   2    |   3   |   4    |   5   |   6   |   7   |
1595  *                |                |                |               |
1596  *
1597  * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1598  *
1599  *                |                |                |               |
1600  *   1   |   0    |   3    |   2   |   5    |   4   |   7   |   6   |
1601  *                |                |                |               |
1602  *
1603  * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1604  *
1605  *                |                |                |               |
1606  *   3   |   2    |   1   |   0    |   7   |   6    |   5   |   4   |
1607  *                |                |                |               |
1608  */
1609 #define SHMEM_ARRAY_BITPOS(i, eb, fb)   \
1610         ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1611         (((i)%((fb)/(eb))) * (eb)))
1612
1613 #define SHMEM_ARRAY_GET(a, i, eb, fb)                                   \
1614         ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
1615         SHMEM_ARRAY_MASK(eb))
1616
1617 #define SHMEM_ARRAY_SET(a, i, eb, fb, val)                              \
1618 do {                                                                       \
1619         a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<           \
1620         SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
1621         a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
1622         SHMEM_ARRAY_BITPOS(i, eb, fb));                                    \
1623 } while (0)
1624
1625
1626 /****START OF DCBX STRUCTURES DECLARATIONS****/
1627 #define DCBX_MAX_NUM_PRI_PG_ENTRIES     8
1628 #define DCBX_PRI_PG_BITWIDTH            4
1629 #define DCBX_PRI_PG_FBITS               8
1630 #define DCBX_PRI_PG_GET(a, i)           \
1631         SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1632 #define DCBX_PRI_PG_SET(a, i, val)      \
1633         SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1634 #define DCBX_MAX_NUM_PG_BW_ENTRIES      8
1635 #define DCBX_BW_PG_BITWIDTH             8
1636 #define DCBX_PG_BW_GET(a, i)            \
1637         SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1638 #define DCBX_PG_BW_SET(a, i, val)       \
1639         SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1640 #define DCBX_STRICT_PRI_PG              15
1641 #define DCBX_MAX_APP_PROTOCOL           16
1642 #define FCOE_APP_IDX                    0
1643 #define ISCSI_APP_IDX                   1
1644 #define PREDEFINED_APP_IDX_MAX          2
1645
1646
1647 /* Big/Little endian have the same representation. */
1648 struct dcbx_ets_feature {
1649         /*
1650          * For Admin MIB - is this feature supported by the
1651          * driver | For Local MIB - should this feature be enabled.
1652          */
1653         u32 enabled;
1654         u32  pg_bw_tbl[2];
1655         u32  pri_pg_tbl[1];
1656 };
1657
1658 /* Driver structure in LE */
1659 struct dcbx_pfc_feature {
1660 #ifdef __BIG_ENDIAN
1661         u8 pri_en_bitmap;
1662         #define DCBX_PFC_PRI_0 0x01
1663         #define DCBX_PFC_PRI_1 0x02
1664         #define DCBX_PFC_PRI_2 0x04
1665         #define DCBX_PFC_PRI_3 0x08
1666         #define DCBX_PFC_PRI_4 0x10
1667         #define DCBX_PFC_PRI_5 0x20
1668         #define DCBX_PFC_PRI_6 0x40
1669         #define DCBX_PFC_PRI_7 0x80
1670         u8 pfc_caps;
1671         u8 reserved;
1672         u8 enabled;
1673 #elif defined(__LITTLE_ENDIAN)
1674         u8 enabled;
1675         u8 reserved;
1676         u8 pfc_caps;
1677         u8 pri_en_bitmap;
1678         #define DCBX_PFC_PRI_0 0x01
1679         #define DCBX_PFC_PRI_1 0x02
1680         #define DCBX_PFC_PRI_2 0x04
1681         #define DCBX_PFC_PRI_3 0x08
1682         #define DCBX_PFC_PRI_4 0x10
1683         #define DCBX_PFC_PRI_5 0x20
1684         #define DCBX_PFC_PRI_6 0x40
1685         #define DCBX_PFC_PRI_7 0x80
1686 #endif
1687 };
1688
1689 struct dcbx_app_priority_entry {
1690 #ifdef __BIG_ENDIAN
1691         u16  app_id;
1692         u8  pri_bitmap;
1693         u8  appBitfield;
1694         #define DCBX_APP_ENTRY_VALID         0x01
1695         #define DCBX_APP_ENTRY_SF_MASK       0x30
1696         #define DCBX_APP_ENTRY_SF_SHIFT      4
1697         #define DCBX_APP_SF_ETH_TYPE         0x10
1698         #define DCBX_APP_SF_PORT             0x20
1699 #elif defined(__LITTLE_ENDIAN)
1700         u8 appBitfield;
1701         #define DCBX_APP_ENTRY_VALID         0x01
1702         #define DCBX_APP_ENTRY_SF_MASK       0x30
1703         #define DCBX_APP_ENTRY_SF_SHIFT      4
1704         #define DCBX_APP_SF_ETH_TYPE         0x10
1705         #define DCBX_APP_SF_PORT             0x20
1706         u8  pri_bitmap;
1707         u16  app_id;
1708 #endif
1709 };
1710
1711
1712 /* FW structure in BE */
1713 struct dcbx_app_priority_feature {
1714 #ifdef __BIG_ENDIAN
1715         u8 reserved;
1716         u8 default_pri;
1717         u8 tc_supported;
1718         u8 enabled;
1719 #elif defined(__LITTLE_ENDIAN)
1720         u8 enabled;
1721         u8 tc_supported;
1722         u8 default_pri;
1723         u8 reserved;
1724 #endif
1725         struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1726 };
1727
1728 /* FW structure in BE */
1729 struct dcbx_features {
1730         /* PG feature */
1731         struct dcbx_ets_feature ets;
1732         /* PFC feature */
1733         struct dcbx_pfc_feature pfc;
1734         /* APP feature */
1735         struct dcbx_app_priority_feature app;
1736 };
1737
1738 /* LLDP protocol parameters */
1739 /* FW structure in BE */
1740 struct lldp_params {
1741 #ifdef __BIG_ENDIAN
1742         u8  msg_fast_tx_interval;
1743         u8  msg_tx_hold;
1744         u8  msg_tx_interval;
1745         u8  admin_status;
1746         #define LLDP_TX_ONLY  0x01
1747         #define LLDP_RX_ONLY  0x02
1748         #define LLDP_TX_RX    0x03
1749         #define LLDP_DISABLED 0x04
1750         u8  reserved1;
1751         u8  tx_fast;
1752         u8  tx_crd_max;
1753         u8  tx_crd;
1754 #elif defined(__LITTLE_ENDIAN)
1755         u8  admin_status;
1756         #define LLDP_TX_ONLY  0x01
1757         #define LLDP_RX_ONLY  0x02
1758         #define LLDP_TX_RX    0x03
1759         #define LLDP_DISABLED 0x04
1760         u8  msg_tx_interval;
1761         u8  msg_tx_hold;
1762         u8  msg_fast_tx_interval;
1763         u8  tx_crd;
1764         u8  tx_crd_max;
1765         u8  tx_fast;
1766         u8  reserved1;
1767 #endif
1768         #define REM_CHASSIS_ID_STAT_LEN 4
1769         #define REM_PORT_ID_STAT_LEN 4
1770         /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1771         u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1772         /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1773         u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1774 };
1775
1776 struct lldp_dcbx_stat {
1777         #define LOCAL_CHASSIS_ID_STAT_LEN 2
1778         #define LOCAL_PORT_ID_STAT_LEN 2
1779         /* Holds local Chassis ID 8B payload of constant subtype 4. */
1780         u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1781         /* Holds local Port ID 8B payload of constant subtype 3. */
1782         u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1783         /* Number of DCBX frames transmitted. */
1784         u32 num_tx_dcbx_pkts;
1785         /* Number of DCBX frames received. */
1786         u32 num_rx_dcbx_pkts;
1787 };
1788
1789 /* ADMIN MIB - DCBX local machine default configuration. */
1790 struct lldp_admin_mib {
1791         u32     ver_cfg_flags;
1792         #define DCBX_ETS_CONFIG_TX_ENABLED       0x00000001
1793         #define DCBX_PFC_CONFIG_TX_ENABLED       0x00000002
1794         #define DCBX_APP_CONFIG_TX_ENABLED       0x00000004
1795         #define DCBX_ETS_RECO_TX_ENABLED         0x00000008
1796         #define DCBX_ETS_RECO_VALID              0x00000010
1797         #define DCBX_ETS_WILLING                 0x00000020
1798         #define DCBX_PFC_WILLING                 0x00000040
1799         #define DCBX_APP_WILLING                 0x00000080
1800         #define DCBX_VERSION_CEE                 0x00000100
1801         #define DCBX_VERSION_IEEE                0x00000200
1802         #define DCBX_DCBX_ENABLED                0x00000400
1803         #define DCBX_CEE_VERSION_MASK            0x0000f000
1804         #define DCBX_CEE_VERSION_SHIFT           12
1805         #define DCBX_CEE_MAX_VERSION_MASK        0x000f0000
1806         #define DCBX_CEE_MAX_VERSION_SHIFT       16
1807         struct dcbx_features     features;
1808 };
1809
1810 /* REMOTE MIB - remote machine DCBX configuration. */
1811 struct lldp_remote_mib {
1812         u32 prefix_seq_num;
1813         u32 flags;
1814         #define DCBX_ETS_TLV_RX                  0x00000001
1815         #define DCBX_PFC_TLV_RX                  0x00000002
1816         #define DCBX_APP_TLV_RX                  0x00000004
1817         #define DCBX_ETS_RX_ERROR                0x00000010
1818         #define DCBX_PFC_RX_ERROR                0x00000020
1819         #define DCBX_APP_RX_ERROR                0x00000040
1820         #define DCBX_ETS_REM_WILLING             0x00000100
1821         #define DCBX_PFC_REM_WILLING             0x00000200
1822         #define DCBX_APP_REM_WILLING             0x00000400
1823         #define DCBX_REMOTE_ETS_RECO_VALID       0x00001000
1824         #define DCBX_REMOTE_MIB_VALID            0x00002000
1825         struct dcbx_features features;
1826         u32 suffix_seq_num;
1827 };
1828
1829 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1830 struct lldp_local_mib {
1831         u32 prefix_seq_num;
1832         /* Indicates if there is mismatch with negotiation results. */
1833         u32 error;
1834         #define DCBX_LOCAL_ETS_ERROR             0x00000001
1835         #define DCBX_LOCAL_PFC_ERROR             0x00000002
1836         #define DCBX_LOCAL_APP_ERROR             0x00000004
1837         #define DCBX_LOCAL_PFC_MISMATCH          0x00000010
1838         #define DCBX_LOCAL_APP_MISMATCH          0x00000020
1839         #define DCBX_REMOTE_MIB_ERROR            0x00000040
1840         struct dcbx_features   features;
1841         u32 suffix_seq_num;
1842 };
1843 /***END OF DCBX STRUCTURES DECLARATIONS***/
1844
1845 struct ncsi_oem_fcoe_features {
1846         u32 fcoe_features1;
1847         #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK          0x0000FFFF
1848         #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET        0
1849
1850         #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK             0xFFFF0000
1851         #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET           16
1852
1853         u32 fcoe_features2;
1854         #define FCOE_FEATURES2_EXCHANGES_MASK                   0x0000FFFF
1855         #define FCOE_FEATURES2_EXCHANGES_OFFSET                 0
1856
1857         #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK           0xFFFF0000
1858         #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET         16
1859
1860         u32 fcoe_features3;
1861         #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK           0x0000FFFF
1862         #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET         0
1863
1864         #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK        0xFFFF0000
1865         #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET      16
1866
1867         u32 fcoe_features4;
1868         #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK            0x0000000F
1869         #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET          0
1870 };
1871
1872 struct ncsi_oem_data {
1873         u32 driver_version[4];
1874         struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
1875 };
1876
1877 struct shmem2_region {
1878
1879         u32 size;                                       /* 0x0000 */
1880
1881         u32 dcc_support;                                /* 0x0004 */
1882         #define SHMEM_DCC_SUPPORT_NONE                      0x00000000
1883         #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV     0x00000001
1884         #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV  0x00000004
1885         #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV    0x00000008
1886         #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV          0x00000040
1887         #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV          0x00000080
1888
1889         u32 ext_phy_fw_version2[PORT_MAX];              /* 0x0008 */
1890         /*
1891          * For backwards compatibility, if the mf_cfg_addr does not exist
1892          * (the size filed is smaller than 0xc) the mf_cfg resides at the
1893          * end of struct shmem_region
1894          */
1895         u32 mf_cfg_addr;                                /* 0x0010 */
1896         #define SHMEM_MF_CFG_ADDR_NONE                  0x00000000
1897
1898         struct fw_flr_mb flr_mb;                        /* 0x0014 */
1899         u32 dcbx_lldp_params_offset;                    /* 0x0028 */
1900         #define SHMEM_LLDP_DCBX_PARAMS_NONE             0x00000000
1901         u32 dcbx_neg_res_offset;                        /* 0x002c */
1902         #define SHMEM_DCBX_NEG_RES_NONE                 0x00000000
1903         u32 dcbx_remote_mib_offset;                     /* 0x0030 */
1904         #define SHMEM_DCBX_REMOTE_MIB_NONE              0x00000000
1905         /*
1906          * The other shmemX_base_addr holds the other path's shmem address
1907          * required for example in case of common phy init, or for path1 to know
1908          * the address of mcp debug trace which is located in offset from shmem
1909          * of path0
1910          */
1911         u32 other_shmem_base_addr;                      /* 0x0034 */
1912         u32 other_shmem2_base_addr;                     /* 0x0038 */
1913         /*
1914          * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
1915          * which were disabled/flred
1916          */
1917         u32 mcp_vf_disabled[E2_VF_MAX / 32];            /* 0x003c */
1918
1919         /*
1920          * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
1921          * VFs
1922          */
1923         u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
1924
1925         u32 dcbx_lldp_dcbx_stat_offset;                 /* 0x0064 */
1926         #define SHMEM_LLDP_DCBX_STAT_NONE               0x00000000
1927
1928         /*
1929          * edebug_driver_if field is used to transfer messages between edebug
1930          * app to the driver through shmem2.
1931          *
1932          * message format:
1933          * bits 0-2 -  function number / instance of driver to perform request
1934          * bits 3-5 -  op code / is_ack?
1935          * bits 6-63 - data
1936          */
1937         u32 edebug_driver_if[2];                        /* 0x0068 */
1938         #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR  1
1939         #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR   2
1940         #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT   3
1941
1942         u32 nvm_retain_bitmap_addr;                     /* 0x0070 */
1943
1944         u32     reserved1;      /* 0x0074 */
1945
1946         u32     reserved2[E2_FUNC_MAX];
1947
1948         u32     reserved3[E2_FUNC_MAX];/* 0x0088 */
1949         u32     reserved4[E2_FUNC_MAX];/* 0x0098 */
1950
1951         u32 swim_base_addr;                             /* 0x0108 */
1952         u32 swim_funcs;
1953         u32 swim_main_cb;
1954
1955         u32     reserved5[2];
1956
1957         /* generic flags controlled by the driver */
1958         u32 drv_flags;
1959         #define DRV_FLAGS_DCB_CONFIGURED                0x1
1960
1961         /* pointer to extended dev_info shared data copied from nvm image */
1962         u32 extended_dev_info_shared_addr;
1963         u32 ncsi_oem_data_addr;
1964
1965         u32 ocsd_host_addr;
1966         u32 ocbb_host_addr;
1967         u32 ocsd_req_update_interval;
1968 };
1969
1970
1971 struct emac_stats {
1972         u32     rx_stat_ifhcinoctets;
1973         u32     rx_stat_ifhcinbadoctets;
1974         u32     rx_stat_etherstatsfragments;
1975         u32     rx_stat_ifhcinucastpkts;
1976         u32     rx_stat_ifhcinmulticastpkts;
1977         u32     rx_stat_ifhcinbroadcastpkts;
1978         u32     rx_stat_dot3statsfcserrors;
1979         u32     rx_stat_dot3statsalignmenterrors;
1980         u32     rx_stat_dot3statscarriersenseerrors;
1981         u32     rx_stat_xonpauseframesreceived;
1982         u32     rx_stat_xoffpauseframesreceived;
1983         u32     rx_stat_maccontrolframesreceived;
1984         u32     rx_stat_xoffstateentered;
1985         u32     rx_stat_dot3statsframestoolong;
1986         u32     rx_stat_etherstatsjabbers;
1987         u32     rx_stat_etherstatsundersizepkts;
1988         u32     rx_stat_etherstatspkts64octets;
1989         u32     rx_stat_etherstatspkts65octetsto127octets;
1990         u32     rx_stat_etherstatspkts128octetsto255octets;
1991         u32     rx_stat_etherstatspkts256octetsto511octets;
1992         u32     rx_stat_etherstatspkts512octetsto1023octets;
1993         u32     rx_stat_etherstatspkts1024octetsto1522octets;
1994         u32     rx_stat_etherstatspktsover1522octets;
1995
1996         u32     rx_stat_falsecarriererrors;
1997
1998         u32     tx_stat_ifhcoutoctets;
1999         u32     tx_stat_ifhcoutbadoctets;
2000         u32     tx_stat_etherstatscollisions;
2001         u32     tx_stat_outxonsent;
2002         u32     tx_stat_outxoffsent;
2003         u32     tx_stat_flowcontroldone;
2004         u32     tx_stat_dot3statssinglecollisionframes;
2005         u32     tx_stat_dot3statsmultiplecollisionframes;
2006         u32     tx_stat_dot3statsdeferredtransmissions;
2007         u32     tx_stat_dot3statsexcessivecollisions;
2008         u32     tx_stat_dot3statslatecollisions;
2009         u32     tx_stat_ifhcoutucastpkts;
2010         u32     tx_stat_ifhcoutmulticastpkts;
2011         u32     tx_stat_ifhcoutbroadcastpkts;
2012         u32     tx_stat_etherstatspkts64octets;
2013         u32     tx_stat_etherstatspkts65octetsto127octets;
2014         u32     tx_stat_etherstatspkts128octetsto255octets;
2015         u32     tx_stat_etherstatspkts256octetsto511octets;
2016         u32     tx_stat_etherstatspkts512octetsto1023octets;
2017         u32     tx_stat_etherstatspkts1024octetsto1522octets;
2018         u32     tx_stat_etherstatspktsover1522octets;
2019         u32     tx_stat_dot3statsinternalmactransmiterrors;
2020 };
2021
2022
2023 struct bmac1_stats {
2024         u32     tx_stat_gtpkt_lo;
2025         u32     tx_stat_gtpkt_hi;
2026         u32     tx_stat_gtxpf_lo;
2027         u32     tx_stat_gtxpf_hi;
2028         u32     tx_stat_gtfcs_lo;
2029         u32     tx_stat_gtfcs_hi;
2030         u32     tx_stat_gtmca_lo;
2031         u32     tx_stat_gtmca_hi;
2032         u32     tx_stat_gtbca_lo;
2033         u32     tx_stat_gtbca_hi;
2034         u32     tx_stat_gtfrg_lo;
2035         u32     tx_stat_gtfrg_hi;
2036         u32     tx_stat_gtovr_lo;
2037         u32     tx_stat_gtovr_hi;
2038         u32     tx_stat_gt64_lo;
2039         u32     tx_stat_gt64_hi;
2040         u32     tx_stat_gt127_lo;
2041         u32     tx_stat_gt127_hi;
2042         u32     tx_stat_gt255_lo;
2043         u32     tx_stat_gt255_hi;
2044         u32     tx_stat_gt511_lo;
2045         u32     tx_stat_gt511_hi;
2046         u32     tx_stat_gt1023_lo;
2047         u32     tx_stat_gt1023_hi;
2048         u32     tx_stat_gt1518_lo;
2049         u32     tx_stat_gt1518_hi;
2050         u32     tx_stat_gt2047_lo;
2051         u32     tx_stat_gt2047_hi;
2052         u32     tx_stat_gt4095_lo;
2053         u32     tx_stat_gt4095_hi;
2054         u32     tx_stat_gt9216_lo;
2055         u32     tx_stat_gt9216_hi;
2056         u32     tx_stat_gt16383_lo;
2057         u32     tx_stat_gt16383_hi;
2058         u32     tx_stat_gtmax_lo;
2059         u32     tx_stat_gtmax_hi;
2060         u32     tx_stat_gtufl_lo;
2061         u32     tx_stat_gtufl_hi;
2062         u32     tx_stat_gterr_lo;
2063         u32     tx_stat_gterr_hi;
2064         u32     tx_stat_gtbyt_lo;
2065         u32     tx_stat_gtbyt_hi;
2066
2067         u32     rx_stat_gr64_lo;
2068         u32     rx_stat_gr64_hi;
2069         u32     rx_stat_gr127_lo;
2070         u32     rx_stat_gr127_hi;
2071         u32     rx_stat_gr255_lo;
2072         u32     rx_stat_gr255_hi;
2073         u32     rx_stat_gr511_lo;
2074         u32     rx_stat_gr511_hi;
2075         u32     rx_stat_gr1023_lo;
2076         u32     rx_stat_gr1023_hi;
2077         u32     rx_stat_gr1518_lo;
2078         u32     rx_stat_gr1518_hi;
2079         u32     rx_stat_gr2047_lo;
2080         u32     rx_stat_gr2047_hi;
2081         u32     rx_stat_gr4095_lo;
2082         u32     rx_stat_gr4095_hi;
2083         u32     rx_stat_gr9216_lo;
2084         u32     rx_stat_gr9216_hi;
2085         u32     rx_stat_gr16383_lo;
2086         u32     rx_stat_gr16383_hi;
2087         u32     rx_stat_grmax_lo;
2088         u32     rx_stat_grmax_hi;
2089         u32     rx_stat_grpkt_lo;
2090         u32     rx_stat_grpkt_hi;
2091         u32     rx_stat_grfcs_lo;
2092         u32     rx_stat_grfcs_hi;
2093         u32     rx_stat_grmca_lo;
2094         u32     rx_stat_grmca_hi;
2095         u32     rx_stat_grbca_lo;
2096         u32     rx_stat_grbca_hi;
2097         u32     rx_stat_grxcf_lo;
2098         u32     rx_stat_grxcf_hi;
2099         u32     rx_stat_grxpf_lo;
2100         u32     rx_stat_grxpf_hi;
2101         u32     rx_stat_grxuo_lo;
2102         u32     rx_stat_grxuo_hi;
2103         u32     rx_stat_grjbr_lo;
2104         u32     rx_stat_grjbr_hi;
2105         u32     rx_stat_grovr_lo;
2106         u32     rx_stat_grovr_hi;
2107         u32     rx_stat_grflr_lo;
2108         u32     rx_stat_grflr_hi;
2109         u32     rx_stat_grmeg_lo;
2110         u32     rx_stat_grmeg_hi;
2111         u32     rx_stat_grmeb_lo;
2112         u32     rx_stat_grmeb_hi;
2113         u32     rx_stat_grbyt_lo;
2114         u32     rx_stat_grbyt_hi;
2115         u32     rx_stat_grund_lo;
2116         u32     rx_stat_grund_hi;
2117         u32     rx_stat_grfrg_lo;
2118         u32     rx_stat_grfrg_hi;
2119         u32     rx_stat_grerb_lo;
2120         u32     rx_stat_grerb_hi;
2121         u32     rx_stat_grfre_lo;
2122         u32     rx_stat_grfre_hi;
2123         u32     rx_stat_gripj_lo;
2124         u32     rx_stat_gripj_hi;
2125 };
2126
2127 struct bmac2_stats {
2128         u32     tx_stat_gtpk_lo; /* gtpok */
2129         u32     tx_stat_gtpk_hi; /* gtpok */
2130         u32     tx_stat_gtxpf_lo; /* gtpf */
2131         u32     tx_stat_gtxpf_hi; /* gtpf */
2132         u32     tx_stat_gtpp_lo; /* NEW BMAC2 */
2133         u32     tx_stat_gtpp_hi; /* NEW BMAC2 */
2134         u32     tx_stat_gtfcs_lo;
2135         u32     tx_stat_gtfcs_hi;
2136         u32     tx_stat_gtuca_lo; /* NEW BMAC2 */
2137         u32     tx_stat_gtuca_hi; /* NEW BMAC2 */
2138         u32     tx_stat_gtmca_lo;
2139         u32     tx_stat_gtmca_hi;
2140         u32     tx_stat_gtbca_lo;
2141         u32     tx_stat_gtbca_hi;
2142         u32     tx_stat_gtovr_lo;
2143         u32     tx_stat_gtovr_hi;
2144         u32     tx_stat_gtfrg_lo;
2145         u32     tx_stat_gtfrg_hi;
2146         u32     tx_stat_gtpkt1_lo; /* gtpkt */
2147         u32     tx_stat_gtpkt1_hi; /* gtpkt */
2148         u32     tx_stat_gt64_lo;
2149         u32     tx_stat_gt64_hi;
2150         u32     tx_stat_gt127_lo;
2151         u32     tx_stat_gt127_hi;
2152         u32     tx_stat_gt255_lo;
2153         u32     tx_stat_gt255_hi;
2154         u32     tx_stat_gt511_lo;
2155         u32     tx_stat_gt511_hi;
2156         u32     tx_stat_gt1023_lo;
2157         u32     tx_stat_gt1023_hi;
2158         u32     tx_stat_gt1518_lo;
2159         u32     tx_stat_gt1518_hi;
2160         u32     tx_stat_gt2047_lo;
2161         u32     tx_stat_gt2047_hi;
2162         u32     tx_stat_gt4095_lo;
2163         u32     tx_stat_gt4095_hi;
2164         u32     tx_stat_gt9216_lo;
2165         u32     tx_stat_gt9216_hi;
2166         u32     tx_stat_gt16383_lo;
2167         u32     tx_stat_gt16383_hi;
2168         u32     tx_stat_gtmax_lo;
2169         u32     tx_stat_gtmax_hi;
2170         u32     tx_stat_gtufl_lo;
2171         u32     tx_stat_gtufl_hi;
2172         u32     tx_stat_gterr_lo;
2173         u32     tx_stat_gterr_hi;
2174         u32     tx_stat_gtbyt_lo;
2175         u32     tx_stat_gtbyt_hi;
2176
2177         u32     rx_stat_gr64_lo;
2178         u32     rx_stat_gr64_hi;
2179         u32     rx_stat_gr127_lo;
2180         u32     rx_stat_gr127_hi;
2181         u32     rx_stat_gr255_lo;
2182         u32     rx_stat_gr255_hi;
2183         u32     rx_stat_gr511_lo;
2184         u32     rx_stat_gr511_hi;
2185         u32     rx_stat_gr1023_lo;
2186         u32     rx_stat_gr1023_hi;
2187         u32     rx_stat_gr1518_lo;
2188         u32     rx_stat_gr1518_hi;
2189         u32     rx_stat_gr2047_lo;
2190         u32     rx_stat_gr2047_hi;
2191         u32     rx_stat_gr4095_lo;
2192         u32     rx_stat_gr4095_hi;
2193         u32     rx_stat_gr9216_lo;
2194         u32     rx_stat_gr9216_hi;
2195         u32     rx_stat_gr16383_lo;
2196         u32     rx_stat_gr16383_hi;
2197         u32     rx_stat_grmax_lo;
2198         u32     rx_stat_grmax_hi;
2199         u32     rx_stat_grpkt_lo;
2200         u32     rx_stat_grpkt_hi;
2201         u32     rx_stat_grfcs_lo;
2202         u32     rx_stat_grfcs_hi;
2203         u32     rx_stat_gruca_lo;
2204         u32     rx_stat_gruca_hi;
2205         u32     rx_stat_grmca_lo;
2206         u32     rx_stat_grmca_hi;
2207         u32     rx_stat_grbca_lo;
2208         u32     rx_stat_grbca_hi;
2209         u32     rx_stat_grxpf_lo; /* grpf */
2210         u32     rx_stat_grxpf_hi; /* grpf */
2211         u32     rx_stat_grpp_lo;
2212         u32     rx_stat_grpp_hi;
2213         u32     rx_stat_grxuo_lo; /* gruo */
2214         u32     rx_stat_grxuo_hi; /* gruo */
2215         u32     rx_stat_grjbr_lo;
2216         u32     rx_stat_grjbr_hi;
2217         u32     rx_stat_grovr_lo;
2218         u32     rx_stat_grovr_hi;
2219         u32     rx_stat_grxcf_lo; /* grcf */
2220         u32     rx_stat_grxcf_hi; /* grcf */
2221         u32     rx_stat_grflr_lo;
2222         u32     rx_stat_grflr_hi;
2223         u32     rx_stat_grpok_lo;
2224         u32     rx_stat_grpok_hi;
2225         u32     rx_stat_grmeg_lo;
2226         u32     rx_stat_grmeg_hi;
2227         u32     rx_stat_grmeb_lo;
2228         u32     rx_stat_grmeb_hi;
2229         u32     rx_stat_grbyt_lo;
2230         u32     rx_stat_grbyt_hi;
2231         u32     rx_stat_grund_lo;
2232         u32     rx_stat_grund_hi;
2233         u32     rx_stat_grfrg_lo;
2234         u32     rx_stat_grfrg_hi;
2235         u32     rx_stat_grerb_lo; /* grerrbyt */
2236         u32     rx_stat_grerb_hi; /* grerrbyt */
2237         u32     rx_stat_grfre_lo; /* grfrerr */
2238         u32     rx_stat_grfre_hi; /* grfrerr */
2239         u32     rx_stat_gripj_lo;
2240         u32     rx_stat_gripj_hi;
2241 };
2242
2243 struct mstat_stats {
2244         struct {
2245                 /* OTE MSTAT on E3 has a bug where this register's contents are
2246                  * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2247                  */
2248                 u32 tx_gtxpok_lo;
2249                 u32 tx_gtxpok_hi;
2250                 u32 tx_gtxpf_lo;
2251                 u32 tx_gtxpf_hi;
2252                 u32 tx_gtxpp_lo;
2253                 u32 tx_gtxpp_hi;
2254                 u32 tx_gtfcs_lo;
2255                 u32 tx_gtfcs_hi;
2256                 u32 tx_gtuca_lo;
2257                 u32 tx_gtuca_hi;
2258                 u32 tx_gtmca_lo;
2259                 u32 tx_gtmca_hi;
2260                 u32 tx_gtgca_lo;
2261                 u32 tx_gtgca_hi;
2262                 u32 tx_gtpkt_lo;
2263                 u32 tx_gtpkt_hi;
2264                 u32 tx_gt64_lo;
2265                 u32 tx_gt64_hi;
2266                 u32 tx_gt127_lo;
2267                 u32 tx_gt127_hi;
2268                 u32 tx_gt255_lo;
2269                 u32 tx_gt255_hi;
2270                 u32 tx_gt511_lo;
2271                 u32 tx_gt511_hi;
2272                 u32 tx_gt1023_lo;
2273                 u32 tx_gt1023_hi;
2274                 u32 tx_gt1518_lo;
2275                 u32 tx_gt1518_hi;
2276                 u32 tx_gt2047_lo;
2277                 u32 tx_gt2047_hi;
2278                 u32 tx_gt4095_lo;
2279                 u32 tx_gt4095_hi;
2280                 u32 tx_gt9216_lo;
2281                 u32 tx_gt9216_hi;
2282                 u32 tx_gt16383_lo;
2283                 u32 tx_gt16383_hi;
2284                 u32 tx_gtufl_lo;
2285                 u32 tx_gtufl_hi;
2286                 u32 tx_gterr_lo;
2287                 u32 tx_gterr_hi;
2288                 u32 tx_gtbyt_lo;
2289                 u32 tx_gtbyt_hi;
2290                 u32 tx_collisions_lo;
2291                 u32 tx_collisions_hi;
2292                 u32 tx_singlecollision_lo;
2293                 u32 tx_singlecollision_hi;
2294                 u32 tx_multiplecollisions_lo;
2295                 u32 tx_multiplecollisions_hi;
2296                 u32 tx_deferred_lo;
2297                 u32 tx_deferred_hi;
2298                 u32 tx_excessivecollisions_lo;
2299                 u32 tx_excessivecollisions_hi;
2300                 u32 tx_latecollisions_lo;
2301                 u32 tx_latecollisions_hi;
2302         } stats_tx;
2303
2304         struct {
2305                 u32 rx_gr64_lo;
2306                 u32 rx_gr64_hi;
2307                 u32 rx_gr127_lo;
2308                 u32 rx_gr127_hi;
2309                 u32 rx_gr255_lo;
2310                 u32 rx_gr255_hi;
2311                 u32 rx_gr511_lo;
2312                 u32 rx_gr511_hi;
2313                 u32 rx_gr1023_lo;
2314                 u32 rx_gr1023_hi;
2315                 u32 rx_gr1518_lo;
2316                 u32 rx_gr1518_hi;
2317                 u32 rx_gr2047_lo;
2318                 u32 rx_gr2047_hi;
2319                 u32 rx_gr4095_lo;
2320                 u32 rx_gr4095_hi;
2321                 u32 rx_gr9216_lo;
2322                 u32 rx_gr9216_hi;
2323                 u32 rx_gr16383_lo;
2324                 u32 rx_gr16383_hi;
2325                 u32 rx_grpkt_lo;
2326                 u32 rx_grpkt_hi;
2327                 u32 rx_grfcs_lo;
2328                 u32 rx_grfcs_hi;
2329                 u32 rx_gruca_lo;
2330                 u32 rx_gruca_hi;
2331                 u32 rx_grmca_lo;
2332                 u32 rx_grmca_hi;
2333                 u32 rx_grbca_lo;
2334                 u32 rx_grbca_hi;
2335                 u32 rx_grxpf_lo;
2336                 u32 rx_grxpf_hi;
2337                 u32 rx_grxpp_lo;
2338                 u32 rx_grxpp_hi;
2339                 u32 rx_grxuo_lo;
2340                 u32 rx_grxuo_hi;
2341                 u32 rx_grovr_lo;
2342                 u32 rx_grovr_hi;
2343                 u32 rx_grxcf_lo;
2344                 u32 rx_grxcf_hi;
2345                 u32 rx_grflr_lo;
2346                 u32 rx_grflr_hi;
2347                 u32 rx_grpok_lo;
2348                 u32 rx_grpok_hi;
2349                 u32 rx_grbyt_lo;
2350                 u32 rx_grbyt_hi;
2351                 u32 rx_grund_lo;
2352                 u32 rx_grund_hi;
2353                 u32 rx_grfrg_lo;
2354                 u32 rx_grfrg_hi;
2355                 u32 rx_grerb_lo;
2356                 u32 rx_grerb_hi;
2357                 u32 rx_grfre_lo;
2358                 u32 rx_grfre_hi;
2359
2360                 u32 rx_alignmenterrors_lo;
2361                 u32 rx_alignmenterrors_hi;
2362                 u32 rx_falsecarrier_lo;
2363                 u32 rx_falsecarrier_hi;
2364                 u32 rx_llfcmsgcnt_lo;
2365                 u32 rx_llfcmsgcnt_hi;
2366         } stats_rx;
2367 };
2368
2369 union mac_stats {
2370         struct emac_stats       emac_stats;
2371         struct bmac1_stats      bmac1_stats;
2372         struct bmac2_stats      bmac2_stats;
2373         struct mstat_stats      mstat_stats;
2374 };
2375
2376
2377 struct mac_stx {
2378         /* in_bad_octets */
2379         u32     rx_stat_ifhcinbadoctets_hi;
2380         u32     rx_stat_ifhcinbadoctets_lo;
2381
2382         /* out_bad_octets */
2383         u32     tx_stat_ifhcoutbadoctets_hi;
2384         u32     tx_stat_ifhcoutbadoctets_lo;
2385
2386         /* crc_receive_errors */
2387         u32     rx_stat_dot3statsfcserrors_hi;
2388         u32     rx_stat_dot3statsfcserrors_lo;
2389         /* alignment_errors */
2390         u32     rx_stat_dot3statsalignmenterrors_hi;
2391         u32     rx_stat_dot3statsalignmenterrors_lo;
2392         /* carrier_sense_errors */
2393         u32     rx_stat_dot3statscarriersenseerrors_hi;
2394         u32     rx_stat_dot3statscarriersenseerrors_lo;
2395         /* false_carrier_detections */
2396         u32     rx_stat_falsecarriererrors_hi;
2397         u32     rx_stat_falsecarriererrors_lo;
2398
2399         /* runt_packets_received */
2400         u32     rx_stat_etherstatsundersizepkts_hi;
2401         u32     rx_stat_etherstatsundersizepkts_lo;
2402         /* jabber_packets_received */
2403         u32     rx_stat_dot3statsframestoolong_hi;
2404         u32     rx_stat_dot3statsframestoolong_lo;
2405
2406         /* error_runt_packets_received */
2407         u32     rx_stat_etherstatsfragments_hi;
2408         u32     rx_stat_etherstatsfragments_lo;
2409         /* error_jabber_packets_received */
2410         u32     rx_stat_etherstatsjabbers_hi;
2411         u32     rx_stat_etherstatsjabbers_lo;
2412
2413         /* control_frames_received */
2414         u32     rx_stat_maccontrolframesreceived_hi;
2415         u32     rx_stat_maccontrolframesreceived_lo;
2416         u32     rx_stat_mac_xpf_hi;
2417         u32     rx_stat_mac_xpf_lo;
2418         u32     rx_stat_mac_xcf_hi;
2419         u32     rx_stat_mac_xcf_lo;
2420
2421         /* xoff_state_entered */
2422         u32     rx_stat_xoffstateentered_hi;
2423         u32     rx_stat_xoffstateentered_lo;
2424         /* pause_xon_frames_received */
2425         u32     rx_stat_xonpauseframesreceived_hi;
2426         u32     rx_stat_xonpauseframesreceived_lo;
2427         /* pause_xoff_frames_received */
2428         u32     rx_stat_xoffpauseframesreceived_hi;
2429         u32     rx_stat_xoffpauseframesreceived_lo;
2430         /* pause_xon_frames_transmitted */
2431         u32     tx_stat_outxonsent_hi;
2432         u32     tx_stat_outxonsent_lo;
2433         /* pause_xoff_frames_transmitted */
2434         u32     tx_stat_outxoffsent_hi;
2435         u32     tx_stat_outxoffsent_lo;
2436         /* flow_control_done */
2437         u32     tx_stat_flowcontroldone_hi;
2438         u32     tx_stat_flowcontroldone_lo;
2439
2440         /* ether_stats_collisions */
2441         u32     tx_stat_etherstatscollisions_hi;
2442         u32     tx_stat_etherstatscollisions_lo;
2443         /* single_collision_transmit_frames */
2444         u32     tx_stat_dot3statssinglecollisionframes_hi;
2445         u32     tx_stat_dot3statssinglecollisionframes_lo;
2446         /* multiple_collision_transmit_frames */
2447         u32     tx_stat_dot3statsmultiplecollisionframes_hi;
2448         u32     tx_stat_dot3statsmultiplecollisionframes_lo;
2449         /* deferred_transmissions */
2450         u32     tx_stat_dot3statsdeferredtransmissions_hi;
2451         u32     tx_stat_dot3statsdeferredtransmissions_lo;
2452         /* excessive_collision_frames */
2453         u32     tx_stat_dot3statsexcessivecollisions_hi;
2454         u32     tx_stat_dot3statsexcessivecollisions_lo;
2455         /* late_collision_frames */
2456         u32     tx_stat_dot3statslatecollisions_hi;
2457         u32     tx_stat_dot3statslatecollisions_lo;
2458
2459         /* frames_transmitted_64_bytes */
2460         u32     tx_stat_etherstatspkts64octets_hi;
2461         u32     tx_stat_etherstatspkts64octets_lo;
2462         /* frames_transmitted_65_127_bytes */
2463         u32     tx_stat_etherstatspkts65octetsto127octets_hi;
2464         u32     tx_stat_etherstatspkts65octetsto127octets_lo;
2465         /* frames_transmitted_128_255_bytes */
2466         u32     tx_stat_etherstatspkts128octetsto255octets_hi;
2467         u32     tx_stat_etherstatspkts128octetsto255octets_lo;
2468         /* frames_transmitted_256_511_bytes */
2469         u32     tx_stat_etherstatspkts256octetsto511octets_hi;
2470         u32     tx_stat_etherstatspkts256octetsto511octets_lo;
2471         /* frames_transmitted_512_1023_bytes */
2472         u32     tx_stat_etherstatspkts512octetsto1023octets_hi;
2473         u32     tx_stat_etherstatspkts512octetsto1023octets_lo;
2474         /* frames_transmitted_1024_1522_bytes */
2475         u32     tx_stat_etherstatspkts1024octetsto1522octets_hi;
2476         u32     tx_stat_etherstatspkts1024octetsto1522octets_lo;
2477         /* frames_transmitted_1523_9022_bytes */
2478         u32     tx_stat_etherstatspktsover1522octets_hi;
2479         u32     tx_stat_etherstatspktsover1522octets_lo;
2480         u32     tx_stat_mac_2047_hi;
2481         u32     tx_stat_mac_2047_lo;
2482         u32     tx_stat_mac_4095_hi;
2483         u32     tx_stat_mac_4095_lo;
2484         u32     tx_stat_mac_9216_hi;
2485         u32     tx_stat_mac_9216_lo;
2486         u32     tx_stat_mac_16383_hi;
2487         u32     tx_stat_mac_16383_lo;
2488
2489         /* internal_mac_transmit_errors */
2490         u32     tx_stat_dot3statsinternalmactransmiterrors_hi;
2491         u32     tx_stat_dot3statsinternalmactransmiterrors_lo;
2492
2493         /* if_out_discards */
2494         u32     tx_stat_mac_ufl_hi;
2495         u32     tx_stat_mac_ufl_lo;
2496 };
2497
2498
2499 #define MAC_STX_IDX_MAX                     2
2500
2501 struct host_port_stats {
2502         u32            host_port_stats_start;
2503
2504         struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2505
2506         u32            brb_drop_hi;
2507         u32            brb_drop_lo;
2508
2509         u32            host_port_stats_end;
2510 };
2511
2512
2513 struct host_func_stats {
2514         u32     host_func_stats_start;
2515
2516         u32     total_bytes_received_hi;
2517         u32     total_bytes_received_lo;
2518
2519         u32     total_bytes_transmitted_hi;
2520         u32     total_bytes_transmitted_lo;
2521
2522         u32     total_unicast_packets_received_hi;
2523         u32     total_unicast_packets_received_lo;
2524
2525         u32     total_multicast_packets_received_hi;
2526         u32     total_multicast_packets_received_lo;
2527
2528         u32     total_broadcast_packets_received_hi;
2529         u32     total_broadcast_packets_received_lo;
2530
2531         u32     total_unicast_packets_transmitted_hi;
2532         u32     total_unicast_packets_transmitted_lo;
2533
2534         u32     total_multicast_packets_transmitted_hi;
2535         u32     total_multicast_packets_transmitted_lo;
2536
2537         u32     total_broadcast_packets_transmitted_hi;
2538         u32     total_broadcast_packets_transmitted_lo;
2539
2540         u32     valid_bytes_received_hi;
2541         u32     valid_bytes_received_lo;
2542
2543         u32     host_func_stats_end;
2544 };
2545
2546 /* VIC definitions */
2547 #define VICSTATST_UIF_INDEX 2
2548
2549 #define BCM_5710_FW_MAJOR_VERSION                       7
2550 #define BCM_5710_FW_MINOR_VERSION                       0
2551 #define BCM_5710_FW_REVISION_VERSION            23
2552 #define BCM_5710_FW_ENGINEERING_VERSION         0
2553 #define BCM_5710_FW_COMPILE_FLAGS                       1
2554
2555
2556 /*
2557  * attention bits
2558  */
2559 struct atten_sp_status_block {
2560         __le32 attn_bits;
2561         __le32 attn_bits_ack;
2562         u8 status_block_id;
2563         u8 reserved0;
2564         __le16 attn_bits_index;
2565         __le32 reserved1;
2566 };
2567
2568
2569 /*
2570  * The eth aggregative context of Cstorm
2571  */
2572 struct cstorm_eth_ag_context {
2573         u32 __reserved0[10];
2574 };
2575
2576
2577 /*
2578  * dmae command structure
2579  */
2580 struct dmae_command {
2581         u32 opcode;
2582 #define DMAE_COMMAND_SRC (0x1<<0)
2583 #define DMAE_COMMAND_SRC_SHIFT 0
2584 #define DMAE_COMMAND_DST (0x3<<1)
2585 #define DMAE_COMMAND_DST_SHIFT 1
2586 #define DMAE_COMMAND_C_DST (0x1<<3)
2587 #define DMAE_COMMAND_C_DST_SHIFT 3
2588 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2589 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2590 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2591 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2592 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2593 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2594 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2595 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2596 #define DMAE_COMMAND_PORT (0x1<<11)
2597 #define DMAE_COMMAND_PORT_SHIFT 11
2598 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2599 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2600 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2601 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2602 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2603 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2604 #define DMAE_COMMAND_E1HVN (0x3<<15)
2605 #define DMAE_COMMAND_E1HVN_SHIFT 15
2606 #define DMAE_COMMAND_DST_VN (0x3<<17)
2607 #define DMAE_COMMAND_DST_VN_SHIFT 17
2608 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2609 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2610 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2611 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2612 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2613 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2614         u32 src_addr_lo;
2615         u32 src_addr_hi;
2616         u32 dst_addr_lo;
2617         u32 dst_addr_hi;
2618 #if defined(__BIG_ENDIAN)
2619         u16 opcode_iov;
2620 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2621 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2622 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2623 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2624 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2625 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2626 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2627 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2628 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2629 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2630 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2631 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2632         u16 len;
2633 #elif defined(__LITTLE_ENDIAN)
2634         u16 len;
2635         u16 opcode_iov;
2636 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2637 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2638 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2639 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2640 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2641 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2642 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2643 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2644 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2645 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2646 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2647 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2648 #endif
2649         u32 comp_addr_lo;
2650         u32 comp_addr_hi;
2651         u32 comp_val;
2652         u32 crc32;
2653         u32 crc32_c;
2654 #if defined(__BIG_ENDIAN)
2655         u16 crc16_c;
2656         u16 crc16;
2657 #elif defined(__LITTLE_ENDIAN)
2658         u16 crc16;
2659         u16 crc16_c;
2660 #endif
2661 #if defined(__BIG_ENDIAN)
2662         u16 reserved3;
2663         u16 crc_t10;
2664 #elif defined(__LITTLE_ENDIAN)
2665         u16 crc_t10;
2666         u16 reserved3;
2667 #endif
2668 #if defined(__BIG_ENDIAN)
2669         u16 xsum8;
2670         u16 xsum16;
2671 #elif defined(__LITTLE_ENDIAN)
2672         u16 xsum16;
2673         u16 xsum8;
2674 #endif
2675 };
2676
2677
2678 /*
2679  * common data for all protocols
2680  */
2681 struct doorbell_hdr {
2682         u8 header;
2683 #define DOORBELL_HDR_RX (0x1<<0)
2684 #define DOORBELL_HDR_RX_SHIFT 0
2685 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
2686 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
2687 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
2688 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
2689 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
2690 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
2691 };
2692
2693 /*
2694  * Ethernet doorbell
2695  */
2696 struct eth_tx_doorbell {
2697 #if defined(__BIG_ENDIAN)
2698         u16 npackets;
2699         u8 params;
2700 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2701 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2702 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2703 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2704 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2705 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2706         struct doorbell_hdr hdr;
2707 #elif defined(__LITTLE_ENDIAN)
2708         struct doorbell_hdr hdr;
2709         u8 params;
2710 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2711 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2712 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2713 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2714 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2715 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2716         u16 npackets;
2717 #endif
2718 };
2719
2720
2721 /*
2722  * 3 lines. status block
2723  */
2724 struct hc_status_block_e1x {
2725         __le16 index_values[HC_SB_MAX_INDICES_E1X];
2726         __le16 running_index[HC_SB_MAX_SM];
2727         __le32 rsrv[11];
2728 };
2729
2730 /*
2731  * host status block
2732  */
2733 struct host_hc_status_block_e1x {
2734         struct hc_status_block_e1x sb;
2735 };
2736
2737
2738 /*
2739  * 3 lines. status block
2740  */
2741 struct hc_status_block_e2 {
2742         __le16 index_values[HC_SB_MAX_INDICES_E2];
2743         __le16 running_index[HC_SB_MAX_SM];
2744         __le32 reserved[11];
2745 };
2746
2747 /*
2748  * host status block
2749  */
2750 struct host_hc_status_block_e2 {
2751         struct hc_status_block_e2 sb;
2752 };
2753
2754
2755 /*
2756  * 5 lines. slow-path status block
2757  */
2758 struct hc_sp_status_block {
2759         __le16 index_values[HC_SP_SB_MAX_INDICES];
2760         __le16 running_index;
2761         __le16 rsrv;
2762         u32 rsrv1;
2763 };
2764
2765 /*
2766  * host status block
2767  */
2768 struct host_sp_status_block {
2769         struct atten_sp_status_block atten_status_block;
2770         struct hc_sp_status_block sp_sb;
2771 };
2772
2773
2774 /*
2775  * IGU driver acknowledgment register
2776  */
2777 struct igu_ack_register {
2778 #if defined(__BIG_ENDIAN)
2779         u16 sb_id_and_flags;
2780 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2781 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2782 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2783 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2784 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2785 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2786 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2787 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2788 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2789 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2790         u16 status_block_index;
2791 #elif defined(__LITTLE_ENDIAN)
2792         u16 status_block_index;
2793         u16 sb_id_and_flags;
2794 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2795 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2796 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2797 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2798 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2799 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2800 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2801 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2802 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2803 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2804 #endif
2805 };
2806
2807
2808 /*
2809  * IGU driver acknowledgement register
2810  */
2811 struct igu_backward_compatible {
2812         u32 sb_id_and_flags;
2813 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
2814 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
2815 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
2816 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
2817 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
2818 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
2819 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
2820 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
2821 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
2822 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
2823 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
2824 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
2825         u32 reserved_2;
2826 };
2827
2828
2829 /*
2830  * IGU driver acknowledgement register
2831  */
2832 struct igu_regular {
2833         u32 sb_id_and_flags;
2834 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
2835 #define IGU_REGULAR_SB_INDEX_SHIFT 0
2836 #define IGU_REGULAR_RESERVED0 (0x1<<20)
2837 #define IGU_REGULAR_RESERVED0_SHIFT 20
2838 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
2839 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
2840 #define IGU_REGULAR_BUPDATE (0x1<<24)
2841 #define IGU_REGULAR_BUPDATE_SHIFT 24
2842 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
2843 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
2844 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
2845 #define IGU_REGULAR_RESERVED_1_SHIFT 27
2846 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
2847 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
2848 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
2849 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
2850 #define IGU_REGULAR_BCLEANUP (0x1<<31)
2851 #define IGU_REGULAR_BCLEANUP_SHIFT 31
2852         u32 reserved_2;
2853 };
2854
2855 /*
2856  * IGU driver acknowledgement register
2857  */
2858 union igu_consprod_reg {
2859         struct igu_regular regular;
2860         struct igu_backward_compatible backward_compatible;
2861 };
2862
2863
2864 /*
2865  * Igu control commands
2866  */
2867 enum igu_ctrl_cmd {
2868         IGU_CTRL_CMD_TYPE_RD,
2869         IGU_CTRL_CMD_TYPE_WR,
2870         MAX_IGU_CTRL_CMD
2871 };
2872
2873
2874 /*
2875  * Control register for the IGU command register
2876  */
2877 struct igu_ctrl_reg {
2878         u32 ctrl_data;
2879 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
2880 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
2881 #define IGU_CTRL_REG_FID (0x7F<<12)
2882 #define IGU_CTRL_REG_FID_SHIFT 12
2883 #define IGU_CTRL_REG_RESERVED (0x1<<19)
2884 #define IGU_CTRL_REG_RESERVED_SHIFT 19
2885 #define IGU_CTRL_REG_TYPE (0x1<<20)
2886 #define IGU_CTRL_REG_TYPE_SHIFT 20
2887 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
2888 #define IGU_CTRL_REG_UNUSED_SHIFT 21
2889 };
2890
2891
2892 /*
2893  * Igu interrupt command
2894  */
2895 enum igu_int_cmd {
2896         IGU_INT_ENABLE,
2897         IGU_INT_DISABLE,
2898         IGU_INT_NOP,
2899         IGU_INT_NOP2,
2900         MAX_IGU_INT_CMD
2901 };
2902
2903
2904 /*
2905  * Igu segments
2906  */
2907 enum igu_seg_access {
2908         IGU_SEG_ACCESS_NORM,
2909         IGU_SEG_ACCESS_DEF,
2910         IGU_SEG_ACCESS_ATTN,
2911         MAX_IGU_SEG_ACCESS
2912 };
2913
2914
2915 /*
2916  * Parser parsing flags field
2917  */
2918 struct parsing_flags {
2919         __le16 flags;
2920 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
2921 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
2922 #define PARSING_FLAGS_VLAN (0x1<<1)
2923 #define PARSING_FLAGS_VLAN_SHIFT 1
2924 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
2925 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
2926 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
2927 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
2928 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
2929 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
2930 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
2931 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
2932 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
2933 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
2934 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
2935 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
2936 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
2937 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
2938 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
2939 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
2940 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
2941 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
2942 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
2943 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
2944 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
2945 #define PARSING_FLAGS_RESERVED0_SHIFT 14
2946 };
2947
2948
2949 /*
2950  * Parsing flags for TCP ACK type
2951  */
2952 enum prs_flags_ack_type {
2953         PRS_FLAG_PUREACK_PIGGY,
2954         PRS_FLAG_PUREACK_PURE,
2955         MAX_PRS_FLAGS_ACK_TYPE
2956 };
2957
2958
2959 /*
2960  * Parsing flags for Ethernet address type
2961  */
2962 enum prs_flags_eth_addr_type {
2963         PRS_FLAG_ETHTYPE_NON_UNICAST,
2964         PRS_FLAG_ETHTYPE_UNICAST,
2965         MAX_PRS_FLAGS_ETH_ADDR_TYPE
2966 };
2967
2968
2969 /*
2970  * Parsing flags for over-ethernet protocol
2971  */
2972 enum prs_flags_over_eth {
2973         PRS_FLAG_OVERETH_UNKNOWN,
2974         PRS_FLAG_OVERETH_IPV4,
2975         PRS_FLAG_OVERETH_IPV6,
2976         PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
2977         MAX_PRS_FLAGS_OVER_ETH
2978 };
2979
2980
2981 /*
2982  * Parsing flags for over-IP protocol
2983  */
2984 enum prs_flags_over_ip {
2985         PRS_FLAG_OVERIP_UNKNOWN,
2986         PRS_FLAG_OVERIP_TCP,
2987         PRS_FLAG_OVERIP_UDP,
2988         MAX_PRS_FLAGS_OVER_IP
2989 };
2990
2991
2992 /*
2993  * SDM operation gen command (generate aggregative interrupt)
2994  */
2995 struct sdm_op_gen {
2996         __le32 command;
2997 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
2998 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
2999 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3000 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3001 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3002 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3003 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3004 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3005 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3006 #define SDM_OP_GEN_RESERVED_SHIFT 17
3007 };
3008
3009
3010 /*
3011  * Timers connection context
3012  */
3013 struct timers_block_context {
3014         u32 __reserved_0;
3015         u32 __reserved_1;
3016         u32 __reserved_2;
3017         u32 flags;
3018 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3019 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3020 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3021 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3022 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3023 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3024 };
3025
3026
3027 /*
3028  * The eth aggregative context of Tstorm
3029  */
3030 struct tstorm_eth_ag_context {
3031         u32 __reserved0[14];
3032 };
3033
3034
3035 /*
3036  * The eth aggregative context of Ustorm
3037  */
3038 struct ustorm_eth_ag_context {
3039         u32 __reserved0;
3040 #if defined(__BIG_ENDIAN)
3041         u8 cdu_usage;
3042         u8 __reserved2;
3043         u16 __reserved1;
3044 #elif defined(__LITTLE_ENDIAN)
3045         u16 __reserved1;
3046         u8 __reserved2;
3047         u8 cdu_usage;
3048 #endif
3049         u32 __reserved3[6];
3050 };
3051
3052
3053 /*
3054  * The eth aggregative context of Xstorm
3055  */
3056 struct xstorm_eth_ag_context {
3057         u32 reserved0;
3058 #if defined(__BIG_ENDIAN)
3059         u8 cdu_reserved;
3060         u8 reserved2;
3061         u16 reserved1;
3062 #elif defined(__LITTLE_ENDIAN)
3063         u16 reserved1;
3064         u8 reserved2;
3065         u8 cdu_reserved;
3066 #endif
3067         u32 reserved3[30];
3068 };
3069
3070
3071 /*
3072  * doorbell message sent to the chip
3073  */
3074 struct doorbell {
3075 #if defined(__BIG_ENDIAN)
3076         u16 zero_fill2;
3077         u8 zero_fill1;
3078         struct doorbell_hdr header;
3079 #elif defined(__LITTLE_ENDIAN)
3080         struct doorbell_hdr header;
3081         u8 zero_fill1;
3082         u16 zero_fill2;
3083 #endif
3084 };
3085
3086
3087 /*
3088  * doorbell message sent to the chip
3089  */
3090 struct doorbell_set_prod {
3091 #if defined(__BIG_ENDIAN)
3092         u16 prod;
3093         u8 zero_fill1;
3094         struct doorbell_hdr header;
3095 #elif defined(__LITTLE_ENDIAN)
3096         struct doorbell_hdr header;
3097         u8 zero_fill1;
3098         u16 prod;
3099 #endif
3100 };
3101
3102
3103 struct regpair {
3104         __le32 lo;
3105         __le32 hi;
3106 };
3107
3108
3109 /*
3110  * Classify rule opcodes in E2/E3
3111  */
3112 enum classify_rule {
3113         CLASSIFY_RULE_OPCODE_MAC,
3114         CLASSIFY_RULE_OPCODE_VLAN,
3115         CLASSIFY_RULE_OPCODE_PAIR,
3116         MAX_CLASSIFY_RULE
3117 };
3118
3119
3120 /*
3121  * Classify rule types in E2/E3
3122  */
3123 enum classify_rule_action_type {
3124         CLASSIFY_RULE_REMOVE,
3125         CLASSIFY_RULE_ADD,
3126         MAX_CLASSIFY_RULE_ACTION_TYPE
3127 };
3128
3129
3130 /*
3131  * client init ramrod data
3132  */
3133 struct client_init_general_data {
3134         u8 client_id;
3135         u8 statistics_counter_id;
3136         u8 statistics_en_flg;
3137         u8 is_fcoe_flg;
3138         u8 activate_flg;
3139         u8 sp_client_id;
3140         __le16 mtu;
3141         u8 statistics_zero_flg;
3142         u8 func_id;
3143         u8 cos;
3144         u8 traffic_type;
3145         u32 reserved0;
3146 };
3147
3148
3149 /*
3150  * client init rx data
3151  */
3152 struct client_init_rx_data {
3153         u8 tpa_en;
3154 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3155 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3156 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3157 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3158 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x3F<<2)
3159 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 2
3160         u8 vmqueue_mode_en_flg;
3161         u8 extra_data_over_sgl_en_flg;
3162         u8 cache_line_alignment_log_size;
3163         u8 enable_dynamic_hc;
3164         u8 max_sges_for_packet;
3165         u8 client_qzone_id;
3166         u8 drop_ip_cs_err_flg;
3167         u8 drop_tcp_cs_err_flg;
3168         u8 drop_ttl0_flg;
3169         u8 drop_udp_cs_err_flg;
3170         u8 inner_vlan_removal_enable_flg;
3171         u8 outer_vlan_removal_enable_flg;
3172         u8 status_block_id;
3173         u8 rx_sb_index_number;
3174         u8 reserved0;
3175         u8 max_tpa_queues;
3176         u8 silent_vlan_removal_flg;
3177         __le16 max_bytes_on_bd;
3178         __le16 sge_buff_size;
3179         u8 approx_mcast_engine_id;
3180         u8 rss_engine_id;
3181         struct regpair bd_page_base;
3182         struct regpair sge_page_base;
3183         struct regpair cqe_page_base;
3184         u8 is_leading_rss;
3185         u8 is_approx_mcast;
3186         __le16 max_agg_size;
3187         __le16 state;
3188 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3189 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3190 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3191 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3192 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3193 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3194 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3195 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3196 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3197 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3198 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3199 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3200 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3201 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3202 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3203 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3204         __le16 cqe_pause_thr_low;
3205         __le16 cqe_pause_thr_high;
3206         __le16 bd_pause_thr_low;
3207         __le16 bd_pause_thr_high;
3208         __le16 sge_pause_thr_low;
3209         __le16 sge_pause_thr_high;
3210         __le16 rx_cos_mask;
3211         __le16 silent_vlan_value;
3212         __le16 silent_vlan_mask;
3213         __le32 reserved6[2];
3214 };
3215
3216 /*
3217  * client init tx data
3218  */
3219 struct client_init_tx_data {
3220         u8 enforce_security_flg;
3221         u8 tx_status_block_id;
3222         u8 tx_sb_index_number;
3223         u8 tss_leading_client_id;
3224         u8 tx_switching_flg;
3225         u8 anti_spoofing_flg;
3226         __le16 default_vlan;
3227         struct regpair tx_bd_page_base;
3228         __le16 state;
3229 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3230 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3231 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3232 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3233 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3234 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3235 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3236 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3237 #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)
3238 #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4
3239         u8 default_vlan_flg;
3240         u8 reserved2;
3241         __le32 reserved3;
3242 };
3243
3244 /*
3245  * client init ramrod data
3246  */
3247 struct client_init_ramrod_data {
3248         struct client_init_general_data general;
3249         struct client_init_rx_data rx;
3250         struct client_init_tx_data tx;
3251 };
3252
3253
3254 /*
3255  * client update ramrod data
3256  */
3257 struct client_update_ramrod_data {
3258         u8 client_id;
3259         u8 func_id;
3260         u8 inner_vlan_removal_enable_flg;
3261         u8 inner_vlan_removal_change_flg;
3262         u8 outer_vlan_removal_enable_flg;
3263         u8 outer_vlan_removal_change_flg;
3264         u8 anti_spoofing_enable_flg;
3265         u8 anti_spoofing_change_flg;
3266         u8 activate_flg;
3267         u8 activate_change_flg;
3268         __le16 default_vlan;
3269         u8 default_vlan_enable_flg;
3270         u8 default_vlan_change_flg;
3271         __le16 silent_vlan_value;
3272         __le16 silent_vlan_mask;
3273         u8 silent_vlan_removal_flg;
3274         u8 silent_vlan_change_flg;
3275         __le32 echo;
3276 };
3277
3278
3279 /*
3280  * The eth storm context of Cstorm
3281  */
3282 struct cstorm_eth_st_context {
3283         u32 __reserved0[4];
3284 };
3285
3286
3287 struct double_regpair {
3288         u32 regpair0_lo;
3289         u32 regpair0_hi;
3290         u32 regpair1_lo;
3291         u32 regpair1_hi;
3292 };
3293
3294
3295 /*
3296  * Ethernet address typesm used in ethernet tx BDs
3297  */
3298 enum eth_addr_type {
3299         UNKNOWN_ADDRESS,
3300         UNICAST_ADDRESS,
3301         MULTICAST_ADDRESS,
3302         BROADCAST_ADDRESS,
3303         MAX_ETH_ADDR_TYPE
3304 };
3305
3306
3307 /*
3308  *
3309  */
3310 struct eth_classify_cmd_header {
3311         u8 cmd_general_data;
3312 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3313 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3314 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3315 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3316 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3317 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3318 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3319 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3320 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3321 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3322         u8 func_id;
3323         u8 client_id;
3324         u8 reserved1;
3325 };
3326
3327
3328 /*
3329  * header for eth classification config ramrod
3330  */
3331 struct eth_classify_header {
3332         u8 rule_cnt;
3333         u8 reserved0;
3334         __le16 reserved1;
3335         __le32 echo;
3336 };
3337
3338
3339 /*
3340  * Command for adding/removing a MAC classification rule
3341  */
3342 struct eth_classify_mac_cmd {
3343         struct eth_classify_cmd_header header;
3344         __le32 reserved0;
3345         __le16 mac_lsb;
3346         __le16 mac_mid;
3347         __le16 mac_msb;
3348         __le16 reserved1;
3349 };
3350
3351
3352 /*
3353  * Command for adding/removing a MAC-VLAN pair classification rule
3354  */
3355 struct eth_classify_pair_cmd {
3356         struct eth_classify_cmd_header header;
3357         __le32 reserved0;
3358         __le16 mac_lsb;
3359         __le16 mac_mid;
3360         __le16 mac_msb;
3361         __le16 vlan;
3362 };
3363
3364
3365 /*
3366  * Command for adding/removing a VLAN classification rule
3367  */
3368 struct eth_classify_vlan_cmd {
3369         struct eth_classify_cmd_header header;
3370         __le32 reserved0;
3371         __le32 reserved1;
3372         __le16 reserved2;
3373         __le16 vlan;
3374 };
3375
3376 /*
3377  * union for eth classification rule
3378  */
3379 union eth_classify_rule_cmd {
3380         struct eth_classify_mac_cmd mac;
3381         struct eth_classify_vlan_cmd vlan;
3382         struct eth_classify_pair_cmd pair;
3383 };
3384
3385 /*
3386  * parameters for eth classification configuration ramrod
3387  */
3388 struct eth_classify_rules_ramrod_data {
3389         struct eth_classify_header header;
3390         union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3391 };
3392
3393
3394 /*
3395  * The data contain client ID need to the ramrod
3396  */
3397 struct eth_common_ramrod_data {
3398         __le32 client_id;
3399         __le32 reserved1;
3400 };
3401
3402
3403 /*
3404  * The eth storm context of Ustorm
3405  */
3406 struct ustorm_eth_st_context {
3407         u32 reserved0[52];
3408 };
3409
3410 /*
3411  * The eth storm context of Tstorm
3412  */
3413 struct tstorm_eth_st_context {
3414         u32 __reserved0[28];
3415 };
3416
3417 /*
3418  * The eth storm context of Xstorm
3419  */
3420 struct xstorm_eth_st_context {
3421         u32 reserved0[60];
3422 };
3423
3424 /*
3425  * Ethernet connection context
3426  */
3427 struct eth_context {
3428         struct ustorm_eth_st_context ustorm_st_context;
3429         struct tstorm_eth_st_context tstorm_st_context;
3430         struct xstorm_eth_ag_context xstorm_ag_context;
3431         struct tstorm_eth_ag_context tstorm_ag_context;
3432         struct cstorm_eth_ag_context cstorm_ag_context;
3433         struct ustorm_eth_ag_context ustorm_ag_context;
3434         struct timers_block_context timers_context;
3435         struct xstorm_eth_st_context xstorm_st_context;
3436         struct cstorm_eth_st_context cstorm_st_context;
3437 };
3438
3439
3440 /*
3441  * union for sgl and raw data.
3442  */
3443 union eth_sgl_or_raw_data {
3444         __le16 sgl[8];
3445         u32 raw_data[4];
3446 };
3447
3448 /*
3449  * eth FP end aggregation CQE parameters struct
3450  */
3451 struct eth_end_agg_rx_cqe {
3452         u8 type_error_flags;
3453 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3454 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3455 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3456 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3457 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3458 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3459         u8 reserved1;
3460         u8 queue_index;
3461         u8 reserved2;
3462         __le32 timestamp_delta;
3463         __le16 num_of_coalesced_segs;
3464         __le16 pkt_len;
3465         u8 pure_ack_count;
3466         u8 reserved3;
3467         __le16 reserved4;
3468         union eth_sgl_or_raw_data sgl_or_raw_data;
3469         __le32 reserved5[8];
3470 };
3471
3472
3473 /*
3474  * regular eth FP CQE parameters struct
3475  */
3476 struct eth_fast_path_rx_cqe {
3477         u8 type_error_flags;
3478 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3479 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3480 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3481 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3482 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3483 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3484 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3485 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3486 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3487 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3488 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3489 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3490         u8 status_flags;
3491 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3492 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3493 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3494 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3495 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3496 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3497 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3498 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3499 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3500 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3501 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3502 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3503         u8 queue_index;
3504         u8 placement_offset;
3505         __le32 rss_hash_result;
3506         __le16 vlan_tag;
3507         __le16 pkt_len;
3508         __le16 len_on_bd;
3509         struct parsing_flags pars_flags;
3510         union eth_sgl_or_raw_data sgl_or_raw_data;
3511         __le32 reserved1[8];
3512 };
3513
3514
3515 /*
3516  * Command for setting classification flags for a client
3517  */
3518 struct eth_filter_rules_cmd {
3519         u8 cmd_general_data;
3520 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3521 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3522 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3523 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3524 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3525 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3526         u8 func_id;
3527         u8 client_id;
3528         u8 reserved1;
3529         __le16 state;
3530 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3531 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3532 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3533 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3534 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3535 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3536 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3537 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3538 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3539 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3540 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3541 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3542 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3543 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3544 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3545 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3546         __le16 reserved3;
3547         struct regpair reserved4;
3548 };
3549
3550
3551 /*
3552  * parameters for eth classification filters ramrod
3553  */
3554 struct eth_filter_rules_ramrod_data {
3555         struct eth_classify_header header;
3556         struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3557 };
3558
3559
3560 /*
3561  * parameters for eth classification configuration ramrod
3562  */
3563 struct eth_general_rules_ramrod_data {
3564         struct eth_classify_header header;
3565         union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3566 };
3567
3568
3569 /*
3570  * The data for Halt ramrod
3571  */
3572 struct eth_halt_ramrod_data {
3573         __le32 client_id;
3574         __le32 reserved0;
3575 };
3576
3577
3578 /*
3579  * Command for setting multicast classification for a client
3580  */
3581 struct eth_multicast_rules_cmd {
3582         u8 cmd_general_data;
3583 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3584 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3585 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3586 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3587 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3588 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3589 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3590 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3591         u8 func_id;
3592         u8 bin_id;
3593         u8 engine_id;
3594         __le32 reserved2;
3595         struct regpair reserved3;
3596 };
3597
3598
3599 /*
3600  * parameters for multicast classification ramrod
3601  */
3602 struct eth_multicast_rules_ramrod_data {
3603         struct eth_classify_header header;
3604         struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
3605 };
3606
3607
3608 /*
3609  * Place holder for ramrods protocol specific data
3610  */
3611 struct ramrod_data {
3612         __le32 data_lo;
3613         __le32 data_hi;
3614 };
3615
3616 /*
3617  * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
3618  */
3619 union eth_ramrod_data {
3620         struct ramrod_data general;
3621 };
3622
3623
3624 /*
3625  * RSS toeplitz hash type, as reported in CQE
3626  */
3627 enum eth_rss_hash_type {
3628         DEFAULT_HASH_TYPE,
3629         IPV4_HASH_TYPE,
3630         TCP_IPV4_HASH_TYPE,
3631         IPV6_HASH_TYPE,
3632         TCP_IPV6_HASH_TYPE,
3633         VLAN_PRI_HASH_TYPE,
3634         E1HOV_PRI_HASH_TYPE,
3635         DSCP_HASH_TYPE,
3636         MAX_ETH_RSS_HASH_TYPE
3637 };
3638
3639
3640 /*
3641  * Ethernet RSS mode
3642  */
3643 enum eth_rss_mode {
3644         ETH_RSS_MODE_DISABLED,
3645         ETH_RSS_MODE_REGULAR,
3646         ETH_RSS_MODE_VLAN_PRI,
3647         ETH_RSS_MODE_E1HOV_PRI,
3648         ETH_RSS_MODE_IP_DSCP,
3649         MAX_ETH_RSS_MODE
3650 };
3651
3652
3653 /*
3654  * parameters for RSS update ramrod (E2)
3655  */
3656 struct eth_rss_update_ramrod_data {
3657         u8 rss_engine_id;
3658         u8 capabilities;
3659 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
3660 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
3661 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
3662 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
3663 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
3664 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
3665 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
3666 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
3667 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
3668 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
3669 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
3670 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
3671 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6)
3672 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6
3673 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7)
3674 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7
3675         u8 rss_result_mask;
3676         u8 rss_mode;
3677         __le32 __reserved2;
3678         u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
3679         __le32 rss_key[T_ETH_RSS_KEY];
3680         __le32 echo;
3681         __le32 reserved3;
3682 };
3683
3684
3685 /*
3686  * The eth Rx Buffer Descriptor
3687  */
3688 struct eth_rx_bd {
3689         __le32 addr_lo;
3690         __le32 addr_hi;
3691 };
3692
3693
3694 /*
3695  * Eth Rx Cqe structure- general structure for ramrods
3696  */
3697 struct common_ramrod_eth_rx_cqe {
3698         u8 ramrod_type;
3699 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
3700 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
3701 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
3702 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
3703 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
3704 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
3705         u8 conn_type;
3706         __le16 reserved1;
3707         __le32 conn_and_cmd_data;
3708 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
3709 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
3710 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
3711 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
3712         struct ramrod_data protocol_data;
3713         __le32 echo;
3714         __le32 reserved2[11];
3715 };
3716
3717 /*
3718  * Rx Last CQE in page (in ETH)
3719  */
3720 struct eth_rx_cqe_next_page {
3721         __le32 addr_lo;
3722         __le32 addr_hi;
3723         __le32 reserved[14];
3724 };
3725
3726 /*
3727  * union for all eth rx cqe types (fix their sizes)
3728  */
3729 union eth_rx_cqe {
3730         struct eth_fast_path_rx_cqe fast_path_cqe;
3731         struct common_ramrod_eth_rx_cqe ramrod_cqe;
3732         struct eth_rx_cqe_next_page next_page_cqe;
3733         struct eth_end_agg_rx_cqe end_agg_cqe;
3734 };
3735
3736
3737 /*
3738  * Values for RX ETH CQE type field
3739  */
3740 enum eth_rx_cqe_type {
3741         RX_ETH_CQE_TYPE_ETH_FASTPATH,
3742         RX_ETH_CQE_TYPE_ETH_RAMROD,
3743         RX_ETH_CQE_TYPE_ETH_START_AGG,
3744         RX_ETH_CQE_TYPE_ETH_STOP_AGG,
3745         MAX_ETH_RX_CQE_TYPE
3746 };
3747
3748
3749 /*
3750  * Type of SGL/Raw field in ETH RX fast path CQE
3751  */
3752 enum eth_rx_fp_sel {
3753         ETH_FP_CQE_REGULAR,
3754         ETH_FP_CQE_RAW,
3755         MAX_ETH_RX_FP_SEL
3756 };
3757
3758
3759 /*
3760  * The eth Rx SGE Descriptor
3761  */
3762 struct eth_rx_sge {
3763         __le32 addr_lo;
3764         __le32 addr_hi;
3765 };
3766
3767
3768 /*
3769  * common data for all protocols
3770  */
3771 struct spe_hdr {
3772         __le32 conn_and_cmd_data;
3773 #define SPE_HDR_CID (0xFFFFFF<<0)
3774 #define SPE_HDR_CID_SHIFT 0
3775 #define SPE_HDR_CMD_ID (0xFF<<24)
3776 #define SPE_HDR_CMD_ID_SHIFT 24
3777         __le16 type;
3778 #define SPE_HDR_CONN_TYPE (0xFF<<0)
3779 #define SPE_HDR_CONN_TYPE_SHIFT 0
3780 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
3781 #define SPE_HDR_FUNCTION_ID_SHIFT 8
3782         __le16 reserved1;
3783 };
3784
3785 /*
3786  * specific data for ethernet slow path element
3787  */
3788 union eth_specific_data {
3789         u8 protocol_data[8];
3790         struct regpair client_update_ramrod_data;
3791         struct regpair client_init_ramrod_init_data;
3792         struct eth_halt_ramrod_data halt_ramrod_data;
3793         struct regpair update_data_addr;
3794         struct eth_common_ramrod_data common_ramrod_data;
3795         struct regpair classify_cfg_addr;
3796         struct regpair filter_cfg_addr;
3797         struct regpair mcast_cfg_addr;
3798 };
3799
3800 /*
3801  * Ethernet slow path element
3802  */
3803 struct eth_spe {
3804         struct spe_hdr hdr;
3805         union eth_specific_data data;
3806 };
3807
3808
3809 /*
3810  * Ethernet command ID for slow path elements
3811  */
3812 enum eth_spqe_cmd_id {
3813         RAMROD_CMD_ID_ETH_UNUSED,
3814         RAMROD_CMD_ID_ETH_CLIENT_SETUP,
3815         RAMROD_CMD_ID_ETH_HALT,
3816         RAMROD_CMD_ID_ETH_FORWARD_SETUP,
3817         RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
3818         RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
3819         RAMROD_CMD_ID_ETH_EMPTY,
3820         RAMROD_CMD_ID_ETH_TERMINATE,
3821         RAMROD_CMD_ID_ETH_TPA_UPDATE,
3822         RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
3823         RAMROD_CMD_ID_ETH_FILTER_RULES,
3824         RAMROD_CMD_ID_ETH_MULTICAST_RULES,
3825         RAMROD_CMD_ID_ETH_RSS_UPDATE,
3826         RAMROD_CMD_ID_ETH_SET_MAC,
3827         MAX_ETH_SPQE_CMD_ID
3828 };
3829
3830
3831 /*
3832  * eth tpa update command
3833  */
3834 enum eth_tpa_update_command {
3835         TPA_UPDATE_NONE_COMMAND,
3836         TPA_UPDATE_ENABLE_COMMAND,
3837         TPA_UPDATE_DISABLE_COMMAND,
3838         MAX_ETH_TPA_UPDATE_COMMAND
3839 };
3840
3841
3842 /*
3843  * Tx regular BD structure
3844  */
3845 struct eth_tx_bd {
3846         __le32 addr_lo;
3847         __le32 addr_hi;
3848         __le16 total_pkt_bytes;
3849         __le16 nbytes;
3850         u8 reserved[4];
3851 };
3852
3853
3854 /*
3855  * structure for easy accessibility to assembler
3856  */
3857 struct eth_tx_bd_flags {
3858         u8 as_bitfield;
3859 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
3860 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
3861 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
3862 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
3863 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
3864 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
3865 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
3866 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
3867 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
3868 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
3869 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
3870 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
3871 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
3872 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
3873 };
3874
3875 /*
3876  * The eth Tx Buffer Descriptor
3877  */
3878 struct eth_tx_start_bd {
3879         __le32 addr_lo;
3880         __le32 addr_hi;
3881         __le16 nbd;
3882         __le16 nbytes;
3883         __le16 vlan_or_ethertype;
3884         struct eth_tx_bd_flags bd_flags;
3885         u8 general_data;
3886 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
3887 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
3888 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
3889 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
3890 #define ETH_TX_START_BD_RESREVED (0x1<<5)
3891 #define ETH_TX_START_BD_RESREVED_SHIFT 5
3892 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
3893 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
3894 };
3895
3896 /*
3897  * Tx parsing BD structure for ETH E1/E1h
3898  */
3899 struct eth_tx_parse_bd_e1x {
3900         u8 global_data;
3901 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
3902 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
3903 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
3904 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
3905 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
3906 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
3907 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
3908 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
3909 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
3910 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
3911         u8 tcp_flags;
3912 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
3913 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
3914 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
3915 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
3916 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
3917 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
3918 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
3919 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
3920 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
3921 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
3922 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
3923 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
3924 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
3925 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
3926 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
3927 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
3928         u8 ip_hlen_w;
3929         s8 reserved;
3930         __le16 total_hlen_w;
3931         __le16 tcp_pseudo_csum;
3932         __le16 lso_mss;
3933         __le16 ip_id;
3934         __le32 tcp_send_seq;
3935 };
3936
3937 /*
3938  * Tx parsing BD structure for ETH E2
3939  */
3940 struct eth_tx_parse_bd_e2 {
3941         __le16 dst_mac_addr_lo;
3942         __le16 dst_mac_addr_mid;
3943         __le16 dst_mac_addr_hi;
3944         __le16 src_mac_addr_lo;
3945         __le16 src_mac_addr_mid;
3946         __le16 src_mac_addr_hi;
3947         __le32 parsing_data;
3948 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
3949 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
3950 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
3951 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
3952 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
3953 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
3954 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
3955 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
3956 };
3957
3958 /*
3959  * The last BD in the BD memory will hold a pointer to the next BD memory
3960  */
3961 struct eth_tx_next_bd {
3962         __le32 addr_lo;
3963         __le32 addr_hi;
3964         u8 reserved[8];
3965 };
3966
3967 /*
3968  * union for 4 Bd types
3969  */
3970 union eth_tx_bd_types {
3971         struct eth_tx_start_bd start_bd;
3972         struct eth_tx_bd reg_bd;
3973         struct eth_tx_parse_bd_e1x parse_bd_e1x;
3974         struct eth_tx_parse_bd_e2 parse_bd_e2;
3975         struct eth_tx_next_bd next_bd;
3976 };
3977
3978 /*
3979  * array of 13 bds as appears in the eth xstorm context
3980  */
3981 struct eth_tx_bds_array {
3982         union eth_tx_bd_types bds[13];
3983 };
3984
3985
3986 /*
3987  * VLAN mode on TX BDs
3988  */
3989 enum eth_tx_vlan_type {
3990         X_ETH_NO_VLAN,
3991         X_ETH_OUTBAND_VLAN,
3992         X_ETH_INBAND_VLAN,
3993         X_ETH_FW_ADDED_VLAN,
3994         MAX_ETH_TX_VLAN_TYPE
3995 };
3996
3997
3998 /*
3999  * Ethernet VLAN filtering mode in E1x
4000  */
4001 enum eth_vlan_filter_mode {
4002         ETH_VLAN_FILTER_ANY_VLAN,
4003         ETH_VLAN_FILTER_SPECIFIC_VLAN,
4004         ETH_VLAN_FILTER_CLASSIFY,
4005         MAX_ETH_VLAN_FILTER_MODE
4006 };
4007
4008
4009 /*
4010  * MAC filtering configuration command header
4011  */
4012 struct mac_configuration_hdr {
4013         u8 length;
4014         u8 offset;
4015         __le16 client_id;
4016         __le32 echo;
4017 };
4018
4019 /*
4020  * MAC address in list for ramrod
4021  */
4022 struct mac_configuration_entry {
4023         __le16 lsb_mac_addr;
4024         __le16 middle_mac_addr;
4025         __le16 msb_mac_addr;
4026         __le16 vlan_id;
4027         u8 pf_id;
4028         u8 flags;
4029 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4030 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4031 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4032 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4033 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4034 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4035 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4036 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4037 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4038 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4039 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4040 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4041         __le16 reserved0;
4042         __le32 clients_bit_vector;
4043 };
4044
4045 /*
4046  * MAC filtering configuration command
4047  */
4048 struct mac_configuration_cmd {
4049         struct mac_configuration_hdr hdr;
4050         struct mac_configuration_entry config_table[64];
4051 };
4052
4053
4054 /*
4055  * Set-MAC command type (in E1x)
4056  */
4057 enum set_mac_action_type {
4058         T_ETH_MAC_COMMAND_INVALIDATE,
4059         T_ETH_MAC_COMMAND_SET,
4060         MAX_SET_MAC_ACTION_TYPE
4061 };
4062
4063
4064 /*
4065  * tpa update ramrod data
4066  */
4067 struct tpa_update_ramrod_data {
4068         u8 update_ipv4;
4069         u8 update_ipv6;
4070         u8 client_id;
4071         u8 max_tpa_queues;
4072         u8 max_sges_for_packet;
4073         u8 complete_on_both_clients;
4074         __le16 reserved1;
4075         __le16 sge_buff_size;
4076         __le16 max_agg_size;
4077         __le32 sge_page_base_lo;
4078         __le32 sge_page_base_hi;
4079         __le16 sge_pause_thr_low;
4080         __le16 sge_pause_thr_high;
4081 };
4082
4083
4084 /*
4085  * approximate-match multicast filtering for E1H per function in Tstorm
4086  */
4087 struct tstorm_eth_approximate_match_multicast_filtering {
4088         u32 mcast_add_hash_bit_array[8];
4089 };
4090
4091
4092 /*
4093  * Common configuration parameters per function in Tstorm
4094  */
4095 struct tstorm_eth_function_common_config {
4096         __le16 config_flags;
4097 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4098 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4099 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4100 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4101 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4102 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4103 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4104 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4105 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4106 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4107 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4108 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4109 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4110 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4111         u8 rss_result_mask;
4112         u8 reserved1;
4113         __le16 vlan_id[2];
4114 };
4115
4116
4117 /*
4118  * MAC filtering configuration parameters per port in Tstorm
4119  */
4120 struct tstorm_eth_mac_filter_config {
4121         __le32 ucast_drop_all;
4122         __le32 ucast_accept_all;
4123         __le32 mcast_drop_all;
4124         __le32 mcast_accept_all;
4125         __le32 bcast_accept_all;
4126         __le32 vlan_filter[2];
4127         __le32 unmatched_unicast;
4128 };
4129
4130
4131 /*
4132  * tx only queue init ramrod data
4133  */
4134 struct tx_queue_init_ramrod_data {
4135         struct client_init_general_data general;
4136         struct client_init_tx_data tx;
4137 };
4138
4139
4140 /*
4141  * Three RX producers for ETH
4142  */
4143 struct ustorm_eth_rx_producers {
4144 #if defined(__BIG_ENDIAN)
4145         u16 bd_prod;
4146         u16 cqe_prod;
4147 #elif defined(__LITTLE_ENDIAN)
4148         u16 cqe_prod;
4149         u16 bd_prod;
4150 #endif
4151 #if defined(__BIG_ENDIAN)
4152         u16 reserved;
4153         u16 sge_prod;
4154 #elif defined(__LITTLE_ENDIAN)
4155         u16 sge_prod;
4156         u16 reserved;
4157 #endif
4158 };
4159
4160
4161 /*
4162  * cfc delete event data
4163  */
4164 struct cfc_del_event_data {
4165         u32 cid;
4166         u32 reserved0;
4167         u32 reserved1;
4168 };
4169
4170
4171 /*
4172  * per-port SAFC demo variables
4173  */
4174 struct cmng_flags_per_port {
4175         u32 cmng_enables;
4176 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4177 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4178 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4179 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4180 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4181 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4182 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4183 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4184 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4185 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4186         u32 __reserved1;
4187 };
4188
4189
4190 /*
4191  * per-port rate shaping variables
4192  */
4193 struct rate_shaping_vars_per_port {
4194         u32 rs_periodic_timeout;
4195         u32 rs_threshold;
4196 };
4197
4198 /*
4199  * per-port fairness variables
4200  */
4201 struct fairness_vars_per_port {
4202         u32 upper_bound;
4203         u32 fair_threshold;
4204         u32 fairness_timeout;
4205         u32 reserved0;
4206 };
4207
4208 /*
4209  * per-port SAFC variables
4210  */
4211 struct safc_struct_per_port {
4212 #if defined(__BIG_ENDIAN)
4213         u16 __reserved1;
4214         u8 __reserved0;
4215         u8 safc_timeout_usec;
4216 #elif defined(__LITTLE_ENDIAN)
4217         u8 safc_timeout_usec;
4218         u8 __reserved0;
4219         u16 __reserved1;
4220 #endif
4221         u8 cos_to_traffic_types[MAX_COS_NUMBER];
4222         u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4223 };
4224
4225 /*
4226  * Per-port congestion management variables
4227  */
4228 struct cmng_struct_per_port {
4229         struct rate_shaping_vars_per_port rs_vars;
4230         struct fairness_vars_per_port fair_vars;
4231         struct safc_struct_per_port safc_vars;
4232         struct cmng_flags_per_port flags;
4233 };
4234
4235
4236 /*
4237  * Protocol-common command ID for slow path elements
4238  */
4239 enum common_spqe_cmd_id {
4240         RAMROD_CMD_ID_COMMON_UNUSED,
4241         RAMROD_CMD_ID_COMMON_FUNCTION_START,
4242         RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4243         RAMROD_CMD_ID_COMMON_CFC_DEL,
4244         RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4245         RAMROD_CMD_ID_COMMON_STAT_QUERY,
4246         RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4247         RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4248         RAMROD_CMD_ID_COMMON_RESERVED1,
4249         RAMROD_CMD_ID_COMMON_RESERVED2,
4250         MAX_COMMON_SPQE_CMD_ID
4251 };
4252
4253
4254 /*
4255  * Per-protocol connection types
4256  */
4257 enum connection_type {
4258         ETH_CONNECTION_TYPE,
4259         TOE_CONNECTION_TYPE,
4260         RDMA_CONNECTION_TYPE,
4261         ISCSI_CONNECTION_TYPE,
4262         FCOE_CONNECTION_TYPE,
4263         RESERVED_CONNECTION_TYPE_0,
4264         RESERVED_CONNECTION_TYPE_1,
4265         RESERVED_CONNECTION_TYPE_2,
4266         NONE_CONNECTION_TYPE,
4267         MAX_CONNECTION_TYPE
4268 };
4269
4270
4271 /*
4272  * Cos modes
4273  */
4274 enum cos_mode {
4275         OVERRIDE_COS,
4276         STATIC_COS,
4277         FW_WRR,
4278         MAX_COS_MODE
4279 };
4280
4281
4282 /*
4283  * Dynamic HC counters set by the driver
4284  */
4285 struct hc_dynamic_drv_counter {
4286         u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4287 };
4288
4289 /*
4290  * zone A per-queue data
4291  */
4292 struct cstorm_queue_zone_data {
4293         struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4294         struct regpair reserved[2];
4295 };
4296
4297
4298 /*
4299  * Vf-PF channel data in cstorm ram (non-triggered zone)
4300  */
4301 struct vf_pf_channel_zone_data {
4302         u32 msg_addr_lo;
4303         u32 msg_addr_hi;
4304 };
4305
4306 /*
4307  * zone for VF non-triggered data
4308  */
4309 struct non_trigger_vf_zone {
4310         struct vf_pf_channel_zone_data vf_pf_channel;
4311 };
4312
4313 /*
4314  * Vf-PF channel trigger zone in cstorm ram
4315  */
4316 struct vf_pf_channel_zone_trigger {
4317         u8 addr_valid;
4318 };
4319
4320 /*
4321  * zone that triggers the in-bound interrupt
4322  */
4323 struct trigger_vf_zone {
4324 #if defined(__BIG_ENDIAN)
4325         u16 reserved1;
4326         u8 reserved0;
4327         struct vf_pf_channel_zone_trigger vf_pf_channel;
4328 #elif defined(__LITTLE_ENDIAN)
4329         struct vf_pf_channel_zone_trigger vf_pf_channel;
4330         u8 reserved0;
4331         u16 reserved1;
4332 #endif
4333         u32 reserved2;
4334 };
4335
4336 /*
4337  * zone B per-VF data
4338  */
4339 struct cstorm_vf_zone_data {
4340         struct non_trigger_vf_zone non_trigger;
4341         struct trigger_vf_zone trigger;
4342 };
4343
4344
4345 /*
4346  * Dynamic host coalescing init parameters, per state machine
4347  */
4348 struct dynamic_hc_sm_config {
4349         u32 threshold[3];
4350         u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
4351         u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
4352         u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
4353         u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
4354         u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
4355 };
4356
4357 /*
4358  * Dynamic host coalescing init parameters
4359  */
4360 struct dynamic_hc_config {
4361         struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
4362 };
4363
4364
4365 struct e2_integ_data {
4366 #if defined(__BIG_ENDIAN)
4367         u8 flags;
4368 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4369 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4370 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4371 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4372 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4373 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4374 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4375 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4376 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4377 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4378 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4379 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4380         u8 cos;
4381         u8 voq;
4382         u8 pbf_queue;
4383 #elif defined(__LITTLE_ENDIAN)
4384         u8 pbf_queue;
4385         u8 voq;
4386         u8 cos;
4387         u8 flags;
4388 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4389 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4390 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4391 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4392 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4393 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4394 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4395 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4396 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4397 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4398 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4399 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4400 #endif
4401 #if defined(__BIG_ENDIAN)
4402         u16 reserved3;
4403         u8 reserved2;
4404         u8 ramEn;
4405 #elif defined(__LITTLE_ENDIAN)
4406         u8 ramEn;
4407         u8 reserved2;
4408         u16 reserved3;
4409 #endif
4410 };
4411
4412
4413 /*
4414  * set mac event data
4415  */
4416 struct eth_event_data {
4417         u32 echo;
4418         u32 reserved0;
4419         u32 reserved1;
4420 };
4421
4422
4423 /*
4424  * pf-vf event data
4425  */
4426 struct vf_pf_event_data {
4427         u8 vf_id;
4428         u8 reserved0;
4429         u16 reserved1;
4430         u32 msg_addr_lo;
4431         u32 msg_addr_hi;
4432 };
4433
4434 /*
4435  * VF FLR event data
4436  */
4437 struct vf_flr_event_data {
4438         u8 vf_id;
4439         u8 reserved0;
4440         u16 reserved1;
4441         u32 reserved2;
4442         u32 reserved3;
4443 };
4444
4445 /*
4446  * malicious VF event data
4447  */
4448 struct malicious_vf_event_data {
4449         u8 vf_id;
4450         u8 reserved0;
4451         u16 reserved1;
4452         u32 reserved2;
4453         u32 reserved3;
4454 };
4455
4456 /*
4457  * union for all event ring message types
4458  */
4459 union event_data {
4460         struct vf_pf_event_data vf_pf_event;
4461         struct eth_event_data eth_event;
4462         struct cfc_del_event_data cfc_del_event;
4463         struct vf_flr_event_data vf_flr_event;
4464         struct malicious_vf_event_data malicious_vf_event;
4465 };
4466
4467
4468 /*
4469  * per PF event ring data
4470  */
4471 struct event_ring_data {
4472         struct regpair base_addr;
4473 #if defined(__BIG_ENDIAN)
4474         u8 index_id;
4475         u8 sb_id;
4476         u16 producer;
4477 #elif defined(__LITTLE_ENDIAN)
4478         u16 producer;
4479         u8 sb_id;
4480         u8 index_id;
4481 #endif
4482         u32 reserved0;
4483 };
4484
4485
4486 /*
4487  * event ring message element (each element is 128 bits)
4488  */
4489 struct event_ring_msg {
4490         u8 opcode;
4491         u8 error;
4492         u16 reserved1;
4493         union event_data data;
4494 };
4495
4496 /*
4497  * event ring next page element (128 bits)
4498  */
4499 struct event_ring_next {
4500         struct regpair addr;
4501         u32 reserved[2];
4502 };
4503
4504 /*
4505  * union for event ring element types (each element is 128 bits)
4506  */
4507 union event_ring_elem {
4508         struct event_ring_msg message;
4509         struct event_ring_next next_page;
4510 };
4511
4512
4513 /*
4514  * Common event ring opcodes
4515  */
4516 enum event_ring_opcode {
4517         EVENT_RING_OPCODE_VF_PF_CHANNEL,
4518         EVENT_RING_OPCODE_FUNCTION_START,
4519         EVENT_RING_OPCODE_FUNCTION_STOP,
4520         EVENT_RING_OPCODE_CFC_DEL,
4521         EVENT_RING_OPCODE_CFC_DEL_WB,
4522         EVENT_RING_OPCODE_STAT_QUERY,
4523         EVENT_RING_OPCODE_STOP_TRAFFIC,
4524         EVENT_RING_OPCODE_START_TRAFFIC,
4525         EVENT_RING_OPCODE_VF_FLR,
4526         EVENT_RING_OPCODE_MALICIOUS_VF,
4527         EVENT_RING_OPCODE_FORWARD_SETUP,
4528         EVENT_RING_OPCODE_RSS_UPDATE_RULES,
4529         EVENT_RING_OPCODE_RESERVED1,
4530         EVENT_RING_OPCODE_RESERVED2,
4531         EVENT_RING_OPCODE_SET_MAC,
4532         EVENT_RING_OPCODE_CLASSIFICATION_RULES,
4533         EVENT_RING_OPCODE_FILTERS_RULES,
4534         EVENT_RING_OPCODE_MULTICAST_RULES,
4535         MAX_EVENT_RING_OPCODE
4536 };
4537
4538
4539 /*
4540  * Modes for fairness algorithm
4541  */
4542 enum fairness_mode {
4543         FAIRNESS_COS_WRR_MODE,
4544         FAIRNESS_COS_ETS_MODE,
4545         MAX_FAIRNESS_MODE
4546 };
4547
4548
4549 /*
4550  * per-vnic fairness variables
4551  */
4552 struct fairness_vars_per_vn {
4553         u32 cos_credit_delta[MAX_COS_NUMBER];
4554         u32 vn_credit_delta;
4555         u32 __reserved0;
4556 };
4557
4558
4559 /*
4560  * Priority and cos
4561  */
4562 struct priority_cos {
4563         u8 priority;
4564         u8 cos;
4565         __le16 reserved1;
4566 };
4567
4568 /*
4569  * The data for flow control configuration
4570  */
4571 struct flow_control_configuration {
4572         struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
4573         u8 dcb_enabled;
4574         u8 dcb_version;
4575         u8 dont_add_pri_0_en;
4576         u8 reserved1;
4577         __le32 reserved2;
4578 };
4579
4580
4581 /*
4582  *
4583  */
4584 struct function_start_data {
4585         __le16 function_mode;
4586         __le16 sd_vlan_tag;
4587         u16 reserved;
4588         u8 path_id;
4589         u8 network_cos_mode;
4590 };
4591
4592
4593 /*
4594  * FW version stored in the Xstorm RAM
4595  */
4596 struct fw_version {
4597 #if defined(__BIG_ENDIAN)
4598         u8 engineering;
4599         u8 revision;
4600         u8 minor;
4601         u8 major;
4602 #elif defined(__LITTLE_ENDIAN)
4603         u8 major;
4604         u8 minor;
4605         u8 revision;
4606         u8 engineering;
4607 #endif
4608         u32 flags;
4609 #define FW_VERSION_OPTIMIZED (0x1<<0)
4610 #define FW_VERSION_OPTIMIZED_SHIFT 0
4611 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
4612 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
4613 #define FW_VERSION_CHIP_VERSION (0x3<<2)
4614 #define FW_VERSION_CHIP_VERSION_SHIFT 2
4615 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
4616 #define __FW_VERSION_RESERVED_SHIFT 4
4617 };
4618
4619
4620 /*
4621  * Dynamic Host-Coalescing - Driver(host) counters
4622  */
4623 struct hc_dynamic_sb_drv_counters {
4624         u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
4625 };
4626
4627
4628 /*
4629  * 2 bytes. configuration/state parameters for a single protocol index
4630  */
4631 struct hc_index_data {
4632 #if defined(__BIG_ENDIAN)
4633         u8 flags;
4634 #define HC_INDEX_DATA_SM_ID (0x1<<0)
4635 #define HC_INDEX_DATA_SM_ID_SHIFT 0
4636 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
4637 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
4638 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
4639 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
4640 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
4641 #define HC_INDEX_DATA_RESERVE_SHIFT 3
4642         u8 timeout;
4643 #elif defined(__LITTLE_ENDIAN)
4644         u8 timeout;
4645         u8 flags;
4646 #define HC_INDEX_DATA_SM_ID (0x1<<0)
4647 #define HC_INDEX_DATA_SM_ID_SHIFT 0
4648 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
4649 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
4650 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
4651 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
4652 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
4653 #define HC_INDEX_DATA_RESERVE_SHIFT 3
4654 #endif
4655 };
4656
4657
4658 /*
4659  * HC state-machine
4660  */
4661 struct hc_status_block_sm {
4662 #if defined(__BIG_ENDIAN)
4663         u8 igu_seg_id;
4664         u8 igu_sb_id;
4665         u8 timer_value;
4666         u8 __flags;
4667 #elif defined(__LITTLE_ENDIAN)
4668         u8 __flags;
4669         u8 timer_value;
4670         u8 igu_sb_id;
4671         u8 igu_seg_id;
4672 #endif
4673         u32 time_to_expire;
4674 };
4675
4676 /*
4677  * hold PCI identification variables- used in various places in firmware
4678  */
4679 struct pci_entity {
4680 #if defined(__BIG_ENDIAN)
4681         u8 vf_valid;
4682         u8 vf_id;
4683         u8 vnic_id;
4684         u8 pf_id;
4685 #elif defined(__LITTLE_ENDIAN)
4686         u8 pf_id;
4687         u8 vnic_id;
4688         u8 vf_id;
4689         u8 vf_valid;
4690 #endif
4691 };
4692
4693 /*
4694  * The fast-path status block meta-data, common to all chips
4695  */
4696 struct hc_sb_data {
4697         struct regpair host_sb_addr;
4698         struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
4699         struct pci_entity p_func;
4700 #if defined(__BIG_ENDIAN)
4701         u8 rsrv0;
4702         u8 state;
4703         u8 dhc_qzone_id;
4704         u8 same_igu_sb_1b;
4705 #elif defined(__LITTLE_ENDIAN)
4706         u8 same_igu_sb_1b;
4707         u8 dhc_qzone_id;
4708         u8 state;
4709         u8 rsrv0;
4710 #endif
4711         struct regpair rsrv1[2];
4712 };
4713
4714
4715 /*
4716  * Segment types for host coaslescing
4717  */
4718 enum hc_segment {
4719         HC_REGULAR_SEGMENT,
4720         HC_DEFAULT_SEGMENT,
4721         MAX_HC_SEGMENT
4722 };
4723
4724
4725 /*
4726  * The fast-path status block meta-data
4727  */
4728 struct hc_sp_status_block_data {
4729         struct regpair host_sb_addr;
4730 #if defined(__BIG_ENDIAN)
4731         u8 rsrv1;
4732         u8 state;
4733         u8 igu_seg_id;
4734         u8 igu_sb_id;
4735 #elif defined(__LITTLE_ENDIAN)
4736         u8 igu_sb_id;
4737         u8 igu_seg_id;
4738         u8 state;
4739         u8 rsrv1;
4740 #endif
4741         struct pci_entity p_func;
4742 };
4743
4744
4745 /*
4746  * The fast-path status block meta-data
4747  */
4748 struct hc_status_block_data_e1x {
4749         struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
4750         struct hc_sb_data common;
4751 };
4752
4753
4754 /*
4755  * The fast-path status block meta-data
4756  */
4757 struct hc_status_block_data_e2 {
4758         struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
4759         struct hc_sb_data common;
4760 };
4761
4762
4763 /*
4764  * IGU block operartion modes (in Everest2)
4765  */
4766 enum igu_mode {
4767         HC_IGU_BC_MODE,
4768         HC_IGU_NBC_MODE,
4769         MAX_IGU_MODE
4770 };
4771
4772
4773 /*
4774  * IP versions
4775  */
4776 enum ip_ver {
4777         IP_V4,
4778         IP_V6,
4779         MAX_IP_VER
4780 };
4781
4782
4783 /*
4784  * Multi-function modes
4785  */
4786 enum mf_mode {
4787         SINGLE_FUNCTION,
4788         MULTI_FUNCTION_SD,
4789         MULTI_FUNCTION_SI,
4790         MULTI_FUNCTION_RESERVED,
4791         MAX_MF_MODE
4792 };
4793
4794 /*
4795  * Protocol-common statistics collected by the Tstorm (per pf)
4796  */
4797 struct tstorm_per_pf_stats {
4798         struct regpair rcv_error_bytes;
4799 };
4800
4801 /*
4802  *
4803  */
4804 struct per_pf_stats {
4805         struct tstorm_per_pf_stats tstorm_pf_statistics;
4806 };
4807
4808
4809 /*
4810  * Protocol-common statistics collected by the Tstorm (per port)
4811  */
4812 struct tstorm_per_port_stats {
4813         __le32 mac_discard;
4814         __le32 mac_filter_discard;
4815         __le32 brb_truncate_discard;
4816         __le32 mf_tag_discard;
4817         __le32 packet_drop;
4818         __le32 reserved;
4819 };
4820
4821 /*
4822  *
4823  */
4824 struct per_port_stats {
4825         struct tstorm_per_port_stats tstorm_port_statistics;
4826 };
4827
4828
4829 /*
4830  * Protocol-common statistics collected by the Tstorm (per client)
4831  */
4832 struct tstorm_per_queue_stats {
4833         struct regpair rcv_ucast_bytes;
4834         __le32 rcv_ucast_pkts;
4835         __le32 checksum_discard;
4836         struct regpair rcv_bcast_bytes;
4837         __le32 rcv_bcast_pkts;
4838         __le32 pkts_too_big_discard;
4839         struct regpair rcv_mcast_bytes;
4840         __le32 rcv_mcast_pkts;
4841         __le32 ttl0_discard;
4842         __le16 no_buff_discard;
4843         __le16 reserved0;
4844         __le32 reserved1;
4845 };
4846
4847 /*
4848  * Protocol-common statistics collected by the Ustorm (per client)
4849  */
4850 struct ustorm_per_queue_stats {
4851         struct regpair ucast_no_buff_bytes;
4852         struct regpair mcast_no_buff_bytes;
4853         struct regpair bcast_no_buff_bytes;
4854         __le32 ucast_no_buff_pkts;
4855         __le32 mcast_no_buff_pkts;
4856         __le32 bcast_no_buff_pkts;
4857         __le32 coalesced_pkts;
4858         struct regpair coalesced_bytes;
4859         __le32 coalesced_events;
4860         __le32 coalesced_aborts;
4861 };
4862
4863 /*
4864  * Protocol-common statistics collected by the Xstorm (per client)
4865  */
4866 struct xstorm_per_queue_stats {
4867         struct regpair ucast_bytes_sent;
4868         struct regpair mcast_bytes_sent;
4869         struct regpair bcast_bytes_sent;
4870         __le32 ucast_pkts_sent;
4871         __le32 mcast_pkts_sent;
4872         __le32 bcast_pkts_sent;
4873         __le32 error_drop_pkts;
4874 };
4875
4876 /*
4877  *
4878  */
4879 struct per_queue_stats {
4880         struct tstorm_per_queue_stats tstorm_queue_statistics;
4881         struct ustorm_per_queue_stats ustorm_queue_statistics;
4882         struct xstorm_per_queue_stats xstorm_queue_statistics;
4883 };
4884
4885
4886 /*
4887  * FW version stored in first line of pram
4888  */
4889 struct pram_fw_version {
4890         u8 major;
4891         u8 minor;
4892         u8 revision;
4893         u8 engineering;
4894         u8 flags;
4895 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
4896 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
4897 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
4898 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
4899 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
4900 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
4901 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
4902 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
4903 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
4904 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
4905 };
4906
4907
4908 /*
4909  * Ethernet slow path element
4910  */
4911 union protocol_common_specific_data {
4912         u8 protocol_data[8];
4913         struct regpair phy_address;
4914         struct regpair mac_config_addr;
4915 };
4916
4917 /*
4918  * The send queue element
4919  */
4920 struct protocol_common_spe {
4921         struct spe_hdr hdr;
4922         union protocol_common_specific_data data;
4923 };
4924
4925
4926 /*
4927  * a single rate shaping counter. can be used as protocol or vnic counter
4928  */
4929 struct rate_shaping_counter {
4930         u32 quota;
4931 #if defined(__BIG_ENDIAN)
4932         u16 __reserved0;
4933         u16 rate;
4934 #elif defined(__LITTLE_ENDIAN)
4935         u16 rate;
4936         u16 __reserved0;
4937 #endif
4938 };
4939
4940
4941 /*
4942  * per-vnic rate shaping variables
4943  */
4944 struct rate_shaping_vars_per_vn {
4945         struct rate_shaping_counter vn_counter;
4946 };
4947
4948
4949 /*
4950  * The send queue element
4951  */
4952 struct slow_path_element {
4953         struct spe_hdr hdr;
4954         struct regpair protocol_data;
4955 };
4956
4957
4958 /*
4959  * Protocol-common statistics counter
4960  */
4961 struct stats_counter {
4962         __le16 xstats_counter;
4963         __le16 reserved0;
4964         __le32 reserved1;
4965         __le16 tstats_counter;
4966         __le16 reserved2;
4967         __le32 reserved3;
4968         __le16 ustats_counter;
4969         __le16 reserved4;
4970         __le32 reserved5;
4971         __le16 cstats_counter;
4972         __le16 reserved6;
4973         __le32 reserved7;
4974 };
4975
4976
4977 /*
4978  *
4979  */
4980 struct stats_query_entry {
4981         u8 kind;
4982         u8 index;
4983         __le16 funcID;
4984         __le32 reserved;
4985         struct regpair address;
4986 };
4987
4988 /*
4989  * statistic command
4990  */
4991 struct stats_query_cmd_group {
4992         struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
4993 };
4994
4995
4996 /*
4997  * statistic command header
4998  */
4999 struct stats_query_header {
5000         u8 cmd_num;
5001         u8 reserved0;
5002         __le16 drv_stats_counter;
5003         __le32 reserved1;
5004         struct regpair stats_counters_addrs;
5005 };
5006
5007
5008 /*
5009  * Types of statistcis query entry
5010  */
5011 enum stats_query_type {
5012         STATS_TYPE_QUEUE,
5013         STATS_TYPE_PORT,
5014         STATS_TYPE_PF,
5015         STATS_TYPE_TOE,
5016         STATS_TYPE_FCOE,
5017         MAX_STATS_QUERY_TYPE
5018 };
5019
5020
5021 /*
5022  * Indicate of the function status block state
5023  */
5024 enum status_block_state {
5025         SB_DISABLED,
5026         SB_ENABLED,
5027         SB_CLEANED,
5028         MAX_STATUS_BLOCK_STATE
5029 };
5030
5031
5032 /*
5033  * Storm IDs (including attentions for IGU related enums)
5034  */
5035 enum storm_id {
5036         USTORM_ID,
5037         CSTORM_ID,
5038         XSTORM_ID,
5039         TSTORM_ID,
5040         ATTENTION_ID,
5041         MAX_STORM_ID
5042 };
5043
5044
5045 /*
5046  * Taffic types used in ETS and flow control algorithms
5047  */
5048 enum traffic_type {
5049         LLFC_TRAFFIC_TYPE_NW,
5050         LLFC_TRAFFIC_TYPE_FCOE,
5051         LLFC_TRAFFIC_TYPE_ISCSI,
5052         MAX_TRAFFIC_TYPE
5053 };
5054
5055
5056 /*
5057  * zone A per-queue data
5058  */
5059 struct tstorm_queue_zone_data {
5060         struct regpair reserved[4];
5061 };
5062
5063
5064 /*
5065  * zone B per-VF data
5066  */
5067 struct tstorm_vf_zone_data {
5068         struct regpair reserved;
5069 };
5070
5071
5072 /*
5073  * zone A per-queue data
5074  */
5075 struct ustorm_queue_zone_data {
5076         struct ustorm_eth_rx_producers eth_rx_producers;
5077         struct regpair reserved[3];
5078 };
5079
5080
5081 /*
5082  * zone B per-VF data
5083  */
5084 struct ustorm_vf_zone_data {
5085         struct regpair reserved;
5086 };
5087
5088
5089 /*
5090  * data per VF-PF channel
5091  */
5092 struct vf_pf_channel_data {
5093 #if defined(__BIG_ENDIAN)
5094         u16 reserved0;
5095         u8 valid;
5096         u8 state;
5097 #elif defined(__LITTLE_ENDIAN)
5098         u8 state;
5099         u8 valid;
5100         u16 reserved0;
5101 #endif
5102         u32 reserved1;
5103 };
5104
5105
5106 /*
5107  * State of VF-PF channel
5108  */
5109 enum vf_pf_channel_state {
5110         VF_PF_CHANNEL_STATE_READY,
5111         VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5112         MAX_VF_PF_CHANNEL_STATE
5113 };
5114
5115
5116 /*
5117  * zone A per-queue data
5118  */
5119 struct xstorm_queue_zone_data {
5120         struct regpair reserved[4];
5121 };
5122
5123
5124 /*
5125  * zone B per-VF data
5126  */
5127 struct xstorm_vf_zone_data {
5128         struct regpair reserved;
5129 };
5130
5131 #endif /* BNX2X_HSI_H */