drivers/net/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2010 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17 #include <linux/ethtool.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/types.h>
  20 #include <linux/sched.h>
  21 #include <linux/crc32.h>
  22
  23
  24 #include "bnx2x.h"
  25 #include "bnx2x_cmn.h"
  26 #include "bnx2x_dump.h"
  27 #include "bnx2x_init.h"
  28
  29 /* Note: in the format strings below %s is replaced by the queue-name which is
  30  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  31  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  32  */
  33 #define MAX_QUEUE_NAME_LEN      4
  34 static const struct {
  35         long offset;
  36         int size;
  37         char string[ETH_GSTRING_LEN];
  38 } bnx2x_q_stats_arr[] = {
  39 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  40         { Q_STATS_OFFSET32(error_bytes_received_hi),
  41                                                 8, "[%s]: rx_error_bytes" },
  42         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  43                                                 8, "[%s]: rx_ucast_packets" },
  44         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  45                                                 8, "[%s]: rx_mcast_packets" },
  46         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  47                                                 8, "[%s]: rx_bcast_packets" },
  48         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  49         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  50                                          4, "[%s]: rx_phy_ip_err_discards"},
  51         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  52                                          4, "[%s]: rx_skb_alloc_discard" },
  53         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  54
  55 /* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  56         { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  57                                                 8, "[%s]: tx_ucast_packets" },
  58         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  59                                                 8, "[%s]: tx_mcast_packets" },
  60         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  61                                                 8, "[%s]: tx_bcast_packets" }
  62 };
  63
  64 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  65
  66 static const struct {
  67         long offset;
  68         int size;
  69         u32 flags;
  70 #define STATS_FLAGS_PORT                1
  71 #define STATS_FLAGS_FUNC                2
  72 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  73         char string[ETH_GSTRING_LEN];
  74 } bnx2x_stats_arr[] = {
  75 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  76                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  77         { STATS_OFFSET32(error_bytes_received_hi),
  78                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  79         { STATS_OFFSET32(total_unicast_packets_received_hi),
  80                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  81         { STATS_OFFSET32(total_multicast_packets_received_hi),
  82                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  83         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  84                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  85         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  86                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  87         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  88                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  89         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  90                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  91         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  92                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  93 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
  94                                 8, STATS_FLAGS_PORT, "rx_fragments" },
  95         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
  96                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
  97         { STATS_OFFSET32(no_buff_discard_hi),
  98                                 8, STATS_FLAGS_BOTH, "rx_discards" },
  99         { STATS_OFFSET32(mac_filter_discard),
 100                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 101         { STATS_OFFSET32(xxoverflow_discard),
 102                                 4, STATS_FLAGS_PORT, "rx_fw_discards" },
 103         { STATS_OFFSET32(brb_drop_hi),
 104                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 105         { STATS_OFFSET32(brb_truncate_hi),
 106                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 107         { STATS_OFFSET32(pause_frames_received_hi),
 108                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 109         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 110                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 111         { STATS_OFFSET32(nig_timer_max),
 112                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 113 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 114                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 115         { STATS_OFFSET32(rx_skb_alloc_failed),
 116                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 117         { STATS_OFFSET32(hw_csum_err),
 118                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 119
 120         { STATS_OFFSET32(total_bytes_transmitted_hi),
 121                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 122         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 123                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 124         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 125                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 126         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 127                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 128         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 129                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 130         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 131                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 132         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 133                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 134 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 135                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 136         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 137                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 138         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 139                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 140         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 141                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 142         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 143                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 144         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 145                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 146         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 147                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 148         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 149                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 150         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 151                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 152         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 153                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 154 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 155                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 156         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 157                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 158         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 159                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 160         { STATS_OFFSET32(pause_frames_sent_hi),
 161                                 8, STATS_FLAGS_PORT, "tx_pause_frames" }
 162 };
 163
 164 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 165
 166 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 167 {
 168         struct bnx2x *bp = netdev_priv(dev);
 169         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 170         /* Dual Media boards present all available port types */
 171         cmd->supported = bp->port.supported[cfg_idx] |
 172                 (bp->port.supported[cfg_idx ^ 1] &
 173                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 174         cmd->advertising = bp->port.advertising[cfg_idx];
 175
 176         if ((bp->state == BNX2X_STATE_OPEN) &&
 177             !(bp->flags & MF_FUNC_DIS) &&
 178             (bp->link_vars.link_up)) {
 179                 cmd->speed = bp->link_vars.line_speed;
 180                 cmd->duplex = bp->link_vars.duplex;
 181         } else {
 182
 183                 cmd->speed = bp->link_params.req_line_speed[cfg_idx];
 184                 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
 185         }
 186
 187         if (IS_MF(bp))
 188                 cmd->speed = bnx2x_get_mf_speed(bp);
 189
 190         if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 191                 cmd->port = PORT_TP;
 192         else if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 193                 cmd->port = PORT_FIBRE;
 194         else
 195                 BNX2X_ERR("XGXS PHY Failure detected\n");
 196
 197         cmd->phy_address = bp->mdio.prtad;
 198         cmd->transceiver = XCVR_INTERNAL;
 199
 200         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 201                 cmd->autoneg = AUTONEG_ENABLE;
 202         else
 203                 cmd->autoneg = AUTONEG_DISABLE;
 204
 205         cmd->maxtxpkt = 0;
 206         cmd->maxrxpkt = 0;
 207
 208         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 209            DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %d\n"
 210            DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 211            DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 212            cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
 213            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 214            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 215
 216         return 0;
 217 }
 218
 219 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 220 {
 221         struct bnx2x *bp = netdev_priv(dev);
 222         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 223         u32 speed;
 224
 225         if (IS_MF_SD(bp))
 226                 return 0;
 227
 228         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 229            "  supported 0x%x  advertising 0x%x  speed %d speed_hi %d\n"
 230            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 231            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 232            cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
 233            cmd->speed_hi,
 234            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 235            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 236
 237         speed = cmd->speed;
 238         speed |= (cmd->speed_hi << 16);
 239
 240         if (IS_MF_SI(bp)) {
 241                 u32 part;
 242                 u32 line_speed = bp->link_vars.line_speed;
 243
 244                 /* use 10G if no link detected */
 245                 if (!line_speed)
 246                         line_speed = 10000;
 247
 248                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 249                         BNX2X_DEV_INFO("To set speed BC %X or higher "
 250                                        "is required, please upgrade BC\n",
 251                                        REQ_BC_VER_4_SET_MF_BW);
 252                         return -EINVAL;
 253                 }
 254
 255                 part = (speed * 100) / line_speed;
 256
 257                 if (line_speed < speed || !part) {
 258                         BNX2X_DEV_INFO("Speed setting should be in a range "
 259                                        "from 1%% to 100%% "
 260                                        "of actual line speed\n");
 261                         return -EINVAL;
 262                 }
 263
 264                 if (bp->state != BNX2X_STATE_OPEN)
 265                         /* store value for following "load" */
 266                         bp->pending_max = part;
 267                 else
 268                         bnx2x_update_max_mf_config(bp, part);
 269
 270                 return 0;
 271         }
 272
 273         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 274         old_multi_phy_config = bp->link_params.multi_phy_config;
 275         switch (cmd->port) {
 276         case PORT_TP:
 277                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 278                         break; /* no port change */
 279
 280                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 281                       bp->port.supported[1] & SUPPORTED_TP)) {
 282                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 283                         return -EINVAL;
 284                 }
 285                 bp->link_params.multi_phy_config &=
 286                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 287                 if (bp->link_params.multi_phy_config &
 288                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 289                         bp->link_params.multi_phy_config |=
 290                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 291                 else
 292                         bp->link_params.multi_phy_config |=
 293                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 294                 break;
 295         case PORT_FIBRE:
 296                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 297                         break; /* no port change */
 298
 299                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 300                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 301                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 302                         return -EINVAL;
 303                 }
 304                 bp->link_params.multi_phy_config &=
 305                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 306                 if (bp->link_params.multi_phy_config &
 307                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 308                         bp->link_params.multi_phy_config |=
 309                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 310                 else
 311                         bp->link_params.multi_phy_config |=
 312                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 313                 break;
 314         default:
 315                 DP(NETIF_MSG_LINK, "Unsupported port type\n");
 316                 return -EINVAL;
 317         }
 318         /* Save new config in case command complete successuly */
 319         new_multi_phy_config = bp->link_params.multi_phy_config;
 320         /* Get the new cfg_idx */
 321         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 322         /* Restore old config in case command failed */
 323         bp->link_params.multi_phy_config = old_multi_phy_config;
 324         DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
 325
 326         if (cmd->autoneg == AUTONEG_ENABLE) {
 327                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 328                         DP(NETIF_MSG_LINK, "Autoneg not supported\n");
 329                         return -EINVAL;
 330                 }
 331
 332                 /* advertise the requested speed and duplex if supported */
 333                 cmd->advertising &= bp->port.supported[cfg_idx];
 334
 335                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 336                 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
 337                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
 338                                          cmd->advertising);
 339
 340         } else { /* forced speed */
 341                 /* advertise the requested speed and duplex if supported */
 342                 switch (speed) {
 343                 case SPEED_10:
 344                         if (cmd->duplex == DUPLEX_FULL) {
 345                                 if (!(bp->port.supported[cfg_idx] &
 346                                       SUPPORTED_10baseT_Full)) {
 347                                         DP(NETIF_MSG_LINK,
 348                                            "10M full not supported\n");
 349                                         return -EINVAL;
 350                                 }
 351
 352                                 advertising = (ADVERTISED_10baseT_Full |
 353                                                ADVERTISED_TP);
 354                         } else {
 355                                 if (!(bp->port.supported[cfg_idx] &
 356                                       SUPPORTED_10baseT_Half)) {
 357                                         DP(NETIF_MSG_LINK,
 358                                            "10M half not supported\n");
 359                                         return -EINVAL;
 360                                 }
 361
 362                                 advertising = (ADVERTISED_10baseT_Half |
 363                                                ADVERTISED_TP);
 364                         }
 365                         break;
 366
 367                 case SPEED_100:
 368                         if (cmd->duplex == DUPLEX_FULL) {
 369                                 if (!(bp->port.supported[cfg_idx] &
 370                                                 SUPPORTED_100baseT_Full)) {
 371                                         DP(NETIF_MSG_LINK,
 372                                            "100M full not supported\n");
 373                                         return -EINVAL;
 374                                 }
 375
 376                                 advertising = (ADVERTISED_100baseT_Full |
 377                                                ADVERTISED_TP);
 378                         } else {
 379                                 if (!(bp->port.supported[cfg_idx] &
 380                                                 SUPPORTED_100baseT_Half)) {
 381                                         DP(NETIF_MSG_LINK,
 382                                            "100M half not supported\n");
 383                                         return -EINVAL;
 384                                 }
 385
 386                                 advertising = (ADVERTISED_100baseT_Half |
 387                                                ADVERTISED_TP);
 388                         }
 389                         break;
 390
 391                 case SPEED_1000:
 392                         if (cmd->duplex != DUPLEX_FULL) {
 393                                 DP(NETIF_MSG_LINK, "1G half not supported\n");
 394                                 return -EINVAL;
 395                         }
 396
 397                         if (!(bp->port.supported[cfg_idx] &
 398                               SUPPORTED_1000baseT_Full)) {
 399                                 DP(NETIF_MSG_LINK, "1G full not supported\n");
 400                                 return -EINVAL;
 401                         }
 402
 403                         advertising = (ADVERTISED_1000baseT_Full |
 404                                        ADVERTISED_TP);
 405                         break;
 406
 407                 case SPEED_2500:
 408                         if (cmd->duplex != DUPLEX_FULL) {
 409                                 DP(NETIF_MSG_LINK,
 410                                    "2.5G half not supported\n");
 411                                 return -EINVAL;
 412                         }
 413
 414                         if (!(bp->port.supported[cfg_idx]
 415                               & SUPPORTED_2500baseX_Full)) {
 416                                 DP(NETIF_MSG_LINK,
 417                                    "2.5G full not supported\n");
 418                                 return -EINVAL;
 419                         }
 420
 421                         advertising = (ADVERTISED_2500baseX_Full |
 422                                        ADVERTISED_TP);
 423                         break;
 424
 425                 case SPEED_10000:
 426                         if (cmd->duplex != DUPLEX_FULL) {
 427                                 DP(NETIF_MSG_LINK, "10G half not supported\n");
 428                                 return -EINVAL;
 429                         }
 430
 431                         if (!(bp->port.supported[cfg_idx]
 432                               & SUPPORTED_10000baseT_Full)) {
 433                                 DP(NETIF_MSG_LINK, "10G full not supported\n");
 434                                 return -EINVAL;
 435                         }
 436
 437                         advertising = (ADVERTISED_10000baseT_Full |
 438                                        ADVERTISED_FIBRE);
 439                         break;
 440
 441                 default:
 442                         DP(NETIF_MSG_LINK, "Unsupported speed %d\n", speed);
 443                         return -EINVAL;
 444                 }
 445
 446                 bp->link_params.req_line_speed[cfg_idx] = speed;
 447                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 448                 bp->port.advertising[cfg_idx] = advertising;
 449         }
 450
 451         DP(NETIF_MSG_LINK, "req_line_speed %d\n"
 452            DP_LEVEL "  req_duplex %d  advertising 0x%x\n",
 453            bp->link_params.req_line_speed[cfg_idx],
 454            bp->link_params.req_duplex[cfg_idx],
 455            bp->port.advertising[cfg_idx]);
 456
 457         /* Set new config */
 458         bp->link_params.multi_phy_config = new_multi_phy_config;
 459         if (netif_running(dev)) {
 460                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 461                 bnx2x_link_set(bp);
 462         }
 463
 464         return 0;
 465 }
 466
 467 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 468 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 469 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 470
 471 static int bnx2x_get_regs_len(struct net_device *dev)
 472 {
 473         struct bnx2x *bp = netdev_priv(dev);
 474         int regdump_len = 0;
 475         int i, j, k;
 476
 477         if (CHIP_IS_E1(bp)) {
 478                 for (i = 0; i < REGS_COUNT; i++)
 479                         if (IS_E1_ONLINE(reg_addrs[i].info))
 480                                 regdump_len += reg_addrs[i].size;
 481
 482                 for (i = 0; i < WREGS_COUNT_E1; i++)
 483                         if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
 484                                 regdump_len += wreg_addrs_e1[i].size *
 485                                         (1 + wreg_addrs_e1[i].read_regs_count);
 486
 487         } else if (CHIP_IS_E1H(bp)) {
 488                 for (i = 0; i < REGS_COUNT; i++)
 489                         if (IS_E1H_ONLINE(reg_addrs[i].info))
 490                                 regdump_len += reg_addrs[i].size;
 491
 492                 for (i = 0; i < WREGS_COUNT_E1H; i++)
 493                         if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
 494                                 regdump_len += wreg_addrs_e1h[i].size *
 495                                         (1 + wreg_addrs_e1h[i].read_regs_count);
 496         } else if (CHIP_IS_E2(bp)) {
 497                 for (i = 0; i < REGS_COUNT; i++)
 498                         if (IS_E2_ONLINE(reg_addrs[i].info))
 499                                 regdump_len += reg_addrs[i].size;
 500
 501                 for (i = 0; i < WREGS_COUNT_E2; i++)
 502                         if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
 503                                 regdump_len += wreg_addrs_e2[i].size *
 504                                         (1 + wreg_addrs_e2[i].read_regs_count);
 505
 506                 for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
 507                         for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
 508                                 for (k = 0; k < PAGE_READ_REGS_E2; k++)
 509                                         if (IS_E2_ONLINE(page_read_regs_e2[k].
 510                                                          info))
 511                                                 regdump_len +=
 512                                                 page_read_regs_e2[k].size;
 513                         }
 514         }
 515         regdump_len *= 4;
 516         regdump_len += sizeof(struct dump_hdr);
 517
 518         return regdump_len;
 519 }
 520
 521 static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
 522 {
 523         u32 i, j, k, n;
 524
 525         for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
 526                 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
 527                         REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
 528                         for (k = 0; k < PAGE_READ_REGS_E2; k++)
 529                                 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
 530                                         for (n = 0; n <
 531                                               page_read_regs_e2[k].size; n++)
 532                                                 *p++ = REG_RD(bp,
 533                                         page_read_regs_e2[k].addr + n*4);
 534                 }
 535         }
 536 }
 537
 538 static void bnx2x_get_regs(struct net_device *dev,
 539                            struct ethtool_regs *regs, void *_p)
 540 {
 541         u32 *p = _p, i, j;
 542         struct bnx2x *bp = netdev_priv(dev);
 543         struct dump_hdr dump_hdr = {0};
 544
 545         regs->version = 0;
 546         memset(p, 0, regs->len);
 547
 548         if (!netif_running(bp->dev))
 549                 return;
 550
 551         /* Disable parity attentions as long as following dump may
 552          * cause false alarms by reading never written registers. We
 553          * will re-enable parity attentions right after the dump.
 554          */
 555         bnx2x_disable_blocks_parity(bp);
 556
 557         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 558         dump_hdr.dump_sign = dump_sign_all;
 559         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 560         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 561         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 562         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 563
 564         if (CHIP_IS_E1(bp))
 565                 dump_hdr.info = RI_E1_ONLINE;
 566         else if (CHIP_IS_E1H(bp))
 567                 dump_hdr.info = RI_E1H_ONLINE;
 568         else if (CHIP_IS_E2(bp))
 569                 dump_hdr.info = RI_E2_ONLINE |
 570                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 571
 572         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 573         p += dump_hdr.hdr_size + 1;
 574
 575         if (CHIP_IS_E1(bp)) {
 576                 for (i = 0; i < REGS_COUNT; i++)
 577                         if (IS_E1_ONLINE(reg_addrs[i].info))
 578                                 for (j = 0; j < reg_addrs[i].size; j++)
 579                                         *p++ = REG_RD(bp,
 580                                                       reg_addrs[i].addr + j*4);
 581
 582         } else if (CHIP_IS_E1H(bp)) {
 583                 for (i = 0; i < REGS_COUNT; i++)
 584                         if (IS_E1H_ONLINE(reg_addrs[i].info))
 585                                 for (j = 0; j < reg_addrs[i].size; j++)
 586                                         *p++ = REG_RD(bp,
 587                                                       reg_addrs[i].addr + j*4);
 588
 589         } else if (CHIP_IS_E2(bp)) {
 590                 for (i = 0; i < REGS_COUNT; i++)
 591                         if (IS_E2_ONLINE(reg_addrs[i].info))
 592                                 for (j = 0; j < reg_addrs[i].size; j++)
 593                                         *p++ = REG_RD(bp,
 594                                               reg_addrs[i].addr + j*4);
 595
 596                 bnx2x_read_pages_regs_e2(bp, p);
 597         }
 598         /* Re-enable parity attentions */
 599         bnx2x_clear_blocks_parity(bp);
 600         if (CHIP_PARITY_ENABLED(bp))
 601                 bnx2x_enable_blocks_parity(bp);
 602 }
 603
 604 #define PHY_FW_VER_LEN                  20
 605
 606 static void bnx2x_get_drvinfo(struct net_device *dev,
 607                               struct ethtool_drvinfo *info)
 608 {
 609         struct bnx2x *bp = netdev_priv(dev);
 610         u8 phy_fw_ver[PHY_FW_VER_LEN];
 611
 612         strcpy(info->driver, DRV_MODULE_NAME);
 613         strcpy(info->version, DRV_MODULE_VERSION);
 614
 615         phy_fw_ver[0] = '\0';
 616         if (bp->port.pmf) {
 617                 bnx2x_acquire_phy_lock(bp);
 618                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
 619                                              (bp->state != BNX2X_STATE_CLOSED),
 620                                              phy_fw_ver, PHY_FW_VER_LEN);
 621                 bnx2x_release_phy_lock(bp);
 622         }
 623
 624         strncpy(info->fw_version, bp->fw_ver, 32);
 625         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 626                  "bc %d.%d.%d%s%s",
 627                  (bp->common.bc_ver & 0xff0000) >> 16,
 628                  (bp->common.bc_ver & 0xff00) >> 8,
 629                  (bp->common.bc_ver & 0xff),
 630                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 631         strcpy(info->bus_info, pci_name(bp->pdev));
 632         info->n_stats = BNX2X_NUM_STATS;
 633         info->testinfo_len = BNX2X_NUM_TESTS;
 634         info->eedump_len = bp->common.flash_size;
 635         info->regdump_len = bnx2x_get_regs_len(dev);
 636 }
 637
 638 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 639 {
 640         struct bnx2x *bp = netdev_priv(dev);
 641
 642         if (bp->flags & NO_WOL_FLAG) {
 643                 wol->supported = 0;
 644                 wol->wolopts = 0;
 645         } else {
 646                 wol->supported = WAKE_MAGIC;
 647                 if (bp->wol)
 648                         wol->wolopts = WAKE_MAGIC;
 649                 else
 650                         wol->wolopts = 0;
 651         }
 652         memset(&wol->sopass, 0, sizeof(wol->sopass));
 653 }
 654
 655 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 656 {
 657         struct bnx2x *bp = netdev_priv(dev);
 658
 659         if (wol->wolopts & ~WAKE_MAGIC)
 660                 return -EINVAL;
 661
 662         if (wol->wolopts & WAKE_MAGIC) {
 663                 if (bp->flags & NO_WOL_FLAG)
 664                         return -EINVAL;
 665
 666                 bp->wol = 1;
 667         } else
 668                 bp->wol = 0;
 669
 670         return 0;
 671 }
 672
 673 static u32 bnx2x_get_msglevel(struct net_device *dev)
 674 {
 675         struct bnx2x *bp = netdev_priv(dev);
 676
 677         return bp->msg_enable;
 678 }
 679
 680 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 681 {
 682         struct bnx2x *bp = netdev_priv(dev);
 683
 684         if (capable(CAP_NET_ADMIN))
 685                 bp->msg_enable = level;
 686 }
 687
 688 static int bnx2x_nway_reset(struct net_device *dev)
 689 {
 690         struct bnx2x *bp = netdev_priv(dev);
 691
 692         if (!bp->port.pmf)
 693                 return 0;
 694
 695         if (netif_running(dev)) {
 696                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 697                 bnx2x_link_set(bp);
 698         }
 699
 700         return 0;
 701 }
 702
 703 static u32 bnx2x_get_link(struct net_device *dev)
 704 {
 705         struct bnx2x *bp = netdev_priv(dev);
 706
 707         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 708                 return 0;
 709
 710         return bp->link_vars.link_up;
 711 }
 712
 713 static int bnx2x_get_eeprom_len(struct net_device *dev)
 714 {
 715         struct bnx2x *bp = netdev_priv(dev);
 716
 717         return bp->common.flash_size;
 718 }
 719
 720 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 721 {
 722         int port = BP_PORT(bp);
 723         int count, i;
 724         u32 val = 0;
 725
 726         /* adjust timeout for emulation/FPGA */
 727         count = NVRAM_TIMEOUT_COUNT;
 728         if (CHIP_REV_IS_SLOW(bp))
 729                 count *= 100;
 730
 731         /* request access to nvram interface */
 732         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 733                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 734
 735         for (i = 0; i < count*10; i++) {
 736                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 737                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 738                         break;
 739
 740                 udelay(5);
 741         }
 742
 743         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 744                 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
 745                 return -EBUSY;
 746         }
 747
 748         return 0;
 749 }
 750
 751 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 752 {
 753         int port = BP_PORT(bp);
 754         int count, i;
 755         u32 val = 0;
 756
 757         /* adjust timeout for emulation/FPGA */
 758         count = NVRAM_TIMEOUT_COUNT;
 759         if (CHIP_REV_IS_SLOW(bp))
 760                 count *= 100;
 761
 762         /* relinquish nvram interface */
 763         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 764                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 765
 766         for (i = 0; i < count*10; i++) {
 767                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 768                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 769                         break;
 770
 771                 udelay(5);
 772         }
 773
 774         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
 775                 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
 776                 return -EBUSY;
 777         }
 778
 779         return 0;
 780 }
 781
 782 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
 783 {
 784         u32 val;
 785
 786         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 787
 788         /* enable both bits, even on read */
 789         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 790                (val | MCPR_NVM_ACCESS_ENABLE_EN |
 791                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
 792 }
 793
 794 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
 795 {
 796         u32 val;
 797
 798         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 799
 800         /* disable both bits, even after read */
 801         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 802                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
 803                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
 804 }
 805
 806 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
 807                                   u32 cmd_flags)
 808 {
 809         int count, i, rc;
 810         u32 val;
 811
 812         /* build the command word */
 813         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
 814
 815         /* need to clear DONE bit separately */
 816         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 817
 818         /* address of the NVRAM to read from */
 819         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 820                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 821
 822         /* issue a read command */
 823         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 824
 825         /* adjust timeout for emulation/FPGA */
 826         count = NVRAM_TIMEOUT_COUNT;
 827         if (CHIP_REV_IS_SLOW(bp))
 828                 count *= 100;
 829
 830         /* wait for completion */
 831         *ret_val = 0;
 832         rc = -EBUSY;
 833         for (i = 0; i < count; i++) {
 834                 udelay(5);
 835                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 836
 837                 if (val & MCPR_NVM_COMMAND_DONE) {
 838                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
 839                         /* we read nvram data in cpu order
 840                          * but ethtool sees it as an array of bytes
 841                          * converting to big-endian will do the work */
 842                         *ret_val = cpu_to_be32(val);
 843                         rc = 0;
 844                         break;
 845                 }
 846         }
 847
 848         return rc;
 849 }
 850
 851 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
 852                             int buf_size)
 853 {
 854         int rc;
 855         u32 cmd_flags;
 856         __be32 val;
 857
 858         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
 859                 DP(BNX2X_MSG_NVM,
 860                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
 861                    offset, buf_size);
 862                 return -EINVAL;
 863         }
 864
 865         if (offset + buf_size > bp->common.flash_size) {
 866                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
 867                                   " buf_size (0x%x) > flash_size (0x%x)\n",
 868                    offset, buf_size, bp->common.flash_size);
 869                 return -EINVAL;
 870         }
 871
 872         /* request access to nvram interface */
 873         rc = bnx2x_acquire_nvram_lock(bp);
 874         if (rc)
 875                 return rc;
 876
 877         /* enable access to nvram interface */
 878         bnx2x_enable_nvram_access(bp);
 879
 880         /* read the first word(s) */
 881         cmd_flags = MCPR_NVM_COMMAND_FIRST;
 882         while ((buf_size > sizeof(u32)) && (rc == 0)) {
 883                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
 884                 memcpy(ret_buf, &val, 4);
 885
 886                 /* advance to the next dword */
 887                 offset += sizeof(u32);
 888                 ret_buf += sizeof(u32);
 889                 buf_size -= sizeof(u32);
 890                 cmd_flags = 0;
 891         }
 892
 893         if (rc == 0) {
 894                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
 895                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
 896                 memcpy(ret_buf, &val, 4);
 897         }
 898
 899         /* disable access to nvram interface */
 900         bnx2x_disable_nvram_access(bp);
 901         bnx2x_release_nvram_lock(bp);
 902
 903         return rc;
 904 }
 905
 906 static int bnx2x_get_eeprom(struct net_device *dev,
 907                             struct ethtool_eeprom *eeprom, u8 *eebuf)
 908 {
 909         struct bnx2x *bp = netdev_priv(dev);
 910         int rc;
 911
 912         if (!netif_running(dev))
 913                 return -EAGAIN;
 914
 915         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
 916            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
 917            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
 918            eeprom->len, eeprom->len);
 919
 920         /* parameters already validated in ethtool_get_eeprom */
 921
 922         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
 923
 924         return rc;
 925 }
 926
 927 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
 928                                    u32 cmd_flags)
 929 {
 930         int count, i, rc;
 931
 932         /* build the command word */
 933         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
 934
 935         /* need to clear DONE bit separately */
 936         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 937
 938         /* write the data */
 939         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
 940
 941         /* address of the NVRAM to write to */
 942         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 943                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 944
 945         /* issue the write command */
 946         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 947
 948         /* adjust timeout for emulation/FPGA */
 949         count = NVRAM_TIMEOUT_COUNT;
 950         if (CHIP_REV_IS_SLOW(bp))
 951                 count *= 100;
 952
 953         /* wait for completion */
 954         rc = -EBUSY;
 955         for (i = 0; i < count; i++) {
 956                 udelay(5);
 957                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 958                 if (val & MCPR_NVM_COMMAND_DONE) {
 959                         rc = 0;
 960                         break;
 961                 }
 962         }
 963
 964         return rc;
 965 }
 966
 967 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
 968
 969 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
 970                               int buf_size)
 971 {
 972         int rc;
 973         u32 cmd_flags;
 974         u32 align_offset;
 975         __be32 val;
 976
 977         if (offset + buf_size > bp->common.flash_size) {
 978                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
 979                                   " buf_size (0x%x) > flash_size (0x%x)\n",
 980                    offset, buf_size, bp->common.flash_size);
 981                 return -EINVAL;
 982         }
 983
 984         /* request access to nvram interface */
 985         rc = bnx2x_acquire_nvram_lock(bp);
 986         if (rc)
 987                 return rc;
 988
 989         /* enable access to nvram interface */
 990         bnx2x_enable_nvram_access(bp);
 991
 992         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
 993         align_offset = (offset & ~0x03);
 994         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
 995
 996         if (rc == 0) {
 997                 val &= ~(0xff << BYTE_OFFSET(offset));
 998                 val |= (*data_buf << BYTE_OFFSET(offset));
 999
1000                 /* nvram data is returned as an array of bytes
1001                  * convert it back to cpu order */
1002                 val = be32_to_cpu(val);
1003
1004                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1005                                              cmd_flags);
1006         }
1007
1008         /* disable access to nvram interface */
1009         bnx2x_disable_nvram_access(bp);
1010         bnx2x_release_nvram_lock(bp);
1011
1012         return rc;
1013 }
1014
1015 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1016                              int buf_size)
1017 {
1018         int rc;
1019         u32 cmd_flags;
1020         u32 val;
1021         u32 written_so_far;
1022
1023         if (buf_size == 1)      /* ethtool */
1024                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1025
1026         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1027                 DP(BNX2X_MSG_NVM,
1028                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1029                    offset, buf_size);
1030                 return -EINVAL;
1031         }
1032
1033         if (offset + buf_size > bp->common.flash_size) {
1034                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1035                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1036                    offset, buf_size, bp->common.flash_size);
1037                 return -EINVAL;
1038         }
1039
1040         /* request access to nvram interface */
1041         rc = bnx2x_acquire_nvram_lock(bp);
1042         if (rc)
1043                 return rc;
1044
1045         /* enable access to nvram interface */
1046         bnx2x_enable_nvram_access(bp);
1047
1048         written_so_far = 0;
1049         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1050         while ((written_so_far < buf_size) && (rc == 0)) {
1051                 if (written_so_far == (buf_size - sizeof(u32)))
1052                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1053                 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
1054                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1055                 else if ((offset % NVRAM_PAGE_SIZE) == 0)
1056                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1057
1058                 memcpy(&val, data_buf, 4);
1059
1060                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1061
1062                 /* advance to the next dword */
1063                 offset += sizeof(u32);
1064                 data_buf += sizeof(u32);
1065                 written_so_far += sizeof(u32);
1066                 cmd_flags = 0;
1067         }
1068
1069         /* disable access to nvram interface */
1070         bnx2x_disable_nvram_access(bp);
1071         bnx2x_release_nvram_lock(bp);
1072
1073         return rc;
1074 }
1075
1076 static int bnx2x_set_eeprom(struct net_device *dev,
1077                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1078 {
1079         struct bnx2x *bp = netdev_priv(dev);
1080         int port = BP_PORT(bp);
1081         int rc = 0;
1082         u32 ext_phy_config;
1083         if (!netif_running(dev))
1084                 return -EAGAIN;
1085
1086         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1087            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1088            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1089            eeprom->len, eeprom->len);
1090
1091         /* parameters already validated in ethtool_set_eeprom */
1092
1093         /* PHY eeprom can be accessed only by the PMF */
1094         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1095             !bp->port.pmf)
1096                 return -EINVAL;
1097
1098         ext_phy_config =
1099                 SHMEM_RD(bp,
1100                          dev_info.port_hw_config[port].external_phy_config);
1101
1102         if (eeprom->magic == 0x50485950) {
1103                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1104                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1105
1106                 bnx2x_acquire_phy_lock(bp);
1107                 rc |= bnx2x_link_reset(&bp->link_params,
1108                                        &bp->link_vars, 0);
1109                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1110                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1111                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1112                                        MISC_REGISTERS_GPIO_HIGH, port);
1113                 bnx2x_release_phy_lock(bp);
1114                 bnx2x_link_report(bp);
1115
1116         } else if (eeprom->magic == 0x50485952) {
1117                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1118                 if (bp->state == BNX2X_STATE_OPEN) {
1119                         bnx2x_acquire_phy_lock(bp);
1120                         rc |= bnx2x_link_reset(&bp->link_params,
1121                                                &bp->link_vars, 1);
1122
1123                         rc |= bnx2x_phy_init(&bp->link_params,
1124                                              &bp->link_vars);
1125                         bnx2x_release_phy_lock(bp);
1126                         bnx2x_calc_fc_adv(bp);
1127                 }
1128         } else if (eeprom->magic == 0x53985943) {
1129                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1130                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1131                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1132
1133                         /* DSP Remove Download Mode */
1134                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1135                                        MISC_REGISTERS_GPIO_LOW, port);
1136
1137                         bnx2x_acquire_phy_lock(bp);
1138
1139                         bnx2x_sfx7101_sp_sw_reset(bp,
1140                                                 &bp->link_params.phy[EXT_PHY1]);
1141
1142                         /* wait 0.5 sec to allow it to run */
1143                         msleep(500);
1144                         bnx2x_ext_phy_hw_reset(bp, port);
1145                         msleep(500);
1146                         bnx2x_release_phy_lock(bp);
1147                 }
1148         } else
1149                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1150
1151         return rc;
1152 }
1153
1154 static int bnx2x_get_coalesce(struct net_device *dev,
1155                               struct ethtool_coalesce *coal)
1156 {
1157         struct bnx2x *bp = netdev_priv(dev);
1158
1159         memset(coal, 0, sizeof(struct ethtool_coalesce));
1160
1161         coal->rx_coalesce_usecs = bp->rx_ticks;
1162         coal->tx_coalesce_usecs = bp->tx_ticks;
1163
1164         return 0;
1165 }
1166
1167 static int bnx2x_set_coalesce(struct net_device *dev,
1168                               struct ethtool_coalesce *coal)
1169 {
1170         struct bnx2x *bp = netdev_priv(dev);
1171
1172         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1173         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1174                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1175
1176         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1177         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1178                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1179
1180         if (netif_running(dev))
1181                 bnx2x_update_coalesce(bp);
1182
1183         return 0;
1184 }
1185
1186 static void bnx2x_get_ringparam(struct net_device *dev,
1187                                 struct ethtool_ringparam *ering)
1188 {
1189         struct bnx2x *bp = netdev_priv(dev);
1190
1191         ering->rx_max_pending = MAX_RX_AVAIL;
1192         ering->rx_mini_max_pending = 0;
1193         ering->rx_jumbo_max_pending = 0;
1194
1195         if (bp->rx_ring_size)
1196                 ering->rx_pending = bp->rx_ring_size;
1197         else
1198                 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1199                         ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1200                 else
1201                         ering->rx_pending = MAX_RX_AVAIL;
1202
1203         ering->rx_mini_pending = 0;
1204         ering->rx_jumbo_pending = 0;
1205
1206         ering->tx_max_pending = MAX_TX_AVAIL;
1207         ering->tx_pending = bp->tx_ring_size;
1208 }
1209
1210 static int bnx2x_set_ringparam(struct net_device *dev,
1211                                struct ethtool_ringparam *ering)
1212 {
1213         struct bnx2x *bp = netdev_priv(dev);
1214         int rc = 0;
1215
1216         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1217                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1218                 return -EAGAIN;
1219         }
1220
1221         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1222             (ering->rx_pending < MIN_RX_AVAIL) ||
1223             (ering->tx_pending > MAX_TX_AVAIL) ||
1224             (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1225                 return -EINVAL;
1226
1227         bp->rx_ring_size = ering->rx_pending;
1228         bp->tx_ring_size = ering->tx_pending;
1229
1230         if (netif_running(dev)) {
1231                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1232                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1233         }
1234
1235         return rc;
1236 }
1237
1238 static void bnx2x_get_pauseparam(struct net_device *dev,
1239                                  struct ethtool_pauseparam *epause)
1240 {
1241         struct bnx2x *bp = netdev_priv(dev);
1242         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1243         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1244                            BNX2X_FLOW_CTRL_AUTO);
1245
1246         epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1247                             BNX2X_FLOW_CTRL_RX);
1248         epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1249                             BNX2X_FLOW_CTRL_TX);
1250
1251         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1252            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
1253            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1254 }
1255
1256 static int bnx2x_set_pauseparam(struct net_device *dev,
1257                                 struct ethtool_pauseparam *epause)
1258 {
1259         struct bnx2x *bp = netdev_priv(dev);
1260         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1261         if (IS_MF(bp))
1262                 return 0;
1263
1264         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1265            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
1266            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1267
1268         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1269
1270         if (epause->rx_pause)
1271                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1272
1273         if (epause->tx_pause)
1274                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1275
1276         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1277                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1278
1279         if (epause->autoneg) {
1280                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1281                         DP(NETIF_MSG_LINK, "autoneg not supported\n");
1282                         return -EINVAL;
1283                 }
1284
1285                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1286                         bp->link_params.req_flow_ctrl[cfg_idx] =
1287                                 BNX2X_FLOW_CTRL_AUTO;
1288                 }
1289         }
1290
1291         DP(NETIF_MSG_LINK,
1292            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1293
1294         if (netif_running(dev)) {
1295                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1296                 bnx2x_link_set(bp);
1297         }
1298
1299         return 0;
1300 }
1301
1302 static int bnx2x_set_flags(struct net_device *dev, u32 data)
1303 {
1304         struct bnx2x *bp = netdev_priv(dev);
1305         int changed = 0;
1306         int rc = 0;
1307
1308         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1309                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1310                 return -EAGAIN;
1311         }
1312
1313         if (!(data & ETH_FLAG_RXVLAN))
1314                 return -EINVAL;
1315
1316         if ((data & ETH_FLAG_LRO) && bp->rx_csum && bp->disable_tpa)
1317                 return -EINVAL;
1318
1319         rc = ethtool_op_set_flags(dev, data, ETH_FLAG_LRO | ETH_FLAG_RXVLAN |
1320                                         ETH_FLAG_TXVLAN | ETH_FLAG_RXHASH);
1321         if (rc)
1322                 return rc;
1323
1324         /* TPA requires Rx CSUM offloading */
1325         if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
1326                 if (!(bp->flags & TPA_ENABLE_FLAG)) {
1327                         bp->flags |= TPA_ENABLE_FLAG;
1328                         changed = 1;
1329                 }
1330         } else if (bp->flags & TPA_ENABLE_FLAG) {
1331                 dev->features &= ~NETIF_F_LRO;
1332                 bp->flags &= ~TPA_ENABLE_FLAG;
1333                 changed = 1;
1334         }
1335
1336         if (changed && netif_running(dev)) {
1337                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1338                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1339         }
1340
1341         return rc;
1342 }
1343
1344 static u32 bnx2x_get_rx_csum(struct net_device *dev)
1345 {
1346         struct bnx2x *bp = netdev_priv(dev);
1347
1348         return bp->rx_csum;
1349 }
1350
1351 static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
1352 {
1353         struct bnx2x *bp = netdev_priv(dev);
1354         int rc = 0;
1355
1356         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1357                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1358                 return -EAGAIN;
1359         }
1360
1361         bp->rx_csum = data;
1362
1363         /* Disable TPA, when Rx CSUM is disabled. Otherwise all
1364            TPA'ed packets will be discarded due to wrong TCP CSUM */
1365         if (!data) {
1366                 u32 flags = ethtool_op_get_flags(dev);
1367
1368                 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
1369         }
1370
1371         return rc;
1372 }
1373
1374 static int bnx2x_set_tso(struct net_device *dev, u32 data)
1375 {
1376         if (data) {
1377                 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
1378                 dev->features |= NETIF_F_TSO6;
1379         } else {
1380                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
1381                 dev->features &= ~NETIF_F_TSO6;
1382         }
1383
1384         return 0;
1385 }
1386
1387 static const struct {
1388         char string[ETH_GSTRING_LEN];
1389 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1390         { "register_test (offline)" },
1391         { "memory_test (offline)" },
1392         { "loopback_test (offline)" },
1393         { "nvram_test (online)" },
1394         { "interrupt_test (online)" },
1395         { "link_test (online)" },
1396         { "idle check (online)" }
1397 };
1398
1399 static int bnx2x_test_registers(struct bnx2x *bp)
1400 {
1401         int idx, i, rc = -ENODEV;
1402         u32 wr_val = 0;
1403         int port = BP_PORT(bp);
1404         static const struct {
1405                 u32 offset0;
1406                 u32 offset1;
1407                 u32 mask;
1408         } reg_tbl[] = {
1409 /* 0 */         { BRB1_REG_PAUSE_LOW_THRESHOLD_0,      4, 0x000003ff },
1410                 { DORQ_REG_DB_ADDR0,                   4, 0xffffffff },
1411                 { HC_REG_AGG_INT_0,                    4, 0x000003ff },
1412                 { PBF_REG_MAC_IF0_ENABLE,              4, 0x00000001 },
1413                 { PBF_REG_P0_INIT_CRD,                 4, 0x000007ff },
1414                 { PRS_REG_CID_PORT_0,                  4, 0x00ffffff },
1415                 { PXP2_REG_PSWRQ_CDU0_L2P,             4, 0x000fffff },
1416                 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR,    8, 0x0003ffff },
1417                 { PXP2_REG_PSWRQ_TM0_L2P,              4, 0x000fffff },
1418                 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR,   8, 0x0003ffff },
1419 /* 10 */        { PXP2_REG_PSWRQ_TSDM0_L2P,            4, 0x000fffff },
1420                 { QM_REG_CONNNUM_0,                    4, 0x000fffff },
1421                 { TM_REG_LIN0_MAX_ACTIVE_CID,          4, 0x0003ffff },
1422                 { SRC_REG_KEYRSS0_0,                  40, 0xffffffff },
1423                 { SRC_REG_KEYRSS0_7,                  40, 0xffffffff },
1424                 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1425                 { XCM_REG_WU_DA_CNT_CMD00,             4, 0x00000003 },
1426                 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0,       4, 0x000000ff },
1427                 { NIG_REG_LLH0_T_BIT,                  4, 0x00000001 },
1428                 { NIG_REG_EMAC0_IN_EN,                 4, 0x00000001 },
1429 /* 20 */        { NIG_REG_BMAC0_IN_EN,                 4, 0x00000001 },
1430                 { NIG_REG_XCM0_OUT_EN,                 4, 0x00000001 },
1431                 { NIG_REG_BRB0_OUT_EN,                 4, 0x00000001 },
1432                 { NIG_REG_LLH0_XCM_MASK,               4, 0x00000007 },
1433                 { NIG_REG_LLH0_ACPI_PAT_6_LEN,        68, 0x000000ff },
1434                 { NIG_REG_LLH0_ACPI_PAT_0_CRC,        68, 0xffffffff },
1435                 { NIG_REG_LLH0_DEST_MAC_0_0,         160, 0xffffffff },
1436                 { NIG_REG_LLH0_DEST_IP_0_1,          160, 0xffffffff },
1437                 { NIG_REG_LLH0_IPV4_IPV6_0,          160, 0x00000001 },
1438                 { NIG_REG_LLH0_DEST_UDP_0,           160, 0x0000ffff },
1439 /* 30 */        { NIG_REG_LLH0_DEST_TCP_0,           160, 0x0000ffff },
1440                 { NIG_REG_LLH0_VLAN_ID_0,            160, 0x00000fff },
1441                 { NIG_REG_XGXS_SERDES0_MODE_SEL,       4, 0x00000001 },
1442                 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1443                 { NIG_REG_STATUS_INTERRUPT_PORT0,      4, 0x07ffffff },
1444                 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1445                 { NIG_REG_SERDES0_CTRL_PHY_ADDR,      16, 0x0000001f },
1446
1447                 { 0xffffffff, 0, 0x00000000 }
1448         };
1449
1450         if (!netif_running(bp->dev))
1451                 return rc;
1452
1453         /* Repeat the test twice:
1454            First by writing 0x00000000, second by writing 0xffffffff */
1455         for (idx = 0; idx < 2; idx++) {
1456
1457                 switch (idx) {
1458                 case 0:
1459                         wr_val = 0;
1460                         break;
1461                 case 1:
1462                         wr_val = 0xffffffff;
1463                         break;
1464                 }
1465
1466                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1467                         u32 offset, mask, save_val, val;
1468                         if (CHIP_IS_E2(bp) &&
1469                             reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1470                                 continue;
1471
1472                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1473                         mask = reg_tbl[i].mask;
1474
1475                         save_val = REG_RD(bp, offset);
1476
1477                         REG_WR(bp, offset, wr_val & mask);
1478
1479                         val = REG_RD(bp, offset);
1480
1481                         /* Restore the original register's value */
1482                         REG_WR(bp, offset, save_val);
1483
1484                         /* verify value is as expected */
1485                         if ((val & mask) != (wr_val & mask)) {
1486                                 DP(NETIF_MSG_PROBE,
1487                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1488                                    offset, val, wr_val, mask);
1489                                 goto test_reg_exit;
1490                         }
1491                 }
1492         }
1493
1494         rc = 0;
1495
1496 test_reg_exit:
1497         return rc;
1498 }
1499
1500 static int bnx2x_test_memory(struct bnx2x *bp)
1501 {
1502         int i, j, rc = -ENODEV;
1503         u32 val;
1504         static const struct {
1505                 u32 offset;
1506                 int size;
1507         } mem_tbl[] = {
1508                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1509                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1510                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1511                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1512                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1513                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1514                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1515
1516                 { 0xffffffff, 0 }
1517         };
1518         static const struct {
1519                 char *name;
1520                 u32 offset;
1521                 u32 e1_mask;
1522                 u32 e1h_mask;
1523                 u32 e2_mask;
1524         } prty_tbl[] = {
1525                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,   0x3ffc0, 0,   0 },
1526                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,   0x2,     0x2, 0 },
1527                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0,       0,   0 },
1528                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,   0x3ffc0, 0,   0 },
1529                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,   0x3ffc0, 0,   0 },
1530                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,   0x3ffc1, 0,   0 },
1531
1532                 { NULL, 0xffffffff, 0, 0, 0 }
1533         };
1534
1535         if (!netif_running(bp->dev))
1536                 return rc;
1537
1538         /* pre-Check the parity status */
1539         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1540                 val = REG_RD(bp, prty_tbl[i].offset);
1541                 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1542                     (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1543                     (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1544                         DP(NETIF_MSG_HW,
1545                            "%s is 0x%x\n", prty_tbl[i].name, val);
1546                         goto test_mem_exit;
1547                 }
1548         }
1549
1550         /* Go through all the memories */
1551         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1552                 for (j = 0; j < mem_tbl[i].size; j++)
1553                         REG_RD(bp, mem_tbl[i].offset + j*4);
1554
1555         /* Check the parity status */
1556         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1557                 val = REG_RD(bp, prty_tbl[i].offset);
1558                 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1559                     (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1560                     (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1561                         DP(NETIF_MSG_HW,
1562                            "%s is 0x%x\n", prty_tbl[i].name, val);
1563                         goto test_mem_exit;
1564                 }
1565         }
1566
1567         rc = 0;
1568
1569 test_mem_exit:
1570         return rc;
1571 }
1572
1573 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1574 {
1575         int cnt = 1400;
1576
1577         if (link_up)
1578                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1579                         msleep(10);
1580 }
1581
1582 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1583 {
1584         unsigned int pkt_size, num_pkts, i;
1585         struct sk_buff *skb;
1586         unsigned char *packet;
1587         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1588         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1589         u16 tx_start_idx, tx_idx;
1590         u16 rx_start_idx, rx_idx;
1591         u16 pkt_prod, bd_prod;
1592         struct sw_tx_bd *tx_buf;
1593         struct eth_tx_start_bd *tx_start_bd;
1594         struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
1595         struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
1596         dma_addr_t mapping;
1597         union eth_rx_cqe *cqe;
1598         u8 cqe_fp_flags;
1599         struct sw_rx_bd *rx_buf;
1600         u16 len;
1601         int rc = -ENODEV;
1602
1603         /* check the loopback mode */
1604         switch (loopback_mode) {
1605         case BNX2X_PHY_LOOPBACK:
1606                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1607                         return -EINVAL;
1608                 break;
1609         case BNX2X_MAC_LOOPBACK:
1610                 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1611                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1612                 break;
1613         default:
1614                 return -EINVAL;
1615         }
1616
1617         /* prepare the loopback packet */
1618         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1619                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1620         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1621         if (!skb) {
1622                 rc = -ENOMEM;
1623                 goto test_loopback_exit;
1624         }
1625         packet = skb_put(skb, pkt_size);
1626         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1627         memset(packet + ETH_ALEN, 0, ETH_ALEN);
1628         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1629         for (i = ETH_HLEN; i < pkt_size; i++)
1630                 packet[i] = (unsigned char) (i & 0xff);
1631
1632         /* send the loopback packet */
1633         num_pkts = 0;
1634         tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1635         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1636
1637         pkt_prod = fp_tx->tx_pkt_prod++;
1638         tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1639         tx_buf->first_bd = fp_tx->tx_bd_prod;
1640         tx_buf->skb = skb;
1641         tx_buf->flags = 0;
1642
1643         bd_prod = TX_BD(fp_tx->tx_bd_prod);
1644         tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1645         mapping = dma_map_single(&bp->pdev->dev, skb->data,
1646                                  skb_headlen(skb), DMA_TO_DEVICE);
1647         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1648         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1649         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1650         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1651         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1652         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1653         SET_FLAG(tx_start_bd->general_data,
1654                  ETH_TX_START_BD_ETH_ADDR_TYPE,
1655                  UNICAST_ADDRESS);
1656         SET_FLAG(tx_start_bd->general_data,
1657                  ETH_TX_START_BD_HDR_NBDS,
1658                  1);
1659
1660         /* turn on parsing and get a BD */
1661         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1662
1663         pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
1664         pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
1665
1666         memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1667         memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1668
1669         wmb();
1670
1671         fp_tx->tx_db.data.prod += 2;
1672         barrier();
1673         DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1674
1675         mmiowb();
1676
1677         num_pkts++;
1678         fp_tx->tx_bd_prod += 2; /* start + pbd */
1679
1680         udelay(100);
1681
1682         tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1683         if (tx_idx != tx_start_idx + num_pkts)
1684                 goto test_loopback_exit;
1685
1686         /* Unlike HC IGU won't generate an interrupt for status block
1687          * updates that have been performed while interrupts were
1688          * disabled.
1689          */
1690         if (bp->common.int_block == INT_BLOCK_IGU) {
1691                 /* Disable local BHes to prevent a dead-lock situation between
1692                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
1693                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
1694                  */
1695                 local_bh_disable();
1696                 bnx2x_tx_int(fp_tx);
1697                 local_bh_enable();
1698         }
1699
1700         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1701         if (rx_idx != rx_start_idx + num_pkts)
1702                 goto test_loopback_exit;
1703
1704         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1705         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1706         if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1707                 goto test_loopback_rx_exit;
1708
1709         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1710         if (len != pkt_size)
1711                 goto test_loopback_rx_exit;
1712
1713         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1714         skb = rx_buf->skb;
1715         skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1716         for (i = ETH_HLEN; i < pkt_size; i++)
1717                 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1718                         goto test_loopback_rx_exit;
1719
1720         rc = 0;
1721
1722 test_loopback_rx_exit:
1723
1724         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1725         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1726         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1727         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1728
1729         /* Update producers */
1730         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1731                              fp_rx->rx_sge_prod);
1732
1733 test_loopback_exit:
1734         bp->link_params.loopback_mode = LOOPBACK_NONE;
1735
1736         return rc;
1737 }
1738
1739 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1740 {
1741         int rc = 0, res;
1742
1743         if (BP_NOMCP(bp))
1744                 return rc;
1745
1746         if (!netif_running(bp->dev))
1747                 return BNX2X_LOOPBACK_FAILED;
1748
1749         bnx2x_netif_stop(bp, 1);
1750         bnx2x_acquire_phy_lock(bp);
1751
1752         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1753         if (res) {
1754                 DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
1755                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1756         }
1757
1758         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1759         if (res) {
1760                 DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
1761                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1762         }
1763
1764         bnx2x_release_phy_lock(bp);
1765         bnx2x_netif_start(bp);
1766
1767         return rc;
1768 }
1769
1770 #define CRC32_RESIDUAL                  0xdebb20e3
1771
1772 static int bnx2x_test_nvram(struct bnx2x *bp)
1773 {
1774         static const struct {
1775                 int offset;
1776                 int size;
1777         } nvram_tbl[] = {
1778                 {     0,  0x14 }, /* bootstrap */
1779                 {  0x14,  0xec }, /* dir */
1780                 { 0x100, 0x350 }, /* manuf_info */
1781                 { 0x450,  0xf0 }, /* feature_info */
1782                 { 0x640,  0x64 }, /* upgrade_key_info */
1783                 { 0x708,  0x70 }, /* manuf_key_info */
1784                 {     0,     0 }
1785         };
1786         __be32 buf[0x350 / 4];
1787         u8 *data = (u8 *)buf;
1788         int i, rc;
1789         u32 magic, crc;
1790
1791         if (BP_NOMCP(bp))
1792                 return 0;
1793
1794         rc = bnx2x_nvram_read(bp, 0, data, 4);
1795         if (rc) {
1796                 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1797                 goto test_nvram_exit;
1798         }
1799
1800         magic = be32_to_cpu(buf[0]);
1801         if (magic != 0x669955aa) {
1802                 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1803                 rc = -ENODEV;
1804                 goto test_nvram_exit;
1805         }
1806
1807         for (i = 0; nvram_tbl[i].size; i++) {
1808
1809                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1810                                       nvram_tbl[i].size);
1811                 if (rc) {
1812                         DP(NETIF_MSG_PROBE,
1813                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1814                         goto test_nvram_exit;
1815                 }
1816
1817                 crc = ether_crc_le(nvram_tbl[i].size, data);
1818                 if (crc != CRC32_RESIDUAL) {
1819                         DP(NETIF_MSG_PROBE,
1820                            "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1821                         rc = -ENODEV;
1822                         goto test_nvram_exit;
1823                 }
1824         }
1825
1826 test_nvram_exit:
1827         return rc;
1828 }
1829
1830 static int bnx2x_test_intr(struct bnx2x *bp)
1831 {
1832         struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1833         int i, rc;
1834
1835         if (!netif_running(bp->dev))
1836                 return -ENODEV;
1837
1838         config->hdr.length = 0;
1839         if (CHIP_IS_E1(bp))
1840                 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
1841         else
1842                 config->hdr.offset = BP_FUNC(bp);
1843         config->hdr.client_id = bp->fp->cl_id;
1844         config->hdr.reserved1 = 0;
1845
1846         bp->set_mac_pending = 1;
1847         smp_wmb();
1848         rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
1849                            U64_HI(bnx2x_sp_mapping(bp, mac_config)),
1850                            U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
1851         if (rc == 0) {
1852                 for (i = 0; i < 10; i++) {
1853                         if (!bp->set_mac_pending)
1854                                 break;
1855                         smp_rmb();
1856                         msleep_interruptible(10);
1857                 }
1858                 if (i == 10)
1859                         rc = -ENODEV;
1860         }
1861
1862         return rc;
1863 }
1864
1865 static void bnx2x_self_test(struct net_device *dev,
1866                             struct ethtool_test *etest, u64 *buf)
1867 {
1868         struct bnx2x *bp = netdev_priv(dev);
1869         u8 is_serdes;
1870         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1871                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1872                 etest->flags |= ETH_TEST_FL_FAILED;
1873                 return;
1874         }
1875
1876         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1877
1878         if (!netif_running(dev))
1879                 return;
1880
1881         /* offline tests are not supported in MF mode */
1882         if (IS_MF(bp))
1883                 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1884         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
1885
1886         if (etest->flags & ETH_TEST_FL_OFFLINE) {
1887                 int port = BP_PORT(bp);
1888                 u32 val;
1889                 u8 link_up;
1890
1891                 /* save current value of input enable for TX port IF */
1892                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1893                 /* disable input for TX port IF */
1894                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1895
1896                 link_up = bp->link_vars.link_up;
1897
1898                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1899                 bnx2x_nic_load(bp, LOAD_DIAG);
1900                 /* wait until link state is restored */
1901                 bnx2x_wait_for_link(bp, link_up, is_serdes);
1902
1903                 if (bnx2x_test_registers(bp) != 0) {
1904                         buf[0] = 1;
1905                         etest->flags |= ETH_TEST_FL_FAILED;
1906                 }
1907                 if (bnx2x_test_memory(bp) != 0) {
1908                         buf[1] = 1;
1909                         etest->flags |= ETH_TEST_FL_FAILED;
1910                 }
1911
1912                 buf[2] = bnx2x_test_loopback(bp, link_up);
1913                 if (buf[2] != 0)
1914                         etest->flags |= ETH_TEST_FL_FAILED;
1915
1916                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1917
1918                 /* restore input for TX port IF */
1919                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1920
1921                 bnx2x_nic_load(bp, LOAD_NORMAL);
1922                 /* wait until link state is restored */
1923                 bnx2x_wait_for_link(bp, link_up, is_serdes);
1924         }
1925         if (bnx2x_test_nvram(bp) != 0) {
1926                 buf[3] = 1;
1927                 etest->flags |= ETH_TEST_FL_FAILED;
1928         }
1929         if (bnx2x_test_intr(bp) != 0) {
1930                 buf[4] = 1;
1931                 etest->flags |= ETH_TEST_FL_FAILED;
1932         }
1933
1934         if (bnx2x_link_test(bp, is_serdes) != 0) {
1935                 buf[5] = 1;
1936                 etest->flags |= ETH_TEST_FL_FAILED;
1937         }
1938
1939 #ifdef BNX2X_EXTRA_DEBUG
1940         bnx2x_panic_dump(bp);
1941 #endif
1942 }
1943
1944 #define IS_PORT_STAT(i) \
1945         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1946 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1947 #define IS_MF_MODE_STAT(bp) \
1948                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1949
1950 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1951 {
1952         struct bnx2x *bp = netdev_priv(dev);
1953         int i, num_stats;
1954
1955         switch (stringset) {
1956         case ETH_SS_STATS:
1957                 if (is_multi(bp)) {
1958                         num_stats = BNX2X_NUM_STAT_QUEUES(bp) *
1959                                 BNX2X_NUM_Q_STATS;
1960                         if (!IS_MF_MODE_STAT(bp))
1961                                 num_stats += BNX2X_NUM_STATS;
1962                 } else {
1963                         if (IS_MF_MODE_STAT(bp)) {
1964                                 num_stats = 0;
1965                                 for (i = 0; i < BNX2X_NUM_STATS; i++)
1966                                         if (IS_FUNC_STAT(i))
1967                                                 num_stats++;
1968                         } else
1969                                 num_stats = BNX2X_NUM_STATS;
1970                 }
1971                 return num_stats;
1972
1973         case ETH_SS_TEST:
1974                 return BNX2X_NUM_TESTS;
1975
1976         default:
1977                 return -EINVAL;
1978         }
1979 }
1980
1981 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1982 {
1983         struct bnx2x *bp = netdev_priv(dev);
1984         int i, j, k;
1985         char queue_name[MAX_QUEUE_NAME_LEN+1];
1986
1987         switch (stringset) {
1988         case ETH_SS_STATS:
1989                 if (is_multi(bp)) {
1990                         k = 0;
1991                         for_each_napi_queue(bp, i) {
1992                                 memset(queue_name, 0, sizeof(queue_name));
1993
1994                                 if (IS_FCOE_IDX(i))
1995                                         sprintf(queue_name, "fcoe");
1996                                 else
1997                                         sprintf(queue_name, "%d", i);
1998
1999                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
2000                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2001                                                 ETH_GSTRING_LEN,
2002                                                 bnx2x_q_stats_arr[j].string,
2003                                                 queue_name);
2004                                 k += BNX2X_NUM_Q_STATS;
2005                         }
2006                         if (IS_MF_MODE_STAT(bp))
2007                                 break;
2008                         for (j = 0; j < BNX2X_NUM_STATS; j++)
2009                                 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2010                                        bnx2x_stats_arr[j].string);
2011                 } else {
2012                         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2013                                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2014                                         continue;
2015                                 strcpy(buf + j*ETH_GSTRING_LEN,
2016                                        bnx2x_stats_arr[i].string);
2017                                 j++;
2018                         }
2019                 }
2020                 break;
2021
2022         case ETH_SS_TEST:
2023                 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2024                 break;
2025         }
2026 }
2027
2028 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2029                                     struct ethtool_stats *stats, u64 *buf)
2030 {
2031         struct bnx2x *bp = netdev_priv(dev);
2032         u32 *hw_stats, *offset;
2033         int i, j, k;
2034
2035         if (is_multi(bp)) {
2036                 k = 0;
2037                 for_each_napi_queue(bp, i) {
2038                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2039                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2040                                 if (bnx2x_q_stats_arr[j].size == 0) {
2041                                         /* skip this counter */
2042                                         buf[k + j] = 0;
2043                                         continue;
2044                                 }
2045                                 offset = (hw_stats +
2046                                           bnx2x_q_stats_arr[j].offset);
2047                                 if (bnx2x_q_stats_arr[j].size == 4) {
2048                                         /* 4-byte counter */
2049                                         buf[k + j] = (u64) *offset;
2050                                         continue;
2051                                 }
2052                                 /* 8-byte counter */
2053                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2054                         }
2055                         k += BNX2X_NUM_Q_STATS;
2056                 }
2057                 if (IS_MF_MODE_STAT(bp))
2058                         return;
2059                 hw_stats = (u32 *)&bp->eth_stats;
2060                 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2061                         if (bnx2x_stats_arr[j].size == 0) {
2062                                 /* skip this counter */
2063                                 buf[k + j] = 0;
2064                                 continue;
2065                         }
2066                         offset = (hw_stats + bnx2x_stats_arr[j].offset);
2067                         if (bnx2x_stats_arr[j].size == 4) {
2068                                 /* 4-byte counter */
2069                                 buf[k + j] = (u64) *offset;
2070                                 continue;
2071                         }
2072                         /* 8-byte counter */
2073                         buf[k + j] = HILO_U64(*offset, *(offset + 1));
2074                 }
2075         } else {
2076                 hw_stats = (u32 *)&bp->eth_stats;
2077                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2078                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2079                                 continue;
2080                         if (bnx2x_stats_arr[i].size == 0) {
2081                                 /* skip this counter */
2082                                 buf[j] = 0;
2083                                 j++;
2084                                 continue;
2085                         }
2086                         offset = (hw_stats + bnx2x_stats_arr[i].offset);
2087                         if (bnx2x_stats_arr[i].size == 4) {
2088                                 /* 4-byte counter */
2089                                 buf[j] = (u64) *offset;
2090                                 j++;
2091                                 continue;
2092                         }
2093                         /* 8-byte counter */
2094                         buf[j] = HILO_U64(*offset, *(offset + 1));
2095                         j++;
2096                 }
2097         }
2098 }
2099
2100 static int bnx2x_phys_id(struct net_device *dev, u32 data)
2101 {
2102         struct bnx2x *bp = netdev_priv(dev);
2103         int i;
2104
2105         if (!netif_running(dev))
2106                 return 0;
2107
2108         if (!bp->port.pmf)
2109                 return 0;
2110
2111         if (data == 0)
2112                 data = 2;
2113
2114         for (i = 0; i < (data * 2); i++) {
2115                 if ((i % 2) == 0)
2116                         bnx2x_set_led(&bp->link_params, &bp->link_vars,
2117                                       LED_MODE_ON, SPEED_1000);
2118                 else
2119                         bnx2x_set_led(&bp->link_params, &bp->link_vars,
2120                                       LED_MODE_FRONT_PANEL_OFF, 0);
2121
2122                 msleep_interruptible(500);
2123                 if (signal_pending(current))
2124                         break;
2125         }
2126
2127         bnx2x_set_led(&bp->link_params, &bp->link_vars,
2128                       LED_MODE_OPER, bp->link_vars.line_speed);
2129
2130         return 0;
2131 }
2132
2133 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2134                            void *rules __always_unused)
2135 {
2136         struct bnx2x *bp = netdev_priv(dev);
2137
2138         switch (info->cmd) {
2139         case ETHTOOL_GRXRINGS:
2140                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2141                 return 0;
2142
2143         default:
2144                 return -EOPNOTSUPP;
2145         }
2146 }
2147
2148 static int bnx2x_get_rxfh_indir(struct net_device *dev,
2149                                 struct ethtool_rxfh_indir *indir)
2150 {
2151         struct bnx2x *bp = netdev_priv(dev);
2152         size_t copy_size =
2153                 min_t(size_t, indir->size, TSTORM_INDIRECTION_TABLE_SIZE);
2154
2155         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2156                 return -EOPNOTSUPP;
2157
2158         indir->size = TSTORM_INDIRECTION_TABLE_SIZE;
2159         memcpy(indir->ring_index, bp->rx_indir_table,
2160                copy_size * sizeof(bp->rx_indir_table[0]));
2161         return 0;
2162 }
2163
2164 static int bnx2x_set_rxfh_indir(struct net_device *dev,
2165                                 const struct ethtool_rxfh_indir *indir)
2166 {
2167         struct bnx2x *bp = netdev_priv(dev);
2168         size_t i;
2169
2170         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2171                 return -EOPNOTSUPP;
2172
2173         /* Validate size and indices */
2174         if (indir->size != TSTORM_INDIRECTION_TABLE_SIZE)
2175                 return -EINVAL;
2176         for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
2177                 if (indir->ring_index[i] >= BNX2X_NUM_ETH_QUEUES(bp))
2178                         return -EINVAL;
2179
2180         memcpy(bp->rx_indir_table, indir->ring_index,
2181                indir->size * sizeof(bp->rx_indir_table[0]));
2182         bnx2x_push_indir_table(bp);
2183         return 0;
2184 }
2185
2186 static const struct ethtool_ops bnx2x_ethtool_ops = {
2187         .get_settings           = bnx2x_get_settings,
2188         .set_settings           = bnx2x_set_settings,
2189         .get_drvinfo            = bnx2x_get_drvinfo,
2190         .get_regs_len           = bnx2x_get_regs_len,
2191         .get_regs               = bnx2x_get_regs,
2192         .get_wol                = bnx2x_get_wol,
2193         .set_wol                = bnx2x_set_wol,
2194         .get_msglevel           = bnx2x_get_msglevel,
2195         .set_msglevel           = bnx2x_set_msglevel,
2196         .nway_reset             = bnx2x_nway_reset,
2197         .get_link               = bnx2x_get_link,
2198         .get_eeprom_len         = bnx2x_get_eeprom_len,
2199         .get_eeprom             = bnx2x_get_eeprom,
2200         .set_eeprom             = bnx2x_set_eeprom,
2201         .get_coalesce           = bnx2x_get_coalesce,
2202         .set_coalesce           = bnx2x_set_coalesce,
2203         .get_ringparam          = bnx2x_get_ringparam,
2204         .set_ringparam          = bnx2x_set_ringparam,
2205         .get_pauseparam         = bnx2x_get_pauseparam,
2206         .set_pauseparam         = bnx2x_set_pauseparam,
2207         .get_rx_csum            = bnx2x_get_rx_csum,
2208         .set_rx_csum            = bnx2x_set_rx_csum,
2209         .get_tx_csum            = ethtool_op_get_tx_csum,
2210         .set_tx_csum            = ethtool_op_set_tx_hw_csum,
2211         .set_flags              = bnx2x_set_flags,
2212         .get_flags              = ethtool_op_get_flags,
2213         .get_sg                 = ethtool_op_get_sg,
2214         .set_sg                 = ethtool_op_set_sg,
2215         .get_tso                = ethtool_op_get_tso,
2216         .set_tso                = bnx2x_set_tso,
2217         .self_test              = bnx2x_self_test,
2218         .get_sset_count         = bnx2x_get_sset_count,
2219         .get_strings            = bnx2x_get_strings,
2220         .phys_id                = bnx2x_phys_id,
2221         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2222         .get_rxnfc              = bnx2x_get_rxnfc,
2223         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
2224         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
2225 };
2226
2227 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2228 {
2229         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2230 }