1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
16 #include <linux/netdevice.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/types.h>
20 /* compilation time flags */
22 /* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24 /* #define BNX2X_STOP_ON_ERROR */
26 #define DRV_MODULE_VERSION "1.70.00-0"
27 #define DRV_MODULE_RELDATE "2011/06/13"
28 #define BNX2X_BC_VER 0x040200
30 #if defined(CONFIG_DCB)
33 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
35 #include "../cnic_if.h"
39 #define BNX2X_MIN_MSIX_VEC_CNT 3
40 #define BNX2X_MSIX_VEC_FP_START 2
42 #define BNX2X_MIN_MSIX_VEC_CNT 2
43 #define BNX2X_MSIX_VEC_FP_START 1
46 #include <linux/mdio.h>
48 #include "bnx2x_reg.h"
49 #include "bnx2x_fw_defs.h"
50 #include "bnx2x_hsi.h"
51 #include "bnx2x_link.h"
53 #include "bnx2x_dcb.h"
54 #include "bnx2x_stats.h"
56 /* error/debug prints */
58 #define DRV_MODULE_NAME "bnx2x"
60 /* for messages that are currently off */
61 #define BNX2X_MSG_OFF 0
62 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
63 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
64 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
65 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
66 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
67 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
69 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
71 /* regular debug print */
72 #define DP(__mask, __fmt, __args...) \
74 if (bp->msg_enable & (__mask)) \
75 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
77 bp->dev ? (bp->dev->name) : "?", \
81 #define DP_CONT(__mask, __fmt, __args...) \
83 if (bp->msg_enable & (__mask)) \
84 pr_cont(__fmt, ##__args); \
87 /* errors debug print */
88 #define BNX2X_DBG_ERR(__fmt, __args...) \
90 if (netif_msg_probe(bp)) \
91 pr_err("[%s:%d(%s)]" __fmt, \
93 bp->dev ? (bp->dev->name) : "?", \
97 /* for errors (never masked) */
98 #define BNX2X_ERR(__fmt, __args...) \
100 pr_err("[%s:%d(%s)]" __fmt, \
101 __func__, __LINE__, \
102 bp->dev ? (bp->dev->name) : "?", \
106 #define BNX2X_ERROR(__fmt, __args...) do { \
107 pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
111 /* before we have a dev->name use dev_info() */
112 #define BNX2X_DEV_INFO(__fmt, __args...) \
114 if (netif_msg_probe(bp)) \
115 dev_info(&bp->pdev->dev, __fmt, ##__args); \
118 #define BNX2X_MAC_FMT "%pM"
119 #define BNX2X_MAC_PRN_LIST(mac) (mac)
122 #ifdef BNX2X_STOP_ON_ERROR
123 void bnx2x_int_disable(struct bnx2x *bp);
124 #define bnx2x_panic() do { \
126 BNX2X_ERR("driver assert\n"); \
127 bnx2x_int_disable(bp); \
128 bnx2x_panic_dump(bp); \
131 #define bnx2x_panic() do { \
133 BNX2X_ERR("driver assert\n"); \
134 bnx2x_panic_dump(bp); \
138 #define bnx2x_mc_addr(ha) ((ha)->addr)
139 #define bnx2x_uc_addr(ha) ((ha)->addr)
141 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
142 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
143 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
146 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
148 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
149 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
150 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
152 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
153 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
154 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
156 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
157 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
159 #define REG_RD_DMAE(bp, offset, valp, len32) \
161 bnx2x_read_dmae(bp, offset, len32);\
162 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
165 #define REG_WR_DMAE(bp, offset, valp, len32) \
167 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
168 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
172 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
173 REG_WR_DMAE(bp, offset, valp, len32)
175 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
177 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
178 bnx2x_write_big_buf_wb(bp, addr, len32); \
181 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
182 offsetof(struct shmem_region, field))
183 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
184 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
186 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
187 offsetof(struct shmem2_region, field))
188 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
189 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
190 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
191 offsetof(struct mf_cfg, field))
192 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
193 offsetof(struct mf2_cfg, field))
195 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
196 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
197 MF_CFG_ADDR(bp, field), (val))
198 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
200 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
201 (SHMEM2_RD((bp), size) > \
202 offsetof(struct shmem2_region, field)))
204 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
205 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
209 /* General SP events - stats query, cfc delete, etc */
210 #define HC_SP_INDEX_ETH_DEF_CONS 3
213 #define HC_SP_INDEX_EQ_CONS 7
215 /* FCoE L2 connection completions */
216 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
217 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
219 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
220 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
222 /* Special clients parameters */
226 #define BNX2X_FCOE_L2_RX_INDEX \
227 (&bp->def_status_blk->sp_sb.\
228 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
230 #define BNX2X_FCOE_L2_TX_INDEX \
231 (&bp->def_status_blk->sp_sb.\
232 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
236 * CLIDs below is a CLID for func 0, then the CLID for other
237 * functions will be calculated by the formula:
239 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
243 BNX2X_ISCSI_ETH_CL_ID_IDX,
244 BNX2X_FCOE_ETH_CL_ID_IDX,
245 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
248 #define BNX2X_CNIC_START_ETH_CID 48
251 BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID,
256 /** Additional rings budgeting */
258 #define CNIC_PRESENT 1
259 #define FCOE_PRESENT 1
261 #define CNIC_PRESENT 0
262 #define FCOE_PRESENT 0
263 #endif /* BCM_CNIC */
264 #define NON_ETH_CONTEXT_USE (FCOE_PRESENT)
266 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
267 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
272 /* defines for multiple tx priority indices */
273 #define FIRST_TX_ONLY_COS_INDEX 1
274 #define FIRST_TX_COS_INDEX 0
276 /* defines for decodeing the fastpath index and the cos index out of the
277 * transmission queue index
279 #define MAX_TXQS_PER_COS FP_SB_MAX_E1x
281 #define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS)
282 #define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS)
284 /* rules for calculating the cids of tx-only connections */
285 #define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS)
286 #define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS)
288 /* fp index inside class of service range */
289 #define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS)
293 * 16..31 eth cos1 if applicable
294 * 32..47 eth cos2 If applicable
295 * fcoe queue follows eth queues (16, 32, 48 depending on cos)
297 #define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos)
298 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp))
303 DEFINE_DMA_UNMAP_ADDR(mapping);
310 /* Set on the first BD descriptor when there is a split BD */
311 #define BNX2X_TSO_SPLIT_BD (1<<0)
316 DEFINE_DMA_UNMAP_ADDR(mapping);
320 struct doorbell_set_prod data;
324 /* dropless fc FW/HW related params */
325 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
326 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
327 ETH_MAX_AGGREGATION_QUEUES_E1 :\
328 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
329 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
330 #define FW_PREFETCH_CNT 16
331 #define DROPLESS_FC_HEADROOM 100
334 #define BCM_PAGE_SHIFT 12
335 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
336 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
337 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
339 #define PAGES_PER_SGE_SHIFT 0
340 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
341 #define SGE_PAGE_SIZE PAGE_SIZE
342 #define SGE_PAGE_SHIFT PAGE_SHIFT
343 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
345 /* SGE ring related macros */
346 #define NUM_RX_SGE_PAGES 2
347 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
348 #define NEXT_PAGE_SGE_DESC_CNT 2
349 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
350 /* RX_SGE_CNT is promised to be a power of 2 */
351 #define RX_SGE_MASK (RX_SGE_CNT - 1)
352 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
353 #define MAX_RX_SGE (NUM_RX_SGE - 1)
354 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
355 (MAX_RX_SGE_CNT - 1)) ? \
356 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
358 #define RX_SGE(x) ((x) & MAX_RX_SGE)
361 * Number of required SGEs is the sum of two:
362 * 1. Number of possible opened aggregations (next packet for
363 * these aggregations will probably consume SGE immidiatelly)
364 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
365 * after placement on BD for new TPA aggregation)
367 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
369 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
370 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
371 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
373 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
374 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
375 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
377 /* Manipulate a bit vector defined as an array of u64 */
379 /* Number of bits in one sge_mask array element */
380 #define BIT_VEC64_ELEM_SZ 64
381 #define BIT_VEC64_ELEM_SHIFT 6
382 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
385 #define __BIT_VEC64_SET_BIT(el, bit) \
387 el = ((el) | ((u64)0x1 << (bit))); \
390 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
392 el = ((el) & (~((u64)0x1 << (bit)))); \
396 #define BIT_VEC64_SET_BIT(vec64, idx) \
397 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
398 (idx) & BIT_VEC64_ELEM_MASK)
400 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
401 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
402 (idx) & BIT_VEC64_ELEM_MASK)
404 #define BIT_VEC64_TEST_BIT(vec64, idx) \
405 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
406 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
408 /* Creates a bitmask of all ones in less significant bits.
409 idx - index of the most significant bit in the created mask */
410 #define BIT_VEC64_ONES_MASK(idx) \
411 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
412 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
414 /*******************************************************/
418 /* Number of u64 elements in SGE mask array */
419 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
421 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
422 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
424 union host_hc_status_block {
425 /* pointer to fp status block e1x */
426 struct host_hc_status_block_e1x *e1x_sb;
427 /* pointer to fp status block e2 */
428 struct host_hc_status_block_e2 *e2_sb;
431 struct bnx2x_agg_info {
433 * First aggregation buffer is an skb, the following - are pages.
434 * We will preallocate the skbs for each aggregation when
435 * we open the interface and will replace the BD at the consumer
436 * with this one when we receive the TPA_START CQE in order to
437 * keep the Rx BD ring consistent.
439 struct sw_rx_bd first_buf;
441 #define BNX2X_TPA_START 1
442 #define BNX2X_TPA_STOP 2
443 #define BNX2X_TPA_ERROR 3
450 #define Q_STATS_OFFSET32(stat_name) \
451 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
453 struct bnx2x_fp_txdata {
455 struct sw_tx_bd *tx_buf_ring;
457 union eth_tx_bd_types *tx_desc_ring;
458 dma_addr_t tx_desc_mapping;
469 unsigned long tx_pkt;
476 struct bnx2x_fastpath {
477 struct bnx2x *bp; /* parent */
479 #define BNX2X_NAPI_WEIGHT 128
480 struct napi_struct napi;
481 union host_hc_status_block status_blk;
482 /* chip independed shortcuts into sb structure */
483 __le16 *sb_index_values;
484 __le16 *sb_running_index;
485 /* chip independed shortcut into rx_prods_offset memory */
486 u32 ustorm_rx_prods_offset;
490 dma_addr_t status_blk_mapping;
492 u8 max_cos; /* actual number of active tx coses */
493 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS];
495 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
496 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
498 struct eth_rx_bd *rx_desc_ring;
499 dma_addr_t rx_desc_mapping;
501 union eth_rx_cqe *rx_comp_ring;
502 dma_addr_t rx_comp_mapping;
505 struct eth_rx_sge *rx_sge_ring;
506 dma_addr_t rx_sge_mapping;
508 u64 sge_mask[RX_SGE_MASK_LEN];
514 u8 index; /* number in fp array */
515 u8 cl_id; /* eth client id */
517 u8 fw_sb_id; /* status block number in FW */
518 u8 igu_sb_id; /* status block number in HW */
525 /* The last maximal completed SGE */
528 unsigned long rx_pkt,
532 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
534 #ifdef BNX2X_STOP_ON_ERROR
538 struct tstorm_per_queue_stats old_tclient;
539 struct ustorm_per_queue_stats old_uclient;
540 struct xstorm_per_queue_stats old_xclient;
541 struct bnx2x_eth_q_stats eth_q_stats;
543 /* The size is calculated using the following:
544 sizeof name field from netdev structure +
546 4 (for the digits and to make it DWORD aligned) */
547 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
548 char name[FP_NAME_SIZE];
551 struct bnx2x_vlan_mac_obj mac_obj;
553 /* Queue State object */
554 struct bnx2x_queue_sp_obj q_obj;
558 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
560 /* Use 2500 as a mini-jumbo MTU for FCoE */
561 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
563 /* FCoE L2 `fastpath' entry is right after the eth entries */
564 #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
565 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
566 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
567 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
568 txdata[FIRST_TX_COS_INDEX].var)
571 #define IS_ETH_FP(fp) (fp->index < \
572 BNX2X_NUM_ETH_QUEUES(fp->bp))
574 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
575 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
577 #define IS_FCOE_FP(fp) false
578 #define IS_FCOE_IDX(idx) false
583 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
584 #define RX_COPY_THRESH 92
586 #define NUM_TX_RINGS 16
587 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
588 #define NEXT_PAGE_TX_DESC_CNT 1
589 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
590 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
591 #define MAX_TX_BD (NUM_TX_BD - 1)
592 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
593 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
594 (MAX_TX_DESC_CNT - 1)) ? \
595 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
597 #define TX_BD(x) ((x) & MAX_TX_BD)
598 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
600 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
601 #define NUM_RX_RINGS 8
602 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
603 #define NEXT_PAGE_RX_DESC_CNT 2
604 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
605 #define RX_DESC_MASK (RX_DESC_CNT - 1)
606 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
607 #define MAX_RX_BD (NUM_RX_BD - 1)
608 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
610 /* dropless fc calculations for BDs
612 * Number of BDs should as number of buffers in BRB:
613 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
614 * "next" elements on each page
616 #define NUM_BD_REQ BRB_SIZE(bp)
617 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
619 #define BD_TH_LO(bp) (NUM_BD_REQ + \
620 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
622 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
624 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
626 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
627 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
628 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
629 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
630 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
631 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
634 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
635 (MAX_RX_DESC_CNT - 1)) ? \
636 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
638 #define RX_BD(x) ((x) & MAX_RX_BD)
641 * As long as CQE is X times bigger than BD entry we have to allocate X times
642 * more pages for CQ ring in order to keep it balanced with BD ring
644 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
645 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
646 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
647 #define NEXT_PAGE_RCQ_DESC_CNT 1
648 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
649 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
650 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
651 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
652 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
653 (MAX_RCQ_DESC_CNT - 1)) ? \
654 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
656 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
658 /* dropless fc calculations for RCQs
660 * Number of RCQs should be as number of buffers in BRB:
661 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
662 * "next" elements on each page
664 #define NUM_RCQ_REQ BRB_SIZE(bp)
665 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
667 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
668 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
670 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
673 /* This is needed for determining of last_max */
674 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
675 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
678 #define BNX2X_SWCID_SHIFT 17
679 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
681 /* used on a CID received from the HW */
682 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
683 #define CQE_CMD(x) (le32_to_cpu(x) >> \
684 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
686 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
687 le32_to_cpu((bd)->addr_lo))
688 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
690 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
691 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
692 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
693 #error "Min DB doorbell stride is 8"
695 #define DPM_TRIGER_TYPE 0x40
696 #define DOORBELL(bp, cid, val) \
698 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
703 /* TX CSUM helpers */
704 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
706 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
709 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
712 #define XMIT_CSUM_V4 0x1
713 #define XMIT_CSUM_V6 0x2
714 #define XMIT_CSUM_TCP 0x4
715 #define XMIT_GSO_V4 0x8
716 #define XMIT_GSO_V6 0x10
718 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
719 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
722 /* stuff added to make the code fit 80Col */
723 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
724 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
725 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
726 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
727 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
729 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
731 #define BNX2X_IP_CSUM_ERR(cqe) \
732 (!((cqe)->fast_path_cqe.status_flags & \
733 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
734 ((cqe)->fast_path_cqe.type_error_flags & \
735 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
737 #define BNX2X_L4_CSUM_ERR(cqe) \
738 (!((cqe)->fast_path_cqe.status_flags & \
739 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
740 ((cqe)->fast_path_cqe.type_error_flags & \
741 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
743 #define BNX2X_RX_CSUM_OK(cqe) \
744 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
746 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
747 (((le16_to_cpu(flags) & \
748 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
749 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
750 == PRS_FLAG_OVERETH_IPV4)
751 #define BNX2X_RX_SUM_FIX(cqe) \
752 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
755 #define FP_USB_FUNC_OFF \
756 offsetof(struct cstorm_status_block_u, func)
757 #define FP_CSB_FUNC_OFF \
758 offsetof(struct cstorm_status_block_c, func)
760 #define HC_INDEX_ETH_RX_CQ_CONS 1
762 #define HC_INDEX_OOO_TX_CQ_CONS 4
764 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
766 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
768 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
770 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
772 #define BNX2X_RX_SB_INDEX \
773 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
775 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
777 #define BNX2X_TX_SB_INDEX_COS0 \
778 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
780 /* end of fast path */
784 struct bnx2x_common {
787 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
788 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
790 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
791 #define CHIP_NUM_57710 0x164e
792 #define CHIP_NUM_57711 0x164f
793 #define CHIP_NUM_57711E 0x1650
794 #define CHIP_NUM_57712 0x1662
795 #define CHIP_NUM_57712_MF 0x1663
796 #define CHIP_NUM_57713 0x1651
797 #define CHIP_NUM_57713E 0x1652
798 #define CHIP_NUM_57800 0x168a
799 #define CHIP_NUM_57800_MF 0x16a5
800 #define CHIP_NUM_57810 0x168e
801 #define CHIP_NUM_57810_MF 0x16ae
802 #define CHIP_NUM_57840 0x168d
803 #define CHIP_NUM_57840_MF 0x16ab
804 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
805 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
806 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
807 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
808 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
809 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
810 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
811 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
812 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
813 #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840)
814 #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF)
815 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
817 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
818 CHIP_IS_57712_MF(bp))
819 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
820 CHIP_IS_57800_MF(bp) || \
821 CHIP_IS_57810(bp) || \
822 CHIP_IS_57810_MF(bp) || \
823 CHIP_IS_57840(bp) || \
824 CHIP_IS_57840_MF(bp))
825 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
826 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
827 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
829 #define CHIP_REV_SHIFT 12
830 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
831 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
832 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
833 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
834 /* assume maximum 5 revisions */
835 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
836 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
837 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
838 !(CHIP_REV_VAL(bp) & 0x00001000))
839 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
840 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
841 (CHIP_REV_VAL(bp) & 0x00001000))
843 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
844 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
846 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
847 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
848 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
849 (CHIP_REV_SHIFT + 1)) \
851 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
854 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
855 (CHIP_REV(bp) == CHIP_REV_Bx))
856 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
857 (CHIP_REV(bp) == CHIP_REV_Ax))
860 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
861 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
862 #define BNX2X_NVRAM_PAGE_SIZE 256
874 #define INT_BLOCK_HC 0
875 #define INT_BLOCK_IGU 1
876 #define INT_BLOCK_MODE_NORMAL 0
877 #define INT_BLOCK_MODE_BW_COMP 2
878 #define CHIP_INT_MODE_IS_NBC(bp) \
879 (!CHIP_IS_E1x(bp) && \
880 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
881 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
884 #define CHIP_4_PORT_MODE 0x0
885 #define CHIP_2_PORT_MODE 0x1
886 #define CHIP_PORT_MODE_NONE 0x2
887 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
888 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
891 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
892 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
893 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
902 u32 link_config[LINK_CONFIG_SIZE];
904 u32 supported[LINK_CONFIG_SIZE];
905 /* link settings - missing defines */
906 #define SUPPORTED_2500baseX_Full (1 << 15)
908 u32 advertising[LINK_CONFIG_SIZE];
909 /* link settings - missing defines */
910 #define ADVERTISED_2500baseX_Full (1 << 15)
914 /* used to synchronize phy accesses */
915 struct mutex phy_mutex;
920 struct nig_stats old_nig_stats;
925 #define STATS_OFFSET32(stat_name) \
926 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
930 /* slow path work-queue */
931 extern struct workqueue_struct *bnx2x_wq;
933 #define BNX2X_MAX_NUM_OF_VFS 64
934 #define BNX2X_VF_ID_INVALID 0xFF
937 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
938 * control by the number of fast-path status blocks supported by the
939 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
940 * status block represents an independent interrupts context that can
941 * serve a regular L2 networking queue. However special L2 queues such
942 * as the FCoE queue do not require a FP-SB and other components like
943 * the CNIC may consume FP-SB reducing the number of possible L2 queues
945 * If the maximum number of FP-SB available is X then:
946 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
947 * regular L2 queues is Y=X-1
948 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
949 * c. If the FCoE L2 queue is supported the actual number of L2 queues
951 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
952 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
953 * FP interrupt context for the CNIC).
954 * e. The number of HW context (CID count) is always X or X+1 if FCoE
955 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
958 /* fast-path interrupt contexts E1x */
959 #define FP_SB_MAX_E1x 16
960 /* fast-path interrupt contexts E2 */
961 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
964 struct eth_context eth;
968 /* CDU host DB constants */
969 #define CDU_ILT_PAGE_SZ_HW 3
970 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */
971 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
974 #define CNIC_ISCSI_CID_MAX 256
975 #define CNIC_FCOE_CID_MAX 2048
976 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
977 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
980 #define QM_ILT_PAGE_SZ_HW 0
981 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
982 #define QM_CID_ROUND 1024
985 /* TM (timers) host DB constants */
986 #define TM_ILT_PAGE_SZ_HW 0
987 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
988 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
989 #define TM_CONN_NUM 1024
990 #define TM_ILT_SZ (8 * TM_CONN_NUM)
991 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
993 /* SRC (Searcher) host DB constants */
994 #define SRC_ILT_PAGE_SZ_HW 0
995 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
996 #define SRC_HASH_BITS 10
997 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
998 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
999 #define SRC_T2_SZ SRC_ILT_SZ
1000 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1004 #define MAX_DMAE_C 8
1006 /* DMA memory not used in fastpath */
1007 struct bnx2x_slowpath {
1009 struct mac_configuration_cmd e1x;
1010 struct eth_classify_rules_ramrod_data e2;
1015 struct tstorm_eth_mac_filter_config e1x;
1016 struct eth_filter_rules_ramrod_data e2;
1020 struct mac_configuration_cmd e1;
1021 struct eth_multicast_rules_ramrod_data e2;
1024 struct eth_rss_update_ramrod_data rss_rdata;
1026 /* Queue State related ramrods are always sent under rtnl_lock */
1028 struct client_init_ramrod_data init_data;
1029 struct client_update_ramrod_data update_data;
1033 struct function_start_data func_start;
1034 /* pfc configuration for DCBX ramrod */
1035 struct flow_control_configuration pfc_config;
1038 /* used by dmae command executer */
1039 struct dmae_command dmae[MAX_DMAE_C];
1042 union mac_stats mac_stats;
1043 struct nig_stats nig_stats;
1044 struct host_port_stats port_stats;
1045 struct host_func_stats func_stats;
1046 struct host_func_stats func_stats_base;
1052 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1053 #define bnx2x_sp_mapping(bp, var) \
1054 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1057 /* attn group wiring */
1058 #define MAX_DYNAMIC_ATTN_GRPS 8
1073 union cdu_context *vcxt;
1074 dma_addr_t cxt_mapping;
1082 enum bnx2x_recovery_state {
1083 BNX2X_RECOVERY_DONE,
1084 BNX2X_RECOVERY_INIT,
1085 BNX2X_RECOVERY_WAIT,
1086 BNX2X_RECOVERY_FAILED
1090 * Event queue (EQ or event ring) MC hsi
1091 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1093 #define NUM_EQ_PAGES 1
1094 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1095 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1096 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1097 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1098 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1100 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1101 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1102 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1104 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1105 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1107 #define BNX2X_EQ_INDEX \
1108 (&bp->def_status_blk->sp_sb.\
1109 index_values[HC_SP_INDEX_EQ_CONS])
1111 /* This is a data that will be used to create a link report message.
1112 * We will keep the data used for the last link report in order
1113 * to prevent reporting the same link parameters twice.
1115 struct bnx2x_link_report_data {
1116 u16 line_speed; /* Effective line speed */
1117 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1121 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1122 BNX2X_LINK_REPORT_LINK_DOWN,
1123 BNX2X_LINK_REPORT_RX_FC_ON,
1124 BNX2X_LINK_REPORT_TX_FC_ON,
1128 BNX2X_PORT_QUERY_IDX,
1130 BNX2X_FIRST_QUEUE_QUERY_IDX,
1133 struct bnx2x_fw_stats_req {
1134 struct stats_query_header hdr;
1135 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
1138 struct bnx2x_fw_stats_data {
1139 struct stats_counter storm_counters;
1140 struct per_port_stats port;
1141 struct per_pf_stats pf;
1142 struct per_queue_stats queue_stats[1];
1145 /* Public slow path states */
1147 BNX2X_SP_RTNL_SETUP_TC,
1148 BNX2X_SP_RTNL_TX_TIMEOUT,
1153 /* Fields used in the tx and intr/napi performance paths
1154 * are grouped together in the beginning of the structure
1156 struct bnx2x_fastpath *fp;
1157 void __iomem *regview;
1158 void __iomem *doorbells;
1161 u8 pf_num; /* absolute PF number */
1162 u8 pfid; /* per-path PF number */
1163 int base_fw_ndsb; /**/
1164 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1165 #define BP_PORT(bp) (bp->pfid & 1)
1166 #define BP_FUNC(bp) (bp->pfid)
1167 #define BP_ABS_FUNC(bp) (bp->pf_num)
1168 #define BP_VN(bp) ((bp)->pfid >> 1)
1169 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1170 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1171 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1172 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1173 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1175 struct net_device *dev;
1176 struct pci_dev *pdev;
1178 const struct iro *iro_arr;
1179 #define IRO (bp->iro_arr)
1181 enum bnx2x_recovery_state recovery_state;
1183 struct msix_entry *msix_table;
1187 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1188 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1189 #define ETH_MIN_PACKET_SIZE 60
1190 #define ETH_MAX_PACKET_SIZE 1500
1191 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1193 /* Max supported alignment is 256 (8 shift) */
1194 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
1196 /* FW use 2 Cache lines Alignment for start packet and size */
1197 #define BNX2X_FW_RX_ALIGN (2 << BNX2X_RX_ALIGN_SHIFT)
1198 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1200 struct host_sp_status_block *def_status_blk;
1201 #define DEF_SB_IGU_ID 16
1202 #define DEF_SB_ID HC_SP_SB_ID
1206 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1208 /* slow path ring */
1209 struct eth_spe *spq;
1210 dma_addr_t spq_mapping;
1212 struct eth_spe *spq_prod_bd;
1213 struct eth_spe *spq_last_bd;
1214 __le16 *dsb_sp_prod;
1215 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1216 /* used to synchronize spq accesses */
1217 spinlock_t spq_lock;
1220 union event_ring_elem *eq_ring;
1221 dma_addr_t eq_mapping;
1225 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1229 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1231 /* Counter for completed statistics ramrods */
1234 /* End of fields used in the performance code paths */
1240 #define PCIX_FLAG (1 << 0)
1241 #define PCI_32BIT_FLAG (1 << 1)
1242 #define ONE_PORT_FLAG (1 << 2)
1243 #define NO_WOL_FLAG (1 << 3)
1244 #define USING_DAC_FLAG (1 << 4)
1245 #define USING_MSIX_FLAG (1 << 5)
1246 #define USING_MSI_FLAG (1 << 6)
1247 #define DISABLE_MSI_FLAG (1 << 7)
1248 #define TPA_ENABLE_FLAG (1 << 8)
1249 #define NO_MCP_FLAG (1 << 9)
1251 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1252 #define MF_FUNC_DIS (1 << 11)
1253 #define OWN_CNIC_IRQ (1 << 12)
1254 #define NO_ISCSI_OOO_FLAG (1 << 13)
1255 #define NO_ISCSI_FLAG (1 << 14)
1256 #define NO_FCOE_FLAG (1 << 15)
1258 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1259 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1260 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1265 struct delayed_work sp_task;
1266 struct delayed_work sp_rtnl_task;
1268 struct delayed_work period_task;
1269 struct timer_list timer;
1270 int current_interval;
1273 u16 fw_drv_pulse_wr_seq;
1276 struct link_params link_params;
1277 struct link_vars link_vars;
1279 struct bnx2x_link_report_data last_reported_link;
1281 struct mdio_if_info mdio;
1283 struct bnx2x_common common;
1284 struct bnx2x_port port;
1286 struct cmng_struct_per_port cmng;
1288 u32 mf_config[E1HVN_MAX];
1289 u32 mf2_config[E2_FUNC_MAX];
1290 u32 path_has_ovlan; /* E3 */
1293 #define IS_MF(bp) (bp->mf_mode != 0)
1294 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1295 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1301 u16 tx_quick_cons_trip_int;
1302 u16 tx_quick_cons_trip;
1306 u16 rx_quick_cons_trip_int;
1307 u16 rx_quick_cons_trip;
1310 /* Maximal coalescing timeout in us */
1311 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1316 #define BNX2X_STATE_CLOSED 0
1317 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1318 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1319 #define BNX2X_STATE_OPEN 0x3000
1320 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1321 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1323 #define BNX2X_STATE_DIAG 0xe000
1324 #define BNX2X_STATE_ERROR 0xf000
1327 #define BNX2X_MAX_PRIORITY 8
1328 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1329 #define BNX2X_MAX_COS 3
1330 #define BNX2X_MAX_TX_COS 2
1335 #define BNX2X_RX_MODE_NONE 0
1336 #define BNX2X_RX_MODE_NORMAL 1
1337 #define BNX2X_RX_MODE_ALLMULTI 2
1338 #define BNX2X_RX_MODE_PROMISC 3
1339 #define BNX2X_MAX_MULTICAST 64
1344 dma_addr_t def_status_blk_mapping;
1346 struct bnx2x_slowpath *slowpath;
1347 dma_addr_t slowpath_mapping;
1349 /* Total number of FW statistics requests */
1353 * This is a memory buffer that will contain both statistics
1354 * ramrod request and data.
1357 dma_addr_t fw_stats_mapping;
1360 * FW statistics request shortcut (points at the
1361 * beginning of fw_stats buffer).
1363 struct bnx2x_fw_stats_req *fw_stats_req;
1364 dma_addr_t fw_stats_req_mapping;
1365 int fw_stats_req_sz;
1368 * FW statistics data shortcut (points at the begining of
1369 * fw_stats buffer + fw_stats_req_sz).
1371 struct bnx2x_fw_stats_data *fw_stats_data;
1372 dma_addr_t fw_stats_data_mapping;
1373 int fw_stats_data_sz;
1375 struct hw_context context;
1377 struct bnx2x_ilt *ilt;
1378 #define BP_ILT(bp) ((bp)->ilt)
1379 #define ILT_MAX_LINES 256
1381 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1384 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT)
1387 * Maximum CID count that might be required by the bnx2x:
1388 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related)
1390 #define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\
1391 NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1392 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1394 #define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT))
1402 #define BNX2X_CNIC_FLAG_MAC_SET 1
1404 dma_addr_t t2_mapping;
1405 struct cnic_ops __rcu *cnic_ops;
1408 struct cnic_eth_dev cnic_eth_dev;
1409 union host_hc_status_block cnic_sb;
1410 dma_addr_t cnic_sb_mapping;
1411 struct eth_spe *cnic_kwq;
1412 struct eth_spe *cnic_kwq_prod;
1413 struct eth_spe *cnic_kwq_cons;
1414 struct eth_spe *cnic_kwq_last;
1415 u16 cnic_kwq_pending;
1416 u16 cnic_spq_pending;
1417 u8 fip_mac[ETH_ALEN];
1418 struct mutex cnic_mutex;
1419 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1421 /* Start index of the "special" (CNIC related) L2 cleints */
1426 /* used to synchronize dmae accesses */
1427 spinlock_t dmae_lock;
1429 /* used to protect the FW mail box */
1430 struct mutex fw_mb_mutex;
1432 /* used to synchronize stats collecting */
1435 /* used for synchronization of concurrent threads statistics handling */
1436 spinlock_t stats_lock;
1438 /* used by dmae command loader */
1439 struct dmae_command stats_dmae;
1443 struct bnx2x_eth_stats eth_stats;
1445 struct z_stream_s *strm;
1447 dma_addr_t gunzip_mapping;
1449 #define FW_BUF_SIZE 0x8000
1450 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1451 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1452 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1454 struct raw_op *init_ops;
1455 /* Init blocks offsets inside init_ops */
1456 u16 *init_ops_offsets;
1457 /* Data blob - has 32 bit granularity */
1459 u32 init_mode_flags;
1460 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1461 /* Zipped PRAM blobs - raw data */
1462 const u8 *tsem_int_table_data;
1463 const u8 *tsem_pram_data;
1464 const u8 *usem_int_table_data;
1465 const u8 *usem_pram_data;
1466 const u8 *xsem_int_table_data;
1467 const u8 *xsem_pram_data;
1468 const u8 *csem_int_table_data;
1469 const u8 *csem_pram_data;
1470 #define INIT_OPS(bp) (bp->init_ops)
1471 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1472 #define INIT_DATA(bp) (bp->init_data)
1473 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1474 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1475 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1476 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1477 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1478 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1479 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1480 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1482 #define PHY_FW_VER_LEN 20
1484 const struct firmware *firmware;
1486 /* DCB support on/off */
1488 #define BNX2X_DCB_STATE_OFF 0
1489 #define BNX2X_DCB_STATE_ON 1
1491 /* DCBX engine mode */
1493 #define BNX2X_DCBX_ENABLED_OFF 0
1494 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1495 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1496 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1498 bool dcbx_mode_uset;
1500 struct bnx2x_config_dcbx_params dcbx_config_params;
1501 struct bnx2x_dcbx_port_params dcbx_port_params;
1504 /* CAM credit pools */
1505 struct bnx2x_credit_pool_obj macs_pool;
1507 /* RX_MODE object */
1508 struct bnx2x_rx_mode_obj rx_mode_obj;
1511 struct bnx2x_mcast_obj mcast_obj;
1513 /* RSS configuration object */
1514 struct bnx2x_rss_config_obj rss_conf_obj;
1516 /* Function State controlling object */
1517 struct bnx2x_func_sp_obj func_obj;
1519 unsigned long sp_state;
1521 /* operation indication for the sp_rtnl task */
1522 unsigned long sp_rtnl_state;
1524 /* DCBX Negotation results */
1525 struct dcbx_features dcbx_local_feat;
1529 struct dcbx_features dcbx_remote_feat;
1530 u32 dcbx_remote_flags;
1534 /* multiple tx classes of service */
1537 /* priority to cos mapping */
1541 /* Tx queues may be less or equal to Rx queues */
1542 extern int num_queues;
1543 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1544 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE)
1545 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1547 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1549 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1550 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1552 #define RSS_IPV4_CAP_MASK \
1553 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1555 #define RSS_IPV4_TCP_CAP_MASK \
1556 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1558 #define RSS_IPV6_CAP_MASK \
1559 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1561 #define RSS_IPV6_TCP_CAP_MASK \
1562 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1564 /* func init flags */
1565 #define FUNC_FLG_RSS 0x0001
1566 #define FUNC_FLG_STATS 0x0002
1567 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1568 #define FUNC_FLG_TPA 0x0008
1569 #define FUNC_FLG_SPQ 0x0010
1570 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1573 struct bnx2x_func_init_params {
1575 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1576 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1579 u16 func_id; /* abs fid */
1581 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1584 #define for_each_eth_queue(bp, var) \
1585 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1587 #define for_each_nondefault_eth_queue(bp, var) \
1588 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1590 #define for_each_queue(bp, var) \
1591 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1592 if (skip_queue(bp, var)) \
1596 /* Skip forwarding FP */
1597 #define for_each_rx_queue(bp, var) \
1598 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1599 if (skip_rx_queue(bp, var)) \
1604 #define for_each_tx_queue(bp, var) \
1605 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1606 if (skip_tx_queue(bp, var)) \
1610 #define for_each_nondefault_queue(bp, var) \
1611 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1612 if (skip_queue(bp, var)) \
1616 #define for_each_cos_in_tx_queue(fp, var) \
1617 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1620 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1622 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1625 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1627 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1629 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1635 * bnx2x_set_mac_one - configure a single MAC address
1637 * @bp: driver handle
1638 * @mac: MAC to configure
1639 * @obj: MAC object handle
1640 * @set: if 'true' add a new MAC, otherwise - delete
1641 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1642 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1644 * Configures one MAC according to provided parameters or continues the
1645 * execution of previously scheduled commands if RAMROD_CONT is set in
1648 * Returns zero if operation has successfully completed, a positive value if the
1649 * operation has been successfully scheduled and a negative - if a requested
1650 * operations has failed.
1652 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1653 struct bnx2x_vlan_mac_obj *obj, bool set,
1654 int mac_type, unsigned long *ramrod_flags);
1656 * Deletes all MACs configured for the specific MAC object.
1658 * @param bp Function driver instance
1659 * @param mac_obj MAC object to cleanup
1661 * @return zero if all MACs were cleaned
1665 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1667 * @bp: driver handle
1668 * @mac_obj: MAC object handle
1669 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1670 * @wait_for_comp: if 'true' block until completion
1672 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1674 * Returns zero if operation has successfully completed, a positive value if the
1675 * operation has been successfully scheduled and a negative - if a requested
1676 * operations has failed.
1678 int bnx2x_del_all_macs(struct bnx2x *bp,
1679 struct bnx2x_vlan_mac_obj *mac_obj,
1680 int mac_type, bool wait_for_comp);
1682 /* Init Function API */
1683 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1684 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1685 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1686 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1687 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1688 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1692 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1693 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1695 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1696 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1697 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1698 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1699 bool with_comp, u8 comp_type);
1702 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1703 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1704 u32 data_hi, u32 data_lo, int cmd_type);
1705 void bnx2x_update_coalesce(struct bnx2x *bp);
1706 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1708 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1714 val = REG_RD(bp, reg);
1715 if (val == expected)
1725 #define BNX2X_ILT_ZALLOC(x, y, size) \
1727 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1729 memset(x, 0, size); \
1732 #define BNX2X_ILT_FREE(x, y, size) \
1735 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1741 #define ILOG2(x) (ilog2((x)))
1743 #define ILT_NUM_PAGE_ENTRIES (3072)
1744 /* In 57710/11 we use whole table since we have 8 func
1745 * In 57712 we have only 4 func, but use same size per func, then only half of
1748 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1750 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1752 * the phys address is shifted right 12 bits and has an added
1753 * 1=valid bit added to the 53rd bit
1754 * then since this is a wide register(TM)
1755 * we split it into two 32 bit writes
1757 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1758 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1760 /* load/unload mode */
1761 #define LOAD_NORMAL 0
1764 #define UNLOAD_NORMAL 0
1765 #define UNLOAD_CLOSE 1
1766 #define UNLOAD_RECOVERY 2
1769 /* DMAE command defines */
1770 #define DMAE_TIMEOUT -1
1771 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1772 #define DMAE_NOT_RDY -3
1773 #define DMAE_PCI_ERR_FLAG 0x80000000
1775 #define DMAE_SRC_PCI 0
1776 #define DMAE_SRC_GRC 1
1778 #define DMAE_DST_NONE 0
1779 #define DMAE_DST_PCI 1
1780 #define DMAE_DST_GRC 2
1782 #define DMAE_COMP_PCI 0
1783 #define DMAE_COMP_GRC 1
1785 /* E2 and onward - PCI error handling in the completion */
1787 #define DMAE_COMP_REGULAR 0
1788 #define DMAE_COM_SET_ERR 1
1790 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1791 DMAE_COMMAND_SRC_SHIFT)
1792 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1793 DMAE_COMMAND_SRC_SHIFT)
1795 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1796 DMAE_COMMAND_DST_SHIFT)
1797 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1798 DMAE_COMMAND_DST_SHIFT)
1800 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1801 DMAE_COMMAND_C_DST_SHIFT)
1802 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1803 DMAE_COMMAND_C_DST_SHIFT)
1805 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1807 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1808 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1809 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1810 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1812 #define DMAE_CMD_PORT_0 0
1813 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1815 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1816 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1817 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1819 #define DMAE_SRC_PF 0
1820 #define DMAE_SRC_VF 1
1822 #define DMAE_DST_PF 0
1823 #define DMAE_DST_VF 1
1825 #define DMAE_C_SRC 0
1826 #define DMAE_C_DST 1
1828 #define DMAE_LEN32_RD_MAX 0x80
1829 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1831 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1834 #define MAX_DMAE_C_PER_PORT 8
1835 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1837 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1840 /* PCIE link and speed */
1841 #define PCICFG_LINK_WIDTH 0x1f00000
1842 #define PCICFG_LINK_WIDTH_SHIFT 20
1843 #define PCICFG_LINK_SPEED 0xf0000
1844 #define PCICFG_LINK_SPEED_SHIFT 16
1847 #define BNX2X_NUM_TESTS 7
1849 #define BNX2X_PHY_LOOPBACK 0
1850 #define BNX2X_MAC_LOOPBACK 1
1851 #define BNX2X_PHY_LOOPBACK_FAILED 1
1852 #define BNX2X_MAC_LOOPBACK_FAILED 2
1853 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1854 BNX2X_PHY_LOOPBACK_FAILED)
1857 #define STROM_ASSERT_ARRAY_SIZE 50
1860 /* must be used on a CID before placing it on a HW ring */
1861 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1862 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
1865 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1866 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1870 #define MAX_SPQ_PENDING 8
1872 /* CMNG constants, as derived from system spec calculations */
1873 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1874 #define DEF_MIN_RATE 100
1875 /* resolution of the rate shaping timer - 400 usec */
1876 #define RS_PERIODIC_TIMEOUT_USEC 400
1877 /* number of bytes in single QM arbitration cycle -
1878 * coefficient for calculating the fairness timer */
1879 #define QM_ARB_BYTES 160000
1880 /* resolution of Min algorithm 1:100 */
1882 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1883 #define MIN_ABOVE_THRESH 32768
1884 /* Fairness algorithm integration time coefficient -
1885 * for calculating the actual Tfair */
1886 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
1887 /* Memory of fairness algorithm . 2 cycles */
1891 #define ATTN_NIG_FOR_FUNC (1L << 8)
1892 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1893 #define GPIO_2_FUNC (1L << 10)
1894 #define GPIO_3_FUNC (1L << 11)
1895 #define GPIO_4_FUNC (1L << 12)
1896 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1897 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1898 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1899 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1900 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1901 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1903 #define ATTN_HARD_WIRED_MASK 0xff00
1904 #define ATTENTION_ID 4
1907 /* stuff added to make the code fit 80Col */
1909 #define BNX2X_PMF_LINK_ASSERT \
1910 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1912 #define BNX2X_MC_ASSERT_BITS \
1913 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1914 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1915 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1916 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1918 #define BNX2X_MCP_ASSERT \
1919 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1921 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1922 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1923 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1924 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1925 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1926 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1927 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1929 #define HW_INTERRUT_ASSERT_SET_0 \
1930 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1931 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1932 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1933 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
1934 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1935 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1936 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1937 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1938 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
1939 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
1940 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
1941 #define HW_INTERRUT_ASSERT_SET_1 \
1942 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1943 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1944 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1945 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1946 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1947 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1948 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1949 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1950 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1951 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1952 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1953 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
1954 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1955 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
1956 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1957 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
1958 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1959 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1960 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
1961 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1962 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1963 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1964 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
1965 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1966 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1967 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
1968 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
1969 #define HW_INTERRUT_ASSERT_SET_2 \
1970 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1971 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1972 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1973 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1974 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1975 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1976 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1977 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1978 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1979 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1980 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
1981 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1982 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1984 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1985 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1986 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1987 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1989 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
1990 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
1992 #define RSS_FLAGS(bp) \
1993 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1994 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1995 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1996 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1997 (bp->multi_mode << \
1998 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1999 #define MULTI_MASK 0x7f
2002 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2003 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2004 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2005 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2007 #define DEF_USB_IGU_INDEX_OFF \
2008 offsetof(struct cstorm_def_status_block_u, igu_index)
2009 #define DEF_CSB_IGU_INDEX_OFF \
2010 offsetof(struct cstorm_def_status_block_c, igu_index)
2011 #define DEF_XSB_IGU_INDEX_OFF \
2012 offsetof(struct xstorm_def_status_block, igu_index)
2013 #define DEF_TSB_IGU_INDEX_OFF \
2014 offsetof(struct tstorm_def_status_block, igu_index)
2016 #define DEF_USB_SEGMENT_OFF \
2017 offsetof(struct cstorm_def_status_block_u, segment)
2018 #define DEF_CSB_SEGMENT_OFF \
2019 offsetof(struct cstorm_def_status_block_c, segment)
2020 #define DEF_XSB_SEGMENT_OFF \
2021 offsetof(struct xstorm_def_status_block, segment)
2022 #define DEF_TSB_SEGMENT_OFF \
2023 offsetof(struct tstorm_def_status_block, segment)
2025 #define BNX2X_SP_DSB_INDEX \
2026 (&bp->def_status_blk->sp_sb.\
2027 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2029 #define SET_FLAG(value, mask, flag) \
2031 (value) &= ~(mask);\
2032 (value) |= ((flag) << (mask##_SHIFT));\
2035 #define GET_FLAG(value, mask) \
2036 (((value) & (mask)) >> (mask##_SHIFT))
2038 #define GET_FIELD(value, fname) \
2039 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2041 #define CAM_IS_INVALID(x) \
2042 (GET_FLAG(x.flags, \
2043 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2044 (T_ETH_MAC_COMMAND_INVALIDATE))
2046 /* Number of u32 elements in MC hash array */
2047 #define MC_HASH_SIZE 8
2048 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2049 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2052 #ifndef PXP2_REG_PXP2_INT_STS
2053 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2056 #ifndef ETH_MAX_RX_CLIENTS_E2
2057 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2060 #define BNX2X_VPD_LEN 128
2061 #define VENDOR_ID_LEN 4
2063 /* Congestion management fairness mode */
2064 #define CMNG_FNS_NONE 0
2065 #define CMNG_FNS_MINMAX 1
2067 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2068 #define HC_SEG_ACCESS_ATTN 4
2069 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2071 static const u32 dmae_reg_go_c[] = {
2072 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2073 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2074 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2075 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2078 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2079 void bnx2x_notify_link_changed(struct bnx2x *bp);
2080 #endif /* bnx2x.h */