drivers/net/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include "be.h"
  19 #include "be_cmds.h"
  20
  21 /* Must be a power of 2 or else MODULO will BUG_ON */
  22 static int be_get_temp_freq = 32;
  23
  24 static void be_mcc_notify(struct be_adapter *adapter)
  25 {
  26         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  27         u32 val = 0;
  28
  29         if (adapter->eeh_err) {
  30                 dev_info(&adapter->pdev->dev,
  31                         "Error in Card Detected! Cannot issue commands\n");
  32                 return;
  33         }
  34
  35         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  36         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  37
  38         wmb();
  39         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  40 }
  41
  42 /* To check if valid bit is set, check the entire word as we don't know
  43  * the endianness of the data (old entry is host endian while a new entry is
  44  * little endian) */
  45 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  46 {
  47         if (compl->flags != 0) {
  48                 compl->flags = le32_to_cpu(compl->flags);
  49                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  50                 return true;
  51         } else {
  52                 return false;
  53         }
  54 }
  55
  56 /* Need to reset the entire word that houses the valid bit */
  57 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  58 {
  59         compl->flags = 0;
  60 }
  61
  62 static int be_mcc_compl_process(struct be_adapter *adapter,
  63         struct be_mcc_compl *compl)
  64 {
  65         u16 compl_status, extd_status;
  66
  67         /* Just swap the status to host endian; mcc tag is opaquely copied
  68          * from mcc_wrb */
  69         be_dws_le_to_cpu(compl, 4);
  70
  71         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  72                                 CQE_STATUS_COMPL_MASK;
  73
  74         if ((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) &&
  75                 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
  76                 adapter->flash_status = compl_status;
  77                 complete(&adapter->flash_compl);
  78         }
  79
  80         if (compl_status == MCC_STATUS_SUCCESS) {
  81                 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
  82                         struct be_cmd_resp_get_stats *resp =
  83                                                 adapter->stats_cmd.va;
  84                         be_dws_le_to_cpu(&resp->hw_stats,
  85                                                 sizeof(resp->hw_stats));
  86                         netdev_stats_update(adapter);
  87                         adapter->stats_cmd_sent = false;
  88                 }
  89         } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
  90                    (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
  91                 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
  92                                 CQE_STATUS_EXTD_MASK;
  93                 dev_warn(&adapter->pdev->dev,
  94                 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
  95                         compl->tag0, compl_status, extd_status);
  96         }
  97         return compl_status;
  98 }
  99
 100 /* Link state evt is a string of bytes; no need for endian swapping */
 101 static void be_async_link_state_process(struct be_adapter *adapter,
 102                 struct be_async_event_link_state *evt)
 103 {
 104         be_link_status_update(adapter,
 105                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
 106 }
 107
 108 /* Grp5 CoS Priority evt */
 109 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 110                 struct be_async_event_grp5_cos_priority *evt)
 111 {
 112         if (evt->valid) {
 113                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 114                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 115                 adapter->recommended_prio =
 116                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 117         }
 118 }
 119
 120 /* Grp5 QOS Speed evt */
 121 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 122                 struct be_async_event_grp5_qos_link_speed *evt)
 123 {
 124         if (evt->physical_port == adapter->port_num) {
 125                 /* qos_link_speed is in units of 10 Mbps */
 126                 adapter->link_speed = evt->qos_link_speed * 10;
 127         }
 128 }
 129
 130 /*Grp5 PVID evt*/
 131 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 132                 struct be_async_event_grp5_pvid_state *evt)
 133 {
 134         if (evt->enabled)
 135                 adapter->pvid = evt->tag;
 136         else
 137                 adapter->pvid = 0;
 138 }
 139
 140 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 141                 u32 trailer, struct be_mcc_compl *evt)
 142 {
 143         u8 event_type = 0;
 144
 145         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 146                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 147
 148         switch (event_type) {
 149         case ASYNC_EVENT_COS_PRIORITY:
 150                 be_async_grp5_cos_priority_process(adapter,
 151                 (struct be_async_event_grp5_cos_priority *)evt);
 152         break;
 153         case ASYNC_EVENT_QOS_SPEED:
 154                 be_async_grp5_qos_speed_process(adapter,
 155                 (struct be_async_event_grp5_qos_link_speed *)evt);
 156         break;
 157         case ASYNC_EVENT_PVID_STATE:
 158                 be_async_grp5_pvid_state_process(adapter,
 159                 (struct be_async_event_grp5_pvid_state *)evt);
 160         break;
 161         default:
 162                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 163                 break;
 164         }
 165 }
 166
 167 static inline bool is_link_state_evt(u32 trailer)
 168 {
 169         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 170                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 171                                 ASYNC_EVENT_CODE_LINK_STATE;
 172 }
 173
 174 static inline bool is_grp5_evt(u32 trailer)
 175 {
 176         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 177                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 178                                 ASYNC_EVENT_CODE_GRP_5);
 179 }
 180
 181 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 182 {
 183         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 184         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 185
 186         if (be_mcc_compl_is_new(compl)) {
 187                 queue_tail_inc(mcc_cq);
 188                 return compl;
 189         }
 190         return NULL;
 191 }
 192
 193 void be_async_mcc_enable(struct be_adapter *adapter)
 194 {
 195         spin_lock_bh(&adapter->mcc_cq_lock);
 196
 197         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 198         adapter->mcc_obj.rearm_cq = true;
 199
 200         spin_unlock_bh(&adapter->mcc_cq_lock);
 201 }
 202
 203 void be_async_mcc_disable(struct be_adapter *adapter)
 204 {
 205         adapter->mcc_obj.rearm_cq = false;
 206 }
 207
 208 int be_process_mcc(struct be_adapter *adapter, int *status)
 209 {
 210         struct be_mcc_compl *compl;
 211         int num = 0;
 212         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 213
 214         spin_lock_bh(&adapter->mcc_cq_lock);
 215         while ((compl = be_mcc_compl_get(adapter))) {
 216                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 217                         /* Interpret flags as an async trailer */
 218                         if (is_link_state_evt(compl->flags))
 219                                 be_async_link_state_process(adapter,
 220                                 (struct be_async_event_link_state *) compl);
 221                         else if (is_grp5_evt(compl->flags))
 222                                 be_async_grp5_evt_process(adapter,
 223                                 compl->flags, compl);
 224                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 225                                 *status = be_mcc_compl_process(adapter, compl);
 226                                 atomic_dec(&mcc_obj->q.used);
 227                 }
 228                 be_mcc_compl_use(compl);
 229                 num++;
 230         }
 231
 232         spin_unlock_bh(&adapter->mcc_cq_lock);
 233         return num;
 234 }
 235
 236 /* Wait till no more pending mcc requests are present */
 237 static int be_mcc_wait_compl(struct be_adapter *adapter)
 238 {
 239 #define mcc_timeout             120000 /* 12s timeout */
 240         int i, num, status = 0;
 241         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 242
 243         if (adapter->eeh_err)
 244                 return -EIO;
 245
 246         for (i = 0; i < mcc_timeout; i++) {
 247                 num = be_process_mcc(adapter, &status);
 248                 if (num)
 249                         be_cq_notify(adapter, mcc_obj->cq.id,
 250                                 mcc_obj->rearm_cq, num);
 251
 252                 if (atomic_read(&mcc_obj->q.used) == 0)
 253                         break;
 254                 udelay(100);
 255         }
 256         if (i == mcc_timeout) {
 257                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
 258                 return -1;
 259         }
 260         return status;
 261 }
 262
 263 /* Notify MCC requests and wait for completion */
 264 static int be_mcc_notify_wait(struct be_adapter *adapter)
 265 {
 266         be_mcc_notify(adapter);
 267         return be_mcc_wait_compl(adapter);
 268 }
 269
 270 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 271 {
 272         int msecs = 0;
 273         u32 ready;
 274
 275         if (adapter->eeh_err) {
 276                 dev_err(&adapter->pdev->dev,
 277                         "Error detected in card.Cannot issue commands\n");
 278                 return -EIO;
 279         }
 280
 281         do {
 282                 ready = ioread32(db);
 283                 if (ready == 0xffffffff) {
 284                         dev_err(&adapter->pdev->dev,
 285                                 "pci slot disconnected\n");
 286                         return -1;
 287                 }
 288
 289                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 290                 if (ready)
 291                         break;
 292
 293                 if (msecs > 4000) {
 294                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
 295                         be_detect_dump_ue(adapter);
 296                         return -1;
 297                 }
 298
 299                 set_current_state(TASK_INTERRUPTIBLE);
 300                 schedule_timeout(msecs_to_jiffies(1));
 301                 msecs++;
 302         } while (true);
 303
 304         return 0;
 305 }
 306
 307 /*
 308  * Insert the mailbox address into the doorbell in two steps
 309  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 310  */
 311 static int be_mbox_notify_wait(struct be_adapter *adapter)
 312 {
 313         int status;
 314         u32 val = 0;
 315         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 316         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 317         struct be_mcc_mailbox *mbox = mbox_mem->va;
 318         struct be_mcc_compl *compl = &mbox->compl;
 319
 320         /* wait for ready to be set */
 321         status = be_mbox_db_ready_wait(adapter, db);
 322         if (status != 0)
 323                 return status;
 324
 325         val |= MPU_MAILBOX_DB_HI_MASK;
 326         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 327         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 328         iowrite32(val, db);
 329
 330         /* wait for ready to be set */
 331         status = be_mbox_db_ready_wait(adapter, db);
 332         if (status != 0)
 333                 return status;
 334
 335         val = 0;
 336         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 337         val |= (u32)(mbox_mem->dma >> 4) << 2;
 338         iowrite32(val, db);
 339
 340         status = be_mbox_db_ready_wait(adapter, db);
 341         if (status != 0)
 342                 return status;
 343
 344         /* A cq entry has been made now */
 345         if (be_mcc_compl_is_new(compl)) {
 346                 status = be_mcc_compl_process(adapter, &mbox->compl);
 347                 be_mcc_compl_use(compl);
 348                 if (status)
 349                         return status;
 350         } else {
 351                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 352                 return -1;
 353         }
 354         return 0;
 355 }
 356
 357 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 358 {
 359         u32 sem;
 360
 361         if (lancer_chip(adapter))
 362                 sem  = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
 363         else
 364                 sem  = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 365
 366         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 367         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 368                 return -1;
 369         else
 370                 return 0;
 371 }
 372
 373 int be_cmd_POST(struct be_adapter *adapter)
 374 {
 375         u16 stage;
 376         int status, timeout = 0;
 377
 378         do {
 379                 status = be_POST_stage_get(adapter, &stage);
 380                 if (status) {
 381                         dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
 382                                 stage);
 383                         return -1;
 384                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 385                         set_current_state(TASK_INTERRUPTIBLE);
 386                         schedule_timeout(2 * HZ);
 387                         timeout += 2;
 388                 } else {
 389                         return 0;
 390                 }
 391         } while (timeout < 40);
 392
 393         dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
 394         return -1;
 395 }
 396
 397 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 398 {
 399         return wrb->payload.embedded_payload;
 400 }
 401
 402 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 403 {
 404         return &wrb->payload.sgl[0];
 405 }
 406
 407 /* Don't touch the hdr after it's prepared */
 408 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
 409                                 bool embedded, u8 sge_cnt, u32 opcode)
 410 {
 411         if (embedded)
 412                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 413         else
 414                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
 415                                 MCC_WRB_SGE_CNT_SHIFT;
 416         wrb->payload_length = payload_len;
 417         wrb->tag0 = opcode;
 418         be_dws_cpu_to_le(wrb, 8);
 419 }
 420
 421 /* Don't touch the hdr after it's prepared */
 422 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 423                                 u8 subsystem, u8 opcode, int cmd_len)
 424 {
 425         req_hdr->opcode = opcode;
 426         req_hdr->subsystem = subsystem;
 427         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 428         req_hdr->version = 0;
 429 }
 430
 431 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 432                         struct be_dma_mem *mem)
 433 {
 434         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 435         u64 dma = (u64)mem->dma;
 436
 437         for (i = 0; i < buf_pages; i++) {
 438                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 439                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 440                 dma += PAGE_SIZE_4K;
 441         }
 442 }
 443
 444 /* Converts interrupt delay in microseconds to multiplier value */
 445 static u32 eq_delay_to_mult(u32 usec_delay)
 446 {
 447 #define MAX_INTR_RATE                   651042
 448         const u32 round = 10;
 449         u32 multiplier;
 450
 451         if (usec_delay == 0)
 452                 multiplier = 0;
 453         else {
 454                 u32 interrupt_rate = 1000000 / usec_delay;
 455                 /* Max delay, corresponding to the lowest interrupt rate */
 456                 if (interrupt_rate == 0)
 457                         multiplier = 1023;
 458                 else {
 459                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 460                         multiplier /= interrupt_rate;
 461                         /* Round the multiplier to the closest value.*/
 462                         multiplier = (multiplier + round/2) / round;
 463                         multiplier = min(multiplier, (u32)1023);
 464                 }
 465         }
 466         return multiplier;
 467 }
 468
 469 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 470 {
 471         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 472         struct be_mcc_wrb *wrb
 473                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 474         memset(wrb, 0, sizeof(*wrb));
 475         return wrb;
 476 }
 477
 478 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 479 {
 480         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 481         struct be_mcc_wrb *wrb;
 482
 483         if (atomic_read(&mccq->used) >= mccq->len) {
 484                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 485                 return NULL;
 486         }
 487
 488         wrb = queue_head_node(mccq);
 489         queue_head_inc(mccq);
 490         atomic_inc(&mccq->used);
 491         memset(wrb, 0, sizeof(*wrb));
 492         return wrb;
 493 }
 494
 495 /* Tell fw we're about to start firing cmds by writing a
 496  * special pattern across the wrb hdr; uses mbox
 497  */
 498 int be_cmd_fw_init(struct be_adapter *adapter)
 499 {
 500         u8 *wrb;
 501         int status;
 502
 503         if (mutex_lock_interruptible(&adapter->mbox_lock))
 504                 return -1;
 505
 506         wrb = (u8 *)wrb_from_mbox(adapter);
 507         *wrb++ = 0xFF;
 508         *wrb++ = 0x12;
 509         *wrb++ = 0x34;
 510         *wrb++ = 0xFF;
 511         *wrb++ = 0xFF;
 512         *wrb++ = 0x56;
 513         *wrb++ = 0x78;
 514         *wrb = 0xFF;
 515
 516         status = be_mbox_notify_wait(adapter);
 517
 518         mutex_unlock(&adapter->mbox_lock);
 519         return status;
 520 }
 521
 522 /* Tell fw we're done with firing cmds by writing a
 523  * special pattern across the wrb hdr; uses mbox
 524  */
 525 int be_cmd_fw_clean(struct be_adapter *adapter)
 526 {
 527         u8 *wrb;
 528         int status;
 529
 530         if (adapter->eeh_err)
 531                 return -EIO;
 532
 533         if (mutex_lock_interruptible(&adapter->mbox_lock))
 534                 return -1;
 535
 536         wrb = (u8 *)wrb_from_mbox(adapter);
 537         *wrb++ = 0xFF;
 538         *wrb++ = 0xAA;
 539         *wrb++ = 0xBB;
 540         *wrb++ = 0xFF;
 541         *wrb++ = 0xFF;
 542         *wrb++ = 0xCC;
 543         *wrb++ = 0xDD;
 544         *wrb = 0xFF;
 545
 546         status = be_mbox_notify_wait(adapter);
 547
 548         mutex_unlock(&adapter->mbox_lock);
 549         return status;
 550 }
 551 int be_cmd_eq_create(struct be_adapter *adapter,
 552                 struct be_queue_info *eq, int eq_delay)
 553 {
 554         struct be_mcc_wrb *wrb;
 555         struct be_cmd_req_eq_create *req;
 556         struct be_dma_mem *q_mem = &eq->dma_mem;
 557         int status;
 558
 559         if (mutex_lock_interruptible(&adapter->mbox_lock))
 560                 return -1;
 561
 562         wrb = wrb_from_mbox(adapter);
 563         req = embedded_payload(wrb);
 564
 565         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
 566
 567         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 568                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
 569
 570         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 571
 572         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 573         /* 4byte eqe*/
 574         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 575         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 576                         __ilog2_u32(eq->len/256));
 577         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 578                         eq_delay_to_mult(eq_delay));
 579         be_dws_cpu_to_le(req->context, sizeof(req->context));
 580
 581         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 582
 583         status = be_mbox_notify_wait(adapter);
 584         if (!status) {
 585                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 586                 eq->id = le16_to_cpu(resp->eq_id);
 587                 eq->created = true;
 588         }
 589
 590         mutex_unlock(&adapter->mbox_lock);
 591         return status;
 592 }
 593
 594 /* Uses mbox */
 595 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 596                         u8 type, bool permanent, u32 if_handle)
 597 {
 598         struct be_mcc_wrb *wrb;
 599         struct be_cmd_req_mac_query *req;
 600         int status;
 601
 602         if (mutex_lock_interruptible(&adapter->mbox_lock))
 603                 return -1;
 604
 605         wrb = wrb_from_mbox(adapter);
 606         req = embedded_payload(wrb);
 607
 608         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 609                         OPCODE_COMMON_NTWK_MAC_QUERY);
 610
 611         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 612                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
 613
 614         req->type = type;
 615         if (permanent) {
 616                 req->permanent = 1;
 617         } else {
 618                 req->if_id = cpu_to_le16((u16) if_handle);
 619                 req->permanent = 0;
 620         }
 621
 622         status = be_mbox_notify_wait(adapter);
 623         if (!status) {
 624                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 625                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 626         }
 627
 628         mutex_unlock(&adapter->mbox_lock);
 629         return status;
 630 }
 631
 632 /* Uses synchronous MCCQ */
 633 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 634                 u32 if_id, u32 *pmac_id, u32 domain)
 635 {
 636         struct be_mcc_wrb *wrb;
 637         struct be_cmd_req_pmac_add *req;
 638         int status;
 639
 640         spin_lock_bh(&adapter->mcc_lock);
 641
 642         wrb = wrb_from_mccq(adapter);
 643         if (!wrb) {
 644                 status = -EBUSY;
 645                 goto err;
 646         }
 647         req = embedded_payload(wrb);
 648
 649         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 650                         OPCODE_COMMON_NTWK_PMAC_ADD);
 651
 652         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 653                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
 654
 655         req->hdr.domain = domain;
 656         req->if_id = cpu_to_le32(if_id);
 657         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 658
 659         status = be_mcc_notify_wait(adapter);
 660         if (!status) {
 661                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 662                 *pmac_id = le32_to_cpu(resp->pmac_id);
 663         }
 664
 665 err:
 666         spin_unlock_bh(&adapter->mcc_lock);
 667         return status;
 668 }
 669
 670 /* Uses synchronous MCCQ */
 671 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
 672 {
 673         struct be_mcc_wrb *wrb;
 674         struct be_cmd_req_pmac_del *req;
 675         int status;
 676
 677         spin_lock_bh(&adapter->mcc_lock);
 678
 679         wrb = wrb_from_mccq(adapter);
 680         if (!wrb) {
 681                 status = -EBUSY;
 682                 goto err;
 683         }
 684         req = embedded_payload(wrb);
 685
 686         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 687                         OPCODE_COMMON_NTWK_PMAC_DEL);
 688
 689         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 690                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
 691
 692         req->hdr.domain = dom;
 693         req->if_id = cpu_to_le32(if_id);
 694         req->pmac_id = cpu_to_le32(pmac_id);
 695
 696         status = be_mcc_notify_wait(adapter);
 697
 698 err:
 699         spin_unlock_bh(&adapter->mcc_lock);
 700         return status;
 701 }
 702
 703 /* Uses Mbox */
 704 int be_cmd_cq_create(struct be_adapter *adapter,
 705                 struct be_queue_info *cq, struct be_queue_info *eq,
 706                 bool sol_evts, bool no_delay, int coalesce_wm)
 707 {
 708         struct be_mcc_wrb *wrb;
 709         struct be_cmd_req_cq_create *req;
 710         struct be_dma_mem *q_mem = &cq->dma_mem;
 711         void *ctxt;
 712         int status;
 713
 714         if (mutex_lock_interruptible(&adapter->mbox_lock))
 715                 return -1;
 716
 717         wrb = wrb_from_mbox(adapter);
 718         req = embedded_payload(wrb);
 719         ctxt = &req->context;
 720
 721         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 722                         OPCODE_COMMON_CQ_CREATE);
 723
 724         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 725                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
 726
 727         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 728         if (lancer_chip(adapter)) {
 729                 req->hdr.version = 2;
 730                 req->page_size = 1; /* 1 for 4K */
 731                 AMAP_SET_BITS(struct amap_cq_context_lancer, coalescwm, ctxt,
 732                                                                 coalesce_wm);
 733                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 734                                                                 no_delay);
 735                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 736                                                 __ilog2_u32(cq->len/256));
 737                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 738                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 739                                                                 ctxt, 1);
 740                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 741                                                                 ctxt, eq->id);
 742                 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
 743         } else {
 744                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 745                                                                 coalesce_wm);
 746                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 747                                                                 ctxt, no_delay);
 748                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 749                                                 __ilog2_u32(cq->len/256));
 750                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 751                 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
 752                                                                 ctxt, sol_evts);
 753                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 754                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 755                 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
 756         }
 757
 758         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 759
 760         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 761
 762         status = be_mbox_notify_wait(adapter);
 763         if (!status) {
 764                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 765                 cq->id = le16_to_cpu(resp->cq_id);
 766                 cq->created = true;
 767         }
 768
 769         mutex_unlock(&adapter->mbox_lock);
 770
 771         return status;
 772 }
 773
 774 static u32 be_encoded_q_len(int q_len)
 775 {
 776         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 777         if (len_encoded == 16)
 778                 len_encoded = 0;
 779         return len_encoded;
 780 }
 781
 782 int be_cmd_mccq_create(struct be_adapter *adapter,
 783                         struct be_queue_info *mccq,
 784                         struct be_queue_info *cq)
 785 {
 786         struct be_mcc_wrb *wrb;
 787         struct be_cmd_req_mcc_create *req;
 788         struct be_dma_mem *q_mem = &mccq->dma_mem;
 789         void *ctxt;
 790         int status;
 791
 792         if (mutex_lock_interruptible(&adapter->mbox_lock))
 793                 return -1;
 794
 795         wrb = wrb_from_mbox(adapter);
 796         req = embedded_payload(wrb);
 797         ctxt = &req->context;
 798
 799         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 800                         OPCODE_COMMON_MCC_CREATE_EXT);
 801
 802         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 803                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
 804
 805         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 806         if (lancer_chip(adapter)) {
 807                 req->hdr.version = 1;
 808                 req->cq_id = cpu_to_le16(cq->id);
 809
 810                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
 811                                                 be_encoded_q_len(mccq->len));
 812                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
 813                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
 814                                                                 ctxt, cq->id);
 815                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
 816                                                                  ctxt, 1);
 817
 818         } else {
 819                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 820                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 821                                                 be_encoded_q_len(mccq->len));
 822                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 823         }
 824
 825         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
 826         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
 827         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 828
 829         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 830
 831         status = be_mbox_notify_wait(adapter);
 832         if (!status) {
 833                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 834                 mccq->id = le16_to_cpu(resp->id);
 835                 mccq->created = true;
 836         }
 837         mutex_unlock(&adapter->mbox_lock);
 838
 839         return status;
 840 }
 841
 842 int be_cmd_txq_create(struct be_adapter *adapter,
 843                         struct be_queue_info *txq,
 844                         struct be_queue_info *cq)
 845 {
 846         struct be_mcc_wrb *wrb;
 847         struct be_cmd_req_eth_tx_create *req;
 848         struct be_dma_mem *q_mem = &txq->dma_mem;
 849         void *ctxt;
 850         int status;
 851
 852         if (mutex_lock_interruptible(&adapter->mbox_lock))
 853                 return -1;
 854
 855         wrb = wrb_from_mbox(adapter);
 856         req = embedded_payload(wrb);
 857         ctxt = &req->context;
 858
 859         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 860                         OPCODE_ETH_TX_CREATE);
 861
 862         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
 863                 sizeof(*req));
 864
 865         if (lancer_chip(adapter)) {
 866                 req->hdr.version = 1;
 867                 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
 868                                         adapter->if_handle);
 869         }
 870
 871         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 872         req->ulp_num = BE_ULP1_NUM;
 873         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
 874
 875         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
 876                 be_encoded_q_len(txq->len));
 877         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
 878         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
 879
 880         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 881
 882         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 883
 884         status = be_mbox_notify_wait(adapter);
 885         if (!status) {
 886                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
 887                 txq->id = le16_to_cpu(resp->cid);
 888                 txq->created = true;
 889         }
 890
 891         mutex_unlock(&adapter->mbox_lock);
 892
 893         return status;
 894 }
 895
 896 /* Uses mbox */
 897 int be_cmd_rxq_create(struct be_adapter *adapter,
 898                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
 899                 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
 900 {
 901         struct be_mcc_wrb *wrb;
 902         struct be_cmd_req_eth_rx_create *req;
 903         struct be_dma_mem *q_mem = &rxq->dma_mem;
 904         int status;
 905
 906         if (mutex_lock_interruptible(&adapter->mbox_lock))
 907                 return -1;
 908
 909         wrb = wrb_from_mbox(adapter);
 910         req = embedded_payload(wrb);
 911
 912         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 913                         OPCODE_ETH_RX_CREATE);
 914
 915         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
 916                 sizeof(*req));
 917
 918         req->cq_id = cpu_to_le16(cq_id);
 919         req->frag_size = fls(frag_size) - 1;
 920         req->num_pages = 2;
 921         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 922         req->interface_id = cpu_to_le32(if_id);
 923         req->max_frame_size = cpu_to_le16(max_frame_size);
 924         req->rss_queue = cpu_to_le32(rss);
 925
 926         status = be_mbox_notify_wait(adapter);
 927         if (!status) {
 928                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
 929                 rxq->id = le16_to_cpu(resp->id);
 930                 rxq->created = true;
 931                 *rss_id = resp->rss_id;
 932         }
 933
 934         mutex_unlock(&adapter->mbox_lock);
 935
 936         return status;
 937 }
 938
 939 /* Generic destroyer function for all types of queues
 940  * Uses Mbox
 941  */
 942 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 943                 int queue_type)
 944 {
 945         struct be_mcc_wrb *wrb;
 946         struct be_cmd_req_q_destroy *req;
 947         u8 subsys = 0, opcode = 0;
 948         int status;
 949
 950         if (adapter->eeh_err)
 951                 return -EIO;
 952
 953         if (mutex_lock_interruptible(&adapter->mbox_lock))
 954                 return -1;
 955
 956         wrb = wrb_from_mbox(adapter);
 957         req = embedded_payload(wrb);
 958
 959         switch (queue_type) {
 960         case QTYPE_EQ:
 961                 subsys = CMD_SUBSYSTEM_COMMON;
 962                 opcode = OPCODE_COMMON_EQ_DESTROY;
 963                 break;
 964         case QTYPE_CQ:
 965                 subsys = CMD_SUBSYSTEM_COMMON;
 966                 opcode = OPCODE_COMMON_CQ_DESTROY;
 967                 break;
 968         case QTYPE_TXQ:
 969                 subsys = CMD_SUBSYSTEM_ETH;
 970                 opcode = OPCODE_ETH_TX_DESTROY;
 971                 break;
 972         case QTYPE_RXQ:
 973                 subsys = CMD_SUBSYSTEM_ETH;
 974                 opcode = OPCODE_ETH_RX_DESTROY;
 975                 break;
 976         case QTYPE_MCCQ:
 977                 subsys = CMD_SUBSYSTEM_COMMON;
 978                 opcode = OPCODE_COMMON_MCC_DESTROY;
 979                 break;
 980         default:
 981                 BUG();
 982         }
 983
 984         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
 985
 986         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
 987         req->id = cpu_to_le16(q->id);
 988
 989         status = be_mbox_notify_wait(adapter);
 990
 991         mutex_unlock(&adapter->mbox_lock);
 992
 993         return status;
 994 }
 995
 996 /* Create an rx filtering policy configuration on an i/f
 997  * Uses mbox
 998  */
 999 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1000                 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
1001                 u32 domain)
1002 {
1003         struct be_mcc_wrb *wrb;
1004         struct be_cmd_req_if_create *req;
1005         int status;
1006
1007         if (mutex_lock_interruptible(&adapter->mbox_lock))
1008                 return -1;
1009
1010         wrb = wrb_from_mbox(adapter);
1011         req = embedded_payload(wrb);
1012
1013         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1014                         OPCODE_COMMON_NTWK_INTERFACE_CREATE);
1015
1016         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1017                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
1018
1019         req->hdr.domain = domain;
1020         req->capability_flags = cpu_to_le32(cap_flags);
1021         req->enable_flags = cpu_to_le32(en_flags);
1022         req->pmac_invalid = pmac_invalid;
1023         if (!pmac_invalid)
1024                 memcpy(req->mac_addr, mac, ETH_ALEN);
1025
1026         status = be_mbox_notify_wait(adapter);
1027         if (!status) {
1028                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1029                 *if_handle = le32_to_cpu(resp->interface_id);
1030                 if (!pmac_invalid)
1031                         *pmac_id = le32_to_cpu(resp->pmac_id);
1032         }
1033
1034         mutex_unlock(&adapter->mbox_lock);
1035         return status;
1036 }
1037
1038 /* Uses mbox */
1039 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
1040 {
1041         struct be_mcc_wrb *wrb;
1042         struct be_cmd_req_if_destroy *req;
1043         int status;
1044
1045         if (adapter->eeh_err)
1046                 return -EIO;
1047
1048         if (mutex_lock_interruptible(&adapter->mbox_lock))
1049                 return -1;
1050
1051         wrb = wrb_from_mbox(adapter);
1052         req = embedded_payload(wrb);
1053
1054         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1055                         OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
1056
1057         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1058                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
1059
1060         req->hdr.domain = domain;
1061         req->interface_id = cpu_to_le32(interface_id);
1062
1063         status = be_mbox_notify_wait(adapter);
1064
1065         mutex_unlock(&adapter->mbox_lock);
1066
1067         return status;
1068 }
1069
1070 /* Get stats is a non embedded command: the request is not embedded inside
1071  * WRB but is a separate dma memory block
1072  * Uses asynchronous MCC
1073  */
1074 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1075 {
1076         struct be_mcc_wrb *wrb;
1077         struct be_cmd_req_get_stats *req;
1078         struct be_sge *sge;
1079         int status = 0;
1080
1081         if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1082                 be_cmd_get_die_temperature(adapter);
1083
1084         spin_lock_bh(&adapter->mcc_lock);
1085
1086         wrb = wrb_from_mccq(adapter);
1087         if (!wrb) {
1088                 status = -EBUSY;
1089                 goto err;
1090         }
1091         req = nonemb_cmd->va;
1092         sge = nonembedded_sgl(wrb);
1093
1094         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1095                         OPCODE_ETH_GET_STATISTICS);
1096
1097         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1098                 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
1099         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1100         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1101         sge->len = cpu_to_le32(nonemb_cmd->size);
1102
1103         be_mcc_notify(adapter);
1104         adapter->stats_cmd_sent = true;
1105
1106 err:
1107         spin_unlock_bh(&adapter->mcc_lock);
1108         return status;
1109 }
1110
1111 /* Uses synchronous mcc */
1112 int be_cmd_link_status_query(struct be_adapter *adapter,
1113                         bool *link_up, u8 *mac_speed, u16 *link_speed)
1114 {
1115         struct be_mcc_wrb *wrb;
1116         struct be_cmd_req_link_status *req;
1117         int status;
1118
1119         spin_lock_bh(&adapter->mcc_lock);
1120
1121         wrb = wrb_from_mccq(adapter);
1122         if (!wrb) {
1123                 status = -EBUSY;
1124                 goto err;
1125         }
1126         req = embedded_payload(wrb);
1127
1128         *link_up = false;
1129
1130         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1131                         OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1132
1133         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1134                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1135
1136         status = be_mcc_notify_wait(adapter);
1137         if (!status) {
1138                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1139                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1140                         *link_up = true;
1141                         *link_speed = le16_to_cpu(resp->link_speed);
1142                         *mac_speed = resp->mac_speed;
1143                 }
1144         }
1145
1146 err:
1147         spin_unlock_bh(&adapter->mcc_lock);
1148         return status;
1149 }
1150
1151 /* Uses synchronous mcc */
1152 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1153 {
1154         struct be_mcc_wrb *wrb;
1155         struct be_cmd_req_get_cntl_addnl_attribs *req;
1156         int status;
1157
1158         spin_lock_bh(&adapter->mcc_lock);
1159
1160         wrb = wrb_from_mccq(adapter);
1161         if (!wrb) {
1162                 status = -EBUSY;
1163                 goto err;
1164         }
1165         req = embedded_payload(wrb);
1166
1167         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1168                         OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES);
1169
1170         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1171                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req));
1172
1173         status = be_mcc_notify_wait(adapter);
1174         if (!status) {
1175                 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
1176                                                 embedded_payload(wrb);
1177                 adapter->drv_stats.be_on_die_temperature =
1178                                                 resp->on_die_temperature;
1179         }
1180         /* If IOCTL fails once, do not bother issuing it again */
1181         else
1182                 be_get_temp_freq = 0;
1183
1184 err:
1185         spin_unlock_bh(&adapter->mcc_lock);
1186         return status;
1187 }
1188
1189 /* Uses Mbox */
1190 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1191 {
1192         struct be_mcc_wrb *wrb;
1193         struct be_cmd_req_get_fw_version *req;
1194         int status;
1195
1196         if (mutex_lock_interruptible(&adapter->mbox_lock))
1197                 return -1;
1198
1199         wrb = wrb_from_mbox(adapter);
1200         req = embedded_payload(wrb);
1201
1202         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1203                         OPCODE_COMMON_GET_FW_VERSION);
1204
1205         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1206                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1207
1208         status = be_mbox_notify_wait(adapter);
1209         if (!status) {
1210                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1211                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1212         }
1213
1214         mutex_unlock(&adapter->mbox_lock);
1215         return status;
1216 }
1217
1218 /* set the EQ delay interval of an EQ to specified value
1219  * Uses async mcc
1220  */
1221 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1222 {
1223         struct be_mcc_wrb *wrb;
1224         struct be_cmd_req_modify_eq_delay *req;
1225         int status = 0;
1226
1227         spin_lock_bh(&adapter->mcc_lock);
1228
1229         wrb = wrb_from_mccq(adapter);
1230         if (!wrb) {
1231                 status = -EBUSY;
1232                 goto err;
1233         }
1234         req = embedded_payload(wrb);
1235
1236         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1237                         OPCODE_COMMON_MODIFY_EQ_DELAY);
1238
1239         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1240                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1241
1242         req->num_eq = cpu_to_le32(1);
1243         req->delay[0].eq_id = cpu_to_le32(eq_id);
1244         req->delay[0].phase = 0;
1245         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1246
1247         be_mcc_notify(adapter);
1248
1249 err:
1250         spin_unlock_bh(&adapter->mcc_lock);
1251         return status;
1252 }
1253
1254 /* Uses sycnhronous mcc */
1255 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1256                         u32 num, bool untagged, bool promiscuous)
1257 {
1258         struct be_mcc_wrb *wrb;
1259         struct be_cmd_req_vlan_config *req;
1260         int status;
1261
1262         spin_lock_bh(&adapter->mcc_lock);
1263
1264         wrb = wrb_from_mccq(adapter);
1265         if (!wrb) {
1266                 status = -EBUSY;
1267                 goto err;
1268         }
1269         req = embedded_payload(wrb);
1270
1271         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1272                         OPCODE_COMMON_NTWK_VLAN_CONFIG);
1273
1274         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1275                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1276
1277         req->interface_id = if_id;
1278         req->promiscuous = promiscuous;
1279         req->untagged = untagged;
1280         req->num_vlan = num;
1281         if (!promiscuous) {
1282                 memcpy(req->normal_vlan, vtag_array,
1283                         req->num_vlan * sizeof(vtag_array[0]));
1284         }
1285
1286         status = be_mcc_notify_wait(adapter);
1287
1288 err:
1289         spin_unlock_bh(&adapter->mcc_lock);
1290         return status;
1291 }
1292
1293 /* Uses MCC for this command as it may be called in BH context
1294  * Uses synchronous mcc
1295  */
1296 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1297 {
1298         struct be_mcc_wrb *wrb;
1299         struct be_cmd_req_promiscuous_config *req;
1300         int status;
1301
1302         spin_lock_bh(&adapter->mcc_lock);
1303
1304         wrb = wrb_from_mccq(adapter);
1305         if (!wrb) {
1306                 status = -EBUSY;
1307                 goto err;
1308         }
1309         req = embedded_payload(wrb);
1310
1311         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1312
1313         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1314                 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1315
1316         /* In FW versions X.102.149/X.101.487 and later,
1317          * the port setting associated only with the
1318          * issuing pci function will take effect
1319          */
1320         if (port_num)
1321                 req->port1_promiscuous = en;
1322         else
1323                 req->port0_promiscuous = en;
1324
1325         status = be_mcc_notify_wait(adapter);
1326
1327 err:
1328         spin_unlock_bh(&adapter->mcc_lock);
1329         return status;
1330 }
1331
1332 /*
1333  * Uses MCC for this command as it may be called in BH context
1334  * (mc == NULL) => multicast promiscuous
1335  */
1336 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1337                 struct net_device *netdev, struct be_dma_mem *mem)
1338 {
1339         struct be_mcc_wrb *wrb;
1340         struct be_cmd_req_mcast_mac_config *req = mem->va;
1341         struct be_sge *sge;
1342         int status;
1343
1344         spin_lock_bh(&adapter->mcc_lock);
1345
1346         wrb = wrb_from_mccq(adapter);
1347         if (!wrb) {
1348                 status = -EBUSY;
1349                 goto err;
1350         }
1351         sge = nonembedded_sgl(wrb);
1352         memset(req, 0, sizeof(*req));
1353
1354         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1355                         OPCODE_COMMON_NTWK_MULTICAST_SET);
1356         sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1357         sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1358         sge->len = cpu_to_le32(mem->size);
1359
1360         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1361                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1362
1363         req->interface_id = if_id;
1364         if (netdev) {
1365                 int i;
1366                 struct netdev_hw_addr *ha;
1367
1368                 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1369
1370                 i = 0;
1371                 netdev_for_each_mc_addr(ha, netdev)
1372                         memcpy(req->mac[i++].byte, ha->addr, ETH_ALEN);
1373         } else {
1374                 req->promiscuous = 1;
1375         }
1376
1377         status = be_mcc_notify_wait(adapter);
1378
1379 err:
1380         spin_unlock_bh(&adapter->mcc_lock);
1381         return status;
1382 }
1383
1384 /* Uses synchrounous mcc */
1385 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1386 {
1387         struct be_mcc_wrb *wrb;
1388         struct be_cmd_req_set_flow_control *req;
1389         int status;
1390
1391         spin_lock_bh(&adapter->mcc_lock);
1392
1393         wrb = wrb_from_mccq(adapter);
1394         if (!wrb) {
1395                 status = -EBUSY;
1396                 goto err;
1397         }
1398         req = embedded_payload(wrb);
1399
1400         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1401                         OPCODE_COMMON_SET_FLOW_CONTROL);
1402
1403         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1404                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1405
1406         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1407         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1408
1409         status = be_mcc_notify_wait(adapter);
1410
1411 err:
1412         spin_unlock_bh(&adapter->mcc_lock);
1413         return status;
1414 }
1415
1416 /* Uses sycn mcc */
1417 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1418 {
1419         struct be_mcc_wrb *wrb;
1420         struct be_cmd_req_get_flow_control *req;
1421         int status;
1422
1423         spin_lock_bh(&adapter->mcc_lock);
1424
1425         wrb = wrb_from_mccq(adapter);
1426         if (!wrb) {
1427                 status = -EBUSY;
1428                 goto err;
1429         }
1430         req = embedded_payload(wrb);
1431
1432         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1433                         OPCODE_COMMON_GET_FLOW_CONTROL);
1434
1435         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1436                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1437
1438         status = be_mcc_notify_wait(adapter);
1439         if (!status) {
1440                 struct be_cmd_resp_get_flow_control *resp =
1441                                                 embedded_payload(wrb);
1442                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1443                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1444         }
1445
1446 err:
1447         spin_unlock_bh(&adapter->mcc_lock);
1448         return status;
1449 }
1450
1451 /* Uses mbox */
1452 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1453                 u32 *mode, u32 *caps)
1454 {
1455         struct be_mcc_wrb *wrb;
1456         struct be_cmd_req_query_fw_cfg *req;
1457         int status;
1458
1459         if (mutex_lock_interruptible(&adapter->mbox_lock))
1460                 return -1;
1461
1462         wrb = wrb_from_mbox(adapter);
1463         req = embedded_payload(wrb);
1464
1465         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1466                         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1467
1468         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1469                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1470
1471         status = be_mbox_notify_wait(adapter);
1472         if (!status) {
1473                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1474                 *port_num = le32_to_cpu(resp->phys_port);
1475                 *mode = le32_to_cpu(resp->function_mode);
1476                 *caps = le32_to_cpu(resp->function_caps);
1477         }
1478
1479         mutex_unlock(&adapter->mbox_lock);
1480         return status;
1481 }
1482
1483 /* Uses mbox */
1484 int be_cmd_reset_function(struct be_adapter *adapter)
1485 {
1486         struct be_mcc_wrb *wrb;
1487         struct be_cmd_req_hdr *req;
1488         int status;
1489
1490         if (mutex_lock_interruptible(&adapter->mbox_lock))
1491                 return -1;
1492
1493         wrb = wrb_from_mbox(adapter);
1494         req = embedded_payload(wrb);
1495
1496         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1497                         OPCODE_COMMON_FUNCTION_RESET);
1498
1499         be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1500                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1501
1502         status = be_mbox_notify_wait(adapter);
1503
1504         mutex_unlock(&adapter->mbox_lock);
1505         return status;
1506 }
1507
1508 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1509 {
1510         struct be_mcc_wrb *wrb;
1511         struct be_cmd_req_rss_config *req;
1512         u32 myhash[10];
1513         int status;
1514
1515         if (mutex_lock_interruptible(&adapter->mbox_lock))
1516                 return -1;
1517
1518         wrb = wrb_from_mbox(adapter);
1519         req = embedded_payload(wrb);
1520
1521         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1522                 OPCODE_ETH_RSS_CONFIG);
1523
1524         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1525                 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1526
1527         req->if_id = cpu_to_le32(adapter->if_handle);
1528         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1529         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1530         memcpy(req->cpu_table, rsstable, table_size);
1531         memcpy(req->hash, myhash, sizeof(myhash));
1532         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1533
1534         status = be_mbox_notify_wait(adapter);
1535
1536         mutex_unlock(&adapter->mbox_lock);
1537         return status;
1538 }
1539
1540 /* Uses sync mcc */
1541 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1542                         u8 bcn, u8 sts, u8 state)
1543 {
1544         struct be_mcc_wrb *wrb;
1545         struct be_cmd_req_enable_disable_beacon *req;
1546         int status;
1547
1548         spin_lock_bh(&adapter->mcc_lock);
1549
1550         wrb = wrb_from_mccq(adapter);
1551         if (!wrb) {
1552                 status = -EBUSY;
1553                 goto err;
1554         }
1555         req = embedded_payload(wrb);
1556
1557         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1558                         OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1559
1560         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1561                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1562
1563         req->port_num = port_num;
1564         req->beacon_state = state;
1565         req->beacon_duration = bcn;
1566         req->status_duration = sts;
1567
1568         status = be_mcc_notify_wait(adapter);
1569
1570 err:
1571         spin_unlock_bh(&adapter->mcc_lock);
1572         return status;
1573 }
1574
1575 /* Uses sync mcc */
1576 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1577 {
1578         struct be_mcc_wrb *wrb;
1579         struct be_cmd_req_get_beacon_state *req;
1580         int status;
1581
1582         spin_lock_bh(&adapter->mcc_lock);
1583
1584         wrb = wrb_from_mccq(adapter);
1585         if (!wrb) {
1586                 status = -EBUSY;
1587                 goto err;
1588         }
1589         req = embedded_payload(wrb);
1590
1591         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1592                         OPCODE_COMMON_GET_BEACON_STATE);
1593
1594         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1595                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1596
1597         req->port_num = port_num;
1598
1599         status = be_mcc_notify_wait(adapter);
1600         if (!status) {
1601                 struct be_cmd_resp_get_beacon_state *resp =
1602                                                 embedded_payload(wrb);
1603                 *state = resp->beacon_state;
1604         }
1605
1606 err:
1607         spin_unlock_bh(&adapter->mcc_lock);
1608         return status;
1609 }
1610
1611 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1612                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1613 {
1614         struct be_mcc_wrb *wrb;
1615         struct be_cmd_write_flashrom *req;
1616         struct be_sge *sge;
1617         int status;
1618
1619         spin_lock_bh(&adapter->mcc_lock);
1620         adapter->flash_status = 0;
1621
1622         wrb = wrb_from_mccq(adapter);
1623         if (!wrb) {
1624                 status = -EBUSY;
1625                 goto err_unlock;
1626         }
1627         req = cmd->va;
1628         sge = nonembedded_sgl(wrb);
1629
1630         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1631                         OPCODE_COMMON_WRITE_FLASHROM);
1632         wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1633
1634         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1635                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1636         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1637         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1638         sge->len = cpu_to_le32(cmd->size);
1639
1640         req->params.op_type = cpu_to_le32(flash_type);
1641         req->params.op_code = cpu_to_le32(flash_opcode);
1642         req->params.data_buf_size = cpu_to_le32(buf_size);
1643
1644         be_mcc_notify(adapter);
1645         spin_unlock_bh(&adapter->mcc_lock);
1646
1647         if (!wait_for_completion_timeout(&adapter->flash_compl,
1648                         msecs_to_jiffies(12000)))
1649                 status = -1;
1650         else
1651                 status = adapter->flash_status;
1652
1653         return status;
1654
1655 err_unlock:
1656         spin_unlock_bh(&adapter->mcc_lock);
1657         return status;
1658 }
1659
1660 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1661                          int offset)
1662 {
1663         struct be_mcc_wrb *wrb;
1664         struct be_cmd_write_flashrom *req;
1665         int status;
1666
1667         spin_lock_bh(&adapter->mcc_lock);
1668
1669         wrb = wrb_from_mccq(adapter);
1670         if (!wrb) {
1671                 status = -EBUSY;
1672                 goto err;
1673         }
1674         req = embedded_payload(wrb);
1675
1676         be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1677                         OPCODE_COMMON_READ_FLASHROM);
1678
1679         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1680                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1681
1682         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1683         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1684         req->params.offset = cpu_to_le32(offset);
1685         req->params.data_buf_size = cpu_to_le32(0x4);
1686
1687         status = be_mcc_notify_wait(adapter);
1688         if (!status)
1689                 memcpy(flashed_crc, req->params.data_buf, 4);
1690
1691 err:
1692         spin_unlock_bh(&adapter->mcc_lock);
1693         return status;
1694 }
1695
1696 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1697                                 struct be_dma_mem *nonemb_cmd)
1698 {
1699         struct be_mcc_wrb *wrb;
1700         struct be_cmd_req_acpi_wol_magic_config *req;
1701         struct be_sge *sge;
1702         int status;
1703
1704         spin_lock_bh(&adapter->mcc_lock);
1705
1706         wrb = wrb_from_mccq(adapter);
1707         if (!wrb) {
1708                 status = -EBUSY;
1709                 goto err;
1710         }
1711         req = nonemb_cmd->va;
1712         sge = nonembedded_sgl(wrb);
1713
1714         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1715                         OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1716
1717         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1718                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1719         memcpy(req->magic_mac, mac, ETH_ALEN);
1720
1721         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1722         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1723         sge->len = cpu_to_le32(nonemb_cmd->size);
1724
1725         status = be_mcc_notify_wait(adapter);
1726
1727 err:
1728         spin_unlock_bh(&adapter->mcc_lock);
1729         return status;
1730 }
1731
1732 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1733                         u8 loopback_type, u8 enable)
1734 {
1735         struct be_mcc_wrb *wrb;
1736         struct be_cmd_req_set_lmode *req;
1737         int status;
1738
1739         spin_lock_bh(&adapter->mcc_lock);
1740
1741         wrb = wrb_from_mccq(adapter);
1742         if (!wrb) {
1743                 status = -EBUSY;
1744                 goto err;
1745         }
1746
1747         req = embedded_payload(wrb);
1748
1749         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1750                                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1751
1752         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1753                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1754                         sizeof(*req));
1755
1756         req->src_port = port_num;
1757         req->dest_port = port_num;
1758         req->loopback_type = loopback_type;
1759         req->loopback_state = enable;
1760
1761         status = be_mcc_notify_wait(adapter);
1762 err:
1763         spin_unlock_bh(&adapter->mcc_lock);
1764         return status;
1765 }
1766
1767 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1768                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1769 {
1770         struct be_mcc_wrb *wrb;
1771         struct be_cmd_req_loopback_test *req;
1772         int status;
1773
1774         spin_lock_bh(&adapter->mcc_lock);
1775
1776         wrb = wrb_from_mccq(adapter);
1777         if (!wrb) {
1778                 status = -EBUSY;
1779                 goto err;
1780         }
1781
1782         req = embedded_payload(wrb);
1783
1784         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1785                                 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1786
1787         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1788                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1789         req->hdr.timeout = cpu_to_le32(4);
1790
1791         req->pattern = cpu_to_le64(pattern);
1792         req->src_port = cpu_to_le32(port_num);
1793         req->dest_port = cpu_to_le32(port_num);
1794         req->pkt_size = cpu_to_le32(pkt_size);
1795         req->num_pkts = cpu_to_le32(num_pkts);
1796         req->loopback_type = cpu_to_le32(loopback_type);
1797
1798         status = be_mcc_notify_wait(adapter);
1799         if (!status) {
1800                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1801                 status = le32_to_cpu(resp->status);
1802         }
1803
1804 err:
1805         spin_unlock_bh(&adapter->mcc_lock);
1806         return status;
1807 }
1808
1809 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1810                                 u32 byte_cnt, struct be_dma_mem *cmd)
1811 {
1812         struct be_mcc_wrb *wrb;
1813         struct be_cmd_req_ddrdma_test *req;
1814         struct be_sge *sge;
1815         int status;
1816         int i, j = 0;
1817
1818         spin_lock_bh(&adapter->mcc_lock);
1819
1820         wrb = wrb_from_mccq(adapter);
1821         if (!wrb) {
1822                 status = -EBUSY;
1823                 goto err;
1824         }
1825         req = cmd->va;
1826         sge = nonembedded_sgl(wrb);
1827         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1828                                 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1829         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1830                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1831
1832         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1833         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1834         sge->len = cpu_to_le32(cmd->size);
1835
1836         req->pattern = cpu_to_le64(pattern);
1837         req->byte_count = cpu_to_le32(byte_cnt);
1838         for (i = 0; i < byte_cnt; i++) {
1839                 req->snd_buff[i] = (u8)(pattern >> (j*8));
1840                 j++;
1841                 if (j > 7)
1842                         j = 0;
1843         }
1844
1845         status = be_mcc_notify_wait(adapter);
1846
1847         if (!status) {
1848                 struct be_cmd_resp_ddrdma_test *resp;
1849                 resp = cmd->va;
1850                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1851                                 resp->snd_err) {
1852                         status = -1;
1853                 }
1854         }
1855
1856 err:
1857         spin_unlock_bh(&adapter->mcc_lock);
1858         return status;
1859 }
1860
1861 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1862                                 struct be_dma_mem *nonemb_cmd)
1863 {
1864         struct be_mcc_wrb *wrb;
1865         struct be_cmd_req_seeprom_read *req;
1866         struct be_sge *sge;
1867         int status;
1868
1869         spin_lock_bh(&adapter->mcc_lock);
1870
1871         wrb = wrb_from_mccq(adapter);
1872         if (!wrb) {
1873                 status = -EBUSY;
1874                 goto err;
1875         }
1876         req = nonemb_cmd->va;
1877         sge = nonembedded_sgl(wrb);
1878
1879         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1880                         OPCODE_COMMON_SEEPROM_READ);
1881
1882         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1883                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1884
1885         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1886         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1887         sge->len = cpu_to_le32(nonemb_cmd->size);
1888
1889         status = be_mcc_notify_wait(adapter);
1890
1891 err:
1892         spin_unlock_bh(&adapter->mcc_lock);
1893         return status;
1894 }
1895
1896 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
1897 {
1898         struct be_mcc_wrb *wrb;
1899         struct be_cmd_req_get_phy_info *req;
1900         struct be_sge *sge;
1901         int status;
1902
1903         spin_lock_bh(&adapter->mcc_lock);
1904
1905         wrb = wrb_from_mccq(adapter);
1906         if (!wrb) {
1907                 status = -EBUSY;
1908                 goto err;
1909         }
1910
1911         req = cmd->va;
1912         sge = nonembedded_sgl(wrb);
1913
1914         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1915                                 OPCODE_COMMON_GET_PHY_DETAILS);
1916
1917         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1918                         OPCODE_COMMON_GET_PHY_DETAILS,
1919                         sizeof(*req));
1920
1921         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1922         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1923         sge->len = cpu_to_le32(cmd->size);
1924
1925         status = be_mcc_notify_wait(adapter);
1926 err:
1927         spin_unlock_bh(&adapter->mcc_lock);
1928         return status;
1929 }
1930
1931 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
1932 {
1933         struct be_mcc_wrb *wrb;
1934         struct be_cmd_req_set_qos *req;
1935         int status;
1936
1937         spin_lock_bh(&adapter->mcc_lock);
1938
1939         wrb = wrb_from_mccq(adapter);
1940         if (!wrb) {
1941                 status = -EBUSY;
1942                 goto err;
1943         }
1944
1945         req = embedded_payload(wrb);
1946
1947         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1948                                 OPCODE_COMMON_SET_QOS);
1949
1950         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1951                         OPCODE_COMMON_SET_QOS, sizeof(*req));
1952
1953         req->hdr.domain = domain;
1954         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
1955         req->max_bps_nic = cpu_to_le32(bps);
1956
1957         status = be_mcc_notify_wait(adapter);
1958
1959 err:
1960         spin_unlock_bh(&adapter->mcc_lock);
1961         return status;
1962 }
1963
1964 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
1965 {
1966         struct be_mcc_wrb *wrb;
1967         struct be_cmd_req_cntl_attribs *req;
1968         struct be_cmd_resp_cntl_attribs *resp;
1969         struct be_sge *sge;
1970         int status;
1971         int payload_len = max(sizeof(*req), sizeof(*resp));
1972         struct mgmt_controller_attrib *attribs;
1973         struct be_dma_mem attribs_cmd;
1974
1975         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
1976         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
1977         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
1978                                                 &attribs_cmd.dma);
1979         if (!attribs_cmd.va) {
1980                 dev_err(&adapter->pdev->dev,
1981                                 "Memory allocation failure\n");
1982                 return -ENOMEM;
1983         }
1984
1985         if (mutex_lock_interruptible(&adapter->mbox_lock))
1986                 return -1;
1987
1988         wrb = wrb_from_mbox(adapter);
1989         if (!wrb) {
1990                 status = -EBUSY;
1991                 goto err;
1992         }
1993         req = attribs_cmd.va;
1994         sge = nonembedded_sgl(wrb);
1995
1996         be_wrb_hdr_prepare(wrb, payload_len, false, 1,
1997                         OPCODE_COMMON_GET_CNTL_ATTRIBUTES);
1998         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1999                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len);
2000         sge->pa_hi = cpu_to_le32(upper_32_bits(attribs_cmd.dma));
2001         sge->pa_lo = cpu_to_le32(attribs_cmd.dma & 0xFFFFFFFF);
2002         sge->len = cpu_to_le32(attribs_cmd.size);
2003
2004         status = be_mbox_notify_wait(adapter);
2005         if (!status) {
2006                 attribs = (struct mgmt_controller_attrib *)( attribs_cmd.va +
2007                                         sizeof(struct be_cmd_resp_hdr));
2008                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2009         }
2010
2011 err:
2012         mutex_unlock(&adapter->mbox_lock);
2013         pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2014                                         attribs_cmd.dma);
2015         return status;
2016 }
2017
2018 /* Uses mbox */
2019 int be_cmd_check_native_mode(struct be_adapter *adapter)
2020 {
2021         struct be_mcc_wrb *wrb;
2022         struct be_cmd_req_set_func_cap *req;
2023         int status;
2024
2025         if (mutex_lock_interruptible(&adapter->mbox_lock))
2026                 return -1;
2027
2028         wrb = wrb_from_mbox(adapter);
2029         if (!wrb) {
2030                 status = -EBUSY;
2031                 goto err;
2032         }
2033
2034         req = embedded_payload(wrb);
2035
2036         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2037                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP);
2038
2039         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2040                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req));
2041
2042         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2043                                 CAPABILITY_BE3_NATIVE_ERX_API);
2044         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2045
2046         status = be_mbox_notify_wait(adapter);
2047         if (!status) {
2048                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2049                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2050                                         CAPABILITY_BE3_NATIVE_ERX_API;
2051         }
2052 err:
2053         mutex_unlock(&adapter->mbox_lock);
2054         return status;
2055 }