drivers/mtd/nand/pxa3xx_nand.c

   1 /*
   2  * drivers/mtd/nand/pxa3xx_nand.c
   3  *
   4  * Copyright © 2005 Intel Corporation
   5  * Copyright © 2006 Marvell International Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/delay.h>
  18 #include <linux/clk.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/io.h>
  23 #include <linux/irq.h>
  24 #include <linux/slab.h>
  25
  26 #include <mach/dma.h>
  27 #include <plat/pxa3xx_nand.h>
  28
  29 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
  30
  31 /* registers and bit definitions */
  32 #define NDCR            (0x00) /* Control register */
  33 #define NDTR0CS0        (0x04) /* Timing Parameter 0 for CS0 */
  34 #define NDTR1CS0        (0x0C) /* Timing Parameter 1 for CS0 */
  35 #define NDSR            (0x14) /* Status Register */
  36 #define NDPCR           (0x18) /* Page Count Register */
  37 #define NDBDR0          (0x1C) /* Bad Block Register 0 */
  38 #define NDBDR1          (0x20) /* Bad Block Register 1 */
  39 #define NDDB            (0x40) /* Data Buffer */
  40 #define NDCB0           (0x48) /* Command Buffer0 */
  41 #define NDCB1           (0x4C) /* Command Buffer1 */
  42 #define NDCB2           (0x50) /* Command Buffer2 */
  43
  44 #define NDCR_SPARE_EN           (0x1 << 31)
  45 #define NDCR_ECC_EN             (0x1 << 30)
  46 #define NDCR_DMA_EN             (0x1 << 29)
  47 #define NDCR_ND_RUN             (0x1 << 28)
  48 #define NDCR_DWIDTH_C           (0x1 << 27)
  49 #define NDCR_DWIDTH_M           (0x1 << 26)
  50 #define NDCR_PAGE_SZ            (0x1 << 24)
  51 #define NDCR_NCSX               (0x1 << 23)
  52 #define NDCR_ND_MODE            (0x3 << 21)
  53 #define NDCR_NAND_MODE          (0x0)
  54 #define NDCR_CLR_PG_CNT         (0x1 << 20)
  55 #define NDCR_CLR_ECC            (0x1 << 19)
  56 #define NDCR_RD_ID_CNT_MASK     (0x7 << 16)
  57 #define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  58
  59 #define NDCR_RA_START           (0x1 << 15)
  60 #define NDCR_PG_PER_BLK         (0x1 << 14)
  61 #define NDCR_ND_ARB_EN          (0x1 << 12)
  62
  63 #define NDSR_MASK               (0xfff)
  64 #define NDSR_RDY                (0x1 << 11)
  65 #define NDSR_CS0_PAGED          (0x1 << 10)
  66 #define NDSR_CS1_PAGED          (0x1 << 9)
  67 #define NDSR_CS0_CMDD           (0x1 << 8)
  68 #define NDSR_CS1_CMDD           (0x1 << 7)
  69 #define NDSR_CS0_BBD            (0x1 << 6)
  70 #define NDSR_CS1_BBD            (0x1 << 5)
  71 #define NDSR_DBERR              (0x1 << 4)
  72 #define NDSR_SBERR              (0x1 << 3)
  73 #define NDSR_WRDREQ             (0x1 << 2)
  74 #define NDSR_RDDREQ             (0x1 << 1)
  75 #define NDSR_WRCMDREQ           (0x1)
  76
  77 #define NDCB0_AUTO_RS           (0x1 << 25)
  78 #define NDCB0_CSEL              (0x1 << 24)
  79 #define NDCB0_CMD_TYPE_MASK     (0x7 << 21)
  80 #define NDCB0_CMD_TYPE(x)       (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  81 #define NDCB0_NC                (0x1 << 20)
  82 #define NDCB0_DBC               (0x1 << 19)
  83 #define NDCB0_ADDR_CYC_MASK     (0x7 << 16)
  84 #define NDCB0_ADDR_CYC(x)       (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  85 #define NDCB0_CMD2_MASK         (0xff << 8)
  86 #define NDCB0_CMD1_MASK         (0xff)
  87 #define NDCB0_ADDR_CYC_SHIFT    (16)
  88
  89 /* macros for registers read/write */
  90 #define nand_writel(info, off, val)     \
  91         __raw_writel((val), (info)->mmio_base + (off))
  92
  93 #define nand_readl(info, off)           \
  94         __raw_readl((info)->mmio_base + (off))
  95
  96 /* error code and state */
  97 enum {
  98         ERR_NONE        = 0,
  99         ERR_DMABUSERR   = -1,
 100         ERR_SENDCMD     = -2,
 101         ERR_DBERR       = -3,
 102         ERR_BBERR       = -4,
 103         ERR_SBERR       = -5,
 104 };
 105
 106 enum {
 107         STATE_READY     = 0,
 108         STATE_CMD_HANDLE,
 109         STATE_DMA_READING,
 110         STATE_DMA_WRITING,
 111         STATE_DMA_DONE,
 112         STATE_PIO_READING,
 113         STATE_PIO_WRITING,
 114 };
 115
 116 struct pxa3xx_nand_info {
 117         struct nand_chip        nand_chip;
 118
 119         struct platform_device   *pdev;
 120         struct pxa3xx_nand_cmdset *cmdset;
 121
 122         struct clk              *clk;
 123         void __iomem            *mmio_base;
 124         unsigned long           mmio_phys;
 125
 126         unsigned int            buf_start;
 127         unsigned int            buf_count;
 128
 129         /* DMA information */
 130         int                     drcmr_dat;
 131         int                     drcmr_cmd;
 132
 133         unsigned char           *data_buff;
 134         unsigned char           *oob_buff;
 135         dma_addr_t              data_buff_phys;
 136         size_t                  data_buff_size;
 137         int                     data_dma_ch;
 138         struct pxa_dma_desc     *data_desc;
 139         dma_addr_t              data_desc_addr;
 140
 141         uint32_t                reg_ndcr;
 142
 143         /* saved column/page_addr during CMD_SEQIN */
 144         int                     seqin_column;
 145         int                     seqin_page_addr;
 146
 147         /* relate to the command */
 148         unsigned int            state;
 149
 150         int                     use_ecc;        /* use HW ECC ? */
 151         int                     use_dma;        /* use DMA ? */
 152
 153         unsigned int            page_size;      /* page size of attached chip */
 154         unsigned int            data_size;      /* data size in FIFO */
 155         int                     retcode;
 156         struct completion       cmd_complete;
 157
 158         /* generated NDCBx register values */
 159         uint32_t                ndcb0;
 160         uint32_t                ndcb1;
 161         uint32_t                ndcb2;
 162
 163         /* timing calcuted from setting */
 164         uint32_t                ndtr0cs0;
 165         uint32_t                ndtr1cs0;
 166
 167         /* calculated from pxa3xx_nand_flash data */
 168         size_t          oob_size;
 169         size_t          read_id_bytes;
 170
 171         unsigned int    col_addr_cycles;
 172         unsigned int    row_addr_cycles;
 173 };
 174
 175 static int use_dma = 1;
 176 module_param(use_dma, bool, 0444);
 177 MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
 178
 179 /*
 180  * Default NAND flash controller configuration setup by the
 181  * bootloader. This configuration is used only when pdata->keep_config is set
 182  */
 183 static struct pxa3xx_nand_cmdset default_cmdset = {
 184         .read1          = 0x3000,
 185         .read2          = 0x0050,
 186         .program        = 0x1080,
 187         .read_status    = 0x0070,
 188         .read_id        = 0x0090,
 189         .erase          = 0xD060,
 190         .reset          = 0x00FF,
 191         .lock           = 0x002A,
 192         .unlock         = 0x2423,
 193         .lock_status    = 0x007A,
 194 };
 195
 196 static struct pxa3xx_nand_timing timing[] = {
 197         { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
 198         { 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 199         { 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 200         { 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
 201 };
 202
 203 static struct pxa3xx_nand_flash builtin_flash_types[] = {
 204         {      0,   0, 2048,  8,  8,    0, &default_cmdset, &timing[0] },
 205         { 0x46ec,  32,  512, 16, 16, 4096, &default_cmdset, &timing[1] },
 206         { 0xdaec,  64, 2048,  8,  8, 2048, &default_cmdset, &timing[1] },
 207         { 0xd7ec, 128, 4096,  8,  8, 8192, &default_cmdset, &timing[1] },
 208         { 0xa12c,  64, 2048,  8,  8, 1024, &default_cmdset, &timing[2] },
 209         { 0xb12c,  64, 2048, 16, 16, 1024, &default_cmdset, &timing[2] },
 210         { 0xdc2c,  64, 2048,  8,  8, 4096, &default_cmdset, &timing[2] },
 211         { 0xcc2c,  64, 2048, 16, 16, 4096, &default_cmdset, &timing[2] },
 212         { 0xba20,  64, 2048, 16, 16, 2048, &default_cmdset, &timing[3] },
 213 };
 214
 215 /* Define a default flash type setting serve as flash detecting only */
 216 #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
 217
 218 #define NDTR0_tCH(c)    (min((c), 7) << 19)
 219 #define NDTR0_tCS(c)    (min((c), 7) << 16)
 220 #define NDTR0_tWH(c)    (min((c), 7) << 11)
 221 #define NDTR0_tWP(c)    (min((c), 7) << 8)
 222 #define NDTR0_tRH(c)    (min((c), 7) << 3)
 223 #define NDTR0_tRP(c)    (min((c), 7) << 0)
 224
 225 #define NDTR1_tR(c)     (min((c), 65535) << 16)
 226 #define NDTR1_tWHR(c)   (min((c), 15) << 4)
 227 #define NDTR1_tAR(c)    (min((c), 15) << 0)
 228
 229 /* convert nano-seconds to nand flash controller clock cycles */
 230 #define ns2cycle(ns, clk)       (int)((ns) * (clk / 1000000) / 1000)
 231
 232 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
 233                                    const struct pxa3xx_nand_timing *t)
 234 {
 235         unsigned long nand_clk = clk_get_rate(info->clk);
 236         uint32_t ndtr0, ndtr1;
 237
 238         ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
 239                 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
 240                 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
 241                 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
 242                 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
 243                 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
 244
 245         ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
 246                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
 247                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
 248
 249         info->ndtr0cs0 = ndtr0;
 250         info->ndtr1cs0 = ndtr1;
 251         nand_writel(info, NDTR0CS0, ndtr0);
 252         nand_writel(info, NDTR1CS0, ndtr1);
 253 }
 254
 255 #define WAIT_EVENT_TIMEOUT      10
 256
 257 static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
 258 {
 259         int timeout = WAIT_EVENT_TIMEOUT;
 260         uint32_t ndsr;
 261
 262         while (timeout--) {
 263                 ndsr = nand_readl(info, NDSR) & NDSR_MASK;
 264                 if (ndsr & event) {
 265                         nand_writel(info, NDSR, ndsr);
 266                         return 0;
 267                 }
 268                 udelay(10);
 269         }
 270
 271         return -ETIMEDOUT;
 272 }
 273
 274 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 275 {
 276         int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
 277
 278         info->data_size = info->page_size;
 279         if (!oob_enable) {
 280                 info->oob_size = 0;
 281                 return;
 282         }
 283
 284         switch (info->page_size) {
 285         case 2048:
 286                 info->oob_size = (info->use_ecc) ? 40 : 64;
 287                 break;
 288         case 512:
 289                 info->oob_size = (info->use_ecc) ? 8 : 16;
 290                 break;
 291         }
 292 }
 293
 294 static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
 295                 uint16_t cmd, int column, int page_addr)
 296 {
 297         const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
 298         pxa3xx_set_datasize(info);
 299
 300         /* generate values for NDCBx registers */
 301         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
 302         info->ndcb1 = 0;
 303         info->ndcb2 = 0;
 304         info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
 305
 306         if (info->col_addr_cycles == 2) {
 307                 /* large block, 2 cycles for column address
 308                  * row address starts from 3rd cycle
 309                  */
 310                 info->ndcb1 |= page_addr << 16;
 311                 if (info->row_addr_cycles == 3)
 312                         info->ndcb2 = (page_addr >> 16) & 0xff;
 313         } else
 314                 /* small block, 1 cycles for column address
 315                  * row address starts from 2nd cycle
 316                  */
 317                 info->ndcb1 = page_addr << 8;
 318
 319         if (cmd == cmdset->program)
 320                 info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
 321
 322         return 0;
 323 }
 324
 325 static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
 326                         uint16_t cmd, int page_addr)
 327 {
 328         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
 329         info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
 330         info->ndcb1 = page_addr;
 331         info->ndcb2 = 0;
 332         return 0;
 333 }
 334
 335 static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
 336 {
 337         const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
 338
 339         info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
 340         info->ndcb1 = 0;
 341         info->ndcb2 = 0;
 342
 343         info->oob_size = 0;
 344         if (cmd == cmdset->read_id) {
 345                 info->ndcb0 |= NDCB0_CMD_TYPE(3);
 346                 info->data_size = 8;
 347         } else if (cmd == cmdset->read_status) {
 348                 info->ndcb0 |= NDCB0_CMD_TYPE(4);
 349                 info->data_size = 8;
 350         } else if (cmd == cmdset->reset || cmd == cmdset->lock ||
 351                    cmd == cmdset->unlock) {
 352                 info->ndcb0 |= NDCB0_CMD_TYPE(5);
 353         } else
 354                 return -EINVAL;
 355
 356         return 0;
 357 }
 358
 359 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 360 {
 361         uint32_t ndcr;
 362
 363         ndcr = nand_readl(info, NDCR);
 364         nand_writel(info, NDCR, ndcr & ~int_mask);
 365 }
 366
 367 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 368 {
 369         uint32_t ndcr;
 370
 371         ndcr = nand_readl(info, NDCR);
 372         nand_writel(info, NDCR, ndcr | int_mask);
 373 }
 374
 375 /* NOTE: it is a must to set ND_RUN firstly, then write command buffer
 376  * otherwise, it does not work
 377  */
 378 static int write_cmd(struct pxa3xx_nand_info *info)
 379 {
 380         uint32_t ndcr;
 381
 382         /* clear status bits and run */
 383         nand_writel(info, NDSR, NDSR_MASK);
 384
 385         ndcr = info->reg_ndcr;
 386
 387         ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
 388         ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
 389         ndcr |= NDCR_ND_RUN;
 390
 391         nand_writel(info, NDCR, ndcr);
 392
 393         if (wait_for_event(info, NDSR_WRCMDREQ)) {
 394                 printk(KERN_ERR "timed out writing command\n");
 395                 return -ETIMEDOUT;
 396         }
 397
 398         nand_writel(info, NDCB0, info->ndcb0);
 399         nand_writel(info, NDCB0, info->ndcb1);
 400         nand_writel(info, NDCB0, info->ndcb2);
 401         return 0;
 402 }
 403
 404 static int handle_data_pio(struct pxa3xx_nand_info *info)
 405 {
 406         int ret, timeout = CHIP_DELAY_TIMEOUT;
 407
 408         switch (info->state) {
 409         case STATE_PIO_WRITING:
 410                 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
 411                                 DIV_ROUND_UP(info->data_size, 4));
 412                 if (info->oob_size > 0)
 413                         __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
 414                                         DIV_ROUND_UP(info->oob_size, 4));
 415
 416                 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
 417
 418                 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
 419                 if (!ret) {
 420                         printk(KERN_ERR "program command time out\n");
 421                         return -1;
 422                 }
 423                 break;
 424         case STATE_PIO_READING:
 425                 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
 426                                 DIV_ROUND_UP(info->data_size, 4));
 427                 if (info->oob_size > 0)
 428                         __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
 429                                         DIV_ROUND_UP(info->oob_size, 4));
 430                 break;
 431         default:
 432                 printk(KERN_ERR "%s: invalid state %d\n", __func__,
 433                                 info->state);
 434                 return -EINVAL;
 435         }
 436
 437         info->state = STATE_READY;
 438         return 0;
 439 }
 440
 441 static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
 442 {
 443         struct pxa_dma_desc *desc = info->data_desc;
 444         int dma_len = ALIGN(info->data_size + info->oob_size, 32);
 445
 446         desc->ddadr = DDADR_STOP;
 447         desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
 448
 449         if (dir_out) {
 450                 desc->dsadr = info->data_buff_phys;
 451                 desc->dtadr = info->mmio_phys + NDDB;
 452                 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
 453         } else {
 454                 desc->dtadr = info->data_buff_phys;
 455                 desc->dsadr = info->mmio_phys + NDDB;
 456                 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
 457         }
 458
 459         DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
 460         DDADR(info->data_dma_ch) = info->data_desc_addr;
 461         DCSR(info->data_dma_ch) |= DCSR_RUN;
 462 }
 463
 464 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
 465 {
 466         struct pxa3xx_nand_info *info = data;
 467         uint32_t dcsr;
 468
 469         dcsr = DCSR(channel);
 470         DCSR(channel) = dcsr;
 471
 472         if (dcsr & DCSR_BUSERR) {
 473                 info->retcode = ERR_DMABUSERR;
 474                 complete(&info->cmd_complete);
 475         }
 476
 477         if (info->state == STATE_DMA_WRITING) {
 478                 info->state = STATE_DMA_DONE;
 479                 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
 480         } else {
 481                 info->state = STATE_READY;
 482                 complete(&info->cmd_complete);
 483         }
 484 }
 485
 486 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 487 {
 488         struct pxa3xx_nand_info *info = devid;
 489         unsigned int status;
 490
 491         status = nand_readl(info, NDSR);
 492
 493         if (status & (NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR)) {
 494                 if (status & NDSR_DBERR)
 495                         info->retcode = ERR_DBERR;
 496                 else if (status & NDSR_SBERR)
 497                         info->retcode = ERR_SBERR;
 498
 499                 disable_int(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
 500
 501                 if (info->use_dma) {
 502                         info->state = STATE_DMA_READING;
 503                         start_data_dma(info, 0);
 504                 } else {
 505                         info->state = STATE_PIO_READING;
 506                         complete(&info->cmd_complete);
 507                 }
 508         } else if (status & NDSR_WRDREQ) {
 509                 disable_int(info, NDSR_WRDREQ);
 510                 if (info->use_dma) {
 511                         info->state = STATE_DMA_WRITING;
 512                         start_data_dma(info, 1);
 513                 } else {
 514                         info->state = STATE_PIO_WRITING;
 515                         complete(&info->cmd_complete);
 516                 }
 517         } else if (status & (NDSR_CS0_BBD | NDSR_CS0_CMDD)) {
 518                 if (status & NDSR_CS0_BBD)
 519                         info->retcode = ERR_BBERR;
 520
 521                 disable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
 522                 info->state = STATE_READY;
 523                 complete(&info->cmd_complete);
 524         }
 525         nand_writel(info, NDSR, status);
 526         return IRQ_HANDLED;
 527 }
 528
 529 static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
 530 {
 531         uint32_t ndcr;
 532         int ret, timeout = CHIP_DELAY_TIMEOUT;
 533
 534         if (write_cmd(info)) {
 535                 info->retcode = ERR_SENDCMD;
 536                 goto fail_stop;
 537         }
 538
 539         info->state = STATE_CMD_HANDLE;
 540
 541         enable_int(info, event);
 542
 543         ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
 544         if (!ret) {
 545                 printk(KERN_ERR "command execution timed out\n");
 546                 info->retcode = ERR_SENDCMD;
 547                 goto fail_stop;
 548         }
 549
 550         if (info->use_dma == 0 && info->data_size > 0)
 551                 if (handle_data_pio(info))
 552                         goto fail_stop;
 553
 554         return 0;
 555
 556 fail_stop:
 557         ndcr = nand_readl(info, NDCR);
 558         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
 559         udelay(10);
 560         return -ETIMEDOUT;
 561 }
 562
 563 static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
 564 {
 565         struct pxa3xx_nand_info *info = mtd->priv;
 566         return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
 567 }
 568
 569 static inline int is_buf_blank(uint8_t *buf, size_t len)
 570 {
 571         for (; len > 0; len--)
 572                 if (*buf++ != 0xff)
 573                         return 0;
 574         return 1;
 575 }
 576
 577 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 578                                 int column, int page_addr)
 579 {
 580         struct pxa3xx_nand_info *info = mtd->priv;
 581         const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
 582         int ret;
 583
 584         info->use_dma = (use_dma) ? 1 : 0;
 585         info->use_ecc = 0;
 586         info->data_size = 0;
 587         info->state = STATE_READY;
 588
 589         init_completion(&info->cmd_complete);
 590
 591         switch (command) {
 592         case NAND_CMD_READOOB:
 593                 /* disable HW ECC to get all the OOB data */
 594                 info->buf_count = mtd->writesize + mtd->oobsize;
 595                 info->buf_start = mtd->writesize + column;
 596                 memset(info->data_buff, 0xFF, info->buf_count);
 597
 598                 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
 599                         break;
 600
 601                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
 602
 603                 /* We only are OOB, so if the data has error, does not matter */
 604                 if (info->retcode == ERR_DBERR)
 605                         info->retcode = ERR_NONE;
 606                 break;
 607
 608         case NAND_CMD_READ0:
 609                 info->use_ecc = 1;
 610                 info->retcode = ERR_NONE;
 611                 info->buf_start = column;
 612                 info->buf_count = mtd->writesize + mtd->oobsize;
 613                 memset(info->data_buff, 0xFF, info->buf_count);
 614
 615                 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
 616                         break;
 617
 618                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
 619
 620                 if (info->retcode == ERR_DBERR) {
 621                         /* for blank page (all 0xff), HW will calculate its ECC as
 622                          * 0, which is different from the ECC information within
 623                          * OOB, ignore such double bit errors
 624                          */
 625                         if (is_buf_blank(info->data_buff, mtd->writesize))
 626                                 info->retcode = ERR_NONE;
 627                 }
 628                 break;
 629         case NAND_CMD_SEQIN:
 630                 info->buf_start = column;
 631                 info->buf_count = mtd->writesize + mtd->oobsize;
 632                 memset(info->data_buff, 0xff, info->buf_count);
 633
 634                 /* save column/page_addr for next CMD_PAGEPROG */
 635                 info->seqin_column = column;
 636                 info->seqin_page_addr = page_addr;
 637                 break;
 638         case NAND_CMD_PAGEPROG:
 639                 info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
 640
 641                 if (prepare_read_prog_cmd(info, cmdset->program,
 642                                 info->seqin_column, info->seqin_page_addr))
 643                         break;
 644
 645                 pxa3xx_nand_do_cmd(info, NDSR_WRDREQ);
 646                 break;
 647         case NAND_CMD_ERASE1:
 648                 if (prepare_erase_cmd(info, cmdset->erase, page_addr))
 649                         break;
 650
 651                 pxa3xx_nand_do_cmd(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
 652                 break;
 653         case NAND_CMD_ERASE2:
 654                 break;
 655         case NAND_CMD_READID:
 656         case NAND_CMD_STATUS:
 657                 info->use_dma = 0;      /* force PIO read */
 658                 info->buf_start = 0;
 659                 info->buf_count = (command == NAND_CMD_READID) ?
 660                                 info->read_id_bytes : 1;
 661
 662                 if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
 663                                 cmdset->read_id : cmdset->read_status))
 664                         break;
 665
 666                 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ);
 667                 break;
 668         case NAND_CMD_RESET:
 669                 if (prepare_other_cmd(info, cmdset->reset))
 670                         break;
 671
 672                 ret = pxa3xx_nand_do_cmd(info, NDSR_CS0_CMDD);
 673                 if (ret == 0) {
 674                         int timeout = 2;
 675                         uint32_t ndcr;
 676
 677                         while (timeout--) {
 678                                 if (nand_readl(info, NDSR) & NDSR_RDY)
 679                                         break;
 680                                 msleep(10);
 681                         }
 682
 683                         ndcr = nand_readl(info, NDCR);
 684                         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
 685                 }
 686                 break;
 687         default:
 688                 printk(KERN_ERR "non-supported command.\n");
 689                 break;
 690         }
 691
 692         if (info->retcode == ERR_DBERR) {
 693                 printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
 694                 info->retcode = ERR_NONE;
 695         }
 696 }
 697
 698 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 699 {
 700         struct pxa3xx_nand_info *info = mtd->priv;
 701         char retval = 0xFF;
 702
 703         if (info->buf_start < info->buf_count)
 704                 /* Has just send a new command? */
 705                 retval = info->data_buff[info->buf_start++];
 706
 707         return retval;
 708 }
 709
 710 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 711 {
 712         struct pxa3xx_nand_info *info = mtd->priv;
 713         u16 retval = 0xFFFF;
 714
 715         if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
 716                 retval = *((u16 *)(info->data_buff+info->buf_start));
 717                 info->buf_start += 2;
 718         }
 719         return retval;
 720 }
 721
 722 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 723 {
 724         struct pxa3xx_nand_info *info = mtd->priv;
 725         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 726
 727         memcpy(buf, info->data_buff + info->buf_start, real_len);
 728         info->buf_start += real_len;
 729 }
 730
 731 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 732                 const uint8_t *buf, int len)
 733 {
 734         struct pxa3xx_nand_info *info = mtd->priv;
 735         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 736
 737         memcpy(info->data_buff + info->buf_start, buf, real_len);
 738         info->buf_start += real_len;
 739 }
 740
 741 static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
 742                 const uint8_t *buf, int len)
 743 {
 744         return 0;
 745 }
 746
 747 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
 748 {
 749         return;
 750 }
 751
 752 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
 753 {
 754         struct pxa3xx_nand_info *info = mtd->priv;
 755
 756         /* pxa3xx_nand_send_command has waited for command complete */
 757         if (this->state == FL_WRITING || this->state == FL_ERASING) {
 758                 if (info->retcode == ERR_NONE)
 759                         return 0;
 760                 else {
 761                         /*
 762                          * any error make it return 0x01 which will tell
 763                          * the caller the erase and write fail
 764                          */
 765                         return 0x01;
 766                 }
 767         }
 768
 769         return 0;
 770 }
 771
 772 static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
 773 {
 774         return;
 775 }
 776
 777 static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
 778                 const uint8_t *dat, uint8_t *ecc_code)
 779 {
 780         return 0;
 781 }
 782
 783 static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
 784                 uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
 785 {
 786         struct pxa3xx_nand_info *info = mtd->priv;
 787         /*
 788          * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
 789          * consider it as a ecc error which will tell the caller the
 790          * read fail We have distinguish all the errors, but the
 791          * nand_read_ecc only check this function return value
 792          *
 793          * Corrected (single-bit) errors must also be noted.
 794          */
 795         if (info->retcode == ERR_SBERR)
 796                 return 1;
 797         else if (info->retcode != ERR_NONE)
 798                 return -1;
 799
 800         return 0;
 801 }
 802
 803 static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
 804 {
 805         const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
 806         uint32_t ndcr;
 807         uint8_t  id_buff[8];
 808
 809         if (prepare_other_cmd(info, cmdset->read_id)) {
 810                 printk(KERN_ERR "failed to prepare command\n");
 811                 return -EINVAL;
 812         }
 813
 814         /* Send command */
 815         if (write_cmd(info))
 816                 goto fail_timeout;
 817
 818         /* Wait for CMDDM(command done successfully) */
 819         if (wait_for_event(info, NDSR_RDDREQ))
 820                 goto fail_timeout;
 821
 822         __raw_readsl(info->mmio_base + NDDB, id_buff, 2);
 823         *id = id_buff[0] | (id_buff[1] << 8);
 824         return 0;
 825
 826 fail_timeout:
 827         ndcr = nand_readl(info, NDCR);
 828         nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
 829         udelay(10);
 830         return -ETIMEDOUT;
 831 }
 832
 833 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
 834                                     const struct pxa3xx_nand_flash *f)
 835 {
 836         struct platform_device *pdev = info->pdev;
 837         struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 838         uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
 839
 840         if (f->page_size != 2048 && f->page_size != 512)
 841                 return -EINVAL;
 842
 843         if (f->flash_width != 16 && f->flash_width != 8)
 844                 return -EINVAL;
 845
 846         /* calculate flash information */
 847         info->cmdset = f->cmdset;
 848         info->page_size = f->page_size;
 849         info->oob_buff = info->data_buff + f->page_size;
 850         info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
 851
 852         /* calculate addressing information */
 853         info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
 854
 855         if (f->num_blocks * f->page_per_block > 65536)
 856                 info->row_addr_cycles = 3;
 857         else
 858                 info->row_addr_cycles = 2;
 859
 860         ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
 861         ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
 862         ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
 863         ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
 864         ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
 865         ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
 866
 867         ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
 868         ndcr |= NDCR_SPARE_EN; /* enable spare by default */
 869
 870         info->reg_ndcr = ndcr;
 871
 872         pxa3xx_nand_set_timing(info, f->timing);
 873         return 0;
 874 }
 875
 876 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 877 {
 878         uint32_t ndcr = nand_readl(info, NDCR);
 879         struct nand_flash_dev *type = NULL;
 880         uint32_t id = -1, page_per_block, num_blocks;
 881         int i;
 882
 883         page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
 884         info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
 885         /* set info fields needed to __readid */
 886         info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
 887         info->reg_ndcr = ndcr;
 888
 889         if (__readid(info, &id))
 890                 return -ENODEV;
 891
 892         /* Lookup the flash id */
 893         id = (id >> 8) & 0xff;          /* device id is byte 2 */
 894         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
 895                 if (id == nand_flash_ids[i].id) {
 896                         type =  &nand_flash_ids[i];
 897                         break;
 898                 }
 899         }
 900
 901         if (!type)
 902                 return -ENODEV;
 903
 904         /* fill the missing flash information */
 905         i = __ffs(page_per_block * info->page_size);
 906         num_blocks = type->chipsize << (20 - i);
 907
 908         /* calculate addressing information */
 909         info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;
 910
 911         if (num_blocks * page_per_block > 65536)
 912                 info->row_addr_cycles = 3;
 913         else
 914                 info->row_addr_cycles = 2;
 915
 916         info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
 917         info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
 918         info->cmdset = &default_cmdset;
 919
 920         return 0;
 921 }
 922
 923 static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
 924                                     const struct pxa3xx_nand_platform_data *pdata)
 925 {
 926         const struct pxa3xx_nand_flash *f;
 927         uint32_t id = -1;
 928         int i;
 929
 930         if (pdata->keep_config)
 931                 if (pxa3xx_nand_detect_config(info) == 0)
 932                         return 0;
 933
 934         /* we use default timing to detect id */
 935         f = DEFAULT_FLASH_TYPE;
 936         pxa3xx_nand_config_flash(info, f);
 937         if (__readid(info, &id))
 938                 goto fail_detect;
 939
 940         for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
 941                 /* we first choose the flash definition from platfrom */
 942                 if (i < pdata->num_flash)
 943                         f = pdata->flash + i;
 944                 else
 945                         f = &builtin_flash_types[i - pdata->num_flash + 1];
 946                 if (f->chip_id == id) {
 947                         dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
 948                         pxa3xx_nand_config_flash(info, f);
 949                         return 0;
 950                 }
 951         }
 952
 953         dev_warn(&info->pdev->dev,
 954                  "failed to detect configured nand flash; found %04x instead of\n",
 955                  id);
 956 fail_detect:
 957         return -ENODEV;
 958 }
 959
 960 /* the maximum possible buffer size for large page with OOB data
 961  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
 962  * data buffer and the DMA descriptor
 963  */
 964 #define MAX_BUFF_SIZE   PAGE_SIZE
 965
 966 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 967 {
 968         struct platform_device *pdev = info->pdev;
 969         int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
 970
 971         if (use_dma == 0) {
 972                 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
 973                 if (info->data_buff == NULL)
 974                         return -ENOMEM;
 975                 return 0;
 976         }
 977
 978         info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
 979                                 &info->data_buff_phys, GFP_KERNEL);
 980         if (info->data_buff == NULL) {
 981                 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
 982                 return -ENOMEM;
 983         }
 984
 985         info->data_buff_size = MAX_BUFF_SIZE;
 986         info->data_desc = (void *)info->data_buff + data_desc_offset;
 987         info->data_desc_addr = info->data_buff_phys + data_desc_offset;
 988
 989         info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
 990                                 pxa3xx_nand_data_dma_irq, info);
 991         if (info->data_dma_ch < 0) {
 992                 dev_err(&pdev->dev, "failed to request data dma\n");
 993                 dma_free_coherent(&pdev->dev, info->data_buff_size,
 994                                 info->data_buff, info->data_buff_phys);
 995                 return info->data_dma_ch;
 996         }
 997
 998         return 0;
 999 }
1000
1001 static struct nand_ecclayout hw_smallpage_ecclayout = {
1002         .eccbytes = 6,
1003         .eccpos = {8, 9, 10, 11, 12, 13 },
1004         .oobfree = { {2, 6} }
1005 };
1006
1007 static struct nand_ecclayout hw_largepage_ecclayout = {
1008         .eccbytes = 24,
1009         .eccpos = {
1010                 40, 41, 42, 43, 44, 45, 46, 47,
1011                 48, 49, 50, 51, 52, 53, 54, 55,
1012                 56, 57, 58, 59, 60, 61, 62, 63},
1013         .oobfree = { {2, 38} }
1014 };
1015
1016 static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
1017                                  struct pxa3xx_nand_info *info)
1018 {
1019         struct nand_chip *this = &info->nand_chip;
1020
1021         this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
1022
1023         this->waitfunc          = pxa3xx_nand_waitfunc;
1024         this->select_chip       = pxa3xx_nand_select_chip;
1025         this->dev_ready         = pxa3xx_nand_dev_ready;
1026         this->cmdfunc           = pxa3xx_nand_cmdfunc;
1027         this->read_word         = pxa3xx_nand_read_word;
1028         this->read_byte         = pxa3xx_nand_read_byte;
1029         this->read_buf          = pxa3xx_nand_read_buf;
1030         this->write_buf         = pxa3xx_nand_write_buf;
1031         this->verify_buf        = pxa3xx_nand_verify_buf;
1032
1033         this->ecc.mode          = NAND_ECC_HW;
1034         this->ecc.hwctl         = pxa3xx_nand_ecc_hwctl;
1035         this->ecc.calculate     = pxa3xx_nand_ecc_calculate;
1036         this->ecc.correct       = pxa3xx_nand_ecc_correct;
1037         this->ecc.size          = info->page_size;
1038
1039         if (info->page_size == 2048)
1040                 this->ecc.layout = &hw_largepage_ecclayout;
1041         else
1042                 this->ecc.layout = &hw_smallpage_ecclayout;
1043
1044         this->chip_delay = 25;
1045 }
1046
1047 static int pxa3xx_nand_probe(struct platform_device *pdev)
1048 {
1049         struct pxa3xx_nand_platform_data *pdata;
1050         struct pxa3xx_nand_info *info;
1051         struct nand_chip *this;
1052         struct mtd_info *mtd;
1053         struct resource *r;
1054         int ret = 0, irq;
1055
1056         pdata = pdev->dev.platform_data;
1057
1058         if (!pdata) {
1059                 dev_err(&pdev->dev, "no platform data defined\n");
1060                 return -ENODEV;
1061         }
1062
1063         mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
1064                         GFP_KERNEL);
1065         if (!mtd) {
1066                 dev_err(&pdev->dev, "failed to allocate memory\n");
1067                 return -ENOMEM;
1068         }
1069
1070         info = (struct pxa3xx_nand_info *)(&mtd[1]);
1071         info->pdev = pdev;
1072
1073         this = &info->nand_chip;
1074         mtd->priv = info;
1075         mtd->owner = THIS_MODULE;
1076
1077         info->clk = clk_get(&pdev->dev, NULL);
1078         if (IS_ERR(info->clk)) {
1079                 dev_err(&pdev->dev, "failed to get nand clock\n");
1080                 ret = PTR_ERR(info->clk);
1081                 goto fail_free_mtd;
1082         }
1083         clk_enable(info->clk);
1084
1085         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1086         if (r == NULL) {
1087                 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1088                 ret = -ENXIO;
1089                 goto fail_put_clk;
1090         }
1091         info->drcmr_dat = r->start;
1092
1093         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1094         if (r == NULL) {
1095                 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1096                 ret = -ENXIO;
1097                 goto fail_put_clk;
1098         }
1099         info->drcmr_cmd = r->start;
1100
1101         irq = platform_get_irq(pdev, 0);
1102         if (irq < 0) {
1103                 dev_err(&pdev->dev, "no IRQ resource defined\n");
1104                 ret = -ENXIO;
1105                 goto fail_put_clk;
1106         }
1107
1108         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1109         if (r == NULL) {
1110                 dev_err(&pdev->dev, "no IO memory resource defined\n");
1111                 ret = -ENODEV;
1112                 goto fail_put_clk;
1113         }
1114
1115         r = request_mem_region(r->start, resource_size(r), pdev->name);
1116         if (r == NULL) {
1117                 dev_err(&pdev->dev, "failed to request memory resource\n");
1118                 ret = -EBUSY;
1119                 goto fail_put_clk;
1120         }
1121
1122         info->mmio_base = ioremap(r->start, resource_size(r));
1123         if (info->mmio_base == NULL) {
1124                 dev_err(&pdev->dev, "ioremap() failed\n");
1125                 ret = -ENODEV;
1126                 goto fail_free_res;
1127         }
1128         info->mmio_phys = r->start;
1129
1130         ret = pxa3xx_nand_init_buff(info);
1131         if (ret)
1132                 goto fail_free_io;
1133
1134         /* initialize all interrupts to be disabled */
1135         disable_int(info, NDSR_MASK);
1136
1137         ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1138                           pdev->name, info);
1139         if (ret < 0) {
1140                 dev_err(&pdev->dev, "failed to request IRQ\n");
1141                 goto fail_free_buf;
1142         }
1143
1144         ret = pxa3xx_nand_detect_flash(info, pdata);
1145         if (ret) {
1146                 dev_err(&pdev->dev, "failed to detect flash\n");
1147                 ret = -ENODEV;
1148                 goto fail_free_irq;
1149         }
1150
1151         pxa3xx_nand_init_mtd(mtd, info);
1152
1153         platform_set_drvdata(pdev, mtd);
1154
1155         if (nand_scan(mtd, 1)) {
1156                 dev_err(&pdev->dev, "failed to scan nand\n");
1157                 ret = -ENXIO;
1158                 goto fail_free_irq;
1159         }
1160
1161 #ifdef CONFIG_MTD_PARTITIONS
1162         if (mtd_has_cmdlinepart()) {
1163                 static const char *probes[] = { "cmdlinepart", NULL };
1164                 struct mtd_partition *parts;
1165                 int nr_parts;
1166
1167                 nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0);
1168
1169                 if (nr_parts)
1170                         return add_mtd_partitions(mtd, parts, nr_parts);
1171         }
1172
1173         return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
1174 #else
1175         return 0;
1176 #endif
1177
1178 fail_free_irq:
1179         free_irq(irq, info);
1180 fail_free_buf:
1181         if (use_dma) {
1182                 pxa_free_dma(info->data_dma_ch);
1183                 dma_free_coherent(&pdev->dev, info->data_buff_size,
1184                         info->data_buff, info->data_buff_phys);
1185         } else
1186                 kfree(info->data_buff);
1187 fail_free_io:
1188         iounmap(info->mmio_base);
1189 fail_free_res:
1190         release_mem_region(r->start, resource_size(r));
1191 fail_put_clk:
1192         clk_disable(info->clk);
1193         clk_put(info->clk);
1194 fail_free_mtd:
1195         kfree(mtd);
1196         return ret;
1197 }
1198
1199 static int pxa3xx_nand_remove(struct platform_device *pdev)
1200 {
1201         struct mtd_info *mtd = platform_get_drvdata(pdev);
1202         struct pxa3xx_nand_info *info = mtd->priv;
1203         struct resource *r;
1204         int irq;
1205
1206         platform_set_drvdata(pdev, NULL);
1207
1208         del_mtd_device(mtd);
1209 #ifdef CONFIG_MTD_PARTITIONS
1210         del_mtd_partitions(mtd);
1211 #endif
1212         irq = platform_get_irq(pdev, 0);
1213         if (irq >= 0)
1214                 free_irq(irq, info);
1215         if (use_dma) {
1216                 pxa_free_dma(info->data_dma_ch);
1217                 dma_free_writecombine(&pdev->dev, info->data_buff_size,
1218                                 info->data_buff, info->data_buff_phys);
1219         } else
1220                 kfree(info->data_buff);
1221
1222         iounmap(info->mmio_base);
1223         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1224         release_mem_region(r->start, resource_size(r));
1225
1226         clk_disable(info->clk);
1227         clk_put(info->clk);
1228
1229         kfree(mtd);
1230         return 0;
1231 }
1232
1233 #ifdef CONFIG_PM
1234 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1235 {
1236         struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1237         struct pxa3xx_nand_info *info = mtd->priv;
1238
1239         if (info->state != STATE_READY) {
1240                 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1241                 return -EAGAIN;
1242         }
1243
1244         return 0;
1245 }
1246
1247 static int pxa3xx_nand_resume(struct platform_device *pdev)
1248 {
1249         struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1250         struct pxa3xx_nand_info *info = mtd->priv;
1251
1252         nand_writel(info, NDTR0CS0, info->ndtr0cs0);
1253         nand_writel(info, NDTR1CS0, info->ndtr1cs0);
1254         clk_enable(info->clk);
1255
1256         return 0;
1257 }
1258 #else
1259 #define pxa3xx_nand_suspend     NULL
1260 #define pxa3xx_nand_resume      NULL
1261 #endif
1262
1263 static struct platform_driver pxa3xx_nand_driver = {
1264         .driver = {
1265                 .name   = "pxa3xx-nand",
1266         },
1267         .probe          = pxa3xx_nand_probe,
1268         .remove         = pxa3xx_nand_remove,
1269         .suspend        = pxa3xx_nand_suspend,
1270         .resume         = pxa3xx_nand_resume,
1271 };
1272
1273 static int __init pxa3xx_nand_init(void)
1274 {
1275         return platform_driver_register(&pxa3xx_nand_driver);
1276 }
1277 module_init(pxa3xx_nand_init);
1278
1279 static void __exit pxa3xx_nand_exit(void)
1280 {
1281         platform_driver_unregister(&pxa3xx_nand_driver);
1282 }
1283 module_exit(pxa3xx_nand_exit);
1284
1285 MODULE_LICENSE("GPL");
1286 MODULE_DESCRIPTION("PXA3xx NAND controller driver");