drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/delay.h>
  14 #include <linux/module.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/jiffies.h>
  17 #include <linux/sched.h>
  18 #include <linux/mtd/mtd.h>
  19 #include <linux/mtd/nand.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/io.h>
  22 #include <linux/slab.h>
  23
  24 #include <plat/dma.h>
  25 #include <plat/gpmc.h>
  26 #include <plat/nand.h>
  27
  28 #define DRIVER_NAME     "omap2-nand"
  29 #define OMAP_NAND_TIMEOUT_MS    5000
  30
  31 #define NAND_Ecc_P1e            (1 << 0)
  32 #define NAND_Ecc_P2e            (1 << 1)
  33 #define NAND_Ecc_P4e            (1 << 2)
  34 #define NAND_Ecc_P8e            (1 << 3)
  35 #define NAND_Ecc_P16e           (1 << 4)
  36 #define NAND_Ecc_P32e           (1 << 5)
  37 #define NAND_Ecc_P64e           (1 << 6)
  38 #define NAND_Ecc_P128e          (1 << 7)
  39 #define NAND_Ecc_P256e          (1 << 8)
  40 #define NAND_Ecc_P512e          (1 << 9)
  41 #define NAND_Ecc_P1024e         (1 << 10)
  42 #define NAND_Ecc_P2048e         (1 << 11)
  43
  44 #define NAND_Ecc_P1o            (1 << 16)
  45 #define NAND_Ecc_P2o            (1 << 17)
  46 #define NAND_Ecc_P4o            (1 << 18)
  47 #define NAND_Ecc_P8o            (1 << 19)
  48 #define NAND_Ecc_P16o           (1 << 20)
  49 #define NAND_Ecc_P32o           (1 << 21)
  50 #define NAND_Ecc_P64o           (1 << 22)
  51 #define NAND_Ecc_P128o          (1 << 23)
  52 #define NAND_Ecc_P256o          (1 << 24)
  53 #define NAND_Ecc_P512o          (1 << 25)
  54 #define NAND_Ecc_P1024o         (1 << 26)
  55 #define NAND_Ecc_P2048o         (1 << 27)
  56
  57 #define TF(value)       (value ? 1 : 0)
  58
  59 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  60 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  61 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  62 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  63 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  64 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  65 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  66 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  67
  68 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  69 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  70 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  71 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  72 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  73 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  74 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  75 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  76
  77 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  78 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  79 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  80 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  81 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  82 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  83 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  84 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  85
  86 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  87 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  88 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  89 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  90 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  91 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  92 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  93 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
  94
  95 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
  96 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
  97
  98 /* oob info generated runtime depending on ecc algorithm and layout selected */
  99 static struct nand_ecclayout omap_oobinfo;
 100 /* Define some generic bad / good block scan pattern which are used
 101  * while scanning a device for factory marked good / bad blocks
 102  */
 103 static uint8_t scan_ff_pattern[] = { 0xff };
 104 static struct nand_bbt_descr bb_descrip_flashbased = {
 105         .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
 106         .offs = 0,
 107         .len = 1,
 108         .pattern = scan_ff_pattern,
 109 };
 110
 111
 112 struct omap_nand_info {
 113         struct nand_hw_control          controller;
 114         struct omap_nand_platform_data  *pdata;
 115         struct mtd_info                 mtd;
 116         struct nand_chip                nand;
 117         struct platform_device          *pdev;
 118
 119         int                             gpmc_cs;
 120         unsigned long                   phys_base;
 121         struct completion               comp;
 122         int                             dma_ch;
 123         int                             gpmc_irq;
 124         enum {
 125                 OMAP_NAND_IO_READ = 0,  /* read */
 126                 OMAP_NAND_IO_WRITE,     /* write */
 127         } iomode;
 128         u_char                          *buf;
 129         int                                     buf_len;
 130 };
 131
 132 /**
 133  * omap_hwcontrol - hardware specific access to control-lines
 134  * @mtd: MTD device structure
 135  * @cmd: command to device
 136  * @ctrl:
 137  * NAND_NCE: bit 0 -> don't care
 138  * NAND_CLE: bit 1 -> Command Latch
 139  * NAND_ALE: bit 2 -> Address Latch
 140  *
 141  * NOTE: boards may use different bits for these!!
 142  */
 143 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 144 {
 145         struct omap_nand_info *info = container_of(mtd,
 146                                         struct omap_nand_info, mtd);
 147
 148         if (cmd != NAND_CMD_NONE) {
 149                 if (ctrl & NAND_CLE)
 150                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
 151
 152                 else if (ctrl & NAND_ALE)
 153                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
 154
 155                 else /* NAND_NCE */
 156                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
 157         }
 158 }
 159
 160 /**
 161  * omap_read_buf8 - read data from NAND controller into buffer
 162  * @mtd: MTD device structure
 163  * @buf: buffer to store date
 164  * @len: number of bytes to read
 165  */
 166 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 167 {
 168         struct nand_chip *nand = mtd->priv;
 169
 170         ioread8_rep(nand->IO_ADDR_R, buf, len);
 171 }
 172
 173 /**
 174  * omap_write_buf8 - write buffer to NAND controller
 175  * @mtd: MTD device structure
 176  * @buf: data buffer
 177  * @len: number of bytes to write
 178  */
 179 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 180 {
 181         struct omap_nand_info *info = container_of(mtd,
 182                                                 struct omap_nand_info, mtd);
 183         u_char *p = (u_char *)buf;
 184         u32     status = 0;
 185
 186         while (len--) {
 187                 iowrite8(*p++, info->nand.IO_ADDR_W);
 188                 /* wait until buffer is available for write */
 189                 do {
 190                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 191                 } while (!status);
 192         }
 193 }
 194
 195 /**
 196  * omap_read_buf16 - read data from NAND controller into buffer
 197  * @mtd: MTD device structure
 198  * @buf: buffer to store date
 199  * @len: number of bytes to read
 200  */
 201 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 202 {
 203         struct nand_chip *nand = mtd->priv;
 204
 205         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 206 }
 207
 208 /**
 209  * omap_write_buf16 - write buffer to NAND controller
 210  * @mtd: MTD device structure
 211  * @buf: data buffer
 212  * @len: number of bytes to write
 213  */
 214 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 215 {
 216         struct omap_nand_info *info = container_of(mtd,
 217                                                 struct omap_nand_info, mtd);
 218         u16 *p = (u16 *) buf;
 219         u32     status = 0;
 220         /* FIXME try bursts of writesw() or DMA ... */
 221         len >>= 1;
 222
 223         while (len--) {
 224                 iowrite16(*p++, info->nand.IO_ADDR_W);
 225                 /* wait until buffer is available for write */
 226                 do {
 227                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 228                 } while (!status);
 229         }
 230 }
 231
 232 /**
 233  * omap_read_buf_pref - read data from NAND controller into buffer
 234  * @mtd: MTD device structure
 235  * @buf: buffer to store date
 236  * @len: number of bytes to read
 237  */
 238 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 239 {
 240         struct omap_nand_info *info = container_of(mtd,
 241                                                 struct omap_nand_info, mtd);
 242         uint32_t r_count = 0;
 243         int ret = 0;
 244         u32 *p = (u32 *)buf;
 245
 246         /* take care of subpage reads */
 247         if (len % 4) {
 248                 if (info->nand.options & NAND_BUSWIDTH_16)
 249                         omap_read_buf16(mtd, buf, len % 4);
 250                 else
 251                         omap_read_buf8(mtd, buf, len % 4);
 252                 p = (u32 *) (buf + len % 4);
 253                 len -= len % 4;
 254         }
 255
 256         /* configure and start prefetch transfer */
 257         ret = gpmc_prefetch_enable(info->gpmc_cs,
 258                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
 259         if (ret) {
 260                 /* PFPW engine is busy, use cpu copy method */
 261                 if (info->nand.options & NAND_BUSWIDTH_16)
 262                         omap_read_buf16(mtd, (u_char *)p, len);
 263                 else
 264                         omap_read_buf8(mtd, (u_char *)p, len);
 265         } else {
 266                 do {
 267                         r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 268                         r_count = r_count >> 2;
 269                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 270                         p += r_count;
 271                         len -= r_count << 2;
 272                 } while (len);
 273                 /* disable and stop the PFPW engine */
 274                 gpmc_prefetch_reset(info->gpmc_cs);
 275         }
 276 }
 277
 278 /**
 279  * omap_write_buf_pref - write buffer to NAND controller
 280  * @mtd: MTD device structure
 281  * @buf: data buffer
 282  * @len: number of bytes to write
 283  */
 284 static void omap_write_buf_pref(struct mtd_info *mtd,
 285                                         const u_char *buf, int len)
 286 {
 287         struct omap_nand_info *info = container_of(mtd,
 288                                                 struct omap_nand_info, mtd);
 289         uint32_t w_count = 0;
 290         int i = 0, ret = 0;
 291         u16 *p = (u16 *)buf;
 292         unsigned long tim, limit;
 293
 294         /* take care of subpage writes */
 295         if (len % 2 != 0) {
 296                 writeb(*buf, info->nand.IO_ADDR_W);
 297                 p = (u16 *)(buf + 1);
 298                 len--;
 299         }
 300
 301         /*  configure and start prefetch transfer */
 302         ret = gpmc_prefetch_enable(info->gpmc_cs,
 303                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
 304         if (ret) {
 305                 /* PFPW engine is busy, use cpu copy method */
 306                 if (info->nand.options & NAND_BUSWIDTH_16)
 307                         omap_write_buf16(mtd, (u_char *)p, len);
 308                 else
 309                         omap_write_buf8(mtd, (u_char *)p, len);
 310         } else {
 311                 while (len) {
 312                         w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 313                         w_count = w_count >> 1;
 314                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 315                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 316                 }
 317                 /* wait for data to flushed-out before reset the prefetch */
 318                 tim = 0;
 319                 limit = (loops_per_jiffy *
 320                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 321                 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 322                         cpu_relax();
 323
 324                 /* disable and stop the PFPW engine */
 325                 gpmc_prefetch_reset(info->gpmc_cs);
 326         }
 327 }
 328
 329 /*
 330  * omap_nand_dma_cb: callback on the completion of dma transfer
 331  * @lch: logical channel
 332  * @ch_satuts: channel status
 333  * @data: pointer to completion data structure
 334  */
 335 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
 336 {
 337         complete((struct completion *) data);
 338 }
 339
 340 /*
 341  * omap_nand_dma_transfer: configer and start dma transfer
 342  * @mtd: MTD device structure
 343  * @addr: virtual address in RAM of source/destination
 344  * @len: number of data bytes to be transferred
 345  * @is_write: flag for read/write operation
 346  */
 347 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 348                                         unsigned int len, int is_write)
 349 {
 350         struct omap_nand_info *info = container_of(mtd,
 351                                         struct omap_nand_info, mtd);
 352         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 353                                                         DMA_FROM_DEVICE;
 354         dma_addr_t dma_addr;
 355         int ret;
 356         unsigned long tim, limit;
 357
 358         /* The fifo depth is 64 bytes max.
 359          * But configure the FIFO-threahold to 32 to get a sync at each frame
 360          * and frame length is 32 bytes.
 361          */
 362         int buf_len = len >> 6;
 363
 364         if (addr >= high_memory) {
 365                 struct page *p1;
 366
 367                 if (((size_t)addr & PAGE_MASK) !=
 368                         ((size_t)(addr + len - 1) & PAGE_MASK))
 369                         goto out_copy;
 370                 p1 = vmalloc_to_page(addr);
 371                 if (!p1)
 372                         goto out_copy;
 373                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 374         }
 375
 376         dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
 377         if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
 378                 dev_err(&info->pdev->dev,
 379                         "Couldn't DMA map a %d byte buffer\n", len);
 380                 goto out_copy;
 381         }
 382
 383         if (is_write) {
 384             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 385                                                 info->phys_base, 0, 0);
 386             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 387                                                         dma_addr, 0, 0);
 388             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 389                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 390                                         OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
 391         } else {
 392             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 393                                                 info->phys_base, 0, 0);
 394             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 395                                                         dma_addr, 0, 0);
 396             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 397                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 398                                         OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
 399         }
 400         /*  configure and start prefetch transfer */
 401         ret = gpmc_prefetch_enable(info->gpmc_cs,
 402                         PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
 403         if (ret)
 404                 /* PFPW engine is busy, use cpu copy method */
 405                 goto out_copy;
 406
 407         init_completion(&info->comp);
 408
 409         omap_start_dma(info->dma_ch);
 410
 411         /* setup and start DMA using dma_addr */
 412         wait_for_completion(&info->comp);
 413         tim = 0;
 414         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 415         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 416                 cpu_relax();
 417
 418         /* disable and stop the PFPW engine */
 419         gpmc_prefetch_reset(info->gpmc_cs);
 420
 421         dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
 422         return 0;
 423
 424 out_copy:
 425         if (info->nand.options & NAND_BUSWIDTH_16)
 426                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 427                         : omap_write_buf16(mtd, (u_char *) addr, len);
 428         else
 429                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 430                         : omap_write_buf8(mtd, (u_char *) addr, len);
 431         return 0;
 432 }
 433
 434 /**
 435  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 436  * @mtd: MTD device structure
 437  * @buf: buffer to store date
 438  * @len: number of bytes to read
 439  */
 440 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 441 {
 442         if (len <= mtd->oobsize)
 443                 omap_read_buf_pref(mtd, buf, len);
 444         else
 445                 /* start transfer in DMA mode */
 446                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 447 }
 448
 449 /**
 450  * omap_write_buf_dma_pref - write buffer to NAND controller
 451  * @mtd: MTD device structure
 452  * @buf: data buffer
 453  * @len: number of bytes to write
 454  */
 455 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 456                                         const u_char *buf, int len)
 457 {
 458         if (len <= mtd->oobsize)
 459                 omap_write_buf_pref(mtd, buf, len);
 460         else
 461                 /* start transfer in DMA mode */
 462                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 463 }
 464
 465 /*
 466  * omap_nand_irq - GMPC irq handler
 467  * @this_irq: gpmc irq number
 468  * @dev: omap_nand_info structure pointer is passed here
 469  */
 470 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 471 {
 472         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 473         u32 bytes;
 474         u32 irq_stat;
 475
 476         irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 477         bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 478         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 479         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 480                 if (irq_stat & 0x2)
 481                         goto done;
 482
 483                 if (info->buf_len && (info->buf_len < bytes))
 484                         bytes = info->buf_len;
 485                 else if (!info->buf_len)
 486                         bytes = 0;
 487                 iowrite32_rep(info->nand.IO_ADDR_W,
 488                                                 (u32 *)info->buf, bytes >> 2);
 489                 info->buf = info->buf + bytes;
 490                 info->buf_len -= bytes;
 491
 492         } else {
 493                 ioread32_rep(info->nand.IO_ADDR_R,
 494                                                 (u32 *)info->buf, bytes >> 2);
 495                 info->buf = info->buf + bytes;
 496
 497                 if (irq_stat & 0x2)
 498                         goto done;
 499         }
 500         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 501
 502         return IRQ_HANDLED;
 503
 504 done:
 505         complete(&info->comp);
 506         /* disable irq */
 507         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
 508
 509         /* clear status */
 510         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 511
 512         return IRQ_HANDLED;
 513 }
 514
 515 /*
 516  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 517  * @mtd: MTD device structure
 518  * @buf: buffer to store date
 519  * @len: number of bytes to read
 520  */
 521 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 522 {
 523         struct omap_nand_info *info = container_of(mtd,
 524                                                 struct omap_nand_info, mtd);
 525         int ret = 0;
 526
 527         if (len <= mtd->oobsize) {
 528                 omap_read_buf_pref(mtd, buf, len);
 529                 return;
 530         }
 531
 532         info->iomode = OMAP_NAND_IO_READ;
 533         info->buf = buf;
 534         init_completion(&info->comp);
 535
 536         /*  configure and start prefetch transfer */
 537         ret = gpmc_prefetch_enable(info->gpmc_cs,
 538                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
 539         if (ret)
 540                 /* PFPW engine is busy, use cpu copy method */
 541                 goto out_copy;
 542
 543         info->buf_len = len;
 544         /* enable irq */
 545         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 546                 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 547
 548         /* waiting for read to complete */
 549         wait_for_completion(&info->comp);
 550
 551         /* disable and stop the PFPW engine */
 552         gpmc_prefetch_reset(info->gpmc_cs);
 553         return;
 554
 555 out_copy:
 556         if (info->nand.options & NAND_BUSWIDTH_16)
 557                 omap_read_buf16(mtd, buf, len);
 558         else
 559                 omap_read_buf8(mtd, buf, len);
 560 }
 561
 562 /*
 563  * omap_write_buf_irq_pref - write buffer to NAND controller
 564  * @mtd: MTD device structure
 565  * @buf: data buffer
 566  * @len: number of bytes to write
 567  */
 568 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 569                                         const u_char *buf, int len)
 570 {
 571         struct omap_nand_info *info = container_of(mtd,
 572                                                 struct omap_nand_info, mtd);
 573         int ret = 0;
 574         unsigned long tim, limit;
 575
 576         if (len <= mtd->oobsize) {
 577                 omap_write_buf_pref(mtd, buf, len);
 578                 return;
 579         }
 580
 581         info->iomode = OMAP_NAND_IO_WRITE;
 582         info->buf = (u_char *) buf;
 583         init_completion(&info->comp);
 584
 585         /* configure and start prefetch transfer : size=24 */
 586         ret = gpmc_prefetch_enable(info->gpmc_cs,
 587                         (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
 588         if (ret)
 589                 /* PFPW engine is busy, use cpu copy method */
 590                 goto out_copy;
 591
 592         info->buf_len = len;
 593         /* enable irq */
 594         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 595                         (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 596
 597         /* waiting for write to complete */
 598         wait_for_completion(&info->comp);
 599         /* wait for data to flushed-out before reset the prefetch */
 600         tim = 0;
 601         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 602         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 603                 cpu_relax();
 604
 605         /* disable and stop the PFPW engine */
 606         gpmc_prefetch_reset(info->gpmc_cs);
 607         return;
 608
 609 out_copy:
 610         if (info->nand.options & NAND_BUSWIDTH_16)
 611                 omap_write_buf16(mtd, buf, len);
 612         else
 613                 omap_write_buf8(mtd, buf, len);
 614 }
 615
 616 /**
 617  * omap_verify_buf - Verify chip data against buffer
 618  * @mtd: MTD device structure
 619  * @buf: buffer containing the data to compare
 620  * @len: number of bytes to compare
 621  */
 622 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
 623 {
 624         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 625                                                         mtd);
 626         u16 *p = (u16 *) buf;
 627
 628         len >>= 1;
 629         while (len--) {
 630                 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
 631                         return -EFAULT;
 632         }
 633
 634         return 0;
 635 }
 636
 637 /**
 638  * gen_true_ecc - This function will generate true ECC value
 639  * @ecc_buf: buffer to store ecc code
 640  *
 641  * This generated true ECC value can be used when correcting
 642  * data read from NAND flash memory core
 643  */
 644 static void gen_true_ecc(u8 *ecc_buf)
 645 {
 646         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 647                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 648
 649         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 650                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 651         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 652                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 653         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 654                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 655 }
 656
 657 /**
 658  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 659  * @ecc_data1:  ecc code from nand spare area
 660  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 661  * @page_data:  page data
 662  *
 663  * This function compares two ECC's and indicates if there is an error.
 664  * If the error can be corrected it will be corrected to the buffer.
 665  * If there is no error, %0 is returned. If there is an error but it
 666  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 667  */
 668 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 669                             u8 *ecc_data2,      /* read from register */
 670                             u8 *page_data)
 671 {
 672         uint    i;
 673         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 674         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 675         u8      ecc_bit[24];
 676         u8      ecc_sum = 0;
 677         u8      find_bit = 0;
 678         uint    find_byte = 0;
 679         int     isEccFF;
 680
 681         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 682
 683         gen_true_ecc(ecc_data1);
 684         gen_true_ecc(ecc_data2);
 685
 686         for (i = 0; i <= 2; i++) {
 687                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 688                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 689         }
 690
 691         for (i = 0; i < 8; i++) {
 692                 tmp0_bit[i]     = *ecc_data1 % 2;
 693                 *ecc_data1      = *ecc_data1 / 2;
 694         }
 695
 696         for (i = 0; i < 8; i++) {
 697                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 698                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 699         }
 700
 701         for (i = 0; i < 8; i++) {
 702                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 703                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 704         }
 705
 706         for (i = 0; i < 8; i++) {
 707                 comp0_bit[i]     = *ecc_data2 % 2;
 708                 *ecc_data2       = *ecc_data2 / 2;
 709         }
 710
 711         for (i = 0; i < 8; i++) {
 712                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 713                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 714         }
 715
 716         for (i = 0; i < 8; i++) {
 717                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 718                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 719         }
 720
 721         for (i = 0; i < 6; i++)
 722                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 723
 724         for (i = 0; i < 8; i++)
 725                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 726
 727         for (i = 0; i < 8; i++)
 728                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 729
 730         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 731         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 732
 733         for (i = 0; i < 24; i++)
 734                 ecc_sum += ecc_bit[i];
 735
 736         switch (ecc_sum) {
 737         case 0:
 738                 /* Not reached because this function is not called if
 739                  *  ECC values are equal
 740                  */
 741                 return 0;
 742
 743         case 1:
 744                 /* Uncorrectable error */
 745                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
 746                 return -1;
 747
 748         case 11:
 749                 /* UN-Correctable error */
 750                 pr_debug("ECC UNCORRECTED_ERROR B\n");
 751                 return -1;
 752
 753         case 12:
 754                 /* Correctable error */
 755                 find_byte = (ecc_bit[23] << 8) +
 756                             (ecc_bit[21] << 7) +
 757                             (ecc_bit[19] << 6) +
 758                             (ecc_bit[17] << 5) +
 759                             (ecc_bit[15] << 4) +
 760                             (ecc_bit[13] << 3) +
 761                             (ecc_bit[11] << 2) +
 762                             (ecc_bit[9]  << 1) +
 763                             ecc_bit[7];
 764
 765                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 766
 767                 pr_debug("Correcting single bit ECC error at offset: "
 768                                 "%d, bit: %d\n", find_byte, find_bit);
 769
 770                 page_data[find_byte] ^= (1 << find_bit);
 771
 772                 return 1;
 773         default:
 774                 if (isEccFF) {
 775                         if (ecc_data2[0] == 0 &&
 776                             ecc_data2[1] == 0 &&
 777                             ecc_data2[2] == 0)
 778                                 return 0;
 779                 }
 780                 pr_debug("UNCORRECTED_ERROR default\n");
 781                 return -1;
 782         }
 783 }
 784
 785 /**
 786  * omap_correct_data - Compares the ECC read with HW generated ECC
 787  * @mtd: MTD device structure
 788  * @dat: page data
 789  * @read_ecc: ecc read from nand flash
 790  * @calc_ecc: ecc read from HW ECC registers
 791  *
 792  * Compares the ecc read from nand spare area with ECC registers values
 793  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 794  * detection and correction. If there are no errors, %0 is returned. If
 795  * there were errors and all of the errors were corrected, the number of
 796  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 797  * returned.
 798  */
 799 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 800                                 u_char *read_ecc, u_char *calc_ecc)
 801 {
 802         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 803                                                         mtd);
 804         int blockCnt = 0, i = 0, ret = 0;
 805         int stat = 0;
 806
 807         /* Ex NAND_ECC_HW12_2048 */
 808         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 809                         (info->nand.ecc.size  == 2048))
 810                 blockCnt = 4;
 811         else
 812                 blockCnt = 1;
 813
 814         for (i = 0; i < blockCnt; i++) {
 815                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 816                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 817                         if (ret < 0)
 818                                 return ret;
 819                         /* keep track of the number of corrected errors */
 820                         stat += ret;
 821                 }
 822                 read_ecc += 3;
 823                 calc_ecc += 3;
 824                 dat      += 512;
 825         }
 826         return stat;
 827 }
 828
 829 /**
 830  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 831  * @mtd: MTD device structure
 832  * @dat: The pointer to data on which ecc is computed
 833  * @ecc_code: The ecc_code buffer
 834  *
 835  * Using noninverted ECC can be considered ugly since writing a blank
 836  * page ie. padding will clear the ECC bytes. This is no problem as long
 837  * nobody is trying to write data on the seemingly unused page. Reading
 838  * an erased page will produce an ECC mismatch between generated and read
 839  * ECC bytes that has to be dealt with separately.
 840  */
 841 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 842                                 u_char *ecc_code)
 843 {
 844         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 845                                                         mtd);
 846         return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
 847 }
 848
 849 /**
 850  * omap_enable_hwecc - This function enables the hardware ecc functionality
 851  * @mtd: MTD device structure
 852  * @mode: Read/Write mode
 853  */
 854 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 855 {
 856         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 857                                                         mtd);
 858         struct nand_chip *chip = mtd->priv;
 859         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 860
 861         gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
 862 }
 863
 864 /**
 865  * omap_wait - wait until the command is done
 866  * @mtd: MTD device structure
 867  * @chip: NAND Chip structure
 868  *
 869  * Wait function is called during Program and erase operations and
 870  * the way it is called from MTD layer, we should wait till the NAND
 871  * chip is ready after the programming/erase operation has completed.
 872  *
 873  * Erase can take up to 400ms and program up to 20ms according to
 874  * general NAND and SmartMedia specs
 875  */
 876 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
 877 {
 878         struct nand_chip *this = mtd->priv;
 879         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 880                                                         mtd);
 881         unsigned long timeo = jiffies;
 882         int status = NAND_STATUS_FAIL, state = this->state;
 883
 884         if (state == FL_ERASING)
 885                 timeo += (HZ * 400) / 1000;
 886         else
 887                 timeo += (HZ * 20) / 1000;
 888
 889         gpmc_nand_write(info->gpmc_cs,
 890                         GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
 891         while (time_before(jiffies, timeo)) {
 892                 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
 893                 if (status & NAND_STATUS_READY)
 894                         break;
 895                 cond_resched();
 896         }
 897         return status;
 898 }
 899
 900 /**
 901  * omap_dev_ready - calls the platform specific dev_ready function
 902  * @mtd: MTD device structure
 903  */
 904 static int omap_dev_ready(struct mtd_info *mtd)
 905 {
 906         unsigned int val = 0;
 907         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 908                                                         mtd);
 909
 910         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 911         if ((val & 0x100) == 0x100) {
 912                 /* Clear IRQ Interrupt */
 913                 val |= 0x100;
 914                 val &= ~(0x0);
 915                 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
 916         } else {
 917                 unsigned int cnt = 0;
 918                 while (cnt++ < 0x1FF) {
 919                         if  ((val & 0x100) == 0x100)
 920                                 return 0;
 921                         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 922                 }
 923         }
 924
 925         return 1;
 926 }
 927
 928 static int __devinit omap_nand_probe(struct platform_device *pdev)
 929 {
 930         struct omap_nand_info           *info;
 931         struct omap_nand_platform_data  *pdata;
 932         int                             err;
 933         int                             i, offset;
 934
 935         pdata = pdev->dev.platform_data;
 936         if (pdata == NULL) {
 937                 dev_err(&pdev->dev, "platform data missing\n");
 938                 return -ENODEV;
 939         }
 940
 941         info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
 942         if (!info)
 943                 return -ENOMEM;
 944
 945         platform_set_drvdata(pdev, info);
 946
 947         spin_lock_init(&info->controller.lock);
 948         init_waitqueue_head(&info->controller.wq);
 949
 950         info->pdev = pdev;
 951
 952         info->gpmc_cs           = pdata->cs;
 953         info->phys_base         = pdata->phys_base;
 954
 955         info->mtd.priv          = &info->nand;
 956         info->mtd.name          = dev_name(&pdev->dev);
 957         info->mtd.owner         = THIS_MODULE;
 958
 959         info->nand.options      = pdata->devsize;
 960         info->nand.options      |= NAND_SKIP_BBTSCAN;
 961
 962         /* NAND write protect off */
 963         gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
 964
 965         if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
 966                                 pdev->dev.driver->name)) {
 967                 err = -EBUSY;
 968                 goto out_free_info;
 969         }
 970
 971         info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
 972         if (!info->nand.IO_ADDR_R) {
 973                 err = -ENOMEM;
 974                 goto out_release_mem_region;
 975         }
 976
 977         info->nand.controller = &info->controller;
 978
 979         info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
 980         info->nand.cmd_ctrl  = omap_hwcontrol;
 981
 982         /*
 983          * If RDY/BSY line is connected to OMAP then use the omap ready
 984          * funcrtion and the generic nand_wait function which reads the status
 985          * register after monitoring the RDY/BSY line.Otherwise use a standard
 986          * chip delay which is slightly more than tR (AC Timing) of the NAND
 987          * device and read status register until you get a failure or success
 988          */
 989         if (pdata->dev_ready) {
 990                 info->nand.dev_ready = omap_dev_ready;
 991                 info->nand.chip_delay = 0;
 992         } else {
 993                 info->nand.waitfunc = omap_wait;
 994                 info->nand.chip_delay = 50;
 995         }
 996
 997         switch (pdata->xfer_type) {
 998         case NAND_OMAP_PREFETCH_POLLED:
 999                 info->nand.read_buf   = omap_read_buf_pref;
1000                 info->nand.write_buf  = omap_write_buf_pref;
1001                 break;
1002
1003         case NAND_OMAP_POLLED:
1004                 if (info->nand.options & NAND_BUSWIDTH_16) {
1005                         info->nand.read_buf   = omap_read_buf16;
1006                         info->nand.write_buf  = omap_write_buf16;
1007                 } else {
1008                         info->nand.read_buf   = omap_read_buf8;
1009                         info->nand.write_buf  = omap_write_buf8;
1010                 }
1011                 break;
1012
1013         case NAND_OMAP_PREFETCH_DMA:
1014                 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
1015                                 omap_nand_dma_cb, &info->comp, &info->dma_ch);
1016                 if (err < 0) {
1017                         info->dma_ch = -1;
1018                         dev_err(&pdev->dev, "DMA request failed!\n");
1019                         goto out_release_mem_region;
1020                 } else {
1021                         omap_set_dma_dest_burst_mode(info->dma_ch,
1022                                         OMAP_DMA_DATA_BURST_16);
1023                         omap_set_dma_src_burst_mode(info->dma_ch,
1024                                         OMAP_DMA_DATA_BURST_16);
1025
1026                         info->nand.read_buf   = omap_read_buf_dma_pref;
1027                         info->nand.write_buf  = omap_write_buf_dma_pref;
1028                 }
1029                 break;
1030
1031         case NAND_OMAP_PREFETCH_IRQ:
1032                 err = request_irq(pdata->gpmc_irq,
1033                                 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
1034                 if (err) {
1035                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1036                                                         pdata->gpmc_irq, err);
1037                         goto out_release_mem_region;
1038                 } else {
1039                         info->gpmc_irq       = pdata->gpmc_irq;
1040                         info->nand.read_buf  = omap_read_buf_irq_pref;
1041                         info->nand.write_buf = omap_write_buf_irq_pref;
1042                 }
1043                 break;
1044
1045         default:
1046                 dev_err(&pdev->dev,
1047                         "xfer_type(%d) not supported!\n", pdata->xfer_type);
1048                 err = -EINVAL;
1049                 goto out_release_mem_region;
1050         }
1051
1052         info->nand.verify_buf = omap_verify_buf;
1053
1054         /* selsect the ecc type */
1055         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
1056                 info->nand.ecc.mode = NAND_ECC_SOFT;
1057         else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
1058                 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1059                 info->nand.ecc.bytes            = 3;
1060                 info->nand.ecc.size             = 512;
1061                 info->nand.ecc.calculate        = omap_calculate_ecc;
1062                 info->nand.ecc.hwctl            = omap_enable_hwecc;
1063                 info->nand.ecc.correct          = omap_correct_data;
1064                 info->nand.ecc.mode             = NAND_ECC_HW;
1065         }
1066
1067         /* DIP switches on some boards change between 8 and 16 bit
1068          * bus widths for flash.  Try the other width if the first try fails.
1069          */
1070         if (nand_scan_ident(&info->mtd, 1, NULL)) {
1071                 info->nand.options ^= NAND_BUSWIDTH_16;
1072                 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1073                         err = -ENXIO;
1074                         goto out_release_mem_region;
1075                 }
1076         }
1077
1078         /* rom code layout */
1079         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1080
1081                 if (info->nand.options & NAND_BUSWIDTH_16)
1082                         offset = 2;
1083                 else {
1084                         offset = 1;
1085                         info->nand.badblock_pattern = &bb_descrip_flashbased;
1086                 }
1087                 omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
1088                 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1089                         omap_oobinfo.eccpos[i] = i+offset;
1090
1091                 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
1092                 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1093                                         (offset + omap_oobinfo.eccbytes);
1094
1095                 info->nand.ecc.layout = &omap_oobinfo;
1096         }
1097
1098         /* second phase scan */
1099         if (nand_scan_tail(&info->mtd)) {
1100                 err = -ENXIO;
1101                 goto out_release_mem_region;
1102         }
1103
1104         mtd_device_parse_register(&info->mtd, NULL, 0,
1105                         pdata->parts, pdata->nr_parts);
1106
1107         platform_set_drvdata(pdev, &info->mtd);
1108
1109         return 0;
1110
1111 out_release_mem_region:
1112         release_mem_region(info->phys_base, NAND_IO_SIZE);
1113 out_free_info:
1114         kfree(info);
1115
1116         return err;
1117 }
1118
1119 static int omap_nand_remove(struct platform_device *pdev)
1120 {
1121         struct mtd_info *mtd = platform_get_drvdata(pdev);
1122         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1123                                                         mtd);
1124
1125         platform_set_drvdata(pdev, NULL);
1126         if (info->dma_ch != -1)
1127                 omap_free_dma(info->dma_ch);
1128
1129         if (info->gpmc_irq)
1130                 free_irq(info->gpmc_irq, info);
1131
1132         /* Release NAND device, its internal structures and partitions */
1133         nand_release(&info->mtd);
1134         iounmap(info->nand.IO_ADDR_R);
1135         kfree(&info->mtd);
1136         return 0;
1137 }
1138
1139 static struct platform_driver omap_nand_driver = {
1140         .probe          = omap_nand_probe,
1141         .remove         = omap_nand_remove,
1142         .driver         = {
1143                 .name   = DRIVER_NAME,
1144                 .owner  = THIS_MODULE,
1145         },
1146 };
1147
1148 static int __init omap_nand_init(void)
1149 {
1150         pr_info("%s driver initializing\n", DRIVER_NAME);
1151
1152         return platform_driver_register(&omap_nand_driver);
1153 }
1154
1155 static void __exit omap_nand_exit(void)
1156 {
1157         platform_driver_unregister(&omap_nand_driver);
1158 }
1159
1160 module_init(omap_nand_init);
1161 module_exit(omap_nand_exit);
1162
1163 MODULE_ALIAS("platform:" DRIVER_NAME);
1164 MODULE_LICENSE("GPL");
1165 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");