drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/tech/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *
  28  * This program is free software; you can redistribute it and/or modify
  29  * it under the terms of the GNU General Public License version 2 as
  30  * published by the Free Software Foundation.
  31  *
  32  */
  33
  34 #include <linux/module.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/err.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/types.h>
  41 #include <linux/mtd/mtd.h>
  42 #include <linux/mtd/nand.h>
  43 #include <linux/mtd/nand_ecc.h>
  44 #include <linux/mtd/compatmac.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/bitops.h>
  47 #include <linux/leds.h>
  48 #include <asm/io.h>
  49
  50 #ifdef CONFIG_MTD_PARTITIONS
  51 #include <linux/mtd/partitions.h>
  52 #endif
  53
  54 /* Define default oob placement schemes for large and small page devices */
  55 static struct nand_ecclayout nand_oob_8 = {
  56         .eccbytes = 3,
  57         .eccpos = {0, 1, 2},
  58         .oobfree = {
  59                 {.offset = 3,
  60                  .length = 2},
  61                 {.offset = 6,
  62                  .length = 2}}
  63 };
  64
  65 static struct nand_ecclayout nand_oob_16 = {
  66         .eccbytes = 6,
  67         .eccpos = {0, 1, 2, 3, 6, 7},
  68         .oobfree = {
  69                 {.offset = 8,
  70                  . length = 8}}
  71 };
  72
  73 static struct nand_ecclayout nand_oob_64 = {
  74         .eccbytes = 24,
  75         .eccpos = {
  76                    40, 41, 42, 43, 44, 45, 46, 47,
  77                    48, 49, 50, 51, 52, 53, 54, 55,
  78                    56, 57, 58, 59, 60, 61, 62, 63},
  79         .oobfree = {
  80                 {.offset = 2,
  81                  .length = 38}}
  82 };
  83
  84 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
  85                            int new_state);
  86
  87 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  88                              struct mtd_oob_ops *ops);
  89
  90 /*
  91  * For devices which display every fart in the system on a seperate LED. Is
  92  * compiled away when LED support is disabled.
  93  */
  94 DEFINE_LED_TRIGGER(nand_led_trigger);
  95
  96 /**
  97  * nand_release_device - [GENERIC] release chip
  98  * @mtd:        MTD device structure
  99  *
 100  * Deselect, release chip lock and wake up anyone waiting on the device
 101  */
 102 static void nand_release_device(struct mtd_info *mtd)
 103 {
 104         struct nand_chip *chip = mtd->priv;
 105
 106         /* De-select the NAND device */
 107         chip->select_chip(mtd, -1);
 108
 109         /* Release the controller and the chip */
 110         spin_lock(&chip->controller->lock);
 111         chip->controller->active = NULL;
 112         chip->state = FL_READY;
 113         wake_up(&chip->controller->wq);
 114         spin_unlock(&chip->controller->lock);
 115 }
 116
 117 /**
 118  * nand_read_byte - [DEFAULT] read one byte from the chip
 119  * @mtd:        MTD device structure
 120  *
 121  * Default read function for 8bit buswith
 122  */
 123 static uint8_t nand_read_byte(struct mtd_info *mtd)
 124 {
 125         struct nand_chip *chip = mtd->priv;
 126         return readb(chip->IO_ADDR_R);
 127 }
 128
 129 /**
 130  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 131  * @mtd:        MTD device structure
 132  *
 133  * Default read function for 16bit buswith with
 134  * endianess conversion
 135  */
 136 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 137 {
 138         struct nand_chip *chip = mtd->priv;
 139         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 140 }
 141
 142 /**
 143  * nand_read_word - [DEFAULT] read one word from the chip
 144  * @mtd:        MTD device structure
 145  *
 146  * Default read function for 16bit buswith without
 147  * endianess conversion
 148  */
 149 static u16 nand_read_word(struct mtd_info *mtd)
 150 {
 151         struct nand_chip *chip = mtd->priv;
 152         return readw(chip->IO_ADDR_R);
 153 }
 154
 155 /**
 156  * nand_select_chip - [DEFAULT] control CE line
 157  * @mtd:        MTD device structure
 158  * @chipnr:     chipnumber to select, -1 for deselect
 159  *
 160  * Default select function for 1 chip devices.
 161  */
 162 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 163 {
 164         struct nand_chip *chip = mtd->priv;
 165
 166         switch (chipnr) {
 167         case -1:
 168                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 169                 break;
 170         case 0:
 171                 break;
 172
 173         default:
 174                 BUG();
 175         }
 176 }
 177
 178 /**
 179  * nand_write_buf - [DEFAULT] write buffer to chip
 180  * @mtd:        MTD device structure
 181  * @buf:        data buffer
 182  * @len:        number of bytes to write
 183  *
 184  * Default write function for 8bit buswith
 185  */
 186 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 187 {
 188         int i;
 189         struct nand_chip *chip = mtd->priv;
 190
 191         for (i = 0; i < len; i++)
 192                 writeb(buf[i], chip->IO_ADDR_W);
 193 }
 194
 195 /**
 196  * nand_read_buf - [DEFAULT] read chip data into buffer
 197  * @mtd:        MTD device structure
 198  * @buf:        buffer to store date
 199  * @len:        number of bytes to read
 200  *
 201  * Default read function for 8bit buswith
 202  */
 203 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 204 {
 205         int i;
 206         struct nand_chip *chip = mtd->priv;
 207
 208         for (i = 0; i < len; i++)
 209                 buf[i] = readb(chip->IO_ADDR_R);
 210 }
 211
 212 /**
 213  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 214  * @mtd:        MTD device structure
 215  * @buf:        buffer containing the data to compare
 216  * @len:        number of bytes to compare
 217  *
 218  * Default verify function for 8bit buswith
 219  */
 220 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 221 {
 222         int i;
 223         struct nand_chip *chip = mtd->priv;
 224
 225         for (i = 0; i < len; i++)
 226                 if (buf[i] != readb(chip->IO_ADDR_R))
 227                         return -EFAULT;
 228         return 0;
 229 }
 230
 231 /**
 232  * nand_write_buf16 - [DEFAULT] write buffer to chip
 233  * @mtd:        MTD device structure
 234  * @buf:        data buffer
 235  * @len:        number of bytes to write
 236  *
 237  * Default write function for 16bit buswith
 238  */
 239 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 240 {
 241         int i;
 242         struct nand_chip *chip = mtd->priv;
 243         u16 *p = (u16 *) buf;
 244         len >>= 1;
 245
 246         for (i = 0; i < len; i++)
 247                 writew(p[i], chip->IO_ADDR_W);
 248
 249 }
 250
 251 /**
 252  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 253  * @mtd:        MTD device structure
 254  * @buf:        buffer to store date
 255  * @len:        number of bytes to read
 256  *
 257  * Default read function for 16bit buswith
 258  */
 259 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 260 {
 261         int i;
 262         struct nand_chip *chip = mtd->priv;
 263         u16 *p = (u16 *) buf;
 264         len >>= 1;
 265
 266         for (i = 0; i < len; i++)
 267                 p[i] = readw(chip->IO_ADDR_R);
 268 }
 269
 270 /**
 271  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 272  * @mtd:        MTD device structure
 273  * @buf:        buffer containing the data to compare
 274  * @len:        number of bytes to compare
 275  *
 276  * Default verify function for 16bit buswith
 277  */
 278 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 279 {
 280         int i;
 281         struct nand_chip *chip = mtd->priv;
 282         u16 *p = (u16 *) buf;
 283         len >>= 1;
 284
 285         for (i = 0; i < len; i++)
 286                 if (p[i] != readw(chip->IO_ADDR_R))
 287                         return -EFAULT;
 288
 289         return 0;
 290 }
 291
 292 /**
 293  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 294  * @mtd:        MTD device structure
 295  * @ofs:        offset from device start
 296  * @getchip:    0, if the chip is already selected
 297  *
 298  * Check, if the block is bad.
 299  */
 300 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 301 {
 302         int page, chipnr, res = 0;
 303         struct nand_chip *chip = mtd->priv;
 304         u16 bad;
 305
 306         if (getchip) {
 307                 page = (int)(ofs >> chip->page_shift);
 308                 chipnr = (int)(ofs >> chip->chip_shift);
 309
 310                 nand_get_device(chip, mtd, FL_READING);
 311
 312                 /* Select the NAND device */
 313                 chip->select_chip(mtd, chipnr);
 314         } else
 315                 page = (int)ofs;
 316
 317         if (chip->options & NAND_BUSWIDTH_16) {
 318                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 319                               page & chip->pagemask);
 320                 bad = cpu_to_le16(chip->read_word(mtd));
 321                 if (chip->badblockpos & 0x1)
 322                         bad >>= 8;
 323                 if ((bad & 0xFF) != 0xff)
 324                         res = 1;
 325         } else {
 326                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 327                               page & chip->pagemask);
 328                 if (chip->read_byte(mtd) != 0xff)
 329                         res = 1;
 330         }
 331
 332         if (getchip)
 333                 nand_release_device(mtd);
 334
 335         return res;
 336 }
 337
 338 /**
 339  * nand_default_block_markbad - [DEFAULT] mark a block bad
 340  * @mtd:        MTD device structure
 341  * @ofs:        offset from device start
 342  *
 343  * This is the default implementation, which can be overridden by
 344  * a hardware specific driver.
 345 */
 346 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 347 {
 348         struct nand_chip *chip = mtd->priv;
 349         uint8_t buf[2] = { 0, 0 };
 350         int block, ret;
 351
 352         /* Get block number */
 353         block = ((int)ofs) >> chip->bbt_erase_shift;
 354         if (chip->bbt)
 355                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 356
 357         /* Do we have a flash based bad block table ? */
 358         if (chip->options & NAND_USE_FLASH_BBT)
 359                 ret = nand_update_bbt(mtd, ofs);
 360         else {
 361                 /* We write two bytes, so we dont have to mess with 16 bit
 362                  * access
 363                  */
 364                 ofs += mtd->oobsize;
 365                 chip->ops.len = chip->ops.ooblen = 2;
 366                 chip->ops.datbuf = NULL;
 367                 chip->ops.oobbuf = buf;
 368                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 369
 370                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 371         }
 372         if (!ret)
 373                 mtd->ecc_stats.badblocks++;
 374         return ret;
 375 }
 376
 377 /**
 378  * nand_check_wp - [GENERIC] check if the chip is write protected
 379  * @mtd:        MTD device structure
 380  * Check, if the device is write protected
 381  *
 382  * The function expects, that the device is already selected
 383  */
 384 static int nand_check_wp(struct mtd_info *mtd)
 385 {
 386         struct nand_chip *chip = mtd->priv;
 387         /* Check the WP bit */
 388         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 389         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 390 }
 391
 392 /**
 393  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 394  * @mtd:        MTD device structure
 395  * @ofs:        offset from device start
 396  * @getchip:    0, if the chip is already selected
 397  * @allowbbt:   1, if its allowed to access the bbt area
 398  *
 399  * Check, if the block is bad. Either by reading the bad block table or
 400  * calling of the scan function.
 401  */
 402 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 403                                int allowbbt)
 404 {
 405         struct nand_chip *chip = mtd->priv;
 406
 407         if (!chip->bbt)
 408                 return chip->block_bad(mtd, ofs, getchip);
 409
 410         /* Return info from the table */
 411         return nand_isbad_bbt(mtd, ofs, allowbbt);
 412 }
 413
 414 /*
 415  * Wait for the ready pin, after a command
 416  * The timeout is catched later.
 417  */
 418 void nand_wait_ready(struct mtd_info *mtd)
 419 {
 420         struct nand_chip *chip = mtd->priv;
 421         unsigned long timeo = jiffies + 2;
 422
 423         led_trigger_event(nand_led_trigger, LED_FULL);
 424         /* wait until command is processed or timeout occures */
 425         do {
 426                 if (chip->dev_ready(mtd))
 427                         break;
 428                 touch_softlockup_watchdog();
 429         } while (time_before(jiffies, timeo));
 430         led_trigger_event(nand_led_trigger, LED_OFF);
 431 }
 432 EXPORT_SYMBOL_GPL(nand_wait_ready);
 433
 434 /**
 435  * nand_command - [DEFAULT] Send command to NAND device
 436  * @mtd:        MTD device structure
 437  * @command:    the command to be sent
 438  * @column:     the column address for this command, -1 if none
 439  * @page_addr:  the page address for this command, -1 if none
 440  *
 441  * Send command to NAND device. This function is used for small page
 442  * devices (256/512 Bytes per page)
 443  */
 444 static void nand_command(struct mtd_info *mtd, unsigned int command,
 445                          int column, int page_addr)
 446 {
 447         register struct nand_chip *chip = mtd->priv;
 448         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 449
 450         /*
 451          * Write out the command to the device.
 452          */
 453         if (command == NAND_CMD_SEQIN) {
 454                 int readcmd;
 455
 456                 if (column >= mtd->writesize) {
 457                         /* OOB area */
 458                         column -= mtd->writesize;
 459                         readcmd = NAND_CMD_READOOB;
 460                 } else if (column < 256) {
 461                         /* First 256 bytes --> READ0 */
 462                         readcmd = NAND_CMD_READ0;
 463                 } else {
 464                         column -= 256;
 465                         readcmd = NAND_CMD_READ1;
 466                 }
 467                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 468                 ctrl &= ~NAND_CTRL_CHANGE;
 469         }
 470         chip->cmd_ctrl(mtd, command, ctrl);
 471
 472         /*
 473          * Address cycle, when necessary
 474          */
 475         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 476         /* Serially input address */
 477         if (column != -1) {
 478                 /* Adjust columns for 16 bit buswidth */
 479                 if (chip->options & NAND_BUSWIDTH_16)
 480                         column >>= 1;
 481                 chip->cmd_ctrl(mtd, column, ctrl);
 482                 ctrl &= ~NAND_CTRL_CHANGE;
 483         }
 484         if (page_addr != -1) {
 485                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 486                 ctrl &= ~NAND_CTRL_CHANGE;
 487                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 488                 /* One more address cycle for devices > 32MiB */
 489                 if (chip->chipsize > (32 << 20))
 490                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 491         }
 492         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 493
 494         /*
 495          * program and erase have their own busy handlers
 496          * status and sequential in needs no delay
 497          */
 498         switch (command) {
 499
 500         case NAND_CMD_PAGEPROG:
 501         case NAND_CMD_ERASE1:
 502         case NAND_CMD_ERASE2:
 503         case NAND_CMD_SEQIN:
 504         case NAND_CMD_STATUS:
 505                 return;
 506
 507         case NAND_CMD_RESET:
 508                 if (chip->dev_ready)
 509                         break;
 510                 udelay(chip->chip_delay);
 511                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 512                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 513                 chip->cmd_ctrl(mtd,
 514                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 515                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 516                 return;
 517
 518                 /* This applies to read commands */
 519         default:
 520                 /*
 521                  * If we don't have access to the busy pin, we apply the given
 522                  * command delay
 523                  */
 524                 if (!chip->dev_ready) {
 525                         udelay(chip->chip_delay);
 526                         return;
 527                 }
 528         }
 529         /* Apply this short delay always to ensure that we do wait tWB in
 530          * any case on any machine. */
 531         ndelay(100);
 532
 533         nand_wait_ready(mtd);
 534 }
 535
 536 /**
 537  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 538  * @mtd:        MTD device structure
 539  * @command:    the command to be sent
 540  * @column:     the column address for this command, -1 if none
 541  * @page_addr:  the page address for this command, -1 if none
 542  *
 543  * Send command to NAND device. This is the version for the new large page
 544  * devices We dont have the separate regions as we have in the small page
 545  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 546  */
 547 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 548                             int column, int page_addr)
 549 {
 550         register struct nand_chip *chip = mtd->priv;
 551
 552         /* Emulate NAND_CMD_READOOB */
 553         if (command == NAND_CMD_READOOB) {
 554                 column += mtd->writesize;
 555                 command = NAND_CMD_READ0;
 556         }
 557
 558         /* Command latch cycle */
 559         chip->cmd_ctrl(mtd, command & 0xff,
 560                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 561
 562         if (column != -1 || page_addr != -1) {
 563                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 564
 565                 /* Serially input address */
 566                 if (column != -1) {
 567                         /* Adjust columns for 16 bit buswidth */
 568                         if (chip->options & NAND_BUSWIDTH_16)
 569                                 column >>= 1;
 570                         chip->cmd_ctrl(mtd, column, ctrl);
 571                         ctrl &= ~NAND_CTRL_CHANGE;
 572                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 573                 }
 574                 if (page_addr != -1) {
 575                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 576                         chip->cmd_ctrl(mtd, page_addr >> 8,
 577                                        NAND_NCE | NAND_ALE);
 578                         /* One more address cycle for devices > 128MiB */
 579                         if (chip->chipsize > (128 << 20))
 580                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 581                                                NAND_NCE | NAND_ALE);
 582                 }
 583         }
 584         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 585
 586         /*
 587          * program and erase have their own busy handlers
 588          * status, sequential in, and deplete1 need no delay
 589          */
 590         switch (command) {
 591
 592         case NAND_CMD_CACHEDPROG:
 593         case NAND_CMD_PAGEPROG:
 594         case NAND_CMD_ERASE1:
 595         case NAND_CMD_ERASE2:
 596         case NAND_CMD_SEQIN:
 597         case NAND_CMD_RNDIN:
 598         case NAND_CMD_STATUS:
 599         case NAND_CMD_DEPLETE1:
 600                 return;
 601
 602                 /*
 603                  * read error status commands require only a short delay
 604                  */
 605         case NAND_CMD_STATUS_ERROR:
 606         case NAND_CMD_STATUS_ERROR0:
 607         case NAND_CMD_STATUS_ERROR1:
 608         case NAND_CMD_STATUS_ERROR2:
 609         case NAND_CMD_STATUS_ERROR3:
 610                 udelay(chip->chip_delay);
 611                 return;
 612
 613         case NAND_CMD_RESET:
 614                 if (chip->dev_ready)
 615                         break;
 616                 udelay(chip->chip_delay);
 617                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 618                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 619                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 620                                NAND_NCE | NAND_CTRL_CHANGE);
 621                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 622                 return;
 623
 624         case NAND_CMD_RNDOUT:
 625                 /* No ready / busy check necessary */
 626                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 627                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 628                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 629                                NAND_NCE | NAND_CTRL_CHANGE);
 630                 return;
 631
 632         case NAND_CMD_READ0:
 633                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 634                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 635                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 636                                NAND_NCE | NAND_CTRL_CHANGE);
 637
 638                 /* This applies to read commands */
 639         default:
 640                 /*
 641                  * If we don't have access to the busy pin, we apply the given
 642                  * command delay
 643                  */
 644                 if (!chip->dev_ready) {
 645                         udelay(chip->chip_delay);
 646                         return;
 647                 }
 648         }
 649
 650         /* Apply this short delay always to ensure that we do wait tWB in
 651          * any case on any machine. */
 652         ndelay(100);
 653
 654         nand_wait_ready(mtd);
 655 }
 656
 657 /**
 658  * nand_get_device - [GENERIC] Get chip for selected access
 659  * @chip:       the nand chip descriptor
 660  * @mtd:        MTD device structure
 661  * @new_state:  the state which is requested
 662  *
 663  * Get the device and lock it for exclusive access
 664  */
 665 static int
 666 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 667 {
 668         spinlock_t *lock = &chip->controller->lock;
 669         wait_queue_head_t *wq = &chip->controller->wq;
 670         DECLARE_WAITQUEUE(wait, current);
 671  retry:
 672         spin_lock(lock);
 673
 674         /* Hardware controller shared among independend devices */
 675         /* Hardware controller shared among independend devices */
 676         if (!chip->controller->active)
 677                 chip->controller->active = chip;
 678
 679         if (chip->controller->active == chip && chip->state == FL_READY) {
 680                 chip->state = new_state;
 681                 spin_unlock(lock);
 682                 return 0;
 683         }
 684         if (new_state == FL_PM_SUSPENDED) {
 685                 spin_unlock(lock);
 686                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 687         }
 688         set_current_state(TASK_UNINTERRUPTIBLE);
 689         add_wait_queue(wq, &wait);
 690         spin_unlock(lock);
 691         schedule();
 692         remove_wait_queue(wq, &wait);
 693         goto retry;
 694 }
 695
 696 /**
 697  * nand_wait - [DEFAULT]  wait until the command is done
 698  * @mtd:        MTD device structure
 699  * @chip:       NAND chip structure
 700  *
 701  * Wait for command done. This applies to erase and program only
 702  * Erase can take up to 400ms and program up to 20ms according to
 703  * general NAND and SmartMedia specs
 704  */
 705 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 706 {
 707
 708         unsigned long timeo = jiffies;
 709         int status, state = chip->state;
 710
 711         if (state == FL_ERASING)
 712                 timeo += (HZ * 400) / 1000;
 713         else
 714                 timeo += (HZ * 20) / 1000;
 715
 716         led_trigger_event(nand_led_trigger, LED_FULL);
 717
 718         /* Apply this short delay always to ensure that we do wait tWB in
 719          * any case on any machine. */
 720         ndelay(100);
 721
 722         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 723                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 724         else
 725                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 726
 727         while (time_before(jiffies, timeo)) {
 728                 if (chip->dev_ready) {
 729                         if (chip->dev_ready(mtd))
 730                                 break;
 731                 } else {
 732                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 733                                 break;
 734                 }
 735                 cond_resched();
 736         }
 737         led_trigger_event(nand_led_trigger, LED_OFF);
 738
 739         status = (int)chip->read_byte(mtd);
 740         return status;
 741 }
 742
 743 /**
 744  * nand_read_page_raw - [Intern] read raw page data without ecc
 745  * @mtd:        mtd info structure
 746  * @chip:       nand chip info structure
 747  * @buf:        buffer to store read data
 748  */
 749 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 750                               uint8_t *buf)
 751 {
 752         chip->read_buf(mtd, buf, mtd->writesize);
 753         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 754         return 0;
 755 }
 756
 757 /**
 758  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 759  * @mtd:        mtd info structure
 760  * @chip:       nand chip info structure
 761  * @buf:        buffer to store read data
 762  */
 763 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 764                                 uint8_t *buf)
 765 {
 766         int i, eccsize = chip->ecc.size;
 767         int eccbytes = chip->ecc.bytes;
 768         int eccsteps = chip->ecc.steps;
 769         uint8_t *p = buf;
 770         uint8_t *ecc_calc = chip->buffers->ecccalc;
 771         uint8_t *ecc_code = chip->buffers->ecccode;
 772         int *eccpos = chip->ecc.layout->eccpos;
 773
 774         nand_read_page_raw(mtd, chip, buf);
 775
 776         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 777                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 778
 779         for (i = 0; i < chip->ecc.total; i++)
 780                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 781
 782         eccsteps = chip->ecc.steps;
 783         p = buf;
 784
 785         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 786                 int stat;
 787
 788                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 789                 if (stat == -1)
 790                         mtd->ecc_stats.failed++;
 791                 else
 792                         mtd->ecc_stats.corrected += stat;
 793         }
 794         return 0;
 795 }
 796
 797 /**
 798  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
 799  * @mtd:        mtd info structure
 800  * @chip:       nand chip info structure
 801  * @buf:        buffer to store read data
 802  *
 803  * Not for syndrome calculating ecc controllers which need a special oob layout
 804  */
 805 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 806                                 uint8_t *buf)
 807 {
 808         int i, eccsize = chip->ecc.size;
 809         int eccbytes = chip->ecc.bytes;
 810         int eccsteps = chip->ecc.steps;
 811         uint8_t *p = buf;
 812         uint8_t *ecc_calc = chip->buffers->ecccalc;
 813         uint8_t *ecc_code = chip->buffers->ecccode;
 814         int *eccpos = chip->ecc.layout->eccpos;
 815
 816         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 817                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 818                 chip->read_buf(mtd, p, eccsize);
 819                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 820         }
 821         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 822
 823         for (i = 0; i < chip->ecc.total; i++)
 824                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 825
 826         eccsteps = chip->ecc.steps;
 827         p = buf;
 828
 829         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 830                 int stat;
 831
 832                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 833                 if (stat == -1)
 834                         mtd->ecc_stats.failed++;
 835                 else
 836                         mtd->ecc_stats.corrected += stat;
 837         }
 838         return 0;
 839 }
 840
 841 /**
 842  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
 843  * @mtd:        mtd info structure
 844  * @chip:       nand chip info structure
 845  * @buf:        buffer to store read data
 846  *
 847  * The hw generator calculates the error syndrome automatically. Therefor
 848  * we need a special oob layout and handling.
 849  */
 850 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 851                                    uint8_t *buf)
 852 {
 853         int i, eccsize = chip->ecc.size;
 854         int eccbytes = chip->ecc.bytes;
 855         int eccsteps = chip->ecc.steps;
 856         uint8_t *p = buf;
 857         uint8_t *oob = chip->oob_poi;
 858
 859         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 860                 int stat;
 861
 862                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 863                 chip->read_buf(mtd, p, eccsize);
 864
 865                 if (chip->ecc.prepad) {
 866                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 867                         oob += chip->ecc.prepad;
 868                 }
 869
 870                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
 871                 chip->read_buf(mtd, oob, eccbytes);
 872                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 873
 874                 if (stat == -1)
 875                         mtd->ecc_stats.failed++;
 876                 else
 877                         mtd->ecc_stats.corrected += stat;
 878
 879                 oob += eccbytes;
 880
 881                 if (chip->ecc.postpad) {
 882                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 883                         oob += chip->ecc.postpad;
 884                 }
 885         }
 886
 887         /* Calculate remaining oob bytes */
 888         i = mtd->oobsize - (oob - chip->oob_poi);
 889         if (i)
 890                 chip->read_buf(mtd, oob, i);
 891
 892         return 0;
 893 }
 894
 895 /**
 896  * nand_transfer_oob - [Internal] Transfer oob to client buffer
 897  * @chip:       nand chip structure
 898  * @oob:        oob destination address
 899  * @ops:        oob ops structure
 900  * @len:        size of oob to transfer
 901  */
 902 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
 903                                   struct mtd_oob_ops *ops, size_t len)
 904 {
 905         switch(ops->mode) {
 906
 907         case MTD_OOB_PLACE:
 908         case MTD_OOB_RAW:
 909                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
 910                 return oob + len;
 911
 912         case MTD_OOB_AUTO: {
 913                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
 914                 uint32_t boffs = 0, roffs = ops->ooboffs;
 915                 size_t bytes = 0;
 916
 917                 for(; free->length && len; free++, len -= bytes) {
 918                         /* Read request not from offset 0 ? */
 919                         if (unlikely(roffs)) {
 920                                 if (roffs >= free->length) {
 921                                         roffs -= free->length;
 922                                         continue;
 923                                 }
 924                                 boffs = free->offset + roffs;
 925                                 bytes = min_t(size_t, len,
 926                                               (free->length - roffs));
 927                                 roffs = 0;
 928                         } else {
 929                                 bytes = min_t(size_t, len, free->length);
 930                                 boffs = free->offset;
 931                         }
 932                         memcpy(oob, chip->oob_poi + boffs, bytes);
 933                         oob += bytes;
 934                 }
 935                 return oob;
 936         }
 937         default:
 938                 BUG();
 939         }
 940         return NULL;
 941 }
 942
 943 /**
 944  * nand_do_read_ops - [Internal] Read data with ECC
 945  *
 946  * @mtd:        MTD device structure
 947  * @from:       offset to read from
 948  * @ops:        oob ops structure
 949  *
 950  * Internal function. Called with chip held.
 951  */
 952 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 953                             struct mtd_oob_ops *ops)
 954 {
 955         int chipnr, page, realpage, col, bytes, aligned;
 956         struct nand_chip *chip = mtd->priv;
 957         struct mtd_ecc_stats stats;
 958         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
 959         int sndcmd = 1;
 960         int ret = 0;
 961         uint32_t readlen = ops->len;
 962         uint32_t oobreadlen = ops->ooblen;
 963         uint8_t *bufpoi, *oob, *buf;
 964
 965         stats = mtd->ecc_stats;
 966
 967         chipnr = (int)(from >> chip->chip_shift);
 968         chip->select_chip(mtd, chipnr);
 969
 970         realpage = (int)(from >> chip->page_shift);
 971         page = realpage & chip->pagemask;
 972
 973         col = (int)(from & (mtd->writesize - 1));
 974
 975         buf = ops->datbuf;
 976         oob = ops->oobbuf;
 977
 978         while(1) {
 979                 bytes = min(mtd->writesize - col, readlen);
 980                 aligned = (bytes == mtd->writesize);
 981
 982                 /* Is the current page in the buffer ? */
 983                 if (realpage != chip->pagebuf || oob) {
 984                         bufpoi = aligned ? buf : chip->buffers->databuf;
 985
 986                         if (likely(sndcmd)) {
 987                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 988                                 sndcmd = 0;
 989                         }
 990
 991                         /* Now read the page into the buffer */
 992                         if (unlikely(ops->mode == MTD_OOB_RAW))
 993                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
 994                         else
 995                                 ret = chip->ecc.read_page(mtd, chip, bufpoi);
 996                         if (ret < 0)
 997                                 break;
 998
 999                         /* Transfer not aligned data */
1000                         if (!aligned) {
1001                                 chip->pagebuf = realpage;
1002                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1003                         }
1004
1005                         buf += bytes;
1006
1007                         if (unlikely(oob)) {
1008                                 /* Raw mode does data:oob:data:oob */
1009                                 if (ops->mode != MTD_OOB_RAW) {
1010                                         int toread = min(oobreadlen,
1011                                                 chip->ecc.layout->oobavail);
1012                                         if (toread) {
1013                                                 oob = nand_transfer_oob(chip,
1014                                                         oob, ops, toread);
1015                                                 oobreadlen -= toread;
1016                                         }
1017                                 } else
1018                                         buf = nand_transfer_oob(chip,
1019                                                 buf, ops, mtd->oobsize);
1020                         }
1021
1022                         if (!(chip->options & NAND_NO_READRDY)) {
1023                                 /*
1024                                  * Apply delay or wait for ready/busy pin. Do
1025                                  * this before the AUTOINCR check, so no
1026                                  * problems arise if a chip which does auto
1027                                  * increment is marked as NOAUTOINCR by the
1028                                  * board driver.
1029                                  */
1030                                 if (!chip->dev_ready)
1031                                         udelay(chip->chip_delay);
1032                                 else
1033                                         nand_wait_ready(mtd);
1034                         }
1035                 } else {
1036                         memcpy(buf, chip->buffers->databuf + col, bytes);
1037                         buf += bytes;
1038                 }
1039
1040                 readlen -= bytes;
1041
1042                 if (!readlen)
1043                         break;
1044
1045                 /* For subsequent reads align to page boundary. */
1046                 col = 0;
1047                 /* Increment page address */
1048                 realpage++;
1049
1050                 page = realpage & chip->pagemask;
1051                 /* Check, if we cross a chip boundary */
1052                 if (!page) {
1053                         chipnr++;
1054                         chip->select_chip(mtd, -1);
1055                         chip->select_chip(mtd, chipnr);
1056                 }
1057
1058                 /* Check, if the chip supports auto page increment
1059                  * or if we have hit a block boundary.
1060                  */
1061                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1062                         sndcmd = 1;
1063         }
1064
1065         ops->retlen = ops->len - (size_t) readlen;
1066         if (oob)
1067                 ops->oobretlen = ops->ooblen - oobreadlen;
1068
1069         if (ret)
1070                 return ret;
1071
1072         if (mtd->ecc_stats.failed - stats.failed)
1073                 return -EBADMSG;
1074
1075         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1076 }
1077
1078 /**
1079  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1080  * @mtd:        MTD device structure
1081  * @from:       offset to read from
1082  * @len:        number of bytes to read
1083  * @retlen:     pointer to variable to store the number of read bytes
1084  * @buf:        the databuffer to put data
1085  *
1086  * Get hold of the chip and call nand_do_read
1087  */
1088 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1089                      size_t *retlen, uint8_t *buf)
1090 {
1091         struct nand_chip *chip = mtd->priv;
1092         int ret;
1093
1094         /* Do not allow reads past end of device */
1095         if ((from + len) > mtd->size)
1096                 return -EINVAL;
1097         if (!len)
1098                 return 0;
1099
1100         nand_get_device(chip, mtd, FL_READING);
1101
1102         chip->ops.len = len;
1103         chip->ops.datbuf = buf;
1104         chip->ops.oobbuf = NULL;
1105
1106         ret = nand_do_read_ops(mtd, from, &chip->ops);
1107
1108         *retlen = chip->ops.retlen;
1109
1110         nand_release_device(mtd);
1111
1112         return ret;
1113 }
1114
1115 /**
1116  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1117  * @mtd:        mtd info structure
1118  * @chip:       nand chip info structure
1119  * @page:       page number to read
1120  * @sndcmd:     flag whether to issue read command or not
1121  */
1122 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1123                              int page, int sndcmd)
1124 {
1125         if (sndcmd) {
1126                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1127                 sndcmd = 0;
1128         }
1129         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1130         return sndcmd;
1131 }
1132
1133 /**
1134  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1135  *                          with syndromes
1136  * @mtd:        mtd info structure
1137  * @chip:       nand chip info structure
1138  * @page:       page number to read
1139  * @sndcmd:     flag whether to issue read command or not
1140  */
1141 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1142                                   int page, int sndcmd)
1143 {
1144         uint8_t *buf = chip->oob_poi;
1145         int length = mtd->oobsize;
1146         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1147         int eccsize = chip->ecc.size;
1148         uint8_t *bufpoi = buf;
1149         int i, toread, sndrnd = 0, pos;
1150
1151         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1152         for (i = 0; i < chip->ecc.steps; i++) {
1153                 if (sndrnd) {
1154                         pos = eccsize + i * (eccsize + chunk);
1155                         if (mtd->writesize > 512)
1156                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1157                         else
1158                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1159                 } else
1160                         sndrnd = 1;
1161                 toread = min_t(int, length, chunk);
1162                 chip->read_buf(mtd, bufpoi, toread);
1163                 bufpoi += toread;
1164                 length -= toread;
1165         }
1166         if (length > 0)
1167                 chip->read_buf(mtd, bufpoi, length);
1168
1169         return 1;
1170 }
1171
1172 /**
1173  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1174  * @mtd:        mtd info structure
1175  * @chip:       nand chip info structure
1176  * @page:       page number to write
1177  */
1178 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1179                               int page)
1180 {
1181         int status = 0;
1182         const uint8_t *buf = chip->oob_poi;
1183         int length = mtd->oobsize;
1184
1185         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1186         chip->write_buf(mtd, buf, length);
1187         /* Send command to program the OOB data */
1188         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1189
1190         status = chip->waitfunc(mtd, chip);
1191
1192         return status & NAND_STATUS_FAIL ? -EIO : 0;
1193 }
1194
1195 /**
1196  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1197  *                           with syndrome - only for large page flash !
1198  * @mtd:        mtd info structure
1199  * @chip:       nand chip info structure
1200  * @page:       page number to write
1201  */
1202 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1203                                    struct nand_chip *chip, int page)
1204 {
1205         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1206         int eccsize = chip->ecc.size, length = mtd->oobsize;
1207         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1208         const uint8_t *bufpoi = chip->oob_poi;
1209
1210         /*
1211          * data-ecc-data-ecc ... ecc-oob
1212          * or
1213          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1214          */
1215         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1216                 pos = steps * (eccsize + chunk);
1217                 steps = 0;
1218         } else
1219                 pos = eccsize;
1220
1221         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1222         for (i = 0; i < steps; i++) {
1223                 if (sndcmd) {
1224                         if (mtd->writesize <= 512) {
1225                                 uint32_t fill = 0xFFFFFFFF;
1226
1227                                 len = eccsize;
1228                                 while (len > 0) {
1229                                         int num = min_t(int, len, 4);
1230                                         chip->write_buf(mtd, (uint8_t *)&fill,
1231                                                         num);
1232                                         len -= num;
1233                                 }
1234                         } else {
1235                                 pos = eccsize + i * (eccsize + chunk);
1236                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1237                         }
1238                 } else
1239                         sndcmd = 1;
1240                 len = min_t(int, length, chunk);
1241                 chip->write_buf(mtd, bufpoi, len);
1242                 bufpoi += len;
1243                 length -= len;
1244         }
1245         if (length > 0)
1246                 chip->write_buf(mtd, bufpoi, length);
1247
1248         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1249         status = chip->waitfunc(mtd, chip);
1250
1251         return status & NAND_STATUS_FAIL ? -EIO : 0;
1252 }
1253
1254 /**
1255  * nand_do_read_oob - [Intern] NAND read out-of-band
1256  * @mtd:        MTD device structure
1257  * @from:       offset to read from
1258  * @ops:        oob operations description structure
1259  *
1260  * NAND read out-of-band data from the spare area
1261  */
1262 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1263                             struct mtd_oob_ops *ops)
1264 {
1265         int page, realpage, chipnr, sndcmd = 1;
1266         struct nand_chip *chip = mtd->priv;
1267         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1268         int readlen = ops->ooblen;
1269         int len;
1270         uint8_t *buf = ops->oobbuf;
1271
1272         DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1273               (unsigned long long)from, readlen);
1274
1275         if (ops->mode == MTD_OOB_AUTO)
1276                 len = chip->ecc.layout->oobavail;
1277         else
1278                 len = mtd->oobsize;
1279
1280         if (unlikely(ops->ooboffs >= len)) {
1281                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1282                         "Attempt to start read outside oob\n");
1283                 return -EINVAL;
1284         }
1285
1286         /* Do not allow reads past end of device */
1287         if (unlikely(from >= mtd->size ||
1288                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1289                                         (from >> chip->page_shift)) * len)) {
1290                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1291                         "Attempt read beyond end of device\n");
1292                 return -EINVAL;
1293         }
1294
1295         chipnr = (int)(from >> chip->chip_shift);
1296         chip->select_chip(mtd, chipnr);
1297
1298         /* Shift to get page */
1299         realpage = (int)(from >> chip->page_shift);
1300         page = realpage & chip->pagemask;
1301
1302         while(1) {
1303                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1304
1305                 len = min(len, readlen);
1306                 buf = nand_transfer_oob(chip, buf, ops, len);
1307
1308                 if (!(chip->options & NAND_NO_READRDY)) {
1309                         /*
1310                          * Apply delay or wait for ready/busy pin. Do this
1311                          * before the AUTOINCR check, so no problems arise if a
1312                          * chip which does auto increment is marked as
1313                          * NOAUTOINCR by the board driver.
1314                          */
1315                         if (!chip->dev_ready)
1316                                 udelay(chip->chip_delay);
1317                         else
1318                                 nand_wait_ready(mtd);
1319                 }
1320
1321                 readlen -= len;
1322                 if (!readlen)
1323                         break;
1324
1325                 /* Increment page address */
1326                 realpage++;
1327
1328                 page = realpage & chip->pagemask;
1329                 /* Check, if we cross a chip boundary */
1330                 if (!page) {
1331                         chipnr++;
1332                         chip->select_chip(mtd, -1);
1333                         chip->select_chip(mtd, chipnr);
1334                 }
1335
1336                 /* Check, if the chip supports auto page increment
1337                  * or if we have hit a block boundary.
1338                  */
1339                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1340                         sndcmd = 1;
1341         }
1342
1343         ops->oobretlen = ops->ooblen;
1344         return 0;
1345 }
1346
1347 /**
1348  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1349  * @mtd:        MTD device structure
1350  * @from:       offset to read from
1351  * @ops:        oob operation description structure
1352  *
1353  * NAND read data and/or out-of-band data
1354  */
1355 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1356                          struct mtd_oob_ops *ops)
1357 {
1358         struct nand_chip *chip = mtd->priv;
1359         int ret = -ENOTSUPP;
1360
1361         ops->retlen = 0;
1362
1363         /* Do not allow reads past end of device */
1364         if (ops->datbuf && (from + ops->len) > mtd->size) {
1365                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1366                       "Attempt read beyond end of device\n");
1367                 return -EINVAL;
1368         }
1369
1370         nand_get_device(chip, mtd, FL_READING);
1371
1372         switch(ops->mode) {
1373         case MTD_OOB_PLACE:
1374         case MTD_OOB_AUTO:
1375         case MTD_OOB_RAW:
1376                 break;
1377
1378         default:
1379                 goto out;
1380         }
1381
1382         if (!ops->datbuf)
1383                 ret = nand_do_read_oob(mtd, from, ops);
1384         else
1385                 ret = nand_do_read_ops(mtd, from, ops);
1386
1387  out:
1388         nand_release_device(mtd);
1389         return ret;
1390 }
1391
1392
1393 /**
1394  * nand_write_page_raw - [Intern] raw page write function
1395  * @mtd:        mtd info structure
1396  * @chip:       nand chip info structure
1397  * @buf:        data buffer
1398  */
1399 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1400                                 const uint8_t *buf)
1401 {
1402         chip->write_buf(mtd, buf, mtd->writesize);
1403         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1404 }
1405
1406 /**
1407  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1408  * @mtd:        mtd info structure
1409  * @chip:       nand chip info structure
1410  * @buf:        data buffer
1411  */
1412 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1413                                   const uint8_t *buf)
1414 {
1415         int i, eccsize = chip->ecc.size;
1416         int eccbytes = chip->ecc.bytes;
1417         int eccsteps = chip->ecc.steps;
1418         uint8_t *ecc_calc = chip->buffers->ecccalc;
1419         const uint8_t *p = buf;
1420         int *eccpos = chip->ecc.layout->eccpos;
1421
1422         /* Software ecc calculation */
1423         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1424                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1425
1426         for (i = 0; i < chip->ecc.total; i++)
1427                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1428
1429         nand_write_page_raw(mtd, chip, buf);
1430 }
1431
1432 /**
1433  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1434  * @mtd:        mtd info structure
1435  * @chip:       nand chip info structure
1436  * @buf:        data buffer
1437  */
1438 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1439                                   const uint8_t *buf)
1440 {
1441         int i, eccsize = chip->ecc.size;
1442         int eccbytes = chip->ecc.bytes;
1443         int eccsteps = chip->ecc.steps;
1444         uint8_t *ecc_calc = chip->buffers->ecccalc;
1445         const uint8_t *p = buf;
1446         int *eccpos = chip->ecc.layout->eccpos;
1447
1448         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1449                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1450                 chip->write_buf(mtd, p, eccsize);
1451                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1452         }
1453
1454         for (i = 0; i < chip->ecc.total; i++)
1455                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1456
1457         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1458 }
1459
1460 /**
1461  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1462  * @mtd:        mtd info structure
1463  * @chip:       nand chip info structure
1464  * @buf:        data buffer
1465  *
1466  * The hw generator calculates the error syndrome automatically. Therefor
1467  * we need a special oob layout and handling.
1468  */
1469 static void nand_write_page_syndrome(struct mtd_info *mtd,
1470                                     struct nand_chip *chip, const uint8_t *buf)
1471 {
1472         int i, eccsize = chip->ecc.size;
1473         int eccbytes = chip->ecc.bytes;
1474         int eccsteps = chip->ecc.steps;
1475         const uint8_t *p = buf;
1476         uint8_t *oob = chip->oob_poi;
1477
1478         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1479
1480                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1481                 chip->write_buf(mtd, p, eccsize);
1482
1483                 if (chip->ecc.prepad) {
1484                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1485                         oob += chip->ecc.prepad;
1486                 }
1487
1488                 chip->ecc.calculate(mtd, p, oob);
1489                 chip->write_buf(mtd, oob, eccbytes);
1490                 oob += eccbytes;
1491
1492                 if (chip->ecc.postpad) {
1493                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1494                         oob += chip->ecc.postpad;
1495                 }
1496         }
1497
1498         /* Calculate remaining oob bytes */
1499         i = mtd->oobsize - (oob - chip->oob_poi);
1500         if (i)
1501                 chip->write_buf(mtd, oob, i);
1502 }
1503
1504 /**
1505  * nand_write_page - [REPLACEABLE] write one page
1506  * @mtd:        MTD device structure
1507  * @chip:       NAND chip descriptor
1508  * @buf:        the data to write
1509  * @page:       page number to write
1510  * @cached:     cached programming
1511  * @raw:        use _raw version of write_page
1512  */
1513 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1514                            const uint8_t *buf, int page, int cached, int raw)
1515 {
1516         int status;
1517
1518         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1519
1520         if (unlikely(raw))
1521                 chip->ecc.write_page_raw(mtd, chip, buf);
1522         else
1523                 chip->ecc.write_page(mtd, chip, buf);
1524
1525         /*
1526          * Cached progamming disabled for now, Not sure if its worth the
1527          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1528          */
1529         cached = 0;
1530
1531         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1532
1533                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1534                 status = chip->waitfunc(mtd, chip);
1535                 /*
1536                  * See if operation failed and additional status checks are
1537                  * available
1538                  */
1539                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1540                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1541                                                page);
1542
1543                 if (status & NAND_STATUS_FAIL)
1544                         return -EIO;
1545         } else {
1546                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1547                 status = chip->waitfunc(mtd, chip);
1548         }
1549
1550 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1551         /* Send command to read back the data */
1552         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1553
1554         if (chip->verify_buf(mtd, buf, mtd->writesize))
1555                 return -EIO;
1556 #endif
1557         return 0;
1558 }
1559
1560 /**
1561  * nand_fill_oob - [Internal] Transfer client buffer to oob
1562  * @chip:       nand chip structure
1563  * @oob:        oob data buffer
1564  * @ops:        oob ops structure
1565  */
1566 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1567                                   struct mtd_oob_ops *ops)
1568 {
1569         size_t len = ops->ooblen;
1570
1571         switch(ops->mode) {
1572
1573         case MTD_OOB_PLACE:
1574         case MTD_OOB_RAW:
1575                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1576                 return oob + len;
1577
1578         case MTD_OOB_AUTO: {
1579                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1580                 uint32_t boffs = 0, woffs = ops->ooboffs;
1581                 size_t bytes = 0;
1582
1583                 for(; free->length && len; free++, len -= bytes) {
1584                         /* Write request not from offset 0 ? */
1585                         if (unlikely(woffs)) {
1586                                 if (woffs >= free->length) {
1587                                         woffs -= free->length;
1588                                         continue;
1589                                 }
1590                                 boffs = free->offset + woffs;
1591                                 bytes = min_t(size_t, len,
1592                                               (free->length - woffs));
1593                                 woffs = 0;
1594                         } else {
1595                                 bytes = min_t(size_t, len, free->length);
1596                                 boffs = free->offset;
1597                         }
1598                         memcpy(chip->oob_poi + boffs, oob, bytes);
1599                         oob += bytes;
1600                 }
1601                 return oob;
1602         }
1603         default:
1604                 BUG();
1605         }
1606         return NULL;
1607 }
1608
1609 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1610
1611 /**
1612  * nand_do_write_ops - [Internal] NAND write with ECC
1613  * @mtd:        MTD device structure
1614  * @to:         offset to write to
1615  * @ops:        oob operations description structure
1616  *
1617  * NAND write with ECC
1618  */
1619 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1620                              struct mtd_oob_ops *ops)
1621 {
1622         int chipnr, realpage, page, blockmask, column;
1623         struct nand_chip *chip = mtd->priv;
1624         uint32_t writelen = ops->len;
1625         uint8_t *oob = ops->oobbuf;
1626         uint8_t *buf = ops->datbuf;
1627         int ret, subpage;
1628
1629         ops->retlen = 0;
1630         if (!writelen)
1631                 return 0;
1632
1633         /* reject writes, which are not page aligned */
1634         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1635                 printk(KERN_NOTICE "nand_write: "
1636                        "Attempt to write not page aligned data\n");
1637                 return -EINVAL;
1638         }
1639
1640         column = to & (mtd->writesize - 1);
1641         subpage = column || (writelen & (mtd->writesize - 1));
1642
1643         if (subpage && oob)
1644                 return -EINVAL;
1645
1646         chipnr = (int)(to >> chip->chip_shift);
1647         chip->select_chip(mtd, chipnr);
1648
1649         /* Check, if it is write protected */
1650         if (nand_check_wp(mtd))
1651                 return -EIO;
1652
1653         realpage = (int)(to >> chip->page_shift);
1654         page = realpage & chip->pagemask;
1655         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1656
1657         /* Invalidate the page cache, when we write to the cached page */
1658         if (to <= (chip->pagebuf << chip->page_shift) &&
1659             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1660                 chip->pagebuf = -1;
1661
1662         /* If we're not given explicit OOB data, let it be 0xFF */
1663         if (likely(!oob))
1664                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1665
1666         while(1) {
1667                 int bytes = mtd->writesize;
1668                 int cached = writelen > bytes && page != blockmask;
1669                 uint8_t *wbuf = buf;
1670
1671                 /* Partial page write ? */
1672                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1673                         cached = 0;
1674                         bytes = min_t(int, bytes - column, (int) writelen);
1675                         chip->pagebuf = -1;
1676                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1677                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1678                         wbuf = chip->buffers->databuf;
1679                 }
1680
1681                 if (unlikely(oob))
1682                         oob = nand_fill_oob(chip, oob, ops);
1683
1684                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1685                                        (ops->mode == MTD_OOB_RAW));
1686                 if (ret)
1687                         break;
1688
1689                 writelen -= bytes;
1690                 if (!writelen)
1691                         break;
1692
1693                 column = 0;
1694                 buf += bytes;
1695                 realpage++;
1696
1697                 page = realpage & chip->pagemask;
1698                 /* Check, if we cross a chip boundary */
1699                 if (!page) {
1700                         chipnr++;
1701                         chip->select_chip(mtd, -1);
1702                         chip->select_chip(mtd, chipnr);
1703                 }
1704         }
1705
1706         ops->retlen = ops->len - writelen;
1707         if (unlikely(oob))
1708                 ops->oobretlen = ops->ooblen;
1709         return ret;
1710 }
1711
1712 /**
1713  * nand_write - [MTD Interface] NAND write with ECC
1714  * @mtd:        MTD device structure
1715  * @to:         offset to write to
1716  * @len:        number of bytes to write
1717  * @retlen:     pointer to variable to store the number of written bytes
1718  * @buf:        the data to write
1719  *
1720  * NAND write with ECC
1721  */
1722 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1723                           size_t *retlen, const uint8_t *buf)
1724 {
1725         struct nand_chip *chip = mtd->priv;
1726         int ret;
1727
1728         /* Do not allow reads past end of device */
1729         if ((to + len) > mtd->size)
1730                 return -EINVAL;
1731         if (!len)
1732                 return 0;
1733
1734         nand_get_device(chip, mtd, FL_WRITING);
1735
1736         chip->ops.len = len;
1737         chip->ops.datbuf = (uint8_t *)buf;
1738         chip->ops.oobbuf = NULL;
1739
1740         ret = nand_do_write_ops(mtd, to, &chip->ops);
1741
1742         *retlen = chip->ops.retlen;
1743
1744         nand_release_device(mtd);
1745
1746         return ret;
1747 }
1748
1749 /**
1750  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1751  * @mtd:        MTD device structure
1752  * @to:         offset to write to
1753  * @ops:        oob operation description structure
1754  *
1755  * NAND write out-of-band
1756  */
1757 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1758                              struct mtd_oob_ops *ops)
1759 {
1760         int chipnr, page, status, len;
1761         struct nand_chip *chip = mtd->priv;
1762
1763         DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1764               (unsigned int)to, (int)ops->ooblen);
1765
1766         if (ops->mode == MTD_OOB_AUTO)
1767                 len = chip->ecc.layout->oobavail;
1768         else
1769                 len = mtd->oobsize;
1770
1771         /* Do not allow write past end of page */
1772         if ((ops->ooboffs + ops->ooblen) > len) {
1773                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1774                       "Attempt to write past end of page\n");
1775                 return -EINVAL;
1776         }
1777
1778         if (unlikely(ops->ooboffs >= len)) {
1779                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1780                         "Attempt to start write outside oob\n");
1781                 return -EINVAL;
1782         }
1783
1784         /* Do not allow reads past end of device */
1785         if (unlikely(to >= mtd->size ||
1786                      ops->ooboffs + ops->ooblen >
1787                         ((mtd->size >> chip->page_shift) -
1788                          (to >> chip->page_shift)) * len)) {
1789                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1790                         "Attempt write beyond end of device\n");
1791                 return -EINVAL;
1792         }
1793
1794         chipnr = (int)(to >> chip->chip_shift);
1795         chip->select_chip(mtd, chipnr);
1796
1797         /* Shift to get page */
1798         page = (int)(to >> chip->page_shift);
1799
1800         /*
1801          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1802          * of my DiskOnChip 2000 test units) will clear the whole data page too
1803          * if we don't do this. I have no clue why, but I seem to have 'fixed'
1804          * it in the doc2000 driver in August 1999.  dwmw2.
1805          */
1806         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1807
1808         /* Check, if it is write protected */
1809         if (nand_check_wp(mtd))
1810                 return -EROFS;
1811
1812         /* Invalidate the page cache, if we write to the cached page */
1813         if (page == chip->pagebuf)
1814                 chip->pagebuf = -1;
1815
1816         memset(chip->oob_poi, 0xff, mtd->oobsize);
1817         nand_fill_oob(chip, ops->oobbuf, ops);
1818         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1819         memset(chip->oob_poi, 0xff, mtd->oobsize);
1820
1821         if (status)
1822                 return status;
1823
1824         ops->oobretlen = ops->ooblen;
1825
1826         return 0;
1827 }
1828
1829 /**
1830  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1831  * @mtd:        MTD device structure
1832  * @to:         offset to write to
1833  * @ops:        oob operation description structure
1834  */
1835 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
1836                           struct mtd_oob_ops *ops)
1837 {
1838         struct nand_chip *chip = mtd->priv;
1839         int ret = -ENOTSUPP;
1840
1841         ops->retlen = 0;
1842
1843         /* Do not allow writes past end of device */
1844         if (ops->datbuf && (to + ops->len) > mtd->size) {
1845                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1846                       "Attempt read beyond end of device\n");
1847                 return -EINVAL;
1848         }
1849
1850         nand_get_device(chip, mtd, FL_WRITING);
1851
1852         switch(ops->mode) {
1853         case MTD_OOB_PLACE:
1854         case MTD_OOB_AUTO:
1855         case MTD_OOB_RAW:
1856                 break;
1857
1858         default:
1859                 goto out;
1860         }
1861
1862         if (!ops->datbuf)
1863                 ret = nand_do_write_oob(mtd, to, ops);
1864         else
1865                 ret = nand_do_write_ops(mtd, to, ops);
1866
1867  out:
1868         nand_release_device(mtd);
1869         return ret;
1870 }
1871
1872 /**
1873  * single_erease_cmd - [GENERIC] NAND standard block erase command function
1874  * @mtd:        MTD device structure
1875  * @page:       the page address of the block which will be erased
1876  *
1877  * Standard erase command for NAND chips
1878  */
1879 static void single_erase_cmd(struct mtd_info *mtd, int page)
1880 {
1881         struct nand_chip *chip = mtd->priv;
1882         /* Send commands to erase a block */
1883         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1884         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1885 }
1886
1887 /**
1888  * multi_erease_cmd - [GENERIC] AND specific block erase command function
1889  * @mtd:        MTD device structure
1890  * @page:       the page address of the block which will be erased
1891  *
1892  * AND multi block erase command function
1893  * Erase 4 consecutive blocks
1894  */
1895 static void multi_erase_cmd(struct mtd_info *mtd, int page)
1896 {
1897         struct nand_chip *chip = mtd->priv;
1898         /* Send commands to erase a block */
1899         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1900         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1901         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1902         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1903         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1904 }
1905
1906 /**
1907  * nand_erase - [MTD Interface] erase block(s)
1908  * @mtd:        MTD device structure
1909  * @instr:      erase instruction
1910  *
1911  * Erase one ore more blocks
1912  */
1913 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1914 {
1915         return nand_erase_nand(mtd, instr, 0);
1916 }
1917
1918 #define BBT_PAGE_MASK   0xffffff3f
1919 /**
1920  * nand_erase_nand - [Internal] erase block(s)
1921  * @mtd:        MTD device structure
1922  * @instr:      erase instruction
1923  * @allowbbt:   allow erasing the bbt area
1924  *
1925  * Erase one ore more blocks
1926  */
1927 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1928                     int allowbbt)
1929 {
1930         int page, len, status, pages_per_block, ret, chipnr;
1931         struct nand_chip *chip = mtd->priv;
1932         int rewrite_bbt[NAND_MAX_CHIPS]={0};
1933         unsigned int bbt_masked_page = 0xffffffff;
1934
1935         DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
1936               (unsigned int)instr->addr, (unsigned int)instr->len);
1937
1938         /* Start address must align on block boundary */
1939         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
1940                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1941                 return -EINVAL;
1942         }
1943
1944         /* Length must align on block boundary */
1945         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
1946                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1947                       "Length not block aligned\n");
1948                 return -EINVAL;
1949         }
1950
1951         /* Do not allow erase past end of device */
1952         if ((instr->len + instr->addr) > mtd->size) {
1953                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1954                       "Erase past end of device\n");
1955                 return -EINVAL;
1956         }
1957
1958         instr->fail_addr = 0xffffffff;
1959
1960         /* Grab the lock and see if the device is available */
1961         nand_get_device(chip, mtd, FL_ERASING);
1962
1963         /* Shift to get first page */
1964         page = (int)(instr->addr >> chip->page_shift);
1965         chipnr = (int)(instr->addr >> chip->chip_shift);
1966
1967         /* Calculate pages in each block */
1968         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1969
1970         /* Select the NAND device */
1971         chip->select_chip(mtd, chipnr);
1972
1973         /* Check, if it is write protected */
1974         if (nand_check_wp(mtd)) {
1975                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1976                       "Device is write protected!!!\n");
1977                 instr->state = MTD_ERASE_FAILED;
1978                 goto erase_exit;
1979         }
1980
1981         /*
1982          * If BBT requires refresh, set the BBT page mask to see if the BBT
1983          * should be rewritten. Otherwise the mask is set to 0xffffffff which
1984          * can not be matched. This is also done when the bbt is actually
1985          * erased to avoid recusrsive updates
1986          */
1987         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
1988                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
1989
1990         /* Loop through the pages */
1991         len = instr->len;
1992
1993         instr->state = MTD_ERASING;
1994
1995         while (len) {
1996                 /*
1997                  * heck if we have a bad block, we do not erase bad blocks !
1998                  */
1999                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2000                                         chip->page_shift, 0, allowbbt)) {
2001                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2002                                "bad block at page 0x%08x\n", page);
2003                         instr->state = MTD_ERASE_FAILED;
2004                         goto erase_exit;
2005                 }
2006
2007                 /*
2008                  * Invalidate the page cache, if we erase the block which
2009                  * contains the current cached page
2010                  */
2011                 if (page <= chip->pagebuf && chip->pagebuf <
2012                     (page + pages_per_block))
2013                         chip->pagebuf = -1;
2014
2015                 chip->erase_cmd(mtd, page & chip->pagemask);
2016
2017                 status = chip->waitfunc(mtd, chip);
2018
2019                 /*
2020                  * See if operation failed and additional status checks are
2021                  * available
2022                  */
2023                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2024                         status = chip->errstat(mtd, chip, FL_ERASING,
2025                                                status, page);
2026
2027                 /* See if block erase succeeded */
2028                 if (status & NAND_STATUS_FAIL) {
2029                         DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2030                               "Failed erase, page 0x%08x\n", page);
2031                         instr->state = MTD_ERASE_FAILED;
2032                         instr->fail_addr = (page << chip->page_shift);
2033                         goto erase_exit;
2034                 }
2035
2036                 /*
2037                  * If BBT requires refresh, set the BBT rewrite flag to the
2038                  * page being erased
2039                  */
2040                 if (bbt_masked_page != 0xffffffff &&
2041                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2042                             rewrite_bbt[chipnr] = (page << chip->page_shift);
2043
2044                 /* Increment page address and decrement length */
2045                 len -= (1 << chip->phys_erase_shift);
2046                 page += pages_per_block;
2047
2048                 /* Check, if we cross a chip boundary */
2049                 if (len && !(page & chip->pagemask)) {
2050                         chipnr++;
2051                         chip->select_chip(mtd, -1);
2052                         chip->select_chip(mtd, chipnr);
2053
2054                         /*
2055                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2056                          * page mask to see if this BBT should be rewritten
2057                          */
2058                         if (bbt_masked_page != 0xffffffff &&
2059                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2060                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2061                                         BBT_PAGE_MASK;
2062                 }
2063         }
2064         instr->state = MTD_ERASE_DONE;
2065
2066  erase_exit:
2067
2068         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2069         /* Do call back function */
2070         if (!ret)
2071                 mtd_erase_callback(instr);
2072
2073         /* Deselect and wake up anyone waiting on the device */
2074         nand_release_device(mtd);
2075
2076         /*
2077          * If BBT requires refresh and erase was successful, rewrite any
2078          * selected bad block tables
2079          */
2080         if (bbt_masked_page == 0xffffffff || ret)
2081                 return ret;
2082
2083         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2084                 if (!rewrite_bbt[chipnr])
2085                         continue;
2086                 /* update the BBT for chip */
2087                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2088                       "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2089                       chip->bbt_td->pages[chipnr]);
2090                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2091         }
2092
2093         /* Return more or less happy */
2094         return ret;
2095 }
2096
2097 /**
2098  * nand_sync - [MTD Interface] sync
2099  * @mtd:        MTD device structure
2100  *
2101  * Sync is actually a wait for chip ready function
2102  */
2103 static void nand_sync(struct mtd_info *mtd)
2104 {
2105         struct nand_chip *chip = mtd->priv;
2106
2107         DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2108
2109         /* Grab the lock and see if the device is available */
2110         nand_get_device(chip, mtd, FL_SYNCING);
2111         /* Release it and go back */
2112         nand_release_device(mtd);
2113 }
2114
2115 /**
2116  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2117  * @mtd:        MTD device structure
2118  * @offs:       offset relative to mtd start
2119  */
2120 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2121 {
2122         /* Check for invalid offset */
2123         if (offs > mtd->size)
2124                 return -EINVAL;
2125
2126         return nand_block_checkbad(mtd, offs, 1, 0);
2127 }
2128
2129 /**
2130  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2131  * @mtd:        MTD device structure
2132  * @ofs:        offset relative to mtd start
2133  */
2134 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2135 {
2136         struct nand_chip *chip = mtd->priv;
2137         int ret;
2138
2139         if ((ret = nand_block_isbad(mtd, ofs))) {
2140                 /* If it was bad already, return success and do nothing. */
2141                 if (ret > 0)
2142                         return 0;
2143                 return ret;
2144         }
2145
2146         return chip->block_markbad(mtd, ofs);
2147 }
2148
2149 /**
2150  * nand_suspend - [MTD Interface] Suspend the NAND flash
2151  * @mtd:        MTD device structure
2152  */
2153 static int nand_suspend(struct mtd_info *mtd)
2154 {
2155         struct nand_chip *chip = mtd->priv;
2156
2157         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2158 }
2159
2160 /**
2161  * nand_resume - [MTD Interface] Resume the NAND flash
2162  * @mtd:        MTD device structure
2163  */
2164 static void nand_resume(struct mtd_info *mtd)
2165 {
2166         struct nand_chip *chip = mtd->priv;
2167
2168         if (chip->state == FL_PM_SUSPENDED)
2169                 nand_release_device(mtd);
2170         else
2171                 printk(KERN_ERR "nand_resume() called for a chip which is not "
2172                        "in suspended state\n");
2173 }
2174
2175 /*
2176  * Set default functions
2177  */
2178 static void nand_set_defaults(struct nand_chip *chip, int busw)
2179 {
2180         /* check for proper chip_delay setup, set 20us if not */
2181         if (!chip->chip_delay)
2182                 chip->chip_delay = 20;
2183
2184         /* check, if a user supplied command function given */
2185         if (chip->cmdfunc == NULL)
2186                 chip->cmdfunc = nand_command;
2187
2188         /* check, if a user supplied wait function given */
2189         if (chip->waitfunc == NULL)
2190                 chip->waitfunc = nand_wait;
2191
2192         if (!chip->select_chip)
2193                 chip->select_chip = nand_select_chip;
2194         if (!chip->read_byte)
2195                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2196         if (!chip->read_word)
2197                 chip->read_word = nand_read_word;
2198         if (!chip->block_bad)
2199                 chip->block_bad = nand_block_bad;
2200         if (!chip->block_markbad)
2201                 chip->block_markbad = nand_default_block_markbad;
2202         if (!chip->write_buf)
2203                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2204         if (!chip->read_buf)
2205                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2206         if (!chip->verify_buf)
2207                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2208         if (!chip->scan_bbt)
2209                 chip->scan_bbt = nand_default_bbt;
2210
2211         if (!chip->controller) {
2212                 chip->controller = &chip->hwcontrol;
2213                 spin_lock_init(&chip->controller->lock);
2214                 init_waitqueue_head(&chip->controller->wq);
2215         }
2216
2217 }
2218
2219 /*
2220  * Get the flash and manufacturer id and lookup if the type is supported
2221  */
2222 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2223                                                   struct nand_chip *chip,
2224                                                   int busw, int *maf_id)
2225 {
2226         struct nand_flash_dev *type = NULL;
2227         int i, dev_id, maf_idx;
2228
2229         /* Select the device */
2230         chip->select_chip(mtd, 0);
2231
2232         /* Send the command for reading device ID */
2233         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2234
2235         /* Read manufacturer and device IDs */
2236         *maf_id = chip->read_byte(mtd);
2237         dev_id = chip->read_byte(mtd);
2238
2239         /* Lookup the flash id */
2240         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2241                 if (dev_id == nand_flash_ids[i].id) {
2242                         type =  &nand_flash_ids[i];
2243                         break;
2244                 }
2245         }
2246
2247         if (!type)
2248                 return ERR_PTR(-ENODEV);
2249
2250         if (!mtd->name)
2251                 mtd->name = type->name;
2252
2253         chip->chipsize = type->chipsize << 20;
2254
2255         /* Newer devices have all the information in additional id bytes */
2256         if (!type->pagesize) {
2257                 int extid;
2258                 /* The 3rd id byte holds MLC / multichip data */
2259                 chip->cellinfo = chip->read_byte(mtd);
2260                 /* The 4th id byte is the important one */
2261                 extid = chip->read_byte(mtd);
2262                 /* Calc pagesize */
2263                 mtd->writesize = 1024 << (extid & 0x3);
2264                 extid >>= 2;
2265                 /* Calc oobsize */
2266                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2267                 extid >>= 2;
2268                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2269                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2270                 extid >>= 2;
2271                 /* Get buswidth information */
2272                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2273
2274         } else {
2275                 /*
2276                  * Old devices have chip data hardcoded in the device id table
2277                  */
2278                 mtd->erasesize = type->erasesize;
2279                 mtd->writesize = type->pagesize;
2280                 mtd->oobsize = mtd->writesize / 32;
2281                 busw = type->options & NAND_BUSWIDTH_16;
2282         }
2283
2284         /* Try to identify manufacturer */
2285         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2286                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2287                         break;
2288         }
2289
2290         /*
2291          * Check, if buswidth is correct. Hardware drivers should set
2292          * chip correct !
2293          */
2294         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2295                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2296                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2297                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2298                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2299                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2300                        busw ? 16 : 8);
2301                 return ERR_PTR(-EINVAL);
2302         }
2303
2304         /* Calculate the address shift from the page size */
2305         chip->page_shift = ffs(mtd->writesize) - 1;
2306         /* Convert chipsize to number of pages per chip -1. */
2307         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2308
2309         chip->bbt_erase_shift = chip->phys_erase_shift =
2310                 ffs(mtd->erasesize) - 1;
2311         chip->chip_shift = ffs(chip->chipsize) - 1;
2312
2313         /* Set the bad block position */
2314         chip->badblockpos = mtd->writesize > 512 ?
2315                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2316
2317         /* Get chip options, preserve non chip based options */
2318         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2319         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2320
2321         /*
2322          * Set chip as a default. Board drivers can override it, if necessary
2323          */
2324         chip->options |= NAND_NO_AUTOINCR;
2325
2326         /* Check if chip is a not a samsung device. Do not clear the
2327          * options for chips which are not having an extended id.
2328          */
2329         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2330                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2331
2332         /* Check for AND chips with 4 page planes */
2333         if (chip->options & NAND_4PAGE_ARRAY)
2334                 chip->erase_cmd = multi_erase_cmd;
2335         else
2336                 chip->erase_cmd = single_erase_cmd;
2337
2338         /* Do not replace user supplied command function ! */
2339         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2340                 chip->cmdfunc = nand_command_lp;
2341
2342         printk(KERN_INFO "NAND device: Manufacturer ID:"
2343                " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2344                nand_manuf_ids[maf_idx].name, type->name);
2345
2346         return type;
2347 }
2348
2349 /**
2350  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2351  * @mtd:             MTD device structure
2352  * @maxchips:        Number of chips to scan for
2353  *
2354  * This is the first phase of the normal nand_scan() function. It
2355  * reads the flash ID and sets up MTD fields accordingly.
2356  *
2357  * The mtd->owner field must be set to the module of the caller.
2358  */
2359 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2360 {
2361         int i, busw, nand_maf_id;
2362         struct nand_chip *chip = mtd->priv;
2363         struct nand_flash_dev *type;
2364
2365         /* Get buswidth to select the correct functions */
2366         busw = chip->options & NAND_BUSWIDTH_16;
2367         /* Set the default functions */
2368         nand_set_defaults(chip, busw);
2369
2370         /* Read the flash type */
2371         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2372
2373         if (IS_ERR(type)) {
2374                 printk(KERN_WARNING "No NAND device found!!!\n");
2375                 chip->select_chip(mtd, -1);
2376                 return PTR_ERR(type);
2377         }
2378
2379         /* Check for a chip array */
2380         for (i = 1; i < maxchips; i++) {
2381                 chip->select_chip(mtd, i);
2382                 /* Send the command for reading device ID */
2383                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2384                 /* Read manufacturer and device IDs */
2385                 if (nand_maf_id != chip->read_byte(mtd) ||
2386                     type->id != chip->read_byte(mtd))
2387                         break;
2388         }
2389         if (i > 1)
2390                 printk(KERN_INFO "%d NAND chips detected\n", i);
2391
2392         /* Store the number of chips and calc total size for mtd */
2393         chip->numchips = i;
2394         mtd->size = i * chip->chipsize;
2395
2396         return 0;
2397 }
2398
2399
2400 /**
2401  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2402  * @mtd:            MTD device structure
2403  * @maxchips:       Number of chips to scan for
2404  *
2405  * This is the second phase of the normal nand_scan() function. It
2406  * fills out all the uninitialized function pointers with the defaults
2407  * and scans for a bad block table if appropriate.
2408  */
2409 int nand_scan_tail(struct mtd_info *mtd)
2410 {
2411         int i;
2412         struct nand_chip *chip = mtd->priv;
2413
2414         if (!(chip->options & NAND_OWN_BUFFERS))
2415                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2416         if (!chip->buffers)
2417                 return -ENOMEM;
2418
2419         /* Set the internal oob buffer location, just after the page data */
2420         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2421
2422         /*
2423          * If no default placement scheme is given, select an appropriate one
2424          */
2425         if (!chip->ecc.layout) {
2426                 switch (mtd->oobsize) {
2427                 case 8:
2428                         chip->ecc.layout = &nand_oob_8;
2429                         break;
2430                 case 16:
2431                         chip->ecc.layout = &nand_oob_16;
2432                         break;
2433                 case 64:
2434                         chip->ecc.layout = &nand_oob_64;
2435                         break;
2436                 default:
2437                         printk(KERN_WARNING "No oob scheme defined for "
2438                                "oobsize %d\n", mtd->oobsize);
2439                         BUG();
2440                 }
2441         }
2442
2443         if (!chip->write_page)
2444                 chip->write_page = nand_write_page;
2445
2446         /*
2447          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2448          * selected and we have 256 byte pagesize fallback to software ECC
2449          */
2450         if (!chip->ecc.read_page_raw)
2451                 chip->ecc.read_page_raw = nand_read_page_raw;
2452         if (!chip->ecc.write_page_raw)
2453                 chip->ecc.write_page_raw = nand_write_page_raw;
2454
2455         switch (chip->ecc.mode) {
2456         case NAND_ECC_HW:
2457                 /* Use standard hwecc read page function ? */
2458                 if (!chip->ecc.read_page)
2459                         chip->ecc.read_page = nand_read_page_hwecc;
2460                 if (!chip->ecc.write_page)
2461                         chip->ecc.write_page = nand_write_page_hwecc;
2462                 if (!chip->ecc.read_oob)
2463                         chip->ecc.read_oob = nand_read_oob_std;
2464                 if (!chip->ecc.write_oob)
2465                         chip->ecc.write_oob = nand_write_oob_std;
2466
2467         case NAND_ECC_HW_SYNDROME:
2468                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2469                     !chip->ecc.hwctl) {
2470                         printk(KERN_WARNING "No ECC functions supplied, "
2471                                "Hardware ECC not possible\n");
2472                         BUG();
2473                 }
2474                 /* Use standard syndrome read/write page function ? */
2475                 if (!chip->ecc.read_page)
2476                         chip->ecc.read_page = nand_read_page_syndrome;
2477                 if (!chip->ecc.write_page)
2478                         chip->ecc.write_page = nand_write_page_syndrome;
2479                 if (!chip->ecc.read_oob)
2480                         chip->ecc.read_oob = nand_read_oob_syndrome;
2481                 if (!chip->ecc.write_oob)
2482                         chip->ecc.write_oob = nand_write_oob_syndrome;
2483
2484                 if (mtd->writesize >= chip->ecc.size)
2485                         break;
2486                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2487                        "%d byte page size, fallback to SW ECC\n",
2488                        chip->ecc.size, mtd->writesize);
2489                 chip->ecc.mode = NAND_ECC_SOFT;
2490
2491         case NAND_ECC_SOFT:
2492                 chip->ecc.calculate = nand_calculate_ecc;
2493                 chip->ecc.correct = nand_correct_data;
2494                 chip->ecc.read_page = nand_read_page_swecc;
2495                 chip->ecc.write_page = nand_write_page_swecc;
2496                 chip->ecc.read_oob = nand_read_oob_std;
2497                 chip->ecc.write_oob = nand_write_oob_std;
2498                 chip->ecc.size = 256;
2499                 chip->ecc.bytes = 3;
2500                 break;
2501
2502         case NAND_ECC_NONE:
2503                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2504                        "This is not recommended !!\n");
2505                 chip->ecc.read_page = nand_read_page_raw;
2506                 chip->ecc.write_page = nand_write_page_raw;
2507                 chip->ecc.read_oob = nand_read_oob_std;
2508                 chip->ecc.write_oob = nand_write_oob_std;
2509                 chip->ecc.size = mtd->writesize;
2510                 chip->ecc.bytes = 0;
2511                 break;
2512
2513         default:
2514                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2515                        chip->ecc.mode);
2516                 BUG();
2517         }
2518
2519         /*
2520          * The number of bytes available for a client to place data into
2521          * the out of band area
2522          */
2523         chip->ecc.layout->oobavail = 0;
2524         for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2525                 chip->ecc.layout->oobavail +=
2526                         chip->ecc.layout->oobfree[i].length;
2527
2528         /*
2529          * Set the number of read / write steps for one page depending on ECC
2530          * mode
2531          */
2532         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2533         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2534                 printk(KERN_WARNING "Invalid ecc parameters\n");
2535                 BUG();
2536         }
2537         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2538
2539         /*
2540          * Allow subpage writes up to ecc.steps. Not possible for MLC
2541          * FLASH.
2542          */
2543         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2544             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2545                 switch(chip->ecc.steps) {
2546                 case 2:
2547                         mtd->subpage_sft = 1;
2548                         break;
2549                 case 4:
2550                 case 8:
2551                         mtd->subpage_sft = 2;
2552                         break;
2553                 }
2554         }
2555         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2556
2557         /* Initialize state */
2558         chip->state = FL_READY;
2559
2560         /* De-select the device */
2561         chip->select_chip(mtd, -1);
2562
2563         /* Invalidate the pagebuffer reference */
2564         chip->pagebuf = -1;
2565
2566         /* Fill in remaining MTD driver data */
2567         mtd->type = MTD_NANDFLASH;
2568         mtd->flags = MTD_CAP_NANDFLASH;
2569         mtd->erase = nand_erase;
2570         mtd->point = NULL;
2571         mtd->unpoint = NULL;
2572         mtd->read = nand_read;
2573         mtd->write = nand_write;
2574         mtd->read_oob = nand_read_oob;
2575         mtd->write_oob = nand_write_oob;
2576         mtd->sync = nand_sync;
2577         mtd->lock = NULL;
2578         mtd->unlock = NULL;
2579         mtd->suspend = nand_suspend;
2580         mtd->resume = nand_resume;
2581         mtd->block_isbad = nand_block_isbad;
2582         mtd->block_markbad = nand_block_markbad;
2583
2584         /* propagate ecc.layout to mtd_info */
2585         mtd->ecclayout = chip->ecc.layout;
2586
2587         /* Check, if we should skip the bad block table scan */
2588         if (chip->options & NAND_SKIP_BBTSCAN)
2589                 return 0;
2590
2591         /* Build bad block table */
2592         return chip->scan_bbt(mtd);
2593 }
2594
2595 /* module_text_address() isn't exported, and it's mostly a pointless
2596    test if this is a module _anyway_ -- they'd have to try _really_ hard
2597    to call us from in-kernel code if the core NAND support is modular. */
2598 #ifdef MODULE
2599 #define caller_is_module() (1)
2600 #else
2601 #define caller_is_module() \
2602         module_text_address((unsigned long)__builtin_return_address(0))
2603 #endif
2604
2605 /**
2606  * nand_scan - [NAND Interface] Scan for the NAND device
2607  * @mtd:        MTD device structure
2608  * @maxchips:   Number of chips to scan for
2609  *
2610  * This fills out all the uninitialized function pointers
2611  * with the defaults.
2612  * The flash ID is read and the mtd/chip structures are
2613  * filled with the appropriate values.
2614  * The mtd->owner field must be set to the module of the caller
2615  *
2616  */
2617 int nand_scan(struct mtd_info *mtd, int maxchips)
2618 {
2619         int ret;
2620
2621         /* Many callers got this wrong, so check for it for a while... */
2622         if (!mtd->owner && caller_is_module()) {
2623                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2624                 BUG();
2625         }
2626
2627         ret = nand_scan_ident(mtd, maxchips);
2628         if (!ret)
2629                 ret = nand_scan_tail(mtd);
2630         return ret;
2631 }
2632
2633 /**
2634  * nand_release - [NAND Interface] Free resources held by the NAND device
2635  * @mtd:        MTD device structure
2636 */
2637 void nand_release(struct mtd_info *mtd)
2638 {
2639         struct nand_chip *chip = mtd->priv;
2640
2641 #ifdef CONFIG_MTD_PARTITIONS
2642         /* Deregister partitions */
2643         del_mtd_partitions(mtd);
2644 #endif
2645         /* Deregister the device */
2646         del_mtd_device(mtd);
2647
2648         /* Free bad block table memory */
2649         kfree(chip->bbt);
2650         if (!(chip->options & NAND_OWN_BUFFERS))
2651                 kfree(chip->buffers);
2652 }
2653
2654 EXPORT_SYMBOL_GPL(nand_scan);
2655 EXPORT_SYMBOL_GPL(nand_scan_ident);
2656 EXPORT_SYMBOL_GPL(nand_scan_tail);
2657 EXPORT_SYMBOL_GPL(nand_release);
2658
2659 static int __init nand_base_init(void)
2660 {
2661         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2662         return 0;
2663 }
2664
2665 static void __exit nand_base_exit(void)
2666 {
2667         led_trigger_unregister_simple(nand_led_trigger);
2668 }
2669
2670 module_init(nand_base_init);
2671 module_exit(nand_base_exit);
2672
2673 MODULE_LICENSE("GPL");
2674 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2675 MODULE_DESCRIPTION("Generic NAND flash driver code");