drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/compatmac.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <asm/io.h>
  50
  51 #ifdef CONFIG_MTD_PARTITIONS
  52 #include <linux/mtd/partitions.h>
  53 #endif
  54
  55 /* Define default oob placement schemes for large and small page devices */
  56 static struct nand_ecclayout nand_oob_8 = {
  57         .eccbytes = 3,
  58         .eccpos = {0, 1, 2},
  59         .oobfree = {
  60                 {.offset = 3,
  61                  .length = 2},
  62                 {.offset = 6,
  63                  .length = 2}}
  64 };
  65
  66 static struct nand_ecclayout nand_oob_16 = {
  67         .eccbytes = 6,
  68         .eccpos = {0, 1, 2, 3, 6, 7},
  69         .oobfree = {
  70                 {.offset = 8,
  71                  . length = 8}}
  72 };
  73
  74 static struct nand_ecclayout nand_oob_64 = {
  75         .eccbytes = 24,
  76         .eccpos = {
  77                    40, 41, 42, 43, 44, 45, 46, 47,
  78                    48, 49, 50, 51, 52, 53, 54, 55,
  79                    56, 57, 58, 59, 60, 61, 62, 63},
  80         .oobfree = {
  81                 {.offset = 2,
  82                  .length = 38}}
  83 };
  84
  85 static struct nand_ecclayout nand_oob_128 = {
  86         .eccbytes = 48,
  87         .eccpos = {
  88                    80, 81, 82, 83, 84, 85, 86, 87,
  89                    88, 89, 90, 91, 92, 93, 94, 95,
  90                    96, 97, 98, 99, 100, 101, 102, 103,
  91                    104, 105, 106, 107, 108, 109, 110, 111,
  92                    112, 113, 114, 115, 116, 117, 118, 119,
  93                    120, 121, 122, 123, 124, 125, 126, 127},
  94         .oobfree = {
  95                 {.offset = 2,
  96                  .length = 78}}
  97 };
  98
  99 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 100                            int new_state);
 101
 102 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 103                              struct mtd_oob_ops *ops);
 104
 105 /*
 106  * For devices which display every fart in the system on a separate LED. Is
 107  * compiled away when LED support is disabled.
 108  */
 109 DEFINE_LED_TRIGGER(nand_led_trigger);
 110
 111 /**
 112  * nand_release_device - [GENERIC] release chip
 113  * @mtd:        MTD device structure
 114  *
 115  * Deselect, release chip lock and wake up anyone waiting on the device
 116  */
 117 static void nand_release_device(struct mtd_info *mtd)
 118 {
 119         struct nand_chip *chip = mtd->priv;
 120
 121         /* De-select the NAND device */
 122         chip->select_chip(mtd, -1);
 123
 124         /* Release the controller and the chip */
 125         spin_lock(&chip->controller->lock);
 126         chip->controller->active = NULL;
 127         chip->state = FL_READY;
 128         wake_up(&chip->controller->wq);
 129         spin_unlock(&chip->controller->lock);
 130 }
 131
 132 /**
 133  * nand_read_byte - [DEFAULT] read one byte from the chip
 134  * @mtd:        MTD device structure
 135  *
 136  * Default read function for 8bit buswith
 137  */
 138 static uint8_t nand_read_byte(struct mtd_info *mtd)
 139 {
 140         struct nand_chip *chip = mtd->priv;
 141         return readb(chip->IO_ADDR_R);
 142 }
 143
 144 /**
 145  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 146  * @mtd:        MTD device structure
 147  *
 148  * Default read function for 16bit buswith with
 149  * endianess conversion
 150  */
 151 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 152 {
 153         struct nand_chip *chip = mtd->priv;
 154         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 155 }
 156
 157 /**
 158  * nand_read_word - [DEFAULT] read one word from the chip
 159  * @mtd:        MTD device structure
 160  *
 161  * Default read function for 16bit buswith without
 162  * endianess conversion
 163  */
 164 static u16 nand_read_word(struct mtd_info *mtd)
 165 {
 166         struct nand_chip *chip = mtd->priv;
 167         return readw(chip->IO_ADDR_R);
 168 }
 169
 170 /**
 171  * nand_select_chip - [DEFAULT] control CE line
 172  * @mtd:        MTD device structure
 173  * @chipnr:     chipnumber to select, -1 for deselect
 174  *
 175  * Default select function for 1 chip devices.
 176  */
 177 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 178 {
 179         struct nand_chip *chip = mtd->priv;
 180
 181         switch (chipnr) {
 182         case -1:
 183                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 184                 break;
 185         case 0:
 186                 break;
 187
 188         default:
 189                 BUG();
 190         }
 191 }
 192
 193 /**
 194  * nand_write_buf - [DEFAULT] write buffer to chip
 195  * @mtd:        MTD device structure
 196  * @buf:        data buffer
 197  * @len:        number of bytes to write
 198  *
 199  * Default write function for 8bit buswith
 200  */
 201 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 202 {
 203         int i;
 204         struct nand_chip *chip = mtd->priv;
 205
 206         for (i = 0; i < len; i++)
 207                 writeb(buf[i], chip->IO_ADDR_W);
 208 }
 209
 210 /**
 211  * nand_read_buf - [DEFAULT] read chip data into buffer
 212  * @mtd:        MTD device structure
 213  * @buf:        buffer to store date
 214  * @len:        number of bytes to read
 215  *
 216  * Default read function for 8bit buswith
 217  */
 218 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 219 {
 220         int i;
 221         struct nand_chip *chip = mtd->priv;
 222
 223         for (i = 0; i < len; i++)
 224                 buf[i] = readb(chip->IO_ADDR_R);
 225 }
 226
 227 /**
 228  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 229  * @mtd:        MTD device structure
 230  * @buf:        buffer containing the data to compare
 231  * @len:        number of bytes to compare
 232  *
 233  * Default verify function for 8bit buswith
 234  */
 235 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 236 {
 237         int i;
 238         struct nand_chip *chip = mtd->priv;
 239
 240         for (i = 0; i < len; i++)
 241                 if (buf[i] != readb(chip->IO_ADDR_R))
 242                         return -EFAULT;
 243         return 0;
 244 }
 245
 246 /**
 247  * nand_write_buf16 - [DEFAULT] write buffer to chip
 248  * @mtd:        MTD device structure
 249  * @buf:        data buffer
 250  * @len:        number of bytes to write
 251  *
 252  * Default write function for 16bit buswith
 253  */
 254 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 255 {
 256         int i;
 257         struct nand_chip *chip = mtd->priv;
 258         u16 *p = (u16 *) buf;
 259         len >>= 1;
 260
 261         for (i = 0; i < len; i++)
 262                 writew(p[i], chip->IO_ADDR_W);
 263
 264 }
 265
 266 /**
 267  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 268  * @mtd:        MTD device structure
 269  * @buf:        buffer to store date
 270  * @len:        number of bytes to read
 271  *
 272  * Default read function for 16bit buswith
 273  */
 274 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 275 {
 276         int i;
 277         struct nand_chip *chip = mtd->priv;
 278         u16 *p = (u16 *) buf;
 279         len >>= 1;
 280
 281         for (i = 0; i < len; i++)
 282                 p[i] = readw(chip->IO_ADDR_R);
 283 }
 284
 285 /**
 286  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 287  * @mtd:        MTD device structure
 288  * @buf:        buffer containing the data to compare
 289  * @len:        number of bytes to compare
 290  *
 291  * Default verify function for 16bit buswith
 292  */
 293 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 294 {
 295         int i;
 296         struct nand_chip *chip = mtd->priv;
 297         u16 *p = (u16 *) buf;
 298         len >>= 1;
 299
 300         for (i = 0; i < len; i++)
 301                 if (p[i] != readw(chip->IO_ADDR_R))
 302                         return -EFAULT;
 303
 304         return 0;
 305 }
 306
 307 /**
 308  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 309  * @mtd:        MTD device structure
 310  * @ofs:        offset from device start
 311  * @getchip:    0, if the chip is already selected
 312  *
 313  * Check, if the block is bad.
 314  */
 315 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 316 {
 317         int page, chipnr, res = 0;
 318         struct nand_chip *chip = mtd->priv;
 319         u16 bad;
 320
 321         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 322
 323         if (getchip) {
 324                 chipnr = (int)(ofs >> chip->chip_shift);
 325
 326                 nand_get_device(chip, mtd, FL_READING);
 327
 328                 /* Select the NAND device */
 329                 chip->select_chip(mtd, chipnr);
 330         }
 331
 332         if (chip->options & NAND_BUSWIDTH_16) {
 333                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 334                               page);
 335                 bad = cpu_to_le16(chip->read_word(mtd));
 336                 if (chip->badblockpos & 0x1)
 337                         bad >>= 8;
 338                 if ((bad & 0xFF) != 0xff)
 339                         res = 1;
 340         } else {
 341                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 342                 if (chip->read_byte(mtd) != 0xff)
 343                         res = 1;
 344         }
 345
 346         if (getchip)
 347                 nand_release_device(mtd);
 348
 349         return res;
 350 }
 351
 352 /**
 353  * nand_default_block_markbad - [DEFAULT] mark a block bad
 354  * @mtd:        MTD device structure
 355  * @ofs:        offset from device start
 356  *
 357  * This is the default implementation, which can be overridden by
 358  * a hardware specific driver.
 359 */
 360 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 361 {
 362         struct nand_chip *chip = mtd->priv;
 363         uint8_t buf[2] = { 0, 0 };
 364         int block, ret;
 365
 366         /* Get block number */
 367         block = (int)(ofs >> chip->bbt_erase_shift);
 368         if (chip->bbt)
 369                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 370
 371         /* Do we have a flash based bad block table ? */
 372         if (chip->options & NAND_USE_FLASH_BBT)
 373                 ret = nand_update_bbt(mtd, ofs);
 374         else {
 375                 /* We write two bytes, so we dont have to mess with 16 bit
 376                  * access
 377                  */
 378                 nand_get_device(chip, mtd, FL_WRITING);
 379                 ofs += mtd->oobsize;
 380                 chip->ops.len = chip->ops.ooblen = 2;
 381                 chip->ops.datbuf = NULL;
 382                 chip->ops.oobbuf = buf;
 383                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 384
 385                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 386                 nand_release_device(mtd);
 387         }
 388         if (!ret)
 389                 mtd->ecc_stats.badblocks++;
 390
 391         return ret;
 392 }
 393
 394 /**
 395  * nand_check_wp - [GENERIC] check if the chip is write protected
 396  * @mtd:        MTD device structure
 397  * Check, if the device is write protected
 398  *
 399  * The function expects, that the device is already selected
 400  */
 401 static int nand_check_wp(struct mtd_info *mtd)
 402 {
 403         struct nand_chip *chip = mtd->priv;
 404         /* Check the WP bit */
 405         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 406         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 407 }
 408
 409 /**
 410  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 411  * @mtd:        MTD device structure
 412  * @ofs:        offset from device start
 413  * @getchip:    0, if the chip is already selected
 414  * @allowbbt:   1, if its allowed to access the bbt area
 415  *
 416  * Check, if the block is bad. Either by reading the bad block table or
 417  * calling of the scan function.
 418  */
 419 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 420                                int allowbbt)
 421 {
 422         struct nand_chip *chip = mtd->priv;
 423
 424         if (!chip->bbt)
 425                 return chip->block_bad(mtd, ofs, getchip);
 426
 427         /* Return info from the table */
 428         return nand_isbad_bbt(mtd, ofs, allowbbt);
 429 }
 430
 431 /*
 432  * Wait for the ready pin, after a command
 433  * The timeout is catched later.
 434  */
 435 void nand_wait_ready(struct mtd_info *mtd)
 436 {
 437         struct nand_chip *chip = mtd->priv;
 438         unsigned long timeo = jiffies + 2;
 439
 440         led_trigger_event(nand_led_trigger, LED_FULL);
 441         /* wait until command is processed or timeout occures */
 442         do {
 443                 if (chip->dev_ready(mtd))
 444                         break;
 445                 touch_softlockup_watchdog();
 446         } while (time_before(jiffies, timeo));
 447         led_trigger_event(nand_led_trigger, LED_OFF);
 448 }
 449 EXPORT_SYMBOL_GPL(nand_wait_ready);
 450
 451 /**
 452  * nand_command - [DEFAULT] Send command to NAND device
 453  * @mtd:        MTD device structure
 454  * @command:    the command to be sent
 455  * @column:     the column address for this command, -1 if none
 456  * @page_addr:  the page address for this command, -1 if none
 457  *
 458  * Send command to NAND device. This function is used for small page
 459  * devices (256/512 Bytes per page)
 460  */
 461 static void nand_command(struct mtd_info *mtd, unsigned int command,
 462                          int column, int page_addr)
 463 {
 464         register struct nand_chip *chip = mtd->priv;
 465         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 466
 467         /*
 468          * Write out the command to the device.
 469          */
 470         if (command == NAND_CMD_SEQIN) {
 471                 int readcmd;
 472
 473                 if (column >= mtd->writesize) {
 474                         /* OOB area */
 475                         column -= mtd->writesize;
 476                         readcmd = NAND_CMD_READOOB;
 477                 } else if (column < 256) {
 478                         /* First 256 bytes --> READ0 */
 479                         readcmd = NAND_CMD_READ0;
 480                 } else {
 481                         column -= 256;
 482                         readcmd = NAND_CMD_READ1;
 483                 }
 484                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 485                 ctrl &= ~NAND_CTRL_CHANGE;
 486         }
 487         chip->cmd_ctrl(mtd, command, ctrl);
 488
 489         /*
 490          * Address cycle, when necessary
 491          */
 492         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 493         /* Serially input address */
 494         if (column != -1) {
 495                 /* Adjust columns for 16 bit buswidth */
 496                 if (chip->options & NAND_BUSWIDTH_16)
 497                         column >>= 1;
 498                 chip->cmd_ctrl(mtd, column, ctrl);
 499                 ctrl &= ~NAND_CTRL_CHANGE;
 500         }
 501         if (page_addr != -1) {
 502                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 503                 ctrl &= ~NAND_CTRL_CHANGE;
 504                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 505                 /* One more address cycle for devices > 32MiB */
 506                 if (chip->chipsize > (32 << 20))
 507                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 508         }
 509         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 510
 511         /*
 512          * program and erase have their own busy handlers
 513          * status and sequential in needs no delay
 514          */
 515         switch (command) {
 516
 517         case NAND_CMD_PAGEPROG:
 518         case NAND_CMD_ERASE1:
 519         case NAND_CMD_ERASE2:
 520         case NAND_CMD_SEQIN:
 521         case NAND_CMD_STATUS:
 522                 return;
 523
 524         case NAND_CMD_RESET:
 525                 if (chip->dev_ready)
 526                         break;
 527                 udelay(chip->chip_delay);
 528                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 529                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 530                 chip->cmd_ctrl(mtd,
 531                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 532                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 533                 return;
 534
 535                 /* This applies to read commands */
 536         default:
 537                 /*
 538                  * If we don't have access to the busy pin, we apply the given
 539                  * command delay
 540                  */
 541                 if (!chip->dev_ready) {
 542                         udelay(chip->chip_delay);
 543                         return;
 544                 }
 545         }
 546         /* Apply this short delay always to ensure that we do wait tWB in
 547          * any case on any machine. */
 548         ndelay(100);
 549
 550         nand_wait_ready(mtd);
 551 }
 552
 553 /**
 554  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 555  * @mtd:        MTD device structure
 556  * @command:    the command to be sent
 557  * @column:     the column address for this command, -1 if none
 558  * @page_addr:  the page address for this command, -1 if none
 559  *
 560  * Send command to NAND device. This is the version for the new large page
 561  * devices We dont have the separate regions as we have in the small page
 562  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 563  */
 564 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 565                             int column, int page_addr)
 566 {
 567         register struct nand_chip *chip = mtd->priv;
 568
 569         /* Emulate NAND_CMD_READOOB */
 570         if (command == NAND_CMD_READOOB) {
 571                 column += mtd->writesize;
 572                 command = NAND_CMD_READ0;
 573         }
 574
 575         /* Command latch cycle */
 576         chip->cmd_ctrl(mtd, command & 0xff,
 577                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 578
 579         if (column != -1 || page_addr != -1) {
 580                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 581
 582                 /* Serially input address */
 583                 if (column != -1) {
 584                         /* Adjust columns for 16 bit buswidth */
 585                         if (chip->options & NAND_BUSWIDTH_16)
 586                                 column >>= 1;
 587                         chip->cmd_ctrl(mtd, column, ctrl);
 588                         ctrl &= ~NAND_CTRL_CHANGE;
 589                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 590                 }
 591                 if (page_addr != -1) {
 592                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 593                         chip->cmd_ctrl(mtd, page_addr >> 8,
 594                                        NAND_NCE | NAND_ALE);
 595                         /* One more address cycle for devices > 128MiB */
 596                         if (chip->chipsize > (128 << 20))
 597                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 598                                                NAND_NCE | NAND_ALE);
 599                 }
 600         }
 601         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 602
 603         /*
 604          * program and erase have their own busy handlers
 605          * status, sequential in, and deplete1 need no delay
 606          */
 607         switch (command) {
 608
 609         case NAND_CMD_CACHEDPROG:
 610         case NAND_CMD_PAGEPROG:
 611         case NAND_CMD_ERASE1:
 612         case NAND_CMD_ERASE2:
 613         case NAND_CMD_SEQIN:
 614         case NAND_CMD_RNDIN:
 615         case NAND_CMD_STATUS:
 616         case NAND_CMD_DEPLETE1:
 617                 return;
 618
 619                 /*
 620                  * read error status commands require only a short delay
 621                  */
 622         case NAND_CMD_STATUS_ERROR:
 623         case NAND_CMD_STATUS_ERROR0:
 624         case NAND_CMD_STATUS_ERROR1:
 625         case NAND_CMD_STATUS_ERROR2:
 626         case NAND_CMD_STATUS_ERROR3:
 627                 udelay(chip->chip_delay);
 628                 return;
 629
 630         case NAND_CMD_RESET:
 631                 if (chip->dev_ready)
 632                         break;
 633                 udelay(chip->chip_delay);
 634                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 635                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 636                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 637                                NAND_NCE | NAND_CTRL_CHANGE);
 638                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 639                 return;
 640
 641         case NAND_CMD_RNDOUT:
 642                 /* No ready / busy check necessary */
 643                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 644                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 645                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 646                                NAND_NCE | NAND_CTRL_CHANGE);
 647                 return;
 648
 649         case NAND_CMD_READ0:
 650                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 651                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 652                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 653                                NAND_NCE | NAND_CTRL_CHANGE);
 654
 655                 /* This applies to read commands */
 656         default:
 657                 /*
 658                  * If we don't have access to the busy pin, we apply the given
 659                  * command delay
 660                  */
 661                 if (!chip->dev_ready) {
 662                         udelay(chip->chip_delay);
 663                         return;
 664                 }
 665         }
 666
 667         /* Apply this short delay always to ensure that we do wait tWB in
 668          * any case on any machine. */
 669         ndelay(100);
 670
 671         nand_wait_ready(mtd);
 672 }
 673
 674 /**
 675  * nand_get_device - [GENERIC] Get chip for selected access
 676  * @chip:       the nand chip descriptor
 677  * @mtd:        MTD device structure
 678  * @new_state:  the state which is requested
 679  *
 680  * Get the device and lock it for exclusive access
 681  */
 682 static int
 683 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 684 {
 685         spinlock_t *lock = &chip->controller->lock;
 686         wait_queue_head_t *wq = &chip->controller->wq;
 687         DECLARE_WAITQUEUE(wait, current);
 688  retry:
 689         spin_lock(lock);
 690
 691         /* Hardware controller shared among independend devices */
 692         /* Hardware controller shared among independend devices */
 693         if (!chip->controller->active)
 694                 chip->controller->active = chip;
 695
 696         if (chip->controller->active == chip && chip->state == FL_READY) {
 697                 chip->state = new_state;
 698                 spin_unlock(lock);
 699                 return 0;
 700         }
 701         if (new_state == FL_PM_SUSPENDED) {
 702                 spin_unlock(lock);
 703                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 704         }
 705         set_current_state(TASK_UNINTERRUPTIBLE);
 706         add_wait_queue(wq, &wait);
 707         spin_unlock(lock);
 708         schedule();
 709         remove_wait_queue(wq, &wait);
 710         goto retry;
 711 }
 712
 713 /**
 714  * nand_wait - [DEFAULT]  wait until the command is done
 715  * @mtd:        MTD device structure
 716  * @chip:       NAND chip structure
 717  *
 718  * Wait for command done. This applies to erase and program only
 719  * Erase can take up to 400ms and program up to 20ms according to
 720  * general NAND and SmartMedia specs
 721  */
 722 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 723 {
 724
 725         unsigned long timeo = jiffies;
 726         int status, state = chip->state;
 727
 728         if (state == FL_ERASING)
 729                 timeo += (HZ * 400) / 1000;
 730         else
 731                 timeo += (HZ * 20) / 1000;
 732
 733         led_trigger_event(nand_led_trigger, LED_FULL);
 734
 735         /* Apply this short delay always to ensure that we do wait tWB in
 736          * any case on any machine. */
 737         ndelay(100);
 738
 739         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 740                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 741         else
 742                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 743
 744         while (time_before(jiffies, timeo)) {
 745                 if (chip->dev_ready) {
 746                         if (chip->dev_ready(mtd))
 747                                 break;
 748                 } else {
 749                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 750                                 break;
 751                 }
 752                 cond_resched();
 753         }
 754         led_trigger_event(nand_led_trigger, LED_OFF);
 755
 756         status = (int)chip->read_byte(mtd);
 757         return status;
 758 }
 759
 760 /**
 761  * nand_read_page_raw - [Intern] read raw page data without ecc
 762  * @mtd:        mtd info structure
 763  * @chip:       nand chip info structure
 764  * @buf:        buffer to store read data
 765  *
 766  * Not for syndrome calculating ecc controllers, which use a special oob layout
 767  */
 768 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 769                               uint8_t *buf)
 770 {
 771         chip->read_buf(mtd, buf, mtd->writesize);
 772         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 773         return 0;
 774 }
 775
 776 /**
 777  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
 778  * @mtd:        mtd info structure
 779  * @chip:       nand chip info structure
 780  * @buf:        buffer to store read data
 781  *
 782  * We need a special oob layout and handling even when OOB isn't used.
 783  */
 784 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 785                               uint8_t *buf)
 786 {
 787         int eccsize = chip->ecc.size;
 788         int eccbytes = chip->ecc.bytes;
 789         uint8_t *oob = chip->oob_poi;
 790         int steps, size;
 791
 792         for (steps = chip->ecc.steps; steps > 0; steps--) {
 793                 chip->read_buf(mtd, buf, eccsize);
 794                 buf += eccsize;
 795
 796                 if (chip->ecc.prepad) {
 797                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 798                         oob += chip->ecc.prepad;
 799                 }
 800
 801                 chip->read_buf(mtd, oob, eccbytes);
 802                 oob += eccbytes;
 803
 804                 if (chip->ecc.postpad) {
 805                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 806                         oob += chip->ecc.postpad;
 807                 }
 808         }
 809
 810         size = mtd->oobsize - (oob - chip->oob_poi);
 811         if (size)
 812                 chip->read_buf(mtd, oob, size);
 813
 814         return 0;
 815 }
 816
 817 /**
 818  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 819  * @mtd:        mtd info structure
 820  * @chip:       nand chip info structure
 821  * @buf:        buffer to store read data
 822  */
 823 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 824                                 uint8_t *buf)
 825 {
 826         int i, eccsize = chip->ecc.size;
 827         int eccbytes = chip->ecc.bytes;
 828         int eccsteps = chip->ecc.steps;
 829         uint8_t *p = buf;
 830         uint8_t *ecc_calc = chip->buffers->ecccalc;
 831         uint8_t *ecc_code = chip->buffers->ecccode;
 832         uint32_t *eccpos = chip->ecc.layout->eccpos;
 833
 834         chip->ecc.read_page_raw(mtd, chip, buf);
 835
 836         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 837                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 838
 839         for (i = 0; i < chip->ecc.total; i++)
 840                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 841
 842         eccsteps = chip->ecc.steps;
 843         p = buf;
 844
 845         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 846                 int stat;
 847
 848                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 849                 if (stat < 0)
 850                         mtd->ecc_stats.failed++;
 851                 else
 852                         mtd->ecc_stats.corrected += stat;
 853         }
 854         return 0;
 855 }
 856
 857 /**
 858  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
 859  * @mtd:        mtd info structure
 860  * @chip:       nand chip info structure
 861  * @data_offs:  offset of requested data within the page
 862  * @readlen:    data length
 863  * @bufpoi:     buffer to store read data
 864  */
 865 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 866 {
 867         int start_step, end_step, num_steps;
 868         uint32_t *eccpos = chip->ecc.layout->eccpos;
 869         uint8_t *p;
 870         int data_col_addr, i, gaps = 0;
 871         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 872         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 873
 874         /* Column address wihin the page aligned to ECC size (256bytes). */
 875         start_step = data_offs / chip->ecc.size;
 876         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 877         num_steps = end_step - start_step + 1;
 878
 879         /* Data size aligned to ECC ecc.size*/
 880         datafrag_len = num_steps * chip->ecc.size;
 881         eccfrag_len = num_steps * chip->ecc.bytes;
 882
 883         data_col_addr = start_step * chip->ecc.size;
 884         /* If we read not a page aligned data */
 885         if (data_col_addr != 0)
 886                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 887
 888         p = bufpoi + data_col_addr;
 889         chip->read_buf(mtd, p, datafrag_len);
 890
 891         /* Calculate  ECC */
 892         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 893                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 894
 895         /* The performance is faster if to position offsets
 896            according to ecc.pos. Let make sure here that
 897            there are no gaps in ecc positions */
 898         for (i = 0; i < eccfrag_len - 1; i++) {
 899                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 900                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
 901                         gaps = 1;
 902                         break;
 903                 }
 904         }
 905         if (gaps) {
 906                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 907                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 908         } else {
 909                 /* send the command to read the particular ecc bytes */
 910                 /* take care about buswidth alignment in read_buf */
 911                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
 912                 aligned_len = eccfrag_len;
 913                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
 914                         aligned_len++;
 915                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
 916                         aligned_len++;
 917
 918                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
 919                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
 920         }
 921
 922         for (i = 0; i < eccfrag_len; i++)
 923                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
 924
 925         p = bufpoi + data_col_addr;
 926         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
 927                 int stat;
 928
 929                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
 930                 if (stat == -1)
 931                         mtd->ecc_stats.failed++;
 932                 else
 933                         mtd->ecc_stats.corrected += stat;
 934         }
 935         return 0;
 936 }
 937
 938 /**
 939  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
 940  * @mtd:        mtd info structure
 941  * @chip:       nand chip info structure
 942  * @buf:        buffer to store read data
 943  *
 944  * Not for syndrome calculating ecc controllers which need a special oob layout
 945  */
 946 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 947                                 uint8_t *buf)
 948 {
 949         int i, eccsize = chip->ecc.size;
 950         int eccbytes = chip->ecc.bytes;
 951         int eccsteps = chip->ecc.steps;
 952         uint8_t *p = buf;
 953         uint8_t *ecc_calc = chip->buffers->ecccalc;
 954         uint8_t *ecc_code = chip->buffers->ecccode;
 955         uint32_t *eccpos = chip->ecc.layout->eccpos;
 956
 957         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 958                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 959                 chip->read_buf(mtd, p, eccsize);
 960                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 961         }
 962         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 963
 964         for (i = 0; i < chip->ecc.total; i++)
 965                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 966
 967         eccsteps = chip->ecc.steps;
 968         p = buf;
 969
 970         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 971                 int stat;
 972
 973                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 974                 if (stat < 0)
 975                         mtd->ecc_stats.failed++;
 976                 else
 977                         mtd->ecc_stats.corrected += stat;
 978         }
 979         return 0;
 980 }
 981
 982 /**
 983  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
 984  * @mtd:        mtd info structure
 985  * @chip:       nand chip info structure
 986  * @buf:        buffer to store read data
 987  *
 988  * The hw generator calculates the error syndrome automatically. Therefor
 989  * we need a special oob layout and handling.
 990  */
 991 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 992                                    uint8_t *buf)
 993 {
 994         int i, eccsize = chip->ecc.size;
 995         int eccbytes = chip->ecc.bytes;
 996         int eccsteps = chip->ecc.steps;
 997         uint8_t *p = buf;
 998         uint8_t *oob = chip->oob_poi;
 999
1000         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1001                 int stat;
1002
1003                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1004                 chip->read_buf(mtd, p, eccsize);
1005
1006                 if (chip->ecc.prepad) {
1007                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1008                         oob += chip->ecc.prepad;
1009                 }
1010
1011                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1012                 chip->read_buf(mtd, oob, eccbytes);
1013                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1014
1015                 if (stat < 0)
1016                         mtd->ecc_stats.failed++;
1017                 else
1018                         mtd->ecc_stats.corrected += stat;
1019
1020                 oob += eccbytes;
1021
1022                 if (chip->ecc.postpad) {
1023                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1024                         oob += chip->ecc.postpad;
1025                 }
1026         }
1027
1028         /* Calculate remaining oob bytes */
1029         i = mtd->oobsize - (oob - chip->oob_poi);
1030         if (i)
1031                 chip->read_buf(mtd, oob, i);
1032
1033         return 0;
1034 }
1035
1036 /**
1037  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1038  * @chip:       nand chip structure
1039  * @oob:        oob destination address
1040  * @ops:        oob ops structure
1041  * @len:        size of oob to transfer
1042  */
1043 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1044                                   struct mtd_oob_ops *ops, size_t len)
1045 {
1046         switch(ops->mode) {
1047
1048         case MTD_OOB_PLACE:
1049         case MTD_OOB_RAW:
1050                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1051                 return oob + len;
1052
1053         case MTD_OOB_AUTO: {
1054                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1055                 uint32_t boffs = 0, roffs = ops->ooboffs;
1056                 size_t bytes = 0;
1057
1058                 for(; free->length && len; free++, len -= bytes) {
1059                         /* Read request not from offset 0 ? */
1060                         if (unlikely(roffs)) {
1061                                 if (roffs >= free->length) {
1062                                         roffs -= free->length;
1063                                         continue;
1064                                 }
1065                                 boffs = free->offset + roffs;
1066                                 bytes = min_t(size_t, len,
1067                                               (free->length - roffs));
1068                                 roffs = 0;
1069                         } else {
1070                                 bytes = min_t(size_t, len, free->length);
1071                                 boffs = free->offset;
1072                         }
1073                         memcpy(oob, chip->oob_poi + boffs, bytes);
1074                         oob += bytes;
1075                 }
1076                 return oob;
1077         }
1078         default:
1079                 BUG();
1080         }
1081         return NULL;
1082 }
1083
1084 /**
1085  * nand_do_read_ops - [Internal] Read data with ECC
1086  *
1087  * @mtd:        MTD device structure
1088  * @from:       offset to read from
1089  * @ops:        oob ops structure
1090  *
1091  * Internal function. Called with chip held.
1092  */
1093 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1094                             struct mtd_oob_ops *ops)
1095 {
1096         int chipnr, page, realpage, col, bytes, aligned;
1097         struct nand_chip *chip = mtd->priv;
1098         struct mtd_ecc_stats stats;
1099         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1100         int sndcmd = 1;
1101         int ret = 0;
1102         uint32_t readlen = ops->len;
1103         uint32_t oobreadlen = ops->ooblen;
1104         uint8_t *bufpoi, *oob, *buf;
1105
1106         stats = mtd->ecc_stats;
1107
1108         chipnr = (int)(from >> chip->chip_shift);
1109         chip->select_chip(mtd, chipnr);
1110
1111         realpage = (int)(from >> chip->page_shift);
1112         page = realpage & chip->pagemask;
1113
1114         col = (int)(from & (mtd->writesize - 1));
1115
1116         buf = ops->datbuf;
1117         oob = ops->oobbuf;
1118
1119         while(1) {
1120                 bytes = min(mtd->writesize - col, readlen);
1121                 aligned = (bytes == mtd->writesize);
1122
1123                 /* Is the current page in the buffer ? */
1124                 if (realpage != chip->pagebuf || oob) {
1125                         bufpoi = aligned ? buf : chip->buffers->databuf;
1126
1127                         if (likely(sndcmd)) {
1128                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1129                                 sndcmd = 0;
1130                         }
1131
1132                         /* Now read the page into the buffer */
1133                         if (unlikely(ops->mode == MTD_OOB_RAW))
1134                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1135                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1136                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1137                         else
1138                                 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1139                         if (ret < 0)
1140                                 break;
1141
1142                         /* Transfer not aligned data */
1143                         if (!aligned) {
1144                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1145                                         chip->pagebuf = realpage;
1146                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1147                         }
1148
1149                         buf += bytes;
1150
1151                         if (unlikely(oob)) {
1152                                 /* Raw mode does data:oob:data:oob */
1153                                 if (ops->mode != MTD_OOB_RAW) {
1154                                         int toread = min(oobreadlen,
1155                                                 chip->ecc.layout->oobavail);
1156                                         if (toread) {
1157                                                 oob = nand_transfer_oob(chip,
1158                                                         oob, ops, toread);
1159                                                 oobreadlen -= toread;
1160                                         }
1161                                 } else
1162                                         buf = nand_transfer_oob(chip,
1163                                                 buf, ops, mtd->oobsize);
1164                         }
1165
1166                         if (!(chip->options & NAND_NO_READRDY)) {
1167                                 /*
1168                                  * Apply delay or wait for ready/busy pin. Do
1169                                  * this before the AUTOINCR check, so no
1170                                  * problems arise if a chip which does auto
1171                                  * increment is marked as NOAUTOINCR by the
1172                                  * board driver.
1173                                  */
1174                                 if (!chip->dev_ready)
1175                                         udelay(chip->chip_delay);
1176                                 else
1177                                         nand_wait_ready(mtd);
1178                         }
1179                 } else {
1180                         memcpy(buf, chip->buffers->databuf + col, bytes);
1181                         buf += bytes;
1182                 }
1183
1184                 readlen -= bytes;
1185
1186                 if (!readlen)
1187                         break;
1188
1189                 /* For subsequent reads align to page boundary. */
1190                 col = 0;
1191                 /* Increment page address */
1192                 realpage++;
1193
1194                 page = realpage & chip->pagemask;
1195                 /* Check, if we cross a chip boundary */
1196                 if (!page) {
1197                         chipnr++;
1198                         chip->select_chip(mtd, -1);
1199                         chip->select_chip(mtd, chipnr);
1200                 }
1201
1202                 /* Check, if the chip supports auto page increment
1203                  * or if we have hit a block boundary.
1204                  */
1205                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1206                         sndcmd = 1;
1207         }
1208
1209         ops->retlen = ops->len - (size_t) readlen;
1210         if (oob)
1211                 ops->oobretlen = ops->ooblen - oobreadlen;
1212
1213         if (ret)
1214                 return ret;
1215
1216         if (mtd->ecc_stats.failed - stats.failed)
1217                 return -EBADMSG;
1218
1219         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1220 }
1221
1222 /**
1223  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1224  * @mtd:        MTD device structure
1225  * @from:       offset to read from
1226  * @len:        number of bytes to read
1227  * @retlen:     pointer to variable to store the number of read bytes
1228  * @buf:        the databuffer to put data
1229  *
1230  * Get hold of the chip and call nand_do_read
1231  */
1232 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1233                      size_t *retlen, uint8_t *buf)
1234 {
1235         struct nand_chip *chip = mtd->priv;
1236         int ret;
1237
1238         /* Do not allow reads past end of device */
1239         if ((from + len) > mtd->size)
1240                 return -EINVAL;
1241         if (!len)
1242                 return 0;
1243
1244         nand_get_device(chip, mtd, FL_READING);
1245
1246         chip->ops.len = len;
1247         chip->ops.datbuf = buf;
1248         chip->ops.oobbuf = NULL;
1249
1250         ret = nand_do_read_ops(mtd, from, &chip->ops);
1251
1252         *retlen = chip->ops.retlen;
1253
1254         nand_release_device(mtd);
1255
1256         return ret;
1257 }
1258
1259 /**
1260  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1261  * @mtd:        mtd info structure
1262  * @chip:       nand chip info structure
1263  * @page:       page number to read
1264  * @sndcmd:     flag whether to issue read command or not
1265  */
1266 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1267                              int page, int sndcmd)
1268 {
1269         if (sndcmd) {
1270                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1271                 sndcmd = 0;
1272         }
1273         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1274         return sndcmd;
1275 }
1276
1277 /**
1278  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1279  *                          with syndromes
1280  * @mtd:        mtd info structure
1281  * @chip:       nand chip info structure
1282  * @page:       page number to read
1283  * @sndcmd:     flag whether to issue read command or not
1284  */
1285 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1286                                   int page, int sndcmd)
1287 {
1288         uint8_t *buf = chip->oob_poi;
1289         int length = mtd->oobsize;
1290         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1291         int eccsize = chip->ecc.size;
1292         uint8_t *bufpoi = buf;
1293         int i, toread, sndrnd = 0, pos;
1294
1295         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1296         for (i = 0; i < chip->ecc.steps; i++) {
1297                 if (sndrnd) {
1298                         pos = eccsize + i * (eccsize + chunk);
1299                         if (mtd->writesize > 512)
1300                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1301                         else
1302                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1303                 } else
1304                         sndrnd = 1;
1305                 toread = min_t(int, length, chunk);
1306                 chip->read_buf(mtd, bufpoi, toread);
1307                 bufpoi += toread;
1308                 length -= toread;
1309         }
1310         if (length > 0)
1311                 chip->read_buf(mtd, bufpoi, length);
1312
1313         return 1;
1314 }
1315
1316 /**
1317  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1318  * @mtd:        mtd info structure
1319  * @chip:       nand chip info structure
1320  * @page:       page number to write
1321  */
1322 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1323                               int page)
1324 {
1325         int status = 0;
1326         const uint8_t *buf = chip->oob_poi;
1327         int length = mtd->oobsize;
1328
1329         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1330         chip->write_buf(mtd, buf, length);
1331         /* Send command to program the OOB data */
1332         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1333
1334         status = chip->waitfunc(mtd, chip);
1335
1336         return status & NAND_STATUS_FAIL ? -EIO : 0;
1337 }
1338
1339 /**
1340  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1341  *                           with syndrome - only for large page flash !
1342  * @mtd:        mtd info structure
1343  * @chip:       nand chip info structure
1344  * @page:       page number to write
1345  */
1346 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1347                                    struct nand_chip *chip, int page)
1348 {
1349         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1350         int eccsize = chip->ecc.size, length = mtd->oobsize;
1351         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1352         const uint8_t *bufpoi = chip->oob_poi;
1353
1354         /*
1355          * data-ecc-data-ecc ... ecc-oob
1356          * or
1357          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1358          */
1359         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1360                 pos = steps * (eccsize + chunk);
1361                 steps = 0;
1362         } else
1363                 pos = eccsize;
1364
1365         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1366         for (i = 0; i < steps; i++) {
1367                 if (sndcmd) {
1368                         if (mtd->writesize <= 512) {
1369                                 uint32_t fill = 0xFFFFFFFF;
1370
1371                                 len = eccsize;
1372                                 while (len > 0) {
1373                                         int num = min_t(int, len, 4);
1374                                         chip->write_buf(mtd, (uint8_t *)&fill,
1375                                                         num);
1376                                         len -= num;
1377                                 }
1378                         } else {
1379                                 pos = eccsize + i * (eccsize + chunk);
1380                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1381                         }
1382                 } else
1383                         sndcmd = 1;
1384                 len = min_t(int, length, chunk);
1385                 chip->write_buf(mtd, bufpoi, len);
1386                 bufpoi += len;
1387                 length -= len;
1388         }
1389         if (length > 0)
1390                 chip->write_buf(mtd, bufpoi, length);
1391
1392         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1393         status = chip->waitfunc(mtd, chip);
1394
1395         return status & NAND_STATUS_FAIL ? -EIO : 0;
1396 }
1397
1398 /**
1399  * nand_do_read_oob - [Intern] NAND read out-of-band
1400  * @mtd:        MTD device structure
1401  * @from:       offset to read from
1402  * @ops:        oob operations description structure
1403  *
1404  * NAND read out-of-band data from the spare area
1405  */
1406 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1407                             struct mtd_oob_ops *ops)
1408 {
1409         int page, realpage, chipnr, sndcmd = 1;
1410         struct nand_chip *chip = mtd->priv;
1411         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1412         int readlen = ops->ooblen;
1413         int len;
1414         uint8_t *buf = ops->oobbuf;
1415
1416         DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1417               (unsigned long long)from, readlen);
1418
1419         if (ops->mode == MTD_OOB_AUTO)
1420                 len = chip->ecc.layout->oobavail;
1421         else
1422                 len = mtd->oobsize;
1423
1424         if (unlikely(ops->ooboffs >= len)) {
1425                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1426                         "Attempt to start read outside oob\n");
1427                 return -EINVAL;
1428         }
1429
1430         /* Do not allow reads past end of device */
1431         if (unlikely(from >= mtd->size ||
1432                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1433                                         (from >> chip->page_shift)) * len)) {
1434                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1435                         "Attempt read beyond end of device\n");
1436                 return -EINVAL;
1437         }
1438
1439         chipnr = (int)(from >> chip->chip_shift);
1440         chip->select_chip(mtd, chipnr);
1441
1442         /* Shift to get page */
1443         realpage = (int)(from >> chip->page_shift);
1444         page = realpage & chip->pagemask;
1445
1446         while(1) {
1447                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1448
1449                 len = min(len, readlen);
1450                 buf = nand_transfer_oob(chip, buf, ops, len);
1451
1452                 if (!(chip->options & NAND_NO_READRDY)) {
1453                         /*
1454                          * Apply delay or wait for ready/busy pin. Do this
1455                          * before the AUTOINCR check, so no problems arise if a
1456                          * chip which does auto increment is marked as
1457                          * NOAUTOINCR by the board driver.
1458                          */
1459                         if (!chip->dev_ready)
1460                                 udelay(chip->chip_delay);
1461                         else
1462                                 nand_wait_ready(mtd);
1463                 }
1464
1465                 readlen -= len;
1466                 if (!readlen)
1467                         break;
1468
1469                 /* Increment page address */
1470                 realpage++;
1471
1472                 page = realpage & chip->pagemask;
1473                 /* Check, if we cross a chip boundary */
1474                 if (!page) {
1475                         chipnr++;
1476                         chip->select_chip(mtd, -1);
1477                         chip->select_chip(mtd, chipnr);
1478                 }
1479
1480                 /* Check, if the chip supports auto page increment
1481                  * or if we have hit a block boundary.
1482                  */
1483                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1484                         sndcmd = 1;
1485         }
1486
1487         ops->oobretlen = ops->ooblen;
1488         return 0;
1489 }
1490
1491 /**
1492  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1493  * @mtd:        MTD device structure
1494  * @from:       offset to read from
1495  * @ops:        oob operation description structure
1496  *
1497  * NAND read data and/or out-of-band data
1498  */
1499 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1500                          struct mtd_oob_ops *ops)
1501 {
1502         struct nand_chip *chip = mtd->priv;
1503         int ret = -ENOTSUPP;
1504
1505         ops->retlen = 0;
1506
1507         /* Do not allow reads past end of device */
1508         if (ops->datbuf && (from + ops->len) > mtd->size) {
1509                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1510                       "Attempt read beyond end of device\n");
1511                 return -EINVAL;
1512         }
1513
1514         nand_get_device(chip, mtd, FL_READING);
1515
1516         switch(ops->mode) {
1517         case MTD_OOB_PLACE:
1518         case MTD_OOB_AUTO:
1519         case MTD_OOB_RAW:
1520                 break;
1521
1522         default:
1523                 goto out;
1524         }
1525
1526         if (!ops->datbuf)
1527                 ret = nand_do_read_oob(mtd, from, ops);
1528         else
1529                 ret = nand_do_read_ops(mtd, from, ops);
1530
1531  out:
1532         nand_release_device(mtd);
1533         return ret;
1534 }
1535
1536
1537 /**
1538  * nand_write_page_raw - [Intern] raw page write function
1539  * @mtd:        mtd info structure
1540  * @chip:       nand chip info structure
1541  * @buf:        data buffer
1542  *
1543  * Not for syndrome calculating ecc controllers, which use a special oob layout
1544  */
1545 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1546                                 const uint8_t *buf)
1547 {
1548         chip->write_buf(mtd, buf, mtd->writesize);
1549         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1550 }
1551
1552 /**
1553  * nand_write_page_raw_syndrome - [Intern] raw page write function
1554  * @mtd:        mtd info structure
1555  * @chip:       nand chip info structure
1556  * @buf:        data buffer
1557  *
1558  * We need a special oob layout and handling even when ECC isn't checked.
1559  */
1560 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1561                                 const uint8_t *buf)
1562 {
1563         int eccsize = chip->ecc.size;
1564         int eccbytes = chip->ecc.bytes;
1565         uint8_t *oob = chip->oob_poi;
1566         int steps, size;
1567
1568         for (steps = chip->ecc.steps; steps > 0; steps--) {
1569                 chip->write_buf(mtd, buf, eccsize);
1570                 buf += eccsize;
1571
1572                 if (chip->ecc.prepad) {
1573                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1574                         oob += chip->ecc.prepad;
1575                 }
1576
1577                 chip->read_buf(mtd, oob, eccbytes);
1578                 oob += eccbytes;
1579
1580                 if (chip->ecc.postpad) {
1581                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1582                         oob += chip->ecc.postpad;
1583                 }
1584         }
1585
1586         size = mtd->oobsize - (oob - chip->oob_poi);
1587         if (size)
1588                 chip->write_buf(mtd, oob, size);
1589 }
1590 /**
1591  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1592  * @mtd:        mtd info structure
1593  * @chip:       nand chip info structure
1594  * @buf:        data buffer
1595  */
1596 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1597                                   const uint8_t *buf)
1598 {
1599         int i, eccsize = chip->ecc.size;
1600         int eccbytes = chip->ecc.bytes;
1601         int eccsteps = chip->ecc.steps;
1602         uint8_t *ecc_calc = chip->buffers->ecccalc;
1603         const uint8_t *p = buf;
1604         uint32_t *eccpos = chip->ecc.layout->eccpos;
1605
1606         /* Software ecc calculation */
1607         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1608                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1609
1610         for (i = 0; i < chip->ecc.total; i++)
1611                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1612
1613         chip->ecc.write_page_raw(mtd, chip, buf);
1614 }
1615
1616 /**
1617  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1618  * @mtd:        mtd info structure
1619  * @chip:       nand chip info structure
1620  * @buf:        data buffer
1621  */
1622 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1623                                   const uint8_t *buf)
1624 {
1625         int i, eccsize = chip->ecc.size;
1626         int eccbytes = chip->ecc.bytes;
1627         int eccsteps = chip->ecc.steps;
1628         uint8_t *ecc_calc = chip->buffers->ecccalc;
1629         const uint8_t *p = buf;
1630         uint32_t *eccpos = chip->ecc.layout->eccpos;
1631
1632         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1633                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1634                 chip->write_buf(mtd, p, eccsize);
1635                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1636         }
1637
1638         for (i = 0; i < chip->ecc.total; i++)
1639                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1640
1641         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1642 }
1643
1644 /**
1645  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1646  * @mtd:        mtd info structure
1647  * @chip:       nand chip info structure
1648  * @buf:        data buffer
1649  *
1650  * The hw generator calculates the error syndrome automatically. Therefor
1651  * we need a special oob layout and handling.
1652  */
1653 static void nand_write_page_syndrome(struct mtd_info *mtd,
1654                                     struct nand_chip *chip, const uint8_t *buf)
1655 {
1656         int i, eccsize = chip->ecc.size;
1657         int eccbytes = chip->ecc.bytes;
1658         int eccsteps = chip->ecc.steps;
1659         const uint8_t *p = buf;
1660         uint8_t *oob = chip->oob_poi;
1661
1662         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1663
1664                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1665                 chip->write_buf(mtd, p, eccsize);
1666
1667                 if (chip->ecc.prepad) {
1668                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1669                         oob += chip->ecc.prepad;
1670                 }
1671
1672                 chip->ecc.calculate(mtd, p, oob);
1673                 chip->write_buf(mtd, oob, eccbytes);
1674                 oob += eccbytes;
1675
1676                 if (chip->ecc.postpad) {
1677                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1678                         oob += chip->ecc.postpad;
1679                 }
1680         }
1681
1682         /* Calculate remaining oob bytes */
1683         i = mtd->oobsize - (oob - chip->oob_poi);
1684         if (i)
1685                 chip->write_buf(mtd, oob, i);
1686 }
1687
1688 /**
1689  * nand_write_page - [REPLACEABLE] write one page
1690  * @mtd:        MTD device structure
1691  * @chip:       NAND chip descriptor
1692  * @buf:        the data to write
1693  * @page:       page number to write
1694  * @cached:     cached programming
1695  * @raw:        use _raw version of write_page
1696  */
1697 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1698                            const uint8_t *buf, int page, int cached, int raw)
1699 {
1700         int status;
1701
1702         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1703
1704         if (unlikely(raw))
1705                 chip->ecc.write_page_raw(mtd, chip, buf);
1706         else
1707                 chip->ecc.write_page(mtd, chip, buf);
1708
1709         /*
1710          * Cached progamming disabled for now, Not sure if its worth the
1711          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1712          */
1713         cached = 0;
1714
1715         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1716
1717                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1718                 status = chip->waitfunc(mtd, chip);
1719                 /*
1720                  * See if operation failed and additional status checks are
1721                  * available
1722                  */
1723                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1724                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1725                                                page);
1726
1727                 if (status & NAND_STATUS_FAIL)
1728                         return -EIO;
1729         } else {
1730                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1731                 status = chip->waitfunc(mtd, chip);
1732         }
1733
1734 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1735         /* Send command to read back the data */
1736         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1737
1738         if (chip->verify_buf(mtd, buf, mtd->writesize))
1739                 return -EIO;
1740 #endif
1741         return 0;
1742 }
1743
1744 /**
1745  * nand_fill_oob - [Internal] Transfer client buffer to oob
1746  * @chip:       nand chip structure
1747  * @oob:        oob data buffer
1748  * @ops:        oob ops structure
1749  */
1750 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1751                                   struct mtd_oob_ops *ops)
1752 {
1753         size_t len = ops->ooblen;
1754
1755         switch(ops->mode) {
1756
1757         case MTD_OOB_PLACE:
1758         case MTD_OOB_RAW:
1759                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1760                 return oob + len;
1761
1762         case MTD_OOB_AUTO: {
1763                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1764                 uint32_t boffs = 0, woffs = ops->ooboffs;
1765                 size_t bytes = 0;
1766
1767                 for(; free->length && len; free++, len -= bytes) {
1768                         /* Write request not from offset 0 ? */
1769                         if (unlikely(woffs)) {
1770                                 if (woffs >= free->length) {
1771                                         woffs -= free->length;
1772                                         continue;
1773                                 }
1774                                 boffs = free->offset + woffs;
1775                                 bytes = min_t(size_t, len,
1776                                               (free->length - woffs));
1777                                 woffs = 0;
1778                         } else {
1779                                 bytes = min_t(size_t, len, free->length);
1780                                 boffs = free->offset;
1781                         }
1782                         memcpy(chip->oob_poi + boffs, oob, bytes);
1783                         oob += bytes;
1784                 }
1785                 return oob;
1786         }
1787         default:
1788                 BUG();
1789         }
1790         return NULL;
1791 }
1792
1793 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1794
1795 /**
1796  * nand_do_write_ops - [Internal] NAND write with ECC
1797  * @mtd:        MTD device structure
1798  * @to:         offset to write to
1799  * @ops:        oob operations description structure
1800  *
1801  * NAND write with ECC
1802  */
1803 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1804                              struct mtd_oob_ops *ops)
1805 {
1806         int chipnr, realpage, page, blockmask, column;
1807         struct nand_chip *chip = mtd->priv;
1808         uint32_t writelen = ops->len;
1809         uint8_t *oob = ops->oobbuf;
1810         uint8_t *buf = ops->datbuf;
1811         int ret, subpage;
1812
1813         ops->retlen = 0;
1814         if (!writelen)
1815                 return 0;
1816
1817         /* reject writes, which are not page aligned */
1818         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1819                 printk(KERN_NOTICE "nand_write: "
1820                        "Attempt to write not page aligned data\n");
1821                 return -EINVAL;
1822         }
1823
1824         column = to & (mtd->writesize - 1);
1825         subpage = column || (writelen & (mtd->writesize - 1));
1826
1827         if (subpage && oob)
1828                 return -EINVAL;
1829
1830         chipnr = (int)(to >> chip->chip_shift);
1831         chip->select_chip(mtd, chipnr);
1832
1833         /* Check, if it is write protected */
1834         if (nand_check_wp(mtd))
1835                 return -EIO;
1836
1837         realpage = (int)(to >> chip->page_shift);
1838         page = realpage & chip->pagemask;
1839         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1840
1841         /* Invalidate the page cache, when we write to the cached page */
1842         if (to <= (chip->pagebuf << chip->page_shift) &&
1843             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1844                 chip->pagebuf = -1;
1845
1846         /* If we're not given explicit OOB data, let it be 0xFF */
1847         if (likely(!oob))
1848                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1849
1850         while(1) {
1851                 int bytes = mtd->writesize;
1852                 int cached = writelen > bytes && page != blockmask;
1853                 uint8_t *wbuf = buf;
1854
1855                 /* Partial page write ? */
1856                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1857                         cached = 0;
1858                         bytes = min_t(int, bytes - column, (int) writelen);
1859                         chip->pagebuf = -1;
1860                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1861                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1862                         wbuf = chip->buffers->databuf;
1863                 }
1864
1865                 if (unlikely(oob))
1866                         oob = nand_fill_oob(chip, oob, ops);
1867
1868                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1869                                        (ops->mode == MTD_OOB_RAW));
1870                 if (ret)
1871                         break;
1872
1873                 writelen -= bytes;
1874                 if (!writelen)
1875                         break;
1876
1877                 column = 0;
1878                 buf += bytes;
1879                 realpage++;
1880
1881                 page = realpage & chip->pagemask;
1882                 /* Check, if we cross a chip boundary */
1883                 if (!page) {
1884                         chipnr++;
1885                         chip->select_chip(mtd, -1);
1886                         chip->select_chip(mtd, chipnr);
1887                 }
1888         }
1889
1890         ops->retlen = ops->len - writelen;
1891         if (unlikely(oob))
1892                 ops->oobretlen = ops->ooblen;
1893         return ret;
1894 }
1895
1896 /**
1897  * nand_write - [MTD Interface] NAND write with ECC
1898  * @mtd:        MTD device structure
1899  * @to:         offset to write to
1900  * @len:        number of bytes to write
1901  * @retlen:     pointer to variable to store the number of written bytes
1902  * @buf:        the data to write
1903  *
1904  * NAND write with ECC
1905  */
1906 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1907                           size_t *retlen, const uint8_t *buf)
1908 {
1909         struct nand_chip *chip = mtd->priv;
1910         int ret;
1911
1912         /* Do not allow reads past end of device */
1913         if ((to + len) > mtd->size)
1914                 return -EINVAL;
1915         if (!len)
1916                 return 0;
1917
1918         nand_get_device(chip, mtd, FL_WRITING);
1919
1920         chip->ops.len = len;
1921         chip->ops.datbuf = (uint8_t *)buf;
1922         chip->ops.oobbuf = NULL;
1923
1924         ret = nand_do_write_ops(mtd, to, &chip->ops);
1925
1926         *retlen = chip->ops.retlen;
1927
1928         nand_release_device(mtd);
1929
1930         return ret;
1931 }
1932
1933 /**
1934  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1935  * @mtd:        MTD device structure
1936  * @to:         offset to write to
1937  * @ops:        oob operation description structure
1938  *
1939  * NAND write out-of-band
1940  */
1941 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1942                              struct mtd_oob_ops *ops)
1943 {
1944         int chipnr, page, status, len;
1945         struct nand_chip *chip = mtd->priv;
1946
1947         DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1948               (unsigned int)to, (int)ops->ooblen);
1949
1950         if (ops->mode == MTD_OOB_AUTO)
1951                 len = chip->ecc.layout->oobavail;
1952         else
1953                 len = mtd->oobsize;
1954
1955         /* Do not allow write past end of page */
1956         if ((ops->ooboffs + ops->ooblen) > len) {
1957                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1958                       "Attempt to write past end of page\n");
1959                 return -EINVAL;
1960         }
1961
1962         if (unlikely(ops->ooboffs >= len)) {
1963                 DEBUG(MTD_DEBUG_LEVEL0, "nand_do_write_oob: "
1964                         "Attempt to start write outside oob\n");
1965                 return -EINVAL;
1966         }
1967
1968         /* Do not allow reads past end of device */
1969         if (unlikely(to >= mtd->size ||
1970                      ops->ooboffs + ops->ooblen >
1971                         ((mtd->size >> chip->page_shift) -
1972                          (to >> chip->page_shift)) * len)) {
1973                 DEBUG(MTD_DEBUG_LEVEL0, "nand_do_write_oob: "
1974                         "Attempt write beyond end of device\n");
1975                 return -EINVAL;
1976         }
1977
1978         chipnr = (int)(to >> chip->chip_shift);
1979         chip->select_chip(mtd, chipnr);
1980
1981         /* Shift to get page */
1982         page = (int)(to >> chip->page_shift);
1983
1984         /*
1985          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1986          * of my DiskOnChip 2000 test units) will clear the whole data page too
1987          * if we don't do this. I have no clue why, but I seem to have 'fixed'
1988          * it in the doc2000 driver in August 1999.  dwmw2.
1989          */
1990         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1991
1992         /* Check, if it is write protected */
1993         if (nand_check_wp(mtd))
1994                 return -EROFS;
1995
1996         /* Invalidate the page cache, if we write to the cached page */
1997         if (page == chip->pagebuf)
1998                 chip->pagebuf = -1;
1999
2000         memset(chip->oob_poi, 0xff, mtd->oobsize);
2001         nand_fill_oob(chip, ops->oobbuf, ops);
2002         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2003         memset(chip->oob_poi, 0xff, mtd->oobsize);
2004
2005         if (status)
2006                 return status;
2007
2008         ops->oobretlen = ops->ooblen;
2009
2010         return 0;
2011 }
2012
2013 /**
2014  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2015  * @mtd:        MTD device structure
2016  * @to:         offset to write to
2017  * @ops:        oob operation description structure
2018  */
2019 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2020                           struct mtd_oob_ops *ops)
2021 {
2022         struct nand_chip *chip = mtd->priv;
2023         int ret = -ENOTSUPP;
2024
2025         ops->retlen = 0;
2026
2027         /* Do not allow writes past end of device */
2028         if (ops->datbuf && (to + ops->len) > mtd->size) {
2029                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
2030                       "Attempt write beyond end of device\n");
2031                 return -EINVAL;
2032         }
2033
2034         nand_get_device(chip, mtd, FL_WRITING);
2035
2036         switch(ops->mode) {
2037         case MTD_OOB_PLACE:
2038         case MTD_OOB_AUTO:
2039         case MTD_OOB_RAW:
2040                 break;
2041
2042         default:
2043                 goto out;
2044         }
2045
2046         if (!ops->datbuf)
2047                 ret = nand_do_write_oob(mtd, to, ops);
2048         else
2049                 ret = nand_do_write_ops(mtd, to, ops);
2050
2051  out:
2052         nand_release_device(mtd);
2053         return ret;
2054 }
2055
2056 /**
2057  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2058  * @mtd:        MTD device structure
2059  * @page:       the page address of the block which will be erased
2060  *
2061  * Standard erase command for NAND chips
2062  */
2063 static void single_erase_cmd(struct mtd_info *mtd, int page)
2064 {
2065         struct nand_chip *chip = mtd->priv;
2066         /* Send commands to erase a block */
2067         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2068         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2069 }
2070
2071 /**
2072  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2073  * @mtd:        MTD device structure
2074  * @page:       the page address of the block which will be erased
2075  *
2076  * AND multi block erase command function
2077  * Erase 4 consecutive blocks
2078  */
2079 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2080 {
2081         struct nand_chip *chip = mtd->priv;
2082         /* Send commands to erase a block */
2083         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2084         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2085         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2086         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2087         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2088 }
2089
2090 /**
2091  * nand_erase - [MTD Interface] erase block(s)
2092  * @mtd:        MTD device structure
2093  * @instr:      erase instruction
2094  *
2095  * Erase one ore more blocks
2096  */
2097 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2098 {
2099         return nand_erase_nand(mtd, instr, 0);
2100 }
2101
2102 #define BBT_PAGE_MASK   0xffffff3f
2103 /**
2104  * nand_erase_nand - [Internal] erase block(s)
2105  * @mtd:        MTD device structure
2106  * @instr:      erase instruction
2107  * @allowbbt:   allow erasing the bbt area
2108  *
2109  * Erase one ore more blocks
2110  */
2111 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2112                     int allowbbt)
2113 {
2114         int page, status, pages_per_block, ret, chipnr;
2115         struct nand_chip *chip = mtd->priv;
2116         loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
2117         unsigned int bbt_masked_page = 0xffffffff;
2118         loff_t len;
2119
2120         DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, len = %llu\n",
2121               (unsigned long long)instr->addr, (unsigned long long)instr->len);
2122
2123         /* Start address must align on block boundary */
2124         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2125                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2126                 return -EINVAL;
2127         }
2128
2129         /* Length must align on block boundary */
2130         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2131                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2132                       "Length not block aligned\n");
2133                 return -EINVAL;
2134         }
2135
2136         /* Do not allow erase past end of device */
2137         if ((instr->len + instr->addr) > mtd->size) {
2138                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2139                       "Erase past end of device\n");
2140                 return -EINVAL;
2141         }
2142
2143         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2144
2145         /* Grab the lock and see if the device is available */
2146         nand_get_device(chip, mtd, FL_ERASING);
2147
2148         /* Shift to get first page */
2149         page = (int)(instr->addr >> chip->page_shift);
2150         chipnr = (int)(instr->addr >> chip->chip_shift);
2151
2152         /* Calculate pages in each block */
2153         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2154
2155         /* Select the NAND device */
2156         chip->select_chip(mtd, chipnr);
2157
2158         /* Check, if it is write protected */
2159         if (nand_check_wp(mtd)) {
2160                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2161                       "Device is write protected!!!\n");
2162                 instr->state = MTD_ERASE_FAILED;
2163                 goto erase_exit;
2164         }
2165
2166         /*
2167          * If BBT requires refresh, set the BBT page mask to see if the BBT
2168          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2169          * can not be matched. This is also done when the bbt is actually
2170          * erased to avoid recusrsive updates
2171          */
2172         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2173                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2174
2175         /* Loop through the pages */
2176         len = instr->len;
2177
2178         instr->state = MTD_ERASING;
2179
2180         while (len) {
2181                 /*
2182                  * heck if we have a bad block, we do not erase bad blocks !
2183                  */
2184                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2185                                         chip->page_shift, 0, allowbbt)) {
2186                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2187                                "bad block at page 0x%08x\n", page);
2188                         instr->state = MTD_ERASE_FAILED;
2189                         goto erase_exit;
2190                 }
2191
2192                 /*
2193                  * Invalidate the page cache, if we erase the block which
2194                  * contains the current cached page
2195                  */
2196                 if (page <= chip->pagebuf && chip->pagebuf <
2197                     (page + pages_per_block))
2198                         chip->pagebuf = -1;
2199
2200                 chip->erase_cmd(mtd, page & chip->pagemask);
2201
2202                 status = chip->waitfunc(mtd, chip);
2203
2204                 /*
2205                  * See if operation failed and additional status checks are
2206                  * available
2207                  */
2208                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2209                         status = chip->errstat(mtd, chip, FL_ERASING,
2210                                                status, page);
2211
2212                 /* See if block erase succeeded */
2213                 if (status & NAND_STATUS_FAIL) {
2214                         DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2215                               "Failed erase, page 0x%08x\n", page);
2216                         instr->state = MTD_ERASE_FAILED;
2217                         instr->fail_addr =
2218                                 ((loff_t)page << chip->page_shift);
2219                         goto erase_exit;
2220                 }
2221
2222                 /*
2223                  * If BBT requires refresh, set the BBT rewrite flag to the
2224                  * page being erased
2225                  */
2226                 if (bbt_masked_page != 0xffffffff &&
2227                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2228                             rewrite_bbt[chipnr] =
2229                                         ((loff_t)page << chip->page_shift);
2230
2231                 /* Increment page address and decrement length */
2232                 len -= (1 << chip->phys_erase_shift);
2233                 page += pages_per_block;
2234
2235                 /* Check, if we cross a chip boundary */
2236                 if (len && !(page & chip->pagemask)) {
2237                         chipnr++;
2238                         chip->select_chip(mtd, -1);
2239                         chip->select_chip(mtd, chipnr);
2240
2241                         /*
2242                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2243                          * page mask to see if this BBT should be rewritten
2244                          */
2245                         if (bbt_masked_page != 0xffffffff &&
2246                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2247                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2248                                         BBT_PAGE_MASK;
2249                 }
2250         }
2251         instr->state = MTD_ERASE_DONE;
2252
2253  erase_exit:
2254
2255         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2256
2257         /* Deselect and wake up anyone waiting on the device */
2258         nand_release_device(mtd);
2259
2260         /* Do call back function */
2261         if (!ret)
2262                 mtd_erase_callback(instr);
2263
2264         /*
2265          * If BBT requires refresh and erase was successful, rewrite any
2266          * selected bad block tables
2267          */
2268         if (bbt_masked_page == 0xffffffff || ret)
2269                 return ret;
2270
2271         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2272                 if (!rewrite_bbt[chipnr])
2273                         continue;
2274                 /* update the BBT for chip */
2275                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2276                       "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2277                       chip->bbt_td->pages[chipnr]);
2278                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2279         }
2280
2281         /* Return more or less happy */
2282         return ret;
2283 }
2284
2285 /**
2286  * nand_sync - [MTD Interface] sync
2287  * @mtd:        MTD device structure
2288  *
2289  * Sync is actually a wait for chip ready function
2290  */
2291 static void nand_sync(struct mtd_info *mtd)
2292 {
2293         struct nand_chip *chip = mtd->priv;
2294
2295         DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2296
2297         /* Grab the lock and see if the device is available */
2298         nand_get_device(chip, mtd, FL_SYNCING);
2299         /* Release it and go back */
2300         nand_release_device(mtd);
2301 }
2302
2303 /**
2304  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2305  * @mtd:        MTD device structure
2306  * @offs:       offset relative to mtd start
2307  */
2308 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2309 {
2310         /* Check for invalid offset */
2311         if (offs > mtd->size)
2312                 return -EINVAL;
2313
2314         return nand_block_checkbad(mtd, offs, 1, 0);
2315 }
2316
2317 /**
2318  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2319  * @mtd:        MTD device structure
2320  * @ofs:        offset relative to mtd start
2321  */
2322 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2323 {
2324         struct nand_chip *chip = mtd->priv;
2325         int ret;
2326
2327         if ((ret = nand_block_isbad(mtd, ofs))) {
2328                 /* If it was bad already, return success and do nothing. */
2329                 if (ret > 0)
2330                         return 0;
2331                 return ret;
2332         }
2333
2334         return chip->block_markbad(mtd, ofs);
2335 }
2336
2337 /**
2338  * nand_suspend - [MTD Interface] Suspend the NAND flash
2339  * @mtd:        MTD device structure
2340  */
2341 static int nand_suspend(struct mtd_info *mtd)
2342 {
2343         struct nand_chip *chip = mtd->priv;
2344
2345         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2346 }
2347
2348 /**
2349  * nand_resume - [MTD Interface] Resume the NAND flash
2350  * @mtd:        MTD device structure
2351  */
2352 static void nand_resume(struct mtd_info *mtd)
2353 {
2354         struct nand_chip *chip = mtd->priv;
2355
2356         if (chip->state == FL_PM_SUSPENDED)
2357                 nand_release_device(mtd);
2358         else
2359                 printk(KERN_ERR "nand_resume() called for a chip which is not "
2360                        "in suspended state\n");
2361 }
2362
2363 /*
2364  * Set default functions
2365  */
2366 static void nand_set_defaults(struct nand_chip *chip, int busw)
2367 {
2368         /* check for proper chip_delay setup, set 20us if not */
2369         if (!chip->chip_delay)
2370                 chip->chip_delay = 20;
2371
2372         /* check, if a user supplied command function given */
2373         if (chip->cmdfunc == NULL)
2374                 chip->cmdfunc = nand_command;
2375
2376         /* check, if a user supplied wait function given */
2377         if (chip->waitfunc == NULL)
2378                 chip->waitfunc = nand_wait;
2379
2380         if (!chip->select_chip)
2381                 chip->select_chip = nand_select_chip;
2382         if (!chip->read_byte)
2383                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2384         if (!chip->read_word)
2385                 chip->read_word = nand_read_word;
2386         if (!chip->block_bad)
2387                 chip->block_bad = nand_block_bad;
2388         if (!chip->block_markbad)
2389                 chip->block_markbad = nand_default_block_markbad;
2390         if (!chip->write_buf)
2391                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2392         if (!chip->read_buf)
2393                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2394         if (!chip->verify_buf)
2395                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2396         if (!chip->scan_bbt)
2397                 chip->scan_bbt = nand_default_bbt;
2398
2399         if (!chip->controller) {
2400                 chip->controller = &chip->hwcontrol;
2401                 spin_lock_init(&chip->controller->lock);
2402                 init_waitqueue_head(&chip->controller->wq);
2403         }
2404
2405 }
2406
2407 /*
2408  * Get the flash and manufacturer id and lookup if the type is supported
2409  */
2410 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2411                                                   struct nand_chip *chip,
2412                                                   int busw, int *maf_id)
2413 {
2414         struct nand_flash_dev *type = NULL;
2415         int i, dev_id, maf_idx;
2416         int tmp_id, tmp_manf;
2417
2418         /* Select the device */
2419         chip->select_chip(mtd, 0);
2420
2421         /*
2422          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2423          * after power-up
2424          */
2425         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2426
2427         /* Send the command for reading device ID */
2428         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2429
2430         /* Read manufacturer and device IDs */
2431         *maf_id = chip->read_byte(mtd);
2432         dev_id = chip->read_byte(mtd);
2433
2434         /* Try again to make sure, as some systems the bus-hold or other
2435          * interface concerns can cause random data which looks like a
2436          * possibly credible NAND flash to appear. If the two results do
2437          * not match, ignore the device completely.
2438          */
2439
2440         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2441
2442         /* Read manufacturer and device IDs */
2443
2444         tmp_manf = chip->read_byte(mtd);
2445         tmp_id = chip->read_byte(mtd);
2446
2447         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2448                 printk(KERN_INFO "%s: second ID read did not match "
2449                        "%02x,%02x against %02x,%02x\n", __func__,
2450                        *maf_id, dev_id, tmp_manf, tmp_id);
2451                 return ERR_PTR(-ENODEV);
2452         }
2453
2454         /* Lookup the flash id */
2455         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2456                 if (dev_id == nand_flash_ids[i].id) {
2457                         type =  &nand_flash_ids[i];
2458                         break;
2459                 }
2460         }
2461
2462         if (!type)
2463                 return ERR_PTR(-ENODEV);
2464
2465         if (!mtd->name)
2466                 mtd->name = type->name;
2467
2468         chip->chipsize = (uint64_t)type->chipsize << 20;
2469
2470         /* Newer devices have all the information in additional id bytes */
2471         if (!type->pagesize) {
2472                 int extid;
2473                 /* The 3rd id byte holds MLC / multichip data */
2474                 chip->cellinfo = chip->read_byte(mtd);
2475                 /* The 4th id byte is the important one */
2476                 extid = chip->read_byte(mtd);
2477                 /* Calc pagesize */
2478                 mtd->writesize = 1024 << (extid & 0x3);
2479                 extid >>= 2;
2480                 /* Calc oobsize */
2481                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2482                 extid >>= 2;
2483                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2484                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2485                 extid >>= 2;
2486                 /* Get buswidth information */
2487                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2488
2489         } else {
2490                 /*
2491                  * Old devices have chip data hardcoded in the device id table
2492                  */
2493                 mtd->erasesize = type->erasesize;
2494                 mtd->writesize = type->pagesize;
2495                 mtd->oobsize = mtd->writesize / 32;
2496                 busw = type->options & NAND_BUSWIDTH_16;
2497         }
2498
2499         /* Try to identify manufacturer */
2500         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2501                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2502                         break;
2503         }
2504
2505         /*
2506          * Check, if buswidth is correct. Hardware drivers should set
2507          * chip correct !
2508          */
2509         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2510                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2511                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2512                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2513                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2514                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2515                        busw ? 16 : 8);
2516                 return ERR_PTR(-EINVAL);
2517         }
2518
2519         /* Calculate the address shift from the page size */
2520         chip->page_shift = ffs(mtd->writesize) - 1;
2521         /* Convert chipsize to number of pages per chip -1. */
2522         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2523
2524         chip->bbt_erase_shift = chip->phys_erase_shift =
2525                 ffs(mtd->erasesize) - 1;
2526         if (chip->chipsize & 0xffffffff)
2527                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2528         else
2529                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
2530
2531         /* Set the bad block position */
2532         chip->badblockpos = mtd->writesize > 512 ?
2533                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2534
2535         /* Get chip options, preserve non chip based options */
2536         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2537         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2538
2539         /*
2540          * Set chip as a default. Board drivers can override it, if necessary
2541          */
2542         chip->options |= NAND_NO_AUTOINCR;
2543
2544         /* Check if chip is a not a samsung device. Do not clear the
2545          * options for chips which are not having an extended id.
2546          */
2547         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2548                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2549
2550         /* Check for AND chips with 4 page planes */
2551         if (chip->options & NAND_4PAGE_ARRAY)
2552                 chip->erase_cmd = multi_erase_cmd;
2553         else
2554                 chip->erase_cmd = single_erase_cmd;
2555
2556         /* Do not replace user supplied command function ! */
2557         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2558                 chip->cmdfunc = nand_command_lp;
2559
2560         printk(KERN_INFO "NAND device: Manufacturer ID:"
2561                " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2562                nand_manuf_ids[maf_idx].name, type->name);
2563
2564         return type;
2565 }
2566
2567 /**
2568  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2569  * @mtd:             MTD device structure
2570  * @maxchips:        Number of chips to scan for
2571  *
2572  * This is the first phase of the normal nand_scan() function. It
2573  * reads the flash ID and sets up MTD fields accordingly.
2574  *
2575  * The mtd->owner field must be set to the module of the caller.
2576  */
2577 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2578 {
2579         int i, busw, nand_maf_id;
2580         struct nand_chip *chip = mtd->priv;
2581         struct nand_flash_dev *type;
2582
2583         /* Get buswidth to select the correct functions */
2584         busw = chip->options & NAND_BUSWIDTH_16;
2585         /* Set the default functions */
2586         nand_set_defaults(chip, busw);
2587
2588         /* Read the flash type */
2589         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2590
2591         if (IS_ERR(type)) {
2592                 printk(KERN_WARNING "No NAND device found!!!\n");
2593                 chip->select_chip(mtd, -1);
2594                 return PTR_ERR(type);
2595         }
2596
2597         /* Check for a chip array */
2598         for (i = 1; i < maxchips; i++) {
2599                 chip->select_chip(mtd, i);
2600                 /* See comment in nand_get_flash_type for reset */
2601                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2602                 /* Send the command for reading device ID */
2603                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2604                 /* Read manufacturer and device IDs */
2605                 if (nand_maf_id != chip->read_byte(mtd) ||
2606                     type->id != chip->read_byte(mtd))
2607                         break;
2608         }
2609         if (i > 1)
2610                 printk(KERN_INFO "%d NAND chips detected\n", i);
2611
2612         /* Store the number of chips and calc total size for mtd */
2613         chip->numchips = i;
2614         mtd->size = i * chip->chipsize;
2615
2616         return 0;
2617 }
2618
2619
2620 /**
2621  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2622  * @mtd:            MTD device structure
2623  *
2624  * This is the second phase of the normal nand_scan() function. It
2625  * fills out all the uninitialized function pointers with the defaults
2626  * and scans for a bad block table if appropriate.
2627  */
2628 int nand_scan_tail(struct mtd_info *mtd)
2629 {
2630         int i;
2631         struct nand_chip *chip = mtd->priv;
2632
2633         if (!(chip->options & NAND_OWN_BUFFERS))
2634                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2635         if (!chip->buffers)
2636                 return -ENOMEM;
2637
2638         /* Set the internal oob buffer location, just after the page data */
2639         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2640
2641         /*
2642          * If no default placement scheme is given, select an appropriate one
2643          */
2644         if (!chip->ecc.layout) {
2645                 switch (mtd->oobsize) {
2646                 case 8:
2647                         chip->ecc.layout = &nand_oob_8;
2648                         break;
2649                 case 16:
2650                         chip->ecc.layout = &nand_oob_16;
2651                         break;
2652                 case 64:
2653                         chip->ecc.layout = &nand_oob_64;
2654                         break;
2655                 case 128:
2656                         chip->ecc.layout = &nand_oob_128;
2657                         break;
2658                 default:
2659                         printk(KERN_WARNING "No oob scheme defined for "
2660                                "oobsize %d\n", mtd->oobsize);
2661                         BUG();
2662                 }
2663         }
2664
2665         if (!chip->write_page)
2666                 chip->write_page = nand_write_page;
2667
2668         /*
2669          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2670          * selected and we have 256 byte pagesize fallback to software ECC
2671          */
2672
2673         switch (chip->ecc.mode) {
2674         case NAND_ECC_HW:
2675                 /* Use standard hwecc read page function ? */
2676                 if (!chip->ecc.read_page)
2677                         chip->ecc.read_page = nand_read_page_hwecc;
2678                 if (!chip->ecc.write_page)
2679                         chip->ecc.write_page = nand_write_page_hwecc;
2680                 if (!chip->ecc.read_page_raw)
2681                         chip->ecc.read_page_raw = nand_read_page_raw;
2682                 if (!chip->ecc.write_page_raw)
2683                         chip->ecc.write_page_raw = nand_write_page_raw;
2684                 if (!chip->ecc.read_oob)
2685                         chip->ecc.read_oob = nand_read_oob_std;
2686                 if (!chip->ecc.write_oob)
2687                         chip->ecc.write_oob = nand_write_oob_std;
2688
2689         case NAND_ECC_HW_SYNDROME:
2690                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2691                      !chip->ecc.hwctl) &&
2692                     (!chip->ecc.read_page ||
2693                      chip->ecc.read_page == nand_read_page_hwecc ||
2694                      !chip->ecc.write_page ||
2695                      chip->ecc.write_page == nand_write_page_hwecc)) {
2696                         printk(KERN_WARNING "No ECC functions supplied, "
2697                                "Hardware ECC not possible\n");
2698                         BUG();
2699                 }
2700                 /* Use standard syndrome read/write page function ? */
2701                 if (!chip->ecc.read_page)
2702                         chip->ecc.read_page = nand_read_page_syndrome;
2703                 if (!chip->ecc.write_page)
2704                         chip->ecc.write_page = nand_write_page_syndrome;
2705                 if (!chip->ecc.read_page_raw)
2706                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2707                 if (!chip->ecc.write_page_raw)
2708                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2709                 if (!chip->ecc.read_oob)
2710                         chip->ecc.read_oob = nand_read_oob_syndrome;
2711                 if (!chip->ecc.write_oob)
2712                         chip->ecc.write_oob = nand_write_oob_syndrome;
2713
2714                 if (mtd->writesize >= chip->ecc.size)
2715                         break;
2716                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2717                        "%d byte page size, fallback to SW ECC\n",
2718                        chip->ecc.size, mtd->writesize);
2719                 chip->ecc.mode = NAND_ECC_SOFT;
2720
2721         case NAND_ECC_SOFT:
2722                 chip->ecc.calculate = nand_calculate_ecc;
2723                 chip->ecc.correct = nand_correct_data;
2724                 chip->ecc.read_page = nand_read_page_swecc;
2725                 chip->ecc.read_subpage = nand_read_subpage;
2726                 chip->ecc.write_page = nand_write_page_swecc;
2727                 chip->ecc.read_page_raw = nand_read_page_raw;
2728                 chip->ecc.write_page_raw = nand_write_page_raw;
2729                 chip->ecc.read_oob = nand_read_oob_std;
2730                 chip->ecc.write_oob = nand_write_oob_std;
2731                 chip->ecc.size = 256;
2732                 chip->ecc.bytes = 3;
2733                 break;
2734
2735         case NAND_ECC_NONE:
2736                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2737                        "This is not recommended !!\n");
2738                 chip->ecc.read_page = nand_read_page_raw;
2739                 chip->ecc.write_page = nand_write_page_raw;
2740                 chip->ecc.read_oob = nand_read_oob_std;
2741                 chip->ecc.read_page_raw = nand_read_page_raw;
2742                 chip->ecc.write_page_raw = nand_write_page_raw;
2743                 chip->ecc.write_oob = nand_write_oob_std;
2744                 chip->ecc.size = mtd->writesize;
2745                 chip->ecc.bytes = 0;
2746                 break;
2747
2748         default:
2749                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2750                        chip->ecc.mode);
2751                 BUG();
2752         }
2753
2754         /*
2755          * The number of bytes available for a client to place data into
2756          * the out of band area
2757          */
2758         chip->ecc.layout->oobavail = 0;
2759         for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2760                 chip->ecc.layout->oobavail +=
2761                         chip->ecc.layout->oobfree[i].length;
2762         mtd->oobavail = chip->ecc.layout->oobavail;
2763
2764         /*
2765          * Set the number of read / write steps for one page depending on ECC
2766          * mode
2767          */
2768         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2769         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2770                 printk(KERN_WARNING "Invalid ecc parameters\n");
2771                 BUG();
2772         }
2773         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2774
2775         /*
2776          * Allow subpage writes up to ecc.steps. Not possible for MLC
2777          * FLASH.
2778          */
2779         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2780             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2781                 switch(chip->ecc.steps) {
2782                 case 2:
2783                         mtd->subpage_sft = 1;
2784                         break;
2785                 case 4:
2786                 case 8:
2787                 case 16:
2788                         mtd->subpage_sft = 2;
2789                         break;
2790                 }
2791         }
2792         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2793
2794         /* Initialize state */
2795         chip->state = FL_READY;
2796
2797         /* De-select the device */
2798         chip->select_chip(mtd, -1);
2799
2800         /* Invalidate the pagebuffer reference */
2801         chip->pagebuf = -1;
2802
2803         /* Fill in remaining MTD driver data */
2804         mtd->type = MTD_NANDFLASH;
2805         mtd->flags = MTD_CAP_NANDFLASH;
2806         mtd->erase = nand_erase;
2807         mtd->point = NULL;
2808         mtd->unpoint = NULL;
2809         mtd->read = nand_read;
2810         mtd->write = nand_write;
2811         mtd->read_oob = nand_read_oob;
2812         mtd->write_oob = nand_write_oob;
2813         mtd->sync = nand_sync;
2814         mtd->lock = NULL;
2815         mtd->unlock = NULL;
2816         mtd->suspend = nand_suspend;
2817         mtd->resume = nand_resume;
2818         mtd->block_isbad = nand_block_isbad;
2819         mtd->block_markbad = nand_block_markbad;
2820
2821         /* propagate ecc.layout to mtd_info */
2822         mtd->ecclayout = chip->ecc.layout;
2823
2824         /* Check, if we should skip the bad block table scan */
2825         if (chip->options & NAND_SKIP_BBTSCAN)
2826                 return 0;
2827
2828         /* Build bad block table */
2829         return chip->scan_bbt(mtd);
2830 }
2831
2832 /* is_module_text_address() isn't exported, and it's mostly a pointless
2833    test if this is a module _anyway_ -- they'd have to try _really_ hard
2834    to call us from in-kernel code if the core NAND support is modular. */
2835 #ifdef MODULE
2836 #define caller_is_module() (1)
2837 #else
2838 #define caller_is_module() \
2839         is_module_text_address((unsigned long)__builtin_return_address(0))
2840 #endif
2841
2842 /**
2843  * nand_scan - [NAND Interface] Scan for the NAND device
2844  * @mtd:        MTD device structure
2845  * @maxchips:   Number of chips to scan for
2846  *
2847  * This fills out all the uninitialized function pointers
2848  * with the defaults.
2849  * The flash ID is read and the mtd/chip structures are
2850  * filled with the appropriate values.
2851  * The mtd->owner field must be set to the module of the caller
2852  *
2853  */
2854 int nand_scan(struct mtd_info *mtd, int maxchips)
2855 {
2856         int ret;
2857
2858         /* Many callers got this wrong, so check for it for a while... */
2859         if (!mtd->owner && caller_is_module()) {
2860                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2861                 BUG();
2862         }
2863
2864         ret = nand_scan_ident(mtd, maxchips);
2865         if (!ret)
2866                 ret = nand_scan_tail(mtd);
2867         return ret;
2868 }
2869
2870 /**
2871  * nand_release - [NAND Interface] Free resources held by the NAND device
2872  * @mtd:        MTD device structure
2873 */
2874 void nand_release(struct mtd_info *mtd)
2875 {
2876         struct nand_chip *chip = mtd->priv;
2877
2878 #ifdef CONFIG_MTD_PARTITIONS
2879         /* Deregister partitions */
2880         del_mtd_partitions(mtd);
2881 #endif
2882         /* Deregister the device */
2883         del_mtd_device(mtd);
2884
2885         /* Free bad block table memory */
2886         kfree(chip->bbt);
2887         if (!(chip->options & NAND_OWN_BUFFERS))
2888                 kfree(chip->buffers);
2889 }
2890
2891 EXPORT_SYMBOL_GPL(nand_scan);
2892 EXPORT_SYMBOL_GPL(nand_scan_ident);
2893 EXPORT_SYMBOL_GPL(nand_scan_tail);
2894 EXPORT_SYMBOL_GPL(nand_release);
2895
2896 static int __init nand_base_init(void)
2897 {
2898         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2899         return 0;
2900 }
2901
2902 static void __exit nand_base_exit(void)
2903 {
2904         led_trigger_unregister_simple(nand_led_trigger);
2905 }
2906
2907 module_init(nand_base_init);
2908 module_exit(nand_base_exit);
2909
2910 MODULE_LICENSE("GPL");
2911 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2912 MODULE_DESCRIPTION("Generic NAND flash driver code");