drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/compatmac.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <asm/io.h>
  50
  51 #ifdef CONFIG_MTD_PARTITIONS
  52 #include <linux/mtd/partitions.h>
  53 #endif
  54
  55 /* Define default oob placement schemes for large and small page devices */
  56 static struct nand_ecclayout nand_oob_8 = {
  57         .eccbytes = 3,
  58         .eccpos = {0, 1, 2},
  59         .oobfree = {
  60                 {.offset = 3,
  61                  .length = 2},
  62                 {.offset = 6,
  63                  .length = 2}}
  64 };
  65
  66 static struct nand_ecclayout nand_oob_16 = {
  67         .eccbytes = 6,
  68         .eccpos = {0, 1, 2, 3, 6, 7},
  69         .oobfree = {
  70                 {.offset = 8,
  71                  . length = 8}}
  72 };
  73
  74 static struct nand_ecclayout nand_oob_64 = {
  75         .eccbytes = 24,
  76         .eccpos = {
  77                    40, 41, 42, 43, 44, 45, 46, 47,
  78                    48, 49, 50, 51, 52, 53, 54, 55,
  79                    56, 57, 58, 59, 60, 61, 62, 63},
  80         .oobfree = {
  81                 {.offset = 2,
  82                  .length = 38}}
  83 };
  84
  85 static struct nand_ecclayout nand_oob_128 = {
  86         .eccbytes = 48,
  87         .eccpos = {
  88                    80, 81, 82, 83, 84, 85, 86, 87,
  89                    88, 89, 90, 91, 92, 93, 94, 95,
  90                    96, 97, 98, 99, 100, 101, 102, 103,
  91                    104, 105, 106, 107, 108, 109, 110, 111,
  92                    112, 113, 114, 115, 116, 117, 118, 119,
  93                    120, 121, 122, 123, 124, 125, 126, 127},
  94         .oobfree = {
  95                 {.offset = 2,
  96                  .length = 78}}
  97 };
  98
  99 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 100                            int new_state);
 101
 102 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 103                              struct mtd_oob_ops *ops);
 104
 105 /*
 106  * For devices which display every fart in the system on a separate LED. Is
 107  * compiled away when LED support is disabled.
 108  */
 109 DEFINE_LED_TRIGGER(nand_led_trigger);
 110
 111 /**
 112  * nand_release_device - [GENERIC] release chip
 113  * @mtd:        MTD device structure
 114  *
 115  * Deselect, release chip lock and wake up anyone waiting on the device
 116  */
 117 static void nand_release_device(struct mtd_info *mtd)
 118 {
 119         struct nand_chip *chip = mtd->priv;
 120
 121         /* De-select the NAND device */
 122         chip->select_chip(mtd, -1);
 123
 124         /* Release the controller and the chip */
 125         spin_lock(&chip->controller->lock);
 126         chip->controller->active = NULL;
 127         chip->state = FL_READY;
 128         wake_up(&chip->controller->wq);
 129         spin_unlock(&chip->controller->lock);
 130 }
 131
 132 /**
 133  * nand_read_byte - [DEFAULT] read one byte from the chip
 134  * @mtd:        MTD device structure
 135  *
 136  * Default read function for 8bit buswith
 137  */
 138 static uint8_t nand_read_byte(struct mtd_info *mtd)
 139 {
 140         struct nand_chip *chip = mtd->priv;
 141         return readb(chip->IO_ADDR_R);
 142 }
 143
 144 /**
 145  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 146  * @mtd:        MTD device structure
 147  *
 148  * Default read function for 16bit buswith with
 149  * endianess conversion
 150  */
 151 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 152 {
 153         struct nand_chip *chip = mtd->priv;
 154         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 155 }
 156
 157 /**
 158  * nand_read_word - [DEFAULT] read one word from the chip
 159  * @mtd:        MTD device structure
 160  *
 161  * Default read function for 16bit buswith without
 162  * endianess conversion
 163  */
 164 static u16 nand_read_word(struct mtd_info *mtd)
 165 {
 166         struct nand_chip *chip = mtd->priv;
 167         return readw(chip->IO_ADDR_R);
 168 }
 169
 170 /**
 171  * nand_select_chip - [DEFAULT] control CE line
 172  * @mtd:        MTD device structure
 173  * @chipnr:     chipnumber to select, -1 for deselect
 174  *
 175  * Default select function for 1 chip devices.
 176  */
 177 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 178 {
 179         struct nand_chip *chip = mtd->priv;
 180
 181         switch (chipnr) {
 182         case -1:
 183                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 184                 break;
 185         case 0:
 186                 break;
 187
 188         default:
 189                 BUG();
 190         }
 191 }
 192
 193 /**
 194  * nand_write_buf - [DEFAULT] write buffer to chip
 195  * @mtd:        MTD device structure
 196  * @buf:        data buffer
 197  * @len:        number of bytes to write
 198  *
 199  * Default write function for 8bit buswith
 200  */
 201 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 202 {
 203         int i;
 204         struct nand_chip *chip = mtd->priv;
 205
 206         for (i = 0; i < len; i++)
 207                 writeb(buf[i], chip->IO_ADDR_W);
 208 }
 209
 210 /**
 211  * nand_read_buf - [DEFAULT] read chip data into buffer
 212  * @mtd:        MTD device structure
 213  * @buf:        buffer to store date
 214  * @len:        number of bytes to read
 215  *
 216  * Default read function for 8bit buswith
 217  */
 218 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 219 {
 220         int i;
 221         struct nand_chip *chip = mtd->priv;
 222
 223         for (i = 0; i < len; i++)
 224                 buf[i] = readb(chip->IO_ADDR_R);
 225 }
 226
 227 /**
 228  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 229  * @mtd:        MTD device structure
 230  * @buf:        buffer containing the data to compare
 231  * @len:        number of bytes to compare
 232  *
 233  * Default verify function for 8bit buswith
 234  */
 235 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 236 {
 237         int i;
 238         struct nand_chip *chip = mtd->priv;
 239
 240         for (i = 0; i < len; i++)
 241                 if (buf[i] != readb(chip->IO_ADDR_R))
 242                         return -EFAULT;
 243         return 0;
 244 }
 245
 246 /**
 247  * nand_write_buf16 - [DEFAULT] write buffer to chip
 248  * @mtd:        MTD device structure
 249  * @buf:        data buffer
 250  * @len:        number of bytes to write
 251  *
 252  * Default write function for 16bit buswith
 253  */
 254 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 255 {
 256         int i;
 257         struct nand_chip *chip = mtd->priv;
 258         u16 *p = (u16 *) buf;
 259         len >>= 1;
 260
 261         for (i = 0; i < len; i++)
 262                 writew(p[i], chip->IO_ADDR_W);
 263
 264 }
 265
 266 /**
 267  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 268  * @mtd:        MTD device structure
 269  * @buf:        buffer to store date
 270  * @len:        number of bytes to read
 271  *
 272  * Default read function for 16bit buswith
 273  */
 274 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 275 {
 276         int i;
 277         struct nand_chip *chip = mtd->priv;
 278         u16 *p = (u16 *) buf;
 279         len >>= 1;
 280
 281         for (i = 0; i < len; i++)
 282                 p[i] = readw(chip->IO_ADDR_R);
 283 }
 284
 285 /**
 286  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 287  * @mtd:        MTD device structure
 288  * @buf:        buffer containing the data to compare
 289  * @len:        number of bytes to compare
 290  *
 291  * Default verify function for 16bit buswith
 292  */
 293 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 294 {
 295         int i;
 296         struct nand_chip *chip = mtd->priv;
 297         u16 *p = (u16 *) buf;
 298         len >>= 1;
 299
 300         for (i = 0; i < len; i++)
 301                 if (p[i] != readw(chip->IO_ADDR_R))
 302                         return -EFAULT;
 303
 304         return 0;
 305 }
 306
 307 /**
 308  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 309  * @mtd:        MTD device structure
 310  * @ofs:        offset from device start
 311  * @getchip:    0, if the chip is already selected
 312  *
 313  * Check, if the block is bad.
 314  */
 315 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 316 {
 317         int page, chipnr, res = 0;
 318         struct nand_chip *chip = mtd->priv;
 319         u16 bad;
 320
 321         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 322
 323         if (getchip) {
 324                 chipnr = (int)(ofs >> chip->chip_shift);
 325
 326                 nand_get_device(chip, mtd, FL_READING);
 327
 328                 /* Select the NAND device */
 329                 chip->select_chip(mtd, chipnr);
 330         }
 331
 332         if (chip->options & NAND_BUSWIDTH_16) {
 333                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 334                               page);
 335                 bad = cpu_to_le16(chip->read_word(mtd));
 336                 if (chip->badblockpos & 0x1)
 337                         bad >>= 8;
 338                 if ((bad & 0xFF) != 0xff)
 339                         res = 1;
 340         } else {
 341                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 342                 if (chip->read_byte(mtd) != 0xff)
 343                         res = 1;
 344         }
 345
 346         if (getchip)
 347                 nand_release_device(mtd);
 348
 349         return res;
 350 }
 351
 352 /**
 353  * nand_default_block_markbad - [DEFAULT] mark a block bad
 354  * @mtd:        MTD device structure
 355  * @ofs:        offset from device start
 356  *
 357  * This is the default implementation, which can be overridden by
 358  * a hardware specific driver.
 359 */
 360 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 361 {
 362         struct nand_chip *chip = mtd->priv;
 363         uint8_t buf[2] = { 0, 0 };
 364         int block, ret;
 365
 366         /* Get block number */
 367         block = (int)(ofs >> chip->bbt_erase_shift);
 368         if (chip->bbt)
 369                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 370
 371         /* Do we have a flash based bad block table ? */
 372         if (chip->options & NAND_USE_FLASH_BBT)
 373                 ret = nand_update_bbt(mtd, ofs);
 374         else {
 375                 /* We write two bytes, so we dont have to mess with 16 bit
 376                  * access
 377                  */
 378                 nand_get_device(chip, mtd, FL_WRITING);
 379                 ofs += mtd->oobsize;
 380                 chip->ops.len = chip->ops.ooblen = 2;
 381                 chip->ops.datbuf = NULL;
 382                 chip->ops.oobbuf = buf;
 383                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 384
 385                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 386                 nand_release_device(mtd);
 387         }
 388         if (!ret)
 389                 mtd->ecc_stats.badblocks++;
 390
 391         return ret;
 392 }
 393
 394 /**
 395  * nand_check_wp - [GENERIC] check if the chip is write protected
 396  * @mtd:        MTD device structure
 397  * Check, if the device is write protected
 398  *
 399  * The function expects, that the device is already selected
 400  */
 401 static int nand_check_wp(struct mtd_info *mtd)
 402 {
 403         struct nand_chip *chip = mtd->priv;
 404         /* Check the WP bit */
 405         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 406         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 407 }
 408
 409 /**
 410  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 411  * @mtd:        MTD device structure
 412  * @ofs:        offset from device start
 413  * @getchip:    0, if the chip is already selected
 414  * @allowbbt:   1, if its allowed to access the bbt area
 415  *
 416  * Check, if the block is bad. Either by reading the bad block table or
 417  * calling of the scan function.
 418  */
 419 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 420                                int allowbbt)
 421 {
 422         struct nand_chip *chip = mtd->priv;
 423
 424         if (!chip->bbt)
 425                 return chip->block_bad(mtd, ofs, getchip);
 426
 427         /* Return info from the table */
 428         return nand_isbad_bbt(mtd, ofs, allowbbt);
 429 }
 430
 431 /*
 432  * Wait for the ready pin, after a command
 433  * The timeout is catched later.
 434  */
 435 void nand_wait_ready(struct mtd_info *mtd)
 436 {
 437         struct nand_chip *chip = mtd->priv;
 438         unsigned long timeo = jiffies + 2;
 439
 440         led_trigger_event(nand_led_trigger, LED_FULL);
 441         /* wait until command is processed or timeout occures */
 442         do {
 443                 if (chip->dev_ready(mtd))
 444                         break;
 445                 touch_softlockup_watchdog();
 446         } while (time_before(jiffies, timeo));
 447         led_trigger_event(nand_led_trigger, LED_OFF);
 448 }
 449 EXPORT_SYMBOL_GPL(nand_wait_ready);
 450
 451 /**
 452  * nand_command - [DEFAULT] Send command to NAND device
 453  * @mtd:        MTD device structure
 454  * @command:    the command to be sent
 455  * @column:     the column address for this command, -1 if none
 456  * @page_addr:  the page address for this command, -1 if none
 457  *
 458  * Send command to NAND device. This function is used for small page
 459  * devices (256/512 Bytes per page)
 460  */
 461 static void nand_command(struct mtd_info *mtd, unsigned int command,
 462                          int column, int page_addr)
 463 {
 464         register struct nand_chip *chip = mtd->priv;
 465         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 466
 467         /*
 468          * Write out the command to the device.
 469          */
 470         if (command == NAND_CMD_SEQIN) {
 471                 int readcmd;
 472
 473                 if (column >= mtd->writesize) {
 474                         /* OOB area */
 475                         column -= mtd->writesize;
 476                         readcmd = NAND_CMD_READOOB;
 477                 } else if (column < 256) {
 478                         /* First 256 bytes --> READ0 */
 479                         readcmd = NAND_CMD_READ0;
 480                 } else {
 481                         column -= 256;
 482                         readcmd = NAND_CMD_READ1;
 483                 }
 484                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 485                 ctrl &= ~NAND_CTRL_CHANGE;
 486         }
 487         chip->cmd_ctrl(mtd, command, ctrl);
 488
 489         /*
 490          * Address cycle, when necessary
 491          */
 492         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 493         /* Serially input address */
 494         if (column != -1) {
 495                 /* Adjust columns for 16 bit buswidth */
 496                 if (chip->options & NAND_BUSWIDTH_16)
 497                         column >>= 1;
 498                 chip->cmd_ctrl(mtd, column, ctrl);
 499                 ctrl &= ~NAND_CTRL_CHANGE;
 500         }
 501         if (page_addr != -1) {
 502                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 503                 ctrl &= ~NAND_CTRL_CHANGE;
 504                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 505                 /* One more address cycle for devices > 32MiB */
 506                 if (chip->chipsize > (32 << 20))
 507                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 508         }
 509         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 510
 511         /*
 512          * program and erase have their own busy handlers
 513          * status and sequential in needs no delay
 514          */
 515         switch (command) {
 516
 517         case NAND_CMD_PAGEPROG:
 518         case NAND_CMD_ERASE1:
 519         case NAND_CMD_ERASE2:
 520         case NAND_CMD_SEQIN:
 521         case NAND_CMD_STATUS:
 522                 return;
 523
 524         case NAND_CMD_RESET:
 525                 if (chip->dev_ready)
 526                         break;
 527                 udelay(chip->chip_delay);
 528                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 529                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 530                 chip->cmd_ctrl(mtd,
 531                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 532                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 533                 return;
 534
 535                 /* This applies to read commands */
 536         default:
 537                 /*
 538                  * If we don't have access to the busy pin, we apply the given
 539                  * command delay
 540                  */
 541                 if (!chip->dev_ready) {
 542                         udelay(chip->chip_delay);
 543                         return;
 544                 }
 545         }
 546         /* Apply this short delay always to ensure that we do wait tWB in
 547          * any case on any machine. */
 548         ndelay(100);
 549
 550         nand_wait_ready(mtd);
 551 }
 552
 553 /**
 554  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 555  * @mtd:        MTD device structure
 556  * @command:    the command to be sent
 557  * @column:     the column address for this command, -1 if none
 558  * @page_addr:  the page address for this command, -1 if none
 559  *
 560  * Send command to NAND device. This is the version for the new large page
 561  * devices We dont have the separate regions as we have in the small page
 562  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 563  */
 564 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 565                             int column, int page_addr)
 566 {
 567         register struct nand_chip *chip = mtd->priv;
 568
 569         /* Emulate NAND_CMD_READOOB */
 570         if (command == NAND_CMD_READOOB) {
 571                 column += mtd->writesize;
 572                 command = NAND_CMD_READ0;
 573         }
 574
 575         /* Command latch cycle */
 576         chip->cmd_ctrl(mtd, command & 0xff,
 577                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 578
 579         if (column != -1 || page_addr != -1) {
 580                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 581
 582                 /* Serially input address */
 583                 if (column != -1) {
 584                         /* Adjust columns for 16 bit buswidth */
 585                         if (chip->options & NAND_BUSWIDTH_16)
 586                                 column >>= 1;
 587                         chip->cmd_ctrl(mtd, column, ctrl);
 588                         ctrl &= ~NAND_CTRL_CHANGE;
 589                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 590                 }
 591                 if (page_addr != -1) {
 592                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 593                         chip->cmd_ctrl(mtd, page_addr >> 8,
 594                                        NAND_NCE | NAND_ALE);
 595                         /* One more address cycle for devices > 128MiB */
 596                         if (chip->chipsize > (128 << 20))
 597                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 598                                                NAND_NCE | NAND_ALE);
 599                 }
 600         }
 601         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 602
 603         /*
 604          * program and erase have their own busy handlers
 605          * status, sequential in, and deplete1 need no delay
 606          */
 607         switch (command) {
 608
 609         case NAND_CMD_CACHEDPROG:
 610         case NAND_CMD_PAGEPROG:
 611         case NAND_CMD_ERASE1:
 612         case NAND_CMD_ERASE2:
 613         case NAND_CMD_SEQIN:
 614         case NAND_CMD_RNDIN:
 615         case NAND_CMD_STATUS:
 616         case NAND_CMD_DEPLETE1:
 617                 return;
 618
 619                 /*
 620                  * read error status commands require only a short delay
 621                  */
 622         case NAND_CMD_STATUS_ERROR:
 623         case NAND_CMD_STATUS_ERROR0:
 624         case NAND_CMD_STATUS_ERROR1:
 625         case NAND_CMD_STATUS_ERROR2:
 626         case NAND_CMD_STATUS_ERROR3:
 627                 udelay(chip->chip_delay);
 628                 return;
 629
 630         case NAND_CMD_RESET:
 631                 if (chip->dev_ready)
 632                         break;
 633                 udelay(chip->chip_delay);
 634                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 635                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 636                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 637                                NAND_NCE | NAND_CTRL_CHANGE);
 638                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 639                 return;
 640
 641         case NAND_CMD_RNDOUT:
 642                 /* No ready / busy check necessary */
 643                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 644                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 645                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 646                                NAND_NCE | NAND_CTRL_CHANGE);
 647                 return;
 648
 649         case NAND_CMD_READ0:
 650                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 651                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 652                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 653                                NAND_NCE | NAND_CTRL_CHANGE);
 654
 655                 /* This applies to read commands */
 656         default:
 657                 /*
 658                  * If we don't have access to the busy pin, we apply the given
 659                  * command delay
 660                  */
 661                 if (!chip->dev_ready) {
 662                         udelay(chip->chip_delay);
 663                         return;
 664                 }
 665         }
 666
 667         /* Apply this short delay always to ensure that we do wait tWB in
 668          * any case on any machine. */
 669         ndelay(100);
 670
 671         nand_wait_ready(mtd);
 672 }
 673
 674 /**
 675  * nand_get_device - [GENERIC] Get chip for selected access
 676  * @chip:       the nand chip descriptor
 677  * @mtd:        MTD device structure
 678  * @new_state:  the state which is requested
 679  *
 680  * Get the device and lock it for exclusive access
 681  */
 682 static int
 683 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 684 {
 685         spinlock_t *lock = &chip->controller->lock;
 686         wait_queue_head_t *wq = &chip->controller->wq;
 687         DECLARE_WAITQUEUE(wait, current);
 688  retry:
 689         spin_lock(lock);
 690
 691         /* Hardware controller shared among independent devices */
 692         if (!chip->controller->active)
 693                 chip->controller->active = chip;
 694
 695         if (chip->controller->active == chip && chip->state == FL_READY) {
 696                 chip->state = new_state;
 697                 spin_unlock(lock);
 698                 return 0;
 699         }
 700         if (new_state == FL_PM_SUSPENDED) {
 701                 spin_unlock(lock);
 702                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 703         }
 704         set_current_state(TASK_UNINTERRUPTIBLE);
 705         add_wait_queue(wq, &wait);
 706         spin_unlock(lock);
 707         schedule();
 708         remove_wait_queue(wq, &wait);
 709         goto retry;
 710 }
 711
 712 /**
 713  * nand_wait - [DEFAULT]  wait until the command is done
 714  * @mtd:        MTD device structure
 715  * @chip:       NAND chip structure
 716  *
 717  * Wait for command done. This applies to erase and program only
 718  * Erase can take up to 400ms and program up to 20ms according to
 719  * general NAND and SmartMedia specs
 720  */
 721 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 722 {
 723
 724         unsigned long timeo = jiffies;
 725         int status, state = chip->state;
 726
 727         if (state == FL_ERASING)
 728                 timeo += (HZ * 400) / 1000;
 729         else
 730                 timeo += (HZ * 20) / 1000;
 731
 732         led_trigger_event(nand_led_trigger, LED_FULL);
 733
 734         /* Apply this short delay always to ensure that we do wait tWB in
 735          * any case on any machine. */
 736         ndelay(100);
 737
 738         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 739                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 740         else
 741                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 742
 743         while (time_before(jiffies, timeo)) {
 744                 if (chip->dev_ready) {
 745                         if (chip->dev_ready(mtd))
 746                                 break;
 747                 } else {
 748                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 749                                 break;
 750                 }
 751                 cond_resched();
 752         }
 753         led_trigger_event(nand_led_trigger, LED_OFF);
 754
 755         status = (int)chip->read_byte(mtd);
 756         return status;
 757 }
 758
 759 /**
 760  * nand_read_page_raw - [Intern] read raw page data without ecc
 761  * @mtd:        mtd info structure
 762  * @chip:       nand chip info structure
 763  * @buf:        buffer to store read data
 764  *
 765  * Not for syndrome calculating ecc controllers, which use a special oob layout
 766  */
 767 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 768                               uint8_t *buf, int page)
 769 {
 770         chip->read_buf(mtd, buf, mtd->writesize);
 771         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 772         return 0;
 773 }
 774
 775 /**
 776  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
 777  * @mtd:        mtd info structure
 778  * @chip:       nand chip info structure
 779  * @buf:        buffer to store read data
 780  *
 781  * We need a special oob layout and handling even when OOB isn't used.
 782  */
 783 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 784                               uint8_t *buf, int page)
 785 {
 786         int eccsize = chip->ecc.size;
 787         int eccbytes = chip->ecc.bytes;
 788         uint8_t *oob = chip->oob_poi;
 789         int steps, size;
 790
 791         for (steps = chip->ecc.steps; steps > 0; steps--) {
 792                 chip->read_buf(mtd, buf, eccsize);
 793                 buf += eccsize;
 794
 795                 if (chip->ecc.prepad) {
 796                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 797                         oob += chip->ecc.prepad;
 798                 }
 799
 800                 chip->read_buf(mtd, oob, eccbytes);
 801                 oob += eccbytes;
 802
 803                 if (chip->ecc.postpad) {
 804                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 805                         oob += chip->ecc.postpad;
 806                 }
 807         }
 808
 809         size = mtd->oobsize - (oob - chip->oob_poi);
 810         if (size)
 811                 chip->read_buf(mtd, oob, size);
 812
 813         return 0;
 814 }
 815
 816 /**
 817  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 818  * @mtd:        mtd info structure
 819  * @chip:       nand chip info structure
 820  * @buf:        buffer to store read data
 821  */
 822 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 823                                 uint8_t *buf, int page)
 824 {
 825         int i, eccsize = chip->ecc.size;
 826         int eccbytes = chip->ecc.bytes;
 827         int eccsteps = chip->ecc.steps;
 828         uint8_t *p = buf;
 829         uint8_t *ecc_calc = chip->buffers->ecccalc;
 830         uint8_t *ecc_code = chip->buffers->ecccode;
 831         uint32_t *eccpos = chip->ecc.layout->eccpos;
 832
 833         chip->ecc.read_page_raw(mtd, chip, buf, page);
 834
 835         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 836                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 837
 838         for (i = 0; i < chip->ecc.total; i++)
 839                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 840
 841         eccsteps = chip->ecc.steps;
 842         p = buf;
 843
 844         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 845                 int stat;
 846
 847                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 848                 if (stat < 0)
 849                         mtd->ecc_stats.failed++;
 850                 else
 851                         mtd->ecc_stats.corrected += stat;
 852         }
 853         return 0;
 854 }
 855
 856 /**
 857  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
 858  * @mtd:        mtd info structure
 859  * @chip:       nand chip info structure
 860  * @data_offs:  offset of requested data within the page
 861  * @readlen:    data length
 862  * @bufpoi:     buffer to store read data
 863  */
 864 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 865 {
 866         int start_step, end_step, num_steps;
 867         uint32_t *eccpos = chip->ecc.layout->eccpos;
 868         uint8_t *p;
 869         int data_col_addr, i, gaps = 0;
 870         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 871         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 872
 873         /* Column address wihin the page aligned to ECC size (256bytes). */
 874         start_step = data_offs / chip->ecc.size;
 875         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 876         num_steps = end_step - start_step + 1;
 877
 878         /* Data size aligned to ECC ecc.size*/
 879         datafrag_len = num_steps * chip->ecc.size;
 880         eccfrag_len = num_steps * chip->ecc.bytes;
 881
 882         data_col_addr = start_step * chip->ecc.size;
 883         /* If we read not a page aligned data */
 884         if (data_col_addr != 0)
 885                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 886
 887         p = bufpoi + data_col_addr;
 888         chip->read_buf(mtd, p, datafrag_len);
 889
 890         /* Calculate  ECC */
 891         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 892                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 893
 894         /* The performance is faster if to position offsets
 895            according to ecc.pos. Let make sure here that
 896            there are no gaps in ecc positions */
 897         for (i = 0; i < eccfrag_len - 1; i++) {
 898                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 899                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
 900                         gaps = 1;
 901                         break;
 902                 }
 903         }
 904         if (gaps) {
 905                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 906                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 907         } else {
 908                 /* send the command to read the particular ecc bytes */
 909                 /* take care about buswidth alignment in read_buf */
 910                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
 911                 aligned_len = eccfrag_len;
 912                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
 913                         aligned_len++;
 914                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
 915                         aligned_len++;
 916
 917                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
 918                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
 919         }
 920
 921         for (i = 0; i < eccfrag_len; i++)
 922                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
 923
 924         p = bufpoi + data_col_addr;
 925         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
 926                 int stat;
 927
 928                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
 929                 if (stat == -1)
 930                         mtd->ecc_stats.failed++;
 931                 else
 932                         mtd->ecc_stats.corrected += stat;
 933         }
 934         return 0;
 935 }
 936
 937 /**
 938  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
 939  * @mtd:        mtd info structure
 940  * @chip:       nand chip info structure
 941  * @buf:        buffer to store read data
 942  *
 943  * Not for syndrome calculating ecc controllers which need a special oob layout
 944  */
 945 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 946                                 uint8_t *buf, int page)
 947 {
 948         int i, eccsize = chip->ecc.size;
 949         int eccbytes = chip->ecc.bytes;
 950         int eccsteps = chip->ecc.steps;
 951         uint8_t *p = buf;
 952         uint8_t *ecc_calc = chip->buffers->ecccalc;
 953         uint8_t *ecc_code = chip->buffers->ecccode;
 954         uint32_t *eccpos = chip->ecc.layout->eccpos;
 955
 956         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 957                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 958                 chip->read_buf(mtd, p, eccsize);
 959                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 960         }
 961         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 962
 963         for (i = 0; i < chip->ecc.total; i++)
 964                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 965
 966         eccsteps = chip->ecc.steps;
 967         p = buf;
 968
 969         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 970                 int stat;
 971
 972                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 973                 if (stat < 0)
 974                         mtd->ecc_stats.failed++;
 975                 else
 976                         mtd->ecc_stats.corrected += stat;
 977         }
 978         return 0;
 979 }
 980
 981 /**
 982  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
 983  * @mtd:        mtd info structure
 984  * @chip:       nand chip info structure
 985  * @buf:        buffer to store read data
 986  *
 987  * Hardware ECC for large page chips, require OOB to be read first.
 988  * For this ECC mode, the write_page method is re-used from ECC_HW.
 989  * These methods read/write ECC from the OOB area, unlike the
 990  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
 991  * "infix ECC" scheme and reads/writes ECC from the data area, by
 992  * overwriting the NAND manufacturer bad block markings.
 993  */
 994 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
 995         struct nand_chip *chip, uint8_t *buf, int page)
 996 {
 997         int i, eccsize = chip->ecc.size;
 998         int eccbytes = chip->ecc.bytes;
 999         int eccsteps = chip->ecc.steps;
1000         uint8_t *p = buf;
1001         uint8_t *ecc_code = chip->buffers->ecccode;
1002         uint32_t *eccpos = chip->ecc.layout->eccpos;
1003         uint8_t *ecc_calc = chip->buffers->ecccalc;
1004
1005         /* Read the OOB area first */
1006         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1007         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1008         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1009
1010         for (i = 0; i < chip->ecc.total; i++)
1011                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1012
1013         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1014                 int stat;
1015
1016                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1017                 chip->read_buf(mtd, p, eccsize);
1018                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1019
1020                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1021                 if (stat < 0)
1022                         mtd->ecc_stats.failed++;
1023                 else
1024                         mtd->ecc_stats.corrected += stat;
1025         }
1026         return 0;
1027 }
1028
1029 /**
1030  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1031  * @mtd:        mtd info structure
1032  * @chip:       nand chip info structure
1033  * @buf:        buffer to store read data
1034  *
1035  * The hw generator calculates the error syndrome automatically. Therefor
1036  * we need a special oob layout and handling.
1037  */
1038 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1039                                    uint8_t *buf, int page)
1040 {
1041         int i, eccsize = chip->ecc.size;
1042         int eccbytes = chip->ecc.bytes;
1043         int eccsteps = chip->ecc.steps;
1044         uint8_t *p = buf;
1045         uint8_t *oob = chip->oob_poi;
1046
1047         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1048                 int stat;
1049
1050                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1051                 chip->read_buf(mtd, p, eccsize);
1052
1053                 if (chip->ecc.prepad) {
1054                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1055                         oob += chip->ecc.prepad;
1056                 }
1057
1058                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1059                 chip->read_buf(mtd, oob, eccbytes);
1060                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1061
1062                 if (stat < 0)
1063                         mtd->ecc_stats.failed++;
1064                 else
1065                         mtd->ecc_stats.corrected += stat;
1066
1067                 oob += eccbytes;
1068
1069                 if (chip->ecc.postpad) {
1070                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1071                         oob += chip->ecc.postpad;
1072                 }
1073         }
1074
1075         /* Calculate remaining oob bytes */
1076         i = mtd->oobsize - (oob - chip->oob_poi);
1077         if (i)
1078                 chip->read_buf(mtd, oob, i);
1079
1080         return 0;
1081 }
1082
1083 /**
1084  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1085  * @chip:       nand chip structure
1086  * @oob:        oob destination address
1087  * @ops:        oob ops structure
1088  * @len:        size of oob to transfer
1089  */
1090 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1091                                   struct mtd_oob_ops *ops, size_t len)
1092 {
1093         switch(ops->mode) {
1094
1095         case MTD_OOB_PLACE:
1096         case MTD_OOB_RAW:
1097                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1098                 return oob + len;
1099
1100         case MTD_OOB_AUTO: {
1101                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1102                 uint32_t boffs = 0, roffs = ops->ooboffs;
1103                 size_t bytes = 0;
1104
1105                 for(; free->length && len; free++, len -= bytes) {
1106                         /* Read request not from offset 0 ? */
1107                         if (unlikely(roffs)) {
1108                                 if (roffs >= free->length) {
1109                                         roffs -= free->length;
1110                                         continue;
1111                                 }
1112                                 boffs = free->offset + roffs;
1113                                 bytes = min_t(size_t, len,
1114                                               (free->length - roffs));
1115                                 roffs = 0;
1116                         } else {
1117                                 bytes = min_t(size_t, len, free->length);
1118                                 boffs = free->offset;
1119                         }
1120                         memcpy(oob, chip->oob_poi + boffs, bytes);
1121                         oob += bytes;
1122                 }
1123                 return oob;
1124         }
1125         default:
1126                 BUG();
1127         }
1128         return NULL;
1129 }
1130
1131 /**
1132  * nand_do_read_ops - [Internal] Read data with ECC
1133  *
1134  * @mtd:        MTD device structure
1135  * @from:       offset to read from
1136  * @ops:        oob ops structure
1137  *
1138  * Internal function. Called with chip held.
1139  */
1140 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1141                             struct mtd_oob_ops *ops)
1142 {
1143         int chipnr, page, realpage, col, bytes, aligned;
1144         struct nand_chip *chip = mtd->priv;
1145         struct mtd_ecc_stats stats;
1146         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1147         int sndcmd = 1;
1148         int ret = 0;
1149         uint32_t readlen = ops->len;
1150         uint32_t oobreadlen = ops->ooblen;
1151         uint8_t *bufpoi, *oob, *buf;
1152
1153         stats = mtd->ecc_stats;
1154
1155         chipnr = (int)(from >> chip->chip_shift);
1156         chip->select_chip(mtd, chipnr);
1157
1158         realpage = (int)(from >> chip->page_shift);
1159         page = realpage & chip->pagemask;
1160
1161         col = (int)(from & (mtd->writesize - 1));
1162
1163         buf = ops->datbuf;
1164         oob = ops->oobbuf;
1165
1166         while(1) {
1167                 bytes = min(mtd->writesize - col, readlen);
1168                 aligned = (bytes == mtd->writesize);
1169
1170                 /* Is the current page in the buffer ? */
1171                 if (realpage != chip->pagebuf || oob) {
1172                         bufpoi = aligned ? buf : chip->buffers->databuf;
1173
1174                         if (likely(sndcmd)) {
1175                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1176                                 sndcmd = 0;
1177                         }
1178
1179                         /* Now read the page into the buffer */
1180                         if (unlikely(ops->mode == MTD_OOB_RAW))
1181                                 ret = chip->ecc.read_page_raw(mtd, chip,
1182                                                               bufpoi, page);
1183                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1184                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1185                         else
1186                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1187                                                           page);
1188                         if (ret < 0)
1189                                 break;
1190
1191                         /* Transfer not aligned data */
1192                         if (!aligned) {
1193                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1194                                         chip->pagebuf = realpage;
1195                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1196                         }
1197
1198                         buf += bytes;
1199
1200                         if (unlikely(oob)) {
1201                                 /* Raw mode does data:oob:data:oob */
1202                                 if (ops->mode != MTD_OOB_RAW) {
1203                                         int toread = min(oobreadlen,
1204                                                 chip->ecc.layout->oobavail);
1205                                         if (toread) {
1206                                                 oob = nand_transfer_oob(chip,
1207                                                         oob, ops, toread);
1208                                                 oobreadlen -= toread;
1209                                         }
1210                                 } else
1211                                         buf = nand_transfer_oob(chip,
1212                                                 buf, ops, mtd->oobsize);
1213                         }
1214
1215                         if (!(chip->options & NAND_NO_READRDY)) {
1216                                 /*
1217                                  * Apply delay or wait for ready/busy pin. Do
1218                                  * this before the AUTOINCR check, so no
1219                                  * problems arise if a chip which does auto
1220                                  * increment is marked as NOAUTOINCR by the
1221                                  * board driver.
1222                                  */
1223                                 if (!chip->dev_ready)
1224                                         udelay(chip->chip_delay);
1225                                 else
1226                                         nand_wait_ready(mtd);
1227                         }
1228                 } else {
1229                         memcpy(buf, chip->buffers->databuf + col, bytes);
1230                         buf += bytes;
1231                 }
1232
1233                 readlen -= bytes;
1234
1235                 if (!readlen)
1236                         break;
1237
1238                 /* For subsequent reads align to page boundary. */
1239                 col = 0;
1240                 /* Increment page address */
1241                 realpage++;
1242
1243                 page = realpage & chip->pagemask;
1244                 /* Check, if we cross a chip boundary */
1245                 if (!page) {
1246                         chipnr++;
1247                         chip->select_chip(mtd, -1);
1248                         chip->select_chip(mtd, chipnr);
1249                 }
1250
1251                 /* Check, if the chip supports auto page increment
1252                  * or if we have hit a block boundary.
1253                  */
1254                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1255                         sndcmd = 1;
1256         }
1257
1258         ops->retlen = ops->len - (size_t) readlen;
1259         if (oob)
1260                 ops->oobretlen = ops->ooblen - oobreadlen;
1261
1262         if (ret)
1263                 return ret;
1264
1265         if (mtd->ecc_stats.failed - stats.failed)
1266                 return -EBADMSG;
1267
1268         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1269 }
1270
1271 /**
1272  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1273  * @mtd:        MTD device structure
1274  * @from:       offset to read from
1275  * @len:        number of bytes to read
1276  * @retlen:     pointer to variable to store the number of read bytes
1277  * @buf:        the databuffer to put data
1278  *
1279  * Get hold of the chip and call nand_do_read
1280  */
1281 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1282                      size_t *retlen, uint8_t *buf)
1283 {
1284         struct nand_chip *chip = mtd->priv;
1285         int ret;
1286
1287         /* Do not allow reads past end of device */
1288         if ((from + len) > mtd->size)
1289                 return -EINVAL;
1290         if (!len)
1291                 return 0;
1292
1293         nand_get_device(chip, mtd, FL_READING);
1294
1295         chip->ops.len = len;
1296         chip->ops.datbuf = buf;
1297         chip->ops.oobbuf = NULL;
1298
1299         ret = nand_do_read_ops(mtd, from, &chip->ops);
1300
1301         *retlen = chip->ops.retlen;
1302
1303         nand_release_device(mtd);
1304
1305         return ret;
1306 }
1307
1308 /**
1309  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1310  * @mtd:        mtd info structure
1311  * @chip:       nand chip info structure
1312  * @page:       page number to read
1313  * @sndcmd:     flag whether to issue read command or not
1314  */
1315 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1316                              int page, int sndcmd)
1317 {
1318         if (sndcmd) {
1319                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1320                 sndcmd = 0;
1321         }
1322         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1323         return sndcmd;
1324 }
1325
1326 /**
1327  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1328  *                          with syndromes
1329  * @mtd:        mtd info structure
1330  * @chip:       nand chip info structure
1331  * @page:       page number to read
1332  * @sndcmd:     flag whether to issue read command or not
1333  */
1334 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1335                                   int page, int sndcmd)
1336 {
1337         uint8_t *buf = chip->oob_poi;
1338         int length = mtd->oobsize;
1339         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1340         int eccsize = chip->ecc.size;
1341         uint8_t *bufpoi = buf;
1342         int i, toread, sndrnd = 0, pos;
1343
1344         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1345         for (i = 0; i < chip->ecc.steps; i++) {
1346                 if (sndrnd) {
1347                         pos = eccsize + i * (eccsize + chunk);
1348                         if (mtd->writesize > 512)
1349                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1350                         else
1351                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1352                 } else
1353                         sndrnd = 1;
1354                 toread = min_t(int, length, chunk);
1355                 chip->read_buf(mtd, bufpoi, toread);
1356                 bufpoi += toread;
1357                 length -= toread;
1358         }
1359         if (length > 0)
1360                 chip->read_buf(mtd, bufpoi, length);
1361
1362         return 1;
1363 }
1364
1365 /**
1366  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1367  * @mtd:        mtd info structure
1368  * @chip:       nand chip info structure
1369  * @page:       page number to write
1370  */
1371 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1372                               int page)
1373 {
1374         int status = 0;
1375         const uint8_t *buf = chip->oob_poi;
1376         int length = mtd->oobsize;
1377
1378         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1379         chip->write_buf(mtd, buf, length);
1380         /* Send command to program the OOB data */
1381         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1382
1383         status = chip->waitfunc(mtd, chip);
1384
1385         return status & NAND_STATUS_FAIL ? -EIO : 0;
1386 }
1387
1388 /**
1389  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1390  *                           with syndrome - only for large page flash !
1391  * @mtd:        mtd info structure
1392  * @chip:       nand chip info structure
1393  * @page:       page number to write
1394  */
1395 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1396                                    struct nand_chip *chip, int page)
1397 {
1398         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1399         int eccsize = chip->ecc.size, length = mtd->oobsize;
1400         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1401         const uint8_t *bufpoi = chip->oob_poi;
1402
1403         /*
1404          * data-ecc-data-ecc ... ecc-oob
1405          * or
1406          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1407          */
1408         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1409                 pos = steps * (eccsize + chunk);
1410                 steps = 0;
1411         } else
1412                 pos = eccsize;
1413
1414         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1415         for (i = 0; i < steps; i++) {
1416                 if (sndcmd) {
1417                         if (mtd->writesize <= 512) {
1418                                 uint32_t fill = 0xFFFFFFFF;
1419
1420                                 len = eccsize;
1421                                 while (len > 0) {
1422                                         int num = min_t(int, len, 4);
1423                                         chip->write_buf(mtd, (uint8_t *)&fill,
1424                                                         num);
1425                                         len -= num;
1426                                 }
1427                         } else {
1428                                 pos = eccsize + i * (eccsize + chunk);
1429                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1430                         }
1431                 } else
1432                         sndcmd = 1;
1433                 len = min_t(int, length, chunk);
1434                 chip->write_buf(mtd, bufpoi, len);
1435                 bufpoi += len;
1436                 length -= len;
1437         }
1438         if (length > 0)
1439                 chip->write_buf(mtd, bufpoi, length);
1440
1441         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1442         status = chip->waitfunc(mtd, chip);
1443
1444         return status & NAND_STATUS_FAIL ? -EIO : 0;
1445 }
1446
1447 /**
1448  * nand_do_read_oob - [Intern] NAND read out-of-band
1449  * @mtd:        MTD device structure
1450  * @from:       offset to read from
1451  * @ops:        oob operations description structure
1452  *
1453  * NAND read out-of-band data from the spare area
1454  */
1455 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1456                             struct mtd_oob_ops *ops)
1457 {
1458         int page, realpage, chipnr, sndcmd = 1;
1459         struct nand_chip *chip = mtd->priv;
1460         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1461         int readlen = ops->ooblen;
1462         int len;
1463         uint8_t *buf = ops->oobbuf;
1464
1465         DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1466                         __func__, (unsigned long long)from, readlen);
1467
1468         if (ops->mode == MTD_OOB_AUTO)
1469                 len = chip->ecc.layout->oobavail;
1470         else
1471                 len = mtd->oobsize;
1472
1473         if (unlikely(ops->ooboffs >= len)) {
1474                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1475                                         "outside oob\n", __func__);
1476                 return -EINVAL;
1477         }
1478
1479         /* Do not allow reads past end of device */
1480         if (unlikely(from >= mtd->size ||
1481                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1482                                         (from >> chip->page_shift)) * len)) {
1483                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1484                                         "of device\n", __func__);
1485                 return -EINVAL;
1486         }
1487
1488         chipnr = (int)(from >> chip->chip_shift);
1489         chip->select_chip(mtd, chipnr);
1490
1491         /* Shift to get page */
1492         realpage = (int)(from >> chip->page_shift);
1493         page = realpage & chip->pagemask;
1494
1495         while(1) {
1496                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1497
1498                 len = min(len, readlen);
1499                 buf = nand_transfer_oob(chip, buf, ops, len);
1500
1501                 if (!(chip->options & NAND_NO_READRDY)) {
1502                         /*
1503                          * Apply delay or wait for ready/busy pin. Do this
1504                          * before the AUTOINCR check, so no problems arise if a
1505                          * chip which does auto increment is marked as
1506                          * NOAUTOINCR by the board driver.
1507                          */
1508                         if (!chip->dev_ready)
1509                                 udelay(chip->chip_delay);
1510                         else
1511                                 nand_wait_ready(mtd);
1512                 }
1513
1514                 readlen -= len;
1515                 if (!readlen)
1516                         break;
1517
1518                 /* Increment page address */
1519                 realpage++;
1520
1521                 page = realpage & chip->pagemask;
1522                 /* Check, if we cross a chip boundary */
1523                 if (!page) {
1524                         chipnr++;
1525                         chip->select_chip(mtd, -1);
1526                         chip->select_chip(mtd, chipnr);
1527                 }
1528
1529                 /* Check, if the chip supports auto page increment
1530                  * or if we have hit a block boundary.
1531                  */
1532                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1533                         sndcmd = 1;
1534         }
1535
1536         ops->oobretlen = ops->ooblen;
1537         return 0;
1538 }
1539
1540 /**
1541  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1542  * @mtd:        MTD device structure
1543  * @from:       offset to read from
1544  * @ops:        oob operation description structure
1545  *
1546  * NAND read data and/or out-of-band data
1547  */
1548 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1549                          struct mtd_oob_ops *ops)
1550 {
1551         struct nand_chip *chip = mtd->priv;
1552         int ret = -ENOTSUPP;
1553
1554         ops->retlen = 0;
1555
1556         /* Do not allow reads past end of device */
1557         if (ops->datbuf && (from + ops->len) > mtd->size) {
1558                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1559                                 "beyond end of device\n", __func__);
1560                 return -EINVAL;
1561         }
1562
1563         nand_get_device(chip, mtd, FL_READING);
1564
1565         switch(ops->mode) {
1566         case MTD_OOB_PLACE:
1567         case MTD_OOB_AUTO:
1568         case MTD_OOB_RAW:
1569                 break;
1570
1571         default:
1572                 goto out;
1573         }
1574
1575         if (!ops->datbuf)
1576                 ret = nand_do_read_oob(mtd, from, ops);
1577         else
1578                 ret = nand_do_read_ops(mtd, from, ops);
1579
1580  out:
1581         nand_release_device(mtd);
1582         return ret;
1583 }
1584
1585
1586 /**
1587  * nand_write_page_raw - [Intern] raw page write function
1588  * @mtd:        mtd info structure
1589  * @chip:       nand chip info structure
1590  * @buf:        data buffer
1591  *
1592  * Not for syndrome calculating ecc controllers, which use a special oob layout
1593  */
1594 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1595                                 const uint8_t *buf)
1596 {
1597         chip->write_buf(mtd, buf, mtd->writesize);
1598         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1599 }
1600
1601 /**
1602  * nand_write_page_raw_syndrome - [Intern] raw page write function
1603  * @mtd:        mtd info structure
1604  * @chip:       nand chip info structure
1605  * @buf:        data buffer
1606  *
1607  * We need a special oob layout and handling even when ECC isn't checked.
1608  */
1609 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1610                                 const uint8_t *buf)
1611 {
1612         int eccsize = chip->ecc.size;
1613         int eccbytes = chip->ecc.bytes;
1614         uint8_t *oob = chip->oob_poi;
1615         int steps, size;
1616
1617         for (steps = chip->ecc.steps; steps > 0; steps--) {
1618                 chip->write_buf(mtd, buf, eccsize);
1619                 buf += eccsize;
1620
1621                 if (chip->ecc.prepad) {
1622                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1623                         oob += chip->ecc.prepad;
1624                 }
1625
1626                 chip->read_buf(mtd, oob, eccbytes);
1627                 oob += eccbytes;
1628
1629                 if (chip->ecc.postpad) {
1630                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1631                         oob += chip->ecc.postpad;
1632                 }
1633         }
1634
1635         size = mtd->oobsize - (oob - chip->oob_poi);
1636         if (size)
1637                 chip->write_buf(mtd, oob, size);
1638 }
1639 /**
1640  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1641  * @mtd:        mtd info structure
1642  * @chip:       nand chip info structure
1643  * @buf:        data buffer
1644  */
1645 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1646                                   const uint8_t *buf)
1647 {
1648         int i, eccsize = chip->ecc.size;
1649         int eccbytes = chip->ecc.bytes;
1650         int eccsteps = chip->ecc.steps;
1651         uint8_t *ecc_calc = chip->buffers->ecccalc;
1652         const uint8_t *p = buf;
1653         uint32_t *eccpos = chip->ecc.layout->eccpos;
1654
1655         /* Software ecc calculation */
1656         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1657                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1658
1659         for (i = 0; i < chip->ecc.total; i++)
1660                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1661
1662         chip->ecc.write_page_raw(mtd, chip, buf);
1663 }
1664
1665 /**
1666  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1667  * @mtd:        mtd info structure
1668  * @chip:       nand chip info structure
1669  * @buf:        data buffer
1670  */
1671 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1672                                   const uint8_t *buf)
1673 {
1674         int i, eccsize = chip->ecc.size;
1675         int eccbytes = chip->ecc.bytes;
1676         int eccsteps = chip->ecc.steps;
1677         uint8_t *ecc_calc = chip->buffers->ecccalc;
1678         const uint8_t *p = buf;
1679         uint32_t *eccpos = chip->ecc.layout->eccpos;
1680
1681         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1682                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1683                 chip->write_buf(mtd, p, eccsize);
1684                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1685         }
1686
1687         for (i = 0; i < chip->ecc.total; i++)
1688                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1689
1690         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1691 }
1692
1693 /**
1694  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1695  * @mtd:        mtd info structure
1696  * @chip:       nand chip info structure
1697  * @buf:        data buffer
1698  *
1699  * The hw generator calculates the error syndrome automatically. Therefor
1700  * we need a special oob layout and handling.
1701  */
1702 static void nand_write_page_syndrome(struct mtd_info *mtd,
1703                                     struct nand_chip *chip, const uint8_t *buf)
1704 {
1705         int i, eccsize = chip->ecc.size;
1706         int eccbytes = chip->ecc.bytes;
1707         int eccsteps = chip->ecc.steps;
1708         const uint8_t *p = buf;
1709         uint8_t *oob = chip->oob_poi;
1710
1711         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1712
1713                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1714                 chip->write_buf(mtd, p, eccsize);
1715
1716                 if (chip->ecc.prepad) {
1717                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1718                         oob += chip->ecc.prepad;
1719                 }
1720
1721                 chip->ecc.calculate(mtd, p, oob);
1722                 chip->write_buf(mtd, oob, eccbytes);
1723                 oob += eccbytes;
1724
1725                 if (chip->ecc.postpad) {
1726                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1727                         oob += chip->ecc.postpad;
1728                 }
1729         }
1730
1731         /* Calculate remaining oob bytes */
1732         i = mtd->oobsize - (oob - chip->oob_poi);
1733         if (i)
1734                 chip->write_buf(mtd, oob, i);
1735 }
1736
1737 /**
1738  * nand_write_page - [REPLACEABLE] write one page
1739  * @mtd:        MTD device structure
1740  * @chip:       NAND chip descriptor
1741  * @buf:        the data to write
1742  * @page:       page number to write
1743  * @cached:     cached programming
1744  * @raw:        use _raw version of write_page
1745  */
1746 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1747                            const uint8_t *buf, int page, int cached, int raw)
1748 {
1749         int status;
1750
1751         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1752
1753         if (unlikely(raw))
1754                 chip->ecc.write_page_raw(mtd, chip, buf);
1755         else
1756                 chip->ecc.write_page(mtd, chip, buf);
1757
1758         /*
1759          * Cached progamming disabled for now, Not sure if its worth the
1760          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1761          */
1762         cached = 0;
1763
1764         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1765
1766                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1767                 status = chip->waitfunc(mtd, chip);
1768                 /*
1769                  * See if operation failed and additional status checks are
1770                  * available
1771                  */
1772                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1773                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1774                                                page);
1775
1776                 if (status & NAND_STATUS_FAIL)
1777                         return -EIO;
1778         } else {
1779                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1780                 status = chip->waitfunc(mtd, chip);
1781         }
1782
1783 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1784         /* Send command to read back the data */
1785         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1786
1787         if (chip->verify_buf(mtd, buf, mtd->writesize))
1788                 return -EIO;
1789 #endif
1790         return 0;
1791 }
1792
1793 /**
1794  * nand_fill_oob - [Internal] Transfer client buffer to oob
1795  * @chip:       nand chip structure
1796  * @oob:        oob data buffer
1797  * @ops:        oob ops structure
1798  */
1799 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1800                                   struct mtd_oob_ops *ops)
1801 {
1802         size_t len = ops->ooblen;
1803
1804         switch(ops->mode) {
1805
1806         case MTD_OOB_PLACE:
1807         case MTD_OOB_RAW:
1808                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1809                 return oob + len;
1810
1811         case MTD_OOB_AUTO: {
1812                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1813                 uint32_t boffs = 0, woffs = ops->ooboffs;
1814                 size_t bytes = 0;
1815
1816                 for(; free->length && len; free++, len -= bytes) {
1817                         /* Write request not from offset 0 ? */
1818                         if (unlikely(woffs)) {
1819                                 if (woffs >= free->length) {
1820                                         woffs -= free->length;
1821                                         continue;
1822                                 }
1823                                 boffs = free->offset + woffs;
1824                                 bytes = min_t(size_t, len,
1825                                               (free->length - woffs));
1826                                 woffs = 0;
1827                         } else {
1828                                 bytes = min_t(size_t, len, free->length);
1829                                 boffs = free->offset;
1830                         }
1831                         memcpy(chip->oob_poi + boffs, oob, bytes);
1832                         oob += bytes;
1833                 }
1834                 return oob;
1835         }
1836         default:
1837                 BUG();
1838         }
1839         return NULL;
1840 }
1841
1842 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1843
1844 /**
1845  * nand_do_write_ops - [Internal] NAND write with ECC
1846  * @mtd:        MTD device structure
1847  * @to:         offset to write to
1848  * @ops:        oob operations description structure
1849  *
1850  * NAND write with ECC
1851  */
1852 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1853                              struct mtd_oob_ops *ops)
1854 {
1855         int chipnr, realpage, page, blockmask, column;
1856         struct nand_chip *chip = mtd->priv;
1857         uint32_t writelen = ops->len;
1858         uint8_t *oob = ops->oobbuf;
1859         uint8_t *buf = ops->datbuf;
1860         int ret, subpage;
1861
1862         ops->retlen = 0;
1863         if (!writelen)
1864                 return 0;
1865
1866         /* reject writes, which are not page aligned */
1867         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1868                 printk(KERN_NOTICE "%s: Attempt to write not "
1869                                 "page aligned data\n", __func__);
1870                 return -EINVAL;
1871         }
1872
1873         column = to & (mtd->writesize - 1);
1874         subpage = column || (writelen & (mtd->writesize - 1));
1875
1876         if (subpage && oob)
1877                 return -EINVAL;
1878
1879         chipnr = (int)(to >> chip->chip_shift);
1880         chip->select_chip(mtd, chipnr);
1881
1882         /* Check, if it is write protected */
1883         if (nand_check_wp(mtd))
1884                 return -EIO;
1885
1886         realpage = (int)(to >> chip->page_shift);
1887         page = realpage & chip->pagemask;
1888         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1889
1890         /* Invalidate the page cache, when we write to the cached page */
1891         if (to <= (chip->pagebuf << chip->page_shift) &&
1892             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1893                 chip->pagebuf = -1;
1894
1895         /* If we're not given explicit OOB data, let it be 0xFF */
1896         if (likely(!oob))
1897                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1898
1899         while(1) {
1900                 int bytes = mtd->writesize;
1901                 int cached = writelen > bytes && page != blockmask;
1902                 uint8_t *wbuf = buf;
1903
1904                 /* Partial page write ? */
1905                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1906                         cached = 0;
1907                         bytes = min_t(int, bytes - column, (int) writelen);
1908                         chip->pagebuf = -1;
1909                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1910                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1911                         wbuf = chip->buffers->databuf;
1912                 }
1913
1914                 if (unlikely(oob))
1915                         oob = nand_fill_oob(chip, oob, ops);
1916
1917                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1918                                        (ops->mode == MTD_OOB_RAW));
1919                 if (ret)
1920                         break;
1921
1922                 writelen -= bytes;
1923                 if (!writelen)
1924                         break;
1925
1926                 column = 0;
1927                 buf += bytes;
1928                 realpage++;
1929
1930                 page = realpage & chip->pagemask;
1931                 /* Check, if we cross a chip boundary */
1932                 if (!page) {
1933                         chipnr++;
1934                         chip->select_chip(mtd, -1);
1935                         chip->select_chip(mtd, chipnr);
1936                 }
1937         }
1938
1939         ops->retlen = ops->len - writelen;
1940         if (unlikely(oob))
1941                 ops->oobretlen = ops->ooblen;
1942         return ret;
1943 }
1944
1945 /**
1946  * nand_write - [MTD Interface] NAND write with ECC
1947  * @mtd:        MTD device structure
1948  * @to:         offset to write to
1949  * @len:        number of bytes to write
1950  * @retlen:     pointer to variable to store the number of written bytes
1951  * @buf:        the data to write
1952  *
1953  * NAND write with ECC
1954  */
1955 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1956                           size_t *retlen, const uint8_t *buf)
1957 {
1958         struct nand_chip *chip = mtd->priv;
1959         int ret;
1960
1961         /* Do not allow reads past end of device */
1962         if ((to + len) > mtd->size)
1963                 return -EINVAL;
1964         if (!len)
1965                 return 0;
1966
1967         nand_get_device(chip, mtd, FL_WRITING);
1968
1969         chip->ops.len = len;
1970         chip->ops.datbuf = (uint8_t *)buf;
1971         chip->ops.oobbuf = NULL;
1972
1973         ret = nand_do_write_ops(mtd, to, &chip->ops);
1974
1975         *retlen = chip->ops.retlen;
1976
1977         nand_release_device(mtd);
1978
1979         return ret;
1980 }
1981
1982 /**
1983  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1984  * @mtd:        MTD device structure
1985  * @to:         offset to write to
1986  * @ops:        oob operation description structure
1987  *
1988  * NAND write out-of-band
1989  */
1990 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1991                              struct mtd_oob_ops *ops)
1992 {
1993         int chipnr, page, status, len;
1994         struct nand_chip *chip = mtd->priv;
1995
1996         DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
1997                          __func__, (unsigned int)to, (int)ops->ooblen);
1998
1999         if (ops->mode == MTD_OOB_AUTO)
2000                 len = chip->ecc.layout->oobavail;
2001         else
2002                 len = mtd->oobsize;
2003
2004         /* Do not allow write past end of page */
2005         if ((ops->ooboffs + ops->ooblen) > len) {
2006                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2007                                 "past end of page\n", __func__);
2008                 return -EINVAL;
2009         }
2010
2011         if (unlikely(ops->ooboffs >= len)) {
2012                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2013                                 "write outside oob\n", __func__);
2014                 return -EINVAL;
2015         }
2016
2017         /* Do not allow reads past end of device */
2018         if (unlikely(to >= mtd->size ||
2019                      ops->ooboffs + ops->ooblen >
2020                         ((mtd->size >> chip->page_shift) -
2021                          (to >> chip->page_shift)) * len)) {
2022                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2023                                 "end of device\n", __func__);
2024                 return -EINVAL;
2025         }
2026
2027         chipnr = (int)(to >> chip->chip_shift);
2028         chip->select_chip(mtd, chipnr);
2029
2030         /* Shift to get page */
2031         page = (int)(to >> chip->page_shift);
2032
2033         /*
2034          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2035          * of my DiskOnChip 2000 test units) will clear the whole data page too
2036          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2037          * it in the doc2000 driver in August 1999.  dwmw2.
2038          */
2039         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2040
2041         /* Check, if it is write protected */
2042         if (nand_check_wp(mtd))
2043                 return -EROFS;
2044
2045         /* Invalidate the page cache, if we write to the cached page */
2046         if (page == chip->pagebuf)
2047                 chip->pagebuf = -1;
2048
2049         memset(chip->oob_poi, 0xff, mtd->oobsize);
2050         nand_fill_oob(chip, ops->oobbuf, ops);
2051         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2052         memset(chip->oob_poi, 0xff, mtd->oobsize);
2053
2054         if (status)
2055                 return status;
2056
2057         ops->oobretlen = ops->ooblen;
2058
2059         return 0;
2060 }
2061
2062 /**
2063  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2064  * @mtd:        MTD device structure
2065  * @to:         offset to write to
2066  * @ops:        oob operation description structure
2067  */
2068 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2069                           struct mtd_oob_ops *ops)
2070 {
2071         struct nand_chip *chip = mtd->priv;
2072         int ret = -ENOTSUPP;
2073
2074         ops->retlen = 0;
2075
2076         /* Do not allow writes past end of device */
2077         if (ops->datbuf && (to + ops->len) > mtd->size) {
2078                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2079                                 "end of device\n", __func__);
2080                 return -EINVAL;
2081         }
2082
2083         nand_get_device(chip, mtd, FL_WRITING);
2084
2085         switch(ops->mode) {
2086         case MTD_OOB_PLACE:
2087         case MTD_OOB_AUTO:
2088         case MTD_OOB_RAW:
2089                 break;
2090
2091         default:
2092                 goto out;
2093         }
2094
2095         if (!ops->datbuf)
2096                 ret = nand_do_write_oob(mtd, to, ops);
2097         else
2098                 ret = nand_do_write_ops(mtd, to, ops);
2099
2100  out:
2101         nand_release_device(mtd);
2102         return ret;
2103 }
2104
2105 /**
2106  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2107  * @mtd:        MTD device structure
2108  * @page:       the page address of the block which will be erased
2109  *
2110  * Standard erase command for NAND chips
2111  */
2112 static void single_erase_cmd(struct mtd_info *mtd, int page)
2113 {
2114         struct nand_chip *chip = mtd->priv;
2115         /* Send commands to erase a block */
2116         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2117         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2118 }
2119
2120 /**
2121  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2122  * @mtd:        MTD device structure
2123  * @page:       the page address of the block which will be erased
2124  *
2125  * AND multi block erase command function
2126  * Erase 4 consecutive blocks
2127  */
2128 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2129 {
2130         struct nand_chip *chip = mtd->priv;
2131         /* Send commands to erase a block */
2132         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2133         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2134         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2135         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2136         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2137 }
2138
2139 /**
2140  * nand_erase - [MTD Interface] erase block(s)
2141  * @mtd:        MTD device structure
2142  * @instr:      erase instruction
2143  *
2144  * Erase one ore more blocks
2145  */
2146 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2147 {
2148         return nand_erase_nand(mtd, instr, 0);
2149 }
2150
2151 #define BBT_PAGE_MASK   0xffffff3f
2152 /**
2153  * nand_erase_nand - [Internal] erase block(s)
2154  * @mtd:        MTD device structure
2155  * @instr:      erase instruction
2156  * @allowbbt:   allow erasing the bbt area
2157  *
2158  * Erase one ore more blocks
2159  */
2160 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2161                     int allowbbt)
2162 {
2163         int page, status, pages_per_block, ret, chipnr;
2164         struct nand_chip *chip = mtd->priv;
2165         loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
2166         unsigned int bbt_masked_page = 0xffffffff;
2167         loff_t len;
2168
2169         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2170                                 __func__, (unsigned long long)instr->addr,
2171                                 (unsigned long long)instr->len);
2172
2173         /* Start address must align on block boundary */
2174         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2175                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
2176                 return -EINVAL;
2177         }
2178
2179         /* Length must align on block boundary */
2180         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2181                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
2182                                         __func__);
2183                 return -EINVAL;
2184         }
2185
2186         /* Do not allow erase past end of device */
2187         if ((instr->len + instr->addr) > mtd->size) {
2188                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Erase past end of device\n",
2189                                         __func__);
2190                 return -EINVAL;
2191         }
2192
2193         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2194
2195         /* Grab the lock and see if the device is available */
2196         nand_get_device(chip, mtd, FL_ERASING);
2197
2198         /* Shift to get first page */
2199         page = (int)(instr->addr >> chip->page_shift);
2200         chipnr = (int)(instr->addr >> chip->chip_shift);
2201
2202         /* Calculate pages in each block */
2203         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2204
2205         /* Select the NAND device */
2206         chip->select_chip(mtd, chipnr);
2207
2208         /* Check, if it is write protected */
2209         if (nand_check_wp(mtd)) {
2210                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2211                                         __func__);
2212                 instr->state = MTD_ERASE_FAILED;
2213                 goto erase_exit;
2214         }
2215
2216         /*
2217          * If BBT requires refresh, set the BBT page mask to see if the BBT
2218          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2219          * can not be matched. This is also done when the bbt is actually
2220          * erased to avoid recusrsive updates
2221          */
2222         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2223                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2224
2225         /* Loop through the pages */
2226         len = instr->len;
2227
2228         instr->state = MTD_ERASING;
2229
2230         while (len) {
2231                 /*
2232                  * heck if we have a bad block, we do not erase bad blocks !
2233                  */
2234                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2235                                         chip->page_shift, 0, allowbbt)) {
2236                         printk(KERN_WARNING "%s: attempt to erase a bad block "
2237                                         "at page 0x%08x\n", __func__, page);
2238                         instr->state = MTD_ERASE_FAILED;
2239                         goto erase_exit;
2240                 }
2241
2242                 /*
2243                  * Invalidate the page cache, if we erase the block which
2244                  * contains the current cached page
2245                  */
2246                 if (page <= chip->pagebuf && chip->pagebuf <
2247                     (page + pages_per_block))
2248                         chip->pagebuf = -1;
2249
2250                 chip->erase_cmd(mtd, page & chip->pagemask);
2251
2252                 status = chip->waitfunc(mtd, chip);
2253
2254                 /*
2255                  * See if operation failed and additional status checks are
2256                  * available
2257                  */
2258                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2259                         status = chip->errstat(mtd, chip, FL_ERASING,
2260                                                status, page);
2261
2262                 /* See if block erase succeeded */
2263                 if (status & NAND_STATUS_FAIL) {
2264                         DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2265                                         "page 0x%08x\n", __func__, page);
2266                         instr->state = MTD_ERASE_FAILED;
2267                         instr->fail_addr =
2268                                 ((loff_t)page << chip->page_shift);
2269                         goto erase_exit;
2270                 }
2271
2272                 /*
2273                  * If BBT requires refresh, set the BBT rewrite flag to the
2274                  * page being erased
2275                  */
2276                 if (bbt_masked_page != 0xffffffff &&
2277                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2278                             rewrite_bbt[chipnr] =
2279                                         ((loff_t)page << chip->page_shift);
2280
2281                 /* Increment page address and decrement length */
2282                 len -= (1 << chip->phys_erase_shift);
2283                 page += pages_per_block;
2284
2285                 /* Check, if we cross a chip boundary */
2286                 if (len && !(page & chip->pagemask)) {
2287                         chipnr++;
2288                         chip->select_chip(mtd, -1);
2289                         chip->select_chip(mtd, chipnr);
2290
2291                         /*
2292                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2293                          * page mask to see if this BBT should be rewritten
2294                          */
2295                         if (bbt_masked_page != 0xffffffff &&
2296                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2297                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2298                                         BBT_PAGE_MASK;
2299                 }
2300         }
2301         instr->state = MTD_ERASE_DONE;
2302
2303  erase_exit:
2304
2305         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2306
2307         /* Deselect and wake up anyone waiting on the device */
2308         nand_release_device(mtd);
2309
2310         /* Do call back function */
2311         if (!ret)
2312                 mtd_erase_callback(instr);
2313
2314         /*
2315          * If BBT requires refresh and erase was successful, rewrite any
2316          * selected bad block tables
2317          */
2318         if (bbt_masked_page == 0xffffffff || ret)
2319                 return ret;
2320
2321         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2322                 if (!rewrite_bbt[chipnr])
2323                         continue;
2324                 /* update the BBT for chip */
2325                 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2326                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2327                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2328                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2329         }
2330
2331         /* Return more or less happy */
2332         return ret;
2333 }
2334
2335 /**
2336  * nand_sync - [MTD Interface] sync
2337  * @mtd:        MTD device structure
2338  *
2339  * Sync is actually a wait for chip ready function
2340  */
2341 static void nand_sync(struct mtd_info *mtd)
2342 {
2343         struct nand_chip *chip = mtd->priv;
2344
2345         DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2346
2347         /* Grab the lock and see if the device is available */
2348         nand_get_device(chip, mtd, FL_SYNCING);
2349         /* Release it and go back */
2350         nand_release_device(mtd);
2351 }
2352
2353 /**
2354  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2355  * @mtd:        MTD device structure
2356  * @offs:       offset relative to mtd start
2357  */
2358 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2359 {
2360         /* Check for invalid offset */
2361         if (offs > mtd->size)
2362                 return -EINVAL;
2363
2364         return nand_block_checkbad(mtd, offs, 1, 0);
2365 }
2366
2367 /**
2368  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2369  * @mtd:        MTD device structure
2370  * @ofs:        offset relative to mtd start
2371  */
2372 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2373 {
2374         struct nand_chip *chip = mtd->priv;
2375         int ret;
2376
2377         if ((ret = nand_block_isbad(mtd, ofs))) {
2378                 /* If it was bad already, return success and do nothing. */
2379                 if (ret > 0)
2380                         return 0;
2381                 return ret;
2382         }
2383
2384         return chip->block_markbad(mtd, ofs);
2385 }
2386
2387 /**
2388  * nand_suspend - [MTD Interface] Suspend the NAND flash
2389  * @mtd:        MTD device structure
2390  */
2391 static int nand_suspend(struct mtd_info *mtd)
2392 {
2393         struct nand_chip *chip = mtd->priv;
2394
2395         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2396 }
2397
2398 /**
2399  * nand_resume - [MTD Interface] Resume the NAND flash
2400  * @mtd:        MTD device structure
2401  */
2402 static void nand_resume(struct mtd_info *mtd)
2403 {
2404         struct nand_chip *chip = mtd->priv;
2405
2406         if (chip->state == FL_PM_SUSPENDED)
2407                 nand_release_device(mtd);
2408         else
2409                 printk(KERN_ERR "%s called for a chip which is not "
2410                        "in suspended state\n", __func__);
2411 }
2412
2413 /*
2414  * Set default functions
2415  */
2416 static void nand_set_defaults(struct nand_chip *chip, int busw)
2417 {
2418         /* check for proper chip_delay setup, set 20us if not */
2419         if (!chip->chip_delay)
2420                 chip->chip_delay = 20;
2421
2422         /* check, if a user supplied command function given */
2423         if (chip->cmdfunc == NULL)
2424                 chip->cmdfunc = nand_command;
2425
2426         /* check, if a user supplied wait function given */
2427         if (chip->waitfunc == NULL)
2428                 chip->waitfunc = nand_wait;
2429
2430         if (!chip->select_chip)
2431                 chip->select_chip = nand_select_chip;
2432         if (!chip->read_byte)
2433                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2434         if (!chip->read_word)
2435                 chip->read_word = nand_read_word;
2436         if (!chip->block_bad)
2437                 chip->block_bad = nand_block_bad;
2438         if (!chip->block_markbad)
2439                 chip->block_markbad = nand_default_block_markbad;
2440         if (!chip->write_buf)
2441                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2442         if (!chip->read_buf)
2443                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2444         if (!chip->verify_buf)
2445                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2446         if (!chip->scan_bbt)
2447                 chip->scan_bbt = nand_default_bbt;
2448
2449         if (!chip->controller) {
2450                 chip->controller = &chip->hwcontrol;
2451                 spin_lock_init(&chip->controller->lock);
2452                 init_waitqueue_head(&chip->controller->wq);
2453         }
2454
2455 }
2456
2457 /*
2458  * Get the flash and manufacturer id and lookup if the type is supported
2459  */
2460 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2461                                                   struct nand_chip *chip,
2462                                                   int busw, int *maf_id)
2463 {
2464         struct nand_flash_dev *type = NULL;
2465         int i, dev_id, maf_idx;
2466         int tmp_id, tmp_manf;
2467
2468         /* Select the device */
2469         chip->select_chip(mtd, 0);
2470
2471         /*
2472          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2473          * after power-up
2474          */
2475         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2476
2477         /* Send the command for reading device ID */
2478         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2479
2480         /* Read manufacturer and device IDs */
2481         *maf_id = chip->read_byte(mtd);
2482         dev_id = chip->read_byte(mtd);
2483
2484         /* Try again to make sure, as some systems the bus-hold or other
2485          * interface concerns can cause random data which looks like a
2486          * possibly credible NAND flash to appear. If the two results do
2487          * not match, ignore the device completely.
2488          */
2489
2490         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2491
2492         /* Read manufacturer and device IDs */
2493
2494         tmp_manf = chip->read_byte(mtd);
2495         tmp_id = chip->read_byte(mtd);
2496
2497         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2498                 printk(KERN_INFO "%s: second ID read did not match "
2499                        "%02x,%02x against %02x,%02x\n", __func__,
2500                        *maf_id, dev_id, tmp_manf, tmp_id);
2501                 return ERR_PTR(-ENODEV);
2502         }
2503
2504         /* Lookup the flash id */
2505         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2506                 if (dev_id == nand_flash_ids[i].id) {
2507                         type =  &nand_flash_ids[i];
2508                         break;
2509                 }
2510         }
2511
2512         if (!type)
2513                 return ERR_PTR(-ENODEV);
2514
2515         if (!mtd->name)
2516                 mtd->name = type->name;
2517
2518         chip->chipsize = (uint64_t)type->chipsize << 20;
2519
2520         /* Newer devices have all the information in additional id bytes */
2521         if (!type->pagesize) {
2522                 int extid;
2523                 /* The 3rd id byte holds MLC / multichip data */
2524                 chip->cellinfo = chip->read_byte(mtd);
2525                 /* The 4th id byte is the important one */
2526                 extid = chip->read_byte(mtd);
2527                 /* Calc pagesize */
2528                 mtd->writesize = 1024 << (extid & 0x3);
2529                 extid >>= 2;
2530                 /* Calc oobsize */
2531                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2532                 extid >>= 2;
2533                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2534                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2535                 extid >>= 2;
2536                 /* Get buswidth information */
2537                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2538
2539         } else {
2540                 /*
2541                  * Old devices have chip data hardcoded in the device id table
2542                  */
2543                 mtd->erasesize = type->erasesize;
2544                 mtd->writesize = type->pagesize;
2545                 mtd->oobsize = mtd->writesize / 32;
2546                 busw = type->options & NAND_BUSWIDTH_16;
2547         }
2548
2549         /* Try to identify manufacturer */
2550         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2551                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2552                         break;
2553         }
2554
2555         /*
2556          * Check, if buswidth is correct. Hardware drivers should set
2557          * chip correct !
2558          */
2559         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2560                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2561                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2562                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2563                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2564                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2565                        busw ? 16 : 8);
2566                 return ERR_PTR(-EINVAL);
2567         }
2568
2569         /* Calculate the address shift from the page size */
2570         chip->page_shift = ffs(mtd->writesize) - 1;
2571         /* Convert chipsize to number of pages per chip -1. */
2572         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2573
2574         chip->bbt_erase_shift = chip->phys_erase_shift =
2575                 ffs(mtd->erasesize) - 1;
2576         if (chip->chipsize & 0xffffffff)
2577                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2578         else
2579                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
2580
2581         /* Set the bad block position */
2582         chip->badblockpos = mtd->writesize > 512 ?
2583                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2584
2585         /* Get chip options, preserve non chip based options */
2586         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2587         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2588
2589         /*
2590          * Set chip as a default. Board drivers can override it, if necessary
2591          */
2592         chip->options |= NAND_NO_AUTOINCR;
2593
2594         /* Check if chip is a not a samsung device. Do not clear the
2595          * options for chips which are not having an extended id.
2596          */
2597         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2598                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2599
2600         /* Check for AND chips with 4 page planes */
2601         if (chip->options & NAND_4PAGE_ARRAY)
2602                 chip->erase_cmd = multi_erase_cmd;
2603         else
2604                 chip->erase_cmd = single_erase_cmd;
2605
2606         /* Do not replace user supplied command function ! */
2607         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2608                 chip->cmdfunc = nand_command_lp;
2609
2610         printk(KERN_INFO "NAND device: Manufacturer ID:"
2611                " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2612                nand_manuf_ids[maf_idx].name, type->name);
2613
2614         return type;
2615 }
2616
2617 /**
2618  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2619  * @mtd:             MTD device structure
2620  * @maxchips:        Number of chips to scan for
2621  *
2622  * This is the first phase of the normal nand_scan() function. It
2623  * reads the flash ID and sets up MTD fields accordingly.
2624  *
2625  * The mtd->owner field must be set to the module of the caller.
2626  */
2627 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2628 {
2629         int i, busw, nand_maf_id;
2630         struct nand_chip *chip = mtd->priv;
2631         struct nand_flash_dev *type;
2632
2633         /* Get buswidth to select the correct functions */
2634         busw = chip->options & NAND_BUSWIDTH_16;
2635         /* Set the default functions */
2636         nand_set_defaults(chip, busw);
2637
2638         /* Read the flash type */
2639         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2640
2641         if (IS_ERR(type)) {
2642                 printk(KERN_WARNING "No NAND device found!!!\n");
2643                 chip->select_chip(mtd, -1);
2644                 return PTR_ERR(type);
2645         }
2646
2647         /* Check for a chip array */
2648         for (i = 1; i < maxchips; i++) {
2649                 chip->select_chip(mtd, i);
2650                 /* See comment in nand_get_flash_type for reset */
2651                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2652                 /* Send the command for reading device ID */
2653                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2654                 /* Read manufacturer and device IDs */
2655                 if (nand_maf_id != chip->read_byte(mtd) ||
2656                     type->id != chip->read_byte(mtd))
2657                         break;
2658         }
2659         if (i > 1)
2660                 printk(KERN_INFO "%d NAND chips detected\n", i);
2661
2662         /* Store the number of chips and calc total size for mtd */
2663         chip->numchips = i;
2664         mtd->size = i * chip->chipsize;
2665
2666         return 0;
2667 }
2668
2669
2670 /**
2671  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2672  * @mtd:            MTD device structure
2673  *
2674  * This is the second phase of the normal nand_scan() function. It
2675  * fills out all the uninitialized function pointers with the defaults
2676  * and scans for a bad block table if appropriate.
2677  */
2678 int nand_scan_tail(struct mtd_info *mtd)
2679 {
2680         int i;
2681         struct nand_chip *chip = mtd->priv;
2682
2683         if (!(chip->options & NAND_OWN_BUFFERS))
2684                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2685         if (!chip->buffers)
2686                 return -ENOMEM;
2687
2688         /* Set the internal oob buffer location, just after the page data */
2689         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2690
2691         /*
2692          * If no default placement scheme is given, select an appropriate one
2693          */
2694         if (!chip->ecc.layout) {
2695                 switch (mtd->oobsize) {
2696                 case 8:
2697                         chip->ecc.layout = &nand_oob_8;
2698                         break;
2699                 case 16:
2700                         chip->ecc.layout = &nand_oob_16;
2701                         break;
2702                 case 64:
2703                         chip->ecc.layout = &nand_oob_64;
2704                         break;
2705                 case 128:
2706                         chip->ecc.layout = &nand_oob_128;
2707                         break;
2708                 default:
2709                         printk(KERN_WARNING "No oob scheme defined for "
2710                                "oobsize %d\n", mtd->oobsize);
2711                         BUG();
2712                 }
2713         }
2714
2715         if (!chip->write_page)
2716                 chip->write_page = nand_write_page;
2717
2718         /*
2719          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2720          * selected and we have 256 byte pagesize fallback to software ECC
2721          */
2722
2723         switch (chip->ecc.mode) {
2724         case NAND_ECC_HW_OOB_FIRST:
2725                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2726                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2727                      !chip->ecc.hwctl) {
2728                         printk(KERN_WARNING "No ECC functions supplied; "
2729                                "Hardware ECC not possible\n");
2730                         BUG();
2731                 }
2732                 if (!chip->ecc.read_page)
2733                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2734
2735         case NAND_ECC_HW:
2736                 /* Use standard hwecc read page function ? */
2737                 if (!chip->ecc.read_page)
2738                         chip->ecc.read_page = nand_read_page_hwecc;
2739                 if (!chip->ecc.write_page)
2740                         chip->ecc.write_page = nand_write_page_hwecc;
2741                 if (!chip->ecc.read_page_raw)
2742                         chip->ecc.read_page_raw = nand_read_page_raw;
2743                 if (!chip->ecc.write_page_raw)
2744                         chip->ecc.write_page_raw = nand_write_page_raw;
2745                 if (!chip->ecc.read_oob)
2746                         chip->ecc.read_oob = nand_read_oob_std;
2747                 if (!chip->ecc.write_oob)
2748                         chip->ecc.write_oob = nand_write_oob_std;
2749
2750         case NAND_ECC_HW_SYNDROME:
2751                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2752                      !chip->ecc.hwctl) &&
2753                     (!chip->ecc.read_page ||
2754                      chip->ecc.read_page == nand_read_page_hwecc ||
2755                      !chip->ecc.write_page ||
2756                      chip->ecc.write_page == nand_write_page_hwecc)) {
2757                         printk(KERN_WARNING "No ECC functions supplied; "
2758                                "Hardware ECC not possible\n");
2759                         BUG();
2760                 }
2761                 /* Use standard syndrome read/write page function ? */
2762                 if (!chip->ecc.read_page)
2763                         chip->ecc.read_page = nand_read_page_syndrome;
2764                 if (!chip->ecc.write_page)
2765                         chip->ecc.write_page = nand_write_page_syndrome;
2766                 if (!chip->ecc.read_page_raw)
2767                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2768                 if (!chip->ecc.write_page_raw)
2769                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2770                 if (!chip->ecc.read_oob)
2771                         chip->ecc.read_oob = nand_read_oob_syndrome;
2772                 if (!chip->ecc.write_oob)
2773                         chip->ecc.write_oob = nand_write_oob_syndrome;
2774
2775                 if (mtd->writesize >= chip->ecc.size)
2776                         break;
2777                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2778                        "%d byte page size, fallback to SW ECC\n",
2779                        chip->ecc.size, mtd->writesize);
2780                 chip->ecc.mode = NAND_ECC_SOFT;
2781
2782         case NAND_ECC_SOFT:
2783                 chip->ecc.calculate = nand_calculate_ecc;
2784                 chip->ecc.correct = nand_correct_data;
2785                 chip->ecc.read_page = nand_read_page_swecc;
2786                 chip->ecc.read_subpage = nand_read_subpage;
2787                 chip->ecc.write_page = nand_write_page_swecc;
2788                 chip->ecc.read_page_raw = nand_read_page_raw;
2789                 chip->ecc.write_page_raw = nand_write_page_raw;
2790                 chip->ecc.read_oob = nand_read_oob_std;
2791                 chip->ecc.write_oob = nand_write_oob_std;
2792                 if (!chip->ecc.size)
2793                         chip->ecc.size = 256;
2794                 chip->ecc.bytes = 3;
2795                 break;
2796
2797         case NAND_ECC_NONE:
2798                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2799                        "This is not recommended !!\n");
2800                 chip->ecc.read_page = nand_read_page_raw;
2801                 chip->ecc.write_page = nand_write_page_raw;
2802                 chip->ecc.read_oob = nand_read_oob_std;
2803                 chip->ecc.read_page_raw = nand_read_page_raw;
2804                 chip->ecc.write_page_raw = nand_write_page_raw;
2805                 chip->ecc.write_oob = nand_write_oob_std;
2806                 chip->ecc.size = mtd->writesize;
2807                 chip->ecc.bytes = 0;
2808                 break;
2809
2810         default:
2811                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2812                        chip->ecc.mode);
2813                 BUG();
2814         }
2815
2816         /*
2817          * The number of bytes available for a client to place data into
2818          * the out of band area
2819          */
2820         chip->ecc.layout->oobavail = 0;
2821         for (i = 0; chip->ecc.layout->oobfree[i].length
2822                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2823                 chip->ecc.layout->oobavail +=
2824                         chip->ecc.layout->oobfree[i].length;
2825         mtd->oobavail = chip->ecc.layout->oobavail;
2826
2827         /*
2828          * Set the number of read / write steps for one page depending on ECC
2829          * mode
2830          */
2831         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2832         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2833                 printk(KERN_WARNING "Invalid ecc parameters\n");
2834                 BUG();
2835         }
2836         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2837
2838         /*
2839          * Allow subpage writes up to ecc.steps. Not possible for MLC
2840          * FLASH.
2841          */
2842         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2843             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2844                 switch(chip->ecc.steps) {
2845                 case 2:
2846                         mtd->subpage_sft = 1;
2847                         break;
2848                 case 4:
2849                 case 8:
2850                 case 16:
2851                         mtd->subpage_sft = 2;
2852                         break;
2853                 }
2854         }
2855         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2856
2857         /* Initialize state */
2858         chip->state = FL_READY;
2859
2860         /* De-select the device */
2861         chip->select_chip(mtd, -1);
2862
2863         /* Invalidate the pagebuffer reference */
2864         chip->pagebuf = -1;
2865
2866         /* Fill in remaining MTD driver data */
2867         mtd->type = MTD_NANDFLASH;
2868         mtd->flags = MTD_CAP_NANDFLASH;
2869         mtd->erase = nand_erase;
2870         mtd->point = NULL;
2871         mtd->unpoint = NULL;
2872         mtd->read = nand_read;
2873         mtd->write = nand_write;
2874         mtd->read_oob = nand_read_oob;
2875         mtd->write_oob = nand_write_oob;
2876         mtd->sync = nand_sync;
2877         mtd->lock = NULL;
2878         mtd->unlock = NULL;
2879         mtd->suspend = nand_suspend;
2880         mtd->resume = nand_resume;
2881         mtd->block_isbad = nand_block_isbad;
2882         mtd->block_markbad = nand_block_markbad;
2883
2884         /* propagate ecc.layout to mtd_info */
2885         mtd->ecclayout = chip->ecc.layout;
2886
2887         /* Check, if we should skip the bad block table scan */
2888         if (chip->options & NAND_SKIP_BBTSCAN)
2889                 return 0;
2890
2891         /* Build bad block table */
2892         return chip->scan_bbt(mtd);
2893 }
2894
2895 /* is_module_text_address() isn't exported, and it's mostly a pointless
2896    test if this is a module _anyway_ -- they'd have to try _really_ hard
2897    to call us from in-kernel code if the core NAND support is modular. */
2898 #ifdef MODULE
2899 #define caller_is_module() (1)
2900 #else
2901 #define caller_is_module() \
2902         is_module_text_address((unsigned long)__builtin_return_address(0))
2903 #endif
2904
2905 /**
2906  * nand_scan - [NAND Interface] Scan for the NAND device
2907  * @mtd:        MTD device structure
2908  * @maxchips:   Number of chips to scan for
2909  *
2910  * This fills out all the uninitialized function pointers
2911  * with the defaults.
2912  * The flash ID is read and the mtd/chip structures are
2913  * filled with the appropriate values.
2914  * The mtd->owner field must be set to the module of the caller
2915  *
2916  */
2917 int nand_scan(struct mtd_info *mtd, int maxchips)
2918 {
2919         int ret;
2920
2921         /* Many callers got this wrong, so check for it for a while... */
2922         if (!mtd->owner && caller_is_module()) {
2923                 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
2924                                 __func__);
2925                 BUG();
2926         }
2927
2928         ret = nand_scan_ident(mtd, maxchips);
2929         if (!ret)
2930                 ret = nand_scan_tail(mtd);
2931         return ret;
2932 }
2933
2934 /**
2935  * nand_release - [NAND Interface] Free resources held by the NAND device
2936  * @mtd:        MTD device structure
2937 */
2938 void nand_release(struct mtd_info *mtd)
2939 {
2940         struct nand_chip *chip = mtd->priv;
2941
2942 #ifdef CONFIG_MTD_PARTITIONS
2943         /* Deregister partitions */
2944         del_mtd_partitions(mtd);
2945 #endif
2946         /* Deregister the device */
2947         del_mtd_device(mtd);
2948
2949         /* Free bad block table memory */
2950         kfree(chip->bbt);
2951         if (!(chip->options & NAND_OWN_BUFFERS))
2952                 kfree(chip->buffers);
2953 }
2954
2955 EXPORT_SYMBOL_GPL(nand_scan);
2956 EXPORT_SYMBOL_GPL(nand_scan_ident);
2957 EXPORT_SYMBOL_GPL(nand_scan_tail);
2958 EXPORT_SYMBOL_GPL(nand_release);
2959
2960 static int __init nand_base_init(void)
2961 {
2962         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2963         return 0;
2964 }
2965
2966 static void __exit nand_base_exit(void)
2967 {
2968         led_trigger_unregister_simple(nand_led_trigger);
2969 }
2970
2971 module_init(nand_base_init);
2972 module_exit(nand_base_exit);
2973
2974 MODULE_LICENSE("GPL");
2975 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2976 MODULE_DESCRIPTION("Generic NAND flash driver code");