drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller NAND driver
   2  *
   3  * Copyright (c) 2006-2007 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/types.h>
  25 #include <linux/init.h>
  26 #include <linux/kernel.h>
  27 #include <linux/string.h>
  28 #include <linux/ioport.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/slab.h>
  31 #include <linux/interrupt.h>
  32
  33 #include <linux/mtd/mtd.h>
  34 #include <linux/mtd/nand.h>
  35 #include <linux/mtd/nand_ecc.h>
  36 #include <linux/mtd/partitions.h>
  37
  38 #include <asm/io.h>
  39 #include <asm/fsl_lbc.h>
  40
  41 #define MAX_BANKS 8
  42 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  43 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
  44
  45 struct fsl_elbc_ctrl;
  46
  47 /* mtd information per set */
  48
  49 struct fsl_elbc_mtd {
  50         struct mtd_info mtd;
  51         struct nand_chip chip;
  52         struct fsl_elbc_ctrl *ctrl;
  53
  54         struct device *dev;
  55         int bank;               /* Chip select bank number           */
  56         u8 __iomem *vbase;      /* Chip select base virtual address  */
  57         int page_size;          /* NAND page size (0=512, 1=2048)    */
  58         unsigned int fmr;       /* FCM Flash Mode Register value     */
  59 };
  60
  61 /* overview of the fsl elbc controller */
  62
  63 struct fsl_elbc_ctrl {
  64         struct nand_hw_control controller;
  65         struct fsl_elbc_mtd *chips[MAX_BANKS];
  66
  67         /* device info */
  68         struct device *dev;
  69         struct fsl_lbc_regs __iomem *regs;
  70         int irq;
  71         wait_queue_head_t irq_wait;
  72         unsigned int irq_status; /* status read from LTESR by irq handler */
  73         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  74         unsigned int page;       /* Last page written to / read from      */
  75         unsigned int read_bytes; /* Number of bytes read during command   */
  76         unsigned int column;     /* Saved column from SEQIN               */
  77         unsigned int index;      /* Pointer to next byte to 'read'        */
  78         unsigned int status;     /* status read from LTESR after last op  */
  79         unsigned int mdr;        /* UPM/FCM Data Register value           */
  80         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  81         unsigned int oob;        /* Non zero if operating on OOB data     */
  82         char *oob_poi;           /* Place to write ECC after read back    */
  83 };
  84
  85 /* These map to the positions used by the FCM hardware ECC generator */
  86
  87 /* Small Page FLASH with FMR[ECCM] = 0 */
  88 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  89         .eccbytes = 3,
  90         .eccpos = {6, 7, 8},
  91         .oobfree = { {0, 5}, {9, 7} },
  92 };
  93
  94 /* Small Page FLASH with FMR[ECCM] = 1 */
  95 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  96         .eccbytes = 3,
  97         .eccpos = {8, 9, 10},
  98         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
  99 };
 100
 101 /* Large Page FLASH with FMR[ECCM] = 0 */
 102 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
 103         .eccbytes = 12,
 104         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 105         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 106 };
 107
 108 /* Large Page FLASH with FMR[ECCM] = 1 */
 109 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 110         .eccbytes = 12,
 111         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 112         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 113 };
 114
 115 /*
 116  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 117  * 1, so we have to adjust bad block pattern. This pattern should be used for
 118  * x8 chips only. So far hardware does not support x16 chips anyway.
 119  */
 120 static u8 scan_ff_pattern[] = { 0xff, };
 121
 122 static struct nand_bbt_descr largepage_memorybased = {
 123         .options = 0,
 124         .offs = 0,
 125         .len = 1,
 126         .pattern = scan_ff_pattern,
 127 };
 128
 129 /*
 130  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
 131  * interfere with ECC positions, that's why we implement our own descriptors.
 132  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
 133  */
 134 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 135 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 136
 137 static struct nand_bbt_descr bbt_main_descr = {
 138         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 139                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 140         .offs = 11,
 141         .len = 4,
 142         .veroffs = 15,
 143         .maxblocks = 4,
 144         .pattern = bbt_pattern,
 145 };
 146
 147 static struct nand_bbt_descr bbt_mirror_descr = {
 148         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 149                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 150         .offs = 11,
 151         .len = 4,
 152         .veroffs = 15,
 153         .maxblocks = 4,
 154         .pattern = mirror_pattern,
 155 };
 156
 157 /*=================================*/
 158
 159 /*
 160  * Set up the FCM hardware block and page address fields, and the fcm
 161  * structure addr field to point to the correct FCM buffer in memory
 162  */
 163 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 164 {
 165         struct nand_chip *chip = mtd->priv;
 166         struct fsl_elbc_mtd *priv = chip->priv;
 167         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 168         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 169         int buf_num;
 170
 171         ctrl->page = page_addr;
 172
 173         out_be32(&lbc->fbar,
 174                  page_addr >> (chip->phys_erase_shift - chip->page_shift));
 175
 176         if (priv->page_size) {
 177                 out_be32(&lbc->fpar,
 178                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 179                          (oob ? FPAR_LP_MS : 0) | column);
 180                 buf_num = (page_addr & 1) << 2;
 181         } else {
 182                 out_be32(&lbc->fpar,
 183                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 184                          (oob ? FPAR_SP_MS : 0) | column);
 185                 buf_num = page_addr & 7;
 186         }
 187
 188         ctrl->addr = priv->vbase + buf_num * 1024;
 189         ctrl->index = column;
 190
 191         /* for OOB data point to the second half of the buffer */
 192         if (oob)
 193                 ctrl->index += priv->page_size ? 2048 : 512;
 194
 195         dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
 196                             "index %x, pes %d ps %d\n",
 197                  buf_num, ctrl->addr, priv->vbase, ctrl->index,
 198                  chip->phys_erase_shift, chip->page_shift);
 199 }
 200
 201 /*
 202  * execute FCM command and wait for it to complete
 203  */
 204 static int fsl_elbc_run_command(struct mtd_info *mtd)
 205 {
 206         struct nand_chip *chip = mtd->priv;
 207         struct fsl_elbc_mtd *priv = chip->priv;
 208         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 209         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 210
 211         /* Setup the FMR[OP] to execute without write protection */
 212         out_be32(&lbc->fmr, priv->fmr | 3);
 213         if (ctrl->use_mdr)
 214                 out_be32(&lbc->mdr, ctrl->mdr);
 215
 216         dev_vdbg(ctrl->dev,
 217                  "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 218                  in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 219         dev_vdbg(ctrl->dev,
 220                  "fsl_elbc_run_command: fbar=%08x fpar=%08x "
 221                  "fbcr=%08x bank=%d\n",
 222                  in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 223                  in_be32(&lbc->fbcr), priv->bank);
 224
 225         ctrl->irq_status = 0;
 226         /* execute special operation */
 227         out_be32(&lbc->lsor, priv->bank);
 228
 229         /* wait for FCM complete flag or timeout */
 230         wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
 231                            FCM_TIMEOUT_MSECS * HZ/1000);
 232         ctrl->status = ctrl->irq_status;
 233
 234         /* store mdr value in case it was needed */
 235         if (ctrl->use_mdr)
 236                 ctrl->mdr = in_be32(&lbc->mdr);
 237
 238         ctrl->use_mdr = 0;
 239
 240         if (ctrl->status != LTESR_CC) {
 241                 dev_info(ctrl->dev,
 242                          "command failed: fir %x fcr %x status %x mdr %x\n",
 243                          in_be32(&lbc->fir), in_be32(&lbc->fcr),
 244                          ctrl->status, ctrl->mdr);
 245                 return -EIO;
 246         }
 247
 248         return 0;
 249 }
 250
 251 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 252 {
 253         struct fsl_elbc_mtd *priv = chip->priv;
 254         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 255         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 256
 257         if (priv->page_size) {
 258                 out_be32(&lbc->fir,
 259                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 260                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 261                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 262                          (FIR_OP_CM1 << FIR_OP3_SHIFT) |
 263                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 264
 265                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 266                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 267         } else {
 268                 out_be32(&lbc->fir,
 269                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 270                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 271                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 272                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 273
 274                 if (oob)
 275                         out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 276                 else
 277                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 278         }
 279 }
 280
 281 /* cmdfunc send commands to the FCM */
 282 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 283                              int column, int page_addr)
 284 {
 285         struct nand_chip *chip = mtd->priv;
 286         struct fsl_elbc_mtd *priv = chip->priv;
 287         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 288         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 289
 290         ctrl->use_mdr = 0;
 291
 292         /* clear the read buffer */
 293         ctrl->read_bytes = 0;
 294         if (command != NAND_CMD_PAGEPROG)
 295                 ctrl->index = 0;
 296
 297         switch (command) {
 298         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 299         case NAND_CMD_READ1:
 300                 column += 256;
 301
 302         /* fall-through */
 303         case NAND_CMD_READ0:
 304                 dev_dbg(ctrl->dev,
 305                         "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 306                         " 0x%x, column: 0x%x.\n", page_addr, column);
 307
 308
 309                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 310                 set_addr(mtd, 0, page_addr, 0);
 311
 312                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 313                 ctrl->index += column;
 314
 315                 fsl_elbc_do_read(chip, 0);
 316                 fsl_elbc_run_command(mtd);
 317                 return;
 318
 319         /* READOOB reads only the OOB because no ECC is performed. */
 320         case NAND_CMD_READOOB:
 321                 dev_vdbg(ctrl->dev,
 322                          "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 323                          " 0x%x, column: 0x%x.\n", page_addr, column);
 324
 325                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 326                 set_addr(mtd, column, page_addr, 1);
 327
 328                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 329
 330                 fsl_elbc_do_read(chip, 1);
 331                 fsl_elbc_run_command(mtd);
 332                 return;
 333
 334         /* READID must read all 5 possible bytes while CEB is active */
 335         case NAND_CMD_READID:
 336                 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
 337
 338                 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 339                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 340                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 341                 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
 342                 /* 5 bytes for manuf, device and exts */
 343                 out_be32(&lbc->fbcr, 5);
 344                 ctrl->read_bytes = 5;
 345                 ctrl->use_mdr = 1;
 346                 ctrl->mdr = 0;
 347
 348                 set_addr(mtd, 0, 0, 0);
 349                 fsl_elbc_run_command(mtd);
 350                 return;
 351
 352         /* ERASE1 stores the block and page address */
 353         case NAND_CMD_ERASE1:
 354                 dev_vdbg(ctrl->dev,
 355                          "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 356                          "page_addr: 0x%x.\n", page_addr);
 357                 set_addr(mtd, 0, page_addr, 0);
 358                 return;
 359
 360         /* ERASE2 uses the block and page address from ERASE1 */
 361         case NAND_CMD_ERASE2:
 362                 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 363
 364                 out_be32(&lbc->fir,
 365                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 366                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 367                          (FIR_OP_CM2 << FIR_OP2_SHIFT) |
 368                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 369                          (FIR_OP_RS  << FIR_OP4_SHIFT));
 370
 371                 out_be32(&lbc->fcr,
 372                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 373                          (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
 374                          (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
 375
 376                 out_be32(&lbc->fbcr, 0);
 377                 ctrl->read_bytes = 0;
 378                 ctrl->use_mdr = 1;
 379
 380                 fsl_elbc_run_command(mtd);
 381                 return;
 382
 383         /* SEQIN sets up the addr buffer and all registers except the length */
 384         case NAND_CMD_SEQIN: {
 385                 __be32 fcr;
 386                 dev_vdbg(ctrl->dev,
 387                          "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 388                          "page_addr: 0x%x, column: 0x%x.\n",
 389                          page_addr, column);
 390
 391                 ctrl->column = column;
 392                 ctrl->oob = 0;
 393                 ctrl->use_mdr = 1;
 394
 395                 fcr = (NAND_CMD_STATUS   << FCR_CMD1_SHIFT) |
 396                       (NAND_CMD_SEQIN    << FCR_CMD2_SHIFT) |
 397                       (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
 398
 399                 if (priv->page_size) {
 400                         out_be32(&lbc->fir,
 401                                  (FIR_OP_CM2 << FIR_OP0_SHIFT) |
 402                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 403                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 404                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 405                                  (FIR_OP_CM3 << FIR_OP4_SHIFT) |
 406                                  (FIR_OP_CW1 << FIR_OP5_SHIFT) |
 407                                  (FIR_OP_RS  << FIR_OP6_SHIFT));
 408                 } else {
 409                         out_be32(&lbc->fir,
 410                                  (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 411                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 412                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 413                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 414                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 415                                  (FIR_OP_CM3 << FIR_OP5_SHIFT) |
 416                                  (FIR_OP_CW1 << FIR_OP6_SHIFT) |
 417                                  (FIR_OP_RS  << FIR_OP7_SHIFT));
 418
 419                         if (column >= mtd->writesize) {
 420                                 /* OOB area --> READOOB */
 421                                 column -= mtd->writesize;
 422                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 423                                 ctrl->oob = 1;
 424                         } else {
 425                                 WARN_ON(column != 0);
 426                                 /* First 256 bytes --> READ0 */
 427                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 428                         }
 429                 }
 430
 431                 out_be32(&lbc->fcr, fcr);
 432                 set_addr(mtd, column, page_addr, ctrl->oob);
 433                 return;
 434         }
 435
 436         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 437         case NAND_CMD_PAGEPROG: {
 438                 int full_page;
 439                 dev_vdbg(ctrl->dev,
 440                          "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 441                          "writing %d bytes.\n", ctrl->index);
 442
 443                 /* if the write did not start at 0 or is not a full page
 444                  * then set the exact length, otherwise use a full page
 445                  * write so the HW generates the ECC.
 446                  */
 447                 if (ctrl->oob || ctrl->column != 0 ||
 448                     ctrl->index != mtd->writesize + mtd->oobsize) {
 449                         out_be32(&lbc->fbcr, ctrl->index);
 450                         full_page = 0;
 451                 } else {
 452                         out_be32(&lbc->fbcr, 0);
 453                         full_page = 1;
 454                 }
 455
 456                 fsl_elbc_run_command(mtd);
 457
 458                 /* Read back the page in order to fill in the ECC for the
 459                  * caller.  Is this really needed?
 460                  */
 461                 if (full_page && ctrl->oob_poi) {
 462                         out_be32(&lbc->fbcr, 3);
 463                         set_addr(mtd, 6, page_addr, 1);
 464
 465                         ctrl->read_bytes = mtd->writesize + 9;
 466
 467                         fsl_elbc_do_read(chip, 1);
 468                         fsl_elbc_run_command(mtd);
 469
 470                         memcpy_fromio(ctrl->oob_poi + 6,
 471                                       &ctrl->addr[ctrl->index], 3);
 472                         ctrl->index += 3;
 473                 }
 474
 475                 ctrl->oob_poi = NULL;
 476                 return;
 477         }
 478
 479         /* CMD_STATUS must read the status byte while CEB is active */
 480         /* Note - it does not wait for the ready line */
 481         case NAND_CMD_STATUS:
 482                 out_be32(&lbc->fir,
 483                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 484                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 485                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 486                 out_be32(&lbc->fbcr, 1);
 487                 set_addr(mtd, 0, 0, 0);
 488                 ctrl->read_bytes = 1;
 489
 490                 fsl_elbc_run_command(mtd);
 491
 492                 /* The chip always seems to report that it is
 493                  * write-protected, even when it is not.
 494                  */
 495                 setbits8(ctrl->addr, NAND_STATUS_WP);
 496                 return;
 497
 498         /* RESET without waiting for the ready line */
 499         case NAND_CMD_RESET:
 500                 dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 501                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 502                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 503                 fsl_elbc_run_command(mtd);
 504                 return;
 505
 506         default:
 507                 dev_err(ctrl->dev,
 508                         "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 509                         command);
 510         }
 511 }
 512
 513 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 514 {
 515         /* The hardware does not seem to support multiple
 516          * chips per bank.
 517          */
 518 }
 519
 520 /*
 521  * Write buf to the FCM Controller Data Buffer
 522  */
 523 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 524 {
 525         struct nand_chip *chip = mtd->priv;
 526         struct fsl_elbc_mtd *priv = chip->priv;
 527         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 528         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 529
 530         if (len <= 0) {
 531                 dev_err(ctrl->dev, "write_buf of %d bytes", len);
 532                 ctrl->status = 0;
 533                 return;
 534         }
 535
 536         if ((unsigned int)len > bufsize - ctrl->index) {
 537                 dev_err(ctrl->dev,
 538                         "write_buf beyond end of buffer "
 539                         "(%d requested, %u available)\n",
 540                         len, bufsize - ctrl->index);
 541                 len = bufsize - ctrl->index;
 542         }
 543
 544         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 545         /*
 546          * This is workaround for the weird elbc hangs during nand write,
 547          * Scott Wood says: "...perhaps difference in how long it takes a
 548          * write to make it through the localbus compared to a write to IMMR
 549          * is causing problems, and sync isn't helping for some reason."
 550          * Reading back the last byte helps though.
 551          */
 552         in_8(&ctrl->addr[ctrl->index] + len - 1);
 553
 554         ctrl->index += len;
 555 }
 556
 557 /*
 558  * read a byte from either the FCM hardware buffer if it has any data left
 559  * otherwise issue a command to read a single byte.
 560  */
 561 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 562 {
 563         struct nand_chip *chip = mtd->priv;
 564         struct fsl_elbc_mtd *priv = chip->priv;
 565         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 566
 567         /* If there are still bytes in the FCM, then use the next byte. */
 568         if (ctrl->index < ctrl->read_bytes)
 569                 return in_8(&ctrl->addr[ctrl->index++]);
 570
 571         dev_err(ctrl->dev, "read_byte beyond end of buffer\n");
 572         return ERR_BYTE;
 573 }
 574
 575 /*
 576  * Read from the FCM Controller Data Buffer
 577  */
 578 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 579 {
 580         struct nand_chip *chip = mtd->priv;
 581         struct fsl_elbc_mtd *priv = chip->priv;
 582         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 583         int avail;
 584
 585         if (len < 0)
 586                 return;
 587
 588         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 589         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 590         ctrl->index += avail;
 591
 592         if (len > avail)
 593                 dev_err(ctrl->dev,
 594                         "read_buf beyond end of buffer "
 595                         "(%d requested, %d available)\n",
 596                         len, avail);
 597 }
 598
 599 /*
 600  * Verify buffer against the FCM Controller Data Buffer
 601  */
 602 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 603 {
 604         struct nand_chip *chip = mtd->priv;
 605         struct fsl_elbc_mtd *priv = chip->priv;
 606         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 607         int i;
 608
 609         if (len < 0) {
 610                 dev_err(ctrl->dev, "write_buf of %d bytes", len);
 611                 return -EINVAL;
 612         }
 613
 614         if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
 615                 dev_err(ctrl->dev,
 616                         "verify_buf beyond end of buffer "
 617                         "(%d requested, %u available)\n",
 618                         len, ctrl->read_bytes - ctrl->index);
 619
 620                 ctrl->index = ctrl->read_bytes;
 621                 return -EINVAL;
 622         }
 623
 624         for (i = 0; i < len; i++)
 625                 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
 626                         break;
 627
 628         ctrl->index += len;
 629         return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
 630 }
 631
 632 /* This function is called after Program and Erase Operations to
 633  * check for success or failure.
 634  */
 635 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 636 {
 637         struct fsl_elbc_mtd *priv = chip->priv;
 638         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 639
 640         if (ctrl->status != LTESR_CC)
 641                 return NAND_STATUS_FAIL;
 642
 643         /* The chip always seems to report that it is
 644          * write-protected, even when it is not.
 645          */
 646         return (ctrl->mdr & 0xff) | NAND_STATUS_WP;
 647 }
 648
 649 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 650 {
 651         struct nand_chip *chip = mtd->priv;
 652         struct fsl_elbc_mtd *priv = chip->priv;
 653         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 654         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 655         unsigned int al;
 656
 657         /* calculate FMR Address Length field */
 658         al = 0;
 659         if (chip->pagemask & 0xffff0000)
 660                 al++;
 661         if (chip->pagemask & 0xff000000)
 662                 al++;
 663
 664         /* add to ECCM mode set in fsl_elbc_init */
 665         priv->fmr |= (12 << FMR_CWTO_SHIFT) |  /* Timeout > 12 ms */
 666                      (al << FMR_AL_SHIFT);
 667
 668         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n",
 669                 chip->numchips);
 670         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
 671                 chip->chipsize);
 672         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
 673                 chip->pagemask);
 674         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
 675                 chip->chip_delay);
 676         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
 677                 chip->badblockpos);
 678         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
 679                 chip->chip_shift);
 680         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n",
 681                 chip->page_shift);
 682         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
 683                 chip->phys_erase_shift);
 684         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
 685                 chip->ecclayout);
 686         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
 687                 chip->ecc.mode);
 688         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
 689                 chip->ecc.steps);
 690         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
 691                 chip->ecc.bytes);
 692         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
 693                 chip->ecc.total);
 694         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
 695                 chip->ecc.layout);
 696         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
 697         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
 698         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
 699                 mtd->erasesize);
 700         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n",
 701                 mtd->writesize);
 702         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
 703                 mtd->oobsize);
 704
 705         /* adjust Option Register and ECC to match Flash page size */
 706         if (mtd->writesize == 512) {
 707                 priv->page_size = 0;
 708                 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 709         } else if (mtd->writesize == 2048) {
 710                 priv->page_size = 1;
 711                 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 712                 /* adjust ecc setup if needed */
 713                 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 714                     BR_DECC_CHK_GEN) {
 715                         chip->ecc.size = 512;
 716                         chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 717                                            &fsl_elbc_oob_lp_eccm1 :
 718                                            &fsl_elbc_oob_lp_eccm0;
 719                         chip->badblock_pattern = &largepage_memorybased;
 720                 }
 721         } else {
 722                 dev_err(ctrl->dev,
 723                         "fsl_elbc_init: page size %d is not supported\n",
 724                         mtd->writesize);
 725                 return -1;
 726         }
 727
 728         return 0;
 729 }
 730
 731 static int fsl_elbc_read_page(struct mtd_info *mtd,
 732                               struct nand_chip *chip,
 733                               uint8_t *buf,
 734                               int page)
 735 {
 736         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 737         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 738
 739         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 740                 mtd->ecc_stats.failed++;
 741
 742         return 0;
 743 }
 744
 745 /* ECC will be calculated automatically, and errors will be detected in
 746  * waitfunc.
 747  */
 748 static void fsl_elbc_write_page(struct mtd_info *mtd,
 749                                 struct nand_chip *chip,
 750                                 const uint8_t *buf)
 751 {
 752         struct fsl_elbc_mtd *priv = chip->priv;
 753         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 754
 755         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 756         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 757
 758         ctrl->oob_poi = chip->oob_poi;
 759 }
 760
 761 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 762 {
 763         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 764         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 765         struct nand_chip *chip = &priv->chip;
 766
 767         dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
 768
 769         /* Fill in fsl_elbc_mtd structure */
 770         priv->mtd.priv = chip;
 771         priv->mtd.owner = THIS_MODULE;
 772
 773         /* Set the ECCM according to the settings in bootloader.*/
 774         priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM;
 775
 776         /* fill in nand_chip structure */
 777         /* set up function call table */
 778         chip->read_byte = fsl_elbc_read_byte;
 779         chip->write_buf = fsl_elbc_write_buf;
 780         chip->read_buf = fsl_elbc_read_buf;
 781         chip->verify_buf = fsl_elbc_verify_buf;
 782         chip->select_chip = fsl_elbc_select_chip;
 783         chip->cmdfunc = fsl_elbc_cmdfunc;
 784         chip->waitfunc = fsl_elbc_wait;
 785
 786         chip->bbt_td = &bbt_main_descr;
 787         chip->bbt_md = &bbt_mirror_descr;
 788
 789         /* set up nand options */
 790         chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
 791                         NAND_USE_FLASH_BBT;
 792
 793         chip->controller = &ctrl->controller;
 794         chip->priv = priv;
 795
 796         chip->ecc.read_page = fsl_elbc_read_page;
 797         chip->ecc.write_page = fsl_elbc_write_page;
 798
 799         /* If CS Base Register selects full hardware ECC then use it */
 800         if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 801             BR_DECC_CHK_GEN) {
 802                 chip->ecc.mode = NAND_ECC_HW;
 803                 /* put in small page settings and adjust later if needed */
 804                 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 805                                 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
 806                 chip->ecc.size = 512;
 807                 chip->ecc.bytes = 3;
 808         } else {
 809                 /* otherwise fall back to default software ECC */
 810                 chip->ecc.mode = NAND_ECC_SOFT;
 811         }
 812
 813         return 0;
 814 }
 815
 816 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
 817 {
 818         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 819
 820         nand_release(&priv->mtd);
 821
 822         kfree(priv->mtd.name);
 823
 824         if (priv->vbase)
 825                 iounmap(priv->vbase);
 826
 827         ctrl->chips[priv->bank] = NULL;
 828         kfree(priv);
 829
 830         return 0;
 831 }
 832
 833 static int __devinit fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
 834                                          struct device_node *node)
 835 {
 836         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 837         struct fsl_elbc_mtd *priv;
 838         struct resource res;
 839 #ifdef CONFIG_MTD_PARTITIONS
 840         static const char *part_probe_types[]
 841                 = { "cmdlinepart", "RedBoot", NULL };
 842         struct mtd_partition *parts;
 843 #endif
 844         int ret;
 845         int bank;
 846
 847         /* get, allocate and map the memory resource */
 848         ret = of_address_to_resource(node, 0, &res);
 849         if (ret) {
 850                 dev_err(ctrl->dev, "failed to get resource\n");
 851                 return ret;
 852         }
 853
 854         /* find which chip select it is connected to */
 855         for (bank = 0; bank < MAX_BANKS; bank++)
 856                 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
 857                     (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
 858                     (in_be32(&lbc->bank[bank].br) &
 859                      in_be32(&lbc->bank[bank].or) & BR_BA)
 860                      == res.start)
 861                         break;
 862
 863         if (bank >= MAX_BANKS) {
 864                 dev_err(ctrl->dev, "address did not match any chip selects\n");
 865                 return -ENODEV;
 866         }
 867
 868         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 869         if (!priv)
 870                 return -ENOMEM;
 871
 872         ctrl->chips[bank] = priv;
 873         priv->bank = bank;
 874         priv->ctrl = ctrl;
 875         priv->dev = ctrl->dev;
 876
 877         priv->vbase = ioremap(res.start, resource_size(&res));
 878         if (!priv->vbase) {
 879                 dev_err(ctrl->dev, "failed to map chip region\n");
 880                 ret = -ENOMEM;
 881                 goto err;
 882         }
 883
 884         priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
 885         if (!priv->mtd.name) {
 886                 ret = -ENOMEM;
 887                 goto err;
 888         }
 889
 890         ret = fsl_elbc_chip_init(priv);
 891         if (ret)
 892                 goto err;
 893
 894         ret = nand_scan_ident(&priv->mtd, 1, NULL);
 895         if (ret)
 896                 goto err;
 897
 898         ret = fsl_elbc_chip_init_tail(&priv->mtd);
 899         if (ret)
 900                 goto err;
 901
 902         ret = nand_scan_tail(&priv->mtd);
 903         if (ret)
 904                 goto err;
 905
 906 #ifdef CONFIG_MTD_PARTITIONS
 907         /* First look for RedBoot table or partitions on the command
 908          * line, these take precedence over device tree information */
 909         ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
 910         if (ret < 0)
 911                 goto err;
 912
 913 #ifdef CONFIG_MTD_OF_PARTS
 914         if (ret == 0) {
 915                 ret = of_mtd_parse_partitions(priv->dev, node, &parts);
 916                 if (ret < 0)
 917                         goto err;
 918         }
 919 #endif
 920
 921         if (ret > 0)
 922                 add_mtd_partitions(&priv->mtd, parts, ret);
 923         else
 924 #endif
 925                 add_mtd_device(&priv->mtd);
 926
 927         printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
 928                (unsigned long long)res.start, priv->bank);
 929         return 0;
 930
 931 err:
 932         fsl_elbc_chip_remove(priv);
 933         return ret;
 934 }
 935
 936 static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
 937 {
 938         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 939
 940         /*
 941          * NAND transactions can tie up the bus for a long time, so set the
 942          * bus timeout to max by clearing LBCR[BMT] (highest base counter
 943          * value) and setting LBCR[BMTPS] to the highest prescaler value.
 944          */
 945         clrsetbits_be32(&lbc->lbcr, LBCR_BMT, 15);
 946
 947         /* clear event registers */
 948         setbits32(&lbc->ltesr, LTESR_NAND_MASK);
 949         out_be32(&lbc->lteatr, 0);
 950
 951         /* Enable interrupts for any detected events */
 952         out_be32(&lbc->lteir, LTESR_NAND_MASK);
 953
 954         ctrl->read_bytes = 0;
 955         ctrl->index = 0;
 956         ctrl->addr = NULL;
 957
 958         return 0;
 959 }
 960
 961 static int fsl_elbc_ctrl_remove(struct of_device *ofdev)
 962 {
 963         struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
 964         int i;
 965
 966         for (i = 0; i < MAX_BANKS; i++)
 967                 if (ctrl->chips[i])
 968                         fsl_elbc_chip_remove(ctrl->chips[i]);
 969
 970         if (ctrl->irq)
 971                 free_irq(ctrl->irq, ctrl);
 972
 973         if (ctrl->regs)
 974                 iounmap(ctrl->regs);
 975
 976         dev_set_drvdata(&ofdev->dev, NULL);
 977         kfree(ctrl);
 978         return 0;
 979 }
 980
 981 /* NOTE: This interrupt is also used to report other localbus events,
 982  * such as transaction errors on other chipselects.  If we want to
 983  * capture those, we'll need to move the IRQ code into a shared
 984  * LBC driver.
 985  */
 986
 987 static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
 988 {
 989         struct fsl_elbc_ctrl *ctrl = data;
 990         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 991         __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
 992
 993         if (status) {
 994                 out_be32(&lbc->ltesr, status);
 995                 out_be32(&lbc->lteatr, 0);
 996
 997                 ctrl->irq_status = status;
 998                 smp_wmb();
 999                 wake_up(&ctrl->irq_wait);
1000
1001                 return IRQ_HANDLED;
1002         }
1003
1004         return IRQ_NONE;
1005 }
1006
1007 /* fsl_elbc_ctrl_probe
1008  *
1009  * called by device layer when it finds a device matching
1010  * one our driver can handled. This code allocates all of
1011  * the resources needed for the controller only.  The
1012  * resources for the NAND banks themselves are allocated
1013  * in the chip probe function.
1014 */
1015
1016 static int __devinit fsl_elbc_ctrl_probe(struct of_device *ofdev,
1017                                          const struct of_device_id *match)
1018 {
1019         struct device_node *child;
1020         struct fsl_elbc_ctrl *ctrl;
1021         int ret;
1022
1023         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1024         if (!ctrl)
1025                 return -ENOMEM;
1026
1027         dev_set_drvdata(&ofdev->dev, ctrl);
1028
1029         spin_lock_init(&ctrl->controller.lock);
1030         init_waitqueue_head(&ctrl->controller.wq);
1031         init_waitqueue_head(&ctrl->irq_wait);
1032
1033         ctrl->regs = of_iomap(ofdev->dev.of_node, 0);
1034         if (!ctrl->regs) {
1035                 dev_err(&ofdev->dev, "failed to get memory region\n");
1036                 ret = -ENODEV;
1037                 goto err;
1038         }
1039
1040         ctrl->irq = of_irq_to_resource(ofdev->dev.of_node, 0, NULL);
1041         if (ctrl->irq == NO_IRQ) {
1042                 dev_err(&ofdev->dev, "failed to get irq resource\n");
1043                 ret = -ENODEV;
1044                 goto err;
1045         }
1046
1047         ctrl->dev = &ofdev->dev;
1048
1049         ret = fsl_elbc_ctrl_init(ctrl);
1050         if (ret < 0)
1051                 goto err;
1052
1053         ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl);
1054         if (ret != 0) {
1055                 dev_err(&ofdev->dev, "failed to install irq (%d)\n",
1056                         ctrl->irq);
1057                 ret = ctrl->irq;
1058                 goto err;
1059         }
1060
1061         for_each_child_of_node(ofdev->dev.of_node, child)
1062                 if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
1063                         fsl_elbc_chip_probe(ctrl, child);
1064
1065         return 0;
1066
1067 err:
1068         fsl_elbc_ctrl_remove(ofdev);
1069         return ret;
1070 }
1071
1072 static const struct of_device_id fsl_elbc_match[] = {
1073         {
1074                 .compatible = "fsl,elbc",
1075         },
1076         {}
1077 };
1078
1079 static struct of_platform_driver fsl_elbc_ctrl_driver = {
1080         .driver = {
1081                 .name = "fsl-elbc",
1082                 .owner = THIS_MODULE,
1083                 .of_match_table = fsl_elbc_match,
1084         },
1085         .probe = fsl_elbc_ctrl_probe,
1086         .remove = fsl_elbc_ctrl_remove,
1087 };
1088
1089 static int __init fsl_elbc_init(void)
1090 {
1091         return of_register_platform_driver(&fsl_elbc_ctrl_driver);
1092 }
1093
1094 static void __exit fsl_elbc_exit(void)
1095 {
1096         of_unregister_platform_driver(&fsl_elbc_ctrl_driver);
1097 }
1098
1099 module_init(fsl_elbc_init);
1100 module_exit(fsl_elbc_exit);
1101
1102 MODULE_LICENSE("GPL");
1103 MODULE_AUTHOR("Freescale");
1104 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");