drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/slab.h>
  21 #include <linux/scatterlist.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include <linux/leds.h>
  25
  26 #include <linux/mmc/mmc.h>
  27 #include <linux/mmc/host.h>
  28
  29 #include "sdhci.h"
  30
  31 #define DRIVER_NAME "sdhci"
  32
  33 #define DBG(f, x...) \
  34         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  35
  36 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  37         defined(CONFIG_MMC_SDHCI_MODULE))
  38 #define SDHCI_USE_LEDS_CLASS
  39 #endif
  40
  41 #define MAX_TUNING_LOOP 40
  42
  43 static unsigned int debug_quirks = 0;
  44
  45 static void sdhci_finish_data(struct sdhci_host *);
  46
  47 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  48 static void sdhci_finish_command(struct sdhci_host *);
  49 static int sdhci_execute_tuning(struct mmc_host *mmc);
  50 static void sdhci_tuning_timer(unsigned long data);
  51
  52 static void sdhci_dumpregs(struct sdhci_host *host)
  53 {
  54         printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  55                 mmc_hostname(host->mmc));
  56
  57         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  58                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  59                 sdhci_readw(host, SDHCI_HOST_VERSION));
  60         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  61                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  62                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  63         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  64                 sdhci_readl(host, SDHCI_ARGUMENT),
  65                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  66         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  67                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  68                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  69         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  70                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  71                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  72         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  73                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  74                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  75         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  76                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  77                 sdhci_readl(host, SDHCI_INT_STATUS));
  78         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  79                 sdhci_readl(host, SDHCI_INT_ENABLE),
  80                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  81         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  82                 sdhci_readw(host, SDHCI_ACMD12_ERR),
  83                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  84         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
  85                 sdhci_readl(host, SDHCI_CAPABILITIES),
  86                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
  87         printk(KERN_DEBUG DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
  88                 sdhci_readw(host, SDHCI_COMMAND),
  89                 sdhci_readl(host, SDHCI_MAX_CURRENT));
  90         printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
  91                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
  92
  93         if (host->flags & SDHCI_USE_ADMA)
  94                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
  95                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
  96                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
  97
  98         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  99 }
 100
 101 /*****************************************************************************\
 102  *                                                                           *
 103  * Low level functions                                                       *
 104  *                                                                           *
 105 \*****************************************************************************/
 106
 107 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 108 {
 109         u32 ier;
 110
 111         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 112         ier &= ~clear;
 113         ier |= set;
 114         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 115         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 116 }
 117
 118 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 119 {
 120         sdhci_clear_set_irqs(host, 0, irqs);
 121 }
 122
 123 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 124 {
 125         sdhci_clear_set_irqs(host, irqs, 0);
 126 }
 127
 128 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 129 {
 130         u32 present, irqs;
 131
 132         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
 133                 return;
 134
 135         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 136                               SDHCI_CARD_PRESENT;
 137         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 138
 139         if (enable)
 140                 sdhci_unmask_irqs(host, irqs);
 141         else
 142                 sdhci_mask_irqs(host, irqs);
 143 }
 144
 145 static void sdhci_enable_card_detection(struct sdhci_host *host)
 146 {
 147         sdhci_set_card_detection(host, true);
 148 }
 149
 150 static void sdhci_disable_card_detection(struct sdhci_host *host)
 151 {
 152         sdhci_set_card_detection(host, false);
 153 }
 154
 155 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 156 {
 157         unsigned long timeout;
 158         u32 uninitialized_var(ier);
 159
 160         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 161                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 162                         SDHCI_CARD_PRESENT))
 163                         return;
 164         }
 165
 166         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 167                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 168
 169         if (host->ops->platform_reset_enter)
 170                 host->ops->platform_reset_enter(host, mask);
 171
 172         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 173
 174         if (mask & SDHCI_RESET_ALL)
 175                 host->clock = 0;
 176
 177         /* Wait max 100 ms */
 178         timeout = 100;
 179
 180         /* hw clears the bit when it's done */
 181         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 182                 if (timeout == 0) {
 183                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 184                                 mmc_hostname(host->mmc), (int)mask);
 185                         sdhci_dumpregs(host);
 186                         return;
 187                 }
 188                 timeout--;
 189                 mdelay(1);
 190         }
 191
 192         if (host->ops->platform_reset_exit)
 193                 host->ops->platform_reset_exit(host, mask);
 194
 195         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 196                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 197 }
 198
 199 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 200
 201 static void sdhci_init(struct sdhci_host *host, int soft)
 202 {
 203         if (soft)
 204                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 205         else
 206                 sdhci_reset(host, SDHCI_RESET_ALL);
 207
 208         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 209                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 210                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 211                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 212                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 213
 214         if (soft) {
 215                 /* force clock reconfiguration */
 216                 host->clock = 0;
 217                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 218         }
 219 }
 220
 221 static void sdhci_reinit(struct sdhci_host *host)
 222 {
 223         sdhci_init(host, 0);
 224         sdhci_enable_card_detection(host);
 225 }
 226
 227 static void sdhci_activate_led(struct sdhci_host *host)
 228 {
 229         u8 ctrl;
 230
 231         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 232         ctrl |= SDHCI_CTRL_LED;
 233         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 234 }
 235
 236 static void sdhci_deactivate_led(struct sdhci_host *host)
 237 {
 238         u8 ctrl;
 239
 240         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 241         ctrl &= ~SDHCI_CTRL_LED;
 242         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 243 }
 244
 245 #ifdef SDHCI_USE_LEDS_CLASS
 246 static void sdhci_led_control(struct led_classdev *led,
 247         enum led_brightness brightness)
 248 {
 249         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 250         unsigned long flags;
 251
 252         spin_lock_irqsave(&host->lock, flags);
 253
 254         if (brightness == LED_OFF)
 255                 sdhci_deactivate_led(host);
 256         else
 257                 sdhci_activate_led(host);
 258
 259         spin_unlock_irqrestore(&host->lock, flags);
 260 }
 261 #endif
 262
 263 /*****************************************************************************\
 264  *                                                                           *
 265  * Core functions                                                            *
 266  *                                                                           *
 267 \*****************************************************************************/
 268
 269 static void sdhci_read_block_pio(struct sdhci_host *host)
 270 {
 271         unsigned long flags;
 272         size_t blksize, len, chunk;
 273         u32 uninitialized_var(scratch);
 274         u8 *buf;
 275
 276         DBG("PIO reading\n");
 277
 278         blksize = host->data->blksz;
 279         chunk = 0;
 280
 281         local_irq_save(flags);
 282
 283         while (blksize) {
 284                 if (!sg_miter_next(&host->sg_miter))
 285                         BUG();
 286
 287                 len = min(host->sg_miter.length, blksize);
 288
 289                 blksize -= len;
 290                 host->sg_miter.consumed = len;
 291
 292                 buf = host->sg_miter.addr;
 293
 294                 while (len) {
 295                         if (chunk == 0) {
 296                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 297                                 chunk = 4;
 298                         }
 299
 300                         *buf = scratch & 0xFF;
 301
 302                         buf++;
 303                         scratch >>= 8;
 304                         chunk--;
 305                         len--;
 306                 }
 307         }
 308
 309         sg_miter_stop(&host->sg_miter);
 310
 311         local_irq_restore(flags);
 312 }
 313
 314 static void sdhci_write_block_pio(struct sdhci_host *host)
 315 {
 316         unsigned long flags;
 317         size_t blksize, len, chunk;
 318         u32 scratch;
 319         u8 *buf;
 320
 321         DBG("PIO writing\n");
 322
 323         blksize = host->data->blksz;
 324         chunk = 0;
 325         scratch = 0;
 326
 327         local_irq_save(flags);
 328
 329         while (blksize) {
 330                 if (!sg_miter_next(&host->sg_miter))
 331                         BUG();
 332
 333                 len = min(host->sg_miter.length, blksize);
 334
 335                 blksize -= len;
 336                 host->sg_miter.consumed = len;
 337
 338                 buf = host->sg_miter.addr;
 339
 340                 while (len) {
 341                         scratch |= (u32)*buf << (chunk * 8);
 342
 343                         buf++;
 344                         chunk++;
 345                         len--;
 346
 347                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 348                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 349                                 chunk = 0;
 350                                 scratch = 0;
 351                         }
 352                 }
 353         }
 354
 355         sg_miter_stop(&host->sg_miter);
 356
 357         local_irq_restore(flags);
 358 }
 359
 360 static void sdhci_transfer_pio(struct sdhci_host *host)
 361 {
 362         u32 mask;
 363
 364         BUG_ON(!host->data);
 365
 366         if (host->blocks == 0)
 367                 return;
 368
 369         if (host->data->flags & MMC_DATA_READ)
 370                 mask = SDHCI_DATA_AVAILABLE;
 371         else
 372                 mask = SDHCI_SPACE_AVAILABLE;
 373
 374         /*
 375          * Some controllers (JMicron JMB38x) mess up the buffer bits
 376          * for transfers < 4 bytes. As long as it is just one block,
 377          * we can ignore the bits.
 378          */
 379         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 380                 (host->data->blocks == 1))
 381                 mask = ~0;
 382
 383         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 384                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 385                         udelay(100);
 386
 387                 if (host->data->flags & MMC_DATA_READ)
 388                         sdhci_read_block_pio(host);
 389                 else
 390                         sdhci_write_block_pio(host);
 391
 392                 host->blocks--;
 393                 if (host->blocks == 0)
 394                         break;
 395         }
 396
 397         DBG("PIO transfer complete.\n");
 398 }
 399
 400 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 401 {
 402         local_irq_save(*flags);
 403         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 404 }
 405
 406 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 407 {
 408         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 409         local_irq_restore(*flags);
 410 }
 411
 412 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 413 {
 414         __le32 *dataddr = (__le32 __force *)(desc + 4);
 415         __le16 *cmdlen = (__le16 __force *)desc;
 416
 417         /* SDHCI specification says ADMA descriptors should be 4 byte
 418          * aligned, so using 16 or 32bit operations should be safe. */
 419
 420         cmdlen[0] = cpu_to_le16(cmd);
 421         cmdlen[1] = cpu_to_le16(len);
 422
 423         dataddr[0] = cpu_to_le32(addr);
 424 }
 425
 426 static int sdhci_adma_table_pre(struct sdhci_host *host,
 427         struct mmc_data *data)
 428 {
 429         int direction;
 430
 431         u8 *desc;
 432         u8 *align;
 433         dma_addr_t addr;
 434         dma_addr_t align_addr;
 435         int len, offset;
 436
 437         struct scatterlist *sg;
 438         int i;
 439         char *buffer;
 440         unsigned long flags;
 441
 442         /*
 443          * The spec does not specify endianness of descriptor table.
 444          * We currently guess that it is LE.
 445          */
 446
 447         if (data->flags & MMC_DATA_READ)
 448                 direction = DMA_FROM_DEVICE;
 449         else
 450                 direction = DMA_TO_DEVICE;
 451
 452         /*
 453          * The ADMA descriptor table is mapped further down as we
 454          * need to fill it with data first.
 455          */
 456
 457         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 458                 host->align_buffer, 128 * 4, direction);
 459         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 460                 goto fail;
 461         BUG_ON(host->align_addr & 0x3);
 462
 463         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 464                 data->sg, data->sg_len, direction);
 465         if (host->sg_count == 0)
 466                 goto unmap_align;
 467
 468         desc = host->adma_desc;
 469         align = host->align_buffer;
 470
 471         align_addr = host->align_addr;
 472
 473         for_each_sg(data->sg, sg, host->sg_count, i) {
 474                 addr = sg_dma_address(sg);
 475                 len = sg_dma_len(sg);
 476
 477                 /*
 478                  * The SDHCI specification states that ADMA
 479                  * addresses must be 32-bit aligned. If they
 480                  * aren't, then we use a bounce buffer for
 481                  * the (up to three) bytes that screw up the
 482                  * alignment.
 483                  */
 484                 offset = (4 - (addr & 0x3)) & 0x3;
 485                 if (offset) {
 486                         if (data->flags & MMC_DATA_WRITE) {
 487                                 buffer = sdhci_kmap_atomic(sg, &flags);
 488                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 489                                 memcpy(align, buffer, offset);
 490                                 sdhci_kunmap_atomic(buffer, &flags);
 491                         }
 492
 493                         /* tran, valid */
 494                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 495
 496                         BUG_ON(offset > 65536);
 497
 498                         align += 4;
 499                         align_addr += 4;
 500
 501                         desc += 8;
 502
 503                         addr += offset;
 504                         len -= offset;
 505                 }
 506
 507                 BUG_ON(len > 65536);
 508
 509                 /* tran, valid */
 510                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 511                 desc += 8;
 512
 513                 /*
 514                  * If this triggers then we have a calculation bug
 515                  * somewhere. :/
 516                  */
 517                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 518         }
 519
 520         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 521                 /*
 522                 * Mark the last descriptor as the terminating descriptor
 523                 */
 524                 if (desc != host->adma_desc) {
 525                         desc -= 8;
 526                         desc[0] |= 0x2; /* end */
 527                 }
 528         } else {
 529                 /*
 530                 * Add a terminating entry.
 531                 */
 532
 533                 /* nop, end, valid */
 534                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 535         }
 536
 537         /*
 538          * Resync align buffer as we might have changed it.
 539          */
 540         if (data->flags & MMC_DATA_WRITE) {
 541                 dma_sync_single_for_device(mmc_dev(host->mmc),
 542                         host->align_addr, 128 * 4, direction);
 543         }
 544
 545         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 546                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 547         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 548                 goto unmap_entries;
 549         BUG_ON(host->adma_addr & 0x3);
 550
 551         return 0;
 552
 553 unmap_entries:
 554         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 555                 data->sg_len, direction);
 556 unmap_align:
 557         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 558                 128 * 4, direction);
 559 fail:
 560         return -EINVAL;
 561 }
 562
 563 static void sdhci_adma_table_post(struct sdhci_host *host,
 564         struct mmc_data *data)
 565 {
 566         int direction;
 567
 568         struct scatterlist *sg;
 569         int i, size;
 570         u8 *align;
 571         char *buffer;
 572         unsigned long flags;
 573
 574         if (data->flags & MMC_DATA_READ)
 575                 direction = DMA_FROM_DEVICE;
 576         else
 577                 direction = DMA_TO_DEVICE;
 578
 579         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 580                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 581
 582         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 583                 128 * 4, direction);
 584
 585         if (data->flags & MMC_DATA_READ) {
 586                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 587                         data->sg_len, direction);
 588
 589                 align = host->align_buffer;
 590
 591                 for_each_sg(data->sg, sg, host->sg_count, i) {
 592                         if (sg_dma_address(sg) & 0x3) {
 593                                 size = 4 - (sg_dma_address(sg) & 0x3);
 594
 595                                 buffer = sdhci_kmap_atomic(sg, &flags);
 596                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 597                                 memcpy(buffer, align, size);
 598                                 sdhci_kunmap_atomic(buffer, &flags);
 599
 600                                 align += 4;
 601                         }
 602                 }
 603         }
 604
 605         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 606                 data->sg_len, direction);
 607 }
 608
 609 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 610 {
 611         u8 count;
 612         struct mmc_data *data = cmd->data;
 613         unsigned target_timeout, current_timeout;
 614
 615         /*
 616          * If the host controller provides us with an incorrect timeout
 617          * value, just skip the check and use 0xE.  The hardware may take
 618          * longer to time out, but that's much better than having a too-short
 619          * timeout value.
 620          */
 621         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 622                 return 0xE;
 623
 624         /* Unspecified timeout, assume max */
 625         if (!data && !cmd->cmd_timeout_ms)
 626                 return 0xE;
 627
 628         /* timeout in us */
 629         if (!data)
 630                 target_timeout = cmd->cmd_timeout_ms * 1000;
 631         else
 632                 target_timeout = data->timeout_ns / 1000 +
 633                         data->timeout_clks / host->clock;
 634
 635         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
 636                 host->timeout_clk = host->clock / 1000;
 637
 638         /*
 639          * Figure out needed cycles.
 640          * We do this in steps in order to fit inside a 32 bit int.
 641          * The first step is the minimum timeout, which will have a
 642          * minimum resolution of 6 bits:
 643          * (1) 2^13*1000 > 2^22,
 644          * (2) host->timeout_clk < 2^16
 645          *     =>
 646          *     (1) / (2) > 2^6
 647          */
 648         BUG_ON(!host->timeout_clk);
 649         count = 0;
 650         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 651         while (current_timeout < target_timeout) {
 652                 count++;
 653                 current_timeout <<= 1;
 654                 if (count >= 0xF)
 655                         break;
 656         }
 657
 658         if (count >= 0xF) {
 659                 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
 660                        mmc_hostname(host->mmc), cmd->opcode);
 661                 count = 0xE;
 662         }
 663
 664         return count;
 665 }
 666
 667 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 668 {
 669         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 670         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 671
 672         if (host->flags & SDHCI_REQ_USE_DMA)
 673                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 674         else
 675                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 676 }
 677
 678 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 679 {
 680         u8 count;
 681         u8 ctrl;
 682         struct mmc_data *data = cmd->data;
 683         int ret;
 684
 685         WARN_ON(host->data);
 686
 687         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 688                 count = sdhci_calc_timeout(host, cmd);
 689                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 690         }
 691
 692         if (!data)
 693                 return;
 694
 695         /* Sanity checks */
 696         BUG_ON(data->blksz * data->blocks > 524288);
 697         BUG_ON(data->blksz > host->mmc->max_blk_size);
 698         BUG_ON(data->blocks > 65535);
 699
 700         host->data = data;
 701         host->data_early = 0;
 702         host->data->bytes_xfered = 0;
 703
 704         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 705                 host->flags |= SDHCI_REQ_USE_DMA;
 706
 707         /*
 708          * FIXME: This doesn't account for merging when mapping the
 709          * scatterlist.
 710          */
 711         if (host->flags & SDHCI_REQ_USE_DMA) {
 712                 int broken, i;
 713                 struct scatterlist *sg;
 714
 715                 broken = 0;
 716                 if (host->flags & SDHCI_USE_ADMA) {
 717                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 718                                 broken = 1;
 719                 } else {
 720                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 721                                 broken = 1;
 722                 }
 723
 724                 if (unlikely(broken)) {
 725                         for_each_sg(data->sg, sg, data->sg_len, i) {
 726                                 if (sg->length & 0x3) {
 727                                         DBG("Reverting to PIO because of "
 728                                                 "transfer size (%d)\n",
 729                                                 sg->length);
 730                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 731                                         break;
 732                                 }
 733                         }
 734                 }
 735         }
 736
 737         /*
 738          * The assumption here being that alignment is the same after
 739          * translation to device address space.
 740          */
 741         if (host->flags & SDHCI_REQ_USE_DMA) {
 742                 int broken, i;
 743                 struct scatterlist *sg;
 744
 745                 broken = 0;
 746                 if (host->flags & SDHCI_USE_ADMA) {
 747                         /*
 748                          * As we use 3 byte chunks to work around
 749                          * alignment problems, we need to check this
 750                          * quirk.
 751                          */
 752                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 753                                 broken = 1;
 754                 } else {
 755                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 756                                 broken = 1;
 757                 }
 758
 759                 if (unlikely(broken)) {
 760                         for_each_sg(data->sg, sg, data->sg_len, i) {
 761                                 if (sg->offset & 0x3) {
 762                                         DBG("Reverting to PIO because of "
 763                                                 "bad alignment\n");
 764                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 765                                         break;
 766                                 }
 767                         }
 768                 }
 769         }
 770
 771         if (host->flags & SDHCI_REQ_USE_DMA) {
 772                 if (host->flags & SDHCI_USE_ADMA) {
 773                         ret = sdhci_adma_table_pre(host, data);
 774                         if (ret) {
 775                                 /*
 776                                  * This only happens when someone fed
 777                                  * us an invalid request.
 778                                  */
 779                                 WARN_ON(1);
 780                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 781                         } else {
 782                                 sdhci_writel(host, host->adma_addr,
 783                                         SDHCI_ADMA_ADDRESS);
 784                         }
 785                 } else {
 786                         int sg_cnt;
 787
 788                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 789                                         data->sg, data->sg_len,
 790                                         (data->flags & MMC_DATA_READ) ?
 791                                                 DMA_FROM_DEVICE :
 792                                                 DMA_TO_DEVICE);
 793                         if (sg_cnt == 0) {
 794                                 /*
 795                                  * This only happens when someone fed
 796                                  * us an invalid request.
 797                                  */
 798                                 WARN_ON(1);
 799                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 800                         } else {
 801                                 WARN_ON(sg_cnt != 1);
 802                                 sdhci_writel(host, sg_dma_address(data->sg),
 803                                         SDHCI_DMA_ADDRESS);
 804                         }
 805                 }
 806         }
 807
 808         /*
 809          * Always adjust the DMA selection as some controllers
 810          * (e.g. JMicron) can't do PIO properly when the selection
 811          * is ADMA.
 812          */
 813         if (host->version >= SDHCI_SPEC_200) {
 814                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 815                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 816                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 817                         (host->flags & SDHCI_USE_ADMA))
 818                         ctrl |= SDHCI_CTRL_ADMA32;
 819                 else
 820                         ctrl |= SDHCI_CTRL_SDMA;
 821                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 822         }
 823
 824         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 825                 int flags;
 826
 827                 flags = SG_MITER_ATOMIC;
 828                 if (host->data->flags & MMC_DATA_READ)
 829                         flags |= SG_MITER_TO_SG;
 830                 else
 831                         flags |= SG_MITER_FROM_SG;
 832                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 833                 host->blocks = data->blocks;
 834         }
 835
 836         sdhci_set_transfer_irqs(host);
 837
 838         /* Set the DMA boundary value and block size */
 839         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 840                 data->blksz), SDHCI_BLOCK_SIZE);
 841         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 842 }
 843
 844 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 845         struct mmc_command *cmd)
 846 {
 847         u16 mode;
 848         struct mmc_data *data = cmd->data;
 849
 850         if (data == NULL)
 851                 return;
 852
 853         WARN_ON(!host->data);
 854
 855         mode = SDHCI_TRNS_BLK_CNT_EN;
 856         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 857                 mode |= SDHCI_TRNS_MULTI;
 858                 /*
 859                  * If we are sending CMD23, CMD12 never gets sent
 860                  * on successful completion (so no Auto-CMD12).
 861                  */
 862                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 863                         mode |= SDHCI_TRNS_AUTO_CMD12;
 864                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 865                         mode |= SDHCI_TRNS_AUTO_CMD23;
 866                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 867                 }
 868         }
 869
 870         if (data->flags & MMC_DATA_READ)
 871                 mode |= SDHCI_TRNS_READ;
 872         if (host->flags & SDHCI_REQ_USE_DMA)
 873                 mode |= SDHCI_TRNS_DMA;
 874
 875         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 876 }
 877
 878 static void sdhci_finish_data(struct sdhci_host *host)
 879 {
 880         struct mmc_data *data;
 881
 882         BUG_ON(!host->data);
 883
 884         data = host->data;
 885         host->data = NULL;
 886
 887         if (host->flags & SDHCI_REQ_USE_DMA) {
 888                 if (host->flags & SDHCI_USE_ADMA)
 889                         sdhci_adma_table_post(host, data);
 890                 else {
 891                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 892                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 893                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 894                 }
 895         }
 896
 897         /*
 898          * The specification states that the block count register must
 899          * be updated, but it does not specify at what point in the
 900          * data flow. That makes the register entirely useless to read
 901          * back so we have to assume that nothing made it to the card
 902          * in the event of an error.
 903          */
 904         if (data->error)
 905                 data->bytes_xfered = 0;
 906         else
 907                 data->bytes_xfered = data->blksz * data->blocks;
 908
 909         /*
 910          * Need to send CMD12 if -
 911          * a) open-ended multiblock transfer (no CMD23)
 912          * b) error in multiblock transfer
 913          */
 914         if (data->stop &&
 915             (data->error ||
 916              !host->mrq->sbc)) {
 917
 918                 /*
 919                  * The controller needs a reset of internal state machines
 920                  * upon error conditions.
 921                  */
 922                 if (data->error) {
 923                         sdhci_reset(host, SDHCI_RESET_CMD);
 924                         sdhci_reset(host, SDHCI_RESET_DATA);
 925                 }
 926
 927                 sdhci_send_command(host, data->stop);
 928         } else
 929                 tasklet_schedule(&host->finish_tasklet);
 930 }
 931
 932 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 933 {
 934         int flags;
 935         u32 mask;
 936         unsigned long timeout;
 937
 938         WARN_ON(host->cmd);
 939
 940         /* Wait max 10 ms */
 941         timeout = 10;
 942
 943         mask = SDHCI_CMD_INHIBIT;
 944         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 945                 mask |= SDHCI_DATA_INHIBIT;
 946
 947         /* We shouldn't wait for data inihibit for stop commands, even
 948            though they might use busy signaling */
 949         if (host->mrq->data && (cmd == host->mrq->data->stop))
 950                 mask &= ~SDHCI_DATA_INHIBIT;
 951
 952         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 953                 if (timeout == 0) {
 954                         printk(KERN_ERR "%s: Controller never released "
 955                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 956                         sdhci_dumpregs(host);
 957                         cmd->error = -EIO;
 958                         tasklet_schedule(&host->finish_tasklet);
 959                         return;
 960                 }
 961                 timeout--;
 962                 mdelay(1);
 963         }
 964
 965         mod_timer(&host->timer, jiffies + 10 * HZ);
 966
 967         host->cmd = cmd;
 968
 969         sdhci_prepare_data(host, cmd);
 970
 971         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 972
 973         sdhci_set_transfer_mode(host, cmd);
 974
 975         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 976                 printk(KERN_ERR "%s: Unsupported response type!\n",
 977                         mmc_hostname(host->mmc));
 978                 cmd->error = -EINVAL;
 979                 tasklet_schedule(&host->finish_tasklet);
 980                 return;
 981         }
 982
 983         if (!(cmd->flags & MMC_RSP_PRESENT))
 984                 flags = SDHCI_CMD_RESP_NONE;
 985         else if (cmd->flags & MMC_RSP_136)
 986                 flags = SDHCI_CMD_RESP_LONG;
 987         else if (cmd->flags & MMC_RSP_BUSY)
 988                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 989         else
 990                 flags = SDHCI_CMD_RESP_SHORT;
 991
 992         if (cmd->flags & MMC_RSP_CRC)
 993                 flags |= SDHCI_CMD_CRC;
 994         if (cmd->flags & MMC_RSP_OPCODE)
 995                 flags |= SDHCI_CMD_INDEX;
 996
 997         /* CMD19 is special in that the Data Present Select should be set */
 998         if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
 999                 flags |= SDHCI_CMD_DATA;
1000
1001         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1002 }
1003
1004 static void sdhci_finish_command(struct sdhci_host *host)
1005 {
1006         int i;
1007
1008         BUG_ON(host->cmd == NULL);
1009
1010         if (host->cmd->flags & MMC_RSP_PRESENT) {
1011                 if (host->cmd->flags & MMC_RSP_136) {
1012                         /* CRC is stripped so we need to do some shifting. */
1013                         for (i = 0;i < 4;i++) {
1014                                 host->cmd->resp[i] = sdhci_readl(host,
1015                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1016                                 if (i != 3)
1017                                         host->cmd->resp[i] |=
1018                                                 sdhci_readb(host,
1019                                                 SDHCI_RESPONSE + (3-i)*4-1);
1020                         }
1021                 } else {
1022                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1023                 }
1024         }
1025
1026         host->cmd->error = 0;
1027
1028         /* Finished CMD23, now send actual command. */
1029         if (host->cmd == host->mrq->sbc) {
1030                 host->cmd = NULL;
1031                 sdhci_send_command(host, host->mrq->cmd);
1032         } else {
1033
1034                 /* Processed actual command. */
1035                 if (host->data && host->data_early)
1036                         sdhci_finish_data(host);
1037
1038                 if (!host->cmd->data)
1039                         tasklet_schedule(&host->finish_tasklet);
1040
1041                 host->cmd = NULL;
1042         }
1043 }
1044
1045 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1046 {
1047         int div = 0; /* Initialized for compiler warning */
1048         u16 clk = 0;
1049         unsigned long timeout;
1050
1051         if (clock == host->clock)
1052                 return;
1053
1054         if (host->ops->set_clock) {
1055                 host->ops->set_clock(host, clock);
1056                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1057                         return;
1058         }
1059
1060         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1061
1062         if (clock == 0)
1063                 goto out;
1064
1065         if (host->version >= SDHCI_SPEC_300) {
1066                 /*
1067                  * Check if the Host Controller supports Programmable Clock
1068                  * Mode.
1069                  */
1070                 if (host->clk_mul) {
1071                         u16 ctrl;
1072
1073                         /*
1074                          * We need to figure out whether the Host Driver needs
1075                          * to select Programmable Clock Mode, or the value can
1076                          * be set automatically by the Host Controller based on
1077                          * the Preset Value registers.
1078                          */
1079                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1080                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1081                                 for (div = 1; div <= 1024; div++) {
1082                                         if (((host->max_clk * host->clk_mul) /
1083                                               div) <= clock)
1084                                                 break;
1085                                 }
1086                                 /*
1087                                  * Set Programmable Clock Mode in the Clock
1088                                  * Control register.
1089                                  */
1090                                 clk = SDHCI_PROG_CLOCK_MODE;
1091                                 div--;
1092                         }
1093                 } else {
1094                         /* Version 3.00 divisors must be a multiple of 2. */
1095                         if (host->max_clk <= clock)
1096                                 div = 1;
1097                         else {
1098                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1099                                      div += 2) {
1100                                         if ((host->max_clk / div) <= clock)
1101                                                 break;
1102                                 }
1103                         }
1104                         div >>= 1;
1105                 }
1106         } else {
1107                 /* Version 2.00 divisors must be a power of 2. */
1108                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1109                         if ((host->max_clk / div) <= clock)
1110                                 break;
1111                 }
1112                 div >>= 1;
1113         }
1114
1115         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1116         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1117                 << SDHCI_DIVIDER_HI_SHIFT;
1118         clk |= SDHCI_CLOCK_INT_EN;
1119         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1120
1121         /* Wait max 20 ms */
1122         timeout = 20;
1123         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1124                 & SDHCI_CLOCK_INT_STABLE)) {
1125                 if (timeout == 0) {
1126                         printk(KERN_ERR "%s: Internal clock never "
1127                                 "stabilised.\n", mmc_hostname(host->mmc));
1128                         sdhci_dumpregs(host);
1129                         return;
1130                 }
1131                 timeout--;
1132                 mdelay(1);
1133         }
1134
1135         clk |= SDHCI_CLOCK_CARD_EN;
1136         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1137
1138 out:
1139         host->clock = clock;
1140 }
1141
1142 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1143 {
1144         u8 pwr = 0;
1145
1146         if (power != (unsigned short)-1) {
1147                 switch (1 << power) {
1148                 case MMC_VDD_165_195:
1149                         pwr = SDHCI_POWER_180;
1150                         break;
1151                 case MMC_VDD_29_30:
1152                 case MMC_VDD_30_31:
1153                         pwr = SDHCI_POWER_300;
1154                         break;
1155                 case MMC_VDD_32_33:
1156                 case MMC_VDD_33_34:
1157                         pwr = SDHCI_POWER_330;
1158                         break;
1159                 default:
1160                         BUG();
1161                 }
1162         }
1163
1164         if (host->pwr == pwr)
1165                 return;
1166
1167         host->pwr = pwr;
1168
1169         if (pwr == 0) {
1170                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1171                 return;
1172         }
1173
1174         /*
1175          * Spec says that we should clear the power reg before setting
1176          * a new value. Some controllers don't seem to like this though.
1177          */
1178         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1179                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1180
1181         /*
1182          * At least the Marvell CaFe chip gets confused if we set the voltage
1183          * and set turn on power at the same time, so set the voltage first.
1184          */
1185         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1186                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1187
1188         pwr |= SDHCI_POWER_ON;
1189
1190         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1191
1192         /*
1193          * Some controllers need an extra 10ms delay of 10ms before they
1194          * can apply clock after applying power
1195          */
1196         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1197                 mdelay(10);
1198 }
1199
1200 /*****************************************************************************\
1201  *                                                                           *
1202  * MMC callbacks                                                             *
1203  *                                                                           *
1204 \*****************************************************************************/
1205
1206 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1207 {
1208         struct sdhci_host *host;
1209         bool present;
1210         unsigned long flags;
1211
1212         host = mmc_priv(mmc);
1213
1214         spin_lock_irqsave(&host->lock, flags);
1215
1216         WARN_ON(host->mrq != NULL);
1217
1218 #ifndef SDHCI_USE_LEDS_CLASS
1219         sdhci_activate_led(host);
1220 #endif
1221
1222         /*
1223          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1224          * requests if Auto-CMD12 is enabled.
1225          */
1226         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1227                 if (mrq->stop) {
1228                         mrq->data->stop = NULL;
1229                         mrq->stop = NULL;
1230                 }
1231         }
1232
1233         host->mrq = mrq;
1234
1235         /* If polling, assume that the card is always present. */
1236         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1237                 present = true;
1238         else
1239                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1240                                 SDHCI_CARD_PRESENT;
1241
1242         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1243                 host->mrq->cmd->error = -ENOMEDIUM;
1244                 tasklet_schedule(&host->finish_tasklet);
1245         } else {
1246                 u32 present_state;
1247
1248                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1249                 /*
1250                  * Check if the re-tuning timer has already expired and there
1251                  * is no on-going data transfer. If so, we need to execute
1252                  * tuning procedure before sending command.
1253                  */
1254                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1255                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1256                         spin_unlock_irqrestore(&host->lock, flags);
1257                         sdhci_execute_tuning(mmc);
1258                         spin_lock_irqsave(&host->lock, flags);
1259
1260                         /* Restore original mmc_request structure */
1261                         host->mrq = mrq;
1262                 }
1263
1264                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1265                         sdhci_send_command(host, mrq->sbc);
1266                 else
1267                         sdhci_send_command(host, mrq->cmd);
1268         }
1269
1270         mmiowb();
1271         spin_unlock_irqrestore(&host->lock, flags);
1272 }
1273
1274 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1275 {
1276         struct sdhci_host *host;
1277         unsigned long flags;
1278         u8 ctrl;
1279
1280         host = mmc_priv(mmc);
1281
1282         spin_lock_irqsave(&host->lock, flags);
1283
1284         if (host->flags & SDHCI_DEVICE_DEAD)
1285                 goto out;
1286
1287         /*
1288          * Reset the chip on each power off.
1289          * Should clear out any weird states.
1290          */
1291         if (ios->power_mode == MMC_POWER_OFF) {
1292                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1293                 sdhci_reinit(host);
1294         }
1295
1296         sdhci_set_clock(host, ios->clock);
1297
1298         if (ios->power_mode == MMC_POWER_OFF)
1299                 sdhci_set_power(host, -1);
1300         else
1301                 sdhci_set_power(host, ios->vdd);
1302
1303         if (host->ops->platform_send_init_74_clocks)
1304                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1305
1306         /*
1307          * If your platform has 8-bit width support but is not a v3 controller,
1308          * or if it requires special setup code, you should implement that in
1309          * platform_8bit_width().
1310          */
1311         if (host->ops->platform_8bit_width)
1312                 host->ops->platform_8bit_width(host, ios->bus_width);
1313         else {
1314                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1315                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1316                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1317                         if (host->version >= SDHCI_SPEC_300)
1318                                 ctrl |= SDHCI_CTRL_8BITBUS;
1319                 } else {
1320                         if (host->version >= SDHCI_SPEC_300)
1321                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1322                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1323                                 ctrl |= SDHCI_CTRL_4BITBUS;
1324                         else
1325                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1326                 }
1327                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1328         }
1329
1330         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1331
1332         if ((ios->timing == MMC_TIMING_SD_HS ||
1333              ios->timing == MMC_TIMING_MMC_HS)
1334             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1335                 ctrl |= SDHCI_CTRL_HISPD;
1336         else
1337                 ctrl &= ~SDHCI_CTRL_HISPD;
1338
1339         if (host->version >= SDHCI_SPEC_300) {
1340                 u16 clk, ctrl_2;
1341                 unsigned int clock;
1342
1343                 /* In case of UHS-I modes, set High Speed Enable */
1344                 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1345                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1346                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1347                     (ios->timing == MMC_TIMING_UHS_SDR25) ||
1348                     (ios->timing == MMC_TIMING_UHS_SDR12))
1349                         ctrl |= SDHCI_CTRL_HISPD;
1350
1351                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1352                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1353                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1354                         /*
1355                          * We only need to set Driver Strength if the
1356                          * preset value enable is not set.
1357                          */
1358                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1359                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1360                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1361                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1362                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1363
1364                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1365                 } else {
1366                         /*
1367                          * According to SDHC Spec v3.00, if the Preset Value
1368                          * Enable in the Host Control 2 register is set, we
1369                          * need to reset SD Clock Enable before changing High
1370                          * Speed Enable to avoid generating clock gliches.
1371                          */
1372
1373                         /* Reset SD Clock Enable */
1374                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1375                         clk &= ~SDHCI_CLOCK_CARD_EN;
1376                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1377
1378                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1379
1380                         /* Re-enable SD Clock */
1381                         clock = host->clock;
1382                         host->clock = 0;
1383                         sdhci_set_clock(host, clock);
1384                 }
1385
1386
1387                 /* Reset SD Clock Enable */
1388                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1389                 clk &= ~SDHCI_CLOCK_CARD_EN;
1390                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1391
1392                 if (host->ops->set_uhs_signaling)
1393                         host->ops->set_uhs_signaling(host, ios->timing);
1394                 else {
1395                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1396                         /* Select Bus Speed Mode for host */
1397                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1398                         if (ios->timing == MMC_TIMING_UHS_SDR12)
1399                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1400                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1401                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1402                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1403                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1404                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1405                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1406                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1407                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1408                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1409                 }
1410
1411                 /* Re-enable SD Clock */
1412                 clock = host->clock;
1413                 host->clock = 0;
1414                 sdhci_set_clock(host, clock);
1415         } else
1416                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1417
1418         /*
1419          * Some (ENE) controllers go apeshit on some ios operation,
1420          * signalling timeout and CRC errors even on CMD0. Resetting
1421          * it on each ios seems to solve the problem.
1422          */
1423         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1424                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1425
1426 out:
1427         mmiowb();
1428         spin_unlock_irqrestore(&host->lock, flags);
1429 }
1430
1431 static int check_ro(struct sdhci_host *host)
1432 {
1433         unsigned long flags;
1434         int is_readonly;
1435
1436         spin_lock_irqsave(&host->lock, flags);
1437
1438         if (host->flags & SDHCI_DEVICE_DEAD)
1439                 is_readonly = 0;
1440         else if (host->ops->get_ro)
1441                 is_readonly = host->ops->get_ro(host);
1442         else
1443                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1444                                 & SDHCI_WRITE_PROTECT);
1445
1446         spin_unlock_irqrestore(&host->lock, flags);
1447
1448         /* This quirk needs to be replaced by a callback-function later */
1449         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1450                 !is_readonly : is_readonly;
1451 }
1452
1453 #define SAMPLE_COUNT    5
1454
1455 static int sdhci_get_ro(struct mmc_host *mmc)
1456 {
1457         struct sdhci_host *host;
1458         int i, ro_count;
1459
1460         host = mmc_priv(mmc);
1461
1462         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1463                 return check_ro(host);
1464
1465         ro_count = 0;
1466         for (i = 0; i < SAMPLE_COUNT; i++) {
1467                 if (check_ro(host)) {
1468                         if (++ro_count > SAMPLE_COUNT / 2)
1469                                 return 1;
1470                 }
1471                 msleep(30);
1472         }
1473         return 0;
1474 }
1475
1476 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1477 {
1478         struct sdhci_host *host;
1479         unsigned long flags;
1480
1481         host = mmc_priv(mmc);
1482
1483         spin_lock_irqsave(&host->lock, flags);
1484
1485         if (host->flags & SDHCI_DEVICE_DEAD)
1486                 goto out;
1487
1488         if (enable)
1489                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1490         else
1491                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1492 out:
1493         mmiowb();
1494
1495         spin_unlock_irqrestore(&host->lock, flags);
1496 }
1497
1498 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1499         struct mmc_ios *ios)
1500 {
1501         struct sdhci_host *host;
1502         u8 pwr;
1503         u16 clk, ctrl;
1504         u32 present_state;
1505
1506         host = mmc_priv(mmc);
1507
1508         /*
1509          * Signal Voltage Switching is only applicable for Host Controllers
1510          * v3.00 and above.
1511          */
1512         if (host->version < SDHCI_SPEC_300)
1513                 return 0;
1514
1515         /*
1516          * We first check whether the request is to set signalling voltage
1517          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1518          */
1519         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1520         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1521                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1522                 ctrl &= ~SDHCI_CTRL_VDD_180;
1523                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1524
1525                 /* Wait for 5ms */
1526                 usleep_range(5000, 5500);
1527
1528                 /* 3.3V regulator output should be stable within 5 ms */
1529                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1530                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1531                         return 0;
1532                 else {
1533                         printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1534                                 "signalling voltage failed\n");
1535                         return -EIO;
1536                 }
1537         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1538                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1539                 /* Stop SDCLK */
1540                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1541                 clk &= ~SDHCI_CLOCK_CARD_EN;
1542                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1543
1544                 /* Check whether DAT[3:0] is 0000 */
1545                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1546                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1547                        SDHCI_DATA_LVL_SHIFT)) {
1548                         /*
1549                          * Enable 1.8V Signal Enable in the Host Control2
1550                          * register
1551                          */
1552                         ctrl |= SDHCI_CTRL_VDD_180;
1553                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1554
1555                         /* Wait for 5ms */
1556                         usleep_range(5000, 5500);
1557
1558                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1559                         if (ctrl & SDHCI_CTRL_VDD_180) {
1560                                 /* Provide SDCLK again and wait for 1ms*/
1561                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1562                                 clk |= SDHCI_CLOCK_CARD_EN;
1563                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1564                                 usleep_range(1000, 1500);
1565
1566                                 /*
1567                                  * If DAT[3:0] level is 1111b, then the card
1568                                  * was successfully switched to 1.8V signaling.
1569                                  */
1570                                 present_state = sdhci_readl(host,
1571                                                         SDHCI_PRESENT_STATE);
1572                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1573                                      SDHCI_DATA_LVL_MASK)
1574                                         return 0;
1575                         }
1576                 }
1577
1578                 /*
1579                  * If we are here, that means the switch to 1.8V signaling
1580                  * failed. We power cycle the card, and retry initialization
1581                  * sequence by setting S18R to 0.
1582                  */
1583                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1584                 pwr &= ~SDHCI_POWER_ON;
1585                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1586
1587                 /* Wait for 1ms as per the spec */
1588                 usleep_range(1000, 1500);
1589                 pwr |= SDHCI_POWER_ON;
1590                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1591
1592                 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1593                         "voltage failed, retrying with S18R set to 0\n");
1594                 return -EAGAIN;
1595         } else
1596                 /* No signal voltage switch required */
1597                 return 0;
1598 }
1599
1600 static int sdhci_execute_tuning(struct mmc_host *mmc)
1601 {
1602         struct sdhci_host *host;
1603         u16 ctrl;
1604         u32 ier;
1605         int tuning_loop_counter = MAX_TUNING_LOOP;
1606         unsigned long timeout;
1607         int err = 0;
1608
1609         host = mmc_priv(mmc);
1610
1611         disable_irq(host->irq);
1612         spin_lock(&host->lock);
1613
1614         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1615
1616         /*
1617          * Host Controller needs tuning only in case of SDR104 mode
1618          * and for SDR50 mode when Use Tuning for SDR50 is set in
1619          * Capabilities register.
1620          */
1621         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1622             (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1623             (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1624                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1625         else {
1626                 spin_unlock(&host->lock);
1627                 enable_irq(host->irq);
1628                 return 0;
1629         }
1630
1631         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1632
1633         /*
1634          * As per the Host Controller spec v3.00, tuning command
1635          * generates Buffer Read Ready interrupt, so enable that.
1636          *
1637          * Note: The spec clearly says that when tuning sequence
1638          * is being performed, the controller does not generate
1639          * interrupts other than Buffer Read Ready interrupt. But
1640          * to make sure we don't hit a controller bug, we _only_
1641          * enable Buffer Read Ready interrupt here.
1642          */
1643         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1644         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1645
1646         /*
1647          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1648          * of loops reaches 40 times or a timeout of 150ms occurs.
1649          */
1650         timeout = 150;
1651         do {
1652                 struct mmc_command cmd = {0};
1653                 struct mmc_request mrq = {0};
1654
1655                 if (!tuning_loop_counter && !timeout)
1656                         break;
1657
1658                 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1659                 cmd.arg = 0;
1660                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1661                 cmd.retries = 0;
1662                 cmd.data = NULL;
1663                 cmd.error = 0;
1664
1665                 mrq.cmd = &cmd;
1666                 host->mrq = &mrq;
1667
1668                 /*
1669                  * In response to CMD19, the card sends 64 bytes of tuning
1670                  * block to the Host Controller. So we set the block size
1671                  * to 64 here.
1672                  */
1673                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1674
1675                 /*
1676                  * The tuning block is sent by the card to the host controller.
1677                  * So we set the TRNS_READ bit in the Transfer Mode register.
1678                  * This also takes care of setting DMA Enable and Multi Block
1679                  * Select in the same register to 0.
1680                  */
1681                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1682
1683                 sdhci_send_command(host, &cmd);
1684
1685                 host->cmd = NULL;
1686                 host->mrq = NULL;
1687
1688                 spin_unlock(&host->lock);
1689                 enable_irq(host->irq);
1690
1691                 /* Wait for Buffer Read Ready interrupt */
1692                 wait_event_interruptible_timeout(host->buf_ready_int,
1693                                         (host->tuning_done == 1),
1694                                         msecs_to_jiffies(50));
1695                 disable_irq(host->irq);
1696                 spin_lock(&host->lock);
1697
1698                 if (!host->tuning_done) {
1699                         printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1700                                 "Buffer Read Ready interrupt during tuning "
1701                                 "procedure, falling back to fixed sampling "
1702                                 "clock\n");
1703                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1704                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1705                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1706                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1707
1708                         err = -EIO;
1709                         goto out;
1710                 }
1711
1712                 host->tuning_done = 0;
1713
1714                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1715                 tuning_loop_counter--;
1716                 timeout--;
1717                 mdelay(1);
1718         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1719
1720         /*
1721          * The Host Driver has exhausted the maximum number of loops allowed,
1722          * so use fixed sampling frequency.
1723          */
1724         if (!tuning_loop_counter || !timeout) {
1725                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1726                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1727         } else {
1728                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1729                         printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1730                                 " failed, falling back to fixed sampling"
1731                                 " clock\n");
1732                         err = -EIO;
1733                 }
1734         }
1735
1736 out:
1737         /*
1738          * If this is the very first time we are here, we start the retuning
1739          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1740          * flag won't be set, we check this condition before actually starting
1741          * the timer.
1742          */
1743         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1744             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1745                 mod_timer(&host->tuning_timer, jiffies +
1746                         host->tuning_count * HZ);
1747                 /* Tuning mode 1 limits the maximum data length to 4MB */
1748                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1749         } else {
1750                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1751                 /* Reload the new initial value for timer */
1752                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1753                         mod_timer(&host->tuning_timer, jiffies +
1754                                 host->tuning_count * HZ);
1755         }
1756
1757         /*
1758          * In case tuning fails, host controllers which support re-tuning can
1759          * try tuning again at a later time, when the re-tuning timer expires.
1760          * So for these controllers, we return 0. Since there might be other
1761          * controllers who do not have this capability, we return error for
1762          * them.
1763          */
1764         if (err && host->tuning_count &&
1765             host->tuning_mode == SDHCI_TUNING_MODE_1)
1766                 err = 0;
1767
1768         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1769         spin_unlock(&host->lock);
1770         enable_irq(host->irq);
1771
1772         return err;
1773 }
1774
1775 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1776 {
1777         struct sdhci_host *host;
1778         u16 ctrl;
1779         unsigned long flags;
1780
1781         host = mmc_priv(mmc);
1782
1783         /* Host Controller v3.00 defines preset value registers */
1784         if (host->version < SDHCI_SPEC_300)
1785                 return;
1786
1787         spin_lock_irqsave(&host->lock, flags);
1788
1789         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1790
1791         /*
1792          * We only enable or disable Preset Value if they are not already
1793          * enabled or disabled respectively. Otherwise, we bail out.
1794          */
1795         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1796                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1797                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1798         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1799                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1800                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1801         }
1802
1803         spin_unlock_irqrestore(&host->lock, flags);
1804 }
1805
1806 static const struct mmc_host_ops sdhci_ops = {
1807         .request        = sdhci_request,
1808         .set_ios        = sdhci_set_ios,
1809         .get_ro         = sdhci_get_ro,
1810         .enable_sdio_irq = sdhci_enable_sdio_irq,
1811         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1812         .execute_tuning                 = sdhci_execute_tuning,
1813         .enable_preset_value            = sdhci_enable_preset_value,
1814 };
1815
1816 /*****************************************************************************\
1817  *                                                                           *
1818  * Tasklets                                                                  *
1819  *                                                                           *
1820 \*****************************************************************************/
1821
1822 static void sdhci_tasklet_card(unsigned long param)
1823 {
1824         struct sdhci_host *host;
1825         unsigned long flags;
1826
1827         host = (struct sdhci_host*)param;
1828
1829         spin_lock_irqsave(&host->lock, flags);
1830
1831         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1832                 if (host->mrq) {
1833                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1834                                 mmc_hostname(host->mmc));
1835                         printk(KERN_ERR "%s: Resetting controller.\n",
1836                                 mmc_hostname(host->mmc));
1837
1838                         sdhci_reset(host, SDHCI_RESET_CMD);
1839                         sdhci_reset(host, SDHCI_RESET_DATA);
1840
1841                         host->mrq->cmd->error = -ENOMEDIUM;
1842                         tasklet_schedule(&host->finish_tasklet);
1843                 }
1844         }
1845
1846         spin_unlock_irqrestore(&host->lock, flags);
1847
1848         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1849 }
1850
1851 static void sdhci_tasklet_finish(unsigned long param)
1852 {
1853         struct sdhci_host *host;
1854         unsigned long flags;
1855         struct mmc_request *mrq;
1856
1857         host = (struct sdhci_host*)param;
1858
1859         /*
1860          * If this tasklet gets rescheduled while running, it will
1861          * be run again afterwards but without any active request.
1862          */
1863         if (!host->mrq)
1864                 return;
1865
1866         spin_lock_irqsave(&host->lock, flags);
1867
1868         del_timer(&host->timer);
1869
1870         if (host->version >= SDHCI_SPEC_300)
1871                 del_timer(&host->tuning_timer);
1872
1873         mrq = host->mrq;
1874
1875         /*
1876          * The controller needs a reset of internal state machines
1877          * upon error conditions.
1878          */
1879         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1880             ((mrq->cmd && mrq->cmd->error) ||
1881                  (mrq->data && (mrq->data->error ||
1882                   (mrq->data->stop && mrq->data->stop->error))) ||
1883                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1884
1885                 /* Some controllers need this kick or reset won't work here */
1886                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1887                         unsigned int clock;
1888
1889                         /* This is to force an update */
1890                         clock = host->clock;
1891                         host->clock = 0;
1892                         sdhci_set_clock(host, clock);
1893                 }
1894
1895                 /* Spec says we should do both at the same time, but Ricoh
1896                    controllers do not like that. */
1897                 sdhci_reset(host, SDHCI_RESET_CMD);
1898                 sdhci_reset(host, SDHCI_RESET_DATA);
1899         }
1900
1901         host->mrq = NULL;
1902         host->cmd = NULL;
1903         host->data = NULL;
1904
1905 #ifndef SDHCI_USE_LEDS_CLASS
1906         sdhci_deactivate_led(host);
1907 #endif
1908
1909         mmiowb();
1910         spin_unlock_irqrestore(&host->lock, flags);
1911
1912         mmc_request_done(host->mmc, mrq);
1913 }
1914
1915 static void sdhci_timeout_timer(unsigned long data)
1916 {
1917         struct sdhci_host *host;
1918         unsigned long flags;
1919
1920         host = (struct sdhci_host*)data;
1921
1922         spin_lock_irqsave(&host->lock, flags);
1923
1924         if (host->mrq) {
1925                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1926                         "interrupt.\n", mmc_hostname(host->mmc));
1927                 sdhci_dumpregs(host);
1928
1929                 if (host->data) {
1930                         host->data->error = -ETIMEDOUT;
1931                         sdhci_finish_data(host);
1932                 } else {
1933                         if (host->cmd)
1934                                 host->cmd->error = -ETIMEDOUT;
1935                         else
1936                                 host->mrq->cmd->error = -ETIMEDOUT;
1937
1938                         tasklet_schedule(&host->finish_tasklet);
1939                 }
1940         }
1941
1942         mmiowb();
1943         spin_unlock_irqrestore(&host->lock, flags);
1944 }
1945
1946 static void sdhci_tuning_timer(unsigned long data)
1947 {
1948         struct sdhci_host *host;
1949         unsigned long flags;
1950
1951         host = (struct sdhci_host *)data;
1952
1953         spin_lock_irqsave(&host->lock, flags);
1954
1955         host->flags |= SDHCI_NEEDS_RETUNING;
1956
1957         spin_unlock_irqrestore(&host->lock, flags);
1958 }
1959
1960 /*****************************************************************************\
1961  *                                                                           *
1962  * Interrupt handling                                                        *
1963  *                                                                           *
1964 \*****************************************************************************/
1965
1966 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1967 {
1968         BUG_ON(intmask == 0);
1969
1970         if (!host->cmd) {
1971                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1972                         "though no command operation was in progress.\n",
1973                         mmc_hostname(host->mmc), (unsigned)intmask);
1974                 sdhci_dumpregs(host);
1975                 return;
1976         }
1977
1978         if (intmask & SDHCI_INT_TIMEOUT)
1979                 host->cmd->error = -ETIMEDOUT;
1980         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1981                         SDHCI_INT_INDEX))
1982                 host->cmd->error = -EILSEQ;
1983
1984         if (host->cmd->error) {
1985                 tasklet_schedule(&host->finish_tasklet);
1986                 return;
1987         }
1988
1989         /*
1990          * The host can send and interrupt when the busy state has
1991          * ended, allowing us to wait without wasting CPU cycles.
1992          * Unfortunately this is overloaded on the "data complete"
1993          * interrupt, so we need to take some care when handling
1994          * it.
1995          *
1996          * Note: The 1.0 specification is a bit ambiguous about this
1997          *       feature so there might be some problems with older
1998          *       controllers.
1999          */
2000         if (host->cmd->flags & MMC_RSP_BUSY) {
2001                 if (host->cmd->data)
2002                         DBG("Cannot wait for busy signal when also "
2003                                 "doing a data transfer");
2004                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2005                         return;
2006
2007                 /* The controller does not support the end-of-busy IRQ,
2008                  * fall through and take the SDHCI_INT_RESPONSE */
2009         }
2010
2011         if (intmask & SDHCI_INT_RESPONSE)
2012                 sdhci_finish_command(host);
2013 }
2014
2015 #ifdef CONFIG_MMC_DEBUG
2016 static void sdhci_show_adma_error(struct sdhci_host *host)
2017 {
2018         const char *name = mmc_hostname(host->mmc);
2019         u8 *desc = host->adma_desc;
2020         __le32 *dma;
2021         __le16 *len;
2022         u8 attr;
2023
2024         sdhci_dumpregs(host);
2025
2026         while (true) {
2027                 dma = (__le32 *)(desc + 4);
2028                 len = (__le16 *)(desc + 2);
2029                 attr = *desc;
2030
2031                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2032                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2033
2034                 desc += 8;
2035
2036                 if (attr & 2)
2037                         break;
2038         }
2039 }
2040 #else
2041 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2042 #endif
2043
2044 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2045 {
2046         BUG_ON(intmask == 0);
2047
2048         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2049         if (intmask & SDHCI_INT_DATA_AVAIL) {
2050                 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2051                     MMC_SEND_TUNING_BLOCK) {
2052                         host->tuning_done = 1;
2053                         wake_up(&host->buf_ready_int);
2054                         return;
2055                 }
2056         }
2057
2058         if (!host->data) {
2059                 /*
2060                  * The "data complete" interrupt is also used to
2061                  * indicate that a busy state has ended. See comment
2062                  * above in sdhci_cmd_irq().
2063                  */
2064                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2065                         if (intmask & SDHCI_INT_DATA_END) {
2066                                 sdhci_finish_command(host);
2067                                 return;
2068                         }
2069                 }
2070
2071                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2072                         "though no data operation was in progress.\n",
2073                         mmc_hostname(host->mmc), (unsigned)intmask);
2074                 sdhci_dumpregs(host);
2075
2076                 return;
2077         }
2078
2079         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2080                 host->data->error = -ETIMEDOUT;
2081         else if (intmask & SDHCI_INT_DATA_END_BIT)
2082                 host->data->error = -EILSEQ;
2083         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2084                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2085                         != MMC_BUS_TEST_R)
2086                 host->data->error = -EILSEQ;
2087         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2088                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2089                 sdhci_show_adma_error(host);
2090                 host->data->error = -EIO;
2091         }
2092
2093         if (host->data->error)
2094                 sdhci_finish_data(host);
2095         else {
2096                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2097                         sdhci_transfer_pio(host);
2098
2099                 /*
2100                  * We currently don't do anything fancy with DMA
2101                  * boundaries, but as we can't disable the feature
2102                  * we need to at least restart the transfer.
2103                  *
2104                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2105                  * should return a valid address to continue from, but as
2106                  * some controllers are faulty, don't trust them.
2107                  */
2108                 if (intmask & SDHCI_INT_DMA_END) {
2109                         u32 dmastart, dmanow;
2110                         dmastart = sg_dma_address(host->data->sg);
2111                         dmanow = dmastart + host->data->bytes_xfered;
2112                         /*
2113                          * Force update to the next DMA block boundary.
2114                          */
2115                         dmanow = (dmanow &
2116                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2117                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2118                         host->data->bytes_xfered = dmanow - dmastart;
2119                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2120                                 " next 0x%08x\n",
2121                                 mmc_hostname(host->mmc), dmastart,
2122                                 host->data->bytes_xfered, dmanow);
2123                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2124                 }
2125
2126                 if (intmask & SDHCI_INT_DATA_END) {
2127                         if (host->cmd) {
2128                                 /*
2129                                  * Data managed to finish before the
2130                                  * command completed. Make sure we do
2131                                  * things in the proper order.
2132                                  */
2133                                 host->data_early = 1;
2134                         } else {
2135                                 sdhci_finish_data(host);
2136                         }
2137                 }
2138         }
2139 }
2140
2141 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2142 {
2143         irqreturn_t result;
2144         struct sdhci_host* host = dev_id;
2145         u32 intmask;
2146         int cardint = 0;
2147
2148         spin_lock(&host->lock);
2149
2150         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2151
2152         if (!intmask || intmask == 0xffffffff) {
2153                 result = IRQ_NONE;
2154                 goto out;
2155         }
2156
2157         DBG("*** %s got interrupt: 0x%08x\n",
2158                 mmc_hostname(host->mmc), intmask);
2159
2160         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2161                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2162                               SDHCI_CARD_PRESENT;
2163
2164                 /*
2165                  * There is a observation on i.mx esdhc.  INSERT bit will be
2166                  * immediately set again when it gets cleared, if a card is
2167                  * inserted.  We have to mask the irq to prevent interrupt
2168                  * storm which will freeze the system.  And the REMOVE gets
2169                  * the same situation.
2170                  *
2171                  * More testing are needed here to ensure it works for other
2172                  * platforms though.
2173                  */
2174                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2175                                                 SDHCI_INT_CARD_REMOVE);
2176                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2177                                                   SDHCI_INT_CARD_INSERT);
2178
2179                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2180                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2181                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2182                 tasklet_schedule(&host->card_tasklet);
2183         }
2184
2185         if (intmask & SDHCI_INT_CMD_MASK) {
2186                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2187                         SDHCI_INT_STATUS);
2188                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2189         }
2190
2191         if (intmask & SDHCI_INT_DATA_MASK) {
2192                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2193                         SDHCI_INT_STATUS);
2194                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2195         }
2196
2197         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2198
2199         intmask &= ~SDHCI_INT_ERROR;
2200
2201         if (intmask & SDHCI_INT_BUS_POWER) {
2202                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
2203                         mmc_hostname(host->mmc));
2204                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2205         }
2206
2207         intmask &= ~SDHCI_INT_BUS_POWER;
2208
2209         if (intmask & SDHCI_INT_CARD_INT)
2210                 cardint = 1;
2211
2212         intmask &= ~SDHCI_INT_CARD_INT;
2213
2214         if (intmask) {
2215                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
2216                         mmc_hostname(host->mmc), intmask);
2217                 sdhci_dumpregs(host);
2218
2219                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2220         }
2221
2222         result = IRQ_HANDLED;
2223
2224         mmiowb();
2225 out:
2226         spin_unlock(&host->lock);
2227
2228         /*
2229          * We have to delay this as it calls back into the driver.
2230          */
2231         if (cardint)
2232                 mmc_signal_sdio_irq(host->mmc);
2233
2234         return result;
2235 }
2236
2237 /*****************************************************************************\
2238  *                                                                           *
2239  * Suspend/resume                                                            *
2240  *                                                                           *
2241 \*****************************************************************************/
2242
2243 #ifdef CONFIG_PM
2244
2245 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
2246 {
2247         int ret;
2248
2249         sdhci_disable_card_detection(host);
2250
2251         /* Disable tuning since we are suspending */
2252         if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2253             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2254                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2255                 mod_timer(&host->tuning_timer, jiffies +
2256                         host->tuning_count * HZ);
2257         }
2258
2259         ret = mmc_suspend_host(host->mmc);
2260         if (ret)
2261                 return ret;
2262
2263         free_irq(host->irq, host);
2264
2265         if (host->vmmc)
2266                 ret = regulator_disable(host->vmmc);
2267
2268         return ret;
2269 }
2270
2271 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2272
2273 int sdhci_resume_host(struct sdhci_host *host)
2274 {
2275         int ret;
2276
2277         if (host->vmmc) {
2278                 int ret = regulator_enable(host->vmmc);
2279                 if (ret)
2280                         return ret;
2281         }
2282
2283
2284         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2285                 if (host->ops->enable_dma)
2286                         host->ops->enable_dma(host);
2287         }
2288
2289         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2290                           mmc_hostname(host->mmc), host);
2291         if (ret)
2292                 return ret;
2293
2294         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2295         mmiowb();
2296
2297         ret = mmc_resume_host(host->mmc);
2298         sdhci_enable_card_detection(host);
2299
2300         /* Set the re-tuning expiration flag */
2301         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2302             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2303                 host->flags |= SDHCI_NEEDS_RETUNING;
2304
2305         return ret;
2306 }
2307
2308 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2309
2310 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2311 {
2312         u8 val;
2313         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2314         val |= SDHCI_WAKE_ON_INT;
2315         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2316 }
2317
2318 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2319
2320 #endif /* CONFIG_PM */
2321
2322 /*****************************************************************************\
2323  *                                                                           *
2324  * Device allocation/registration                                            *
2325  *                                                                           *
2326 \*****************************************************************************/
2327
2328 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2329         size_t priv_size)
2330 {
2331         struct mmc_host *mmc;
2332         struct sdhci_host *host;
2333
2334         WARN_ON(dev == NULL);
2335
2336         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2337         if (!mmc)
2338                 return ERR_PTR(-ENOMEM);
2339
2340         host = mmc_priv(mmc);
2341         host->mmc = mmc;
2342
2343         return host;
2344 }
2345
2346 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2347
2348 int sdhci_add_host(struct sdhci_host *host)
2349 {
2350         struct mmc_host *mmc;
2351         u32 caps[2];
2352         u32 max_current_caps;
2353         unsigned int ocr_avail;
2354         int ret;
2355
2356         WARN_ON(host == NULL);
2357         if (host == NULL)
2358                 return -EINVAL;
2359
2360         mmc = host->mmc;
2361
2362         if (debug_quirks)
2363                 host->quirks = debug_quirks;
2364
2365         sdhci_reset(host, SDHCI_RESET_ALL);
2366
2367         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2368         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2369                                 >> SDHCI_SPEC_VER_SHIFT;
2370         if (host->version > SDHCI_SPEC_300) {
2371                 printk(KERN_ERR "%s: Unknown controller version (%d). "
2372                         "You may experience problems.\n", mmc_hostname(mmc),
2373                         host->version);
2374         }
2375
2376         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2377                 sdhci_readl(host, SDHCI_CAPABILITIES);
2378
2379         caps[1] = (host->version >= SDHCI_SPEC_300) ?
2380                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2381
2382         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2383                 host->flags |= SDHCI_USE_SDMA;
2384         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2385                 DBG("Controller doesn't have SDMA capability\n");
2386         else
2387                 host->flags |= SDHCI_USE_SDMA;
2388
2389         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2390                 (host->flags & SDHCI_USE_SDMA)) {
2391                 DBG("Disabling DMA as it is marked broken\n");
2392                 host->flags &= ~SDHCI_USE_SDMA;
2393         }
2394
2395         if ((host->version >= SDHCI_SPEC_200) &&
2396                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2397                 host->flags |= SDHCI_USE_ADMA;
2398
2399         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2400                 (host->flags & SDHCI_USE_ADMA)) {
2401                 DBG("Disabling ADMA as it is marked broken\n");
2402                 host->flags &= ~SDHCI_USE_ADMA;
2403         }
2404
2405         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2406                 if (host->ops->enable_dma) {
2407                         if (host->ops->enable_dma(host)) {
2408                                 printk(KERN_WARNING "%s: No suitable DMA "
2409                                         "available. Falling back to PIO.\n",
2410                                         mmc_hostname(mmc));
2411                                 host->flags &=
2412                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2413                         }
2414                 }
2415         }
2416
2417         if (host->flags & SDHCI_USE_ADMA) {
2418                 /*
2419                  * We need to allocate descriptors for all sg entries
2420                  * (128) and potentially one alignment transfer for
2421                  * each of those entries.
2422                  */
2423                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2424                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2425                 if (!host->adma_desc || !host->align_buffer) {
2426                         kfree(host->adma_desc);
2427                         kfree(host->align_buffer);
2428                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
2429                                 "buffers. Falling back to standard DMA.\n",
2430                                 mmc_hostname(mmc));
2431                         host->flags &= ~SDHCI_USE_ADMA;
2432                 }
2433         }
2434
2435         /*
2436          * If we use DMA, then it's up to the caller to set the DMA
2437          * mask, but PIO does not need the hw shim so we set a new
2438          * mask here in that case.
2439          */
2440         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2441                 host->dma_mask = DMA_BIT_MASK(64);
2442                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2443         }
2444
2445         if (host->version >= SDHCI_SPEC_300)
2446                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2447                         >> SDHCI_CLOCK_BASE_SHIFT;
2448         else
2449                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2450                         >> SDHCI_CLOCK_BASE_SHIFT;
2451
2452         host->max_clk *= 1000000;
2453         if (host->max_clk == 0 || host->quirks &
2454                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2455                 if (!host->ops->get_max_clock) {
2456                         printk(KERN_ERR
2457                                "%s: Hardware doesn't specify base clock "
2458                                "frequency.\n", mmc_hostname(mmc));
2459                         return -ENODEV;
2460                 }
2461                 host->max_clk = host->ops->get_max_clock(host);
2462         }
2463
2464         host->timeout_clk =
2465                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2466         if (host->timeout_clk == 0) {
2467                 if (host->ops->get_timeout_clock) {
2468                         host->timeout_clk = host->ops->get_timeout_clock(host);
2469                 } else if (!(host->quirks &
2470                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2471                         printk(KERN_ERR
2472                                "%s: Hardware doesn't specify timeout clock "
2473                                "frequency.\n", mmc_hostname(mmc));
2474                         return -ENODEV;
2475                 }
2476         }
2477         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2478                 host->timeout_clk *= 1000;
2479
2480         /*
2481          * In case of Host Controller v3.00, find out whether clock
2482          * multiplier is supported.
2483          */
2484         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2485                         SDHCI_CLOCK_MUL_SHIFT;
2486
2487         /*
2488          * In case the value in Clock Multiplier is 0, then programmable
2489          * clock mode is not supported, otherwise the actual clock
2490          * multiplier is one more than the value of Clock Multiplier
2491          * in the Capabilities Register.
2492          */
2493         if (host->clk_mul)
2494                 host->clk_mul += 1;
2495
2496         /*
2497          * Set host parameters.
2498          */
2499         mmc->ops = &sdhci_ops;
2500         mmc->f_max = host->max_clk;
2501         if (host->ops->get_min_clock)
2502                 mmc->f_min = host->ops->get_min_clock(host);
2503         else if (host->version >= SDHCI_SPEC_300) {
2504                 if (host->clk_mul) {
2505                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2506                         mmc->f_max = host->max_clk * host->clk_mul;
2507                 } else
2508                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2509         } else
2510                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2511
2512         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2513                 mmc->max_discard_to = (1 << 27) / (mmc->f_max / 1000);
2514         else
2515                 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2516
2517         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2518
2519         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2520                 host->flags |= SDHCI_AUTO_CMD12;
2521
2522         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2523         if ((host->version >= SDHCI_SPEC_300) &&
2524             ((host->flags & SDHCI_USE_ADMA) ||
2525              !(host->flags & SDHCI_USE_SDMA))) {
2526                 host->flags |= SDHCI_AUTO_CMD23;
2527                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2528         } else {
2529                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2530         }
2531
2532         /*
2533          * A controller may support 8-bit width, but the board itself
2534          * might not have the pins brought out.  Boards that support
2535          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2536          * their platform code before calling sdhci_add_host(), and we
2537          * won't assume 8-bit width for hosts without that CAP.
2538          */
2539         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2540                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2541
2542         if (caps[0] & SDHCI_CAN_DO_HISPD)
2543                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2544
2545         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2546             mmc_card_is_removable(mmc))
2547                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2548
2549         /* UHS-I mode(s) supported by the host controller. */
2550         if (host->version >= SDHCI_SPEC_300)
2551                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2552
2553         /* SDR104 supports also implies SDR50 support */
2554         if (caps[1] & SDHCI_SUPPORT_SDR104)
2555                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2556         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2557                 mmc->caps |= MMC_CAP_UHS_SDR50;
2558
2559         if (caps[1] & SDHCI_SUPPORT_DDR50)
2560                 mmc->caps |= MMC_CAP_UHS_DDR50;
2561
2562         /* Does the host needs tuning for SDR50? */
2563         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2564                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2565
2566         /* Driver Type(s) (A, C, D) supported by the host */
2567         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2568                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2569         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2570                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2571         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2572                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2573
2574         /* Initial value for re-tuning timer count */
2575         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2576                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2577
2578         /*
2579          * In case Re-tuning Timer is not disabled, the actual value of
2580          * re-tuning timer will be 2 ^ (n - 1).
2581          */
2582         if (host->tuning_count)
2583                 host->tuning_count = 1 << (host->tuning_count - 1);
2584
2585         /* Re-tuning mode supported by the Host Controller */
2586         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2587                              SDHCI_RETUNING_MODE_SHIFT;
2588
2589         ocr_avail = 0;
2590         /*
2591          * According to SD Host Controller spec v3.00, if the Host System
2592          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2593          * the value is meaningful only if Voltage Support in the Capabilities
2594          * register is set. The actual current value is 4 times the register
2595          * value.
2596          */
2597         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2598
2599         if (caps[0] & SDHCI_CAN_VDD_330) {
2600                 int max_current_330;
2601
2602                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2603
2604                 max_current_330 = ((max_current_caps &
2605                                    SDHCI_MAX_CURRENT_330_MASK) >>
2606                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2607                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2608
2609                 if (max_current_330 > 150)
2610                         mmc->caps |= MMC_CAP_SET_XPC_330;
2611         }
2612         if (caps[0] & SDHCI_CAN_VDD_300) {
2613                 int max_current_300;
2614
2615                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2616
2617                 max_current_300 = ((max_current_caps &
2618                                    SDHCI_MAX_CURRENT_300_MASK) >>
2619                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2620                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2621
2622                 if (max_current_300 > 150)
2623                         mmc->caps |= MMC_CAP_SET_XPC_300;
2624         }
2625         if (caps[0] & SDHCI_CAN_VDD_180) {
2626                 int max_current_180;
2627
2628                 ocr_avail |= MMC_VDD_165_195;
2629
2630                 max_current_180 = ((max_current_caps &
2631                                    SDHCI_MAX_CURRENT_180_MASK) >>
2632                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2633                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2634
2635                 if (max_current_180 > 150)
2636                         mmc->caps |= MMC_CAP_SET_XPC_180;
2637
2638                 /* Maximum current capabilities of the host at 1.8V */
2639                 if (max_current_180 >= 800)
2640                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2641                 else if (max_current_180 >= 600)
2642                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2643                 else if (max_current_180 >= 400)
2644                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2645                 else
2646                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2647         }
2648
2649         mmc->ocr_avail = ocr_avail;
2650         mmc->ocr_avail_sdio = ocr_avail;
2651         if (host->ocr_avail_sdio)
2652                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2653         mmc->ocr_avail_sd = ocr_avail;
2654         if (host->ocr_avail_sd)
2655                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2656         else /* normal SD controllers don't support 1.8V */
2657                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2658         mmc->ocr_avail_mmc = ocr_avail;
2659         if (host->ocr_avail_mmc)
2660                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2661
2662         if (mmc->ocr_avail == 0) {
2663                 printk(KERN_ERR "%s: Hardware doesn't report any "
2664                         "support voltages.\n", mmc_hostname(mmc));
2665                 return -ENODEV;
2666         }
2667
2668         spin_lock_init(&host->lock);
2669
2670         /*
2671          * Maximum number of segments. Depends on if the hardware
2672          * can do scatter/gather or not.
2673          */
2674         if (host->flags & SDHCI_USE_ADMA)
2675                 mmc->max_segs = 128;
2676         else if (host->flags & SDHCI_USE_SDMA)
2677                 mmc->max_segs = 1;
2678         else /* PIO */
2679                 mmc->max_segs = 128;
2680
2681         /*
2682          * Maximum number of sectors in one transfer. Limited by DMA boundary
2683          * size (512KiB).
2684          */
2685         mmc->max_req_size = 524288;
2686
2687         /*
2688          * Maximum segment size. Could be one segment with the maximum number
2689          * of bytes. When doing hardware scatter/gather, each entry cannot
2690          * be larger than 64 KiB though.
2691          */
2692         if (host->flags & SDHCI_USE_ADMA) {
2693                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2694                         mmc->max_seg_size = 65535;
2695                 else
2696                         mmc->max_seg_size = 65536;
2697         } else {
2698                 mmc->max_seg_size = mmc->max_req_size;
2699         }
2700
2701         /*
2702          * Maximum block size. This varies from controller to controller and
2703          * is specified in the capabilities register.
2704          */
2705         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2706                 mmc->max_blk_size = 2;
2707         } else {
2708                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2709                                 SDHCI_MAX_BLOCK_SHIFT;
2710                 if (mmc->max_blk_size >= 3) {
2711                         printk(KERN_WARNING "%s: Invalid maximum block size, "
2712                                 "assuming 512 bytes\n", mmc_hostname(mmc));
2713                         mmc->max_blk_size = 0;
2714                 }
2715         }
2716
2717         mmc->max_blk_size = 512 << mmc->max_blk_size;
2718
2719         /*
2720          * Maximum block count.
2721          */
2722         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2723
2724         /*
2725          * Init tasklets.
2726          */
2727         tasklet_init(&host->card_tasklet,
2728                 sdhci_tasklet_card, (unsigned long)host);
2729         tasklet_init(&host->finish_tasklet,
2730                 sdhci_tasklet_finish, (unsigned long)host);
2731
2732         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2733
2734         if (host->version >= SDHCI_SPEC_300) {
2735                 init_waitqueue_head(&host->buf_ready_int);
2736
2737                 /* Initialize re-tuning timer */
2738                 init_timer(&host->tuning_timer);
2739                 host->tuning_timer.data = (unsigned long)host;
2740                 host->tuning_timer.function = sdhci_tuning_timer;
2741         }
2742
2743         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2744                 mmc_hostname(mmc), host);
2745         if (ret)
2746                 goto untasklet;
2747
2748         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2749         if (IS_ERR(host->vmmc)) {
2750                 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2751                 host->vmmc = NULL;
2752         } else {
2753                 regulator_enable(host->vmmc);
2754         }
2755
2756         sdhci_init(host, 0);
2757
2758 #ifdef CONFIG_MMC_DEBUG
2759         sdhci_dumpregs(host);
2760 #endif
2761
2762 #ifdef SDHCI_USE_LEDS_CLASS
2763         snprintf(host->led_name, sizeof(host->led_name),
2764                 "%s::", mmc_hostname(mmc));
2765         host->led.name = host->led_name;
2766         host->led.brightness = LED_OFF;
2767         host->led.default_trigger = mmc_hostname(mmc);
2768         host->led.brightness_set = sdhci_led_control;
2769
2770         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2771         if (ret)
2772                 goto reset;
2773 #endif
2774
2775         mmiowb();
2776
2777         mmc_add_host(mmc);
2778
2779         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2780                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2781                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2782                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2783
2784         sdhci_enable_card_detection(host);
2785
2786         return 0;
2787
2788 #ifdef SDHCI_USE_LEDS_CLASS
2789 reset:
2790         sdhci_reset(host, SDHCI_RESET_ALL);
2791         free_irq(host->irq, host);
2792 #endif
2793 untasklet:
2794         tasklet_kill(&host->card_tasklet);
2795         tasklet_kill(&host->finish_tasklet);
2796
2797         return ret;
2798 }
2799
2800 EXPORT_SYMBOL_GPL(sdhci_add_host);
2801
2802 void sdhci_remove_host(struct sdhci_host *host, int dead)
2803 {
2804         unsigned long flags;
2805
2806         if (dead) {
2807                 spin_lock_irqsave(&host->lock, flags);
2808
2809                 host->flags |= SDHCI_DEVICE_DEAD;
2810
2811                 if (host->mrq) {
2812                         printk(KERN_ERR "%s: Controller removed during "
2813                                 " transfer!\n", mmc_hostname(host->mmc));
2814
2815                         host->mrq->cmd->error = -ENOMEDIUM;
2816                         tasklet_schedule(&host->finish_tasklet);
2817                 }
2818
2819                 spin_unlock_irqrestore(&host->lock, flags);
2820         }
2821
2822         sdhci_disable_card_detection(host);
2823
2824         mmc_remove_host(host->mmc);
2825
2826 #ifdef SDHCI_USE_LEDS_CLASS
2827         led_classdev_unregister(&host->led);
2828 #endif
2829
2830         if (!dead)
2831                 sdhci_reset(host, SDHCI_RESET_ALL);
2832
2833         free_irq(host->irq, host);
2834
2835         del_timer_sync(&host->timer);
2836         if (host->version >= SDHCI_SPEC_300)
2837                 del_timer_sync(&host->tuning_timer);
2838
2839         tasklet_kill(&host->card_tasklet);
2840         tasklet_kill(&host->finish_tasklet);
2841
2842         if (host->vmmc) {
2843                 regulator_disable(host->vmmc);
2844                 regulator_put(host->vmmc);
2845         }
2846
2847         kfree(host->adma_desc);
2848         kfree(host->align_buffer);
2849
2850         host->adma_desc = NULL;
2851         host->align_buffer = NULL;
2852 }
2853
2854 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2855
2856 void sdhci_free_host(struct sdhci_host *host)
2857 {
2858         mmc_free_host(host->mmc);
2859 }
2860
2861 EXPORT_SYMBOL_GPL(sdhci_free_host);
2862
2863 /*****************************************************************************\
2864  *                                                                           *
2865  * Driver init/exit                                                          *
2866  *                                                                           *
2867 \*****************************************************************************/
2868
2869 static int __init sdhci_drv_init(void)
2870 {
2871         printk(KERN_INFO DRIVER_NAME
2872                 ": Secure Digital Host Controller Interface driver\n");
2873         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2874
2875         return 0;
2876 }
2877
2878 static void __exit sdhci_drv_exit(void)
2879 {
2880 }
2881
2882 module_init(sdhci_drv_init);
2883 module_exit(sdhci_drv_exit);
2884
2885 module_param(debug_quirks, uint, 0444);
2886
2887 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2888 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2889 MODULE_LICENSE("GPL");
2890
2891 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");