drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/highmem.h>
  14 #include <linux/pci.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/scatterlist.h>
  17
  18 #include <linux/mmc/host.h>
  19
  20 #include <asm/scatterlist.h>
  21
  22 #include "sdhci.h"
  23
  24 #define DRIVER_NAME "sdhci"
  25
  26 #define DBG(f, x...) \
  27         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  28
  29 static unsigned int debug_quirks = 0;
  30
  31 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
  32 #define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
  33 /* Controller doesn't like some resets when there is no card inserted. */
  34 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
  35 #define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
  36 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
  37 #define SDHCI_QUIRK_BROKEN_DMA                          (1<<5)
  38
  39 static const struct pci_device_id pci_ids[] __devinitdata = {
  40         {
  41                 .vendor         = PCI_VENDOR_ID_RICOH,
  42                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  43                 .subvendor      = PCI_VENDOR_ID_IBM,
  44                 .subdevice      = PCI_ANY_ID,
  45                 .driver_data    = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  46                                   SDHCI_QUIRK_FORCE_DMA,
  47         },
  48
  49         {
  50                 .vendor         = PCI_VENDOR_ID_RICOH,
  51                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  52                 .subvendor      = PCI_ANY_ID,
  53                 .subdevice      = PCI_ANY_ID,
  54                 .driver_data    = SDHCI_QUIRK_FORCE_DMA |
  55                                   SDHCI_QUIRK_NO_CARD_NO_RESET,
  56         },
  57
  58         {
  59                 .vendor         = PCI_VENDOR_ID_TI,
  60                 .device         = PCI_DEVICE_ID_TI_XX21_XX11_SD,
  61                 .subvendor      = PCI_ANY_ID,
  62                 .subdevice      = PCI_ANY_ID,
  63                 .driver_data    = SDHCI_QUIRK_FORCE_DMA,
  64         },
  65
  66         {
  67                 .vendor         = PCI_VENDOR_ID_ENE,
  68                 .device         = PCI_DEVICE_ID_ENE_CB712_SD,
  69                 .subvendor      = PCI_ANY_ID,
  70                 .subdevice      = PCI_ANY_ID,
  71                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  72                                   SDHCI_QUIRK_BROKEN_DMA,
  73         },
  74
  75         {
  76                 .vendor         = PCI_VENDOR_ID_ENE,
  77                 .device         = PCI_DEVICE_ID_ENE_CB712_SD_2,
  78                 .subvendor      = PCI_ANY_ID,
  79                 .subdevice      = PCI_ANY_ID,
  80                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  81                                   SDHCI_QUIRK_BROKEN_DMA,
  82         },
  83
  84         {
  85                 .vendor         = PCI_VENDOR_ID_ENE,
  86                 .device         = PCI_DEVICE_ID_ENE_CB714_SD,
  87                 .subvendor      = PCI_ANY_ID,
  88                 .subdevice      = PCI_ANY_ID,
  89                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  90                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
  91         },
  92
  93         {
  94                 .vendor         = PCI_VENDOR_ID_ENE,
  95                 .device         = PCI_DEVICE_ID_ENE_CB714_SD_2,
  96                 .subvendor      = PCI_ANY_ID,
  97                 .subdevice      = PCI_ANY_ID,
  98                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  99                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
 100         },
 101
 102         {       /* Generic SD host controller */
 103                 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
 104         },
 105
 106         { /* end: all zeroes */ },
 107 };
 108
 109 MODULE_DEVICE_TABLE(pci, pci_ids);
 110
 111 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
 112 static void sdhci_finish_data(struct sdhci_host *);
 113
 114 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
 115 static void sdhci_finish_command(struct sdhci_host *);
 116
 117 static void sdhci_dumpregs(struct sdhci_host *host)
 118 {
 119         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
 120
 121         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
 122                 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
 123                 readw(host->ioaddr + SDHCI_HOST_VERSION));
 124         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
 125                 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
 126                 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
 127         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
 128                 readl(host->ioaddr + SDHCI_ARGUMENT),
 129                 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
 130         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 131                 readl(host->ioaddr + SDHCI_PRESENT_STATE),
 132                 readb(host->ioaddr + SDHCI_HOST_CONTROL));
 133         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 134                 readb(host->ioaddr + SDHCI_POWER_CONTROL),
 135                 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
 136         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 137                 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
 138                 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
 139         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 140                 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
 141                 readl(host->ioaddr + SDHCI_INT_STATUS));
 142         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 143                 readl(host->ioaddr + SDHCI_INT_ENABLE),
 144                 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
 145         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 146                 readw(host->ioaddr + SDHCI_ACMD12_ERR),
 147                 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
 148         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
 149                 readl(host->ioaddr + SDHCI_CAPABILITIES),
 150                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
 151
 152         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
 153 }
 154
 155 /*****************************************************************************\
 156  *                                                                           *
 157  * Low level functions                                                       *
 158  *                                                                           *
 159 \*****************************************************************************/
 160
 161 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 162 {
 163         unsigned long timeout;
 164
 165         if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 166                 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 167                         SDHCI_CARD_PRESENT))
 168                         return;
 169         }
 170
 171         writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
 172
 173         if (mask & SDHCI_RESET_ALL)
 174                 host->clock = 0;
 175
 176         /* Wait max 100 ms */
 177         timeout = 100;
 178
 179         /* hw clears the bit when it's done */
 180         while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
 181                 if (timeout == 0) {
 182                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 183                                 mmc_hostname(host->mmc), (int)mask);
 184                         sdhci_dumpregs(host);
 185                         return;
 186                 }
 187                 timeout--;
 188                 mdelay(1);
 189         }
 190 }
 191
 192 static void sdhci_init(struct sdhci_host *host)
 193 {
 194         u32 intmask;
 195
 196         sdhci_reset(host, SDHCI_RESET_ALL);
 197
 198         intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 199                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 200                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 201                 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
 202                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
 203                 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
 204
 205         writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
 206         writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 207 }
 208
 209 static void sdhci_activate_led(struct sdhci_host *host)
 210 {
 211         u8 ctrl;
 212
 213         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 214         ctrl |= SDHCI_CTRL_LED;
 215         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 216 }
 217
 218 static void sdhci_deactivate_led(struct sdhci_host *host)
 219 {
 220         u8 ctrl;
 221
 222         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 223         ctrl &= ~SDHCI_CTRL_LED;
 224         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 225 }
 226
 227 /*****************************************************************************\
 228  *                                                                           *
 229  * Core functions                                                            *
 230  *                                                                           *
 231 \*****************************************************************************/
 232
 233 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
 234 {
 235         return sg_virt(host->cur_sg);
 236 }
 237
 238 static inline int sdhci_next_sg(struct sdhci_host* host)
 239 {
 240         /*
 241          * Skip to next SG entry.
 242          */
 243         host->cur_sg++;
 244         host->num_sg--;
 245
 246         /*
 247          * Any entries left?
 248          */
 249         if (host->num_sg > 0) {
 250                 host->offset = 0;
 251                 host->remain = host->cur_sg->length;
 252         }
 253
 254         return host->num_sg;
 255 }
 256
 257 static void sdhci_read_block_pio(struct sdhci_host *host)
 258 {
 259         int blksize, chunk_remain;
 260         u32 data;
 261         char *buffer;
 262         int size;
 263
 264         DBG("PIO reading\n");
 265
 266         blksize = host->data->blksz;
 267         chunk_remain = 0;
 268         data = 0;
 269
 270         buffer = sdhci_sg_to_buffer(host) + host->offset;
 271
 272         while (blksize) {
 273                 if (chunk_remain == 0) {
 274                         data = readl(host->ioaddr + SDHCI_BUFFER);
 275                         chunk_remain = min(blksize, 4);
 276                 }
 277
 278                 size = min(host->remain, chunk_remain);
 279
 280                 chunk_remain -= size;
 281                 blksize -= size;
 282                 host->offset += size;
 283                 host->remain -= size;
 284
 285                 while (size) {
 286                         *buffer = data & 0xFF;
 287                         buffer++;
 288                         data >>= 8;
 289                         size--;
 290                 }
 291
 292                 if (host->remain == 0) {
 293                         if (sdhci_next_sg(host) == 0) {
 294                                 BUG_ON(blksize != 0);
 295                                 return;
 296                         }
 297                         buffer = sdhci_sg_to_buffer(host);
 298                 }
 299         }
 300 }
 301
 302 static void sdhci_write_block_pio(struct sdhci_host *host)
 303 {
 304         int blksize, chunk_remain;
 305         u32 data;
 306         char *buffer;
 307         int bytes, size;
 308
 309         DBG("PIO writing\n");
 310
 311         blksize = host->data->blksz;
 312         chunk_remain = 4;
 313         data = 0;
 314
 315         bytes = 0;
 316         buffer = sdhci_sg_to_buffer(host) + host->offset;
 317
 318         while (blksize) {
 319                 size = min(host->remain, chunk_remain);
 320
 321                 chunk_remain -= size;
 322                 blksize -= size;
 323                 host->offset += size;
 324                 host->remain -= size;
 325
 326                 while (size) {
 327                         data >>= 8;
 328                         data |= (u32)*buffer << 24;
 329                         buffer++;
 330                         size--;
 331                 }
 332
 333                 if (chunk_remain == 0) {
 334                         writel(data, host->ioaddr + SDHCI_BUFFER);
 335                         chunk_remain = min(blksize, 4);
 336                 }
 337
 338                 if (host->remain == 0) {
 339                         if (sdhci_next_sg(host) == 0) {
 340                                 BUG_ON(blksize != 0);
 341                                 return;
 342                         }
 343                         buffer = sdhci_sg_to_buffer(host);
 344                 }
 345         }
 346 }
 347
 348 static void sdhci_transfer_pio(struct sdhci_host *host)
 349 {
 350         u32 mask;
 351
 352         BUG_ON(!host->data);
 353
 354         if (host->num_sg == 0)
 355                 return;
 356
 357         if (host->data->flags & MMC_DATA_READ)
 358                 mask = SDHCI_DATA_AVAILABLE;
 359         else
 360                 mask = SDHCI_SPACE_AVAILABLE;
 361
 362         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 363                 if (host->data->flags & MMC_DATA_READ)
 364                         sdhci_read_block_pio(host);
 365                 else
 366                         sdhci_write_block_pio(host);
 367
 368                 if (host->num_sg == 0)
 369                         break;
 370         }
 371
 372         DBG("PIO transfer complete.\n");
 373 }
 374
 375 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 376 {
 377         u8 count;
 378         unsigned target_timeout, current_timeout;
 379
 380         WARN_ON(host->data);
 381
 382         if (data == NULL)
 383                 return;
 384
 385         /* Sanity checks */
 386         BUG_ON(data->blksz * data->blocks > 524288);
 387         BUG_ON(data->blksz > host->mmc->max_blk_size);
 388         BUG_ON(data->blocks > 65535);
 389
 390         host->data = data;
 391         host->data_early = 0;
 392
 393         /* timeout in us */
 394         target_timeout = data->timeout_ns / 1000 +
 395                 data->timeout_clks / host->clock;
 396
 397         /*
 398          * Figure out needed cycles.
 399          * We do this in steps in order to fit inside a 32 bit int.
 400          * The first step is the minimum timeout, which will have a
 401          * minimum resolution of 6 bits:
 402          * (1) 2^13*1000 > 2^22,
 403          * (2) host->timeout_clk < 2^16
 404          *     =>
 405          *     (1) / (2) > 2^6
 406          */
 407         count = 0;
 408         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 409         while (current_timeout < target_timeout) {
 410                 count++;
 411                 current_timeout <<= 1;
 412                 if (count >= 0xF)
 413                         break;
 414         }
 415
 416         if (count >= 0xF) {
 417                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 418                         mmc_hostname(host->mmc));
 419                 count = 0xE;
 420         }
 421
 422         writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
 423
 424         if (host->flags & SDHCI_USE_DMA) {
 425                 int count;
 426
 427                 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
 428                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 429                 BUG_ON(count != 1);
 430
 431                 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
 432         } else {
 433                 host->cur_sg = data->sg;
 434                 host->num_sg = data->sg_len;
 435
 436                 host->offset = 0;
 437                 host->remain = host->cur_sg->length;
 438         }
 439
 440         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 441         writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
 442                 host->ioaddr + SDHCI_BLOCK_SIZE);
 443         writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
 444 }
 445
 446 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 447         struct mmc_data *data)
 448 {
 449         u16 mode;
 450
 451         if (data == NULL)
 452                 return;
 453
 454         WARN_ON(!host->data);
 455
 456         mode = SDHCI_TRNS_BLK_CNT_EN;
 457         if (data->blocks > 1)
 458                 mode |= SDHCI_TRNS_MULTI;
 459         if (data->flags & MMC_DATA_READ)
 460                 mode |= SDHCI_TRNS_READ;
 461         if (host->flags & SDHCI_USE_DMA)
 462                 mode |= SDHCI_TRNS_DMA;
 463
 464         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
 465 }
 466
 467 static void sdhci_finish_data(struct sdhci_host *host)
 468 {
 469         struct mmc_data *data;
 470         u16 blocks;
 471
 472         BUG_ON(!host->data);
 473
 474         data = host->data;
 475         host->data = NULL;
 476
 477         if (host->flags & SDHCI_USE_DMA) {
 478                 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
 479                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 480         }
 481
 482         /*
 483          * Controller doesn't count down when in single block mode.
 484          */
 485         if (data->blocks == 1)
 486                 blocks = (data->error == 0) ? 0 : 1;
 487         else
 488                 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
 489         data->bytes_xfered = data->blksz * (data->blocks - blocks);
 490
 491         if (!data->error && blocks) {
 492                 printk(KERN_ERR "%s: Controller signalled completion even "
 493                         "though there were blocks left.\n",
 494                         mmc_hostname(host->mmc));
 495                 data->error = -EIO;
 496         }
 497
 498         if (data->stop) {
 499                 /*
 500                  * The controller needs a reset of internal state machines
 501                  * upon error conditions.
 502                  */
 503                 if (data->error) {
 504                         sdhci_reset(host, SDHCI_RESET_CMD);
 505                         sdhci_reset(host, SDHCI_RESET_DATA);
 506                 }
 507
 508                 sdhci_send_command(host, data->stop);
 509         } else
 510                 tasklet_schedule(&host->finish_tasklet);
 511 }
 512
 513 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 514 {
 515         int flags;
 516         u32 mask;
 517         unsigned long timeout;
 518
 519         WARN_ON(host->cmd);
 520
 521         /* Wait max 10 ms */
 522         timeout = 10;
 523
 524         mask = SDHCI_CMD_INHIBIT;
 525         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 526                 mask |= SDHCI_DATA_INHIBIT;
 527
 528         /* We shouldn't wait for data inihibit for stop commands, even
 529            though they might use busy signaling */
 530         if (host->mrq->data && (cmd == host->mrq->data->stop))
 531                 mask &= ~SDHCI_DATA_INHIBIT;
 532
 533         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 534                 if (timeout == 0) {
 535                         printk(KERN_ERR "%s: Controller never released "
 536                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 537                         sdhci_dumpregs(host);
 538                         cmd->error = -EIO;
 539                         tasklet_schedule(&host->finish_tasklet);
 540                         return;
 541                 }
 542                 timeout--;
 543                 mdelay(1);
 544         }
 545
 546         mod_timer(&host->timer, jiffies + 10 * HZ);
 547
 548         host->cmd = cmd;
 549
 550         sdhci_prepare_data(host, cmd->data);
 551
 552         writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
 553
 554         sdhci_set_transfer_mode(host, cmd->data);
 555
 556         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 557                 printk(KERN_ERR "%s: Unsupported response type!\n",
 558                         mmc_hostname(host->mmc));
 559                 cmd->error = -EINVAL;
 560                 tasklet_schedule(&host->finish_tasklet);
 561                 return;
 562         }
 563
 564         if (!(cmd->flags & MMC_RSP_PRESENT))
 565                 flags = SDHCI_CMD_RESP_NONE;
 566         else if (cmd->flags & MMC_RSP_136)
 567                 flags = SDHCI_CMD_RESP_LONG;
 568         else if (cmd->flags & MMC_RSP_BUSY)
 569                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 570         else
 571                 flags = SDHCI_CMD_RESP_SHORT;
 572
 573         if (cmd->flags & MMC_RSP_CRC)
 574                 flags |= SDHCI_CMD_CRC;
 575         if (cmd->flags & MMC_RSP_OPCODE)
 576                 flags |= SDHCI_CMD_INDEX;
 577         if (cmd->data)
 578                 flags |= SDHCI_CMD_DATA;
 579
 580         writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
 581                 host->ioaddr + SDHCI_COMMAND);
 582 }
 583
 584 static void sdhci_finish_command(struct sdhci_host *host)
 585 {
 586         int i;
 587
 588         BUG_ON(host->cmd == NULL);
 589
 590         if (host->cmd->flags & MMC_RSP_PRESENT) {
 591                 if (host->cmd->flags & MMC_RSP_136) {
 592                         /* CRC is stripped so we need to do some shifting. */
 593                         for (i = 0;i < 4;i++) {
 594                                 host->cmd->resp[i] = readl(host->ioaddr +
 595                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 596                                 if (i != 3)
 597                                         host->cmd->resp[i] |=
 598                                                 readb(host->ioaddr +
 599                                                 SDHCI_RESPONSE + (3-i)*4-1);
 600                         }
 601                 } else {
 602                         host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
 603                 }
 604         }
 605
 606         host->cmd->error = 0;
 607
 608         if (host->data && host->data_early)
 609                 sdhci_finish_data(host);
 610
 611         if (!host->cmd->data)
 612                 tasklet_schedule(&host->finish_tasklet);
 613
 614         host->cmd = NULL;
 615 }
 616
 617 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 618 {
 619         int div;
 620         u16 clk;
 621         unsigned long timeout;
 622
 623         if (clock == host->clock)
 624                 return;
 625
 626         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
 627
 628         if (clock == 0)
 629                 goto out;
 630
 631         for (div = 1;div < 256;div *= 2) {
 632                 if ((host->max_clk / div) <= clock)
 633                         break;
 634         }
 635         div >>= 1;
 636
 637         clk = div << SDHCI_DIVIDER_SHIFT;
 638         clk |= SDHCI_CLOCK_INT_EN;
 639         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 640
 641         /* Wait max 10 ms */
 642         timeout = 10;
 643         while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
 644                 & SDHCI_CLOCK_INT_STABLE)) {
 645                 if (timeout == 0) {
 646                         printk(KERN_ERR "%s: Internal clock never "
 647                                 "stabilised.\n", mmc_hostname(host->mmc));
 648                         sdhci_dumpregs(host);
 649                         return;
 650                 }
 651                 timeout--;
 652                 mdelay(1);
 653         }
 654
 655         clk |= SDHCI_CLOCK_CARD_EN;
 656         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 657
 658 out:
 659         host->clock = clock;
 660 }
 661
 662 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 663 {
 664         u8 pwr;
 665
 666         if (host->power == power)
 667                 return;
 668
 669         if (power == (unsigned short)-1) {
 670                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 671                 goto out;
 672         }
 673
 674         /*
 675          * Spec says that we should clear the power reg before setting
 676          * a new value. Some controllers don't seem to like this though.
 677          */
 678         if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
 679                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 680
 681         pwr = SDHCI_POWER_ON;
 682
 683         switch (1 << power) {
 684         case MMC_VDD_165_195:
 685                 pwr |= SDHCI_POWER_180;
 686                 break;
 687         case MMC_VDD_29_30:
 688         case MMC_VDD_30_31:
 689                 pwr |= SDHCI_POWER_300;
 690                 break;
 691         case MMC_VDD_32_33:
 692         case MMC_VDD_33_34:
 693                 pwr |= SDHCI_POWER_330;
 694                 break;
 695         default:
 696                 BUG();
 697         }
 698
 699         writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
 700
 701 out:
 702         host->power = power;
 703 }
 704
 705 /*****************************************************************************\
 706  *                                                                           *
 707  * MMC callbacks                                                             *
 708  *                                                                           *
 709 \*****************************************************************************/
 710
 711 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 712 {
 713         struct sdhci_host *host;
 714         unsigned long flags;
 715
 716         host = mmc_priv(mmc);
 717
 718         spin_lock_irqsave(&host->lock, flags);
 719
 720         WARN_ON(host->mrq != NULL);
 721
 722         sdhci_activate_led(host);
 723
 724         host->mrq = mrq;
 725
 726         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 727                 host->mrq->cmd->error = -ENOMEDIUM;
 728                 tasklet_schedule(&host->finish_tasklet);
 729         } else
 730                 sdhci_send_command(host, mrq->cmd);
 731
 732         mmiowb();
 733         spin_unlock_irqrestore(&host->lock, flags);
 734 }
 735
 736 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 737 {
 738         struct sdhci_host *host;
 739         unsigned long flags;
 740         u8 ctrl;
 741
 742         host = mmc_priv(mmc);
 743
 744         spin_lock_irqsave(&host->lock, flags);
 745
 746         /*
 747          * Reset the chip on each power off.
 748          * Should clear out any weird states.
 749          */
 750         if (ios->power_mode == MMC_POWER_OFF) {
 751                 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 752                 sdhci_init(host);
 753         }
 754
 755         sdhci_set_clock(host, ios->clock);
 756
 757         if (ios->power_mode == MMC_POWER_OFF)
 758                 sdhci_set_power(host, -1);
 759         else
 760                 sdhci_set_power(host, ios->vdd);
 761
 762         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 763
 764         if (ios->bus_width == MMC_BUS_WIDTH_4)
 765                 ctrl |= SDHCI_CTRL_4BITBUS;
 766         else
 767                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 768
 769         if (ios->timing == MMC_TIMING_SD_HS)
 770                 ctrl |= SDHCI_CTRL_HISPD;
 771         else
 772                 ctrl &= ~SDHCI_CTRL_HISPD;
 773
 774         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 775
 776         /*
 777          * Some (ENE) controllers go apeshit on some ios operation,
 778          * signalling timeout and CRC errors even on CMD0. Resetting
 779          * it on each ios seems to solve the problem.
 780          */
 781         if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
 782                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 783
 784         mmiowb();
 785         spin_unlock_irqrestore(&host->lock, flags);
 786 }
 787
 788 static int sdhci_get_ro(struct mmc_host *mmc)
 789 {
 790         struct sdhci_host *host;
 791         unsigned long flags;
 792         int present;
 793
 794         host = mmc_priv(mmc);
 795
 796         spin_lock_irqsave(&host->lock, flags);
 797
 798         present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
 799
 800         spin_unlock_irqrestore(&host->lock, flags);
 801
 802         return !(present & SDHCI_WRITE_PROTECT);
 803 }
 804
 805 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
 806 {
 807         struct sdhci_host *host;
 808         unsigned long flags;
 809         u32 ier;
 810
 811         host = mmc_priv(mmc);
 812
 813         spin_lock_irqsave(&host->lock, flags);
 814
 815         ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
 816
 817         ier &= ~SDHCI_INT_CARD_INT;
 818         if (enable)
 819                 ier |= SDHCI_INT_CARD_INT;
 820
 821         writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
 822         writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 823
 824         mmiowb();
 825
 826         spin_unlock_irqrestore(&host->lock, flags);
 827 }
 828
 829 static const struct mmc_host_ops sdhci_ops = {
 830         .request        = sdhci_request,
 831         .set_ios        = sdhci_set_ios,
 832         .get_ro         = sdhci_get_ro,
 833         .enable_sdio_irq = sdhci_enable_sdio_irq,
 834 };
 835
 836 /*****************************************************************************\
 837  *                                                                           *
 838  * Tasklets                                                                  *
 839  *                                                                           *
 840 \*****************************************************************************/
 841
 842 static void sdhci_tasklet_card(unsigned long param)
 843 {
 844         struct sdhci_host *host;
 845         unsigned long flags;
 846
 847         host = (struct sdhci_host*)param;
 848
 849         spin_lock_irqsave(&host->lock, flags);
 850
 851         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 852                 if (host->mrq) {
 853                         printk(KERN_ERR "%s: Card removed during transfer!\n",
 854                                 mmc_hostname(host->mmc));
 855                         printk(KERN_ERR "%s: Resetting controller.\n",
 856                                 mmc_hostname(host->mmc));
 857
 858                         sdhci_reset(host, SDHCI_RESET_CMD);
 859                         sdhci_reset(host, SDHCI_RESET_DATA);
 860
 861                         host->mrq->cmd->error = -ENOMEDIUM;
 862                         tasklet_schedule(&host->finish_tasklet);
 863                 }
 864         }
 865
 866         spin_unlock_irqrestore(&host->lock, flags);
 867
 868         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 869 }
 870
 871 static void sdhci_tasklet_finish(unsigned long param)
 872 {
 873         struct sdhci_host *host;
 874         unsigned long flags;
 875         struct mmc_request *mrq;
 876
 877         host = (struct sdhci_host*)param;
 878
 879         spin_lock_irqsave(&host->lock, flags);
 880
 881         del_timer(&host->timer);
 882
 883         mrq = host->mrq;
 884
 885         /*
 886          * The controller needs a reset of internal state machines
 887          * upon error conditions.
 888          */
 889         if (mrq->cmd->error ||
 890                 (mrq->data && (mrq->data->error ||
 891                 (mrq->data->stop && mrq->data->stop->error)))) {
 892
 893                 /* Some controllers need this kick or reset won't work here */
 894                 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
 895                         unsigned int clock;
 896
 897                         /* This is to force an update */
 898                         clock = host->clock;
 899                         host->clock = 0;
 900                         sdhci_set_clock(host, clock);
 901                 }
 902
 903                 /* Spec says we should do both at the same time, but Ricoh
 904                    controllers do not like that. */
 905                 sdhci_reset(host, SDHCI_RESET_CMD);
 906                 sdhci_reset(host, SDHCI_RESET_DATA);
 907         }
 908
 909         host->mrq = NULL;
 910         host->cmd = NULL;
 911         host->data = NULL;
 912
 913         sdhci_deactivate_led(host);
 914
 915         mmiowb();
 916         spin_unlock_irqrestore(&host->lock, flags);
 917
 918         mmc_request_done(host->mmc, mrq);
 919 }
 920
 921 static void sdhci_timeout_timer(unsigned long data)
 922 {
 923         struct sdhci_host *host;
 924         unsigned long flags;
 925
 926         host = (struct sdhci_host*)data;
 927
 928         spin_lock_irqsave(&host->lock, flags);
 929
 930         if (host->mrq) {
 931                 printk(KERN_ERR "%s: Timeout waiting for hardware "
 932                         "interrupt.\n", mmc_hostname(host->mmc));
 933                 sdhci_dumpregs(host);
 934
 935                 if (host->data) {
 936                         host->data->error = -ETIMEDOUT;
 937                         sdhci_finish_data(host);
 938                 } else {
 939                         if (host->cmd)
 940                                 host->cmd->error = -ETIMEDOUT;
 941                         else
 942                                 host->mrq->cmd->error = -ETIMEDOUT;
 943
 944                         tasklet_schedule(&host->finish_tasklet);
 945                 }
 946         }
 947
 948         mmiowb();
 949         spin_unlock_irqrestore(&host->lock, flags);
 950 }
 951
 952 /*****************************************************************************\
 953  *                                                                           *
 954  * Interrupt handling                                                        *
 955  *                                                                           *
 956 \*****************************************************************************/
 957
 958 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
 959 {
 960         BUG_ON(intmask == 0);
 961
 962         if (!host->cmd) {
 963                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
 964                         "though no command operation was in progress.\n",
 965                         mmc_hostname(host->mmc), (unsigned)intmask);
 966                 sdhci_dumpregs(host);
 967                 return;
 968         }
 969
 970         if (intmask & SDHCI_INT_TIMEOUT)
 971                 host->cmd->error = -ETIMEDOUT;
 972         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
 973                         SDHCI_INT_INDEX))
 974                 host->cmd->error = -EILSEQ;
 975
 976         if (host->cmd->error)
 977                 tasklet_schedule(&host->finish_tasklet);
 978         else if (intmask & SDHCI_INT_RESPONSE)
 979                 sdhci_finish_command(host);
 980 }
 981
 982 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
 983 {
 984         BUG_ON(intmask == 0);
 985
 986         if (!host->data) {
 987                 /*
 988                  * A data end interrupt is sent together with the response
 989                  * for the stop command.
 990                  */
 991                 if (intmask & SDHCI_INT_DATA_END)
 992                         return;
 993
 994                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
 995                         "though no data operation was in progress.\n",
 996                         mmc_hostname(host->mmc), (unsigned)intmask);
 997                 sdhci_dumpregs(host);
 998
 999                 return;
1000         }
1001
1002         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1003                 host->data->error = -ETIMEDOUT;
1004         else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1005                 host->data->error = -EILSEQ;
1006
1007         if (host->data->error)
1008                 sdhci_finish_data(host);
1009         else {
1010                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1011                         sdhci_transfer_pio(host);
1012
1013                 /*
1014                  * We currently don't do anything fancy with DMA
1015                  * boundaries, but as we can't disable the feature
1016                  * we need to at least restart the transfer.
1017                  */
1018                 if (intmask & SDHCI_INT_DMA_END)
1019                         writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1020                                 host->ioaddr + SDHCI_DMA_ADDRESS);
1021
1022                 if (intmask & SDHCI_INT_DATA_END) {
1023                         if (host->cmd) {
1024                                 /*
1025                                  * Data managed to finish before the
1026                                  * command completed. Make sure we do
1027                                  * things in the proper order.
1028                                  */
1029                                 host->data_early = 1;
1030                         } else {
1031                                 sdhci_finish_data(host);
1032                         }
1033                 }
1034         }
1035 }
1036
1037 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1038 {
1039         irqreturn_t result;
1040         struct sdhci_host* host = dev_id;
1041         u32 intmask;
1042         int cardint = 0;
1043
1044         spin_lock(&host->lock);
1045
1046         intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1047
1048         if (!intmask || intmask == 0xffffffff) {
1049                 result = IRQ_NONE;
1050                 goto out;
1051         }
1052
1053         DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1054
1055         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1056                 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1057                         host->ioaddr + SDHCI_INT_STATUS);
1058                 tasklet_schedule(&host->card_tasklet);
1059         }
1060
1061         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1062
1063         if (intmask & SDHCI_INT_CMD_MASK) {
1064                 writel(intmask & SDHCI_INT_CMD_MASK,
1065                         host->ioaddr + SDHCI_INT_STATUS);
1066                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1067         }
1068
1069         if (intmask & SDHCI_INT_DATA_MASK) {
1070                 writel(intmask & SDHCI_INT_DATA_MASK,
1071                         host->ioaddr + SDHCI_INT_STATUS);
1072                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1073         }
1074
1075         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1076
1077         intmask &= ~SDHCI_INT_ERROR;
1078
1079         if (intmask & SDHCI_INT_BUS_POWER) {
1080                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1081                         mmc_hostname(host->mmc));
1082                 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1083         }
1084
1085         intmask &= ~SDHCI_INT_BUS_POWER;
1086
1087         if (intmask & SDHCI_INT_CARD_INT)
1088                 cardint = 1;
1089
1090         intmask &= ~SDHCI_INT_CARD_INT;
1091
1092         if (intmask) {
1093                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1094                         mmc_hostname(host->mmc), intmask);
1095                 sdhci_dumpregs(host);
1096
1097                 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1098         }
1099
1100         result = IRQ_HANDLED;
1101
1102         mmiowb();
1103 out:
1104         spin_unlock(&host->lock);
1105
1106         /*
1107          * We have to delay this as it calls back into the driver.
1108          */
1109         if (cardint)
1110                 mmc_signal_sdio_irq(host->mmc);
1111
1112         return result;
1113 }
1114
1115 /*****************************************************************************\
1116  *                                                                           *
1117  * Suspend/resume                                                            *
1118  *                                                                           *
1119 \*****************************************************************************/
1120
1121 #ifdef CONFIG_PM
1122
1123 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1124 {
1125         struct sdhci_chip *chip;
1126         int i, ret;
1127
1128         chip = pci_get_drvdata(pdev);
1129         if (!chip)
1130                 return 0;
1131
1132         DBG("Suspending...\n");
1133
1134         for (i = 0;i < chip->num_slots;i++) {
1135                 if (!chip->hosts[i])
1136                         continue;
1137                 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1138                 if (ret) {
1139                         for (i--;i >= 0;i--)
1140                                 mmc_resume_host(chip->hosts[i]->mmc);
1141                         return ret;
1142                 }
1143         }
1144
1145         pci_save_state(pdev);
1146         pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1147
1148         for (i = 0;i < chip->num_slots;i++) {
1149                 if (!chip->hosts[i])
1150                         continue;
1151                 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1152         }
1153
1154         pci_disable_device(pdev);
1155         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1156
1157         return 0;
1158 }
1159
1160 static int sdhci_resume (struct pci_dev *pdev)
1161 {
1162         struct sdhci_chip *chip;
1163         int i, ret;
1164
1165         chip = pci_get_drvdata(pdev);
1166         if (!chip)
1167                 return 0;
1168
1169         DBG("Resuming...\n");
1170
1171         pci_set_power_state(pdev, PCI_D0);
1172         pci_restore_state(pdev);
1173         ret = pci_enable_device(pdev);
1174         if (ret)
1175                 return ret;
1176
1177         for (i = 0;i < chip->num_slots;i++) {
1178                 if (!chip->hosts[i])
1179                         continue;
1180                 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1181                         pci_set_master(pdev);
1182                 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1183                         IRQF_SHARED, chip->hosts[i]->slot_descr,
1184                         chip->hosts[i]);
1185                 if (ret)
1186                         return ret;
1187                 sdhci_init(chip->hosts[i]);
1188                 mmiowb();
1189                 ret = mmc_resume_host(chip->hosts[i]->mmc);
1190                 if (ret)
1191                         return ret;
1192         }
1193
1194         return 0;
1195 }
1196
1197 #else /* CONFIG_PM */
1198
1199 #define sdhci_suspend NULL
1200 #define sdhci_resume NULL
1201
1202 #endif /* CONFIG_PM */
1203
1204 /*****************************************************************************\
1205  *                                                                           *
1206  * Device probing/removal                                                    *
1207  *                                                                           *
1208 \*****************************************************************************/
1209
1210 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1211 {
1212         int ret;
1213         unsigned int version;
1214         struct sdhci_chip *chip;
1215         struct mmc_host *mmc;
1216         struct sdhci_host *host;
1217
1218         u8 first_bar;
1219         unsigned int caps;
1220
1221         chip = pci_get_drvdata(pdev);
1222         BUG_ON(!chip);
1223
1224         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1225         if (ret)
1226                 return ret;
1227
1228         first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1229
1230         if (first_bar > 5) {
1231                 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1232                 return -ENODEV;
1233         }
1234
1235         if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1236                 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1237                 return -ENODEV;
1238         }
1239
1240         if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1241                 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1242                         "You may experience problems.\n");
1243         }
1244
1245         if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1246                 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1247                 return -ENODEV;
1248         }
1249
1250         if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1251                 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1252                 return -ENODEV;
1253         }
1254
1255         mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1256         if (!mmc)
1257                 return -ENOMEM;
1258
1259         host = mmc_priv(mmc);
1260         host->mmc = mmc;
1261
1262         host->chip = chip;
1263         chip->hosts[slot] = host;
1264
1265         host->bar = first_bar + slot;
1266
1267         host->addr = pci_resource_start(pdev, host->bar);
1268         host->irq = pdev->irq;
1269
1270         DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1271
1272         snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1273
1274         ret = pci_request_region(pdev, host->bar, host->slot_descr);
1275         if (ret)
1276                 goto free;
1277
1278         host->ioaddr = ioremap_nocache(host->addr,
1279                 pci_resource_len(pdev, host->bar));
1280         if (!host->ioaddr) {
1281                 ret = -ENOMEM;
1282                 goto release;
1283         }
1284
1285         sdhci_reset(host, SDHCI_RESET_ALL);
1286
1287         version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1288         version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1289         if (version != 0) {
1290                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1291                         "You may experience problems.\n", host->slot_descr,
1292                         version);
1293         }
1294
1295         caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1296
1297         if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1298                 host->flags |= SDHCI_USE_DMA;
1299         else if (!(caps & SDHCI_CAN_DO_DMA))
1300                 DBG("Controller doesn't have DMA capability\n");
1301         else
1302                 host->flags |= SDHCI_USE_DMA;
1303
1304         if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1305                 (host->flags & SDHCI_USE_DMA)) {
1306                 DBG("Disabling DMA as it is marked broken");
1307                 host->flags &= ~SDHCI_USE_DMA;
1308         }
1309
1310         if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1311                 (host->flags & SDHCI_USE_DMA)) {
1312                 printk(KERN_WARNING "%s: Will use DMA "
1313                         "mode even though HW doesn't fully "
1314                         "claim to support it.\n", host->slot_descr);
1315         }
1316
1317         if (host->flags & SDHCI_USE_DMA) {
1318                 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1319                         printk(KERN_WARNING "%s: No suitable DMA available. "
1320                                 "Falling back to PIO.\n", host->slot_descr);
1321                         host->flags &= ~SDHCI_USE_DMA;
1322                 }
1323         }
1324
1325         if (host->flags & SDHCI_USE_DMA)
1326                 pci_set_master(pdev);
1327         else /* XXX: Hack to get MMC layer to avoid highmem */
1328                 pdev->dma_mask = 0;
1329
1330         host->max_clk =
1331                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1332         if (host->max_clk == 0) {
1333                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1334                         "frequency.\n", host->slot_descr);
1335                 ret = -ENODEV;
1336                 goto unmap;
1337         }
1338         host->max_clk *= 1000000;
1339
1340         host->timeout_clk =
1341                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1342         if (host->timeout_clk == 0) {
1343                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1344                         "frequency.\n", host->slot_descr);
1345                 ret = -ENODEV;
1346                 goto unmap;
1347         }
1348         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1349                 host->timeout_clk *= 1000;
1350
1351         /*
1352          * Set host parameters.
1353          */
1354         mmc->ops = &sdhci_ops;
1355         mmc->f_min = host->max_clk / 256;
1356         mmc->f_max = host->max_clk;
1357         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
1358
1359         if (caps & SDHCI_CAN_DO_HISPD)
1360                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1361
1362         mmc->ocr_avail = 0;
1363         if (caps & SDHCI_CAN_VDD_330)
1364                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1365         if (caps & SDHCI_CAN_VDD_300)
1366                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1367         if (caps & SDHCI_CAN_VDD_180)
1368                 mmc->ocr_avail |= MMC_VDD_165_195;
1369
1370         if (mmc->ocr_avail == 0) {
1371                 printk(KERN_ERR "%s: Hardware doesn't report any "
1372                         "support voltages.\n", host->slot_descr);
1373                 ret = -ENODEV;
1374                 goto unmap;
1375         }
1376
1377         spin_lock_init(&host->lock);
1378
1379         /*
1380          * Maximum number of segments. Hardware cannot do scatter lists.
1381          */
1382         if (host->flags & SDHCI_USE_DMA)
1383                 mmc->max_hw_segs = 1;
1384         else
1385                 mmc->max_hw_segs = 16;
1386         mmc->max_phys_segs = 16;
1387
1388         /*
1389          * Maximum number of sectors in one transfer. Limited by DMA boundary
1390          * size (512KiB).
1391          */
1392         mmc->max_req_size = 524288;
1393
1394         /*
1395          * Maximum segment size. Could be one segment with the maximum number
1396          * of bytes.
1397          */
1398         mmc->max_seg_size = mmc->max_req_size;
1399
1400         /*
1401          * Maximum block size. This varies from controller to controller and
1402          * is specified in the capabilities register.
1403          */
1404         mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1405         if (mmc->max_blk_size >= 3) {
1406                 printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n",
1407                         host->slot_descr);
1408                 mmc->max_blk_size = 512;
1409         } else
1410                 mmc->max_blk_size = 512 << mmc->max_blk_size;
1411
1412         /*
1413          * Maximum block count.
1414          */
1415         mmc->max_blk_count = 65535;
1416
1417         /*
1418          * Init tasklets.
1419          */
1420         tasklet_init(&host->card_tasklet,
1421                 sdhci_tasklet_card, (unsigned long)host);
1422         tasklet_init(&host->finish_tasklet,
1423                 sdhci_tasklet_finish, (unsigned long)host);
1424
1425         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1426
1427         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1428                 host->slot_descr, host);
1429         if (ret)
1430                 goto untasklet;
1431
1432         sdhci_init(host);
1433
1434 #ifdef CONFIG_MMC_DEBUG
1435         sdhci_dumpregs(host);
1436 #endif
1437
1438         mmiowb();
1439
1440         mmc_add_host(mmc);
1441
1442         printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1443                 host->addr, host->irq,
1444                 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1445
1446         return 0;
1447
1448 untasklet:
1449         tasklet_kill(&host->card_tasklet);
1450         tasklet_kill(&host->finish_tasklet);
1451 unmap:
1452         iounmap(host->ioaddr);
1453 release:
1454         pci_release_region(pdev, host->bar);
1455 free:
1456         mmc_free_host(mmc);
1457
1458         return ret;
1459 }
1460
1461 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1462 {
1463         struct sdhci_chip *chip;
1464         struct mmc_host *mmc;
1465         struct sdhci_host *host;
1466
1467         chip = pci_get_drvdata(pdev);
1468         host = chip->hosts[slot];
1469         mmc = host->mmc;
1470
1471         chip->hosts[slot] = NULL;
1472
1473         mmc_remove_host(mmc);
1474
1475         sdhci_reset(host, SDHCI_RESET_ALL);
1476
1477         free_irq(host->irq, host);
1478
1479         del_timer_sync(&host->timer);
1480
1481         tasklet_kill(&host->card_tasklet);
1482         tasklet_kill(&host->finish_tasklet);
1483
1484         iounmap(host->ioaddr);
1485
1486         pci_release_region(pdev, host->bar);
1487
1488         mmc_free_host(mmc);
1489 }
1490
1491 static int __devinit sdhci_probe(struct pci_dev *pdev,
1492         const struct pci_device_id *ent)
1493 {
1494         int ret, i;
1495         u8 slots, rev;
1496         struct sdhci_chip *chip;
1497
1498         BUG_ON(pdev == NULL);
1499         BUG_ON(ent == NULL);
1500
1501         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1502
1503         printk(KERN_INFO DRIVER_NAME
1504                 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1505                 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1506                 (int)rev);
1507
1508         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1509         if (ret)
1510                 return ret;
1511
1512         slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1513         DBG("found %d slot(s)\n", slots);
1514         if (slots == 0)
1515                 return -ENODEV;
1516
1517         ret = pci_enable_device(pdev);
1518         if (ret)
1519                 return ret;
1520
1521         chip = kzalloc(sizeof(struct sdhci_chip) +
1522                 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1523         if (!chip) {
1524                 ret = -ENOMEM;
1525                 goto err;
1526         }
1527
1528         chip->pdev = pdev;
1529         chip->quirks = ent->driver_data;
1530
1531         if (debug_quirks)
1532                 chip->quirks = debug_quirks;
1533
1534         chip->num_slots = slots;
1535         pci_set_drvdata(pdev, chip);
1536
1537         for (i = 0;i < slots;i++) {
1538                 ret = sdhci_probe_slot(pdev, i);
1539                 if (ret) {
1540                         for (i--;i >= 0;i--)
1541                                 sdhci_remove_slot(pdev, i);
1542                         goto free;
1543                 }
1544         }
1545
1546         return 0;
1547
1548 free:
1549         pci_set_drvdata(pdev, NULL);
1550         kfree(chip);
1551
1552 err:
1553         pci_disable_device(pdev);
1554         return ret;
1555 }
1556
1557 static void __devexit sdhci_remove(struct pci_dev *pdev)
1558 {
1559         int i;
1560         struct sdhci_chip *chip;
1561
1562         chip = pci_get_drvdata(pdev);
1563
1564         if (chip) {
1565                 for (i = 0;i < chip->num_slots;i++)
1566                         sdhci_remove_slot(pdev, i);
1567
1568                 pci_set_drvdata(pdev, NULL);
1569
1570                 kfree(chip);
1571         }
1572
1573         pci_disable_device(pdev);
1574 }
1575
1576 static struct pci_driver sdhci_driver = {
1577         .name =         DRIVER_NAME,
1578         .id_table =     pci_ids,
1579         .probe =        sdhci_probe,
1580         .remove =       __devexit_p(sdhci_remove),
1581         .suspend =      sdhci_suspend,
1582         .resume =       sdhci_resume,
1583 };
1584
1585 /*****************************************************************************\
1586  *                                                                           *
1587  * Driver init/exit                                                          *
1588  *                                                                           *
1589 \*****************************************************************************/
1590
1591 static int __init sdhci_drv_init(void)
1592 {
1593         printk(KERN_INFO DRIVER_NAME
1594                 ": Secure Digital Host Controller Interface driver\n");
1595         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1596
1597         return pci_register_driver(&sdhci_driver);
1598 }
1599
1600 static void __exit sdhci_drv_exit(void)
1601 {
1602         DBG("Exiting\n");
1603
1604         pci_unregister_driver(&sdhci_driver);
1605 }
1606
1607 module_init(sdhci_drv_init);
1608 module_exit(sdhci_drv_exit);
1609
1610 module_param(debug_quirks, uint, 0444);
1611
1612 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1613 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1614 MODULE_LICENSE("GPL");
1615
1616 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");