drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/slab.h>
  21 #include <linux/scatterlist.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include <linux/leds.h>
  25
  26 #include <linux/mmc/mmc.h>
  27 #include <linux/mmc/host.h>
  28
  29 #include "sdhci.h"
  30
  31 #define DRIVER_NAME "sdhci"
  32
  33 #define DBG(f, x...) \
  34         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  35
  36 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  37         defined(CONFIG_MMC_SDHCI_MODULE))
  38 #define SDHCI_USE_LEDS_CLASS
  39 #endif
  40
  41 #define MAX_TUNING_LOOP 40
  42
  43 static unsigned int debug_quirks = 0;
  44
  45 static void sdhci_finish_data(struct sdhci_host *);
  46
  47 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  48 static void sdhci_finish_command(struct sdhci_host *);
  49 static int sdhci_execute_tuning(struct mmc_host *mmc);
  50 static void sdhci_tuning_timer(unsigned long data);
  51
  52 static void sdhci_dumpregs(struct sdhci_host *host)
  53 {
  54         printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  55                 mmc_hostname(host->mmc));
  56
  57         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  58                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  59                 sdhci_readw(host, SDHCI_HOST_VERSION));
  60         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  61                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  62                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  63         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  64                 sdhci_readl(host, SDHCI_ARGUMENT),
  65                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  66         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  67                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  68                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  69         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  70                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  71                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  72         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  73                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  74                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  75         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  76                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  77                 sdhci_readl(host, SDHCI_INT_STATUS));
  78         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  79                 sdhci_readl(host, SDHCI_INT_ENABLE),
  80                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  81         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  82                 sdhci_readw(host, SDHCI_ACMD12_ERR),
  83                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  84         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
  85                 sdhci_readl(host, SDHCI_CAPABILITIES),
  86                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
  87         printk(KERN_DEBUG DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
  88                 sdhci_readw(host, SDHCI_COMMAND),
  89                 sdhci_readl(host, SDHCI_MAX_CURRENT));
  90         printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
  91                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
  92
  93         if (host->flags & SDHCI_USE_ADMA)
  94                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
  95                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
  96                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
  97
  98         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  99 }
 100
 101 /*****************************************************************************\
 102  *                                                                           *
 103  * Low level functions                                                       *
 104  *                                                                           *
 105 \*****************************************************************************/
 106
 107 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 108 {
 109         u32 ier;
 110
 111         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 112         ier &= ~clear;
 113         ier |= set;
 114         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 115         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 116 }
 117
 118 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 119 {
 120         sdhci_clear_set_irqs(host, 0, irqs);
 121 }
 122
 123 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 124 {
 125         sdhci_clear_set_irqs(host, irqs, 0);
 126 }
 127
 128 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 129 {
 130         u32 present, irqs;
 131
 132         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
 133                 return;
 134
 135         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 136                               SDHCI_CARD_PRESENT;
 137         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 138
 139         if (enable)
 140                 sdhci_unmask_irqs(host, irqs);
 141         else
 142                 sdhci_mask_irqs(host, irqs);
 143 }
 144
 145 static void sdhci_enable_card_detection(struct sdhci_host *host)
 146 {
 147         sdhci_set_card_detection(host, true);
 148 }
 149
 150 static void sdhci_disable_card_detection(struct sdhci_host *host)
 151 {
 152         sdhci_set_card_detection(host, false);
 153 }
 154
 155 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 156 {
 157         unsigned long timeout;
 158         u32 uninitialized_var(ier);
 159
 160         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 161                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 162                         SDHCI_CARD_PRESENT))
 163                         return;
 164         }
 165
 166         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 167                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 168
 169         if (host->ops->platform_reset_enter)
 170                 host->ops->platform_reset_enter(host, mask);
 171
 172         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 173
 174         if (mask & SDHCI_RESET_ALL)
 175                 host->clock = 0;
 176
 177         /* Wait max 100 ms */
 178         timeout = 100;
 179
 180         /* hw clears the bit when it's done */
 181         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 182                 if (timeout == 0) {
 183                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 184                                 mmc_hostname(host->mmc), (int)mask);
 185                         sdhci_dumpregs(host);
 186                         return;
 187                 }
 188                 timeout--;
 189                 mdelay(1);
 190         }
 191
 192         if (host->ops->platform_reset_exit)
 193                 host->ops->platform_reset_exit(host, mask);
 194
 195         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 196                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 197 }
 198
 199 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 200
 201 static void sdhci_init(struct sdhci_host *host, int soft)
 202 {
 203         if (soft)
 204                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 205         else
 206                 sdhci_reset(host, SDHCI_RESET_ALL);
 207
 208         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 209                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 210                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 211                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 212                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 213
 214         if (soft) {
 215                 /* force clock reconfiguration */
 216                 host->clock = 0;
 217                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 218         }
 219 }
 220
 221 static void sdhci_reinit(struct sdhci_host *host)
 222 {
 223         sdhci_init(host, 0);
 224         sdhci_enable_card_detection(host);
 225 }
 226
 227 static void sdhci_activate_led(struct sdhci_host *host)
 228 {
 229         u8 ctrl;
 230
 231         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 232         ctrl |= SDHCI_CTRL_LED;
 233         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 234 }
 235
 236 static void sdhci_deactivate_led(struct sdhci_host *host)
 237 {
 238         u8 ctrl;
 239
 240         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 241         ctrl &= ~SDHCI_CTRL_LED;
 242         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 243 }
 244
 245 #ifdef SDHCI_USE_LEDS_CLASS
 246 static void sdhci_led_control(struct led_classdev *led,
 247         enum led_brightness brightness)
 248 {
 249         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 250         unsigned long flags;
 251
 252         spin_lock_irqsave(&host->lock, flags);
 253
 254         if (brightness == LED_OFF)
 255                 sdhci_deactivate_led(host);
 256         else
 257                 sdhci_activate_led(host);
 258
 259         spin_unlock_irqrestore(&host->lock, flags);
 260 }
 261 #endif
 262
 263 /*****************************************************************************\
 264  *                                                                           *
 265  * Core functions                                                            *
 266  *                                                                           *
 267 \*****************************************************************************/
 268
 269 static void sdhci_read_block_pio(struct sdhci_host *host)
 270 {
 271         unsigned long flags;
 272         size_t blksize, len, chunk;
 273         u32 uninitialized_var(scratch);
 274         u8 *buf;
 275
 276         DBG("PIO reading\n");
 277
 278         blksize = host->data->blksz;
 279         chunk = 0;
 280
 281         local_irq_save(flags);
 282
 283         while (blksize) {
 284                 if (!sg_miter_next(&host->sg_miter))
 285                         BUG();
 286
 287                 len = min(host->sg_miter.length, blksize);
 288
 289                 blksize -= len;
 290                 host->sg_miter.consumed = len;
 291
 292                 buf = host->sg_miter.addr;
 293
 294                 while (len) {
 295                         if (chunk == 0) {
 296                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 297                                 chunk = 4;
 298                         }
 299
 300                         *buf = scratch & 0xFF;
 301
 302                         buf++;
 303                         scratch >>= 8;
 304                         chunk--;
 305                         len--;
 306                 }
 307         }
 308
 309         sg_miter_stop(&host->sg_miter);
 310
 311         local_irq_restore(flags);
 312 }
 313
 314 static void sdhci_write_block_pio(struct sdhci_host *host)
 315 {
 316         unsigned long flags;
 317         size_t blksize, len, chunk;
 318         u32 scratch;
 319         u8 *buf;
 320
 321         DBG("PIO writing\n");
 322
 323         blksize = host->data->blksz;
 324         chunk = 0;
 325         scratch = 0;
 326
 327         local_irq_save(flags);
 328
 329         while (blksize) {
 330                 if (!sg_miter_next(&host->sg_miter))
 331                         BUG();
 332
 333                 len = min(host->sg_miter.length, blksize);
 334
 335                 blksize -= len;
 336                 host->sg_miter.consumed = len;
 337
 338                 buf = host->sg_miter.addr;
 339
 340                 while (len) {
 341                         scratch |= (u32)*buf << (chunk * 8);
 342
 343                         buf++;
 344                         chunk++;
 345                         len--;
 346
 347                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 348                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 349                                 chunk = 0;
 350                                 scratch = 0;
 351                         }
 352                 }
 353         }
 354
 355         sg_miter_stop(&host->sg_miter);
 356
 357         local_irq_restore(flags);
 358 }
 359
 360 static void sdhci_transfer_pio(struct sdhci_host *host)
 361 {
 362         u32 mask;
 363
 364         BUG_ON(!host->data);
 365
 366         if (host->blocks == 0)
 367                 return;
 368
 369         if (host->data->flags & MMC_DATA_READ)
 370                 mask = SDHCI_DATA_AVAILABLE;
 371         else
 372                 mask = SDHCI_SPACE_AVAILABLE;
 373
 374         /*
 375          * Some controllers (JMicron JMB38x) mess up the buffer bits
 376          * for transfers < 4 bytes. As long as it is just one block,
 377          * we can ignore the bits.
 378          */
 379         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 380                 (host->data->blocks == 1))
 381                 mask = ~0;
 382
 383         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 384                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 385                         udelay(100);
 386
 387                 if (host->data->flags & MMC_DATA_READ)
 388                         sdhci_read_block_pio(host);
 389                 else
 390                         sdhci_write_block_pio(host);
 391
 392                 host->blocks--;
 393                 if (host->blocks == 0)
 394                         break;
 395         }
 396
 397         DBG("PIO transfer complete.\n");
 398 }
 399
 400 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 401 {
 402         local_irq_save(*flags);
 403         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 404 }
 405
 406 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 407 {
 408         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 409         local_irq_restore(*flags);
 410 }
 411
 412 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 413 {
 414         __le32 *dataddr = (__le32 __force *)(desc + 4);
 415         __le16 *cmdlen = (__le16 __force *)desc;
 416
 417         /* SDHCI specification says ADMA descriptors should be 4 byte
 418          * aligned, so using 16 or 32bit operations should be safe. */
 419
 420         cmdlen[0] = cpu_to_le16(cmd);
 421         cmdlen[1] = cpu_to_le16(len);
 422
 423         dataddr[0] = cpu_to_le32(addr);
 424 }
 425
 426 static int sdhci_adma_table_pre(struct sdhci_host *host,
 427         struct mmc_data *data)
 428 {
 429         int direction;
 430
 431         u8 *desc;
 432         u8 *align;
 433         dma_addr_t addr;
 434         dma_addr_t align_addr;
 435         int len, offset;
 436
 437         struct scatterlist *sg;
 438         int i;
 439         char *buffer;
 440         unsigned long flags;
 441
 442         /*
 443          * The spec does not specify endianness of descriptor table.
 444          * We currently guess that it is LE.
 445          */
 446
 447         if (data->flags & MMC_DATA_READ)
 448                 direction = DMA_FROM_DEVICE;
 449         else
 450                 direction = DMA_TO_DEVICE;
 451
 452         /*
 453          * The ADMA descriptor table is mapped further down as we
 454          * need to fill it with data first.
 455          */
 456
 457         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 458                 host->align_buffer, 128 * 4, direction);
 459         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 460                 goto fail;
 461         BUG_ON(host->align_addr & 0x3);
 462
 463         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 464                 data->sg, data->sg_len, direction);
 465         if (host->sg_count == 0)
 466                 goto unmap_align;
 467
 468         desc = host->adma_desc;
 469         align = host->align_buffer;
 470
 471         align_addr = host->align_addr;
 472
 473         for_each_sg(data->sg, sg, host->sg_count, i) {
 474                 addr = sg_dma_address(sg);
 475                 len = sg_dma_len(sg);
 476
 477                 /*
 478                  * The SDHCI specification states that ADMA
 479                  * addresses must be 32-bit aligned. If they
 480                  * aren't, then we use a bounce buffer for
 481                  * the (up to three) bytes that screw up the
 482                  * alignment.
 483                  */
 484                 offset = (4 - (addr & 0x3)) & 0x3;
 485                 if (offset) {
 486                         if (data->flags & MMC_DATA_WRITE) {
 487                                 buffer = sdhci_kmap_atomic(sg, &flags);
 488                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 489                                 memcpy(align, buffer, offset);
 490                                 sdhci_kunmap_atomic(buffer, &flags);
 491                         }
 492
 493                         /* tran, valid */
 494                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 495
 496                         BUG_ON(offset > 65536);
 497
 498                         align += 4;
 499                         align_addr += 4;
 500
 501                         desc += 8;
 502
 503                         addr += offset;
 504                         len -= offset;
 505                 }
 506
 507                 BUG_ON(len > 65536);
 508
 509                 /* tran, valid */
 510                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 511                 desc += 8;
 512
 513                 /*
 514                  * If this triggers then we have a calculation bug
 515                  * somewhere. :/
 516                  */
 517                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 518         }
 519
 520         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 521                 /*
 522                 * Mark the last descriptor as the terminating descriptor
 523                 */
 524                 if (desc != host->adma_desc) {
 525                         desc -= 8;
 526                         desc[0] |= 0x2; /* end */
 527                 }
 528         } else {
 529                 /*
 530                 * Add a terminating entry.
 531                 */
 532
 533                 /* nop, end, valid */
 534                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 535         }
 536
 537         /*
 538          * Resync align buffer as we might have changed it.
 539          */
 540         if (data->flags & MMC_DATA_WRITE) {
 541                 dma_sync_single_for_device(mmc_dev(host->mmc),
 542                         host->align_addr, 128 * 4, direction);
 543         }
 544
 545         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 546                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 547         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 548                 goto unmap_entries;
 549         BUG_ON(host->adma_addr & 0x3);
 550
 551         return 0;
 552
 553 unmap_entries:
 554         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 555                 data->sg_len, direction);
 556 unmap_align:
 557         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 558                 128 * 4, direction);
 559 fail:
 560         return -EINVAL;
 561 }
 562
 563 static void sdhci_adma_table_post(struct sdhci_host *host,
 564         struct mmc_data *data)
 565 {
 566         int direction;
 567
 568         struct scatterlist *sg;
 569         int i, size;
 570         u8 *align;
 571         char *buffer;
 572         unsigned long flags;
 573
 574         if (data->flags & MMC_DATA_READ)
 575                 direction = DMA_FROM_DEVICE;
 576         else
 577                 direction = DMA_TO_DEVICE;
 578
 579         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 580                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 581
 582         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 583                 128 * 4, direction);
 584
 585         if (data->flags & MMC_DATA_READ) {
 586                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 587                         data->sg_len, direction);
 588
 589                 align = host->align_buffer;
 590
 591                 for_each_sg(data->sg, sg, host->sg_count, i) {
 592                         if (sg_dma_address(sg) & 0x3) {
 593                                 size = 4 - (sg_dma_address(sg) & 0x3);
 594
 595                                 buffer = sdhci_kmap_atomic(sg, &flags);
 596                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 597                                 memcpy(buffer, align, size);
 598                                 sdhci_kunmap_atomic(buffer, &flags);
 599
 600                                 align += 4;
 601                         }
 602                 }
 603         }
 604
 605         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 606                 data->sg_len, direction);
 607 }
 608
 609 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 610 {
 611         u8 count;
 612         struct mmc_data *data = cmd->data;
 613         unsigned target_timeout, current_timeout;
 614
 615         /*
 616          * If the host controller provides us with an incorrect timeout
 617          * value, just skip the check and use 0xE.  The hardware may take
 618          * longer to time out, but that's much better than having a too-short
 619          * timeout value.
 620          */
 621         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 622                 return 0xE;
 623
 624         /* Unspecified timeout, assume max */
 625         if (!data && !cmd->cmd_timeout_ms)
 626                 return 0xE;
 627
 628         /* timeout in us */
 629         if (!data)
 630                 target_timeout = cmd->cmd_timeout_ms * 1000;
 631         else {
 632                 target_timeout = data->timeout_ns / 1000;
 633                 if (host->clock)
 634                         target_timeout += data->timeout_clks / host->clock;
 635         }
 636
 637         /*
 638          * Figure out needed cycles.
 639          * We do this in steps in order to fit inside a 32 bit int.
 640          * The first step is the minimum timeout, which will have a
 641          * minimum resolution of 6 bits:
 642          * (1) 2^13*1000 > 2^22,
 643          * (2) host->timeout_clk < 2^16
 644          *     =>
 645          *     (1) / (2) > 2^6
 646          */
 647         count = 0;
 648         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 649         while (current_timeout < target_timeout) {
 650                 count++;
 651                 current_timeout <<= 1;
 652                 if (count >= 0xF)
 653                         break;
 654         }
 655
 656         if (count >= 0xF) {
 657                 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
 658                        mmc_hostname(host->mmc), cmd->opcode);
 659                 count = 0xE;
 660         }
 661
 662         return count;
 663 }
 664
 665 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 666 {
 667         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 668         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 669
 670         if (host->flags & SDHCI_REQ_USE_DMA)
 671                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 672         else
 673                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 674 }
 675
 676 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 677 {
 678         u8 count;
 679         u8 ctrl;
 680         struct mmc_data *data = cmd->data;
 681         int ret;
 682
 683         WARN_ON(host->data);
 684
 685         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 686                 count = sdhci_calc_timeout(host, cmd);
 687                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 688         }
 689
 690         if (!data)
 691                 return;
 692
 693         /* Sanity checks */
 694         BUG_ON(data->blksz * data->blocks > 524288);
 695         BUG_ON(data->blksz > host->mmc->max_blk_size);
 696         BUG_ON(data->blocks > 65535);
 697
 698         host->data = data;
 699         host->data_early = 0;
 700         host->data->bytes_xfered = 0;
 701
 702         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 703                 host->flags |= SDHCI_REQ_USE_DMA;
 704
 705         /*
 706          * FIXME: This doesn't account for merging when mapping the
 707          * scatterlist.
 708          */
 709         if (host->flags & SDHCI_REQ_USE_DMA) {
 710                 int broken, i;
 711                 struct scatterlist *sg;
 712
 713                 broken = 0;
 714                 if (host->flags & SDHCI_USE_ADMA) {
 715                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 716                                 broken = 1;
 717                 } else {
 718                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 719                                 broken = 1;
 720                 }
 721
 722                 if (unlikely(broken)) {
 723                         for_each_sg(data->sg, sg, data->sg_len, i) {
 724                                 if (sg->length & 0x3) {
 725                                         DBG("Reverting to PIO because of "
 726                                                 "transfer size (%d)\n",
 727                                                 sg->length);
 728                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 729                                         break;
 730                                 }
 731                         }
 732                 }
 733         }
 734
 735         /*
 736          * The assumption here being that alignment is the same after
 737          * translation to device address space.
 738          */
 739         if (host->flags & SDHCI_REQ_USE_DMA) {
 740                 int broken, i;
 741                 struct scatterlist *sg;
 742
 743                 broken = 0;
 744                 if (host->flags & SDHCI_USE_ADMA) {
 745                         /*
 746                          * As we use 3 byte chunks to work around
 747                          * alignment problems, we need to check this
 748                          * quirk.
 749                          */
 750                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 751                                 broken = 1;
 752                 } else {
 753                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 754                                 broken = 1;
 755                 }
 756
 757                 if (unlikely(broken)) {
 758                         for_each_sg(data->sg, sg, data->sg_len, i) {
 759                                 if (sg->offset & 0x3) {
 760                                         DBG("Reverting to PIO because of "
 761                                                 "bad alignment\n");
 762                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 763                                         break;
 764                                 }
 765                         }
 766                 }
 767         }
 768
 769         if (host->flags & SDHCI_REQ_USE_DMA) {
 770                 if (host->flags & SDHCI_USE_ADMA) {
 771                         ret = sdhci_adma_table_pre(host, data);
 772                         if (ret) {
 773                                 /*
 774                                  * This only happens when someone fed
 775                                  * us an invalid request.
 776                                  */
 777                                 WARN_ON(1);
 778                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 779                         } else {
 780                                 sdhci_writel(host, host->adma_addr,
 781                                         SDHCI_ADMA_ADDRESS);
 782                         }
 783                 } else {
 784                         int sg_cnt;
 785
 786                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 787                                         data->sg, data->sg_len,
 788                                         (data->flags & MMC_DATA_READ) ?
 789                                                 DMA_FROM_DEVICE :
 790                                                 DMA_TO_DEVICE);
 791                         if (sg_cnt == 0) {
 792                                 /*
 793                                  * This only happens when someone fed
 794                                  * us an invalid request.
 795                                  */
 796                                 WARN_ON(1);
 797                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 798                         } else {
 799                                 WARN_ON(sg_cnt != 1);
 800                                 sdhci_writel(host, sg_dma_address(data->sg),
 801                                         SDHCI_DMA_ADDRESS);
 802                         }
 803                 }
 804         }
 805
 806         /*
 807          * Always adjust the DMA selection as some controllers
 808          * (e.g. JMicron) can't do PIO properly when the selection
 809          * is ADMA.
 810          */
 811         if (host->version >= SDHCI_SPEC_200) {
 812                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 813                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 814                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 815                         (host->flags & SDHCI_USE_ADMA))
 816                         ctrl |= SDHCI_CTRL_ADMA32;
 817                 else
 818                         ctrl |= SDHCI_CTRL_SDMA;
 819                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 820         }
 821
 822         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 823                 int flags;
 824
 825                 flags = SG_MITER_ATOMIC;
 826                 if (host->data->flags & MMC_DATA_READ)
 827                         flags |= SG_MITER_TO_SG;
 828                 else
 829                         flags |= SG_MITER_FROM_SG;
 830                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 831                 host->blocks = data->blocks;
 832         }
 833
 834         sdhci_set_transfer_irqs(host);
 835
 836         /* Set the DMA boundary value and block size */
 837         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 838                 data->blksz), SDHCI_BLOCK_SIZE);
 839         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 840 }
 841
 842 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 843         struct mmc_command *cmd)
 844 {
 845         u16 mode;
 846         struct mmc_data *data = cmd->data;
 847
 848         if (data == NULL)
 849                 return;
 850
 851         WARN_ON(!host->data);
 852
 853         mode = SDHCI_TRNS_BLK_CNT_EN;
 854         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 855                 mode |= SDHCI_TRNS_MULTI;
 856                 /*
 857                  * If we are sending CMD23, CMD12 never gets sent
 858                  * on successful completion (so no Auto-CMD12).
 859                  */
 860                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 861                         mode |= SDHCI_TRNS_AUTO_CMD12;
 862                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 863                         mode |= SDHCI_TRNS_AUTO_CMD23;
 864                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 865                 }
 866         }
 867
 868         if (data->flags & MMC_DATA_READ)
 869                 mode |= SDHCI_TRNS_READ;
 870         if (host->flags & SDHCI_REQ_USE_DMA)
 871                 mode |= SDHCI_TRNS_DMA;
 872
 873         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 874 }
 875
 876 static void sdhci_finish_data(struct sdhci_host *host)
 877 {
 878         struct mmc_data *data;
 879
 880         BUG_ON(!host->data);
 881
 882         data = host->data;
 883         host->data = NULL;
 884
 885         if (host->flags & SDHCI_REQ_USE_DMA) {
 886                 if (host->flags & SDHCI_USE_ADMA)
 887                         sdhci_adma_table_post(host, data);
 888                 else {
 889                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 890                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 891                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 892                 }
 893         }
 894
 895         /*
 896          * The specification states that the block count register must
 897          * be updated, but it does not specify at what point in the
 898          * data flow. That makes the register entirely useless to read
 899          * back so we have to assume that nothing made it to the card
 900          * in the event of an error.
 901          */
 902         if (data->error)
 903                 data->bytes_xfered = 0;
 904         else
 905                 data->bytes_xfered = data->blksz * data->blocks;
 906
 907         /*
 908          * Need to send CMD12 if -
 909          * a) open-ended multiblock transfer (no CMD23)
 910          * b) error in multiblock transfer
 911          */
 912         if (data->stop &&
 913             (data->error ||
 914              !host->mrq->sbc)) {
 915
 916                 /*
 917                  * The controller needs a reset of internal state machines
 918                  * upon error conditions.
 919                  */
 920                 if (data->error) {
 921                         sdhci_reset(host, SDHCI_RESET_CMD);
 922                         sdhci_reset(host, SDHCI_RESET_DATA);
 923                 }
 924
 925                 sdhci_send_command(host, data->stop);
 926         } else
 927                 tasklet_schedule(&host->finish_tasklet);
 928 }
 929
 930 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 931 {
 932         int flags;
 933         u32 mask;
 934         unsigned long timeout;
 935
 936         WARN_ON(host->cmd);
 937
 938         /* Wait max 10 ms */
 939         timeout = 10;
 940
 941         mask = SDHCI_CMD_INHIBIT;
 942         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 943                 mask |= SDHCI_DATA_INHIBIT;
 944
 945         /* We shouldn't wait for data inihibit for stop commands, even
 946            though they might use busy signaling */
 947         if (host->mrq->data && (cmd == host->mrq->data->stop))
 948                 mask &= ~SDHCI_DATA_INHIBIT;
 949
 950         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 951                 if (timeout == 0) {
 952                         printk(KERN_ERR "%s: Controller never released "
 953                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 954                         sdhci_dumpregs(host);
 955                         cmd->error = -EIO;
 956                         tasklet_schedule(&host->finish_tasklet);
 957                         return;
 958                 }
 959                 timeout--;
 960                 mdelay(1);
 961         }
 962
 963         mod_timer(&host->timer, jiffies + 10 * HZ);
 964
 965         host->cmd = cmd;
 966
 967         sdhci_prepare_data(host, cmd);
 968
 969         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 970
 971         sdhci_set_transfer_mode(host, cmd);
 972
 973         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 974                 printk(KERN_ERR "%s: Unsupported response type!\n",
 975                         mmc_hostname(host->mmc));
 976                 cmd->error = -EINVAL;
 977                 tasklet_schedule(&host->finish_tasklet);
 978                 return;
 979         }
 980
 981         if (!(cmd->flags & MMC_RSP_PRESENT))
 982                 flags = SDHCI_CMD_RESP_NONE;
 983         else if (cmd->flags & MMC_RSP_136)
 984                 flags = SDHCI_CMD_RESP_LONG;
 985         else if (cmd->flags & MMC_RSP_BUSY)
 986                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 987         else
 988                 flags = SDHCI_CMD_RESP_SHORT;
 989
 990         if (cmd->flags & MMC_RSP_CRC)
 991                 flags |= SDHCI_CMD_CRC;
 992         if (cmd->flags & MMC_RSP_OPCODE)
 993                 flags |= SDHCI_CMD_INDEX;
 994
 995         /* CMD19 is special in that the Data Present Select should be set */
 996         if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
 997                 flags |= SDHCI_CMD_DATA;
 998
 999         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1000 }
1001
1002 static void sdhci_finish_command(struct sdhci_host *host)
1003 {
1004         int i;
1005
1006         BUG_ON(host->cmd == NULL);
1007
1008         if (host->cmd->flags & MMC_RSP_PRESENT) {
1009                 if (host->cmd->flags & MMC_RSP_136) {
1010                         /* CRC is stripped so we need to do some shifting. */
1011                         for (i = 0;i < 4;i++) {
1012                                 host->cmd->resp[i] = sdhci_readl(host,
1013                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1014                                 if (i != 3)
1015                                         host->cmd->resp[i] |=
1016                                                 sdhci_readb(host,
1017                                                 SDHCI_RESPONSE + (3-i)*4-1);
1018                         }
1019                 } else {
1020                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1021                 }
1022         }
1023
1024         host->cmd->error = 0;
1025
1026         /* Finished CMD23, now send actual command. */
1027         if (host->cmd == host->mrq->sbc) {
1028                 host->cmd = NULL;
1029                 sdhci_send_command(host, host->mrq->cmd);
1030         } else {
1031
1032                 /* Processed actual command. */
1033                 if (host->data && host->data_early)
1034                         sdhci_finish_data(host);
1035
1036                 if (!host->cmd->data)
1037                         tasklet_schedule(&host->finish_tasklet);
1038
1039                 host->cmd = NULL;
1040         }
1041 }
1042
1043 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1044 {
1045         int div = 0; /* Initialized for compiler warning */
1046         u16 clk = 0;
1047         unsigned long timeout;
1048
1049         if (clock == host->clock)
1050                 return;
1051
1052         if (host->ops->set_clock) {
1053                 host->ops->set_clock(host, clock);
1054                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1055                         return;
1056         }
1057
1058         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1059
1060         if (clock == 0)
1061                 goto out;
1062
1063         if (host->version >= SDHCI_SPEC_300) {
1064                 /*
1065                  * Check if the Host Controller supports Programmable Clock
1066                  * Mode.
1067                  */
1068                 if (host->clk_mul) {
1069                         u16 ctrl;
1070
1071                         /*
1072                          * We need to figure out whether the Host Driver needs
1073                          * to select Programmable Clock Mode, or the value can
1074                          * be set automatically by the Host Controller based on
1075                          * the Preset Value registers.
1076                          */
1077                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1078                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1079                                 for (div = 1; div <= 1024; div++) {
1080                                         if (((host->max_clk * host->clk_mul) /
1081                                               div) <= clock)
1082                                                 break;
1083                                 }
1084                                 /*
1085                                  * Set Programmable Clock Mode in the Clock
1086                                  * Control register.
1087                                  */
1088                                 clk = SDHCI_PROG_CLOCK_MODE;
1089                                 div--;
1090                         }
1091                 } else {
1092                         /* Version 3.00 divisors must be a multiple of 2. */
1093                         if (host->max_clk <= clock)
1094                                 div = 1;
1095                         else {
1096                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1097                                      div += 2) {
1098                                         if ((host->max_clk / div) <= clock)
1099                                                 break;
1100                                 }
1101                         }
1102                         div >>= 1;
1103                 }
1104         } else {
1105                 /* Version 2.00 divisors must be a power of 2. */
1106                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1107                         if ((host->max_clk / div) <= clock)
1108                                 break;
1109                 }
1110                 div >>= 1;
1111         }
1112
1113         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1114         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1115                 << SDHCI_DIVIDER_HI_SHIFT;
1116         clk |= SDHCI_CLOCK_INT_EN;
1117         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1118
1119         /* Wait max 20 ms */
1120         timeout = 20;
1121         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1122                 & SDHCI_CLOCK_INT_STABLE)) {
1123                 if (timeout == 0) {
1124                         printk(KERN_ERR "%s: Internal clock never "
1125                                 "stabilised.\n", mmc_hostname(host->mmc));
1126                         sdhci_dumpregs(host);
1127                         return;
1128                 }
1129                 timeout--;
1130                 mdelay(1);
1131         }
1132
1133         clk |= SDHCI_CLOCK_CARD_EN;
1134         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1135
1136 out:
1137         host->clock = clock;
1138 }
1139
1140 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1141 {
1142         u8 pwr = 0;
1143
1144         if (power != (unsigned short)-1) {
1145                 switch (1 << power) {
1146                 case MMC_VDD_165_195:
1147                         pwr = SDHCI_POWER_180;
1148                         break;
1149                 case MMC_VDD_29_30:
1150                 case MMC_VDD_30_31:
1151                         pwr = SDHCI_POWER_300;
1152                         break;
1153                 case MMC_VDD_32_33:
1154                 case MMC_VDD_33_34:
1155                         pwr = SDHCI_POWER_330;
1156                         break;
1157                 default:
1158                         BUG();
1159                 }
1160         }
1161
1162         if (host->pwr == pwr)
1163                 return;
1164
1165         host->pwr = pwr;
1166
1167         if (pwr == 0) {
1168                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1169                 return;
1170         }
1171
1172         /*
1173          * Spec says that we should clear the power reg before setting
1174          * a new value. Some controllers don't seem to like this though.
1175          */
1176         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1177                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1178
1179         /*
1180          * At least the Marvell CaFe chip gets confused if we set the voltage
1181          * and set turn on power at the same time, so set the voltage first.
1182          */
1183         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1184                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1185
1186         pwr |= SDHCI_POWER_ON;
1187
1188         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1189
1190         /*
1191          * Some controllers need an extra 10ms delay of 10ms before they
1192          * can apply clock after applying power
1193          */
1194         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1195                 mdelay(10);
1196 }
1197
1198 /*****************************************************************************\
1199  *                                                                           *
1200  * MMC callbacks                                                             *
1201  *                                                                           *
1202 \*****************************************************************************/
1203
1204 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1205 {
1206         struct sdhci_host *host;
1207         bool present;
1208         unsigned long flags;
1209
1210         host = mmc_priv(mmc);
1211
1212         spin_lock_irqsave(&host->lock, flags);
1213
1214         WARN_ON(host->mrq != NULL);
1215
1216 #ifndef SDHCI_USE_LEDS_CLASS
1217         sdhci_activate_led(host);
1218 #endif
1219
1220         /*
1221          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1222          * requests if Auto-CMD12 is enabled.
1223          */
1224         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1225                 if (mrq->stop) {
1226                         mrq->data->stop = NULL;
1227                         mrq->stop = NULL;
1228                 }
1229         }
1230
1231         host->mrq = mrq;
1232
1233         /* If polling, assume that the card is always present. */
1234         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1235                 present = true;
1236         else
1237                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1238                                 SDHCI_CARD_PRESENT;
1239
1240         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1241                 host->mrq->cmd->error = -ENOMEDIUM;
1242                 tasklet_schedule(&host->finish_tasklet);
1243         } else {
1244                 u32 present_state;
1245
1246                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1247                 /*
1248                  * Check if the re-tuning timer has already expired and there
1249                  * is no on-going data transfer. If so, we need to execute
1250                  * tuning procedure before sending command.
1251                  */
1252                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1253                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1254                         spin_unlock_irqrestore(&host->lock, flags);
1255                         sdhci_execute_tuning(mmc);
1256                         spin_lock_irqsave(&host->lock, flags);
1257
1258                         /* Restore original mmc_request structure */
1259                         host->mrq = mrq;
1260                 }
1261
1262                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1263                         sdhci_send_command(host, mrq->sbc);
1264                 else
1265                         sdhci_send_command(host, mrq->cmd);
1266         }
1267
1268         mmiowb();
1269         spin_unlock_irqrestore(&host->lock, flags);
1270 }
1271
1272 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1273 {
1274         struct sdhci_host *host;
1275         unsigned long flags;
1276         u8 ctrl;
1277
1278         host = mmc_priv(mmc);
1279
1280         spin_lock_irqsave(&host->lock, flags);
1281
1282         if (host->flags & SDHCI_DEVICE_DEAD)
1283                 goto out;
1284
1285         /*
1286          * Reset the chip on each power off.
1287          * Should clear out any weird states.
1288          */
1289         if (ios->power_mode == MMC_POWER_OFF) {
1290                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1291                 sdhci_reinit(host);
1292         }
1293
1294         sdhci_set_clock(host, ios->clock);
1295
1296         if (ios->power_mode == MMC_POWER_OFF)
1297                 sdhci_set_power(host, -1);
1298         else
1299                 sdhci_set_power(host, ios->vdd);
1300
1301         if (host->ops->platform_send_init_74_clocks)
1302                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1303
1304         /*
1305          * If your platform has 8-bit width support but is not a v3 controller,
1306          * or if it requires special setup code, you should implement that in
1307          * platform_8bit_width().
1308          */
1309         if (host->ops->platform_8bit_width)
1310                 host->ops->platform_8bit_width(host, ios->bus_width);
1311         else {
1312                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1313                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1314                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1315                         if (host->version >= SDHCI_SPEC_300)
1316                                 ctrl |= SDHCI_CTRL_8BITBUS;
1317                 } else {
1318                         if (host->version >= SDHCI_SPEC_300)
1319                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1320                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1321                                 ctrl |= SDHCI_CTRL_4BITBUS;
1322                         else
1323                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1324                 }
1325                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1326         }
1327
1328         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1329
1330         if ((ios->timing == MMC_TIMING_SD_HS ||
1331              ios->timing == MMC_TIMING_MMC_HS)
1332             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1333                 ctrl |= SDHCI_CTRL_HISPD;
1334         else
1335                 ctrl &= ~SDHCI_CTRL_HISPD;
1336
1337         if (host->version >= SDHCI_SPEC_300) {
1338                 u16 clk, ctrl_2;
1339                 unsigned int clock;
1340
1341                 /* In case of UHS-I modes, set High Speed Enable */
1342                 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1343                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1344                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1345                     (ios->timing == MMC_TIMING_UHS_SDR25) ||
1346                     (ios->timing == MMC_TIMING_UHS_SDR12))
1347                         ctrl |= SDHCI_CTRL_HISPD;
1348
1349                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1350                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1351                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1352                         /*
1353                          * We only need to set Driver Strength if the
1354                          * preset value enable is not set.
1355                          */
1356                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1357                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1358                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1359                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1360                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1361
1362                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1363                 } else {
1364                         /*
1365                          * According to SDHC Spec v3.00, if the Preset Value
1366                          * Enable in the Host Control 2 register is set, we
1367                          * need to reset SD Clock Enable before changing High
1368                          * Speed Enable to avoid generating clock gliches.
1369                          */
1370
1371                         /* Reset SD Clock Enable */
1372                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1373                         clk &= ~SDHCI_CLOCK_CARD_EN;
1374                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1375
1376                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1377
1378                         /* Re-enable SD Clock */
1379                         clock = host->clock;
1380                         host->clock = 0;
1381                         sdhci_set_clock(host, clock);
1382                 }
1383
1384
1385                 /* Reset SD Clock Enable */
1386                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1387                 clk &= ~SDHCI_CLOCK_CARD_EN;
1388                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1389
1390                 if (host->ops->set_uhs_signaling)
1391                         host->ops->set_uhs_signaling(host, ios->timing);
1392                 else {
1393                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1394                         /* Select Bus Speed Mode for host */
1395                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1396                         if (ios->timing == MMC_TIMING_UHS_SDR12)
1397                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1398                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1399                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1400                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1401                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1402                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1403                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1404                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1405                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1406                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1407                 }
1408
1409                 /* Re-enable SD Clock */
1410                 clock = host->clock;
1411                 host->clock = 0;
1412                 sdhci_set_clock(host, clock);
1413         } else
1414                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1415
1416         /*
1417          * Some (ENE) controllers go apeshit on some ios operation,
1418          * signalling timeout and CRC errors even on CMD0. Resetting
1419          * it on each ios seems to solve the problem.
1420          */
1421         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1422                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1423
1424 out:
1425         mmiowb();
1426         spin_unlock_irqrestore(&host->lock, flags);
1427 }
1428
1429 static int check_ro(struct sdhci_host *host)
1430 {
1431         unsigned long flags;
1432         int is_readonly;
1433
1434         spin_lock_irqsave(&host->lock, flags);
1435
1436         if (host->flags & SDHCI_DEVICE_DEAD)
1437                 is_readonly = 0;
1438         else if (host->ops->get_ro)
1439                 is_readonly = host->ops->get_ro(host);
1440         else
1441                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1442                                 & SDHCI_WRITE_PROTECT);
1443
1444         spin_unlock_irqrestore(&host->lock, flags);
1445
1446         /* This quirk needs to be replaced by a callback-function later */
1447         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1448                 !is_readonly : is_readonly;
1449 }
1450
1451 #define SAMPLE_COUNT    5
1452
1453 static int sdhci_get_ro(struct mmc_host *mmc)
1454 {
1455         struct sdhci_host *host;
1456         int i, ro_count;
1457
1458         host = mmc_priv(mmc);
1459
1460         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1461                 return check_ro(host);
1462
1463         ro_count = 0;
1464         for (i = 0; i < SAMPLE_COUNT; i++) {
1465                 if (check_ro(host)) {
1466                         if (++ro_count > SAMPLE_COUNT / 2)
1467                                 return 1;
1468                 }
1469                 msleep(30);
1470         }
1471         return 0;
1472 }
1473
1474 static void sdhci_hw_reset(struct mmc_host *mmc)
1475 {
1476         struct sdhci_host *host = mmc_priv(mmc);
1477
1478         if (host->ops && host->ops->hw_reset)
1479                 host->ops->hw_reset(host);
1480 }
1481
1482 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1483 {
1484         struct sdhci_host *host;
1485         unsigned long flags;
1486
1487         host = mmc_priv(mmc);
1488
1489         spin_lock_irqsave(&host->lock, flags);
1490
1491         if (host->flags & SDHCI_DEVICE_DEAD)
1492                 goto out;
1493
1494         if (enable)
1495                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1496         else
1497                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1498 out:
1499         mmiowb();
1500
1501         spin_unlock_irqrestore(&host->lock, flags);
1502 }
1503
1504 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1505         struct mmc_ios *ios)
1506 {
1507         struct sdhci_host *host;
1508         u8 pwr;
1509         u16 clk, ctrl;
1510         u32 present_state;
1511
1512         host = mmc_priv(mmc);
1513
1514         /*
1515          * Signal Voltage Switching is only applicable for Host Controllers
1516          * v3.00 and above.
1517          */
1518         if (host->version < SDHCI_SPEC_300)
1519                 return 0;
1520
1521         /*
1522          * We first check whether the request is to set signalling voltage
1523          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1524          */
1525         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1526         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1527                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1528                 ctrl &= ~SDHCI_CTRL_VDD_180;
1529                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1530
1531                 /* Wait for 5ms */
1532                 usleep_range(5000, 5500);
1533
1534                 /* 3.3V regulator output should be stable within 5 ms */
1535                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1536                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1537                         return 0;
1538                 else {
1539                         printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1540                                 "signalling voltage failed\n");
1541                         return -EIO;
1542                 }
1543         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1544                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1545                 /* Stop SDCLK */
1546                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1547                 clk &= ~SDHCI_CLOCK_CARD_EN;
1548                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1549
1550                 /* Check whether DAT[3:0] is 0000 */
1551                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1552                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1553                        SDHCI_DATA_LVL_SHIFT)) {
1554                         /*
1555                          * Enable 1.8V Signal Enable in the Host Control2
1556                          * register
1557                          */
1558                         ctrl |= SDHCI_CTRL_VDD_180;
1559                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1560
1561                         /* Wait for 5ms */
1562                         usleep_range(5000, 5500);
1563
1564                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1565                         if (ctrl & SDHCI_CTRL_VDD_180) {
1566                                 /* Provide SDCLK again and wait for 1ms*/
1567                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1568                                 clk |= SDHCI_CLOCK_CARD_EN;
1569                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1570                                 usleep_range(1000, 1500);
1571
1572                                 /*
1573                                  * If DAT[3:0] level is 1111b, then the card
1574                                  * was successfully switched to 1.8V signaling.
1575                                  */
1576                                 present_state = sdhci_readl(host,
1577                                                         SDHCI_PRESENT_STATE);
1578                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1579                                      SDHCI_DATA_LVL_MASK)
1580                                         return 0;
1581                         }
1582                 }
1583
1584                 /*
1585                  * If we are here, that means the switch to 1.8V signaling
1586                  * failed. We power cycle the card, and retry initialization
1587                  * sequence by setting S18R to 0.
1588                  */
1589                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1590                 pwr &= ~SDHCI_POWER_ON;
1591                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1592
1593                 /* Wait for 1ms as per the spec */
1594                 usleep_range(1000, 1500);
1595                 pwr |= SDHCI_POWER_ON;
1596                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1597
1598                 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1599                         "voltage failed, retrying with S18R set to 0\n");
1600                 return -EAGAIN;
1601         } else
1602                 /* No signal voltage switch required */
1603                 return 0;
1604 }
1605
1606 static int sdhci_execute_tuning(struct mmc_host *mmc)
1607 {
1608         struct sdhci_host *host;
1609         u16 ctrl;
1610         u32 ier;
1611         int tuning_loop_counter = MAX_TUNING_LOOP;
1612         unsigned long timeout;
1613         int err = 0;
1614
1615         host = mmc_priv(mmc);
1616
1617         disable_irq(host->irq);
1618         spin_lock(&host->lock);
1619
1620         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1621
1622         /*
1623          * Host Controller needs tuning only in case of SDR104 mode
1624          * and for SDR50 mode when Use Tuning for SDR50 is set in
1625          * Capabilities register.
1626          */
1627         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1628             (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1629             (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1630                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1631         else {
1632                 spin_unlock(&host->lock);
1633                 enable_irq(host->irq);
1634                 return 0;
1635         }
1636
1637         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1638
1639         /*
1640          * As per the Host Controller spec v3.00, tuning command
1641          * generates Buffer Read Ready interrupt, so enable that.
1642          *
1643          * Note: The spec clearly says that when tuning sequence
1644          * is being performed, the controller does not generate
1645          * interrupts other than Buffer Read Ready interrupt. But
1646          * to make sure we don't hit a controller bug, we _only_
1647          * enable Buffer Read Ready interrupt here.
1648          */
1649         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1650         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1651
1652         /*
1653          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1654          * of loops reaches 40 times or a timeout of 150ms occurs.
1655          */
1656         timeout = 150;
1657         do {
1658                 struct mmc_command cmd = {0};
1659                 struct mmc_request mrq = {0};
1660
1661                 if (!tuning_loop_counter && !timeout)
1662                         break;
1663
1664                 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1665                 cmd.arg = 0;
1666                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1667                 cmd.retries = 0;
1668                 cmd.data = NULL;
1669                 cmd.error = 0;
1670
1671                 mrq.cmd = &cmd;
1672                 host->mrq = &mrq;
1673
1674                 /*
1675                  * In response to CMD19, the card sends 64 bytes of tuning
1676                  * block to the Host Controller. So we set the block size
1677                  * to 64 here.
1678                  */
1679                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1680
1681                 /*
1682                  * The tuning block is sent by the card to the host controller.
1683                  * So we set the TRNS_READ bit in the Transfer Mode register.
1684                  * This also takes care of setting DMA Enable and Multi Block
1685                  * Select in the same register to 0.
1686                  */
1687                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1688
1689                 sdhci_send_command(host, &cmd);
1690
1691                 host->cmd = NULL;
1692                 host->mrq = NULL;
1693
1694                 spin_unlock(&host->lock);
1695                 enable_irq(host->irq);
1696
1697                 /* Wait for Buffer Read Ready interrupt */
1698                 wait_event_interruptible_timeout(host->buf_ready_int,
1699                                         (host->tuning_done == 1),
1700                                         msecs_to_jiffies(50));
1701                 disable_irq(host->irq);
1702                 spin_lock(&host->lock);
1703
1704                 if (!host->tuning_done) {
1705                         printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1706                                 "Buffer Read Ready interrupt during tuning "
1707                                 "procedure, falling back to fixed sampling "
1708                                 "clock\n");
1709                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1710                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1711                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1712                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1713
1714                         err = -EIO;
1715                         goto out;
1716                 }
1717
1718                 host->tuning_done = 0;
1719
1720                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1721                 tuning_loop_counter--;
1722                 timeout--;
1723                 mdelay(1);
1724         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1725
1726         /*
1727          * The Host Driver has exhausted the maximum number of loops allowed,
1728          * so use fixed sampling frequency.
1729          */
1730         if (!tuning_loop_counter || !timeout) {
1731                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1732                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1733         } else {
1734                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1735                         printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1736                                 " failed, falling back to fixed sampling"
1737                                 " clock\n");
1738                         err = -EIO;
1739                 }
1740         }
1741
1742 out:
1743         /*
1744          * If this is the very first time we are here, we start the retuning
1745          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1746          * flag won't be set, we check this condition before actually starting
1747          * the timer.
1748          */
1749         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1750             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1751                 mod_timer(&host->tuning_timer, jiffies +
1752                         host->tuning_count * HZ);
1753                 /* Tuning mode 1 limits the maximum data length to 4MB */
1754                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1755         } else {
1756                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1757                 /* Reload the new initial value for timer */
1758                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1759                         mod_timer(&host->tuning_timer, jiffies +
1760                                 host->tuning_count * HZ);
1761         }
1762
1763         /*
1764          * In case tuning fails, host controllers which support re-tuning can
1765          * try tuning again at a later time, when the re-tuning timer expires.
1766          * So for these controllers, we return 0. Since there might be other
1767          * controllers who do not have this capability, we return error for
1768          * them.
1769          */
1770         if (err && host->tuning_count &&
1771             host->tuning_mode == SDHCI_TUNING_MODE_1)
1772                 err = 0;
1773
1774         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1775         spin_unlock(&host->lock);
1776         enable_irq(host->irq);
1777
1778         return err;
1779 }
1780
1781 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1782 {
1783         struct sdhci_host *host;
1784         u16 ctrl;
1785         unsigned long flags;
1786
1787         host = mmc_priv(mmc);
1788
1789         /* Host Controller v3.00 defines preset value registers */
1790         if (host->version < SDHCI_SPEC_300)
1791                 return;
1792
1793         spin_lock_irqsave(&host->lock, flags);
1794
1795         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1796
1797         /*
1798          * We only enable or disable Preset Value if they are not already
1799          * enabled or disabled respectively. Otherwise, we bail out.
1800          */
1801         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1802                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1803                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1804         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1805                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1806                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1807         }
1808
1809         spin_unlock_irqrestore(&host->lock, flags);
1810 }
1811
1812 static const struct mmc_host_ops sdhci_ops = {
1813         .request        = sdhci_request,
1814         .set_ios        = sdhci_set_ios,
1815         .get_ro         = sdhci_get_ro,
1816         .hw_reset       = sdhci_hw_reset,
1817         .enable_sdio_irq = sdhci_enable_sdio_irq,
1818         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1819         .execute_tuning                 = sdhci_execute_tuning,
1820         .enable_preset_value            = sdhci_enable_preset_value,
1821 };
1822
1823 /*****************************************************************************\
1824  *                                                                           *
1825  * Tasklets                                                                  *
1826  *                                                                           *
1827 \*****************************************************************************/
1828
1829 static void sdhci_tasklet_card(unsigned long param)
1830 {
1831         struct sdhci_host *host;
1832         unsigned long flags;
1833
1834         host = (struct sdhci_host*)param;
1835
1836         spin_lock_irqsave(&host->lock, flags);
1837
1838         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1839                 if (host->mrq) {
1840                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1841                                 mmc_hostname(host->mmc));
1842                         printk(KERN_ERR "%s: Resetting controller.\n",
1843                                 mmc_hostname(host->mmc));
1844
1845                         sdhci_reset(host, SDHCI_RESET_CMD);
1846                         sdhci_reset(host, SDHCI_RESET_DATA);
1847
1848                         host->mrq->cmd->error = -ENOMEDIUM;
1849                         tasklet_schedule(&host->finish_tasklet);
1850                 }
1851         }
1852
1853         spin_unlock_irqrestore(&host->lock, flags);
1854
1855         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1856 }
1857
1858 static void sdhci_tasklet_finish(unsigned long param)
1859 {
1860         struct sdhci_host *host;
1861         unsigned long flags;
1862         struct mmc_request *mrq;
1863
1864         host = (struct sdhci_host*)param;
1865
1866         /*
1867          * If this tasklet gets rescheduled while running, it will
1868          * be run again afterwards but without any active request.
1869          */
1870         if (!host->mrq)
1871                 return;
1872
1873         spin_lock_irqsave(&host->lock, flags);
1874
1875         del_timer(&host->timer);
1876
1877         mrq = host->mrq;
1878
1879         /*
1880          * The controller needs a reset of internal state machines
1881          * upon error conditions.
1882          */
1883         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1884             ((mrq->cmd && mrq->cmd->error) ||
1885                  (mrq->data && (mrq->data->error ||
1886                   (mrq->data->stop && mrq->data->stop->error))) ||
1887                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1888
1889                 /* Some controllers need this kick or reset won't work here */
1890                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1891                         unsigned int clock;
1892
1893                         /* This is to force an update */
1894                         clock = host->clock;
1895                         host->clock = 0;
1896                         sdhci_set_clock(host, clock);
1897                 }
1898
1899                 /* Spec says we should do both at the same time, but Ricoh
1900                    controllers do not like that. */
1901                 sdhci_reset(host, SDHCI_RESET_CMD);
1902                 sdhci_reset(host, SDHCI_RESET_DATA);
1903         }
1904
1905         host->mrq = NULL;
1906         host->cmd = NULL;
1907         host->data = NULL;
1908
1909 #ifndef SDHCI_USE_LEDS_CLASS
1910         sdhci_deactivate_led(host);
1911 #endif
1912
1913         mmiowb();
1914         spin_unlock_irqrestore(&host->lock, flags);
1915
1916         mmc_request_done(host->mmc, mrq);
1917 }
1918
1919 static void sdhci_timeout_timer(unsigned long data)
1920 {
1921         struct sdhci_host *host;
1922         unsigned long flags;
1923
1924         host = (struct sdhci_host*)data;
1925
1926         spin_lock_irqsave(&host->lock, flags);
1927
1928         if (host->mrq) {
1929                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1930                         "interrupt.\n", mmc_hostname(host->mmc));
1931                 sdhci_dumpregs(host);
1932
1933                 if (host->data) {
1934                         host->data->error = -ETIMEDOUT;
1935                         sdhci_finish_data(host);
1936                 } else {
1937                         if (host->cmd)
1938                                 host->cmd->error = -ETIMEDOUT;
1939                         else
1940                                 host->mrq->cmd->error = -ETIMEDOUT;
1941
1942                         tasklet_schedule(&host->finish_tasklet);
1943                 }
1944         }
1945
1946         mmiowb();
1947         spin_unlock_irqrestore(&host->lock, flags);
1948 }
1949
1950 static void sdhci_tuning_timer(unsigned long data)
1951 {
1952         struct sdhci_host *host;
1953         unsigned long flags;
1954
1955         host = (struct sdhci_host *)data;
1956
1957         spin_lock_irqsave(&host->lock, flags);
1958
1959         host->flags |= SDHCI_NEEDS_RETUNING;
1960
1961         spin_unlock_irqrestore(&host->lock, flags);
1962 }
1963
1964 /*****************************************************************************\
1965  *                                                                           *
1966  * Interrupt handling                                                        *
1967  *                                                                           *
1968 \*****************************************************************************/
1969
1970 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1971 {
1972         BUG_ON(intmask == 0);
1973
1974         if (!host->cmd) {
1975                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1976                         "though no command operation was in progress.\n",
1977                         mmc_hostname(host->mmc), (unsigned)intmask);
1978                 sdhci_dumpregs(host);
1979                 return;
1980         }
1981
1982         if (intmask & SDHCI_INT_TIMEOUT)
1983                 host->cmd->error = -ETIMEDOUT;
1984         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1985                         SDHCI_INT_INDEX))
1986                 host->cmd->error = -EILSEQ;
1987
1988         if (host->cmd->error) {
1989                 tasklet_schedule(&host->finish_tasklet);
1990                 return;
1991         }
1992
1993         /*
1994          * The host can send and interrupt when the busy state has
1995          * ended, allowing us to wait without wasting CPU cycles.
1996          * Unfortunately this is overloaded on the "data complete"
1997          * interrupt, so we need to take some care when handling
1998          * it.
1999          *
2000          * Note: The 1.0 specification is a bit ambiguous about this
2001          *       feature so there might be some problems with older
2002          *       controllers.
2003          */
2004         if (host->cmd->flags & MMC_RSP_BUSY) {
2005                 if (host->cmd->data)
2006                         DBG("Cannot wait for busy signal when also "
2007                                 "doing a data transfer");
2008                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2009                         return;
2010
2011                 /* The controller does not support the end-of-busy IRQ,
2012                  * fall through and take the SDHCI_INT_RESPONSE */
2013         }
2014
2015         if (intmask & SDHCI_INT_RESPONSE)
2016                 sdhci_finish_command(host);
2017 }
2018
2019 #ifdef CONFIG_MMC_DEBUG
2020 static void sdhci_show_adma_error(struct sdhci_host *host)
2021 {
2022         const char *name = mmc_hostname(host->mmc);
2023         u8 *desc = host->adma_desc;
2024         __le32 *dma;
2025         __le16 *len;
2026         u8 attr;
2027
2028         sdhci_dumpregs(host);
2029
2030         while (true) {
2031                 dma = (__le32 *)(desc + 4);
2032                 len = (__le16 *)(desc + 2);
2033                 attr = *desc;
2034
2035                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2036                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2037
2038                 desc += 8;
2039
2040                 if (attr & 2)
2041                         break;
2042         }
2043 }
2044 #else
2045 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2046 #endif
2047
2048 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2049 {
2050         BUG_ON(intmask == 0);
2051
2052         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2053         if (intmask & SDHCI_INT_DATA_AVAIL) {
2054                 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2055                     MMC_SEND_TUNING_BLOCK) {
2056                         host->tuning_done = 1;
2057                         wake_up(&host->buf_ready_int);
2058                         return;
2059                 }
2060         }
2061
2062         if (!host->data) {
2063                 /*
2064                  * The "data complete" interrupt is also used to
2065                  * indicate that a busy state has ended. See comment
2066                  * above in sdhci_cmd_irq().
2067                  */
2068                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2069                         if (intmask & SDHCI_INT_DATA_END) {
2070                                 sdhci_finish_command(host);
2071                                 return;
2072                         }
2073                 }
2074
2075                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2076                         "though no data operation was in progress.\n",
2077                         mmc_hostname(host->mmc), (unsigned)intmask);
2078                 sdhci_dumpregs(host);
2079
2080                 return;
2081         }
2082
2083         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2084                 host->data->error = -ETIMEDOUT;
2085         else if (intmask & SDHCI_INT_DATA_END_BIT)
2086                 host->data->error = -EILSEQ;
2087         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2088                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2089                         != MMC_BUS_TEST_R)
2090                 host->data->error = -EILSEQ;
2091         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2092                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2093                 sdhci_show_adma_error(host);
2094                 host->data->error = -EIO;
2095         }
2096
2097         if (host->data->error)
2098                 sdhci_finish_data(host);
2099         else {
2100                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2101                         sdhci_transfer_pio(host);
2102
2103                 /*
2104                  * We currently don't do anything fancy with DMA
2105                  * boundaries, but as we can't disable the feature
2106                  * we need to at least restart the transfer.
2107                  *
2108                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2109                  * should return a valid address to continue from, but as
2110                  * some controllers are faulty, don't trust them.
2111                  */
2112                 if (intmask & SDHCI_INT_DMA_END) {
2113                         u32 dmastart, dmanow;
2114                         dmastart = sg_dma_address(host->data->sg);
2115                         dmanow = dmastart + host->data->bytes_xfered;
2116                         /*
2117                          * Force update to the next DMA block boundary.
2118                          */
2119                         dmanow = (dmanow &
2120                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2121                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2122                         host->data->bytes_xfered = dmanow - dmastart;
2123                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2124                                 " next 0x%08x\n",
2125                                 mmc_hostname(host->mmc), dmastart,
2126                                 host->data->bytes_xfered, dmanow);
2127                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2128                 }
2129
2130                 if (intmask & SDHCI_INT_DATA_END) {
2131                         if (host->cmd) {
2132                                 /*
2133                                  * Data managed to finish before the
2134                                  * command completed. Make sure we do
2135                                  * things in the proper order.
2136                                  */
2137                                 host->data_early = 1;
2138                         } else {
2139                                 sdhci_finish_data(host);
2140                         }
2141                 }
2142         }
2143 }
2144
2145 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2146 {
2147         irqreturn_t result;
2148         struct sdhci_host* host = dev_id;
2149         u32 intmask;
2150         int cardint = 0;
2151
2152         spin_lock(&host->lock);
2153
2154         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2155
2156         if (!intmask || intmask == 0xffffffff) {
2157                 result = IRQ_NONE;
2158                 goto out;
2159         }
2160
2161         DBG("*** %s got interrupt: 0x%08x\n",
2162                 mmc_hostname(host->mmc), intmask);
2163
2164         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2165                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2166                               SDHCI_CARD_PRESENT;
2167
2168                 /*
2169                  * There is a observation on i.mx esdhc.  INSERT bit will be
2170                  * immediately set again when it gets cleared, if a card is
2171                  * inserted.  We have to mask the irq to prevent interrupt
2172                  * storm which will freeze the system.  And the REMOVE gets
2173                  * the same situation.
2174                  *
2175                  * More testing are needed here to ensure it works for other
2176                  * platforms though.
2177                  */
2178                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2179                                                 SDHCI_INT_CARD_REMOVE);
2180                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2181                                                   SDHCI_INT_CARD_INSERT);
2182
2183                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2184                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2185                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2186                 tasklet_schedule(&host->card_tasklet);
2187         }
2188
2189         if (intmask & SDHCI_INT_CMD_MASK) {
2190                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2191                         SDHCI_INT_STATUS);
2192                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2193         }
2194
2195         if (intmask & SDHCI_INT_DATA_MASK) {
2196                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2197                         SDHCI_INT_STATUS);
2198                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2199         }
2200
2201         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2202
2203         intmask &= ~SDHCI_INT_ERROR;
2204
2205         if (intmask & SDHCI_INT_BUS_POWER) {
2206                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
2207                         mmc_hostname(host->mmc));
2208                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2209         }
2210
2211         intmask &= ~SDHCI_INT_BUS_POWER;
2212
2213         if (intmask & SDHCI_INT_CARD_INT)
2214                 cardint = 1;
2215
2216         intmask &= ~SDHCI_INT_CARD_INT;
2217
2218         if (intmask) {
2219                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
2220                         mmc_hostname(host->mmc), intmask);
2221                 sdhci_dumpregs(host);
2222
2223                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2224         }
2225
2226         result = IRQ_HANDLED;
2227
2228         mmiowb();
2229 out:
2230         spin_unlock(&host->lock);
2231
2232         /*
2233          * We have to delay this as it calls back into the driver.
2234          */
2235         if (cardint)
2236                 mmc_signal_sdio_irq(host->mmc);
2237
2238         return result;
2239 }
2240
2241 /*****************************************************************************\
2242  *                                                                           *
2243  * Suspend/resume                                                            *
2244  *                                                                           *
2245 \*****************************************************************************/
2246
2247 #ifdef CONFIG_PM
2248
2249 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
2250 {
2251         int ret;
2252
2253         sdhci_disable_card_detection(host);
2254
2255         /* Disable tuning since we are suspending */
2256         if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2257             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2258                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2259                 mod_timer(&host->tuning_timer, jiffies +
2260                         host->tuning_count * HZ);
2261         }
2262
2263         ret = mmc_suspend_host(host->mmc);
2264         if (ret)
2265                 return ret;
2266
2267         free_irq(host->irq, host);
2268
2269         if (host->vmmc)
2270                 ret = regulator_disable(host->vmmc);
2271
2272         return ret;
2273 }
2274
2275 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2276
2277 int sdhci_resume_host(struct sdhci_host *host)
2278 {
2279         int ret;
2280
2281         if (host->vmmc) {
2282                 int ret = regulator_enable(host->vmmc);
2283                 if (ret)
2284                         return ret;
2285         }
2286
2287
2288         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2289                 if (host->ops->enable_dma)
2290                         host->ops->enable_dma(host);
2291         }
2292
2293         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2294                           mmc_hostname(host->mmc), host);
2295         if (ret)
2296                 return ret;
2297
2298         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2299         mmiowb();
2300
2301         ret = mmc_resume_host(host->mmc);
2302         sdhci_enable_card_detection(host);
2303
2304         /* Set the re-tuning expiration flag */
2305         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2306             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2307                 host->flags |= SDHCI_NEEDS_RETUNING;
2308
2309         return ret;
2310 }
2311
2312 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2313
2314 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2315 {
2316         u8 val;
2317         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2318         val |= SDHCI_WAKE_ON_INT;
2319         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2320 }
2321
2322 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2323
2324 #endif /* CONFIG_PM */
2325
2326 /*****************************************************************************\
2327  *                                                                           *
2328  * Device allocation/registration                                            *
2329  *                                                                           *
2330 \*****************************************************************************/
2331
2332 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2333         size_t priv_size)
2334 {
2335         struct mmc_host *mmc;
2336         struct sdhci_host *host;
2337
2338         WARN_ON(dev == NULL);
2339
2340         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2341         if (!mmc)
2342                 return ERR_PTR(-ENOMEM);
2343
2344         host = mmc_priv(mmc);
2345         host->mmc = mmc;
2346
2347         return host;
2348 }
2349
2350 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2351
2352 int sdhci_add_host(struct sdhci_host *host)
2353 {
2354         struct mmc_host *mmc;
2355         u32 caps[2];
2356         u32 max_current_caps;
2357         unsigned int ocr_avail;
2358         int ret;
2359
2360         WARN_ON(host == NULL);
2361         if (host == NULL)
2362                 return -EINVAL;
2363
2364         mmc = host->mmc;
2365
2366         if (debug_quirks)
2367                 host->quirks = debug_quirks;
2368
2369         sdhci_reset(host, SDHCI_RESET_ALL);
2370
2371         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2372         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2373                                 >> SDHCI_SPEC_VER_SHIFT;
2374         if (host->version > SDHCI_SPEC_300) {
2375                 printk(KERN_ERR "%s: Unknown controller version (%d). "
2376                         "You may experience problems.\n", mmc_hostname(mmc),
2377                         host->version);
2378         }
2379
2380         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2381                 sdhci_readl(host, SDHCI_CAPABILITIES);
2382
2383         caps[1] = (host->version >= SDHCI_SPEC_300) ?
2384                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2385
2386         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2387                 host->flags |= SDHCI_USE_SDMA;
2388         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2389                 DBG("Controller doesn't have SDMA capability\n");
2390         else
2391                 host->flags |= SDHCI_USE_SDMA;
2392
2393         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2394                 (host->flags & SDHCI_USE_SDMA)) {
2395                 DBG("Disabling DMA as it is marked broken\n");
2396                 host->flags &= ~SDHCI_USE_SDMA;
2397         }
2398
2399         if ((host->version >= SDHCI_SPEC_200) &&
2400                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2401                 host->flags |= SDHCI_USE_ADMA;
2402
2403         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2404                 (host->flags & SDHCI_USE_ADMA)) {
2405                 DBG("Disabling ADMA as it is marked broken\n");
2406                 host->flags &= ~SDHCI_USE_ADMA;
2407         }
2408
2409         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2410                 if (host->ops->enable_dma) {
2411                         if (host->ops->enable_dma(host)) {
2412                                 printk(KERN_WARNING "%s: No suitable DMA "
2413                                         "available. Falling back to PIO.\n",
2414                                         mmc_hostname(mmc));
2415                                 host->flags &=
2416                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2417                         }
2418                 }
2419         }
2420
2421         if (host->flags & SDHCI_USE_ADMA) {
2422                 /*
2423                  * We need to allocate descriptors for all sg entries
2424                  * (128) and potentially one alignment transfer for
2425                  * each of those entries.
2426                  */
2427                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2428                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2429                 if (!host->adma_desc || !host->align_buffer) {
2430                         kfree(host->adma_desc);
2431                         kfree(host->align_buffer);
2432                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
2433                                 "buffers. Falling back to standard DMA.\n",
2434                                 mmc_hostname(mmc));
2435                         host->flags &= ~SDHCI_USE_ADMA;
2436                 }
2437         }
2438
2439         /*
2440          * If we use DMA, then it's up to the caller to set the DMA
2441          * mask, but PIO does not need the hw shim so we set a new
2442          * mask here in that case.
2443          */
2444         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2445                 host->dma_mask = DMA_BIT_MASK(64);
2446                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2447         }
2448
2449         if (host->version >= SDHCI_SPEC_300)
2450                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2451                         >> SDHCI_CLOCK_BASE_SHIFT;
2452         else
2453                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2454                         >> SDHCI_CLOCK_BASE_SHIFT;
2455
2456         host->max_clk *= 1000000;
2457         if (host->max_clk == 0 || host->quirks &
2458                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2459                 if (!host->ops->get_max_clock) {
2460                         printk(KERN_ERR
2461                                "%s: Hardware doesn't specify base clock "
2462                                "frequency.\n", mmc_hostname(mmc));
2463                         return -ENODEV;
2464                 }
2465                 host->max_clk = host->ops->get_max_clock(host);
2466         }
2467
2468         /*
2469          * In case of Host Controller v3.00, find out whether clock
2470          * multiplier is supported.
2471          */
2472         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2473                         SDHCI_CLOCK_MUL_SHIFT;
2474
2475         /*
2476          * In case the value in Clock Multiplier is 0, then programmable
2477          * clock mode is not supported, otherwise the actual clock
2478          * multiplier is one more than the value of Clock Multiplier
2479          * in the Capabilities Register.
2480          */
2481         if (host->clk_mul)
2482                 host->clk_mul += 1;
2483
2484         /*
2485          * Set host parameters.
2486          */
2487         mmc->ops = &sdhci_ops;
2488         mmc->f_max = host->max_clk;
2489         if (host->ops->get_min_clock)
2490                 mmc->f_min = host->ops->get_min_clock(host);
2491         else if (host->version >= SDHCI_SPEC_300) {
2492                 if (host->clk_mul) {
2493                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2494                         mmc->f_max = host->max_clk * host->clk_mul;
2495                 } else
2496                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2497         } else
2498                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2499
2500         host->timeout_clk =
2501                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2502         if (host->timeout_clk == 0) {
2503                 if (host->ops->get_timeout_clock) {
2504                         host->timeout_clk = host->ops->get_timeout_clock(host);
2505                 } else if (!(host->quirks &
2506                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2507                         printk(KERN_ERR
2508                                "%s: Hardware doesn't specify timeout clock "
2509                                "frequency.\n", mmc_hostname(mmc));
2510                         return -ENODEV;
2511                 }
2512         }
2513         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2514                 host->timeout_clk *= 1000;
2515
2516         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2517                 host->timeout_clk = mmc->f_max / 1000;
2518
2519         mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2520
2521         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2522
2523         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2524                 host->flags |= SDHCI_AUTO_CMD12;
2525
2526         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2527         if ((host->version >= SDHCI_SPEC_300) &&
2528             ((host->flags & SDHCI_USE_ADMA) ||
2529              !(host->flags & SDHCI_USE_SDMA))) {
2530                 host->flags |= SDHCI_AUTO_CMD23;
2531                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2532         } else {
2533                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2534         }
2535
2536         /*
2537          * A controller may support 8-bit width, but the board itself
2538          * might not have the pins brought out.  Boards that support
2539          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2540          * their platform code before calling sdhci_add_host(), and we
2541          * won't assume 8-bit width for hosts without that CAP.
2542          */
2543         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2544                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2545
2546         if (caps[0] & SDHCI_CAN_DO_HISPD)
2547                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2548
2549         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2550             mmc_card_is_removable(mmc))
2551                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2552
2553         /* UHS-I mode(s) supported by the host controller. */
2554         if (host->version >= SDHCI_SPEC_300)
2555                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2556
2557         /* SDR104 supports also implies SDR50 support */
2558         if (caps[1] & SDHCI_SUPPORT_SDR104)
2559                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2560         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2561                 mmc->caps |= MMC_CAP_UHS_SDR50;
2562
2563         if (caps[1] & SDHCI_SUPPORT_DDR50)
2564                 mmc->caps |= MMC_CAP_UHS_DDR50;
2565
2566         /* Does the host needs tuning for SDR50? */
2567         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2568                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2569
2570         /* Driver Type(s) (A, C, D) supported by the host */
2571         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2572                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2573         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2574                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2575         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2576                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2577
2578         /* Initial value for re-tuning timer count */
2579         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2580                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2581
2582         /*
2583          * In case Re-tuning Timer is not disabled, the actual value of
2584          * re-tuning timer will be 2 ^ (n - 1).
2585          */
2586         if (host->tuning_count)
2587                 host->tuning_count = 1 << (host->tuning_count - 1);
2588
2589         /* Re-tuning mode supported by the Host Controller */
2590         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2591                              SDHCI_RETUNING_MODE_SHIFT;
2592
2593         ocr_avail = 0;
2594         /*
2595          * According to SD Host Controller spec v3.00, if the Host System
2596          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2597          * the value is meaningful only if Voltage Support in the Capabilities
2598          * register is set. The actual current value is 4 times the register
2599          * value.
2600          */
2601         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2602
2603         if (caps[0] & SDHCI_CAN_VDD_330) {
2604                 int max_current_330;
2605
2606                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2607
2608                 max_current_330 = ((max_current_caps &
2609                                    SDHCI_MAX_CURRENT_330_MASK) >>
2610                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2611                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2612
2613                 if (max_current_330 > 150)
2614                         mmc->caps |= MMC_CAP_SET_XPC_330;
2615         }
2616         if (caps[0] & SDHCI_CAN_VDD_300) {
2617                 int max_current_300;
2618
2619                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2620
2621                 max_current_300 = ((max_current_caps &
2622                                    SDHCI_MAX_CURRENT_300_MASK) >>
2623                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2624                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2625
2626                 if (max_current_300 > 150)
2627                         mmc->caps |= MMC_CAP_SET_XPC_300;
2628         }
2629         if (caps[0] & SDHCI_CAN_VDD_180) {
2630                 int max_current_180;
2631
2632                 ocr_avail |= MMC_VDD_165_195;
2633
2634                 max_current_180 = ((max_current_caps &
2635                                    SDHCI_MAX_CURRENT_180_MASK) >>
2636                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2637                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2638
2639                 if (max_current_180 > 150)
2640                         mmc->caps |= MMC_CAP_SET_XPC_180;
2641
2642                 /* Maximum current capabilities of the host at 1.8V */
2643                 if (max_current_180 >= 800)
2644                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2645                 else if (max_current_180 >= 600)
2646                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2647                 else if (max_current_180 >= 400)
2648                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2649                 else
2650                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2651         }
2652
2653         mmc->ocr_avail = ocr_avail;
2654         mmc->ocr_avail_sdio = ocr_avail;
2655         if (host->ocr_avail_sdio)
2656                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2657         mmc->ocr_avail_sd = ocr_avail;
2658         if (host->ocr_avail_sd)
2659                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2660         else /* normal SD controllers don't support 1.8V */
2661                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2662         mmc->ocr_avail_mmc = ocr_avail;
2663         if (host->ocr_avail_mmc)
2664                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2665
2666         if (mmc->ocr_avail == 0) {
2667                 printk(KERN_ERR "%s: Hardware doesn't report any "
2668                         "support voltages.\n", mmc_hostname(mmc));
2669                 return -ENODEV;
2670         }
2671
2672         spin_lock_init(&host->lock);
2673
2674         /*
2675          * Maximum number of segments. Depends on if the hardware
2676          * can do scatter/gather or not.
2677          */
2678         if (host->flags & SDHCI_USE_ADMA)
2679                 mmc->max_segs = 128;
2680         else if (host->flags & SDHCI_USE_SDMA)
2681                 mmc->max_segs = 1;
2682         else /* PIO */
2683                 mmc->max_segs = 128;
2684
2685         /*
2686          * Maximum number of sectors in one transfer. Limited by DMA boundary
2687          * size (512KiB).
2688          */
2689         mmc->max_req_size = 524288;
2690
2691         /*
2692          * Maximum segment size. Could be one segment with the maximum number
2693          * of bytes. When doing hardware scatter/gather, each entry cannot
2694          * be larger than 64 KiB though.
2695          */
2696         if (host->flags & SDHCI_USE_ADMA) {
2697                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2698                         mmc->max_seg_size = 65535;
2699                 else
2700                         mmc->max_seg_size = 65536;
2701         } else {
2702                 mmc->max_seg_size = mmc->max_req_size;
2703         }
2704
2705         /*
2706          * Maximum block size. This varies from controller to controller and
2707          * is specified in the capabilities register.
2708          */
2709         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2710                 mmc->max_blk_size = 2;
2711         } else {
2712                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2713                                 SDHCI_MAX_BLOCK_SHIFT;
2714                 if (mmc->max_blk_size >= 3) {
2715                         printk(KERN_WARNING "%s: Invalid maximum block size, "
2716                                 "assuming 512 bytes\n", mmc_hostname(mmc));
2717                         mmc->max_blk_size = 0;
2718                 }
2719         }
2720
2721         mmc->max_blk_size = 512 << mmc->max_blk_size;
2722
2723         /*
2724          * Maximum block count.
2725          */
2726         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2727
2728         /*
2729          * Init tasklets.
2730          */
2731         tasklet_init(&host->card_tasklet,
2732                 sdhci_tasklet_card, (unsigned long)host);
2733         tasklet_init(&host->finish_tasklet,
2734                 sdhci_tasklet_finish, (unsigned long)host);
2735
2736         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2737
2738         if (host->version >= SDHCI_SPEC_300) {
2739                 init_waitqueue_head(&host->buf_ready_int);
2740
2741                 /* Initialize re-tuning timer */
2742                 init_timer(&host->tuning_timer);
2743                 host->tuning_timer.data = (unsigned long)host;
2744                 host->tuning_timer.function = sdhci_tuning_timer;
2745         }
2746
2747         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2748                 mmc_hostname(mmc), host);
2749         if (ret)
2750                 goto untasklet;
2751
2752         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2753         if (IS_ERR(host->vmmc)) {
2754                 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2755                 host->vmmc = NULL;
2756         } else {
2757                 regulator_enable(host->vmmc);
2758         }
2759
2760         sdhci_init(host, 0);
2761
2762 #ifdef CONFIG_MMC_DEBUG
2763         sdhci_dumpregs(host);
2764 #endif
2765
2766 #ifdef SDHCI_USE_LEDS_CLASS
2767         snprintf(host->led_name, sizeof(host->led_name),
2768                 "%s::", mmc_hostname(mmc));
2769         host->led.name = host->led_name;
2770         host->led.brightness = LED_OFF;
2771         host->led.default_trigger = mmc_hostname(mmc);
2772         host->led.brightness_set = sdhci_led_control;
2773
2774         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2775         if (ret)
2776                 goto reset;
2777 #endif
2778
2779         mmiowb();
2780
2781         mmc_add_host(mmc);
2782
2783         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2784                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2785                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2786                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2787
2788         sdhci_enable_card_detection(host);
2789
2790         return 0;
2791
2792 #ifdef SDHCI_USE_LEDS_CLASS
2793 reset:
2794         sdhci_reset(host, SDHCI_RESET_ALL);
2795         free_irq(host->irq, host);
2796 #endif
2797 untasklet:
2798         tasklet_kill(&host->card_tasklet);
2799         tasklet_kill(&host->finish_tasklet);
2800
2801         return ret;
2802 }
2803
2804 EXPORT_SYMBOL_GPL(sdhci_add_host);
2805
2806 void sdhci_remove_host(struct sdhci_host *host, int dead)
2807 {
2808         unsigned long flags;
2809
2810         if (dead) {
2811                 spin_lock_irqsave(&host->lock, flags);
2812
2813                 host->flags |= SDHCI_DEVICE_DEAD;
2814
2815                 if (host->mrq) {
2816                         printk(KERN_ERR "%s: Controller removed during "
2817                                 " transfer!\n", mmc_hostname(host->mmc));
2818
2819                         host->mrq->cmd->error = -ENOMEDIUM;
2820                         tasklet_schedule(&host->finish_tasklet);
2821                 }
2822
2823                 spin_unlock_irqrestore(&host->lock, flags);
2824         }
2825
2826         sdhci_disable_card_detection(host);
2827
2828         mmc_remove_host(host->mmc);
2829
2830 #ifdef SDHCI_USE_LEDS_CLASS
2831         led_classdev_unregister(&host->led);
2832 #endif
2833
2834         if (!dead)
2835                 sdhci_reset(host, SDHCI_RESET_ALL);
2836
2837         free_irq(host->irq, host);
2838
2839         del_timer_sync(&host->timer);
2840         if (host->version >= SDHCI_SPEC_300)
2841                 del_timer_sync(&host->tuning_timer);
2842
2843         tasklet_kill(&host->card_tasklet);
2844         tasklet_kill(&host->finish_tasklet);
2845
2846         if (host->vmmc) {
2847                 regulator_disable(host->vmmc);
2848                 regulator_put(host->vmmc);
2849         }
2850
2851         kfree(host->adma_desc);
2852         kfree(host->align_buffer);
2853
2854         host->adma_desc = NULL;
2855         host->align_buffer = NULL;
2856 }
2857
2858 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2859
2860 void sdhci_free_host(struct sdhci_host *host)
2861 {
2862         mmc_free_host(host->mmc);
2863 }
2864
2865 EXPORT_SYMBOL_GPL(sdhci_free_host);
2866
2867 /*****************************************************************************\
2868  *                                                                           *
2869  * Driver init/exit                                                          *
2870  *                                                                           *
2871 \*****************************************************************************/
2872
2873 static int __init sdhci_drv_init(void)
2874 {
2875         printk(KERN_INFO DRIVER_NAME
2876                 ": Secure Digital Host Controller Interface driver\n");
2877         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2878
2879         return 0;
2880 }
2881
2882 static void __exit sdhci_drv_exit(void)
2883 {
2884 }
2885
2886 module_init(sdhci_drv_init);
2887 module_exit(sdhci_drv_exit);
2888
2889 module_param(debug_quirks, uint, 0444);
2890
2891 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2892 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2893 MODULE_LICENSE("GPL");
2894
2895 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");