drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24
  25 #include <linux/leds.h>
  26
  27 #include <linux/mmc/mmc.h>
  28 #include <linux/mmc/host.h>
  29
  30 #include "sdhci.h"
  31
  32 #define DRIVER_NAME "sdhci"
  33
  34 #define DBG(f, x...) \
  35         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  36
  37 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  38         defined(CONFIG_MMC_SDHCI_MODULE))
  39 #define SDHCI_USE_LEDS_CLASS
  40 #endif
  41
  42 #define MAX_TUNING_LOOP 40
  43
  44 static unsigned int debug_quirks = 0;
  45
  46 static void sdhci_finish_data(struct sdhci_host *);
  47
  48 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  49 static void sdhci_finish_command(struct sdhci_host *);
  50 static int sdhci_execute_tuning(struct mmc_host *mmc);
  51 static void sdhci_tuning_timer(unsigned long data);
  52
  53 static void sdhci_dumpregs(struct sdhci_host *host)
  54 {
  55         printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  56                 mmc_hostname(host->mmc));
  57
  58         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  59                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  60                 sdhci_readw(host, SDHCI_HOST_VERSION));
  61         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  62                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  63                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  64         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  65                 sdhci_readl(host, SDHCI_ARGUMENT),
  66                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  67         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  68                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  69                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  70         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  71                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  72                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  73         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  74                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  75                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  76         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  77                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  78                 sdhci_readl(host, SDHCI_INT_STATUS));
  79         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  80                 sdhci_readl(host, SDHCI_INT_ENABLE),
  81                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  82         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  83                 sdhci_readw(host, SDHCI_ACMD12_ERR),
  84                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  85         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
  86                 sdhci_readl(host, SDHCI_CAPABILITIES),
  87                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
  88         printk(KERN_DEBUG DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
  89                 sdhci_readw(host, SDHCI_COMMAND),
  90                 sdhci_readl(host, SDHCI_MAX_CURRENT));
  91         printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
  92                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
  93
  94         if (host->flags & SDHCI_USE_ADMA)
  95                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
  96                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
  97                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
  98
  99         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
 100 }
 101
 102 /*****************************************************************************\
 103  *                                                                           *
 104  * Low level functions                                                       *
 105  *                                                                           *
 106 \*****************************************************************************/
 107
 108 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 109 {
 110         u32 ier;
 111
 112         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 113         ier &= ~clear;
 114         ier |= set;
 115         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 116         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 117 }
 118
 119 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 120 {
 121         sdhci_clear_set_irqs(host, 0, irqs);
 122 }
 123
 124 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 125 {
 126         sdhci_clear_set_irqs(host, irqs, 0);
 127 }
 128
 129 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 130 {
 131         u32 present, irqs;
 132
 133         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
 134                 return;
 135
 136         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 137                               SDHCI_CARD_PRESENT;
 138         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 139
 140         if (enable)
 141                 sdhci_unmask_irqs(host, irqs);
 142         else
 143                 sdhci_mask_irqs(host, irqs);
 144 }
 145
 146 static void sdhci_enable_card_detection(struct sdhci_host *host)
 147 {
 148         sdhci_set_card_detection(host, true);
 149 }
 150
 151 static void sdhci_disable_card_detection(struct sdhci_host *host)
 152 {
 153         sdhci_set_card_detection(host, false);
 154 }
 155
 156 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 157 {
 158         unsigned long timeout;
 159         u32 uninitialized_var(ier);
 160
 161         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 162                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 163                         SDHCI_CARD_PRESENT))
 164                         return;
 165         }
 166
 167         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 168                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 169
 170         if (host->ops->platform_reset_enter)
 171                 host->ops->platform_reset_enter(host, mask);
 172
 173         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 174
 175         if (mask & SDHCI_RESET_ALL)
 176                 host->clock = 0;
 177
 178         /* Wait max 100 ms */
 179         timeout = 100;
 180
 181         /* hw clears the bit when it's done */
 182         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 183                 if (timeout == 0) {
 184                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 185                                 mmc_hostname(host->mmc), (int)mask);
 186                         sdhci_dumpregs(host);
 187                         return;
 188                 }
 189                 timeout--;
 190                 mdelay(1);
 191         }
 192
 193         if (host->ops->platform_reset_exit)
 194                 host->ops->platform_reset_exit(host, mask);
 195
 196         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 197                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 198 }
 199
 200 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 201
 202 static void sdhci_init(struct sdhci_host *host, int soft)
 203 {
 204         if (soft)
 205                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 206         else
 207                 sdhci_reset(host, SDHCI_RESET_ALL);
 208
 209         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 210                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 211                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 212                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 213                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 214
 215         if (soft) {
 216                 /* force clock reconfiguration */
 217                 host->clock = 0;
 218                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 219         }
 220 }
 221
 222 static void sdhci_reinit(struct sdhci_host *host)
 223 {
 224         sdhci_init(host, 0);
 225         sdhci_enable_card_detection(host);
 226 }
 227
 228 static void sdhci_activate_led(struct sdhci_host *host)
 229 {
 230         u8 ctrl;
 231
 232         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 233         ctrl |= SDHCI_CTRL_LED;
 234         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 235 }
 236
 237 static void sdhci_deactivate_led(struct sdhci_host *host)
 238 {
 239         u8 ctrl;
 240
 241         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 242         ctrl &= ~SDHCI_CTRL_LED;
 243         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 244 }
 245
 246 #ifdef SDHCI_USE_LEDS_CLASS
 247 static void sdhci_led_control(struct led_classdev *led,
 248         enum led_brightness brightness)
 249 {
 250         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 251         unsigned long flags;
 252
 253         spin_lock_irqsave(&host->lock, flags);
 254
 255         if (brightness == LED_OFF)
 256                 sdhci_deactivate_led(host);
 257         else
 258                 sdhci_activate_led(host);
 259
 260         spin_unlock_irqrestore(&host->lock, flags);
 261 }
 262 #endif
 263
 264 /*****************************************************************************\
 265  *                                                                           *
 266  * Core functions                                                            *
 267  *                                                                           *
 268 \*****************************************************************************/
 269
 270 static void sdhci_read_block_pio(struct sdhci_host *host)
 271 {
 272         unsigned long flags;
 273         size_t blksize, len, chunk;
 274         u32 uninitialized_var(scratch);
 275         u8 *buf;
 276
 277         DBG("PIO reading\n");
 278
 279         blksize = host->data->blksz;
 280         chunk = 0;
 281
 282         local_irq_save(flags);
 283
 284         while (blksize) {
 285                 if (!sg_miter_next(&host->sg_miter))
 286                         BUG();
 287
 288                 len = min(host->sg_miter.length, blksize);
 289
 290                 blksize -= len;
 291                 host->sg_miter.consumed = len;
 292
 293                 buf = host->sg_miter.addr;
 294
 295                 while (len) {
 296                         if (chunk == 0) {
 297                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 298                                 chunk = 4;
 299                         }
 300
 301                         *buf = scratch & 0xFF;
 302
 303                         buf++;
 304                         scratch >>= 8;
 305                         chunk--;
 306                         len--;
 307                 }
 308         }
 309
 310         sg_miter_stop(&host->sg_miter);
 311
 312         local_irq_restore(flags);
 313 }
 314
 315 static void sdhci_write_block_pio(struct sdhci_host *host)
 316 {
 317         unsigned long flags;
 318         size_t blksize, len, chunk;
 319         u32 scratch;
 320         u8 *buf;
 321
 322         DBG("PIO writing\n");
 323
 324         blksize = host->data->blksz;
 325         chunk = 0;
 326         scratch = 0;
 327
 328         local_irq_save(flags);
 329
 330         while (blksize) {
 331                 if (!sg_miter_next(&host->sg_miter))
 332                         BUG();
 333
 334                 len = min(host->sg_miter.length, blksize);
 335
 336                 blksize -= len;
 337                 host->sg_miter.consumed = len;
 338
 339                 buf = host->sg_miter.addr;
 340
 341                 while (len) {
 342                         scratch |= (u32)*buf << (chunk * 8);
 343
 344                         buf++;
 345                         chunk++;
 346                         len--;
 347
 348                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 349                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 350                                 chunk = 0;
 351                                 scratch = 0;
 352                         }
 353                 }
 354         }
 355
 356         sg_miter_stop(&host->sg_miter);
 357
 358         local_irq_restore(flags);
 359 }
 360
 361 static void sdhci_transfer_pio(struct sdhci_host *host)
 362 {
 363         u32 mask;
 364
 365         BUG_ON(!host->data);
 366
 367         if (host->blocks == 0)
 368                 return;
 369
 370         if (host->data->flags & MMC_DATA_READ)
 371                 mask = SDHCI_DATA_AVAILABLE;
 372         else
 373                 mask = SDHCI_SPACE_AVAILABLE;
 374
 375         /*
 376          * Some controllers (JMicron JMB38x) mess up the buffer bits
 377          * for transfers < 4 bytes. As long as it is just one block,
 378          * we can ignore the bits.
 379          */
 380         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 381                 (host->data->blocks == 1))
 382                 mask = ~0;
 383
 384         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 385                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 386                         udelay(100);
 387
 388                 if (host->data->flags & MMC_DATA_READ)
 389                         sdhci_read_block_pio(host);
 390                 else
 391                         sdhci_write_block_pio(host);
 392
 393                 host->blocks--;
 394                 if (host->blocks == 0)
 395                         break;
 396         }
 397
 398         DBG("PIO transfer complete.\n");
 399 }
 400
 401 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 402 {
 403         local_irq_save(*flags);
 404         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 405 }
 406
 407 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 408 {
 409         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 410         local_irq_restore(*flags);
 411 }
 412
 413 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 414 {
 415         __le32 *dataddr = (__le32 __force *)(desc + 4);
 416         __le16 *cmdlen = (__le16 __force *)desc;
 417
 418         /* SDHCI specification says ADMA descriptors should be 4 byte
 419          * aligned, so using 16 or 32bit operations should be safe. */
 420
 421         cmdlen[0] = cpu_to_le16(cmd);
 422         cmdlen[1] = cpu_to_le16(len);
 423
 424         dataddr[0] = cpu_to_le32(addr);
 425 }
 426
 427 static int sdhci_adma_table_pre(struct sdhci_host *host,
 428         struct mmc_data *data)
 429 {
 430         int direction;
 431
 432         u8 *desc;
 433         u8 *align;
 434         dma_addr_t addr;
 435         dma_addr_t align_addr;
 436         int len, offset;
 437
 438         struct scatterlist *sg;
 439         int i;
 440         char *buffer;
 441         unsigned long flags;
 442
 443         /*
 444          * The spec does not specify endianness of descriptor table.
 445          * We currently guess that it is LE.
 446          */
 447
 448         if (data->flags & MMC_DATA_READ)
 449                 direction = DMA_FROM_DEVICE;
 450         else
 451                 direction = DMA_TO_DEVICE;
 452
 453         /*
 454          * The ADMA descriptor table is mapped further down as we
 455          * need to fill it with data first.
 456          */
 457
 458         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 459                 host->align_buffer, 128 * 4, direction);
 460         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 461                 goto fail;
 462         BUG_ON(host->align_addr & 0x3);
 463
 464         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 465                 data->sg, data->sg_len, direction);
 466         if (host->sg_count == 0)
 467                 goto unmap_align;
 468
 469         desc = host->adma_desc;
 470         align = host->align_buffer;
 471
 472         align_addr = host->align_addr;
 473
 474         for_each_sg(data->sg, sg, host->sg_count, i) {
 475                 addr = sg_dma_address(sg);
 476                 len = sg_dma_len(sg);
 477
 478                 /*
 479                  * The SDHCI specification states that ADMA
 480                  * addresses must be 32-bit aligned. If they
 481                  * aren't, then we use a bounce buffer for
 482                  * the (up to three) bytes that screw up the
 483                  * alignment.
 484                  */
 485                 offset = (4 - (addr & 0x3)) & 0x3;
 486                 if (offset) {
 487                         if (data->flags & MMC_DATA_WRITE) {
 488                                 buffer = sdhci_kmap_atomic(sg, &flags);
 489                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 490                                 memcpy(align, buffer, offset);
 491                                 sdhci_kunmap_atomic(buffer, &flags);
 492                         }
 493
 494                         /* tran, valid */
 495                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 496
 497                         BUG_ON(offset > 65536);
 498
 499                         align += 4;
 500                         align_addr += 4;
 501
 502                         desc += 8;
 503
 504                         addr += offset;
 505                         len -= offset;
 506                 }
 507
 508                 BUG_ON(len > 65536);
 509
 510                 /* tran, valid */
 511                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 512                 desc += 8;
 513
 514                 /*
 515                  * If this triggers then we have a calculation bug
 516                  * somewhere. :/
 517                  */
 518                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 519         }
 520
 521         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 522                 /*
 523                 * Mark the last descriptor as the terminating descriptor
 524                 */
 525                 if (desc != host->adma_desc) {
 526                         desc -= 8;
 527                         desc[0] |= 0x2; /* end */
 528                 }
 529         } else {
 530                 /*
 531                 * Add a terminating entry.
 532                 */
 533
 534                 /* nop, end, valid */
 535                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 536         }
 537
 538         /*
 539          * Resync align buffer as we might have changed it.
 540          */
 541         if (data->flags & MMC_DATA_WRITE) {
 542                 dma_sync_single_for_device(mmc_dev(host->mmc),
 543                         host->align_addr, 128 * 4, direction);
 544         }
 545
 546         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 547                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 548         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 549                 goto unmap_entries;
 550         BUG_ON(host->adma_addr & 0x3);
 551
 552         return 0;
 553
 554 unmap_entries:
 555         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 556                 data->sg_len, direction);
 557 unmap_align:
 558         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 559                 128 * 4, direction);
 560 fail:
 561         return -EINVAL;
 562 }
 563
 564 static void sdhci_adma_table_post(struct sdhci_host *host,
 565         struct mmc_data *data)
 566 {
 567         int direction;
 568
 569         struct scatterlist *sg;
 570         int i, size;
 571         u8 *align;
 572         char *buffer;
 573         unsigned long flags;
 574
 575         if (data->flags & MMC_DATA_READ)
 576                 direction = DMA_FROM_DEVICE;
 577         else
 578                 direction = DMA_TO_DEVICE;
 579
 580         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 581                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 582
 583         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 584                 128 * 4, direction);
 585
 586         if (data->flags & MMC_DATA_READ) {
 587                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 588                         data->sg_len, direction);
 589
 590                 align = host->align_buffer;
 591
 592                 for_each_sg(data->sg, sg, host->sg_count, i) {
 593                         if (sg_dma_address(sg) & 0x3) {
 594                                 size = 4 - (sg_dma_address(sg) & 0x3);
 595
 596                                 buffer = sdhci_kmap_atomic(sg, &flags);
 597                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 598                                 memcpy(buffer, align, size);
 599                                 sdhci_kunmap_atomic(buffer, &flags);
 600
 601                                 align += 4;
 602                         }
 603                 }
 604         }
 605
 606         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 607                 data->sg_len, direction);
 608 }
 609
 610 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 611 {
 612         u8 count;
 613         struct mmc_data *data = cmd->data;
 614         unsigned target_timeout, current_timeout;
 615
 616         /*
 617          * If the host controller provides us with an incorrect timeout
 618          * value, just skip the check and use 0xE.  The hardware may take
 619          * longer to time out, but that's much better than having a too-short
 620          * timeout value.
 621          */
 622         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 623                 return 0xE;
 624
 625         /* Unspecified timeout, assume max */
 626         if (!data && !cmd->cmd_timeout_ms)
 627                 return 0xE;
 628
 629         /* timeout in us */
 630         if (!data)
 631                 target_timeout = cmd->cmd_timeout_ms * 1000;
 632         else {
 633                 target_timeout = data->timeout_ns / 1000;
 634                 if (host->clock)
 635                         target_timeout += data->timeout_clks / host->clock;
 636         }
 637
 638         /*
 639          * Figure out needed cycles.
 640          * We do this in steps in order to fit inside a 32 bit int.
 641          * The first step is the minimum timeout, which will have a
 642          * minimum resolution of 6 bits:
 643          * (1) 2^13*1000 > 2^22,
 644          * (2) host->timeout_clk < 2^16
 645          *     =>
 646          *     (1) / (2) > 2^6
 647          */
 648         count = 0;
 649         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 650         while (current_timeout < target_timeout) {
 651                 count++;
 652                 current_timeout <<= 1;
 653                 if (count >= 0xF)
 654                         break;
 655         }
 656
 657         if (count >= 0xF) {
 658                 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
 659                        mmc_hostname(host->mmc), cmd->opcode);
 660                 count = 0xE;
 661         }
 662
 663         return count;
 664 }
 665
 666 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 667 {
 668         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 669         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 670
 671         if (host->flags & SDHCI_REQ_USE_DMA)
 672                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 673         else
 674                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 675 }
 676
 677 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 678 {
 679         u8 count;
 680         u8 ctrl;
 681         struct mmc_data *data = cmd->data;
 682         int ret;
 683
 684         WARN_ON(host->data);
 685
 686         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 687                 count = sdhci_calc_timeout(host, cmd);
 688                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 689         }
 690
 691         if (!data)
 692                 return;
 693
 694         /* Sanity checks */
 695         BUG_ON(data->blksz * data->blocks > 524288);
 696         BUG_ON(data->blksz > host->mmc->max_blk_size);
 697         BUG_ON(data->blocks > 65535);
 698
 699         host->data = data;
 700         host->data_early = 0;
 701         host->data->bytes_xfered = 0;
 702
 703         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 704                 host->flags |= SDHCI_REQ_USE_DMA;
 705
 706         /*
 707          * FIXME: This doesn't account for merging when mapping the
 708          * scatterlist.
 709          */
 710         if (host->flags & SDHCI_REQ_USE_DMA) {
 711                 int broken, i;
 712                 struct scatterlist *sg;
 713
 714                 broken = 0;
 715                 if (host->flags & SDHCI_USE_ADMA) {
 716                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 717                                 broken = 1;
 718                 } else {
 719                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 720                                 broken = 1;
 721                 }
 722
 723                 if (unlikely(broken)) {
 724                         for_each_sg(data->sg, sg, data->sg_len, i) {
 725                                 if (sg->length & 0x3) {
 726                                         DBG("Reverting to PIO because of "
 727                                                 "transfer size (%d)\n",
 728                                                 sg->length);
 729                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 730                                         break;
 731                                 }
 732                         }
 733                 }
 734         }
 735
 736         /*
 737          * The assumption here being that alignment is the same after
 738          * translation to device address space.
 739          */
 740         if (host->flags & SDHCI_REQ_USE_DMA) {
 741                 int broken, i;
 742                 struct scatterlist *sg;
 743
 744                 broken = 0;
 745                 if (host->flags & SDHCI_USE_ADMA) {
 746                         /*
 747                          * As we use 3 byte chunks to work around
 748                          * alignment problems, we need to check this
 749                          * quirk.
 750                          */
 751                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 752                                 broken = 1;
 753                 } else {
 754                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 755                                 broken = 1;
 756                 }
 757
 758                 if (unlikely(broken)) {
 759                         for_each_sg(data->sg, sg, data->sg_len, i) {
 760                                 if (sg->offset & 0x3) {
 761                                         DBG("Reverting to PIO because of "
 762                                                 "bad alignment\n");
 763                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 764                                         break;
 765                                 }
 766                         }
 767                 }
 768         }
 769
 770         if (host->flags & SDHCI_REQ_USE_DMA) {
 771                 if (host->flags & SDHCI_USE_ADMA) {
 772                         ret = sdhci_adma_table_pre(host, data);
 773                         if (ret) {
 774                                 /*
 775                                  * This only happens when someone fed
 776                                  * us an invalid request.
 777                                  */
 778                                 WARN_ON(1);
 779                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 780                         } else {
 781                                 sdhci_writel(host, host->adma_addr,
 782                                         SDHCI_ADMA_ADDRESS);
 783                         }
 784                 } else {
 785                         int sg_cnt;
 786
 787                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 788                                         data->sg, data->sg_len,
 789                                         (data->flags & MMC_DATA_READ) ?
 790                                                 DMA_FROM_DEVICE :
 791                                                 DMA_TO_DEVICE);
 792                         if (sg_cnt == 0) {
 793                                 /*
 794                                  * This only happens when someone fed
 795                                  * us an invalid request.
 796                                  */
 797                                 WARN_ON(1);
 798                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 799                         } else {
 800                                 WARN_ON(sg_cnt != 1);
 801                                 sdhci_writel(host, sg_dma_address(data->sg),
 802                                         SDHCI_DMA_ADDRESS);
 803                         }
 804                 }
 805         }
 806
 807         /*
 808          * Always adjust the DMA selection as some controllers
 809          * (e.g. JMicron) can't do PIO properly when the selection
 810          * is ADMA.
 811          */
 812         if (host->version >= SDHCI_SPEC_200) {
 813                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 814                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 815                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 816                         (host->flags & SDHCI_USE_ADMA))
 817                         ctrl |= SDHCI_CTRL_ADMA32;
 818                 else
 819                         ctrl |= SDHCI_CTRL_SDMA;
 820                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 821         }
 822
 823         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 824                 int flags;
 825
 826                 flags = SG_MITER_ATOMIC;
 827                 if (host->data->flags & MMC_DATA_READ)
 828                         flags |= SG_MITER_TO_SG;
 829                 else
 830                         flags |= SG_MITER_FROM_SG;
 831                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 832                 host->blocks = data->blocks;
 833         }
 834
 835         sdhci_set_transfer_irqs(host);
 836
 837         /* Set the DMA boundary value and block size */
 838         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 839                 data->blksz), SDHCI_BLOCK_SIZE);
 840         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 841 }
 842
 843 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 844         struct mmc_command *cmd)
 845 {
 846         u16 mode;
 847         struct mmc_data *data = cmd->data;
 848
 849         if (data == NULL)
 850                 return;
 851
 852         WARN_ON(!host->data);
 853
 854         mode = SDHCI_TRNS_BLK_CNT_EN;
 855         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 856                 mode |= SDHCI_TRNS_MULTI;
 857                 /*
 858                  * If we are sending CMD23, CMD12 never gets sent
 859                  * on successful completion (so no Auto-CMD12).
 860                  */
 861                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 862                         mode |= SDHCI_TRNS_AUTO_CMD12;
 863                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 864                         mode |= SDHCI_TRNS_AUTO_CMD23;
 865                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 866                 }
 867         }
 868
 869         if (data->flags & MMC_DATA_READ)
 870                 mode |= SDHCI_TRNS_READ;
 871         if (host->flags & SDHCI_REQ_USE_DMA)
 872                 mode |= SDHCI_TRNS_DMA;
 873
 874         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 875 }
 876
 877 static void sdhci_finish_data(struct sdhci_host *host)
 878 {
 879         struct mmc_data *data;
 880
 881         BUG_ON(!host->data);
 882
 883         data = host->data;
 884         host->data = NULL;
 885
 886         if (host->flags & SDHCI_REQ_USE_DMA) {
 887                 if (host->flags & SDHCI_USE_ADMA)
 888                         sdhci_adma_table_post(host, data);
 889                 else {
 890                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 891                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 892                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 893                 }
 894         }
 895
 896         /*
 897          * The specification states that the block count register must
 898          * be updated, but it does not specify at what point in the
 899          * data flow. That makes the register entirely useless to read
 900          * back so we have to assume that nothing made it to the card
 901          * in the event of an error.
 902          */
 903         if (data->error)
 904                 data->bytes_xfered = 0;
 905         else
 906                 data->bytes_xfered = data->blksz * data->blocks;
 907
 908         /*
 909          * Need to send CMD12 if -
 910          * a) open-ended multiblock transfer (no CMD23)
 911          * b) error in multiblock transfer
 912          */
 913         if (data->stop &&
 914             (data->error ||
 915              !host->mrq->sbc)) {
 916
 917                 /*
 918                  * The controller needs a reset of internal state machines
 919                  * upon error conditions.
 920                  */
 921                 if (data->error) {
 922                         sdhci_reset(host, SDHCI_RESET_CMD);
 923                         sdhci_reset(host, SDHCI_RESET_DATA);
 924                 }
 925
 926                 sdhci_send_command(host, data->stop);
 927         } else
 928                 tasklet_schedule(&host->finish_tasklet);
 929 }
 930
 931 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 932 {
 933         int flags;
 934         u32 mask;
 935         unsigned long timeout;
 936
 937         WARN_ON(host->cmd);
 938
 939         /* Wait max 10 ms */
 940         timeout = 10;
 941
 942         mask = SDHCI_CMD_INHIBIT;
 943         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 944                 mask |= SDHCI_DATA_INHIBIT;
 945
 946         /* We shouldn't wait for data inihibit for stop commands, even
 947            though they might use busy signaling */
 948         if (host->mrq->data && (cmd == host->mrq->data->stop))
 949                 mask &= ~SDHCI_DATA_INHIBIT;
 950
 951         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 952                 if (timeout == 0) {
 953                         printk(KERN_ERR "%s: Controller never released "
 954                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 955                         sdhci_dumpregs(host);
 956                         cmd->error = -EIO;
 957                         tasklet_schedule(&host->finish_tasklet);
 958                         return;
 959                 }
 960                 timeout--;
 961                 mdelay(1);
 962         }
 963
 964         mod_timer(&host->timer, jiffies + 10 * HZ);
 965
 966         host->cmd = cmd;
 967
 968         sdhci_prepare_data(host, cmd);
 969
 970         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 971
 972         sdhci_set_transfer_mode(host, cmd);
 973
 974         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 975                 printk(KERN_ERR "%s: Unsupported response type!\n",
 976                         mmc_hostname(host->mmc));
 977                 cmd->error = -EINVAL;
 978                 tasklet_schedule(&host->finish_tasklet);
 979                 return;
 980         }
 981
 982         if (!(cmd->flags & MMC_RSP_PRESENT))
 983                 flags = SDHCI_CMD_RESP_NONE;
 984         else if (cmd->flags & MMC_RSP_136)
 985                 flags = SDHCI_CMD_RESP_LONG;
 986         else if (cmd->flags & MMC_RSP_BUSY)
 987                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 988         else
 989                 flags = SDHCI_CMD_RESP_SHORT;
 990
 991         if (cmd->flags & MMC_RSP_CRC)
 992                 flags |= SDHCI_CMD_CRC;
 993         if (cmd->flags & MMC_RSP_OPCODE)
 994                 flags |= SDHCI_CMD_INDEX;
 995
 996         /* CMD19 is special in that the Data Present Select should be set */
 997         if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
 998                 flags |= SDHCI_CMD_DATA;
 999
1000         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1001 }
1002
1003 static void sdhci_finish_command(struct sdhci_host *host)
1004 {
1005         int i;
1006
1007         BUG_ON(host->cmd == NULL);
1008
1009         if (host->cmd->flags & MMC_RSP_PRESENT) {
1010                 if (host->cmd->flags & MMC_RSP_136) {
1011                         /* CRC is stripped so we need to do some shifting. */
1012                         for (i = 0;i < 4;i++) {
1013                                 host->cmd->resp[i] = sdhci_readl(host,
1014                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1015                                 if (i != 3)
1016                                         host->cmd->resp[i] |=
1017                                                 sdhci_readb(host,
1018                                                 SDHCI_RESPONSE + (3-i)*4-1);
1019                         }
1020                 } else {
1021                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1022                 }
1023         }
1024
1025         host->cmd->error = 0;
1026
1027         /* Finished CMD23, now send actual command. */
1028         if (host->cmd == host->mrq->sbc) {
1029                 host->cmd = NULL;
1030                 sdhci_send_command(host, host->mrq->cmd);
1031         } else {
1032
1033                 /* Processed actual command. */
1034                 if (host->data && host->data_early)
1035                         sdhci_finish_data(host);
1036
1037                 if (!host->cmd->data)
1038                         tasklet_schedule(&host->finish_tasklet);
1039
1040                 host->cmd = NULL;
1041         }
1042 }
1043
1044 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1045 {
1046         int div = 0; /* Initialized for compiler warning */
1047         u16 clk = 0;
1048         unsigned long timeout;
1049
1050         if (clock == host->clock)
1051                 return;
1052
1053         if (host->ops->set_clock) {
1054                 host->ops->set_clock(host, clock);
1055                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1056                         return;
1057         }
1058
1059         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1060
1061         if (clock == 0)
1062                 goto out;
1063
1064         if (host->version >= SDHCI_SPEC_300) {
1065                 /*
1066                  * Check if the Host Controller supports Programmable Clock
1067                  * Mode.
1068                  */
1069                 if (host->clk_mul) {
1070                         u16 ctrl;
1071
1072                         /*
1073                          * We need to figure out whether the Host Driver needs
1074                          * to select Programmable Clock Mode, or the value can
1075                          * be set automatically by the Host Controller based on
1076                          * the Preset Value registers.
1077                          */
1078                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1079                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1080                                 for (div = 1; div <= 1024; div++) {
1081                                         if (((host->max_clk * host->clk_mul) /
1082                                               div) <= clock)
1083                                                 break;
1084                                 }
1085                                 /*
1086                                  * Set Programmable Clock Mode in the Clock
1087                                  * Control register.
1088                                  */
1089                                 clk = SDHCI_PROG_CLOCK_MODE;
1090                                 div--;
1091                         }
1092                 } else {
1093                         /* Version 3.00 divisors must be a multiple of 2. */
1094                         if (host->max_clk <= clock)
1095                                 div = 1;
1096                         else {
1097                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1098                                      div += 2) {
1099                                         if ((host->max_clk / div) <= clock)
1100                                                 break;
1101                                 }
1102                         }
1103                         div >>= 1;
1104                 }
1105         } else {
1106                 /* Version 2.00 divisors must be a power of 2. */
1107                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1108                         if ((host->max_clk / div) <= clock)
1109                                 break;
1110                 }
1111                 div >>= 1;
1112         }
1113
1114         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1115         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1116                 << SDHCI_DIVIDER_HI_SHIFT;
1117         clk |= SDHCI_CLOCK_INT_EN;
1118         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1119
1120         /* Wait max 20 ms */
1121         timeout = 20;
1122         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1123                 & SDHCI_CLOCK_INT_STABLE)) {
1124                 if (timeout == 0) {
1125                         printk(KERN_ERR "%s: Internal clock never "
1126                                 "stabilised.\n", mmc_hostname(host->mmc));
1127                         sdhci_dumpregs(host);
1128                         return;
1129                 }
1130                 timeout--;
1131                 mdelay(1);
1132         }
1133
1134         clk |= SDHCI_CLOCK_CARD_EN;
1135         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1136
1137 out:
1138         host->clock = clock;
1139 }
1140
1141 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1142 {
1143         u8 pwr = 0;
1144
1145         if (power != (unsigned short)-1) {
1146                 switch (1 << power) {
1147                 case MMC_VDD_165_195:
1148                         pwr = SDHCI_POWER_180;
1149                         break;
1150                 case MMC_VDD_29_30:
1151                 case MMC_VDD_30_31:
1152                         pwr = SDHCI_POWER_300;
1153                         break;
1154                 case MMC_VDD_32_33:
1155                 case MMC_VDD_33_34:
1156                         pwr = SDHCI_POWER_330;
1157                         break;
1158                 default:
1159                         BUG();
1160                 }
1161         }
1162
1163         if (host->pwr == pwr)
1164                 return;
1165
1166         host->pwr = pwr;
1167
1168         if (pwr == 0) {
1169                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1170                 return;
1171         }
1172
1173         /*
1174          * Spec says that we should clear the power reg before setting
1175          * a new value. Some controllers don't seem to like this though.
1176          */
1177         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1178                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1179
1180         /*
1181          * At least the Marvell CaFe chip gets confused if we set the voltage
1182          * and set turn on power at the same time, so set the voltage first.
1183          */
1184         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1185                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1186
1187         pwr |= SDHCI_POWER_ON;
1188
1189         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1190
1191         /*
1192          * Some controllers need an extra 10ms delay of 10ms before they
1193          * can apply clock after applying power
1194          */
1195         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1196                 mdelay(10);
1197 }
1198
1199 /*****************************************************************************\
1200  *                                                                           *
1201  * MMC callbacks                                                             *
1202  *                                                                           *
1203 \*****************************************************************************/
1204
1205 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1206 {
1207         struct sdhci_host *host;
1208         bool present;
1209         unsigned long flags;
1210
1211         host = mmc_priv(mmc);
1212
1213         spin_lock_irqsave(&host->lock, flags);
1214
1215         WARN_ON(host->mrq != NULL);
1216
1217 #ifndef SDHCI_USE_LEDS_CLASS
1218         sdhci_activate_led(host);
1219 #endif
1220
1221         /*
1222          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1223          * requests if Auto-CMD12 is enabled.
1224          */
1225         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1226                 if (mrq->stop) {
1227                         mrq->data->stop = NULL;
1228                         mrq->stop = NULL;
1229                 }
1230         }
1231
1232         host->mrq = mrq;
1233
1234         /* If polling, assume that the card is always present. */
1235         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1236                 present = true;
1237         else
1238                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1239                                 SDHCI_CARD_PRESENT;
1240
1241         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1242                 host->mrq->cmd->error = -ENOMEDIUM;
1243                 tasklet_schedule(&host->finish_tasklet);
1244         } else {
1245                 u32 present_state;
1246
1247                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1248                 /*
1249                  * Check if the re-tuning timer has already expired and there
1250                  * is no on-going data transfer. If so, we need to execute
1251                  * tuning procedure before sending command.
1252                  */
1253                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1254                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1255                         spin_unlock_irqrestore(&host->lock, flags);
1256                         sdhci_execute_tuning(mmc);
1257                         spin_lock_irqsave(&host->lock, flags);
1258
1259                         /* Restore original mmc_request structure */
1260                         host->mrq = mrq;
1261                 }
1262
1263                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1264                         sdhci_send_command(host, mrq->sbc);
1265                 else
1266                         sdhci_send_command(host, mrq->cmd);
1267         }
1268
1269         mmiowb();
1270         spin_unlock_irqrestore(&host->lock, flags);
1271 }
1272
1273 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1274 {
1275         struct sdhci_host *host;
1276         unsigned long flags;
1277         u8 ctrl;
1278
1279         host = mmc_priv(mmc);
1280
1281         spin_lock_irqsave(&host->lock, flags);
1282
1283         if (host->flags & SDHCI_DEVICE_DEAD)
1284                 goto out;
1285
1286         /*
1287          * Reset the chip on each power off.
1288          * Should clear out any weird states.
1289          */
1290         if (ios->power_mode == MMC_POWER_OFF) {
1291                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1292                 sdhci_reinit(host);
1293         }
1294
1295         sdhci_set_clock(host, ios->clock);
1296
1297         if (ios->power_mode == MMC_POWER_OFF)
1298                 sdhci_set_power(host, -1);
1299         else
1300                 sdhci_set_power(host, ios->vdd);
1301
1302         if (host->ops->platform_send_init_74_clocks)
1303                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1304
1305         /*
1306          * If your platform has 8-bit width support but is not a v3 controller,
1307          * or if it requires special setup code, you should implement that in
1308          * platform_8bit_width().
1309          */
1310         if (host->ops->platform_8bit_width)
1311                 host->ops->platform_8bit_width(host, ios->bus_width);
1312         else {
1313                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1314                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1315                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1316                         if (host->version >= SDHCI_SPEC_300)
1317                                 ctrl |= SDHCI_CTRL_8BITBUS;
1318                 } else {
1319                         if (host->version >= SDHCI_SPEC_300)
1320                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1321                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1322                                 ctrl |= SDHCI_CTRL_4BITBUS;
1323                         else
1324                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1325                 }
1326                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1327         }
1328
1329         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1330
1331         if ((ios->timing == MMC_TIMING_SD_HS ||
1332              ios->timing == MMC_TIMING_MMC_HS)
1333             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1334                 ctrl |= SDHCI_CTRL_HISPD;
1335         else
1336                 ctrl &= ~SDHCI_CTRL_HISPD;
1337
1338         if (host->version >= SDHCI_SPEC_300) {
1339                 u16 clk, ctrl_2;
1340                 unsigned int clock;
1341
1342                 /* In case of UHS-I modes, set High Speed Enable */
1343                 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1344                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1345                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1346                     (ios->timing == MMC_TIMING_UHS_SDR25) ||
1347                     (ios->timing == MMC_TIMING_UHS_SDR12))
1348                         ctrl |= SDHCI_CTRL_HISPD;
1349
1350                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1351                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1352                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1353                         /*
1354                          * We only need to set Driver Strength if the
1355                          * preset value enable is not set.
1356                          */
1357                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1358                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1359                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1360                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1361                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1362
1363                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1364                 } else {
1365                         /*
1366                          * According to SDHC Spec v3.00, if the Preset Value
1367                          * Enable in the Host Control 2 register is set, we
1368                          * need to reset SD Clock Enable before changing High
1369                          * Speed Enable to avoid generating clock gliches.
1370                          */
1371
1372                         /* Reset SD Clock Enable */
1373                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1374                         clk &= ~SDHCI_CLOCK_CARD_EN;
1375                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1376
1377                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1378
1379                         /* Re-enable SD Clock */
1380                         clock = host->clock;
1381                         host->clock = 0;
1382                         sdhci_set_clock(host, clock);
1383                 }
1384
1385
1386                 /* Reset SD Clock Enable */
1387                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1388                 clk &= ~SDHCI_CLOCK_CARD_EN;
1389                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1390
1391                 if (host->ops->set_uhs_signaling)
1392                         host->ops->set_uhs_signaling(host, ios->timing);
1393                 else {
1394                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1395                         /* Select Bus Speed Mode for host */
1396                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1397                         if (ios->timing == MMC_TIMING_UHS_SDR12)
1398                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1399                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1400                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1401                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1402                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1403                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1404                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1405                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1406                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1407                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1408                 }
1409
1410                 /* Re-enable SD Clock */
1411                 clock = host->clock;
1412                 host->clock = 0;
1413                 sdhci_set_clock(host, clock);
1414         } else
1415                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1416
1417         /*
1418          * Some (ENE) controllers go apeshit on some ios operation,
1419          * signalling timeout and CRC errors even on CMD0. Resetting
1420          * it on each ios seems to solve the problem.
1421          */
1422         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1423                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1424
1425 out:
1426         mmiowb();
1427         spin_unlock_irqrestore(&host->lock, flags);
1428 }
1429
1430 static int check_ro(struct sdhci_host *host)
1431 {
1432         unsigned long flags;
1433         int is_readonly;
1434
1435         spin_lock_irqsave(&host->lock, flags);
1436
1437         if (host->flags & SDHCI_DEVICE_DEAD)
1438                 is_readonly = 0;
1439         else if (host->ops->get_ro)
1440                 is_readonly = host->ops->get_ro(host);
1441         else
1442                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1443                                 & SDHCI_WRITE_PROTECT);
1444
1445         spin_unlock_irqrestore(&host->lock, flags);
1446
1447         /* This quirk needs to be replaced by a callback-function later */
1448         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1449                 !is_readonly : is_readonly;
1450 }
1451
1452 #define SAMPLE_COUNT    5
1453
1454 static int sdhci_get_ro(struct mmc_host *mmc)
1455 {
1456         struct sdhci_host *host;
1457         int i, ro_count;
1458
1459         host = mmc_priv(mmc);
1460
1461         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1462                 return check_ro(host);
1463
1464         ro_count = 0;
1465         for (i = 0; i < SAMPLE_COUNT; i++) {
1466                 if (check_ro(host)) {
1467                         if (++ro_count > SAMPLE_COUNT / 2)
1468                                 return 1;
1469                 }
1470                 msleep(30);
1471         }
1472         return 0;
1473 }
1474
1475 static void sdhci_hw_reset(struct mmc_host *mmc)
1476 {
1477         struct sdhci_host *host = mmc_priv(mmc);
1478
1479         if (host->ops && host->ops->hw_reset)
1480                 host->ops->hw_reset(host);
1481 }
1482
1483 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1484 {
1485         struct sdhci_host *host;
1486         unsigned long flags;
1487
1488         host = mmc_priv(mmc);
1489
1490         spin_lock_irqsave(&host->lock, flags);
1491
1492         if (host->flags & SDHCI_DEVICE_DEAD)
1493                 goto out;
1494
1495         if (enable)
1496                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1497         else
1498                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1499 out:
1500         mmiowb();
1501
1502         spin_unlock_irqrestore(&host->lock, flags);
1503 }
1504
1505 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1506         struct mmc_ios *ios)
1507 {
1508         struct sdhci_host *host;
1509         u8 pwr;
1510         u16 clk, ctrl;
1511         u32 present_state;
1512
1513         host = mmc_priv(mmc);
1514
1515         /*
1516          * Signal Voltage Switching is only applicable for Host Controllers
1517          * v3.00 and above.
1518          */
1519         if (host->version < SDHCI_SPEC_300)
1520                 return 0;
1521
1522         /*
1523          * We first check whether the request is to set signalling voltage
1524          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1525          */
1526         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1527         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1528                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1529                 ctrl &= ~SDHCI_CTRL_VDD_180;
1530                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1531
1532                 /* Wait for 5ms */
1533                 usleep_range(5000, 5500);
1534
1535                 /* 3.3V regulator output should be stable within 5 ms */
1536                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1537                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1538                         return 0;
1539                 else {
1540                         printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1541                                 "signalling voltage failed\n");
1542                         return -EIO;
1543                 }
1544         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1545                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1546                 /* Stop SDCLK */
1547                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1548                 clk &= ~SDHCI_CLOCK_CARD_EN;
1549                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1550
1551                 /* Check whether DAT[3:0] is 0000 */
1552                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1553                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1554                        SDHCI_DATA_LVL_SHIFT)) {
1555                         /*
1556                          * Enable 1.8V Signal Enable in the Host Control2
1557                          * register
1558                          */
1559                         ctrl |= SDHCI_CTRL_VDD_180;
1560                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1561
1562                         /* Wait for 5ms */
1563                         usleep_range(5000, 5500);
1564
1565                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1566                         if (ctrl & SDHCI_CTRL_VDD_180) {
1567                                 /* Provide SDCLK again and wait for 1ms*/
1568                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1569                                 clk |= SDHCI_CLOCK_CARD_EN;
1570                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1571                                 usleep_range(1000, 1500);
1572
1573                                 /*
1574                                  * If DAT[3:0] level is 1111b, then the card
1575                                  * was successfully switched to 1.8V signaling.
1576                                  */
1577                                 present_state = sdhci_readl(host,
1578                                                         SDHCI_PRESENT_STATE);
1579                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1580                                      SDHCI_DATA_LVL_MASK)
1581                                         return 0;
1582                         }
1583                 }
1584
1585                 /*
1586                  * If we are here, that means the switch to 1.8V signaling
1587                  * failed. We power cycle the card, and retry initialization
1588                  * sequence by setting S18R to 0.
1589                  */
1590                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1591                 pwr &= ~SDHCI_POWER_ON;
1592                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1593
1594                 /* Wait for 1ms as per the spec */
1595                 usleep_range(1000, 1500);
1596                 pwr |= SDHCI_POWER_ON;
1597                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1598
1599                 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1600                         "voltage failed, retrying with S18R set to 0\n");
1601                 return -EAGAIN;
1602         } else
1603                 /* No signal voltage switch required */
1604                 return 0;
1605 }
1606
1607 static int sdhci_execute_tuning(struct mmc_host *mmc)
1608 {
1609         struct sdhci_host *host;
1610         u16 ctrl;
1611         u32 ier;
1612         int tuning_loop_counter = MAX_TUNING_LOOP;
1613         unsigned long timeout;
1614         int err = 0;
1615
1616         host = mmc_priv(mmc);
1617
1618         disable_irq(host->irq);
1619         spin_lock(&host->lock);
1620
1621         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1622
1623         /*
1624          * Host Controller needs tuning only in case of SDR104 mode
1625          * and for SDR50 mode when Use Tuning for SDR50 is set in
1626          * Capabilities register.
1627          */
1628         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1629             (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1630             (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1631                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1632         else {
1633                 spin_unlock(&host->lock);
1634                 enable_irq(host->irq);
1635                 return 0;
1636         }
1637
1638         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1639
1640         /*
1641          * As per the Host Controller spec v3.00, tuning command
1642          * generates Buffer Read Ready interrupt, so enable that.
1643          *
1644          * Note: The spec clearly says that when tuning sequence
1645          * is being performed, the controller does not generate
1646          * interrupts other than Buffer Read Ready interrupt. But
1647          * to make sure we don't hit a controller bug, we _only_
1648          * enable Buffer Read Ready interrupt here.
1649          */
1650         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1651         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1652
1653         /*
1654          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1655          * of loops reaches 40 times or a timeout of 150ms occurs.
1656          */
1657         timeout = 150;
1658         do {
1659                 struct mmc_command cmd = {0};
1660                 struct mmc_request mrq = {0};
1661
1662                 if (!tuning_loop_counter && !timeout)
1663                         break;
1664
1665                 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1666                 cmd.arg = 0;
1667                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1668                 cmd.retries = 0;
1669                 cmd.data = NULL;
1670                 cmd.error = 0;
1671
1672                 mrq.cmd = &cmd;
1673                 host->mrq = &mrq;
1674
1675                 /*
1676                  * In response to CMD19, the card sends 64 bytes of tuning
1677                  * block to the Host Controller. So we set the block size
1678                  * to 64 here.
1679                  */
1680                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1681
1682                 /*
1683                  * The tuning block is sent by the card to the host controller.
1684                  * So we set the TRNS_READ bit in the Transfer Mode register.
1685                  * This also takes care of setting DMA Enable and Multi Block
1686                  * Select in the same register to 0.
1687                  */
1688                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1689
1690                 sdhci_send_command(host, &cmd);
1691
1692                 host->cmd = NULL;
1693                 host->mrq = NULL;
1694
1695                 spin_unlock(&host->lock);
1696                 enable_irq(host->irq);
1697
1698                 /* Wait for Buffer Read Ready interrupt */
1699                 wait_event_interruptible_timeout(host->buf_ready_int,
1700                                         (host->tuning_done == 1),
1701                                         msecs_to_jiffies(50));
1702                 disable_irq(host->irq);
1703                 spin_lock(&host->lock);
1704
1705                 if (!host->tuning_done) {
1706                         printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1707                                 "Buffer Read Ready interrupt during tuning "
1708                                 "procedure, falling back to fixed sampling "
1709                                 "clock\n");
1710                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1711                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1712                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1713                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1714
1715                         err = -EIO;
1716                         goto out;
1717                 }
1718
1719                 host->tuning_done = 0;
1720
1721                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1722                 tuning_loop_counter--;
1723                 timeout--;
1724                 mdelay(1);
1725         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1726
1727         /*
1728          * The Host Driver has exhausted the maximum number of loops allowed,
1729          * so use fixed sampling frequency.
1730          */
1731         if (!tuning_loop_counter || !timeout) {
1732                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1733                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1734         } else {
1735                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1736                         printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1737                                 " failed, falling back to fixed sampling"
1738                                 " clock\n");
1739                         err = -EIO;
1740                 }
1741         }
1742
1743 out:
1744         /*
1745          * If this is the very first time we are here, we start the retuning
1746          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1747          * flag won't be set, we check this condition before actually starting
1748          * the timer.
1749          */
1750         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1751             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1752                 mod_timer(&host->tuning_timer, jiffies +
1753                         host->tuning_count * HZ);
1754                 /* Tuning mode 1 limits the maximum data length to 4MB */
1755                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1756         } else {
1757                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1758                 /* Reload the new initial value for timer */
1759                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1760                         mod_timer(&host->tuning_timer, jiffies +
1761                                 host->tuning_count * HZ);
1762         }
1763
1764         /*
1765          * In case tuning fails, host controllers which support re-tuning can
1766          * try tuning again at a later time, when the re-tuning timer expires.
1767          * So for these controllers, we return 0. Since there might be other
1768          * controllers who do not have this capability, we return error for
1769          * them.
1770          */
1771         if (err && host->tuning_count &&
1772             host->tuning_mode == SDHCI_TUNING_MODE_1)
1773                 err = 0;
1774
1775         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1776         spin_unlock(&host->lock);
1777         enable_irq(host->irq);
1778
1779         return err;
1780 }
1781
1782 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1783 {
1784         struct sdhci_host *host;
1785         u16 ctrl;
1786         unsigned long flags;
1787
1788         host = mmc_priv(mmc);
1789
1790         /* Host Controller v3.00 defines preset value registers */
1791         if (host->version < SDHCI_SPEC_300)
1792                 return;
1793
1794         spin_lock_irqsave(&host->lock, flags);
1795
1796         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1797
1798         /*
1799          * We only enable or disable Preset Value if they are not already
1800          * enabled or disabled respectively. Otherwise, we bail out.
1801          */
1802         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1803                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1804                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1805         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1806                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1807                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1808         }
1809
1810         spin_unlock_irqrestore(&host->lock, flags);
1811 }
1812
1813 static const struct mmc_host_ops sdhci_ops = {
1814         .request        = sdhci_request,
1815         .set_ios        = sdhci_set_ios,
1816         .get_ro         = sdhci_get_ro,
1817         .hw_reset       = sdhci_hw_reset,
1818         .enable_sdio_irq = sdhci_enable_sdio_irq,
1819         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1820         .execute_tuning                 = sdhci_execute_tuning,
1821         .enable_preset_value            = sdhci_enable_preset_value,
1822 };
1823
1824 /*****************************************************************************\
1825  *                                                                           *
1826  * Tasklets                                                                  *
1827  *                                                                           *
1828 \*****************************************************************************/
1829
1830 static void sdhci_tasklet_card(unsigned long param)
1831 {
1832         struct sdhci_host *host;
1833         unsigned long flags;
1834
1835         host = (struct sdhci_host*)param;
1836
1837         spin_lock_irqsave(&host->lock, flags);
1838
1839         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1840                 if (host->mrq) {
1841                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1842                                 mmc_hostname(host->mmc));
1843                         printk(KERN_ERR "%s: Resetting controller.\n",
1844                                 mmc_hostname(host->mmc));
1845
1846                         sdhci_reset(host, SDHCI_RESET_CMD);
1847                         sdhci_reset(host, SDHCI_RESET_DATA);
1848
1849                         host->mrq->cmd->error = -ENOMEDIUM;
1850                         tasklet_schedule(&host->finish_tasklet);
1851                 }
1852         }
1853
1854         spin_unlock_irqrestore(&host->lock, flags);
1855
1856         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1857 }
1858
1859 static void sdhci_tasklet_finish(unsigned long param)
1860 {
1861         struct sdhci_host *host;
1862         unsigned long flags;
1863         struct mmc_request *mrq;
1864
1865         host = (struct sdhci_host*)param;
1866
1867         /*
1868          * If this tasklet gets rescheduled while running, it will
1869          * be run again afterwards but without any active request.
1870          */
1871         if (!host->mrq)
1872                 return;
1873
1874         spin_lock_irqsave(&host->lock, flags);
1875
1876         del_timer(&host->timer);
1877
1878         mrq = host->mrq;
1879
1880         /*
1881          * The controller needs a reset of internal state machines
1882          * upon error conditions.
1883          */
1884         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1885             ((mrq->cmd && mrq->cmd->error) ||
1886                  (mrq->data && (mrq->data->error ||
1887                   (mrq->data->stop && mrq->data->stop->error))) ||
1888                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1889
1890                 /* Some controllers need this kick or reset won't work here */
1891                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1892                         unsigned int clock;
1893
1894                         /* This is to force an update */
1895                         clock = host->clock;
1896                         host->clock = 0;
1897                         sdhci_set_clock(host, clock);
1898                 }
1899
1900                 /* Spec says we should do both at the same time, but Ricoh
1901                    controllers do not like that. */
1902                 sdhci_reset(host, SDHCI_RESET_CMD);
1903                 sdhci_reset(host, SDHCI_RESET_DATA);
1904         }
1905
1906         host->mrq = NULL;
1907         host->cmd = NULL;
1908         host->data = NULL;
1909
1910 #ifndef SDHCI_USE_LEDS_CLASS
1911         sdhci_deactivate_led(host);
1912 #endif
1913
1914         mmiowb();
1915         spin_unlock_irqrestore(&host->lock, flags);
1916
1917         mmc_request_done(host->mmc, mrq);
1918 }
1919
1920 static void sdhci_timeout_timer(unsigned long data)
1921 {
1922         struct sdhci_host *host;
1923         unsigned long flags;
1924
1925         host = (struct sdhci_host*)data;
1926
1927         spin_lock_irqsave(&host->lock, flags);
1928
1929         if (host->mrq) {
1930                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1931                         "interrupt.\n", mmc_hostname(host->mmc));
1932                 sdhci_dumpregs(host);
1933
1934                 if (host->data) {
1935                         host->data->error = -ETIMEDOUT;
1936                         sdhci_finish_data(host);
1937                 } else {
1938                         if (host->cmd)
1939                                 host->cmd->error = -ETIMEDOUT;
1940                         else
1941                                 host->mrq->cmd->error = -ETIMEDOUT;
1942
1943                         tasklet_schedule(&host->finish_tasklet);
1944                 }
1945         }
1946
1947         mmiowb();
1948         spin_unlock_irqrestore(&host->lock, flags);
1949 }
1950
1951 static void sdhci_tuning_timer(unsigned long data)
1952 {
1953         struct sdhci_host *host;
1954         unsigned long flags;
1955
1956         host = (struct sdhci_host *)data;
1957
1958         spin_lock_irqsave(&host->lock, flags);
1959
1960         host->flags |= SDHCI_NEEDS_RETUNING;
1961
1962         spin_unlock_irqrestore(&host->lock, flags);
1963 }
1964
1965 /*****************************************************************************\
1966  *                                                                           *
1967  * Interrupt handling                                                        *
1968  *                                                                           *
1969 \*****************************************************************************/
1970
1971 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1972 {
1973         BUG_ON(intmask == 0);
1974
1975         if (!host->cmd) {
1976                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1977                         "though no command operation was in progress.\n",
1978                         mmc_hostname(host->mmc), (unsigned)intmask);
1979                 sdhci_dumpregs(host);
1980                 return;
1981         }
1982
1983         if (intmask & SDHCI_INT_TIMEOUT)
1984                 host->cmd->error = -ETIMEDOUT;
1985         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1986                         SDHCI_INT_INDEX))
1987                 host->cmd->error = -EILSEQ;
1988
1989         if (host->cmd->error) {
1990                 tasklet_schedule(&host->finish_tasklet);
1991                 return;
1992         }
1993
1994         /*
1995          * The host can send and interrupt when the busy state has
1996          * ended, allowing us to wait without wasting CPU cycles.
1997          * Unfortunately this is overloaded on the "data complete"
1998          * interrupt, so we need to take some care when handling
1999          * it.
2000          *
2001          * Note: The 1.0 specification is a bit ambiguous about this
2002          *       feature so there might be some problems with older
2003          *       controllers.
2004          */
2005         if (host->cmd->flags & MMC_RSP_BUSY) {
2006                 if (host->cmd->data)
2007                         DBG("Cannot wait for busy signal when also "
2008                                 "doing a data transfer");
2009                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2010                         return;
2011
2012                 /* The controller does not support the end-of-busy IRQ,
2013                  * fall through and take the SDHCI_INT_RESPONSE */
2014         }
2015
2016         if (intmask & SDHCI_INT_RESPONSE)
2017                 sdhci_finish_command(host);
2018 }
2019
2020 #ifdef CONFIG_MMC_DEBUG
2021 static void sdhci_show_adma_error(struct sdhci_host *host)
2022 {
2023         const char *name = mmc_hostname(host->mmc);
2024         u8 *desc = host->adma_desc;
2025         __le32 *dma;
2026         __le16 *len;
2027         u8 attr;
2028
2029         sdhci_dumpregs(host);
2030
2031         while (true) {
2032                 dma = (__le32 *)(desc + 4);
2033                 len = (__le16 *)(desc + 2);
2034                 attr = *desc;
2035
2036                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2037                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2038
2039                 desc += 8;
2040
2041                 if (attr & 2)
2042                         break;
2043         }
2044 }
2045 #else
2046 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2047 #endif
2048
2049 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2050 {
2051         BUG_ON(intmask == 0);
2052
2053         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2054         if (intmask & SDHCI_INT_DATA_AVAIL) {
2055                 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2056                     MMC_SEND_TUNING_BLOCK) {
2057                         host->tuning_done = 1;
2058                         wake_up(&host->buf_ready_int);
2059                         return;
2060                 }
2061         }
2062
2063         if (!host->data) {
2064                 /*
2065                  * The "data complete" interrupt is also used to
2066                  * indicate that a busy state has ended. See comment
2067                  * above in sdhci_cmd_irq().
2068                  */
2069                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2070                         if (intmask & SDHCI_INT_DATA_END) {
2071                                 sdhci_finish_command(host);
2072                                 return;
2073                         }
2074                 }
2075
2076                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2077                         "though no data operation was in progress.\n",
2078                         mmc_hostname(host->mmc), (unsigned)intmask);
2079                 sdhci_dumpregs(host);
2080
2081                 return;
2082         }
2083
2084         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2085                 host->data->error = -ETIMEDOUT;
2086         else if (intmask & SDHCI_INT_DATA_END_BIT)
2087                 host->data->error = -EILSEQ;
2088         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2089                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2090                         != MMC_BUS_TEST_R)
2091                 host->data->error = -EILSEQ;
2092         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2093                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2094                 sdhci_show_adma_error(host);
2095                 host->data->error = -EIO;
2096         }
2097
2098         if (host->data->error)
2099                 sdhci_finish_data(host);
2100         else {
2101                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2102                         sdhci_transfer_pio(host);
2103
2104                 /*
2105                  * We currently don't do anything fancy with DMA
2106                  * boundaries, but as we can't disable the feature
2107                  * we need to at least restart the transfer.
2108                  *
2109                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2110                  * should return a valid address to continue from, but as
2111                  * some controllers are faulty, don't trust them.
2112                  */
2113                 if (intmask & SDHCI_INT_DMA_END) {
2114                         u32 dmastart, dmanow;
2115                         dmastart = sg_dma_address(host->data->sg);
2116                         dmanow = dmastart + host->data->bytes_xfered;
2117                         /*
2118                          * Force update to the next DMA block boundary.
2119                          */
2120                         dmanow = (dmanow &
2121                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2122                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2123                         host->data->bytes_xfered = dmanow - dmastart;
2124                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2125                                 " next 0x%08x\n",
2126                                 mmc_hostname(host->mmc), dmastart,
2127                                 host->data->bytes_xfered, dmanow);
2128                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2129                 }
2130
2131                 if (intmask & SDHCI_INT_DATA_END) {
2132                         if (host->cmd) {
2133                                 /*
2134                                  * Data managed to finish before the
2135                                  * command completed. Make sure we do
2136                                  * things in the proper order.
2137                                  */
2138                                 host->data_early = 1;
2139                         } else {
2140                                 sdhci_finish_data(host);
2141                         }
2142                 }
2143         }
2144 }
2145
2146 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2147 {
2148         irqreturn_t result;
2149         struct sdhci_host* host = dev_id;
2150         u32 intmask;
2151         int cardint = 0;
2152
2153         spin_lock(&host->lock);
2154
2155         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2156
2157         if (!intmask || intmask == 0xffffffff) {
2158                 result = IRQ_NONE;
2159                 goto out;
2160         }
2161
2162         DBG("*** %s got interrupt: 0x%08x\n",
2163                 mmc_hostname(host->mmc), intmask);
2164
2165         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2166                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2167                               SDHCI_CARD_PRESENT;
2168
2169                 /*
2170                  * There is a observation on i.mx esdhc.  INSERT bit will be
2171                  * immediately set again when it gets cleared, if a card is
2172                  * inserted.  We have to mask the irq to prevent interrupt
2173                  * storm which will freeze the system.  And the REMOVE gets
2174                  * the same situation.
2175                  *
2176                  * More testing are needed here to ensure it works for other
2177                  * platforms though.
2178                  */
2179                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2180                                                 SDHCI_INT_CARD_REMOVE);
2181                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2182                                                   SDHCI_INT_CARD_INSERT);
2183
2184                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2185                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2186                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2187                 tasklet_schedule(&host->card_tasklet);
2188         }
2189
2190         if (intmask & SDHCI_INT_CMD_MASK) {
2191                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2192                         SDHCI_INT_STATUS);
2193                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2194         }
2195
2196         if (intmask & SDHCI_INT_DATA_MASK) {
2197                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2198                         SDHCI_INT_STATUS);
2199                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2200         }
2201
2202         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2203
2204         intmask &= ~SDHCI_INT_ERROR;
2205
2206         if (intmask & SDHCI_INT_BUS_POWER) {
2207                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
2208                         mmc_hostname(host->mmc));
2209                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2210         }
2211
2212         intmask &= ~SDHCI_INT_BUS_POWER;
2213
2214         if (intmask & SDHCI_INT_CARD_INT)
2215                 cardint = 1;
2216
2217         intmask &= ~SDHCI_INT_CARD_INT;
2218
2219         if (intmask) {
2220                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
2221                         mmc_hostname(host->mmc), intmask);
2222                 sdhci_dumpregs(host);
2223
2224                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2225         }
2226
2227         result = IRQ_HANDLED;
2228
2229         mmiowb();
2230 out:
2231         spin_unlock(&host->lock);
2232
2233         /*
2234          * We have to delay this as it calls back into the driver.
2235          */
2236         if (cardint)
2237                 mmc_signal_sdio_irq(host->mmc);
2238
2239         return result;
2240 }
2241
2242 /*****************************************************************************\
2243  *                                                                           *
2244  * Suspend/resume                                                            *
2245  *                                                                           *
2246 \*****************************************************************************/
2247
2248 #ifdef CONFIG_PM
2249
2250 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
2251 {
2252         int ret;
2253
2254         sdhci_disable_card_detection(host);
2255
2256         /* Disable tuning since we are suspending */
2257         if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2258             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2259                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2260                 mod_timer(&host->tuning_timer, jiffies +
2261                         host->tuning_count * HZ);
2262         }
2263
2264         ret = mmc_suspend_host(host->mmc);
2265         if (ret)
2266                 return ret;
2267
2268         free_irq(host->irq, host);
2269
2270         if (host->vmmc)
2271                 ret = regulator_disable(host->vmmc);
2272
2273         return ret;
2274 }
2275
2276 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2277
2278 int sdhci_resume_host(struct sdhci_host *host)
2279 {
2280         int ret;
2281
2282         if (host->vmmc) {
2283                 int ret = regulator_enable(host->vmmc);
2284                 if (ret)
2285                         return ret;
2286         }
2287
2288
2289         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2290                 if (host->ops->enable_dma)
2291                         host->ops->enable_dma(host);
2292         }
2293
2294         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2295                           mmc_hostname(host->mmc), host);
2296         if (ret)
2297                 return ret;
2298
2299         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2300         mmiowb();
2301
2302         ret = mmc_resume_host(host->mmc);
2303         sdhci_enable_card_detection(host);
2304
2305         /* Set the re-tuning expiration flag */
2306         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2307             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2308                 host->flags |= SDHCI_NEEDS_RETUNING;
2309
2310         return ret;
2311 }
2312
2313 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2314
2315 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2316 {
2317         u8 val;
2318         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2319         val |= SDHCI_WAKE_ON_INT;
2320         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2321 }
2322
2323 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2324
2325 #endif /* CONFIG_PM */
2326
2327 /*****************************************************************************\
2328  *                                                                           *
2329  * Device allocation/registration                                            *
2330  *                                                                           *
2331 \*****************************************************************************/
2332
2333 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2334         size_t priv_size)
2335 {
2336         struct mmc_host *mmc;
2337         struct sdhci_host *host;
2338
2339         WARN_ON(dev == NULL);
2340
2341         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2342         if (!mmc)
2343                 return ERR_PTR(-ENOMEM);
2344
2345         host = mmc_priv(mmc);
2346         host->mmc = mmc;
2347
2348         return host;
2349 }
2350
2351 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2352
2353 int sdhci_add_host(struct sdhci_host *host)
2354 {
2355         struct mmc_host *mmc;
2356         u32 caps[2];
2357         u32 max_current_caps;
2358         unsigned int ocr_avail;
2359         int ret;
2360
2361         WARN_ON(host == NULL);
2362         if (host == NULL)
2363                 return -EINVAL;
2364
2365         mmc = host->mmc;
2366
2367         if (debug_quirks)
2368                 host->quirks = debug_quirks;
2369
2370         sdhci_reset(host, SDHCI_RESET_ALL);
2371
2372         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2373         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2374                                 >> SDHCI_SPEC_VER_SHIFT;
2375         if (host->version > SDHCI_SPEC_300) {
2376                 printk(KERN_ERR "%s: Unknown controller version (%d). "
2377                         "You may experience problems.\n", mmc_hostname(mmc),
2378                         host->version);
2379         }
2380
2381         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2382                 sdhci_readl(host, SDHCI_CAPABILITIES);
2383
2384         caps[1] = (host->version >= SDHCI_SPEC_300) ?
2385                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2386
2387         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2388                 host->flags |= SDHCI_USE_SDMA;
2389         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2390                 DBG("Controller doesn't have SDMA capability\n");
2391         else
2392                 host->flags |= SDHCI_USE_SDMA;
2393
2394         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2395                 (host->flags & SDHCI_USE_SDMA)) {
2396                 DBG("Disabling DMA as it is marked broken\n");
2397                 host->flags &= ~SDHCI_USE_SDMA;
2398         }
2399
2400         if ((host->version >= SDHCI_SPEC_200) &&
2401                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2402                 host->flags |= SDHCI_USE_ADMA;
2403
2404         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2405                 (host->flags & SDHCI_USE_ADMA)) {
2406                 DBG("Disabling ADMA as it is marked broken\n");
2407                 host->flags &= ~SDHCI_USE_ADMA;
2408         }
2409
2410         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2411                 if (host->ops->enable_dma) {
2412                         if (host->ops->enable_dma(host)) {
2413                                 printk(KERN_WARNING "%s: No suitable DMA "
2414                                         "available. Falling back to PIO.\n",
2415                                         mmc_hostname(mmc));
2416                                 host->flags &=
2417                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2418                         }
2419                 }
2420         }
2421
2422         if (host->flags & SDHCI_USE_ADMA) {
2423                 /*
2424                  * We need to allocate descriptors for all sg entries
2425                  * (128) and potentially one alignment transfer for
2426                  * each of those entries.
2427                  */
2428                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2429                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2430                 if (!host->adma_desc || !host->align_buffer) {
2431                         kfree(host->adma_desc);
2432                         kfree(host->align_buffer);
2433                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
2434                                 "buffers. Falling back to standard DMA.\n",
2435                                 mmc_hostname(mmc));
2436                         host->flags &= ~SDHCI_USE_ADMA;
2437                 }
2438         }
2439
2440         /*
2441          * If we use DMA, then it's up to the caller to set the DMA
2442          * mask, but PIO does not need the hw shim so we set a new
2443          * mask here in that case.
2444          */
2445         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2446                 host->dma_mask = DMA_BIT_MASK(64);
2447                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2448         }
2449
2450         if (host->version >= SDHCI_SPEC_300)
2451                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2452                         >> SDHCI_CLOCK_BASE_SHIFT;
2453         else
2454                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2455                         >> SDHCI_CLOCK_BASE_SHIFT;
2456
2457         host->max_clk *= 1000000;
2458         if (host->max_clk == 0 || host->quirks &
2459                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2460                 if (!host->ops->get_max_clock) {
2461                         printk(KERN_ERR
2462                                "%s: Hardware doesn't specify base clock "
2463                                "frequency.\n", mmc_hostname(mmc));
2464                         return -ENODEV;
2465                 }
2466                 host->max_clk = host->ops->get_max_clock(host);
2467         }
2468
2469         /*
2470          * In case of Host Controller v3.00, find out whether clock
2471          * multiplier is supported.
2472          */
2473         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2474                         SDHCI_CLOCK_MUL_SHIFT;
2475
2476         /*
2477          * In case the value in Clock Multiplier is 0, then programmable
2478          * clock mode is not supported, otherwise the actual clock
2479          * multiplier is one more than the value of Clock Multiplier
2480          * in the Capabilities Register.
2481          */
2482         if (host->clk_mul)
2483                 host->clk_mul += 1;
2484
2485         /*
2486          * Set host parameters.
2487          */
2488         mmc->ops = &sdhci_ops;
2489         mmc->f_max = host->max_clk;
2490         if (host->ops->get_min_clock)
2491                 mmc->f_min = host->ops->get_min_clock(host);
2492         else if (host->version >= SDHCI_SPEC_300) {
2493                 if (host->clk_mul) {
2494                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2495                         mmc->f_max = host->max_clk * host->clk_mul;
2496                 } else
2497                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2498         } else
2499                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2500
2501         host->timeout_clk =
2502                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2503         if (host->timeout_clk == 0) {
2504                 if (host->ops->get_timeout_clock) {
2505                         host->timeout_clk = host->ops->get_timeout_clock(host);
2506                 } else if (!(host->quirks &
2507                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2508                         printk(KERN_ERR
2509                                "%s: Hardware doesn't specify timeout clock "
2510                                "frequency.\n", mmc_hostname(mmc));
2511                         return -ENODEV;
2512                 }
2513         }
2514         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2515                 host->timeout_clk *= 1000;
2516
2517         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2518                 host->timeout_clk = mmc->f_max / 1000;
2519
2520         mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2521
2522         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2523
2524         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2525                 host->flags |= SDHCI_AUTO_CMD12;
2526
2527         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2528         if ((host->version >= SDHCI_SPEC_300) &&
2529             ((host->flags & SDHCI_USE_ADMA) ||
2530              !(host->flags & SDHCI_USE_SDMA))) {
2531                 host->flags |= SDHCI_AUTO_CMD23;
2532                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2533         } else {
2534                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2535         }
2536
2537         /*
2538          * A controller may support 8-bit width, but the board itself
2539          * might not have the pins brought out.  Boards that support
2540          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2541          * their platform code before calling sdhci_add_host(), and we
2542          * won't assume 8-bit width for hosts without that CAP.
2543          */
2544         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2545                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2546
2547         if (caps[0] & SDHCI_CAN_DO_HISPD)
2548                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2549
2550         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2551             mmc_card_is_removable(mmc))
2552                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2553
2554         /* UHS-I mode(s) supported by the host controller. */
2555         if (host->version >= SDHCI_SPEC_300)
2556                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2557
2558         /* SDR104 supports also implies SDR50 support */
2559         if (caps[1] & SDHCI_SUPPORT_SDR104)
2560                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2561         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2562                 mmc->caps |= MMC_CAP_UHS_SDR50;
2563
2564         if (caps[1] & SDHCI_SUPPORT_DDR50)
2565                 mmc->caps |= MMC_CAP_UHS_DDR50;
2566
2567         /* Does the host needs tuning for SDR50? */
2568         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2569                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2570
2571         /* Driver Type(s) (A, C, D) supported by the host */
2572         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2573                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2574         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2575                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2576         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2577                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2578
2579         /* Initial value for re-tuning timer count */
2580         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2581                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2582
2583         /*
2584          * In case Re-tuning Timer is not disabled, the actual value of
2585          * re-tuning timer will be 2 ^ (n - 1).
2586          */
2587         if (host->tuning_count)
2588                 host->tuning_count = 1 << (host->tuning_count - 1);
2589
2590         /* Re-tuning mode supported by the Host Controller */
2591         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2592                              SDHCI_RETUNING_MODE_SHIFT;
2593
2594         ocr_avail = 0;
2595         /*
2596          * According to SD Host Controller spec v3.00, if the Host System
2597          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2598          * the value is meaningful only if Voltage Support in the Capabilities
2599          * register is set. The actual current value is 4 times the register
2600          * value.
2601          */
2602         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2603
2604         if (caps[0] & SDHCI_CAN_VDD_330) {
2605                 int max_current_330;
2606
2607                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2608
2609                 max_current_330 = ((max_current_caps &
2610                                    SDHCI_MAX_CURRENT_330_MASK) >>
2611                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2612                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2613
2614                 if (max_current_330 > 150)
2615                         mmc->caps |= MMC_CAP_SET_XPC_330;
2616         }
2617         if (caps[0] & SDHCI_CAN_VDD_300) {
2618                 int max_current_300;
2619
2620                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2621
2622                 max_current_300 = ((max_current_caps &
2623                                    SDHCI_MAX_CURRENT_300_MASK) >>
2624                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2625                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2626
2627                 if (max_current_300 > 150)
2628                         mmc->caps |= MMC_CAP_SET_XPC_300;
2629         }
2630         if (caps[0] & SDHCI_CAN_VDD_180) {
2631                 int max_current_180;
2632
2633                 ocr_avail |= MMC_VDD_165_195;
2634
2635                 max_current_180 = ((max_current_caps &
2636                                    SDHCI_MAX_CURRENT_180_MASK) >>
2637                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2638                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2639
2640                 if (max_current_180 > 150)
2641                         mmc->caps |= MMC_CAP_SET_XPC_180;
2642
2643                 /* Maximum current capabilities of the host at 1.8V */
2644                 if (max_current_180 >= 800)
2645                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2646                 else if (max_current_180 >= 600)
2647                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2648                 else if (max_current_180 >= 400)
2649                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2650                 else
2651                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2652         }
2653
2654         mmc->ocr_avail = ocr_avail;
2655         mmc->ocr_avail_sdio = ocr_avail;
2656         if (host->ocr_avail_sdio)
2657                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2658         mmc->ocr_avail_sd = ocr_avail;
2659         if (host->ocr_avail_sd)
2660                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2661         else /* normal SD controllers don't support 1.8V */
2662                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2663         mmc->ocr_avail_mmc = ocr_avail;
2664         if (host->ocr_avail_mmc)
2665                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2666
2667         if (mmc->ocr_avail == 0) {
2668                 printk(KERN_ERR "%s: Hardware doesn't report any "
2669                         "support voltages.\n", mmc_hostname(mmc));
2670                 return -ENODEV;
2671         }
2672
2673         spin_lock_init(&host->lock);
2674
2675         /*
2676          * Maximum number of segments. Depends on if the hardware
2677          * can do scatter/gather or not.
2678          */
2679         if (host->flags & SDHCI_USE_ADMA)
2680                 mmc->max_segs = 128;
2681         else if (host->flags & SDHCI_USE_SDMA)
2682                 mmc->max_segs = 1;
2683         else /* PIO */
2684                 mmc->max_segs = 128;
2685
2686         /*
2687          * Maximum number of sectors in one transfer. Limited by DMA boundary
2688          * size (512KiB).
2689          */
2690         mmc->max_req_size = 524288;
2691
2692         /*
2693          * Maximum segment size. Could be one segment with the maximum number
2694          * of bytes. When doing hardware scatter/gather, each entry cannot
2695          * be larger than 64 KiB though.
2696          */
2697         if (host->flags & SDHCI_USE_ADMA) {
2698                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2699                         mmc->max_seg_size = 65535;
2700                 else
2701                         mmc->max_seg_size = 65536;
2702         } else {
2703                 mmc->max_seg_size = mmc->max_req_size;
2704         }
2705
2706         /*
2707          * Maximum block size. This varies from controller to controller and
2708          * is specified in the capabilities register.
2709          */
2710         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2711                 mmc->max_blk_size = 2;
2712         } else {
2713                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2714                                 SDHCI_MAX_BLOCK_SHIFT;
2715                 if (mmc->max_blk_size >= 3) {
2716                         printk(KERN_WARNING "%s: Invalid maximum block size, "
2717                                 "assuming 512 bytes\n", mmc_hostname(mmc));
2718                         mmc->max_blk_size = 0;
2719                 }
2720         }
2721
2722         mmc->max_blk_size = 512 << mmc->max_blk_size;
2723
2724         /*
2725          * Maximum block count.
2726          */
2727         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2728
2729         /*
2730          * Init tasklets.
2731          */
2732         tasklet_init(&host->card_tasklet,
2733                 sdhci_tasklet_card, (unsigned long)host);
2734         tasklet_init(&host->finish_tasklet,
2735                 sdhci_tasklet_finish, (unsigned long)host);
2736
2737         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2738
2739         if (host->version >= SDHCI_SPEC_300) {
2740                 init_waitqueue_head(&host->buf_ready_int);
2741
2742                 /* Initialize re-tuning timer */
2743                 init_timer(&host->tuning_timer);
2744                 host->tuning_timer.data = (unsigned long)host;
2745                 host->tuning_timer.function = sdhci_tuning_timer;
2746         }
2747
2748         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2749                 mmc_hostname(mmc), host);
2750         if (ret)
2751                 goto untasklet;
2752
2753         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2754         if (IS_ERR(host->vmmc)) {
2755                 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2756                 host->vmmc = NULL;
2757         } else {
2758                 regulator_enable(host->vmmc);
2759         }
2760
2761         sdhci_init(host, 0);
2762
2763 #ifdef CONFIG_MMC_DEBUG
2764         sdhci_dumpregs(host);
2765 #endif
2766
2767 #ifdef SDHCI_USE_LEDS_CLASS
2768         snprintf(host->led_name, sizeof(host->led_name),
2769                 "%s::", mmc_hostname(mmc));
2770         host->led.name = host->led_name;
2771         host->led.brightness = LED_OFF;
2772         host->led.default_trigger = mmc_hostname(mmc);
2773         host->led.brightness_set = sdhci_led_control;
2774
2775         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2776         if (ret)
2777                 goto reset;
2778 #endif
2779
2780         mmiowb();
2781
2782         mmc_add_host(mmc);
2783
2784         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2785                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2786                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2787                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2788
2789         sdhci_enable_card_detection(host);
2790
2791         return 0;
2792
2793 #ifdef SDHCI_USE_LEDS_CLASS
2794 reset:
2795         sdhci_reset(host, SDHCI_RESET_ALL);
2796         free_irq(host->irq, host);
2797 #endif
2798 untasklet:
2799         tasklet_kill(&host->card_tasklet);
2800         tasklet_kill(&host->finish_tasklet);
2801
2802         return ret;
2803 }
2804
2805 EXPORT_SYMBOL_GPL(sdhci_add_host);
2806
2807 void sdhci_remove_host(struct sdhci_host *host, int dead)
2808 {
2809         unsigned long flags;
2810
2811         if (dead) {
2812                 spin_lock_irqsave(&host->lock, flags);
2813
2814                 host->flags |= SDHCI_DEVICE_DEAD;
2815
2816                 if (host->mrq) {
2817                         printk(KERN_ERR "%s: Controller removed during "
2818                                 " transfer!\n", mmc_hostname(host->mmc));
2819
2820                         host->mrq->cmd->error = -ENOMEDIUM;
2821                         tasklet_schedule(&host->finish_tasklet);
2822                 }
2823
2824                 spin_unlock_irqrestore(&host->lock, flags);
2825         }
2826
2827         sdhci_disable_card_detection(host);
2828
2829         mmc_remove_host(host->mmc);
2830
2831 #ifdef SDHCI_USE_LEDS_CLASS
2832         led_classdev_unregister(&host->led);
2833 #endif
2834
2835         if (!dead)
2836                 sdhci_reset(host, SDHCI_RESET_ALL);
2837
2838         free_irq(host->irq, host);
2839
2840         del_timer_sync(&host->timer);
2841         if (host->version >= SDHCI_SPEC_300)
2842                 del_timer_sync(&host->tuning_timer);
2843
2844         tasklet_kill(&host->card_tasklet);
2845         tasklet_kill(&host->finish_tasklet);
2846
2847         if (host->vmmc) {
2848                 regulator_disable(host->vmmc);
2849                 regulator_put(host->vmmc);
2850         }
2851
2852         kfree(host->adma_desc);
2853         kfree(host->align_buffer);
2854
2855         host->adma_desc = NULL;
2856         host->align_buffer = NULL;
2857 }
2858
2859 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2860
2861 void sdhci_free_host(struct sdhci_host *host)
2862 {
2863         mmc_free_host(host->mmc);
2864 }
2865
2866 EXPORT_SYMBOL_GPL(sdhci_free_host);
2867
2868 /*****************************************************************************\
2869  *                                                                           *
2870  * Driver init/exit                                                          *
2871  *                                                                           *
2872 \*****************************************************************************/
2873
2874 static int __init sdhci_drv_init(void)
2875 {
2876         printk(KERN_INFO DRIVER_NAME
2877                 ": Secure Digital Host Controller Interface driver\n");
2878         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2879
2880         return 0;
2881 }
2882
2883 static void __exit sdhci_drv_exit(void)
2884 {
2885 }
2886
2887 module_init(sdhci_drv_init);
2888 module_exit(sdhci_drv_exit);
2889
2890 module_param(debug_quirks, uint, 0444);
2891
2892 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2893 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2894 MODULE_LICENSE("GPL");
2895
2896 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");