drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/highmem.h>
  14 #include <linux/pci.h>
  15 #include <linux/dma-mapping.h>
  16
  17 #include <linux/mmc/host.h>
  18
  19 #include <asm/scatterlist.h>
  20
  21 #include "sdhci.h"
  22
  23 #define DRIVER_NAME "sdhci"
  24
  25 #define DBG(f, x...) \
  26         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  27
  28 static unsigned int debug_nodma = 0;
  29 static unsigned int debug_forcedma = 0;
  30 static unsigned int debug_quirks = 0;
  31
  32 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
  33 #define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
  34 /* Controller doesn't like some resets when there is no card inserted. */
  35 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
  36 #define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
  37
  38 static const struct pci_device_id pci_ids[] __devinitdata = {
  39         {
  40                 .vendor         = PCI_VENDOR_ID_RICOH,
  41                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  42                 .subvendor      = PCI_VENDOR_ID_IBM,
  43                 .subdevice      = PCI_ANY_ID,
  44                 .driver_data    = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  45                                   SDHCI_QUIRK_FORCE_DMA,
  46         },
  47
  48         {
  49                 .vendor         = PCI_VENDOR_ID_RICOH,
  50                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  51                 .subvendor      = PCI_ANY_ID,
  52                 .subdevice      = PCI_ANY_ID,
  53                 .driver_data    = SDHCI_QUIRK_FORCE_DMA |
  54                                   SDHCI_QUIRK_NO_CARD_NO_RESET,
  55         },
  56
  57         {
  58                 .vendor         = PCI_VENDOR_ID_TI,
  59                 .device         = PCI_DEVICE_ID_TI_XX21_XX11_SD,
  60                 .subvendor      = PCI_ANY_ID,
  61                 .subdevice      = PCI_ANY_ID,
  62                 .driver_data    = SDHCI_QUIRK_FORCE_DMA,
  63         },
  64
  65         {
  66                 .vendor         = PCI_VENDOR_ID_ENE,
  67                 .device         = PCI_DEVICE_ID_ENE_CB712_SD,
  68                 .subvendor      = PCI_ANY_ID,
  69                 .subdevice      = PCI_ANY_ID,
  70                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE,
  71         },
  72
  73         {
  74                 .vendor         = PCI_VENDOR_ID_ENE,
  75                 .device         = PCI_DEVICE_ID_ENE_CB712_SD_2,
  76                 .subvendor      = PCI_ANY_ID,
  77                 .subdevice      = PCI_ANY_ID,
  78                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE,
  79         },
  80
  81         {       /* Generic SD host controller */
  82                 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
  83         },
  84
  85         { /* end: all zeroes */ },
  86 };
  87
  88 MODULE_DEVICE_TABLE(pci, pci_ids);
  89
  90 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  91 static void sdhci_finish_data(struct sdhci_host *);
  92
  93 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  94 static void sdhci_finish_command(struct sdhci_host *);
  95
  96 static void sdhci_dumpregs(struct sdhci_host *host)
  97 {
  98         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  99
 100         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
 101                 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
 102                 readw(host->ioaddr + SDHCI_HOST_VERSION));
 103         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
 104                 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
 105                 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
 106         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
 107                 readl(host->ioaddr + SDHCI_ARGUMENT),
 108                 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
 109         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 110                 readl(host->ioaddr + SDHCI_PRESENT_STATE),
 111                 readb(host->ioaddr + SDHCI_HOST_CONTROL));
 112         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 113                 readb(host->ioaddr + SDHCI_POWER_CONTROL),
 114                 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
 115         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 116                 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
 117                 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
 118         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 119                 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
 120                 readl(host->ioaddr + SDHCI_INT_STATUS));
 121         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 122                 readl(host->ioaddr + SDHCI_INT_ENABLE),
 123                 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
 124         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 125                 readw(host->ioaddr + SDHCI_ACMD12_ERR),
 126                 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
 127         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
 128                 readl(host->ioaddr + SDHCI_CAPABILITIES),
 129                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
 130
 131         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
 132 }
 133
 134 /*****************************************************************************\
 135  *                                                                           *
 136  * Low level functions                                                       *
 137  *                                                                           *
 138 \*****************************************************************************/
 139
 140 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 141 {
 142         unsigned long timeout;
 143
 144         if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 145                 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 146                         SDHCI_CARD_PRESENT))
 147                         return;
 148         }
 149
 150         writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
 151
 152         if (mask & SDHCI_RESET_ALL)
 153                 host->clock = 0;
 154
 155         /* Wait max 100 ms */
 156         timeout = 100;
 157
 158         /* hw clears the bit when it's done */
 159         while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
 160                 if (timeout == 0) {
 161                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 162                                 mmc_hostname(host->mmc), (int)mask);
 163                         sdhci_dumpregs(host);
 164                         return;
 165                 }
 166                 timeout--;
 167                 mdelay(1);
 168         }
 169 }
 170
 171 static void sdhci_init(struct sdhci_host *host)
 172 {
 173         u32 intmask;
 174
 175         sdhci_reset(host, SDHCI_RESET_ALL);
 176
 177         intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 178                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 179                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 180                 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
 181                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
 182                 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
 183
 184         writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
 185         writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 186 }
 187
 188 static void sdhci_activate_led(struct sdhci_host *host)
 189 {
 190         u8 ctrl;
 191
 192         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 193         ctrl |= SDHCI_CTRL_LED;
 194         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 195 }
 196
 197 static void sdhci_deactivate_led(struct sdhci_host *host)
 198 {
 199         u8 ctrl;
 200
 201         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 202         ctrl &= ~SDHCI_CTRL_LED;
 203         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 204 }
 205
 206 /*****************************************************************************\
 207  *                                                                           *
 208  * Core functions                                                            *
 209  *                                                                           *
 210 \*****************************************************************************/
 211
 212 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
 213 {
 214         return page_address(host->cur_sg->page) + host->cur_sg->offset;
 215 }
 216
 217 static inline int sdhci_next_sg(struct sdhci_host* host)
 218 {
 219         /*
 220          * Skip to next SG entry.
 221          */
 222         host->cur_sg++;
 223         host->num_sg--;
 224
 225         /*
 226          * Any entries left?
 227          */
 228         if (host->num_sg > 0) {
 229                 host->offset = 0;
 230                 host->remain = host->cur_sg->length;
 231         }
 232
 233         return host->num_sg;
 234 }
 235
 236 static void sdhci_read_block_pio(struct sdhci_host *host)
 237 {
 238         int blksize, chunk_remain;
 239         u32 data;
 240         char *buffer;
 241         int size;
 242
 243         DBG("PIO reading\n");
 244
 245         blksize = host->data->blksz;
 246         chunk_remain = 0;
 247         data = 0;
 248
 249         buffer = sdhci_sg_to_buffer(host) + host->offset;
 250
 251         while (blksize) {
 252                 if (chunk_remain == 0) {
 253                         data = readl(host->ioaddr + SDHCI_BUFFER);
 254                         chunk_remain = min(blksize, 4);
 255                 }
 256
 257                 size = min(host->remain, chunk_remain);
 258
 259                 chunk_remain -= size;
 260                 blksize -= size;
 261                 host->offset += size;
 262                 host->remain -= size;
 263
 264                 while (size) {
 265                         *buffer = data & 0xFF;
 266                         buffer++;
 267                         data >>= 8;
 268                         size--;
 269                 }
 270
 271                 if (host->remain == 0) {
 272                         if (sdhci_next_sg(host) == 0) {
 273                                 BUG_ON(blksize != 0);
 274                                 return;
 275                         }
 276                         buffer = sdhci_sg_to_buffer(host);
 277                 }
 278         }
 279 }
 280
 281 static void sdhci_write_block_pio(struct sdhci_host *host)
 282 {
 283         int blksize, chunk_remain;
 284         u32 data;
 285         char *buffer;
 286         int bytes, size;
 287
 288         DBG("PIO writing\n");
 289
 290         blksize = host->data->blksz;
 291         chunk_remain = 4;
 292         data = 0;
 293
 294         bytes = 0;
 295         buffer = sdhci_sg_to_buffer(host) + host->offset;
 296
 297         while (blksize) {
 298                 size = min(host->remain, chunk_remain);
 299
 300                 chunk_remain -= size;
 301                 blksize -= size;
 302                 host->offset += size;
 303                 host->remain -= size;
 304
 305                 while (size) {
 306                         data >>= 8;
 307                         data |= (u32)*buffer << 24;
 308                         buffer++;
 309                         size--;
 310                 }
 311
 312                 if (chunk_remain == 0) {
 313                         writel(data, host->ioaddr + SDHCI_BUFFER);
 314                         chunk_remain = min(blksize, 4);
 315                 }
 316
 317                 if (host->remain == 0) {
 318                         if (sdhci_next_sg(host) == 0) {
 319                                 BUG_ON(blksize != 0);
 320                                 return;
 321                         }
 322                         buffer = sdhci_sg_to_buffer(host);
 323                 }
 324         }
 325 }
 326
 327 static void sdhci_transfer_pio(struct sdhci_host *host)
 328 {
 329         u32 mask;
 330
 331         BUG_ON(!host->data);
 332
 333         if (host->num_sg == 0)
 334                 return;
 335
 336         if (host->data->flags & MMC_DATA_READ)
 337                 mask = SDHCI_DATA_AVAILABLE;
 338         else
 339                 mask = SDHCI_SPACE_AVAILABLE;
 340
 341         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 342                 if (host->data->flags & MMC_DATA_READ)
 343                         sdhci_read_block_pio(host);
 344                 else
 345                         sdhci_write_block_pio(host);
 346
 347                 if (host->num_sg == 0)
 348                         break;
 349         }
 350
 351         DBG("PIO transfer complete.\n");
 352 }
 353
 354 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 355 {
 356         u8 count;
 357         unsigned target_timeout, current_timeout;
 358
 359         WARN_ON(host->data);
 360
 361         if (data == NULL)
 362                 return;
 363
 364         DBG("blksz %04x blks %04x flags %08x\n",
 365                 data->blksz, data->blocks, data->flags);
 366         DBG("tsac %d ms nsac %d clk\n",
 367                 data->timeout_ns / 1000000, data->timeout_clks);
 368
 369         /* Sanity checks */
 370         BUG_ON(data->blksz * data->blocks > 524288);
 371         BUG_ON(data->blksz > host->mmc->max_blk_size);
 372         BUG_ON(data->blocks > 65535);
 373
 374         /* timeout in us */
 375         target_timeout = data->timeout_ns / 1000 +
 376                 data->timeout_clks / host->clock;
 377
 378         /*
 379          * Figure out needed cycles.
 380          * We do this in steps in order to fit inside a 32 bit int.
 381          * The first step is the minimum timeout, which will have a
 382          * minimum resolution of 6 bits:
 383          * (1) 2^13*1000 > 2^22,
 384          * (2) host->timeout_clk < 2^16
 385          *     =>
 386          *     (1) / (2) > 2^6
 387          */
 388         count = 0;
 389         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 390         while (current_timeout < target_timeout) {
 391                 count++;
 392                 current_timeout <<= 1;
 393                 if (count >= 0xF)
 394                         break;
 395         }
 396
 397         if (count >= 0xF) {
 398                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 399                         mmc_hostname(host->mmc));
 400                 count = 0xE;
 401         }
 402
 403         writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
 404
 405         if (host->flags & SDHCI_USE_DMA) {
 406                 int count;
 407
 408                 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
 409                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 410                 BUG_ON(count != 1);
 411
 412                 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
 413         } else {
 414                 host->cur_sg = data->sg;
 415                 host->num_sg = data->sg_len;
 416
 417                 host->offset = 0;
 418                 host->remain = host->cur_sg->length;
 419         }
 420
 421         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 422         writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
 423                 host->ioaddr + SDHCI_BLOCK_SIZE);
 424         writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
 425 }
 426
 427 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 428         struct mmc_data *data)
 429 {
 430         u16 mode;
 431
 432         WARN_ON(host->data);
 433
 434         if (data == NULL)
 435                 return;
 436
 437         mode = SDHCI_TRNS_BLK_CNT_EN;
 438         if (data->blocks > 1)
 439                 mode |= SDHCI_TRNS_MULTI;
 440         if (data->flags & MMC_DATA_READ)
 441                 mode |= SDHCI_TRNS_READ;
 442         if (host->flags & SDHCI_USE_DMA)
 443                 mode |= SDHCI_TRNS_DMA;
 444
 445         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
 446 }
 447
 448 static void sdhci_finish_data(struct sdhci_host *host)
 449 {
 450         struct mmc_data *data;
 451         u16 blocks;
 452
 453         BUG_ON(!host->data);
 454
 455         data = host->data;
 456         host->data = NULL;
 457
 458         if (host->flags & SDHCI_USE_DMA) {
 459                 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
 460                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 461         }
 462
 463         /*
 464          * Controller doesn't count down when in single block mode.
 465          */
 466         if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
 467                 blocks = 0;
 468         else
 469                 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
 470         data->bytes_xfered = data->blksz * (data->blocks - blocks);
 471
 472         if ((data->error == MMC_ERR_NONE) && blocks) {
 473                 printk(KERN_ERR "%s: Controller signalled completion even "
 474                         "though there were blocks left.\n",
 475                         mmc_hostname(host->mmc));
 476                 data->error = MMC_ERR_FAILED;
 477         }
 478
 479         DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
 480
 481         if (data->stop) {
 482                 /*
 483                  * The controller needs a reset of internal state machines
 484                  * upon error conditions.
 485                  */
 486                 if (data->error != MMC_ERR_NONE) {
 487                         sdhci_reset(host, SDHCI_RESET_CMD);
 488                         sdhci_reset(host, SDHCI_RESET_DATA);
 489                 }
 490
 491                 sdhci_send_command(host, data->stop);
 492         } else
 493                 tasklet_schedule(&host->finish_tasklet);
 494 }
 495
 496 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 497 {
 498         int flags;
 499         u32 mask;
 500         unsigned long timeout;
 501
 502         WARN_ON(host->cmd);
 503
 504         DBG("Sending cmd (%x)\n", cmd->opcode);
 505
 506         /* Wait max 10 ms */
 507         timeout = 10;
 508
 509         mask = SDHCI_CMD_INHIBIT;
 510         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 511                 mask |= SDHCI_DATA_INHIBIT;
 512
 513         /* We shouldn't wait for data inihibit for stop commands, even
 514            though they might use busy signaling */
 515         if (host->mrq->data && (cmd == host->mrq->data->stop))
 516                 mask &= ~SDHCI_DATA_INHIBIT;
 517
 518         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 519                 if (timeout == 0) {
 520                         printk(KERN_ERR "%s: Controller never released "
 521                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 522                         sdhci_dumpregs(host);
 523                         cmd->error = MMC_ERR_FAILED;
 524                         tasklet_schedule(&host->finish_tasklet);
 525                         return;
 526                 }
 527                 timeout--;
 528                 mdelay(1);
 529         }
 530
 531         mod_timer(&host->timer, jiffies + 10 * HZ);
 532
 533         host->cmd = cmd;
 534
 535         sdhci_prepare_data(host, cmd->data);
 536
 537         writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
 538
 539         sdhci_set_transfer_mode(host, cmd->data);
 540
 541         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 542                 printk(KERN_ERR "%s: Unsupported response type!\n",
 543                         mmc_hostname(host->mmc));
 544                 cmd->error = MMC_ERR_INVALID;
 545                 tasklet_schedule(&host->finish_tasklet);
 546                 return;
 547         }
 548
 549         if (!(cmd->flags & MMC_RSP_PRESENT))
 550                 flags = SDHCI_CMD_RESP_NONE;
 551         else if (cmd->flags & MMC_RSP_136)
 552                 flags = SDHCI_CMD_RESP_LONG;
 553         else if (cmd->flags & MMC_RSP_BUSY)
 554                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 555         else
 556                 flags = SDHCI_CMD_RESP_SHORT;
 557
 558         if (cmd->flags & MMC_RSP_CRC)
 559                 flags |= SDHCI_CMD_CRC;
 560         if (cmd->flags & MMC_RSP_OPCODE)
 561                 flags |= SDHCI_CMD_INDEX;
 562         if (cmd->data)
 563                 flags |= SDHCI_CMD_DATA;
 564
 565         writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
 566                 host->ioaddr + SDHCI_COMMAND);
 567 }
 568
 569 static void sdhci_finish_command(struct sdhci_host *host)
 570 {
 571         int i;
 572
 573         BUG_ON(host->cmd == NULL);
 574
 575         if (host->cmd->flags & MMC_RSP_PRESENT) {
 576                 if (host->cmd->flags & MMC_RSP_136) {
 577                         /* CRC is stripped so we need to do some shifting. */
 578                         for (i = 0;i < 4;i++) {
 579                                 host->cmd->resp[i] = readl(host->ioaddr +
 580                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 581                                 if (i != 3)
 582                                         host->cmd->resp[i] |=
 583                                                 readb(host->ioaddr +
 584                                                 SDHCI_RESPONSE + (3-i)*4-1);
 585                         }
 586                 } else {
 587                         host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
 588                 }
 589         }
 590
 591         host->cmd->error = MMC_ERR_NONE;
 592
 593         DBG("Ending cmd (%x)\n", host->cmd->opcode);
 594
 595         if (host->cmd->data)
 596                 host->data = host->cmd->data;
 597         else
 598                 tasklet_schedule(&host->finish_tasklet);
 599
 600         host->cmd = NULL;
 601 }
 602
 603 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 604 {
 605         int div;
 606         u16 clk;
 607         unsigned long timeout;
 608
 609         if (clock == host->clock)
 610                 return;
 611
 612         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
 613
 614         if (clock == 0)
 615                 goto out;
 616
 617         for (div = 1;div < 256;div *= 2) {
 618                 if ((host->max_clk / div) <= clock)
 619                         break;
 620         }
 621         div >>= 1;
 622
 623         clk = div << SDHCI_DIVIDER_SHIFT;
 624         clk |= SDHCI_CLOCK_INT_EN;
 625         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 626
 627         /* Wait max 10 ms */
 628         timeout = 10;
 629         while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
 630                 & SDHCI_CLOCK_INT_STABLE)) {
 631                 if (timeout == 0) {
 632                         printk(KERN_ERR "%s: Internal clock never "
 633                                 "stabilised.\n", mmc_hostname(host->mmc));
 634                         sdhci_dumpregs(host);
 635                         return;
 636                 }
 637                 timeout--;
 638                 mdelay(1);
 639         }
 640
 641         clk |= SDHCI_CLOCK_CARD_EN;
 642         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 643
 644 out:
 645         host->clock = clock;
 646 }
 647
 648 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 649 {
 650         u8 pwr;
 651
 652         if (host->power == power)
 653                 return;
 654
 655         if (power == (unsigned short)-1) {
 656                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 657                 goto out;
 658         }
 659
 660         /*
 661          * Spec says that we should clear the power reg before setting
 662          * a new value. Some controllers don't seem to like this though.
 663          */
 664         if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
 665                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 666
 667         pwr = SDHCI_POWER_ON;
 668
 669         switch (1 << power) {
 670         case MMC_VDD_165_195:
 671                 pwr |= SDHCI_POWER_180;
 672                 break;
 673         case MMC_VDD_29_30:
 674         case MMC_VDD_30_31:
 675                 pwr |= SDHCI_POWER_300;
 676                 break;
 677         case MMC_VDD_32_33:
 678         case MMC_VDD_33_34:
 679                 pwr |= SDHCI_POWER_330;
 680                 break;
 681         default:
 682                 BUG();
 683         }
 684
 685         writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
 686
 687 out:
 688         host->power = power;
 689 }
 690
 691 /*****************************************************************************\
 692  *                                                                           *
 693  * MMC callbacks                                                             *
 694  *                                                                           *
 695 \*****************************************************************************/
 696
 697 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 698 {
 699         struct sdhci_host *host;
 700         unsigned long flags;
 701
 702         host = mmc_priv(mmc);
 703
 704         spin_lock_irqsave(&host->lock, flags);
 705
 706         WARN_ON(host->mrq != NULL);
 707
 708         sdhci_activate_led(host);
 709
 710         host->mrq = mrq;
 711
 712         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 713                 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
 714                 tasklet_schedule(&host->finish_tasklet);
 715         } else
 716                 sdhci_send_command(host, mrq->cmd);
 717
 718         mmiowb();
 719         spin_unlock_irqrestore(&host->lock, flags);
 720 }
 721
 722 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 723 {
 724         struct sdhci_host *host;
 725         unsigned long flags;
 726         u8 ctrl;
 727
 728         host = mmc_priv(mmc);
 729
 730         spin_lock_irqsave(&host->lock, flags);
 731
 732         /*
 733          * Reset the chip on each power off.
 734          * Should clear out any weird states.
 735          */
 736         if (ios->power_mode == MMC_POWER_OFF) {
 737                 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 738                 sdhci_init(host);
 739         }
 740
 741         sdhci_set_clock(host, ios->clock);
 742
 743         if (ios->power_mode == MMC_POWER_OFF)
 744                 sdhci_set_power(host, -1);
 745         else
 746                 sdhci_set_power(host, ios->vdd);
 747
 748         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 749
 750         if (ios->bus_width == MMC_BUS_WIDTH_4)
 751                 ctrl |= SDHCI_CTRL_4BITBUS;
 752         else
 753                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 754
 755         if (ios->timing == MMC_TIMING_SD_HS)
 756                 ctrl |= SDHCI_CTRL_HISPD;
 757         else
 758                 ctrl &= ~SDHCI_CTRL_HISPD;
 759
 760         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 761
 762         mmiowb();
 763         spin_unlock_irqrestore(&host->lock, flags);
 764 }
 765
 766 static int sdhci_get_ro(struct mmc_host *mmc)
 767 {
 768         struct sdhci_host *host;
 769         unsigned long flags;
 770         int present;
 771
 772         host = mmc_priv(mmc);
 773
 774         spin_lock_irqsave(&host->lock, flags);
 775
 776         present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
 777
 778         spin_unlock_irqrestore(&host->lock, flags);
 779
 780         return !(present & SDHCI_WRITE_PROTECT);
 781 }
 782
 783 static const struct mmc_host_ops sdhci_ops = {
 784         .request        = sdhci_request,
 785         .set_ios        = sdhci_set_ios,
 786         .get_ro         = sdhci_get_ro,
 787 };
 788
 789 /*****************************************************************************\
 790  *                                                                           *
 791  * Tasklets                                                                  *
 792  *                                                                           *
 793 \*****************************************************************************/
 794
 795 static void sdhci_tasklet_card(unsigned long param)
 796 {
 797         struct sdhci_host *host;
 798         unsigned long flags;
 799
 800         host = (struct sdhci_host*)param;
 801
 802         spin_lock_irqsave(&host->lock, flags);
 803
 804         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 805                 if (host->mrq) {
 806                         printk(KERN_ERR "%s: Card removed during transfer!\n",
 807                                 mmc_hostname(host->mmc));
 808                         printk(KERN_ERR "%s: Resetting controller.\n",
 809                                 mmc_hostname(host->mmc));
 810
 811                         sdhci_reset(host, SDHCI_RESET_CMD);
 812                         sdhci_reset(host, SDHCI_RESET_DATA);
 813
 814                         host->mrq->cmd->error = MMC_ERR_FAILED;
 815                         tasklet_schedule(&host->finish_tasklet);
 816                 }
 817         }
 818
 819         spin_unlock_irqrestore(&host->lock, flags);
 820
 821         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 822 }
 823
 824 static void sdhci_tasklet_finish(unsigned long param)
 825 {
 826         struct sdhci_host *host;
 827         unsigned long flags;
 828         struct mmc_request *mrq;
 829
 830         host = (struct sdhci_host*)param;
 831
 832         spin_lock_irqsave(&host->lock, flags);
 833
 834         del_timer(&host->timer);
 835
 836         mrq = host->mrq;
 837
 838         DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
 839
 840         /*
 841          * The controller needs a reset of internal state machines
 842          * upon error conditions.
 843          */
 844         if ((mrq->cmd->error != MMC_ERR_NONE) ||
 845                 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
 846                 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
 847
 848                 /* Some controllers need this kick or reset won't work here */
 849                 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
 850                         unsigned int clock;
 851
 852                         /* This is to force an update */
 853                         clock = host->clock;
 854                         host->clock = 0;
 855                         sdhci_set_clock(host, clock);
 856                 }
 857
 858                 /* Spec says we should do both at the same time, but Ricoh
 859                    controllers do not like that. */
 860                 sdhci_reset(host, SDHCI_RESET_CMD);
 861                 sdhci_reset(host, SDHCI_RESET_DATA);
 862         }
 863
 864         host->mrq = NULL;
 865         host->cmd = NULL;
 866         host->data = NULL;
 867
 868         sdhci_deactivate_led(host);
 869
 870         mmiowb();
 871         spin_unlock_irqrestore(&host->lock, flags);
 872
 873         mmc_request_done(host->mmc, mrq);
 874 }
 875
 876 static void sdhci_timeout_timer(unsigned long data)
 877 {
 878         struct sdhci_host *host;
 879         unsigned long flags;
 880
 881         host = (struct sdhci_host*)data;
 882
 883         spin_lock_irqsave(&host->lock, flags);
 884
 885         if (host->mrq) {
 886                 printk(KERN_ERR "%s: Timeout waiting for hardware "
 887                         "interrupt.\n", mmc_hostname(host->mmc));
 888                 sdhci_dumpregs(host);
 889
 890                 if (host->data) {
 891                         host->data->error = MMC_ERR_TIMEOUT;
 892                         sdhci_finish_data(host);
 893                 } else {
 894                         if (host->cmd)
 895                                 host->cmd->error = MMC_ERR_TIMEOUT;
 896                         else
 897                                 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
 898
 899                         tasklet_schedule(&host->finish_tasklet);
 900                 }
 901         }
 902
 903         mmiowb();
 904         spin_unlock_irqrestore(&host->lock, flags);
 905 }
 906
 907 /*****************************************************************************\
 908  *                                                                           *
 909  * Interrupt handling                                                        *
 910  *                                                                           *
 911 \*****************************************************************************/
 912
 913 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
 914 {
 915         BUG_ON(intmask == 0);
 916
 917         if (!host->cmd) {
 918                 printk(KERN_ERR "%s: Got command interrupt even though no "
 919                         "command operation was in progress.\n",
 920                         mmc_hostname(host->mmc));
 921                 sdhci_dumpregs(host);
 922                 return;
 923         }
 924
 925         if (intmask & SDHCI_INT_RESPONSE)
 926                 sdhci_finish_command(host);
 927         else {
 928                 if (intmask & SDHCI_INT_TIMEOUT)
 929                         host->cmd->error = MMC_ERR_TIMEOUT;
 930                 else if (intmask & SDHCI_INT_CRC)
 931                         host->cmd->error = MMC_ERR_BADCRC;
 932                 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
 933                         host->cmd->error = MMC_ERR_FAILED;
 934                 else
 935                         host->cmd->error = MMC_ERR_INVALID;
 936
 937                 tasklet_schedule(&host->finish_tasklet);
 938         }
 939 }
 940
 941 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
 942 {
 943         BUG_ON(intmask == 0);
 944
 945         if (!host->data) {
 946                 /*
 947                  * A data end interrupt is sent together with the response
 948                  * for the stop command.
 949                  */
 950                 if (intmask & SDHCI_INT_DATA_END)
 951                         return;
 952
 953                 printk(KERN_ERR "%s: Got data interrupt even though no "
 954                         "data operation was in progress.\n",
 955                         mmc_hostname(host->mmc));
 956                 sdhci_dumpregs(host);
 957
 958                 return;
 959         }
 960
 961         if (intmask & SDHCI_INT_DATA_TIMEOUT)
 962                 host->data->error = MMC_ERR_TIMEOUT;
 963         else if (intmask & SDHCI_INT_DATA_CRC)
 964                 host->data->error = MMC_ERR_BADCRC;
 965         else if (intmask & SDHCI_INT_DATA_END_BIT)
 966                 host->data->error = MMC_ERR_FAILED;
 967
 968         if (host->data->error != MMC_ERR_NONE)
 969                 sdhci_finish_data(host);
 970         else {
 971                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
 972                         sdhci_transfer_pio(host);
 973
 974                 /*
 975                  * We currently don't do anything fancy with DMA
 976                  * boundaries, but as we can't disable the feature
 977                  * we need to at least restart the transfer.
 978                  */
 979                 if (intmask & SDHCI_INT_DMA_END)
 980                         writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
 981                                 host->ioaddr + SDHCI_DMA_ADDRESS);
 982
 983                 if (intmask & SDHCI_INT_DATA_END)
 984                         sdhci_finish_data(host);
 985         }
 986 }
 987
 988 static irqreturn_t sdhci_irq(int irq, void *dev_id)
 989 {
 990         irqreturn_t result;
 991         struct sdhci_host* host = dev_id;
 992         u32 intmask;
 993
 994         spin_lock(&host->lock);
 995
 996         intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
 997
 998         if (!intmask || intmask == 0xffffffff) {
 999                 result = IRQ_NONE;
1000                 goto out;
1001         }
1002
1003         DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1004
1005         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1006                 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1007                         host->ioaddr + SDHCI_INT_STATUS);
1008                 tasklet_schedule(&host->card_tasklet);
1009         }
1010
1011         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1012
1013         if (intmask & SDHCI_INT_CMD_MASK) {
1014                 writel(intmask & SDHCI_INT_CMD_MASK,
1015                         host->ioaddr + SDHCI_INT_STATUS);
1016                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1017         }
1018
1019         if (intmask & SDHCI_INT_DATA_MASK) {
1020                 writel(intmask & SDHCI_INT_DATA_MASK,
1021                         host->ioaddr + SDHCI_INT_STATUS);
1022                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1023         }
1024
1025         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1026
1027         intmask &= ~SDHCI_INT_ERROR;
1028
1029         if (intmask & SDHCI_INT_BUS_POWER) {
1030                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1031                         mmc_hostname(host->mmc));
1032                 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1033         }
1034
1035         intmask &= ~SDHCI_INT_BUS_POWER;
1036
1037         if (intmask) {
1038                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1039                         mmc_hostname(host->mmc), intmask);
1040                 sdhci_dumpregs(host);
1041
1042                 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1043         }
1044
1045         result = IRQ_HANDLED;
1046
1047         mmiowb();
1048 out:
1049         spin_unlock(&host->lock);
1050
1051         return result;
1052 }
1053
1054 /*****************************************************************************\
1055  *                                                                           *
1056  * Suspend/resume                                                            *
1057  *                                                                           *
1058 \*****************************************************************************/
1059
1060 #ifdef CONFIG_PM
1061
1062 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1063 {
1064         struct sdhci_chip *chip;
1065         int i, ret;
1066
1067         chip = pci_get_drvdata(pdev);
1068         if (!chip)
1069                 return 0;
1070
1071         DBG("Suspending...\n");
1072
1073         for (i = 0;i < chip->num_slots;i++) {
1074                 if (!chip->hosts[i])
1075                         continue;
1076                 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1077                 if (ret) {
1078                         for (i--;i >= 0;i--)
1079                                 mmc_resume_host(chip->hosts[i]->mmc);
1080                         return ret;
1081                 }
1082         }
1083
1084         pci_save_state(pdev);
1085         pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1086
1087         for (i = 0;i < chip->num_slots;i++) {
1088                 if (!chip->hosts[i])
1089                         continue;
1090                 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1091         }
1092
1093         pci_disable_device(pdev);
1094         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1095
1096         return 0;
1097 }
1098
1099 static int sdhci_resume (struct pci_dev *pdev)
1100 {
1101         struct sdhci_chip *chip;
1102         int i, ret;
1103
1104         chip = pci_get_drvdata(pdev);
1105         if (!chip)
1106                 return 0;
1107
1108         DBG("Resuming...\n");
1109
1110         pci_set_power_state(pdev, PCI_D0);
1111         pci_restore_state(pdev);
1112         ret = pci_enable_device(pdev);
1113         if (ret)
1114                 return ret;
1115
1116         for (i = 0;i < chip->num_slots;i++) {
1117                 if (!chip->hosts[i])
1118                         continue;
1119                 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1120                         pci_set_master(pdev);
1121                 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1122                         IRQF_SHARED, chip->hosts[i]->slot_descr,
1123                         chip->hosts[i]);
1124                 if (ret)
1125                         return ret;
1126                 sdhci_init(chip->hosts[i]);
1127                 mmiowb();
1128                 ret = mmc_resume_host(chip->hosts[i]->mmc);
1129                 if (ret)
1130                         return ret;
1131         }
1132
1133         return 0;
1134 }
1135
1136 #else /* CONFIG_PM */
1137
1138 #define sdhci_suspend NULL
1139 #define sdhci_resume NULL
1140
1141 #endif /* CONFIG_PM */
1142
1143 /*****************************************************************************\
1144  *                                                                           *
1145  * Device probing/removal                                                    *
1146  *                                                                           *
1147 \*****************************************************************************/
1148
1149 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1150 {
1151         int ret;
1152         unsigned int version;
1153         struct sdhci_chip *chip;
1154         struct mmc_host *mmc;
1155         struct sdhci_host *host;
1156
1157         u8 first_bar;
1158         unsigned int caps;
1159
1160         chip = pci_get_drvdata(pdev);
1161         BUG_ON(!chip);
1162
1163         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1164         if (ret)
1165                 return ret;
1166
1167         first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1168
1169         if (first_bar > 5) {
1170                 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1171                 return -ENODEV;
1172         }
1173
1174         if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1175                 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1176                 return -ENODEV;
1177         }
1178
1179         if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1180                 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1181                         "You may experience problems.\n");
1182         }
1183
1184         if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1185                 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1186                 return -ENODEV;
1187         }
1188
1189         if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1190                 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1191                 return -ENODEV;
1192         }
1193
1194         mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1195         if (!mmc)
1196                 return -ENOMEM;
1197
1198         host = mmc_priv(mmc);
1199         host->mmc = mmc;
1200
1201         host->chip = chip;
1202         chip->hosts[slot] = host;
1203
1204         host->bar = first_bar + slot;
1205
1206         host->addr = pci_resource_start(pdev, host->bar);
1207         host->irq = pdev->irq;
1208
1209         DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1210
1211         snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1212
1213         ret = pci_request_region(pdev, host->bar, host->slot_descr);
1214         if (ret)
1215                 goto free;
1216
1217         host->ioaddr = ioremap_nocache(host->addr,
1218                 pci_resource_len(pdev, host->bar));
1219         if (!host->ioaddr) {
1220                 ret = -ENOMEM;
1221                 goto release;
1222         }
1223
1224         sdhci_reset(host, SDHCI_RESET_ALL);
1225
1226         version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1227         version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1228         if (version != 0) {
1229                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1230                         "You may experience problems.\n", host->slot_descr,
1231                         version);
1232         }
1233
1234         caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1235
1236         if (debug_nodma)
1237                 DBG("DMA forced off\n");
1238         else if (debug_forcedma) {
1239                 DBG("DMA forced on\n");
1240                 host->flags |= SDHCI_USE_DMA;
1241         } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1242                 host->flags |= SDHCI_USE_DMA;
1243         else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
1244                 DBG("Controller doesn't have DMA interface\n");
1245         else if (!(caps & SDHCI_CAN_DO_DMA))
1246                 DBG("Controller doesn't have DMA capability\n");
1247         else
1248                 host->flags |= SDHCI_USE_DMA;
1249
1250         if (host->flags & SDHCI_USE_DMA) {
1251                 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1252                         printk(KERN_WARNING "%s: No suitable DMA available. "
1253                                 "Falling back to PIO.\n", host->slot_descr);
1254                         host->flags &= ~SDHCI_USE_DMA;
1255                 }
1256         }
1257
1258         if (host->flags & SDHCI_USE_DMA)
1259                 pci_set_master(pdev);
1260         else /* XXX: Hack to get MMC layer to avoid highmem */
1261                 pdev->dma_mask = 0;
1262
1263         host->max_clk =
1264                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1265         if (host->max_clk == 0) {
1266                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1267                         "frequency.\n", host->slot_descr);
1268                 ret = -ENODEV;
1269                 goto unmap;
1270         }
1271         host->max_clk *= 1000000;
1272
1273         host->timeout_clk =
1274                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1275         if (host->timeout_clk == 0) {
1276                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1277                         "frequency.\n", host->slot_descr);
1278                 ret = -ENODEV;
1279                 goto unmap;
1280         }
1281         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1282                 host->timeout_clk *= 1000;
1283
1284         /*
1285          * Set host parameters.
1286          */
1287         mmc->ops = &sdhci_ops;
1288         mmc->f_min = host->max_clk / 256;
1289         mmc->f_max = host->max_clk;
1290         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1291
1292         if (caps & SDHCI_CAN_DO_HISPD)
1293                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1294
1295         mmc->ocr_avail = 0;
1296         if (caps & SDHCI_CAN_VDD_330)
1297                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1298         if (caps & SDHCI_CAN_VDD_300)
1299                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1300         if (caps & SDHCI_CAN_VDD_180)
1301                 mmc->ocr_avail |= MMC_VDD_165_195;
1302
1303         if (mmc->ocr_avail == 0) {
1304                 printk(KERN_ERR "%s: Hardware doesn't report any "
1305                         "support voltages.\n", host->slot_descr);
1306                 ret = -ENODEV;
1307                 goto unmap;
1308         }
1309
1310         spin_lock_init(&host->lock);
1311
1312         /*
1313          * Maximum number of segments. Hardware cannot do scatter lists.
1314          */
1315         if (host->flags & SDHCI_USE_DMA)
1316                 mmc->max_hw_segs = 1;
1317         else
1318                 mmc->max_hw_segs = 16;
1319         mmc->max_phys_segs = 16;
1320
1321         /*
1322          * Maximum number of sectors in one transfer. Limited by DMA boundary
1323          * size (512KiB).
1324          */
1325         mmc->max_req_size = 524288;
1326
1327         /*
1328          * Maximum segment size. Could be one segment with the maximum number
1329          * of bytes.
1330          */
1331         mmc->max_seg_size = mmc->max_req_size;
1332
1333         /*
1334          * Maximum block size. This varies from controller to controller and
1335          * is specified in the capabilities register.
1336          */
1337         mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1338         if (mmc->max_blk_size >= 3) {
1339                 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1340                         host->slot_descr);
1341                 ret = -ENODEV;
1342                 goto unmap;
1343         }
1344         mmc->max_blk_size = 512 << mmc->max_blk_size;
1345
1346         /*
1347          * Maximum block count.
1348          */
1349         mmc->max_blk_count = 65535;
1350
1351         /*
1352          * Init tasklets.
1353          */
1354         tasklet_init(&host->card_tasklet,
1355                 sdhci_tasklet_card, (unsigned long)host);
1356         tasklet_init(&host->finish_tasklet,
1357                 sdhci_tasklet_finish, (unsigned long)host);
1358
1359         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1360
1361         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1362                 host->slot_descr, host);
1363         if (ret)
1364                 goto untasklet;
1365
1366         sdhci_init(host);
1367
1368 #ifdef CONFIG_MMC_DEBUG
1369         sdhci_dumpregs(host);
1370 #endif
1371
1372         mmiowb();
1373
1374         mmc_add_host(mmc);
1375
1376         printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1377                 host->addr, host->irq,
1378                 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1379
1380         return 0;
1381
1382 untasklet:
1383         tasklet_kill(&host->card_tasklet);
1384         tasklet_kill(&host->finish_tasklet);
1385 unmap:
1386         iounmap(host->ioaddr);
1387 release:
1388         pci_release_region(pdev, host->bar);
1389 free:
1390         mmc_free_host(mmc);
1391
1392         return ret;
1393 }
1394
1395 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1396 {
1397         struct sdhci_chip *chip;
1398         struct mmc_host *mmc;
1399         struct sdhci_host *host;
1400
1401         chip = pci_get_drvdata(pdev);
1402         host = chip->hosts[slot];
1403         mmc = host->mmc;
1404
1405         chip->hosts[slot] = NULL;
1406
1407         mmc_remove_host(mmc);
1408
1409         sdhci_reset(host, SDHCI_RESET_ALL);
1410
1411         free_irq(host->irq, host);
1412
1413         del_timer_sync(&host->timer);
1414
1415         tasklet_kill(&host->card_tasklet);
1416         tasklet_kill(&host->finish_tasklet);
1417
1418         iounmap(host->ioaddr);
1419
1420         pci_release_region(pdev, host->bar);
1421
1422         mmc_free_host(mmc);
1423 }
1424
1425 static int __devinit sdhci_probe(struct pci_dev *pdev,
1426         const struct pci_device_id *ent)
1427 {
1428         int ret, i;
1429         u8 slots, rev;
1430         struct sdhci_chip *chip;
1431
1432         BUG_ON(pdev == NULL);
1433         BUG_ON(ent == NULL);
1434
1435         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1436
1437         printk(KERN_INFO DRIVER_NAME
1438                 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1439                 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1440                 (int)rev);
1441
1442         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1443         if (ret)
1444                 return ret;
1445
1446         slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1447         DBG("found %d slot(s)\n", slots);
1448         if (slots == 0)
1449                 return -ENODEV;
1450
1451         ret = pci_enable_device(pdev);
1452         if (ret)
1453                 return ret;
1454
1455         chip = kzalloc(sizeof(struct sdhci_chip) +
1456                 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1457         if (!chip) {
1458                 ret = -ENOMEM;
1459                 goto err;
1460         }
1461
1462         chip->pdev = pdev;
1463         chip->quirks = ent->driver_data;
1464
1465         if (debug_quirks)
1466                 chip->quirks = debug_quirks;
1467
1468         chip->num_slots = slots;
1469         pci_set_drvdata(pdev, chip);
1470
1471         for (i = 0;i < slots;i++) {
1472                 ret = sdhci_probe_slot(pdev, i);
1473                 if (ret) {
1474                         for (i--;i >= 0;i--)
1475                                 sdhci_remove_slot(pdev, i);
1476                         goto free;
1477                 }
1478         }
1479
1480         return 0;
1481
1482 free:
1483         pci_set_drvdata(pdev, NULL);
1484         kfree(chip);
1485
1486 err:
1487         pci_disable_device(pdev);
1488         return ret;
1489 }
1490
1491 static void __devexit sdhci_remove(struct pci_dev *pdev)
1492 {
1493         int i;
1494         struct sdhci_chip *chip;
1495
1496         chip = pci_get_drvdata(pdev);
1497
1498         if (chip) {
1499                 for (i = 0;i < chip->num_slots;i++)
1500                         sdhci_remove_slot(pdev, i);
1501
1502                 pci_set_drvdata(pdev, NULL);
1503
1504                 kfree(chip);
1505         }
1506
1507         pci_disable_device(pdev);
1508 }
1509
1510 static struct pci_driver sdhci_driver = {
1511         .name =         DRIVER_NAME,
1512         .id_table =     pci_ids,
1513         .probe =        sdhci_probe,
1514         .remove =       __devexit_p(sdhci_remove),
1515         .suspend =      sdhci_suspend,
1516         .resume =       sdhci_resume,
1517 };
1518
1519 /*****************************************************************************\
1520  *                                                                           *
1521  * Driver init/exit                                                          *
1522  *                                                                           *
1523 \*****************************************************************************/
1524
1525 static int __init sdhci_drv_init(void)
1526 {
1527         printk(KERN_INFO DRIVER_NAME
1528                 ": Secure Digital Host Controller Interface driver\n");
1529         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1530
1531         return pci_register_driver(&sdhci_driver);
1532 }
1533
1534 static void __exit sdhci_drv_exit(void)
1535 {
1536         DBG("Exiting\n");
1537
1538         pci_unregister_driver(&sdhci_driver);
1539 }
1540
1541 module_init(sdhci_drv_init);
1542 module_exit(sdhci_drv_exit);
1543
1544 module_param(debug_nodma, uint, 0444);
1545 module_param(debug_forcedma, uint, 0444);
1546 module_param(debug_quirks, uint, 0444);
1547
1548 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1549 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1550 MODULE_LICENSE("GPL");
1551
1552 MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1553 MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
1554 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");