1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
10 * Thanks to the following companies for their support:
12 * - JMicron (hardware and technical support)
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/scatterlist.h>
25 #include <linux/gpio.h>
26 #include <linux/sfi.h>
27 #include <linux/pm_runtime.h>
35 #define PCI_SDHCI_IFPIO 0x00
36 #define PCI_SDHCI_IFDMA 0x01
37 #define PCI_SDHCI_IFVENDOR 0x02
39 #define PCI_SLOT_INFO 0x40 /* 8 bits */
40 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
41 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
45 struct sdhci_pci_chip;
46 struct sdhci_pci_slot;
48 struct sdhci_pci_fixes {
51 int (*probe) (struct sdhci_pci_chip *);
53 int (*probe_slot) (struct sdhci_pci_slot *);
54 void (*remove_slot) (struct sdhci_pci_slot *, int);
56 int (*suspend) (struct sdhci_pci_chip *,
58 int (*resume) (struct sdhci_pci_chip *);
61 struct sdhci_pci_slot {
62 struct sdhci_pci_chip *chip;
63 struct sdhci_host *host;
71 struct sdhci_pci_chip {
75 const struct sdhci_pci_fixes *fixes;
77 int num_slots; /* Slots on controller */
78 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
82 /*****************************************************************************\
84 * Hardware specific quirk handling *
86 \*****************************************************************************/
88 static int ricoh_probe(struct sdhci_pci_chip *chip)
90 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
91 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
92 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
96 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
99 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
100 & SDHCI_TIMEOUT_CLK_MASK) |
102 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
103 & SDHCI_CLOCK_BASE_MASK) |
105 SDHCI_TIMEOUT_CLK_UNIT |
111 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
113 /* Apply a delay to allow controller to settle */
114 /* Otherwise it becomes confused if card state changed
120 static const struct sdhci_pci_fixes sdhci_ricoh = {
121 .probe = ricoh_probe,
122 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
123 SDHCI_QUIRK_FORCE_DMA |
124 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
127 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
128 .probe_slot = ricoh_mmc_probe_slot,
129 .resume = ricoh_mmc_resume,
130 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
131 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
132 SDHCI_QUIRK_NO_CARD_NO_RESET |
133 SDHCI_QUIRK_MISSING_CAPS
136 static const struct sdhci_pci_fixes sdhci_ene_712 = {
137 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
138 SDHCI_QUIRK_BROKEN_DMA,
141 static const struct sdhci_pci_fixes sdhci_ene_714 = {
142 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
143 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
144 SDHCI_QUIRK_BROKEN_DMA,
147 static const struct sdhci_pci_fixes sdhci_cafe = {
148 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
149 SDHCI_QUIRK_NO_BUSY_IRQ |
150 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
153 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
155 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
160 * ADMA operation is disabled for Moorestown platform due to
163 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
166 * slots number is fixed here for MRST as SDIO3/5 are never used and
167 * have hardware bugs.
173 /* Medfield eMMC hardware reset GPIOs */
174 static int mfd_emmc0_rst_gpio = -EINVAL;
175 static int mfd_emmc1_rst_gpio = -EINVAL;
177 static int mfd_emmc_gpio_parse(struct sfi_table_header *table)
179 struct sfi_table_simple *sb = (struct sfi_table_simple *)table;
180 struct sfi_gpio_table_entry *entry;
183 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
184 entry = (struct sfi_gpio_table_entry *)sb->pentry;
186 for (i = 0; i < num; i++, entry++) {
187 if (!strncmp(entry->pin_name, "emmc0_rst", SFI_NAME_LEN))
188 mfd_emmc0_rst_gpio = entry->pin_no;
189 else if (!strncmp(entry->pin_name, "emmc1_rst", SFI_NAME_LEN))
190 mfd_emmc1_rst_gpio = entry->pin_no;
196 #ifdef CONFIG_PM_RUNTIME
198 static irqreturn_t mfd_sd_cd(int irq, void *dev_id)
200 struct sdhci_pci_slot *slot = dev_id;
201 struct sdhci_host *host = slot->host;
203 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
207 #define MFLD_SD_CD_PIN 69
209 static int mfd_sd_probe_slot(struct sdhci_pci_slot *slot)
211 int err, irq, gpio = MFLD_SD_CD_PIN;
213 slot->cd_gpio = -EINVAL;
214 slot->cd_irq = -EINVAL;
216 err = gpio_request(gpio, "sd_cd");
220 err = gpio_direction_input(gpio);
224 irq = gpio_to_irq(gpio);
228 err = request_irq(irq, mfd_sd_cd, IRQF_TRIGGER_RISING |
229 IRQF_TRIGGER_FALLING, "sd_cd", slot);
233 slot->cd_gpio = gpio;
235 slot->host->quirks2 |= SDHCI_QUIRK2_OWN_CARD_DETECTION;
242 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
246 static void mfd_sd_remove_slot(struct sdhci_pci_slot *slot, int dead)
248 if (slot->cd_irq >= 0)
249 free_irq(slot->cd_irq, slot);
250 gpio_free(slot->cd_gpio);
255 #define mfd_sd_probe_slot NULL
256 #define mfd_sd_remove_slot NULL
260 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
262 const char *name = NULL;
265 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, mfd_emmc_gpio_parse);
267 switch (slot->chip->pdev->device) {
268 case PCI_DEVICE_ID_INTEL_MFD_EMMC0:
269 gpio = mfd_emmc0_rst_gpio;
270 name = "eMMC0_reset";
272 case PCI_DEVICE_ID_INTEL_MFD_EMMC1:
273 gpio = mfd_emmc1_rst_gpio;
274 name = "eMMC1_reset";
278 if (!gpio_request(gpio, name)) {
279 gpio_direction_output(gpio, 1);
280 slot->rst_n_gpio = gpio;
281 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
284 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
286 slot->host->mmc->caps2 = MMC_CAP2_BOOTPART_NOACC;
291 static void mfd_emmc_remove_slot(struct sdhci_pci_slot *slot, int dead)
293 gpio_free(slot->rst_n_gpio);
296 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
297 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
298 .probe_slot = mrst_hc_probe_slot,
301 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
302 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
303 .probe = mrst_hc_probe,
306 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
307 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
308 .probe_slot = mfd_sd_probe_slot,
309 .remove_slot = mfd_sd_remove_slot,
312 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
313 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
316 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
317 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
318 .probe_slot = mfd_emmc_probe_slot,
319 .remove_slot = mfd_emmc_remove_slot,
322 /* O2Micro extra registers */
323 #define O2_SD_LOCK_WP 0xD3
324 #define O2_SD_MULTI_VCC3V 0xEE
325 #define O2_SD_CLKREQ 0xEC
326 #define O2_SD_CAPS 0xE0
327 #define O2_SD_ADMA1 0xE2
328 #define O2_SD_ADMA2 0xE7
329 #define O2_SD_INF_MOD 0xF1
331 static int o2_probe(struct sdhci_pci_chip *chip)
336 switch (chip->pdev->device) {
337 case PCI_DEVICE_ID_O2_8220:
338 case PCI_DEVICE_ID_O2_8221:
339 case PCI_DEVICE_ID_O2_8320:
340 case PCI_DEVICE_ID_O2_8321:
341 /* This extra setup is required due to broken ADMA. */
342 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
346 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
348 /* Set Multi 3 to VCC3V# */
349 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
351 /* Disable CLK_REQ# support after media DET */
352 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
356 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
358 /* Choose capabilities, enable SDMA. We have to write 0x01
359 * to the capabilities register first to unlock it.
361 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
365 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
366 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
368 /* Disable ADMA1/2 */
369 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
370 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
372 /* Disable the infinite transfer mode */
373 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
377 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
380 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
384 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
390 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
395 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
400 * Turn PMOS on [bit 0], set over current detection to 2.4 V
401 * [bit 1:2] and enable over current debouncing [bit 6].
408 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
415 static int jmicron_probe(struct sdhci_pci_chip *chip)
420 if (chip->pdev->revision == 0) {
421 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
422 SDHCI_QUIRK_32BIT_DMA_SIZE |
423 SDHCI_QUIRK_32BIT_ADMA_SIZE |
424 SDHCI_QUIRK_RESET_AFTER_REQUEST |
425 SDHCI_QUIRK_BROKEN_SMALL_PIO;
429 * JMicron chips can have two interfaces to the same hardware
430 * in order to work around limitations in Microsoft's driver.
431 * We need to make sure we only bind to one of them.
433 * This code assumes two things:
435 * 1. The PCI code adds subfunctions in order.
437 * 2. The MMC interface has a lower subfunction number
438 * than the SD interface.
440 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
441 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
442 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
443 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
446 struct pci_dev *sd_dev;
449 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
450 mmcdev, sd_dev)) != NULL) {
451 if ((PCI_SLOT(chip->pdev->devfn) ==
452 PCI_SLOT(sd_dev->devfn)) &&
453 (chip->pdev->bus == sd_dev->bus))
459 dev_info(&chip->pdev->dev, "Refusing to bind to "
460 "secondary interface.\n");
466 * JMicron chips need a bit of a nudge to enable the power
469 ret = jmicron_pmos(chip, 1);
471 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
475 /* quirk for unsable RO-detection on JM388 chips */
476 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
477 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
478 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
483 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
487 scratch = readb(host->ioaddr + 0xC0);
494 writeb(scratch, host->ioaddr + 0xC0);
497 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
499 if (slot->chip->pdev->revision == 0) {
502 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
503 version = (version & SDHCI_VENDOR_VER_MASK) >>
504 SDHCI_VENDOR_VER_SHIFT;
507 * Older versions of the chip have lots of nasty glitches
508 * in the ADMA engine. It's best just to avoid it
512 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
515 /* JM388 MMC doesn't support 1.8V while SD supports it */
516 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
517 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
518 MMC_VDD_29_30 | MMC_VDD_30_31 |
519 MMC_VDD_165_195; /* allow 1.8V */
520 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
521 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
525 * The secondary interface requires a bit set to get the
528 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
529 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
530 jmicron_enable_mmc(slot->host, 1);
532 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
537 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
542 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
543 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
544 jmicron_enable_mmc(slot->host, 0);
547 static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
551 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
552 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
553 for (i = 0; i < chip->num_slots; i++)
554 jmicron_enable_mmc(chip->slots[i]->host, 0);
560 static int jmicron_resume(struct sdhci_pci_chip *chip)
564 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
565 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
566 for (i = 0; i < chip->num_slots; i++)
567 jmicron_enable_mmc(chip->slots[i]->host, 1);
570 ret = jmicron_pmos(chip, 1);
572 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
579 static const struct sdhci_pci_fixes sdhci_o2 = {
583 static const struct sdhci_pci_fixes sdhci_jmicron = {
584 .probe = jmicron_probe,
586 .probe_slot = jmicron_probe_slot,
587 .remove_slot = jmicron_remove_slot,
589 .suspend = jmicron_suspend,
590 .resume = jmicron_resume,
593 /* SysKonnect CardBus2SDIO extra registers */
594 #define SYSKT_CTRL 0x200
595 #define SYSKT_RDFIFO_STAT 0x204
596 #define SYSKT_WRFIFO_STAT 0x208
597 #define SYSKT_POWER_DATA 0x20c
598 #define SYSKT_POWER_330 0xef
599 #define SYSKT_POWER_300 0xf8
600 #define SYSKT_POWER_184 0xcc
601 #define SYSKT_POWER_CMD 0x20d
602 #define SYSKT_POWER_START (1 << 7)
603 #define SYSKT_POWER_STATUS 0x20e
604 #define SYSKT_POWER_STATUS_OK (1 << 0)
605 #define SYSKT_BOARD_REV 0x210
606 #define SYSKT_CHIP_REV 0x211
607 #define SYSKT_CONF_DATA 0x212
608 #define SYSKT_CONF_DATA_1V8 (1 << 2)
609 #define SYSKT_CONF_DATA_2V5 (1 << 1)
610 #define SYSKT_CONF_DATA_3V3 (1 << 0)
612 static int syskt_probe(struct sdhci_pci_chip *chip)
614 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
615 chip->pdev->class &= ~0x0000FF;
616 chip->pdev->class |= PCI_SDHCI_IFDMA;
621 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
625 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
626 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
627 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
628 "board rev %d.%d, chip rev %d.%d\n",
629 board_rev >> 4, board_rev & 0xf,
630 chip_rev >> 4, chip_rev & 0xf);
631 if (chip_rev >= 0x20)
632 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
634 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
635 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
637 tm = 10; /* Wait max 1 ms */
639 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
640 if (ps & SYSKT_POWER_STATUS_OK)
645 dev_err(&slot->chip->pdev->dev,
646 "power regulator never stabilized");
647 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
654 static const struct sdhci_pci_fixes sdhci_syskt = {
655 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
656 .probe = syskt_probe,
657 .probe_slot = syskt_probe_slot,
660 static int via_probe(struct sdhci_pci_chip *chip)
662 if (chip->pdev->revision == 0x10)
663 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
668 static const struct sdhci_pci_fixes sdhci_via = {
672 static const struct pci_device_id pci_ids[] __devinitdata = {
674 .vendor = PCI_VENDOR_ID_RICOH,
675 .device = PCI_DEVICE_ID_RICOH_R5C822,
676 .subvendor = PCI_ANY_ID,
677 .subdevice = PCI_ANY_ID,
678 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
682 .vendor = PCI_VENDOR_ID_RICOH,
684 .subvendor = PCI_ANY_ID,
685 .subdevice = PCI_ANY_ID,
686 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
690 .vendor = PCI_VENDOR_ID_RICOH,
692 .subvendor = PCI_ANY_ID,
693 .subdevice = PCI_ANY_ID,
694 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
698 .vendor = PCI_VENDOR_ID_RICOH,
700 .subvendor = PCI_ANY_ID,
701 .subdevice = PCI_ANY_ID,
702 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
706 .vendor = PCI_VENDOR_ID_ENE,
707 .device = PCI_DEVICE_ID_ENE_CB712_SD,
708 .subvendor = PCI_ANY_ID,
709 .subdevice = PCI_ANY_ID,
710 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
714 .vendor = PCI_VENDOR_ID_ENE,
715 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
716 .subvendor = PCI_ANY_ID,
717 .subdevice = PCI_ANY_ID,
718 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
722 .vendor = PCI_VENDOR_ID_ENE,
723 .device = PCI_DEVICE_ID_ENE_CB714_SD,
724 .subvendor = PCI_ANY_ID,
725 .subdevice = PCI_ANY_ID,
726 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
730 .vendor = PCI_VENDOR_ID_ENE,
731 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
732 .subvendor = PCI_ANY_ID,
733 .subdevice = PCI_ANY_ID,
734 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
738 .vendor = PCI_VENDOR_ID_MARVELL,
739 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
740 .subvendor = PCI_ANY_ID,
741 .subdevice = PCI_ANY_ID,
742 .driver_data = (kernel_ulong_t)&sdhci_cafe,
746 .vendor = PCI_VENDOR_ID_JMICRON,
747 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
748 .subvendor = PCI_ANY_ID,
749 .subdevice = PCI_ANY_ID,
750 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
754 .vendor = PCI_VENDOR_ID_JMICRON,
755 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
756 .subvendor = PCI_ANY_ID,
757 .subdevice = PCI_ANY_ID,
758 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
762 .vendor = PCI_VENDOR_ID_JMICRON,
763 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
764 .subvendor = PCI_ANY_ID,
765 .subdevice = PCI_ANY_ID,
766 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
770 .vendor = PCI_VENDOR_ID_JMICRON,
771 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
772 .subvendor = PCI_ANY_ID,
773 .subdevice = PCI_ANY_ID,
774 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
778 .vendor = PCI_VENDOR_ID_SYSKONNECT,
780 .subvendor = PCI_ANY_ID,
781 .subdevice = PCI_ANY_ID,
782 .driver_data = (kernel_ulong_t)&sdhci_syskt,
786 .vendor = PCI_VENDOR_ID_VIA,
788 .subvendor = PCI_ANY_ID,
789 .subdevice = PCI_ANY_ID,
790 .driver_data = (kernel_ulong_t)&sdhci_via,
794 .vendor = PCI_VENDOR_ID_INTEL,
795 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
796 .subvendor = PCI_ANY_ID,
797 .subdevice = PCI_ANY_ID,
798 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
802 .vendor = PCI_VENDOR_ID_INTEL,
803 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
804 .subvendor = PCI_ANY_ID,
805 .subdevice = PCI_ANY_ID,
806 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
810 .vendor = PCI_VENDOR_ID_INTEL,
811 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
812 .subvendor = PCI_ANY_ID,
813 .subdevice = PCI_ANY_ID,
814 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
818 .vendor = PCI_VENDOR_ID_INTEL,
819 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
820 .subvendor = PCI_ANY_ID,
821 .subdevice = PCI_ANY_ID,
822 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
826 .vendor = PCI_VENDOR_ID_INTEL,
827 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
828 .subvendor = PCI_ANY_ID,
829 .subdevice = PCI_ANY_ID,
830 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
834 .vendor = PCI_VENDOR_ID_INTEL,
835 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
836 .subvendor = PCI_ANY_ID,
837 .subdevice = PCI_ANY_ID,
838 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
842 .vendor = PCI_VENDOR_ID_INTEL,
843 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
844 .subvendor = PCI_ANY_ID,
845 .subdevice = PCI_ANY_ID,
846 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
850 .vendor = PCI_VENDOR_ID_INTEL,
851 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
852 .subvendor = PCI_ANY_ID,
853 .subdevice = PCI_ANY_ID,
854 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
858 .vendor = PCI_VENDOR_ID_O2,
859 .device = PCI_DEVICE_ID_O2_8120,
860 .subvendor = PCI_ANY_ID,
861 .subdevice = PCI_ANY_ID,
862 .driver_data = (kernel_ulong_t)&sdhci_o2,
866 .vendor = PCI_VENDOR_ID_O2,
867 .device = PCI_DEVICE_ID_O2_8220,
868 .subvendor = PCI_ANY_ID,
869 .subdevice = PCI_ANY_ID,
870 .driver_data = (kernel_ulong_t)&sdhci_o2,
874 .vendor = PCI_VENDOR_ID_O2,
875 .device = PCI_DEVICE_ID_O2_8221,
876 .subvendor = PCI_ANY_ID,
877 .subdevice = PCI_ANY_ID,
878 .driver_data = (kernel_ulong_t)&sdhci_o2,
882 .vendor = PCI_VENDOR_ID_O2,
883 .device = PCI_DEVICE_ID_O2_8320,
884 .subvendor = PCI_ANY_ID,
885 .subdevice = PCI_ANY_ID,
886 .driver_data = (kernel_ulong_t)&sdhci_o2,
890 .vendor = PCI_VENDOR_ID_O2,
891 .device = PCI_DEVICE_ID_O2_8321,
892 .subvendor = PCI_ANY_ID,
893 .subdevice = PCI_ANY_ID,
894 .driver_data = (kernel_ulong_t)&sdhci_o2,
897 { /* Generic SD host controller */
898 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
901 { /* end: all zeroes */ },
904 MODULE_DEVICE_TABLE(pci, pci_ids);
906 /*****************************************************************************\
908 * SDHCI core callbacks *
910 \*****************************************************************************/
912 static int sdhci_pci_enable_dma(struct sdhci_host *host)
914 struct sdhci_pci_slot *slot;
915 struct pci_dev *pdev;
918 slot = sdhci_priv(host);
919 pdev = slot->chip->pdev;
921 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
922 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
923 (host->flags & SDHCI_USE_SDMA)) {
924 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
925 "doesn't fully claim to support it.\n");
928 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
932 pci_set_master(pdev);
937 static int sdhci_pci_8bit_width(struct sdhci_host *host, int width)
941 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
944 case MMC_BUS_WIDTH_8:
945 ctrl |= SDHCI_CTRL_8BITBUS;
946 ctrl &= ~SDHCI_CTRL_4BITBUS;
948 case MMC_BUS_WIDTH_4:
949 ctrl |= SDHCI_CTRL_4BITBUS;
950 ctrl &= ~SDHCI_CTRL_8BITBUS;
953 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
957 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
962 static void sdhci_pci_hw_reset(struct sdhci_host *host)
964 struct sdhci_pci_slot *slot = sdhci_priv(host);
965 int rst_n_gpio = slot->rst_n_gpio;
967 if (!gpio_is_valid(rst_n_gpio))
969 gpio_set_value_cansleep(rst_n_gpio, 0);
970 /* For eMMC, minimum is 1us but give it 10us for good measure */
972 gpio_set_value_cansleep(rst_n_gpio, 1);
973 /* For eMMC, minimum is 200us but give it 300us for good measure */
974 usleep_range(300, 1000);
977 static struct sdhci_ops sdhci_pci_ops = {
978 .enable_dma = sdhci_pci_enable_dma,
979 .platform_8bit_width = sdhci_pci_8bit_width,
980 .hw_reset = sdhci_pci_hw_reset,
983 /*****************************************************************************\
987 \*****************************************************************************/
991 static int sdhci_pci_suspend(struct pci_dev *pdev, pm_message_t state)
993 struct sdhci_pci_chip *chip;
994 struct sdhci_pci_slot *slot;
995 mmc_pm_flag_t slot_pm_flags;
996 mmc_pm_flag_t pm_flags = 0;
999 chip = pci_get_drvdata(pdev);
1003 for (i = 0; i < chip->num_slots; i++) {
1004 slot = chip->slots[i];
1008 ret = sdhci_suspend_host(slot->host, state);
1011 for (i--; i >= 0; i--)
1012 sdhci_resume_host(chip->slots[i]->host);
1016 slot_pm_flags = slot->host->mmc->pm_flags;
1017 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1018 sdhci_enable_irq_wakeups(slot->host);
1020 pm_flags |= slot_pm_flags;
1023 if (chip->fixes && chip->fixes->suspend) {
1024 ret = chip->fixes->suspend(chip, state);
1026 for (i = chip->num_slots - 1; i >= 0; i--)
1027 sdhci_resume_host(chip->slots[i]->host);
1032 pci_save_state(pdev);
1033 if (pm_flags & MMC_PM_KEEP_POWER) {
1034 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
1035 pci_pme_active(pdev, true);
1036 pci_enable_wake(pdev, PCI_D3hot, 1);
1038 pci_set_power_state(pdev, PCI_D3hot);
1040 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1041 pci_disable_device(pdev);
1042 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1048 static int sdhci_pci_resume(struct pci_dev *pdev)
1050 struct sdhci_pci_chip *chip;
1051 struct sdhci_pci_slot *slot;
1054 chip = pci_get_drvdata(pdev);
1058 pci_set_power_state(pdev, PCI_D0);
1059 pci_restore_state(pdev);
1060 ret = pci_enable_device(pdev);
1064 if (chip->fixes && chip->fixes->resume) {
1065 ret = chip->fixes->resume(chip);
1070 for (i = 0; i < chip->num_slots; i++) {
1071 slot = chip->slots[i];
1075 ret = sdhci_resume_host(slot->host);
1083 #else /* CONFIG_PM */
1085 #define sdhci_pci_suspend NULL
1086 #define sdhci_pci_resume NULL
1088 #endif /* CONFIG_PM */
1090 #ifdef CONFIG_PM_RUNTIME
1092 static int sdhci_pci_runtime_suspend(struct device *dev)
1094 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1095 struct sdhci_pci_chip *chip;
1096 struct sdhci_pci_slot *slot;
1097 pm_message_t state = { .event = PM_EVENT_SUSPEND };
1100 chip = pci_get_drvdata(pdev);
1104 for (i = 0; i < chip->num_slots; i++) {
1105 slot = chip->slots[i];
1109 ret = sdhci_runtime_suspend_host(slot->host);
1112 for (i--; i >= 0; i--)
1113 sdhci_runtime_resume_host(chip->slots[i]->host);
1118 if (chip->fixes && chip->fixes->suspend) {
1119 ret = chip->fixes->suspend(chip, state);
1121 for (i = chip->num_slots - 1; i >= 0; i--)
1122 sdhci_runtime_resume_host(chip->slots[i]->host);
1130 static int sdhci_pci_runtime_resume(struct device *dev)
1132 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1133 struct sdhci_pci_chip *chip;
1134 struct sdhci_pci_slot *slot;
1137 chip = pci_get_drvdata(pdev);
1141 if (chip->fixes && chip->fixes->resume) {
1142 ret = chip->fixes->resume(chip);
1147 for (i = 0; i < chip->num_slots; i++) {
1148 slot = chip->slots[i];
1152 ret = sdhci_runtime_resume_host(slot->host);
1160 static int sdhci_pci_runtime_idle(struct device *dev)
1167 #define sdhci_pci_runtime_suspend NULL
1168 #define sdhci_pci_runtime_resume NULL
1169 #define sdhci_pci_runtime_idle NULL
1173 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1174 .runtime_suspend = sdhci_pci_runtime_suspend,
1175 .runtime_resume = sdhci_pci_runtime_resume,
1176 .runtime_idle = sdhci_pci_runtime_idle,
1179 /*****************************************************************************\
1181 * Device probing/removal *
1183 \*****************************************************************************/
1185 static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
1186 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
1188 struct sdhci_pci_slot *slot;
1189 struct sdhci_host *host;
1192 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1193 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1194 return ERR_PTR(-ENODEV);
1197 if (pci_resource_len(pdev, bar) != 0x100) {
1198 dev_err(&pdev->dev, "Invalid iomem size. You may "
1199 "experience problems.\n");
1202 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1203 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1204 return ERR_PTR(-ENODEV);
1207 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1208 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1209 return ERR_PTR(-ENODEV);
1212 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1214 dev_err(&pdev->dev, "cannot allocate host\n");
1215 return ERR_CAST(host);
1218 slot = sdhci_priv(host);
1222 slot->pci_bar = bar;
1223 slot->rst_n_gpio = -EINVAL;
1225 host->hw_name = "PCI";
1226 host->ops = &sdhci_pci_ops;
1227 host->quirks = chip->quirks;
1229 host->irq = pdev->irq;
1231 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1233 dev_err(&pdev->dev, "cannot request region\n");
1237 host->ioaddr = pci_ioremap_bar(pdev, bar);
1238 if (!host->ioaddr) {
1239 dev_err(&pdev->dev, "failed to remap registers\n");
1244 if (chip->fixes && chip->fixes->probe_slot) {
1245 ret = chip->fixes->probe_slot(slot);
1250 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1252 ret = sdhci_add_host(host);
1259 if (chip->fixes && chip->fixes->remove_slot)
1260 chip->fixes->remove_slot(slot, 0);
1263 iounmap(host->ioaddr);
1266 pci_release_region(pdev, bar);
1269 sdhci_free_host(host);
1271 return ERR_PTR(ret);
1274 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1280 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1281 if (scratch == (u32)-1)
1284 sdhci_remove_host(slot->host, dead);
1286 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1287 slot->chip->fixes->remove_slot(slot, dead);
1289 pci_release_region(slot->chip->pdev, slot->pci_bar);
1291 sdhci_free_host(slot->host);
1294 static void __devinit sdhci_pci_runtime_pm_allow(struct device *dev)
1296 pm_runtime_put_noidle(dev);
1297 pm_runtime_allow(dev);
1298 pm_runtime_set_autosuspend_delay(dev, 50);
1299 pm_runtime_use_autosuspend(dev);
1300 pm_suspend_ignore_children(dev, 1);
1303 static void __devexit sdhci_pci_runtime_pm_forbid(struct device *dev)
1305 pm_runtime_forbid(dev);
1306 pm_runtime_get_noresume(dev);
1309 static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
1310 const struct pci_device_id *ent)
1312 struct sdhci_pci_chip *chip;
1313 struct sdhci_pci_slot *slot;
1315 u8 slots, first_bar;
1318 BUG_ON(pdev == NULL);
1319 BUG_ON(ent == NULL);
1321 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1322 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1324 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1328 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1329 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1333 BUG_ON(slots > MAX_SLOTS);
1335 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1339 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1341 if (first_bar > 5) {
1342 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1346 ret = pci_enable_device(pdev);
1350 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1357 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1359 chip->quirks = chip->fixes->quirks;
1360 chip->num_slots = slots;
1362 pci_set_drvdata(pdev, chip);
1364 if (chip->fixes && chip->fixes->probe) {
1365 ret = chip->fixes->probe(chip);
1370 slots = chip->num_slots; /* Quirk may have changed this */
1372 for (i = 0; i < slots; i++) {
1373 slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
1375 for (i--; i >= 0; i--)
1376 sdhci_pci_remove_slot(chip->slots[i]);
1377 ret = PTR_ERR(slot);
1381 chip->slots[i] = slot;
1384 sdhci_pci_runtime_pm_allow(&pdev->dev);
1389 pci_set_drvdata(pdev, NULL);
1393 pci_disable_device(pdev);
1397 static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
1400 struct sdhci_pci_chip *chip;
1402 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1404 chip = pci_get_drvdata(pdev);
1407 for (i = 0; i < chip->num_slots; i++)
1408 sdhci_pci_remove_slot(chip->slots[i]);
1410 pci_set_drvdata(pdev, NULL);
1414 pci_disable_device(pdev);
1417 static struct pci_driver sdhci_driver = {
1418 .name = "sdhci-pci",
1419 .id_table = pci_ids,
1420 .probe = sdhci_pci_probe,
1421 .remove = __devexit_p(sdhci_pci_remove),
1422 .suspend = sdhci_pci_suspend,
1423 .resume = sdhci_pci_resume,
1425 .pm = &sdhci_pci_pm_ops
1429 /*****************************************************************************\
1431 * Driver init/exit *
1433 \*****************************************************************************/
1435 static int __init sdhci_drv_init(void)
1437 return pci_register_driver(&sdhci_driver);
1440 static void __exit sdhci_drv_exit(void)
1442 pci_unregister_driver(&sdhci_driver);
1445 module_init(sdhci_drv_init);
1446 module_exit(sdhci_drv_exit);
1448 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1449 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1450 MODULE_LICENSE("GPL");