1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
10 * Thanks to the following companies for their support:
12 * - JMicron (hardware and technical support)
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/scatterlist.h>
25 #include <linux/gpio.h>
26 #include <linux/sfi.h>
34 #define PCI_SDHCI_IFPIO 0x00
35 #define PCI_SDHCI_IFDMA 0x01
36 #define PCI_SDHCI_IFVENDOR 0x02
38 #define PCI_SLOT_INFO 0x40 /* 8 bits */
39 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
40 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
44 struct sdhci_pci_chip;
45 struct sdhci_pci_slot;
47 struct sdhci_pci_fixes {
50 int (*probe) (struct sdhci_pci_chip *);
52 int (*probe_slot) (struct sdhci_pci_slot *);
53 void (*remove_slot) (struct sdhci_pci_slot *, int);
55 int (*suspend) (struct sdhci_pci_chip *,
57 int (*resume) (struct sdhci_pci_chip *);
60 struct sdhci_pci_slot {
61 struct sdhci_pci_chip *chip;
62 struct sdhci_host *host;
68 struct sdhci_pci_chip {
72 const struct sdhci_pci_fixes *fixes;
74 int num_slots; /* Slots on controller */
75 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
79 /*****************************************************************************\
81 * Hardware specific quirk handling *
83 \*****************************************************************************/
85 static int ricoh_probe(struct sdhci_pci_chip *chip)
87 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
88 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
89 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
93 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
96 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
97 & SDHCI_TIMEOUT_CLK_MASK) |
99 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
100 & SDHCI_CLOCK_BASE_MASK) |
102 SDHCI_TIMEOUT_CLK_UNIT |
108 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
110 /* Apply a delay to allow controller to settle */
111 /* Otherwise it becomes confused if card state changed
117 static const struct sdhci_pci_fixes sdhci_ricoh = {
118 .probe = ricoh_probe,
119 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
120 SDHCI_QUIRK_FORCE_DMA |
121 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
124 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
125 .probe_slot = ricoh_mmc_probe_slot,
126 .resume = ricoh_mmc_resume,
127 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
128 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
129 SDHCI_QUIRK_NO_CARD_NO_RESET |
130 SDHCI_QUIRK_MISSING_CAPS
133 static const struct sdhci_pci_fixes sdhci_ene_712 = {
134 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
135 SDHCI_QUIRK_BROKEN_DMA,
138 static const struct sdhci_pci_fixes sdhci_ene_714 = {
139 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
140 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
141 SDHCI_QUIRK_BROKEN_DMA,
144 static const struct sdhci_pci_fixes sdhci_cafe = {
145 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
146 SDHCI_QUIRK_NO_BUSY_IRQ |
147 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
150 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
152 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
157 * ADMA operation is disabled for Moorestown platform due to
160 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
163 * slots number is fixed here for MRST as SDIO3/5 are never used and
164 * have hardware bugs.
170 /* Medfield eMMC hardware reset GPIOs */
171 static int mfd_emmc0_rst_gpio = -EINVAL;
172 static int mfd_emmc1_rst_gpio = -EINVAL;
174 static int mfd_emmc_gpio_parse(struct sfi_table_header *table)
176 struct sfi_table_simple *sb = (struct sfi_table_simple *)table;
177 struct sfi_gpio_table_entry *entry;
180 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
181 entry = (struct sfi_gpio_table_entry *)sb->pentry;
183 for (i = 0; i < num; i++, entry++) {
184 if (!strncmp(entry->pin_name, "emmc0_rst", SFI_NAME_LEN))
185 mfd_emmc0_rst_gpio = entry->pin_no;
186 else if (!strncmp(entry->pin_name, "emmc1_rst", SFI_NAME_LEN))
187 mfd_emmc1_rst_gpio = entry->pin_no;
193 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
195 const char *name = NULL;
198 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, mfd_emmc_gpio_parse);
200 switch (slot->chip->pdev->device) {
201 case PCI_DEVICE_ID_INTEL_MFD_EMMC0:
202 gpio = mfd_emmc0_rst_gpio;
203 name = "eMMC0_reset";
205 case PCI_DEVICE_ID_INTEL_MFD_EMMC1:
206 gpio = mfd_emmc1_rst_gpio;
207 name = "eMMC1_reset";
211 if (!gpio_request(gpio, name)) {
212 gpio_direction_output(gpio, 1);
213 slot->rst_n_gpio = gpio;
214 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
217 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
219 slot->host->mmc->caps2 = MMC_CAP2_BOOTPART_NOACC;
224 static void mfd_emmc_remove_slot(struct sdhci_pci_slot *slot, int dead)
226 gpio_free(slot->rst_n_gpio);
229 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
230 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
231 .probe_slot = mrst_hc_probe_slot,
234 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
235 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
236 .probe = mrst_hc_probe,
239 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
240 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
243 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
244 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
247 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
248 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
249 .probe_slot = mfd_emmc_probe_slot,
250 .remove_slot = mfd_emmc_remove_slot,
253 /* O2Micro extra registers */
254 #define O2_SD_LOCK_WP 0xD3
255 #define O2_SD_MULTI_VCC3V 0xEE
256 #define O2_SD_CLKREQ 0xEC
257 #define O2_SD_CAPS 0xE0
258 #define O2_SD_ADMA1 0xE2
259 #define O2_SD_ADMA2 0xE7
260 #define O2_SD_INF_MOD 0xF1
262 static int o2_probe(struct sdhci_pci_chip *chip)
267 switch (chip->pdev->device) {
268 case PCI_DEVICE_ID_O2_8220:
269 case PCI_DEVICE_ID_O2_8221:
270 case PCI_DEVICE_ID_O2_8320:
271 case PCI_DEVICE_ID_O2_8321:
272 /* This extra setup is required due to broken ADMA. */
273 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
277 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
279 /* Set Multi 3 to VCC3V# */
280 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
282 /* Disable CLK_REQ# support after media DET */
283 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
287 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
289 /* Choose capabilities, enable SDMA. We have to write 0x01
290 * to the capabilities register first to unlock it.
292 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
296 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
297 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
299 /* Disable ADMA1/2 */
300 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
301 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
303 /* Disable the infinite transfer mode */
304 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
308 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
311 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
315 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
321 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
326 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
331 * Turn PMOS on [bit 0], set over current detection to 2.4 V
332 * [bit 1:2] and enable over current debouncing [bit 6].
339 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
346 static int jmicron_probe(struct sdhci_pci_chip *chip)
351 if (chip->pdev->revision == 0) {
352 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
353 SDHCI_QUIRK_32BIT_DMA_SIZE |
354 SDHCI_QUIRK_32BIT_ADMA_SIZE |
355 SDHCI_QUIRK_RESET_AFTER_REQUEST |
356 SDHCI_QUIRK_BROKEN_SMALL_PIO;
360 * JMicron chips can have two interfaces to the same hardware
361 * in order to work around limitations in Microsoft's driver.
362 * We need to make sure we only bind to one of them.
364 * This code assumes two things:
366 * 1. The PCI code adds subfunctions in order.
368 * 2. The MMC interface has a lower subfunction number
369 * than the SD interface.
371 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
372 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
373 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
374 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
377 struct pci_dev *sd_dev;
380 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
381 mmcdev, sd_dev)) != NULL) {
382 if ((PCI_SLOT(chip->pdev->devfn) ==
383 PCI_SLOT(sd_dev->devfn)) &&
384 (chip->pdev->bus == sd_dev->bus))
390 dev_info(&chip->pdev->dev, "Refusing to bind to "
391 "secondary interface.\n");
397 * JMicron chips need a bit of a nudge to enable the power
400 ret = jmicron_pmos(chip, 1);
402 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
406 /* quirk for unsable RO-detection on JM388 chips */
407 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
408 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
409 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
414 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
418 scratch = readb(host->ioaddr + 0xC0);
425 writeb(scratch, host->ioaddr + 0xC0);
428 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
430 if (slot->chip->pdev->revision == 0) {
433 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
434 version = (version & SDHCI_VENDOR_VER_MASK) >>
435 SDHCI_VENDOR_VER_SHIFT;
438 * Older versions of the chip have lots of nasty glitches
439 * in the ADMA engine. It's best just to avoid it
443 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
446 /* JM388 MMC doesn't support 1.8V while SD supports it */
447 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
448 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
449 MMC_VDD_29_30 | MMC_VDD_30_31 |
450 MMC_VDD_165_195; /* allow 1.8V */
451 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
452 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
456 * The secondary interface requires a bit set to get the
459 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
460 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
461 jmicron_enable_mmc(slot->host, 1);
463 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
468 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
473 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
474 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
475 jmicron_enable_mmc(slot->host, 0);
478 static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
482 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
483 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
484 for (i = 0; i < chip->num_slots; i++)
485 jmicron_enable_mmc(chip->slots[i]->host, 0);
491 static int jmicron_resume(struct sdhci_pci_chip *chip)
495 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
496 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
497 for (i = 0; i < chip->num_slots; i++)
498 jmicron_enable_mmc(chip->slots[i]->host, 1);
501 ret = jmicron_pmos(chip, 1);
503 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
510 static const struct sdhci_pci_fixes sdhci_o2 = {
514 static const struct sdhci_pci_fixes sdhci_jmicron = {
515 .probe = jmicron_probe,
517 .probe_slot = jmicron_probe_slot,
518 .remove_slot = jmicron_remove_slot,
520 .suspend = jmicron_suspend,
521 .resume = jmicron_resume,
524 /* SysKonnect CardBus2SDIO extra registers */
525 #define SYSKT_CTRL 0x200
526 #define SYSKT_RDFIFO_STAT 0x204
527 #define SYSKT_WRFIFO_STAT 0x208
528 #define SYSKT_POWER_DATA 0x20c
529 #define SYSKT_POWER_330 0xef
530 #define SYSKT_POWER_300 0xf8
531 #define SYSKT_POWER_184 0xcc
532 #define SYSKT_POWER_CMD 0x20d
533 #define SYSKT_POWER_START (1 << 7)
534 #define SYSKT_POWER_STATUS 0x20e
535 #define SYSKT_POWER_STATUS_OK (1 << 0)
536 #define SYSKT_BOARD_REV 0x210
537 #define SYSKT_CHIP_REV 0x211
538 #define SYSKT_CONF_DATA 0x212
539 #define SYSKT_CONF_DATA_1V8 (1 << 2)
540 #define SYSKT_CONF_DATA_2V5 (1 << 1)
541 #define SYSKT_CONF_DATA_3V3 (1 << 0)
543 static int syskt_probe(struct sdhci_pci_chip *chip)
545 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
546 chip->pdev->class &= ~0x0000FF;
547 chip->pdev->class |= PCI_SDHCI_IFDMA;
552 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
556 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
557 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
558 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
559 "board rev %d.%d, chip rev %d.%d\n",
560 board_rev >> 4, board_rev & 0xf,
561 chip_rev >> 4, chip_rev & 0xf);
562 if (chip_rev >= 0x20)
563 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
565 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
566 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
568 tm = 10; /* Wait max 1 ms */
570 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
571 if (ps & SYSKT_POWER_STATUS_OK)
576 dev_err(&slot->chip->pdev->dev,
577 "power regulator never stabilized");
578 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
585 static const struct sdhci_pci_fixes sdhci_syskt = {
586 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
587 .probe = syskt_probe,
588 .probe_slot = syskt_probe_slot,
591 static int via_probe(struct sdhci_pci_chip *chip)
593 if (chip->pdev->revision == 0x10)
594 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
599 static const struct sdhci_pci_fixes sdhci_via = {
603 static const struct pci_device_id pci_ids[] __devinitdata = {
605 .vendor = PCI_VENDOR_ID_RICOH,
606 .device = PCI_DEVICE_ID_RICOH_R5C822,
607 .subvendor = PCI_ANY_ID,
608 .subdevice = PCI_ANY_ID,
609 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
613 .vendor = PCI_VENDOR_ID_RICOH,
615 .subvendor = PCI_ANY_ID,
616 .subdevice = PCI_ANY_ID,
617 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
621 .vendor = PCI_VENDOR_ID_RICOH,
623 .subvendor = PCI_ANY_ID,
624 .subdevice = PCI_ANY_ID,
625 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
629 .vendor = PCI_VENDOR_ID_RICOH,
631 .subvendor = PCI_ANY_ID,
632 .subdevice = PCI_ANY_ID,
633 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
637 .vendor = PCI_VENDOR_ID_ENE,
638 .device = PCI_DEVICE_ID_ENE_CB712_SD,
639 .subvendor = PCI_ANY_ID,
640 .subdevice = PCI_ANY_ID,
641 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
645 .vendor = PCI_VENDOR_ID_ENE,
646 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
647 .subvendor = PCI_ANY_ID,
648 .subdevice = PCI_ANY_ID,
649 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
653 .vendor = PCI_VENDOR_ID_ENE,
654 .device = PCI_DEVICE_ID_ENE_CB714_SD,
655 .subvendor = PCI_ANY_ID,
656 .subdevice = PCI_ANY_ID,
657 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
661 .vendor = PCI_VENDOR_ID_ENE,
662 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
663 .subvendor = PCI_ANY_ID,
664 .subdevice = PCI_ANY_ID,
665 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
669 .vendor = PCI_VENDOR_ID_MARVELL,
670 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
671 .subvendor = PCI_ANY_ID,
672 .subdevice = PCI_ANY_ID,
673 .driver_data = (kernel_ulong_t)&sdhci_cafe,
677 .vendor = PCI_VENDOR_ID_JMICRON,
678 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
679 .subvendor = PCI_ANY_ID,
680 .subdevice = PCI_ANY_ID,
681 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
685 .vendor = PCI_VENDOR_ID_JMICRON,
686 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
687 .subvendor = PCI_ANY_ID,
688 .subdevice = PCI_ANY_ID,
689 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
693 .vendor = PCI_VENDOR_ID_JMICRON,
694 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
695 .subvendor = PCI_ANY_ID,
696 .subdevice = PCI_ANY_ID,
697 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
701 .vendor = PCI_VENDOR_ID_JMICRON,
702 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
703 .subvendor = PCI_ANY_ID,
704 .subdevice = PCI_ANY_ID,
705 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
709 .vendor = PCI_VENDOR_ID_SYSKONNECT,
711 .subvendor = PCI_ANY_ID,
712 .subdevice = PCI_ANY_ID,
713 .driver_data = (kernel_ulong_t)&sdhci_syskt,
717 .vendor = PCI_VENDOR_ID_VIA,
719 .subvendor = PCI_ANY_ID,
720 .subdevice = PCI_ANY_ID,
721 .driver_data = (kernel_ulong_t)&sdhci_via,
725 .vendor = PCI_VENDOR_ID_INTEL,
726 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
727 .subvendor = PCI_ANY_ID,
728 .subdevice = PCI_ANY_ID,
729 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
733 .vendor = PCI_VENDOR_ID_INTEL,
734 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
735 .subvendor = PCI_ANY_ID,
736 .subdevice = PCI_ANY_ID,
737 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
741 .vendor = PCI_VENDOR_ID_INTEL,
742 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
743 .subvendor = PCI_ANY_ID,
744 .subdevice = PCI_ANY_ID,
745 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
749 .vendor = PCI_VENDOR_ID_INTEL,
750 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
751 .subvendor = PCI_ANY_ID,
752 .subdevice = PCI_ANY_ID,
753 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
757 .vendor = PCI_VENDOR_ID_INTEL,
758 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
759 .subvendor = PCI_ANY_ID,
760 .subdevice = PCI_ANY_ID,
761 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
765 .vendor = PCI_VENDOR_ID_INTEL,
766 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
767 .subvendor = PCI_ANY_ID,
768 .subdevice = PCI_ANY_ID,
769 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
773 .vendor = PCI_VENDOR_ID_INTEL,
774 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
775 .subvendor = PCI_ANY_ID,
776 .subdevice = PCI_ANY_ID,
777 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
781 .vendor = PCI_VENDOR_ID_INTEL,
782 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
783 .subvendor = PCI_ANY_ID,
784 .subdevice = PCI_ANY_ID,
785 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
789 .vendor = PCI_VENDOR_ID_O2,
790 .device = PCI_DEVICE_ID_O2_8120,
791 .subvendor = PCI_ANY_ID,
792 .subdevice = PCI_ANY_ID,
793 .driver_data = (kernel_ulong_t)&sdhci_o2,
797 .vendor = PCI_VENDOR_ID_O2,
798 .device = PCI_DEVICE_ID_O2_8220,
799 .subvendor = PCI_ANY_ID,
800 .subdevice = PCI_ANY_ID,
801 .driver_data = (kernel_ulong_t)&sdhci_o2,
805 .vendor = PCI_VENDOR_ID_O2,
806 .device = PCI_DEVICE_ID_O2_8221,
807 .subvendor = PCI_ANY_ID,
808 .subdevice = PCI_ANY_ID,
809 .driver_data = (kernel_ulong_t)&sdhci_o2,
813 .vendor = PCI_VENDOR_ID_O2,
814 .device = PCI_DEVICE_ID_O2_8320,
815 .subvendor = PCI_ANY_ID,
816 .subdevice = PCI_ANY_ID,
817 .driver_data = (kernel_ulong_t)&sdhci_o2,
821 .vendor = PCI_VENDOR_ID_O2,
822 .device = PCI_DEVICE_ID_O2_8321,
823 .subvendor = PCI_ANY_ID,
824 .subdevice = PCI_ANY_ID,
825 .driver_data = (kernel_ulong_t)&sdhci_o2,
828 { /* Generic SD host controller */
829 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
832 { /* end: all zeroes */ },
835 MODULE_DEVICE_TABLE(pci, pci_ids);
837 /*****************************************************************************\
839 * SDHCI core callbacks *
841 \*****************************************************************************/
843 static int sdhci_pci_enable_dma(struct sdhci_host *host)
845 struct sdhci_pci_slot *slot;
846 struct pci_dev *pdev;
849 slot = sdhci_priv(host);
850 pdev = slot->chip->pdev;
852 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
853 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
854 (host->flags & SDHCI_USE_SDMA)) {
855 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
856 "doesn't fully claim to support it.\n");
859 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
863 pci_set_master(pdev);
868 static int sdhci_pci_8bit_width(struct sdhci_host *host, int width)
872 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
875 case MMC_BUS_WIDTH_8:
876 ctrl |= SDHCI_CTRL_8BITBUS;
877 ctrl &= ~SDHCI_CTRL_4BITBUS;
879 case MMC_BUS_WIDTH_4:
880 ctrl |= SDHCI_CTRL_4BITBUS;
881 ctrl &= ~SDHCI_CTRL_8BITBUS;
884 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
888 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
893 static void sdhci_pci_hw_reset(struct sdhci_host *host)
895 struct sdhci_pci_slot *slot = sdhci_priv(host);
896 int rst_n_gpio = slot->rst_n_gpio;
898 if (!gpio_is_valid(rst_n_gpio))
900 gpio_set_value_cansleep(rst_n_gpio, 0);
901 /* For eMMC, minimum is 1us but give it 10us for good measure */
903 gpio_set_value_cansleep(rst_n_gpio, 1);
904 /* For eMMC, minimum is 200us but give it 300us for good measure */
905 usleep_range(300, 1000);
908 static struct sdhci_ops sdhci_pci_ops = {
909 .enable_dma = sdhci_pci_enable_dma,
910 .platform_8bit_width = sdhci_pci_8bit_width,
911 .hw_reset = sdhci_pci_hw_reset,
914 /*****************************************************************************\
918 \*****************************************************************************/
922 static int sdhci_pci_suspend(struct pci_dev *pdev, pm_message_t state)
924 struct sdhci_pci_chip *chip;
925 struct sdhci_pci_slot *slot;
926 mmc_pm_flag_t slot_pm_flags;
927 mmc_pm_flag_t pm_flags = 0;
930 chip = pci_get_drvdata(pdev);
934 for (i = 0; i < chip->num_slots; i++) {
935 slot = chip->slots[i];
939 ret = sdhci_suspend_host(slot->host, state);
942 for (i--; i >= 0; i--)
943 sdhci_resume_host(chip->slots[i]->host);
947 slot_pm_flags = slot->host->mmc->pm_flags;
948 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
949 sdhci_enable_irq_wakeups(slot->host);
951 pm_flags |= slot_pm_flags;
954 if (chip->fixes && chip->fixes->suspend) {
955 ret = chip->fixes->suspend(chip, state);
957 for (i = chip->num_slots - 1; i >= 0; i--)
958 sdhci_resume_host(chip->slots[i]->host);
963 pci_save_state(pdev);
964 if (pm_flags & MMC_PM_KEEP_POWER) {
965 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
966 pci_pme_active(pdev, true);
967 pci_enable_wake(pdev, PCI_D3hot, 1);
969 pci_set_power_state(pdev, PCI_D3hot);
971 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
972 pci_disable_device(pdev);
973 pci_set_power_state(pdev, pci_choose_state(pdev, state));
979 static int sdhci_pci_resume(struct pci_dev *pdev)
981 struct sdhci_pci_chip *chip;
982 struct sdhci_pci_slot *slot;
985 chip = pci_get_drvdata(pdev);
989 pci_set_power_state(pdev, PCI_D0);
990 pci_restore_state(pdev);
991 ret = pci_enable_device(pdev);
995 if (chip->fixes && chip->fixes->resume) {
996 ret = chip->fixes->resume(chip);
1001 for (i = 0; i < chip->num_slots; i++) {
1002 slot = chip->slots[i];
1006 ret = sdhci_resume_host(slot->host);
1014 #else /* CONFIG_PM */
1016 #define sdhci_pci_suspend NULL
1017 #define sdhci_pci_resume NULL
1019 #endif /* CONFIG_PM */
1021 /*****************************************************************************\
1023 * Device probing/removal *
1025 \*****************************************************************************/
1027 static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
1028 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
1030 struct sdhci_pci_slot *slot;
1031 struct sdhci_host *host;
1034 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1035 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1036 return ERR_PTR(-ENODEV);
1039 if (pci_resource_len(pdev, bar) != 0x100) {
1040 dev_err(&pdev->dev, "Invalid iomem size. You may "
1041 "experience problems.\n");
1044 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1045 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1046 return ERR_PTR(-ENODEV);
1049 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1050 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1051 return ERR_PTR(-ENODEV);
1054 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1056 dev_err(&pdev->dev, "cannot allocate host\n");
1057 return ERR_CAST(host);
1060 slot = sdhci_priv(host);
1064 slot->pci_bar = bar;
1065 slot->rst_n_gpio = -EINVAL;
1067 host->hw_name = "PCI";
1068 host->ops = &sdhci_pci_ops;
1069 host->quirks = chip->quirks;
1071 host->irq = pdev->irq;
1073 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1075 dev_err(&pdev->dev, "cannot request region\n");
1079 host->ioaddr = pci_ioremap_bar(pdev, bar);
1080 if (!host->ioaddr) {
1081 dev_err(&pdev->dev, "failed to remap registers\n");
1086 if (chip->fixes && chip->fixes->probe_slot) {
1087 ret = chip->fixes->probe_slot(slot);
1092 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1094 ret = sdhci_add_host(host);
1101 if (chip->fixes && chip->fixes->remove_slot)
1102 chip->fixes->remove_slot(slot, 0);
1105 iounmap(host->ioaddr);
1108 pci_release_region(pdev, bar);
1111 sdhci_free_host(host);
1113 return ERR_PTR(ret);
1116 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1122 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1123 if (scratch == (u32)-1)
1126 sdhci_remove_host(slot->host, dead);
1128 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1129 slot->chip->fixes->remove_slot(slot, dead);
1131 pci_release_region(slot->chip->pdev, slot->pci_bar);
1133 sdhci_free_host(slot->host);
1136 static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
1137 const struct pci_device_id *ent)
1139 struct sdhci_pci_chip *chip;
1140 struct sdhci_pci_slot *slot;
1142 u8 slots, first_bar;
1145 BUG_ON(pdev == NULL);
1146 BUG_ON(ent == NULL);
1148 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1149 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1151 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1155 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1156 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1160 BUG_ON(slots > MAX_SLOTS);
1162 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1166 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1168 if (first_bar > 5) {
1169 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1173 ret = pci_enable_device(pdev);
1177 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1184 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1186 chip->quirks = chip->fixes->quirks;
1187 chip->num_slots = slots;
1189 pci_set_drvdata(pdev, chip);
1191 if (chip->fixes && chip->fixes->probe) {
1192 ret = chip->fixes->probe(chip);
1197 slots = chip->num_slots; /* Quirk may have changed this */
1199 for (i = 0; i < slots; i++) {
1200 slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
1202 for (i--; i >= 0; i--)
1203 sdhci_pci_remove_slot(chip->slots[i]);
1204 ret = PTR_ERR(slot);
1208 chip->slots[i] = slot;
1214 pci_set_drvdata(pdev, NULL);
1218 pci_disable_device(pdev);
1222 static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
1225 struct sdhci_pci_chip *chip;
1227 chip = pci_get_drvdata(pdev);
1230 for (i = 0; i < chip->num_slots; i++)
1231 sdhci_pci_remove_slot(chip->slots[i]);
1233 pci_set_drvdata(pdev, NULL);
1237 pci_disable_device(pdev);
1240 static struct pci_driver sdhci_driver = {
1241 .name = "sdhci-pci",
1242 .id_table = pci_ids,
1243 .probe = sdhci_pci_probe,
1244 .remove = __devexit_p(sdhci_pci_remove),
1245 .suspend = sdhci_pci_suspend,
1246 .resume = sdhci_pci_resume,
1249 /*****************************************************************************\
1251 * Driver init/exit *
1253 \*****************************************************************************/
1255 static int __init sdhci_drv_init(void)
1257 return pci_register_driver(&sdhci_driver);
1260 static void __exit sdhci_drv_exit(void)
1262 pci_unregister_driver(&sdhci_driver);
1265 module_init(sdhci_drv_init);
1266 module_exit(sdhci_drv_exit);
1268 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1269 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1270 MODULE_LICENSE("GPL");