drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/core.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/io.h>
  33 #include <linux/semaphore.h>
  34 #include <linux/gpio.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/pm_runtime.h>
  37 #include <plat/dma.h>
  38 #include <mach/hardware.h>
  39 #include <plat/board.h>
  40 #include <plat/mmc.h>
  41 #include <plat/cpu.h>
  42
  43 /* OMAP HSMMC Host Controller Registers */
  44 #define OMAP_HSMMC_SYSCONFIG    0x0010
  45 #define OMAP_HSMMC_SYSSTATUS    0x0014
  46 #define OMAP_HSMMC_CON          0x002C
  47 #define OMAP_HSMMC_BLK          0x0104
  48 #define OMAP_HSMMC_ARG          0x0108
  49 #define OMAP_HSMMC_CMD          0x010C
  50 #define OMAP_HSMMC_RSP10        0x0110
  51 #define OMAP_HSMMC_RSP32        0x0114
  52 #define OMAP_HSMMC_RSP54        0x0118
  53 #define OMAP_HSMMC_RSP76        0x011C
  54 #define OMAP_HSMMC_DATA         0x0120
  55 #define OMAP_HSMMC_HCTL         0x0128
  56 #define OMAP_HSMMC_SYSCTL       0x012C
  57 #define OMAP_HSMMC_STAT         0x0130
  58 #define OMAP_HSMMC_IE           0x0134
  59 #define OMAP_HSMMC_ISE          0x0138
  60 #define OMAP_HSMMC_CAPA         0x0140
  61
  62 #define VS18                    (1 << 26)
  63 #define VS30                    (1 << 25)
  64 #define SDVS18                  (0x5 << 9)
  65 #define SDVS30                  (0x6 << 9)
  66 #define SDVS33                  (0x7 << 9)
  67 #define SDVS_MASK               0x00000E00
  68 #define SDVSCLR                 0xFFFFF1FF
  69 #define SDVSDET                 0x00000400
  70 #define AUTOIDLE                0x1
  71 #define SDBP                    (1 << 8)
  72 #define DTO                     0xe
  73 #define ICE                     0x1
  74 #define ICS                     0x2
  75 #define CEN                     (1 << 2)
  76 #define CLKD_MASK               0x0000FFC0
  77 #define CLKD_SHIFT              6
  78 #define DTO_MASK                0x000F0000
  79 #define DTO_SHIFT               16
  80 #define INT_EN_MASK             0x307F0033
  81 #define BWR_ENABLE              (1 << 4)
  82 #define BRR_ENABLE              (1 << 5)
  83 #define DTO_ENABLE              (1 << 20)
  84 #define INIT_STREAM             (1 << 1)
  85 #define DP_SELECT               (1 << 21)
  86 #define DDIR                    (1 << 4)
  87 #define DMA_EN                  0x1
  88 #define MSBS                    (1 << 5)
  89 #define BCE                     (1 << 1)
  90 #define FOUR_BIT                (1 << 1)
  91 #define DW8                     (1 << 5)
  92 #define CC                      0x1
  93 #define TC                      0x02
  94 #define OD                      0x1
  95 #define ERR                     (1 << 15)
  96 #define CMD_TIMEOUT             (1 << 16)
  97 #define DATA_TIMEOUT            (1 << 20)
  98 #define CMD_CRC                 (1 << 17)
  99 #define DATA_CRC                (1 << 21)
 100 #define CARD_ERR                (1 << 28)
 101 #define STAT_CLEAR              0xFFFFFFFF
 102 #define INIT_STREAM_CMD         0x00000000
 103 #define DUAL_VOLT_OCR_BIT       7
 104 #define SRC                     (1 << 25)
 105 #define SRD                     (1 << 26)
 106 #define SOFTRESET               (1 << 1)
 107 #define RESETDONE               (1 << 0)
 108
 109 /*
 110  * FIXME: Most likely all the data using these _DEVID defines should come
 111  * from the platform_data, or implemented in controller and slot specific
 112  * functions.
 113  */
 114 #define OMAP_MMC1_DEVID         0
 115 #define OMAP_MMC2_DEVID         1
 116 #define OMAP_MMC3_DEVID         2
 117 #define OMAP_MMC4_DEVID         3
 118 #define OMAP_MMC5_DEVID         4
 119
 120 #define MMC_AUTOSUSPEND_DELAY   100
 121 #define MMC_TIMEOUT_MS          20
 122 #define OMAP_MMC_MASTER_CLOCK   96000000
 123 #define OMAP_MMC_MIN_CLOCK      400000
 124 #define OMAP_MMC_MAX_CLOCK      52000000
 125 #define DRIVER_NAME             "omap_hsmmc"
 126
 127 /*
 128  * One controller can have multiple slots, like on some omap boards using
 129  * omap.c controller driver. Luckily this is not currently done on any known
 130  * omap_hsmmc.c device.
 131  */
 132 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 133
 134 /*
 135  * MMC Host controller read/write API's
 136  */
 137 #define OMAP_HSMMC_READ(base, reg)      \
 138         __raw_readl((base) + OMAP_HSMMC_##reg)
 139
 140 #define OMAP_HSMMC_WRITE(base, reg, val) \
 141         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 142
 143 struct omap_hsmmc_next {
 144         unsigned int    dma_len;
 145         s32             cookie;
 146 };
 147
 148 struct omap_hsmmc_host {
 149         struct  device          *dev;
 150         struct  mmc_host        *mmc;
 151         struct  mmc_request     *mrq;
 152         struct  mmc_command     *cmd;
 153         struct  mmc_data        *data;
 154         struct  clk             *fclk;
 155         struct  clk             *dbclk;
 156         /*
 157          * vcc == configured supply
 158          * vcc_aux == optional
 159          *   -  MMC1, supply for DAT4..DAT7
 160          *   -  MMC2/MMC2, external level shifter voltage supply, for
 161          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 162          */
 163         struct  regulator       *vcc;
 164         struct  regulator       *vcc_aux;
 165         void    __iomem         *base;
 166         resource_size_t         mapbase;
 167         spinlock_t              irq_lock; /* Prevent races with irq handler */
 168         unsigned int            id;
 169         unsigned int            dma_len;
 170         unsigned int            dma_sg_idx;
 171         unsigned char           bus_mode;
 172         unsigned char           power_mode;
 173         u32                     *buffer;
 174         u32                     bytesleft;
 175         int                     suspended;
 176         int                     irq;
 177         int                     use_dma, dma_ch;
 178         int                     dma_line_tx, dma_line_rx;
 179         int                     slot_id;
 180         int                     got_dbclk;
 181         int                     response_busy;
 182         int                     context_loss;
 183         int                     dpm_state;
 184         int                     vdd;
 185         int                     protect_card;
 186         int                     reqs_blocked;
 187         int                     use_reg;
 188         int                     req_in_progress;
 189         struct omap_hsmmc_next  next_data;
 190
 191         struct  omap_mmc_platform_data  *pdata;
 192 };
 193
 194 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 195 {
 196         struct omap_mmc_platform_data *mmc = dev->platform_data;
 197
 198         /* NOTE: assumes card detect signal is active-low */
 199         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 200 }
 201
 202 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 203 {
 204         struct omap_mmc_platform_data *mmc = dev->platform_data;
 205
 206         /* NOTE: assumes write protect signal is active-high */
 207         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 208 }
 209
 210 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 211 {
 212         struct omap_mmc_platform_data *mmc = dev->platform_data;
 213
 214         /* NOTE: assumes card detect signal is active-low */
 215         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 216 }
 217
 218 #ifdef CONFIG_PM
 219
 220 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 221 {
 222         struct omap_mmc_platform_data *mmc = dev->platform_data;
 223
 224         disable_irq(mmc->slots[0].card_detect_irq);
 225         return 0;
 226 }
 227
 228 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 229 {
 230         struct omap_mmc_platform_data *mmc = dev->platform_data;
 231
 232         enable_irq(mmc->slots[0].card_detect_irq);
 233         return 0;
 234 }
 235
 236 #else
 237
 238 #define omap_hsmmc_suspend_cdirq        NULL
 239 #define omap_hsmmc_resume_cdirq         NULL
 240
 241 #endif
 242
 243 #ifdef CONFIG_REGULATOR
 244
 245 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
 246                                   int vdd)
 247 {
 248         struct omap_hsmmc_host *host =
 249                 platform_get_drvdata(to_platform_device(dev));
 250         int ret;
 251
 252         if (mmc_slot(host).before_set_reg)
 253                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 254
 255         if (power_on)
 256                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 257         else
 258                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
 259
 260         if (mmc_slot(host).after_set_reg)
 261                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 262
 263         return ret;
 264 }
 265
 266 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
 267                                    int vdd)
 268 {
 269         struct omap_hsmmc_host *host =
 270                 platform_get_drvdata(to_platform_device(dev));
 271         int ret = 0;
 272
 273         /*
 274          * If we don't see a Vcc regulator, assume it's a fixed
 275          * voltage always-on regulator.
 276          */
 277         if (!host->vcc)
 278                 return 0;
 279
 280         if (mmc_slot(host).before_set_reg)
 281                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 282
 283         /*
 284          * Assume Vcc regulator is used only to power the card ... OMAP
 285          * VDDS is used to power the pins, optionally with a transceiver to
 286          * support cards using voltages other than VDDS (1.8V nominal).  When a
 287          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 288          *
 289          * In some cases this regulator won't support enable/disable;
 290          * e.g. it's a fixed rail for a WLAN chip.
 291          *
 292          * In other cases vcc_aux switches interface power.  Example, for
 293          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 294          * chips/cards need an interface voltage rail too.
 295          */
 296         if (power_on) {
 297                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 298                 /* Enable interface voltage rail, if needed */
 299                 if (ret == 0 && host->vcc_aux) {
 300                         ret = regulator_enable(host->vcc_aux);
 301                         if (ret < 0)
 302                                 ret = mmc_regulator_set_ocr(host->mmc,
 303                                                         host->vcc, 0);
 304                 }
 305         } else {
 306                 /* Shut down the rail */
 307                 if (host->vcc_aux)
 308                         ret = regulator_disable(host->vcc_aux);
 309                 if (!ret) {
 310                         /* Then proceed to shut down the local regulator */
 311                         ret = mmc_regulator_set_ocr(host->mmc,
 312                                                 host->vcc, 0);
 313                 }
 314         }
 315
 316         if (mmc_slot(host).after_set_reg)
 317                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 318
 319         return ret;
 320 }
 321
 322 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
 323                                         int vdd)
 324 {
 325         return 0;
 326 }
 327
 328 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
 329                                   int vdd, int cardsleep)
 330 {
 331         struct omap_hsmmc_host *host =
 332                 platform_get_drvdata(to_platform_device(dev));
 333         int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 334
 335         return regulator_set_mode(host->vcc, mode);
 336 }
 337
 338 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
 339                                    int vdd, int cardsleep)
 340 {
 341         struct omap_hsmmc_host *host =
 342                 platform_get_drvdata(to_platform_device(dev));
 343         int err, mode;
 344
 345         /*
 346          * If we don't see a Vcc regulator, assume it's a fixed
 347          * voltage always-on regulator.
 348          */
 349         if (!host->vcc)
 350                 return 0;
 351
 352         mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 353
 354         if (!host->vcc_aux)
 355                 return regulator_set_mode(host->vcc, mode);
 356
 357         if (cardsleep) {
 358                 /* VCC can be turned off if card is asleep */
 359                 if (sleep)
 360                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
 361                 else
 362                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 363         } else
 364                 err = regulator_set_mode(host->vcc, mode);
 365         if (err)
 366                 return err;
 367
 368         if (!mmc_slot(host).vcc_aux_disable_is_sleep)
 369                 return regulator_set_mode(host->vcc_aux, mode);
 370
 371         if (sleep)
 372                 return regulator_disable(host->vcc_aux);
 373         else
 374                 return regulator_enable(host->vcc_aux);
 375 }
 376
 377 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
 378                                         int vdd, int cardsleep)
 379 {
 380         return 0;
 381 }
 382
 383 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 384 {
 385         struct regulator *reg;
 386         int ret = 0;
 387         int ocr_value = 0;
 388
 389         switch (host->id) {
 390         case OMAP_MMC1_DEVID:
 391                 /* On-chip level shifting via PBIAS0/PBIAS1 */
 392                 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
 393                 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
 394                 break;
 395         case OMAP_MMC2_DEVID:
 396         case OMAP_MMC3_DEVID:
 397         case OMAP_MMC5_DEVID:
 398                 /* Off-chip level shifting, or none */
 399                 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
 400                 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
 401                 break;
 402         case OMAP_MMC4_DEVID:
 403                 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
 404                 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
 405         default:
 406                 pr_err("MMC%d configuration not supported!\n", host->id);
 407                 return -EINVAL;
 408         }
 409
 410         reg = regulator_get(host->dev, "vmmc");
 411         if (IS_ERR(reg)) {
 412                 dev_dbg(host->dev, "vmmc regulator missing\n");
 413                 /*
 414                 * HACK: until fixed.c regulator is usable,
 415                 * we don't require a main regulator
 416                 * for MMC2 or MMC3
 417                 */
 418                 if (host->id == OMAP_MMC1_DEVID) {
 419                         ret = PTR_ERR(reg);
 420                         goto err;
 421                 }
 422         } else {
 423                 host->vcc = reg;
 424                 ocr_value = mmc_regulator_get_ocrmask(reg);
 425                 if (!mmc_slot(host).ocr_mask) {
 426                         mmc_slot(host).ocr_mask = ocr_value;
 427                 } else {
 428                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 429                                 pr_err("MMC%d ocrmask %x is not supported\n",
 430                                         host->id, mmc_slot(host).ocr_mask);
 431                                 mmc_slot(host).ocr_mask = 0;
 432                                 return -EINVAL;
 433                         }
 434                 }
 435
 436                 /* Allow an aux regulator */
 437                 reg = regulator_get(host->dev, "vmmc_aux");
 438                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 439
 440                 /* For eMMC do not power off when not in sleep state */
 441                 if (mmc_slot(host).no_regulator_off_init)
 442                         return 0;
 443                 /*
 444                 * UGLY HACK:  workaround regulator framework bugs.
 445                 * When the bootloader leaves a supply active, it's
 446                 * initialized with zero usecount ... and we can't
 447                 * disable it without first enabling it.  Until the
 448                 * framework is fixed, we need a workaround like this
 449                 * (which is safe for MMC, but not in general).
 450                 */
 451                 if (regulator_is_enabled(host->vcc) > 0 ||
 452                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 453                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 454
 455                         mmc_slot(host).set_power(host->dev, host->slot_id,
 456                                                  1, vdd);
 457                         mmc_slot(host).set_power(host->dev, host->slot_id,
 458                                                  0, 0);
 459                 }
 460         }
 461
 462         return 0;
 463
 464 err:
 465         mmc_slot(host).set_power = NULL;
 466         mmc_slot(host).set_sleep = NULL;
 467         return ret;
 468 }
 469
 470 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 471 {
 472         regulator_put(host->vcc);
 473         regulator_put(host->vcc_aux);
 474         mmc_slot(host).set_power = NULL;
 475         mmc_slot(host).set_sleep = NULL;
 476 }
 477
 478 static inline int omap_hsmmc_have_reg(void)
 479 {
 480         return 1;
 481 }
 482
 483 #else
 484
 485 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 486 {
 487         return -EINVAL;
 488 }
 489
 490 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 491 {
 492 }
 493
 494 static inline int omap_hsmmc_have_reg(void)
 495 {
 496         return 0;
 497 }
 498
 499 #endif
 500
 501 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 502 {
 503         int ret;
 504
 505         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 506                 if (pdata->slots[0].cover)
 507                         pdata->slots[0].get_cover_state =
 508                                         omap_hsmmc_get_cover_state;
 509                 else
 510                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 511                 pdata->slots[0].card_detect_irq =
 512                                 gpio_to_irq(pdata->slots[0].switch_pin);
 513                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 514                 if (ret)
 515                         return ret;
 516                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 517                 if (ret)
 518                         goto err_free_sp;
 519         } else
 520                 pdata->slots[0].switch_pin = -EINVAL;
 521
 522         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 523                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 524                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 525                 if (ret)
 526                         goto err_free_cd;
 527                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 528                 if (ret)
 529                         goto err_free_wp;
 530         } else
 531                 pdata->slots[0].gpio_wp = -EINVAL;
 532
 533         return 0;
 534
 535 err_free_wp:
 536         gpio_free(pdata->slots[0].gpio_wp);
 537 err_free_cd:
 538         if (gpio_is_valid(pdata->slots[0].switch_pin))
 539 err_free_sp:
 540                 gpio_free(pdata->slots[0].switch_pin);
 541         return ret;
 542 }
 543
 544 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 545 {
 546         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 547                 gpio_free(pdata->slots[0].gpio_wp);
 548         if (gpio_is_valid(pdata->slots[0].switch_pin))
 549                 gpio_free(pdata->slots[0].switch_pin);
 550 }
 551
 552 /*
 553  * Start clock to the card
 554  */
 555 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 556 {
 557         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 558                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 559 }
 560
 561 /*
 562  * Stop clock to the card
 563  */
 564 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 565 {
 566         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 567                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 568         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 569                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 570 }
 571
 572 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 573                                   struct mmc_command *cmd)
 574 {
 575         unsigned int irq_mask;
 576
 577         if (host->use_dma)
 578                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 579         else
 580                 irq_mask = INT_EN_MASK;
 581
 582         /* Disable timeout for erases */
 583         if (cmd->opcode == MMC_ERASE)
 584                 irq_mask &= ~DTO_ENABLE;
 585
 586         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 587         OMAP_HSMMC_WRITE(host->base, ISE, host->use_dma ? irq_mask : 0);
 588         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 589 }
 590
 591 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 592 {
 593         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 594         OMAP_HSMMC_WRITE(host->base, IE, 0);
 595         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 596 }
 597
 598 /* Calculate divisor for the given clock frequency */
 599 static u16 calc_divisor(struct mmc_ios *ios)
 600 {
 601         u16 dsor = 0;
 602
 603         if (ios->clock) {
 604                 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
 605                 if (dsor > 250)
 606                         dsor = 250;
 607         }
 608
 609         return dsor;
 610 }
 611
 612 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 613 {
 614         struct mmc_ios *ios = &host->mmc->ios;
 615         unsigned long regval;
 616         unsigned long timeout;
 617
 618         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 619
 620         omap_hsmmc_stop_clock(host);
 621
 622         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 623         regval = regval & ~(CLKD_MASK | DTO_MASK);
 624         regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
 625         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 626         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 627                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 628
 629         /* Wait till the ICS bit is set */
 630         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 631         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 632                 && time_before(jiffies, timeout))
 633                 cpu_relax();
 634
 635         omap_hsmmc_start_clock(host);
 636 }
 637
 638 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 639 {
 640         struct mmc_ios *ios = &host->mmc->ios;
 641         u32 con;
 642
 643         con = OMAP_HSMMC_READ(host->base, CON);
 644         switch (ios->bus_width) {
 645         case MMC_BUS_WIDTH_8:
 646                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 647                 break;
 648         case MMC_BUS_WIDTH_4:
 649                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 650                 OMAP_HSMMC_WRITE(host->base, HCTL,
 651                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 652                 break;
 653         case MMC_BUS_WIDTH_1:
 654                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 655                 OMAP_HSMMC_WRITE(host->base, HCTL,
 656                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 657                 break;
 658         }
 659 }
 660
 661 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 662 {
 663         struct mmc_ios *ios = &host->mmc->ios;
 664         u32 con;
 665
 666         con = OMAP_HSMMC_READ(host->base, CON);
 667         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 668                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 669         else
 670                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 671 }
 672
 673 #ifdef CONFIG_PM
 674
 675 /*
 676  * Restore the MMC host context, if it was lost as result of a
 677  * power state change.
 678  */
 679 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 680 {
 681         struct mmc_ios *ios = &host->mmc->ios;
 682         struct omap_mmc_platform_data *pdata = host->pdata;
 683         int context_loss = 0;
 684         u32 hctl, capa;
 685         unsigned long timeout;
 686
 687         if (pdata->get_context_loss_count) {
 688                 context_loss = pdata->get_context_loss_count(host->dev);
 689                 if (context_loss < 0)
 690                         return 1;
 691         }
 692
 693         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 694                 context_loss == host->context_loss ? "not " : "");
 695         if (host->context_loss == context_loss)
 696                 return 1;
 697
 698         /* Wait for hardware reset */
 699         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 700         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 701                 && time_before(jiffies, timeout))
 702                 ;
 703
 704         /* Do software reset */
 705         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 706         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 707         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 708                 && time_before(jiffies, timeout))
 709                 ;
 710
 711         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 712                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 713
 714         if (host->id == OMAP_MMC1_DEVID) {
 715                 if (host->power_mode != MMC_POWER_OFF &&
 716                     (1 << ios->vdd) <= MMC_VDD_23_24)
 717                         hctl = SDVS18;
 718                 else
 719                         hctl = SDVS30;
 720                 capa = VS30 | VS18;
 721         } else {
 722                 hctl = SDVS18;
 723                 capa = VS18;
 724         }
 725
 726         OMAP_HSMMC_WRITE(host->base, HCTL,
 727                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 728
 729         OMAP_HSMMC_WRITE(host->base, CAPA,
 730                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 731
 732         OMAP_HSMMC_WRITE(host->base, HCTL,
 733                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 734
 735         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 736         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 737                 && time_before(jiffies, timeout))
 738                 ;
 739
 740         omap_hsmmc_disable_irq(host);
 741
 742         /* Do not initialize card-specific things if the power is off */
 743         if (host->power_mode == MMC_POWER_OFF)
 744                 goto out;
 745
 746         omap_hsmmc_set_bus_width(host);
 747
 748         omap_hsmmc_set_clock(host);
 749
 750         omap_hsmmc_set_bus_mode(host);
 751
 752 out:
 753         host->context_loss = context_loss;
 754
 755         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 756         return 0;
 757 }
 758
 759 /*
 760  * Save the MMC host context (store the number of power state changes so far).
 761  */
 762 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 763 {
 764         struct omap_mmc_platform_data *pdata = host->pdata;
 765         int context_loss;
 766
 767         if (pdata->get_context_loss_count) {
 768                 context_loss = pdata->get_context_loss_count(host->dev);
 769                 if (context_loss < 0)
 770                         return;
 771                 host->context_loss = context_loss;
 772         }
 773 }
 774
 775 #else
 776
 777 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 778 {
 779         return 0;
 780 }
 781
 782 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 783 {
 784 }
 785
 786 #endif
 787
 788 /*
 789  * Send init stream sequence to card
 790  * before sending IDLE command
 791  */
 792 static void send_init_stream(struct omap_hsmmc_host *host)
 793 {
 794         int reg = 0;
 795         unsigned long timeout;
 796
 797         if (host->protect_card)
 798                 return;
 799
 800         disable_irq(host->irq);
 801
 802         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 803         OMAP_HSMMC_WRITE(host->base, CON,
 804                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 805         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 806
 807         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 808         while ((reg != CC) && time_before(jiffies, timeout))
 809                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 810
 811         OMAP_HSMMC_WRITE(host->base, CON,
 812                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 813
 814         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 815         OMAP_HSMMC_READ(host->base, STAT);
 816
 817         enable_irq(host->irq);
 818 }
 819
 820 static inline
 821 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 822 {
 823         int r = 1;
 824
 825         if (mmc_slot(host).get_cover_state)
 826                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 827         return r;
 828 }
 829
 830 static ssize_t
 831 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 832                            char *buf)
 833 {
 834         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 835         struct omap_hsmmc_host *host = mmc_priv(mmc);
 836
 837         return sprintf(buf, "%s\n",
 838                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 839 }
 840
 841 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 842
 843 static ssize_t
 844 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 845                         char *buf)
 846 {
 847         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 848         struct omap_hsmmc_host *host = mmc_priv(mmc);
 849
 850         return sprintf(buf, "%s\n", mmc_slot(host).name);
 851 }
 852
 853 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 854
 855 /* for hosts with 35xx erratum 2.1.1.128 */
 856 static ssize_t
 857 omap_hsmmc_show_unsafe_read(struct device *dev, struct device_attribute *attr,
 858                         char *buf)
 859 {
 860         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 861         int val = 0;
 862
 863         if (!(mmc->caps2 & MMC_CAP2_NO_MULTI_READ)) {
 864                 val = 1;
 865                 if (mmc->f_max == OMAP_MMC_MAX_CLOCK)
 866                         val = 2;
 867         }
 868
 869         return sprintf(buf, "%d\n", val);
 870 }
 871
 872 static ssize_t
 873 omap_hsmmc_set_unsafe_read(struct device *dev, struct device_attribute *attr,
 874                 const char *buf, size_t count)
 875 {
 876         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 877         unsigned long val;
 878         int ret;
 879
 880         ret = strict_strtoul(buf, 0, &val);
 881         if (ret)
 882                 return -EINVAL;
 883
 884         switch (val) {
 885         case 0:
 886                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
 887                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
 888                 break;
 889         case 1:
 890                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
 891                 mmc->f_max = 32000000;
 892                 break;
 893         case 2:
 894                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
 895                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
 896                 break;
 897         }
 898
 899         return count;
 900 }
 901 static DEVICE_ATTR(unsafe_read, S_IWUSR | S_IRUGO,
 902         omap_hsmmc_show_unsafe_read, omap_hsmmc_set_unsafe_read);
 903
 904 /*
 905  * Configure the response type and send the cmd.
 906  */
 907 static void
 908 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 909         struct mmc_data *data)
 910 {
 911         int cmdreg = 0, resptype = 0, cmdtype = 0;
 912
 913         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 914                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 915         host->cmd = cmd;
 916
 917         omap_hsmmc_enable_irq(host, cmd);
 918
 919         host->response_busy = 0;
 920         if (cmd->flags & MMC_RSP_PRESENT) {
 921                 if (cmd->flags & MMC_RSP_136)
 922                         resptype = 1;
 923                 else if (cmd->flags & MMC_RSP_BUSY) {
 924                         resptype = 3;
 925                         host->response_busy = 1;
 926                 } else
 927                         resptype = 2;
 928         }
 929
 930         /*
 931          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 932          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 933          * a val of 0x3, rest 0x0.
 934          */
 935         if (cmd == host->mrq->stop)
 936                 cmdtype = 0x3;
 937
 938         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 939
 940         if (data) {
 941                 cmdreg |= DP_SELECT | MSBS | BCE;
 942                 if (data->flags & MMC_DATA_READ)
 943                         cmdreg |= DDIR;
 944                 else
 945                         cmdreg &= ~(DDIR);
 946         }
 947
 948         if (host->use_dma)
 949                 cmdreg |= DMA_EN;
 950
 951         host->req_in_progress = 1;
 952
 953         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 954         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 955 }
 956
 957 static int
 958 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 959 {
 960         if (data->flags & MMC_DATA_WRITE)
 961                 return DMA_TO_DEVICE;
 962         else
 963                 return DMA_FROM_DEVICE;
 964 }
 965
 966 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 967 {
 968         int dma_ch;
 969
 970         spin_lock(&host->irq_lock);
 971         host->req_in_progress = 0;
 972         dma_ch = host->dma_ch;
 973         spin_unlock(&host->irq_lock);
 974
 975         omap_hsmmc_disable_irq(host);
 976         /* Do not complete the request if DMA is still in progress */
 977         if (mrq->data && host->use_dma && dma_ch != -1)
 978                 return;
 979         host->mrq = NULL;
 980         mmc_request_done(host->mmc, mrq);
 981 }
 982
 983 /*
 984  * Notify the transfer complete to MMC core
 985  */
 986 static void
 987 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 988 {
 989         if (!data) {
 990                 struct mmc_request *mrq = host->mrq;
 991
 992                 /* TC before CC from CMD6 - don't know why, but it happens */
 993                 if (host->cmd && host->cmd->opcode == 6 &&
 994                     host->response_busy) {
 995                         host->response_busy = 0;
 996                         return;
 997                 }
 998
 999                 omap_hsmmc_request_done(host, mrq);
1000                 return;
1001         }
1002
1003         host->data = NULL;
1004
1005         if (!data->error)
1006                 data->bytes_xfered += data->blocks * (data->blksz);
1007         else
1008                 data->bytes_xfered = 0;
1009
1010         if (!data->stop) {
1011                 omap_hsmmc_request_done(host, data->mrq);
1012                 return;
1013         }
1014         omap_hsmmc_start_command(host, data->stop, NULL);
1015 }
1016
1017 /*
1018  * Notify the core about command completion
1019  */
1020 static void
1021 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
1022 {
1023         host->cmd = NULL;
1024
1025         if (cmd->flags & MMC_RSP_PRESENT) {
1026                 if (cmd->flags & MMC_RSP_136) {
1027                         /* response type 2 */
1028                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1029                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1030                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1031                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1032                 } else {
1033                         /* response types 1, 1b, 3, 4, 5, 6 */
1034                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1035                 }
1036         }
1037         if ((host->data == NULL && !host->response_busy) || cmd->error)
1038                 omap_hsmmc_request_done(host, cmd->mrq);
1039 }
1040
1041 /*
1042  * DMA clean up for command errors
1043  */
1044 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1045 {
1046         int dma_ch;
1047
1048         host->data->error = errno;
1049
1050         spin_lock(&host->irq_lock);
1051         dma_ch = host->dma_ch;
1052         host->dma_ch = -1;
1053         spin_unlock(&host->irq_lock);
1054
1055         if (host->use_dma && dma_ch != -1) {
1056                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1057                         host->data->sg_len,
1058                         omap_hsmmc_get_dma_dir(host, host->data));
1059                 omap_free_dma(dma_ch);
1060                 host->data->host_cookie = 0;
1061         }
1062         host->data = NULL;
1063 }
1064
1065 /*
1066  * Readable error output
1067  */
1068 #ifdef CONFIG_MMC_DEBUG
1069 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1070 {
1071         /* --- means reserved bit without definition at documentation */
1072         static const char *omap_hsmmc_status_bits[] = {
1073                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1074                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1075                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1076                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1077         };
1078         char res[256];
1079         char *buf = res;
1080         int len, i;
1081
1082         len = sprintf(buf, "MMC IRQ 0x%x :", status);
1083         buf += len;
1084
1085         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1086                 if (status & (1 << i)) {
1087                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1088                         buf += len;
1089                 }
1090
1091         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1092 }
1093 #else
1094 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1095                                              u32 status)
1096 {
1097 }
1098 #endif  /* CONFIG_MMC_DEBUG */
1099
1100 /*
1101  * MMC controller internal state machines reset
1102  *
1103  * Used to reset command or data internal state machines, using respectively
1104  *  SRC or SRD bit of SYSCTL register
1105  * Can be called from interrupt context
1106  */
1107 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1108                                                    unsigned long bit)
1109 {
1110         unsigned long i = 0;
1111         unsigned long limit = (loops_per_jiffy *
1112                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
1113
1114         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1115                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1116
1117         /*
1118          * OMAP4 ES2 and greater has an updated reset logic.
1119          * Monitor a 0->1 transition first
1120          */
1121         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1122                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1123                                         && (i++ < limit))
1124                         cpu_relax();
1125         }
1126         i = 0;
1127
1128         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1129                 (i++ < limit))
1130                 cpu_relax();
1131
1132         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1133                 dev_err(mmc_dev(host->mmc),
1134                         "Timeout waiting on controller reset in %s\n",
1135                         __func__);
1136 }
1137
1138 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1139 {
1140         struct mmc_data *data;
1141         int end_cmd = 0, end_trans = 0;
1142
1143         if (unlikely(!host->req_in_progress)) {
1144                 OMAP_HSMMC_WRITE(host->base, STAT, status);
1145                 return;
1146         }
1147
1148         data = host->data;
1149         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1150
1151         if (unlikely(status & ERR)) {
1152                 omap_hsmmc_dbg_report_irq(host, status);
1153                 if ((status & CMD_TIMEOUT) ||
1154                         (status & CMD_CRC)) {
1155                         if (host->cmd) {
1156                                 if (status & CMD_TIMEOUT) {
1157                                         omap_hsmmc_reset_controller_fsm(host,
1158                                                                         SRC);
1159                                         host->cmd->error = -ETIMEDOUT;
1160                                 } else {
1161                                         host->cmd->error = -EILSEQ;
1162                                 }
1163                                 end_cmd = 1;
1164                         }
1165                         if (host->data || host->response_busy) {
1166                                 if (host->data)
1167                                         omap_hsmmc_dma_cleanup(host,
1168                                                                 -ETIMEDOUT);
1169                                 host->response_busy = 0;
1170                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1171                         }
1172                 }
1173                 if ((status & DATA_TIMEOUT) ||
1174                         (status & DATA_CRC)) {
1175                         if (host->data || host->response_busy) {
1176                                 int err = (status & DATA_TIMEOUT) ?
1177                                                 -ETIMEDOUT : -EILSEQ;
1178
1179                                 if (host->data)
1180                                         omap_hsmmc_dma_cleanup(host, err);
1181                                 else
1182                                         host->mrq->cmd->error = err;
1183                                 host->response_busy = 0;
1184                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1185                                 end_trans = 1;
1186                         }
1187                 }
1188                 if (status & CARD_ERR) {
1189                         dev_dbg(mmc_dev(host->mmc),
1190                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1191                         if (host->cmd)
1192                                 end_cmd = 1;
1193                         if (host->data)
1194                                 end_trans = 1;
1195                 }
1196         }
1197
1198         OMAP_HSMMC_WRITE(host->base, STAT, status);
1199
1200         if (end_cmd || ((status & CC) && host->cmd))
1201                 omap_hsmmc_cmd_done(host, host->cmd);
1202         if ((end_trans || (status & TC)) && host->mrq)
1203                 omap_hsmmc_xfer_done(host, data);
1204 }
1205
1206 /*
1207  * MMC controller IRQ handler
1208  */
1209 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1210 {
1211         struct omap_hsmmc_host *host = dev_id;
1212         int status;
1213
1214         status = OMAP_HSMMC_READ(host->base, STAT);
1215         do {
1216                 omap_hsmmc_do_irq(host, status);
1217                 /* Flush posted write */
1218                 status = OMAP_HSMMC_READ(host->base, STAT);
1219         } while (status & INT_EN_MASK);
1220
1221         return IRQ_HANDLED;
1222 }
1223
1224 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1225 {
1226         unsigned long i;
1227
1228         OMAP_HSMMC_WRITE(host->base, HCTL,
1229                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1230         for (i = 0; i < loops_per_jiffy; i++) {
1231                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1232                         break;
1233                 cpu_relax();
1234         }
1235 }
1236
1237 /*
1238  * Switch MMC interface voltage ... only relevant for MMC1.
1239  *
1240  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1241  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1242  * Some chips, like eMMC ones, use internal transceivers.
1243  */
1244 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1245 {
1246         u32 reg_val = 0;
1247         int ret;
1248
1249         /* Disable the clocks */
1250         pm_runtime_put_sync(host->dev);
1251         if (host->got_dbclk)
1252                 clk_disable(host->dbclk);
1253
1254         /* Turn the power off */
1255         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1256
1257         /* Turn the power ON with given VDD 1.8 or 3.0v */
1258         if (!ret)
1259                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1260                                                vdd);
1261         pm_runtime_get_sync(host->dev);
1262         if (host->got_dbclk)
1263                 clk_enable(host->dbclk);
1264
1265         if (ret != 0)
1266                 goto err;
1267
1268         OMAP_HSMMC_WRITE(host->base, HCTL,
1269                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1270         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1271
1272         /*
1273          * If a MMC dual voltage card is detected, the set_ios fn calls
1274          * this fn with VDD bit set for 1.8V. Upon card removal from the
1275          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1276          *
1277          * Cope with a bit of slop in the range ... per data sheets:
1278          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1279          *    but recommended values are 1.71V to 1.89V
1280          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1281          *    but recommended values are 2.7V to 3.3V
1282          *
1283          * Board setup code shouldn't permit anything very out-of-range.
1284          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1285          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1286          */
1287         if ((1 << vdd) <= MMC_VDD_23_24)
1288                 reg_val |= SDVS18;
1289         else
1290                 reg_val |= SDVS30;
1291
1292         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1293         set_sd_bus_power(host);
1294
1295         return 0;
1296 err:
1297         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1298         return ret;
1299 }
1300
1301 /* Protect the card while the cover is open */
1302 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1303 {
1304         if (!mmc_slot(host).get_cover_state)
1305                 return;
1306
1307         host->reqs_blocked = 0;
1308         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1309                 if (host->protect_card) {
1310                         pr_info("%s: cover is closed, "
1311                                          "card is now accessible\n",
1312                                          mmc_hostname(host->mmc));
1313                         host->protect_card = 0;
1314                 }
1315         } else {
1316                 if (!host->protect_card) {
1317                         pr_info("%s: cover is open, "
1318                                          "card is now inaccessible\n",
1319                                          mmc_hostname(host->mmc));
1320                         host->protect_card = 1;
1321                 }
1322         }
1323 }
1324
1325 /*
1326  * irq handler to notify the core about card insertion/removal
1327  */
1328 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1329 {
1330         struct omap_hsmmc_host *host = dev_id;
1331         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1332         int carddetect;
1333
1334         if (host->suspended)
1335                 return IRQ_HANDLED;
1336
1337         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1338
1339         if (slot->card_detect)
1340                 carddetect = slot->card_detect(host->dev, host->slot_id);
1341         else {
1342                 omap_hsmmc_protect_card(host);
1343                 carddetect = -ENOSYS;
1344         }
1345
1346         if (carddetect)
1347                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1348         else
1349                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1350         return IRQ_HANDLED;
1351 }
1352
1353 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1354                                      struct mmc_data *data)
1355 {
1356         int sync_dev;
1357
1358         if (data->flags & MMC_DATA_WRITE)
1359                 sync_dev = host->dma_line_tx;
1360         else
1361                 sync_dev = host->dma_line_rx;
1362         return sync_dev;
1363 }
1364
1365 static void omap_hsmmc_config_dma_params_once(struct omap_hsmmc_host *host,
1366                                               struct mmc_data *data,
1367                                               int dma_ch)
1368 {
1369         if (data->flags & MMC_DATA_WRITE) {
1370                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1371                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1372                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_16);
1373                 omap_set_dma_src_data_pack(dma_ch, 1);
1374         } else {
1375                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1376                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1377                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_16);
1378                 omap_set_dma_dest_data_pack(dma_ch, 1);
1379                 omap_set_dma_write_mode(dma_ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
1380         }
1381 }
1382
1383 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1384                                        struct mmc_data *data,
1385                                        struct scatterlist *sgl)
1386 {
1387         int blksz, nblk, dma_ch, sync;
1388
1389         dma_ch = host->dma_ch;
1390         if (data->flags & MMC_DATA_WRITE) {
1391                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1392                         sg_dma_address(sgl), 0, 0);
1393                 sync = OMAP_DMA_DST_SYNC_PREFETCH;
1394         } else {
1395                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1396                         sg_dma_address(sgl), 0, 0);
1397                 sync = OMAP_DMA_SRC_SYNC;
1398         }
1399
1400         blksz = host->data->blksz;
1401         nblk = sg_dma_len(sgl) / blksz;
1402
1403         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1404                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1405                         omap_hsmmc_get_dma_sync_dev(host, data), sync);
1406
1407         omap_start_dma(dma_ch);
1408 }
1409
1410 /*
1411  * DMA call back function
1412  */
1413 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1414 {
1415         struct omap_hsmmc_host *host = cb_data;
1416         struct mmc_data *data;
1417         int dma_ch, req_in_progress;
1418
1419         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1420                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1421                         ch_status);
1422                 return;
1423         }
1424
1425         spin_lock(&host->irq_lock);
1426         if (host->dma_ch < 0) {
1427                 spin_unlock(&host->irq_lock);
1428                 return;
1429         }
1430
1431         data = host->mrq->data;
1432         host->dma_sg_idx++;
1433         if (host->dma_sg_idx < host->dma_len) {
1434                 /* Fire up the next transfer. */
1435                 omap_hsmmc_config_dma_params(host, data,
1436                                            data->sg + host->dma_sg_idx);
1437                 spin_unlock(&host->irq_lock);
1438                 return;
1439         }
1440
1441         if (!data->host_cookie)
1442                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1443                              omap_hsmmc_get_dma_dir(host, data));
1444
1445         req_in_progress = host->req_in_progress;
1446         dma_ch = host->dma_ch;
1447         host->dma_ch = -1;
1448         spin_unlock(&host->irq_lock);
1449
1450         omap_free_dma(dma_ch);
1451
1452         /* If DMA has finished after TC, complete the request */
1453         if (!req_in_progress) {
1454                 struct mmc_request *mrq = host->mrq;
1455
1456                 host->mrq = NULL;
1457                 mmc_request_done(host->mmc, mrq);
1458         }
1459 }
1460
1461 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1462                                        struct mmc_data *data,
1463                                        struct omap_hsmmc_next *next)
1464 {
1465         int dma_len;
1466
1467         if (unlikely(!next && data->host_cookie &&
1468             data->host_cookie != host->next_data.cookie)) {
1469                 pr_warning("[%s] invalid cookie: data->host_cookie %d"
1470                        " host->next_data.cookie %d\n",
1471                        __func__, data->host_cookie, host->next_data.cookie);
1472                 data->host_cookie = 0;
1473         }
1474
1475         /* Check if next job is already prepared */
1476         if (next ||
1477             (!next && data->host_cookie != host->next_data.cookie)) {
1478                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1479                                      data->sg_len,
1480                                      omap_hsmmc_get_dma_dir(host, data));
1481
1482         } else {
1483                 dma_len = host->next_data.dma_len;
1484                 host->next_data.dma_len = 0;
1485         }
1486
1487
1488         if (unlikely(dma_len == 0))
1489                 return -EINVAL;
1490
1491         if (next) {
1492                 next->dma_len = dma_len;
1493                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1494         } else
1495                 host->dma_len = dma_len;
1496
1497         return 0;
1498 }
1499
1500 /*
1501  * Routine to configure and start DMA for the MMC card
1502  */
1503 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1504                                         struct mmc_request *req)
1505 {
1506         int dma_ch = 0, ret = 0, i;
1507         struct mmc_data *data = req->data;
1508
1509         /* Sanity check: all the SG entries must be aligned by block size. */
1510         for (i = 0; i < data->sg_len; i++) {
1511                 struct scatterlist *sgl;
1512
1513                 sgl = data->sg + i;
1514                 if (unlikely(sgl->length % data->blksz))
1515                         return -EINVAL;
1516         }
1517         if (unlikely((data->blksz % 4) != 0))
1518                 /* REVISIT: The MMC buffer increments only when MSB is written.
1519                  * Return error for blksz which is non multiple of four.
1520                  */
1521                 return -EINVAL;
1522
1523         BUG_ON(host->dma_ch != -1);
1524
1525         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1526                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1527         if (unlikely(ret != 0)) {
1528                 dev_err(mmc_dev(host->mmc),
1529                         "%s: omap_request_dma() failed with %d\n",
1530                         mmc_hostname(host->mmc), ret);
1531                 return ret;
1532         }
1533         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1534         if (unlikely(ret))
1535                 return ret;
1536
1537         host->dma_ch = dma_ch;
1538         host->dma_sg_idx = 0;
1539
1540         omap_hsmmc_config_dma_params_once(host, data, dma_ch);
1541         omap_hsmmc_config_dma_params(host, data, data->sg);
1542
1543         return 0;
1544 }
1545
1546 /* pandora wifi small transfer hack */
1547 static int check_mmc3_dma_hack(struct omap_hsmmc_host *host,
1548                                struct mmc_request *req)
1549 {
1550         if (req->data != NULL && req->data->sg_len == 1
1551             && req->data->sg->length <= 16)
1552                 return 0;
1553         else
1554                 return 1;
1555 }
1556
1557 /*
1558  * Configure block length for MMC/SD cards and initiate the transfer.
1559  */
1560 static int
1561 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1562 {
1563         int ret;
1564         host->data = req->data;
1565
1566         if (req->data == NULL) {
1567                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1568                 return 0;
1569         }
1570
1571         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1572                                         | (req->data->blocks << 16));
1573
1574         if (host->use_dma) {
1575                 ret = omap_hsmmc_start_dma_transfer(host, req);
1576                 if (ret != 0) {
1577                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1578                         return ret;
1579                 }
1580         }
1581         return 0;
1582 }
1583
1584 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1585                                 int err)
1586 {
1587         struct omap_hsmmc_host *host = mmc_priv(mmc);
1588         struct mmc_data *data = mrq->data;
1589
1590         if (host->use_dma) {
1591                 if (data->host_cookie)
1592                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1593                                      data->sg_len,
1594                                      omap_hsmmc_get_dma_dir(host, data));
1595                 data->host_cookie = 0;
1596         }
1597 }
1598
1599 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1600                                bool is_first_req)
1601 {
1602         struct omap_hsmmc_host *host = mmc_priv(mmc);
1603         int use_dma = host->use_dma;
1604
1605         if (mrq->data->host_cookie) {
1606                 mrq->data->host_cookie = 0;
1607                 return ;
1608         }
1609
1610         if (host->id == OMAP_MMC3_DEVID)
1611                 use_dma = check_mmc3_dma_hack(host, mrq);
1612         if (use_dma)
1613                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1614                                                 &host->next_data))
1615                         mrq->data->host_cookie = 0;
1616 }
1617
1618 #define BWR (1 << 4)
1619 #define BRR (1 << 5)
1620
1621 static noinline void omap_hsmmc_request_do_pio(struct mmc_host *mmc,
1622         struct mmc_request *req)
1623 {
1624         struct omap_hsmmc_host *host = mmc_priv(mmc);
1625         u32 *data = sg_virt(req->data->sg);
1626         u32 len = req->data->sg->length;
1627         int stat;
1628         int i;
1629
1630         for (i = 0; i < 10000000; i++) {
1631                 stat = OMAP_HSMMC_READ(host->base, STAT);
1632                 if (stat == 0)
1633                         continue;
1634
1635                 //dev_err(mmc_dev(host->mmc), "stat %x, l %d\n", stat, i);
1636
1637                 if (stat & (DATA_TIMEOUT | DATA_CRC))
1638                         omap_hsmmc_reset_controller_fsm(host, SRD);
1639
1640                 if (stat & ERR) {
1641                         req->cmd->error =
1642                         req->data->error = -EINVAL; // ?
1643                         omap_hsmmc_xfer_done(host, host->data);
1644                         return;
1645                 }
1646
1647                 if (req->data->flags & MMC_DATA_WRITE) {
1648                         while (len > 0 && (stat & BWR)) {
1649                                 OMAP_HSMMC_WRITE(host->base, DATA, *data++);
1650                                 len -= 4;
1651                         }
1652                 } else {
1653                         while (len > 0 && (stat & BRR)) {
1654                                 *data++ = OMAP_HSMMC_READ(host->base, DATA);
1655                                 len -= 4;
1656                         }
1657                 }
1658
1659                 if ((stat & CC) && host->cmd)
1660                         omap_hsmmc_cmd_done(host, host->cmd);
1661                 if ((stat & TC) && host->mrq) {
1662                         omap_hsmmc_xfer_done(host, host->data);
1663                         break;
1664                 }
1665         }
1666
1667         if (len > 0) {
1668                 req->cmd->error =
1669                 req->data->error = -ETIMEDOUT;
1670                 omap_hsmmc_xfer_done(host, req->data);
1671         }
1672 }
1673
1674 /*
1675  * Request function. for read/write operation
1676  */
1677 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1678 {
1679         struct omap_hsmmc_host *host = mmc_priv(mmc);
1680         int err;
1681
1682         BUG_ON(host->req_in_progress);
1683         BUG_ON(host->dma_ch != -1);
1684         if (unlikely(host->protect_card)) {
1685                 if (host->reqs_blocked < 3) {
1686                         /*
1687                          * Ensure the controller is left in a consistent
1688                          * state by resetting the command and data state
1689                          * machines.
1690                          */
1691                         omap_hsmmc_reset_controller_fsm(host, SRD);
1692                         omap_hsmmc_reset_controller_fsm(host, SRC);
1693                         host->reqs_blocked += 1;
1694                 }
1695                 req->cmd->error = -EBADF;
1696                 if (req->data)
1697                         req->data->error = -EBADF;
1698                 req->cmd->retries = 0;
1699                 mmc_request_done(mmc, req);
1700                 return;
1701         } else if (host->reqs_blocked)
1702                 host->reqs_blocked = 0;
1703
1704         /* pandora wifi hack... */
1705         if (host->id == OMAP_MMC3_DEVID)
1706                 host->use_dma = check_mmc3_dma_hack(host, req);
1707
1708         WARN_ON(host->mrq != NULL);
1709         host->mrq = req;
1710         err = omap_hsmmc_prepare_data(host, req);
1711         if (unlikely(err)) {
1712                 req->cmd->error = err;
1713                 if (req->data)
1714                         req->data->error = err;
1715                 host->mrq = NULL;
1716                 mmc_request_done(mmc, req);
1717                 return;
1718         }
1719
1720         omap_hsmmc_start_command(host, req->cmd, req->data);
1721
1722         if (host->use_dma == 0)
1723                 omap_hsmmc_request_do_pio(mmc, req);
1724 }
1725
1726 /* Routine to configure clock values. Exposed API to core */
1727 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1728 {
1729         struct omap_hsmmc_host *host = mmc_priv(mmc);
1730         int do_send_init_stream = 0;
1731
1732         pm_runtime_get_sync(host->dev);
1733
1734         if (ios->power_mode != host->power_mode) {
1735                 switch (ios->power_mode) {
1736                 case MMC_POWER_OFF:
1737                         mmc_slot(host).set_power(host->dev, host->slot_id,
1738                                                  0, 0);
1739                         host->vdd = 0;
1740                         break;
1741                 case MMC_POWER_UP:
1742                         mmc_slot(host).set_power(host->dev, host->slot_id,
1743                                                  1, ios->vdd);
1744                         host->vdd = ios->vdd;
1745                         break;
1746                 case MMC_POWER_ON:
1747                         do_send_init_stream = 1;
1748                         break;
1749                 }
1750                 host->power_mode = ios->power_mode;
1751         }
1752
1753         /* FIXME: set registers based only on changes to ios */
1754
1755         omap_hsmmc_set_bus_width(host);
1756
1757         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1758                 /* Only MMC1 can interface at 3V without some flavor
1759                  * of external transceiver; but they all handle 1.8V.
1760                  */
1761                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1762                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1763                                 /*
1764                                  * The mmc_select_voltage fn of the core does
1765                                  * not seem to set the power_mode to
1766                                  * MMC_POWER_UP upon recalculating the voltage.
1767                                  * vdd 1.8v.
1768                                  */
1769                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1770                                 dev_dbg(mmc_dev(host->mmc),
1771                                                 "Switch operation failed\n");
1772                 }
1773         }
1774
1775         omap_hsmmc_set_clock(host);
1776
1777         if (do_send_init_stream)
1778                 send_init_stream(host);
1779
1780         omap_hsmmc_set_bus_mode(host);
1781
1782         pm_runtime_put_autosuspend(host->dev);
1783 }
1784
1785 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1786 {
1787         struct omap_hsmmc_host *host = mmc_priv(mmc);
1788
1789         if (!mmc_slot(host).card_detect)
1790                 return -ENOSYS;
1791         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1792 }
1793
1794 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1795 {
1796         struct omap_hsmmc_host *host = mmc_priv(mmc);
1797
1798         if (!mmc_slot(host).get_ro)
1799                 return -ENOSYS;
1800         return mmc_slot(host).get_ro(host->dev, 0);
1801 }
1802
1803 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1804 {
1805         struct omap_hsmmc_host *host = mmc_priv(mmc);
1806
1807         if (mmc_slot(host).init_card)
1808                 mmc_slot(host).init_card(card);
1809 }
1810
1811 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1812 {
1813         u32 hctl, capa, value;
1814
1815         /* Only MMC1 supports 3.0V */
1816         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1817                 hctl = SDVS30;
1818                 capa = VS30 | VS18;
1819         } else {
1820                 hctl = SDVS18;
1821                 capa = VS18;
1822         }
1823
1824         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1825         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1826
1827         value = OMAP_HSMMC_READ(host->base, CAPA);
1828         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1829
1830         /* Set the controller to AUTO IDLE mode */
1831         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1832         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1833
1834         /* Set SD bus power bit */
1835         set_sd_bus_power(host);
1836 }
1837
1838 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1839 {
1840         struct omap_hsmmc_host *host = mmc_priv(mmc);
1841
1842         pm_runtime_get_sync(host->dev);
1843
1844         return 0;
1845 }
1846
1847 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1848 {
1849         struct omap_hsmmc_host *host = mmc_priv(mmc);
1850
1851         pm_runtime_mark_last_busy(host->dev);
1852         pm_runtime_put_autosuspend(host->dev);
1853
1854         return 0;
1855 }
1856
1857 static const struct mmc_host_ops omap_hsmmc_ops = {
1858         .enable = omap_hsmmc_enable_fclk,
1859         .disable = omap_hsmmc_disable_fclk,
1860         .post_req = omap_hsmmc_post_req,
1861         .pre_req = omap_hsmmc_pre_req,
1862         .request = omap_hsmmc_request,
1863         .set_ios = omap_hsmmc_set_ios,
1864         .get_cd = omap_hsmmc_get_cd,
1865         .get_ro = omap_hsmmc_get_ro,
1866         .init_card = omap_hsmmc_init_card,
1867         /* NYET -- enable_sdio_irq */
1868 };
1869
1870 #ifdef CONFIG_DEBUG_FS
1871
1872 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1873 {
1874         struct mmc_host *mmc = s->private;
1875         struct omap_hsmmc_host *host = mmc_priv(mmc);
1876         int context_loss = 0;
1877
1878         if (host->pdata->get_context_loss_count)
1879                 context_loss = host->pdata->get_context_loss_count(host->dev);
1880
1881         seq_printf(s, "mmc%d:\n"
1882                         " enabled:\t%d\n"
1883                         " dpm_state:\t%d\n"
1884                         " nesting_cnt:\t%d\n"
1885                         " ctx_loss:\t%d:%d\n"
1886                         "\nregs:\n",
1887                         mmc->index, mmc->enabled ? 1 : 0,
1888                         host->dpm_state, mmc->nesting_cnt,
1889                         host->context_loss, context_loss);
1890
1891         if (host->suspended) {
1892                 seq_printf(s, "host suspended, can't read registers\n");
1893                 return 0;
1894         }
1895
1896         pm_runtime_get_sync(host->dev);
1897
1898         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1899                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1900         seq_printf(s, "CON:\t\t0x%08x\n",
1901                         OMAP_HSMMC_READ(host->base, CON));
1902         seq_printf(s, "HCTL:\t\t0x%08x\n",
1903                         OMAP_HSMMC_READ(host->base, HCTL));
1904         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1905                         OMAP_HSMMC_READ(host->base, SYSCTL));
1906         seq_printf(s, "IE:\t\t0x%08x\n",
1907                         OMAP_HSMMC_READ(host->base, IE));
1908         seq_printf(s, "ISE:\t\t0x%08x\n",
1909                         OMAP_HSMMC_READ(host->base, ISE));
1910         seq_printf(s, "CAPA:\t\t0x%08x\n",
1911                         OMAP_HSMMC_READ(host->base, CAPA));
1912
1913         pm_runtime_mark_last_busy(host->dev);
1914         pm_runtime_put_autosuspend(host->dev);
1915
1916         return 0;
1917 }
1918
1919 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1920 {
1921         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1922 }
1923
1924 static const struct file_operations mmc_regs_fops = {
1925         .open           = omap_hsmmc_regs_open,
1926         .read           = seq_read,
1927         .llseek         = seq_lseek,
1928         .release        = single_release,
1929 };
1930
1931 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1932 {
1933         if (mmc->debugfs_root)
1934                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1935                         mmc, &mmc_regs_fops);
1936 }
1937
1938 #else
1939
1940 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1941 {
1942 }
1943
1944 #endif
1945
1946 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1947 {
1948         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1949         struct mmc_host *mmc;
1950         struct omap_hsmmc_host *host = NULL;
1951         struct resource *res;
1952         int ret, irq;
1953
1954         if (pdata == NULL) {
1955                 dev_err(&pdev->dev, "Platform Data is missing\n");
1956                 return -ENXIO;
1957         }
1958
1959         if (pdata->nr_slots == 0) {
1960                 dev_err(&pdev->dev, "No Slots\n");
1961                 return -ENXIO;
1962         }
1963
1964         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1965         irq = platform_get_irq(pdev, 0);
1966         if (res == NULL || irq < 0)
1967                 return -ENXIO;
1968
1969         res->start += pdata->reg_offset;
1970         res->end += pdata->reg_offset;
1971         res = request_mem_region(res->start, resource_size(res), pdev->name);
1972         if (res == NULL)
1973                 return -EBUSY;
1974
1975         ret = omap_hsmmc_gpio_init(pdata);
1976         if (ret)
1977                 goto err;
1978
1979         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1980         if (!mmc) {
1981                 ret = -ENOMEM;
1982                 goto err_alloc;
1983         }
1984
1985         host            = mmc_priv(mmc);
1986         host->mmc       = mmc;
1987         host->pdata     = pdata;
1988         host->dev       = &pdev->dev;
1989         host->use_dma   = 1;
1990         host->dev->dma_mask = &pdata->dma_mask;
1991         host->dma_ch    = -1;
1992         host->irq       = irq;
1993         host->id        = pdev->id;
1994         host->slot_id   = 0;
1995         host->mapbase   = res->start;
1996         host->base      = ioremap(host->mapbase, SZ_4K);
1997         host->power_mode = MMC_POWER_OFF;
1998         host->next_data.cookie = 1;
1999
2000         platform_set_drvdata(pdev, host);
2001
2002         mmc->ops        = &omap_hsmmc_ops;
2003
2004         /*
2005          * If regulator_disable can only put vcc_aux to sleep then there is
2006          * no off state.
2007          */
2008         if (mmc_slot(host).vcc_aux_disable_is_sleep)
2009                 mmc_slot(host).no_off = 1;
2010
2011         mmc->f_min      = OMAP_MMC_MIN_CLOCK;
2012         mmc->f_max      = OMAP_MMC_MAX_CLOCK;
2013
2014         spin_lock_init(&host->irq_lock);
2015
2016         host->fclk = clk_get(&pdev->dev, "fck");
2017         if (IS_ERR(host->fclk)) {
2018                 ret = PTR_ERR(host->fclk);
2019                 host->fclk = NULL;
2020                 goto err1;
2021         }
2022
2023         omap_hsmmc_context_save(host);
2024
2025         mmc->caps |= MMC_CAP_DISABLE;
2026
2027         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2028                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2029                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
2030         }
2031
2032         pm_runtime_enable(host->dev);
2033         pm_runtime_get_sync(host->dev);
2034         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2035         pm_runtime_use_autosuspend(host->dev);
2036
2037         if (cpu_is_omap2430()) {
2038                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2039                 /*
2040                  * MMC can still work without debounce clock.
2041                  */
2042                 if (IS_ERR(host->dbclk))
2043                         dev_warn(mmc_dev(host->mmc),
2044                                 "Failed to get debounce clock\n");
2045                 else
2046                         host->got_dbclk = 1;
2047
2048                 if (host->got_dbclk)
2049                         if (clk_enable(host->dbclk) != 0)
2050                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2051                                                         " clk failed\n");
2052         }
2053
2054         /* Since we do only SG emulation, we can have as many segs
2055          * as we want. */
2056         mmc->max_segs = 1024;
2057
2058         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2059         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2060         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2061         mmc->max_seg_size = mmc->max_req_size;
2062
2063         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2064                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2065
2066         mmc->caps |= mmc_slot(host).caps;
2067         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2068                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2069
2070         if (mmc_slot(host).nonremovable)
2071                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2072
2073         omap_hsmmc_conf_bus_power(host);
2074
2075         /* Select DMA lines */
2076         switch (host->id) {
2077         case OMAP_MMC1_DEVID:
2078                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2079                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2080                 break;
2081         case OMAP_MMC2_DEVID:
2082                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2083                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2084                 break;
2085         case OMAP_MMC3_DEVID:
2086                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2087                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2088                 break;
2089         case OMAP_MMC4_DEVID:
2090                 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2091                 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2092                 break;
2093         case OMAP_MMC5_DEVID:
2094                 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2095                 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2096                 break;
2097         default:
2098                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2099                 goto err_irq;
2100         }
2101
2102         /* Request IRQ for MMC operations */
2103         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
2104                         mmc_hostname(mmc), host);
2105         if (ret) {
2106                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2107                 goto err_irq;
2108         }
2109
2110         if (pdata->init != NULL) {
2111                 if (pdata->init(&pdev->dev) != 0) {
2112                         dev_dbg(mmc_dev(host->mmc),
2113                                 "Unable to configure MMC IRQs\n");
2114                         goto err_irq_cd_init;
2115                 }
2116         }
2117
2118         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2119                 ret = omap_hsmmc_reg_get(host);
2120                 if (ret)
2121                         goto err_reg;
2122                 host->use_reg = 1;
2123         }
2124
2125         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2126
2127         /* Request IRQ for card detect */
2128         if ((mmc_slot(host).card_detect_irq)) {
2129                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
2130                                            NULL,
2131                                            omap_hsmmc_detect,
2132                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2133                                            mmc_hostname(mmc), host);
2134                 if (ret) {
2135                         dev_dbg(mmc_dev(host->mmc),
2136                                 "Unable to grab MMC CD IRQ\n");
2137                         goto err_irq_cd;
2138                 }
2139                 pdata->suspend = omap_hsmmc_suspend_cdirq;
2140                 pdata->resume = omap_hsmmc_resume_cdirq;
2141         }
2142
2143         omap_hsmmc_disable_irq(host);
2144
2145         omap_hsmmc_protect_card(host);
2146
2147         mmc_add_host(mmc);
2148
2149         if (mmc_slot(host).name != NULL) {
2150                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2151                 if (ret < 0)
2152                         goto err_slot_name;
2153         }
2154         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2155                 ret = device_create_file(&mmc->class_dev,
2156                                         &dev_attr_cover_switch);
2157                 if (ret < 0)
2158                         goto err_slot_name;
2159         }
2160
2161         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2162                 ret = device_create_file(&mmc->class_dev, &dev_attr_unsafe_read);
2163
2164                 /* MMC_CAP2_NO_MULTI_READ makes it crawl, try a different workaround */
2165                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
2166                 mmc->max_segs = 1;
2167                 mmc->f_max = 32000000;
2168         }
2169
2170         omap_hsmmc_debugfs(mmc);
2171         pm_runtime_mark_last_busy(host->dev);
2172         pm_runtime_put_autosuspend(host->dev);
2173
2174         return 0;
2175
2176 err_slot_name:
2177         mmc_remove_host(mmc);
2178         free_irq(mmc_slot(host).card_detect_irq, host);
2179 err_irq_cd:
2180         if (host->use_reg)
2181                 omap_hsmmc_reg_put(host);
2182 err_reg:
2183         if (host->pdata->cleanup)
2184                 host->pdata->cleanup(&pdev->dev);
2185 err_irq_cd_init:
2186         free_irq(host->irq, host);
2187 err_irq:
2188         pm_runtime_mark_last_busy(host->dev);
2189         pm_runtime_put_autosuspend(host->dev);
2190         clk_put(host->fclk);
2191         if (host->got_dbclk) {
2192                 clk_disable(host->dbclk);
2193                 clk_put(host->dbclk);
2194         }
2195 err1:
2196         iounmap(host->base);
2197         platform_set_drvdata(pdev, NULL);
2198         mmc_free_host(mmc);
2199 err_alloc:
2200         omap_hsmmc_gpio_free(pdata);
2201 err:
2202         release_mem_region(res->start, resource_size(res));
2203         return ret;
2204 }
2205
2206 static int omap_hsmmc_remove(struct platform_device *pdev)
2207 {
2208         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2209         struct resource *res;
2210
2211         if (host) {
2212                 pm_runtime_get_sync(host->dev);
2213                 mmc_remove_host(host->mmc);
2214                 if (host->use_reg)
2215                         omap_hsmmc_reg_put(host);
2216                 if (host->pdata->cleanup)
2217                         host->pdata->cleanup(&pdev->dev);
2218                 free_irq(host->irq, host);
2219                 if (mmc_slot(host).card_detect_irq)
2220                         free_irq(mmc_slot(host).card_detect_irq, host);
2221
2222                 pm_runtime_put_sync(host->dev);
2223                 pm_runtime_disable(host->dev);
2224                 clk_put(host->fclk);
2225                 if (host->got_dbclk) {
2226                         clk_disable(host->dbclk);
2227                         clk_put(host->dbclk);
2228                 }
2229
2230                 mmc_free_host(host->mmc);
2231                 iounmap(host->base);
2232                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2233         }
2234
2235         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2236         if (res)
2237                 release_mem_region(res->start, resource_size(res));
2238         platform_set_drvdata(pdev, NULL);
2239
2240         return 0;
2241 }
2242
2243 #ifdef CONFIG_PM
2244 static int omap_hsmmc_suspend(struct device *dev)
2245 {
2246         int ret = 0;
2247         struct platform_device *pdev = to_platform_device(dev);
2248         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2249
2250         if (host && host->suspended)
2251                 return 0;
2252
2253         if (host) {
2254                 pm_runtime_get_sync(host->dev);
2255                 host->suspended = 1;
2256                 if (host->pdata->suspend) {
2257                         ret = host->pdata->suspend(&pdev->dev,
2258                                                         host->slot_id);
2259                         if (ret) {
2260                                 dev_dbg(mmc_dev(host->mmc),
2261                                         "Unable to handle MMC board"
2262                                         " level suspend\n");
2263                                 host->suspended = 0;
2264                                 return ret;
2265                         }
2266                 }
2267                 ret = mmc_suspend_host(host->mmc);
2268
2269                 if (ret == 0) {
2270                         omap_hsmmc_disable_irq(host);
2271                         OMAP_HSMMC_WRITE(host->base, HCTL,
2272                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2273                         if (host->got_dbclk)
2274                                 clk_disable(host->dbclk);
2275                 } else {
2276                         host->suspended = 0;
2277                         if (host->pdata->resume) {
2278                                 if (host->pdata->resume(&pdev->dev, host->slot_id))
2279                                         dev_dbg(mmc_dev(host->mmc),
2280                                                 "Unmask interrupt failed\n");
2281                         }
2282                 }
2283                 pm_runtime_put_sync(host->dev);
2284         }
2285         return ret;
2286 }
2287
2288 /* Routine to resume the MMC device */
2289 static int omap_hsmmc_resume(struct device *dev)
2290 {
2291         int ret = 0;
2292         struct platform_device *pdev = to_platform_device(dev);
2293         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2294
2295         if (host && !host->suspended)
2296                 return 0;
2297
2298         if (host) {
2299                 pm_runtime_get_sync(host->dev);
2300
2301                 if (host->got_dbclk)
2302                         clk_enable(host->dbclk);
2303
2304                 omap_hsmmc_conf_bus_power(host);
2305
2306                 if (host->pdata->resume) {
2307                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2308                         if (ret)
2309                                 dev_dbg(mmc_dev(host->mmc),
2310                                         "Unmask interrupt failed\n");
2311                 }
2312
2313                 omap_hsmmc_protect_card(host);
2314
2315                 /* Notify the core to resume the host */
2316                 ret = mmc_resume_host(host->mmc);
2317                 if (ret == 0)
2318                         host->suspended = 0;
2319
2320                 pm_runtime_mark_last_busy(host->dev);
2321                 pm_runtime_put_autosuspend(host->dev);
2322         }
2323
2324         return ret;
2325
2326 }
2327
2328 #else
2329 #define omap_hsmmc_suspend      NULL
2330 #define omap_hsmmc_resume               NULL
2331 #endif
2332
2333 static int omap_hsmmc_runtime_suspend(struct device *dev)
2334 {
2335         struct omap_hsmmc_host *host;
2336
2337         host = platform_get_drvdata(to_platform_device(dev));
2338         omap_hsmmc_context_save(host);
2339         dev_dbg(mmc_dev(host->mmc), "disabled\n");
2340
2341         return 0;
2342 }
2343
2344 static int omap_hsmmc_runtime_resume(struct device *dev)
2345 {
2346         struct omap_hsmmc_host *host;
2347
2348         host = platform_get_drvdata(to_platform_device(dev));
2349         omap_hsmmc_context_restore(host);
2350         dev_dbg(mmc_dev(host->mmc), "enabled\n");
2351
2352         return 0;
2353 }
2354
2355 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2356         .suspend        = omap_hsmmc_suspend,
2357         .resume         = omap_hsmmc_resume,
2358         .runtime_suspend = omap_hsmmc_runtime_suspend,
2359         .runtime_resume = omap_hsmmc_runtime_resume,
2360 };
2361
2362 static struct platform_driver omap_hsmmc_driver = {
2363         .remove         = omap_hsmmc_remove,
2364         .driver         = {
2365                 .name = DRIVER_NAME,
2366                 .owner = THIS_MODULE,
2367                 .pm = &omap_hsmmc_dev_pm_ops,
2368         },
2369 };
2370
2371 static int __init omap_hsmmc_init(void)
2372 {
2373         /* Register the MMC driver */
2374         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2375 }
2376
2377 static void __exit omap_hsmmc_cleanup(void)
2378 {
2379         /* Unregister MMC driver */
2380         platform_driver_unregister(&omap_hsmmc_driver);
2381 }
2382
2383 module_init(omap_hsmmc_init);
2384 module_exit(omap_hsmmc_cleanup);
2385
2386 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2387 MODULE_LICENSE("GPL");
2388 MODULE_ALIAS("platform:" DRIVER_NAME);
2389 MODULE_AUTHOR("Texas Instruments Inc");