drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/core.h>
  31 #include <linux/io.h>
  32 #include <linux/semaphore.h>
  33 #include <linux/gpio.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <plat/dma.h>
  36 #include <mach/hardware.h>
  37 #include <plat/board.h>
  38 #include <plat/mmc.h>
  39 #include <plat/cpu.h>
  40
  41 /* OMAP HSMMC Host Controller Registers */
  42 #define OMAP_HSMMC_SYSCONFIG    0x0010
  43 #define OMAP_HSMMC_SYSSTATUS    0x0014
  44 #define OMAP_HSMMC_CON          0x002C
  45 #define OMAP_HSMMC_BLK          0x0104
  46 #define OMAP_HSMMC_ARG          0x0108
  47 #define OMAP_HSMMC_CMD          0x010C
  48 #define OMAP_HSMMC_RSP10        0x0110
  49 #define OMAP_HSMMC_RSP32        0x0114
  50 #define OMAP_HSMMC_RSP54        0x0118
  51 #define OMAP_HSMMC_RSP76        0x011C
  52 #define OMAP_HSMMC_DATA         0x0120
  53 #define OMAP_HSMMC_HCTL         0x0128
  54 #define OMAP_HSMMC_SYSCTL       0x012C
  55 #define OMAP_HSMMC_STAT         0x0130
  56 #define OMAP_HSMMC_IE           0x0134
  57 #define OMAP_HSMMC_ISE          0x0138
  58 #define OMAP_HSMMC_CAPA         0x0140
  59
  60 #define VS18                    (1 << 26)
  61 #define VS30                    (1 << 25)
  62 #define SDVS18                  (0x5 << 9)
  63 #define SDVS30                  (0x6 << 9)
  64 #define SDVS33                  (0x7 << 9)
  65 #define SDVS_MASK               0x00000E00
  66 #define SDVSCLR                 0xFFFFF1FF
  67 #define SDVSDET                 0x00000400
  68 #define AUTOIDLE                0x1
  69 #define SDBP                    (1 << 8)
  70 #define DTO                     0xe
  71 #define ICE                     0x1
  72 #define ICS                     0x2
  73 #define CEN                     (1 << 2)
  74 #define CLKD_MASK               0x0000FFC0
  75 #define CLKD_SHIFT              6
  76 #define DTO_MASK                0x000F0000
  77 #define DTO_SHIFT               16
  78 #define INT_EN_MASK             0x307F0033
  79 #define BWR_ENABLE              (1 << 4)
  80 #define BRR_ENABLE              (1 << 5)
  81 #define INIT_STREAM             (1 << 1)
  82 #define DP_SELECT               (1 << 21)
  83 #define DDIR                    (1 << 4)
  84 #define DMA_EN                  0x1
  85 #define MSBS                    (1 << 5)
  86 #define BCE                     (1 << 1)
  87 #define FOUR_BIT                (1 << 1)
  88 #define DW8                     (1 << 5)
  89 #define CC                      0x1
  90 #define TC                      0x02
  91 #define OD                      0x1
  92 #define ERR                     (1 << 15)
  93 #define CMD_TIMEOUT             (1 << 16)
  94 #define DATA_TIMEOUT            (1 << 20)
  95 #define CMD_CRC                 (1 << 17)
  96 #define DATA_CRC                (1 << 21)
  97 #define CARD_ERR                (1 << 28)
  98 #define STAT_CLEAR              0xFFFFFFFF
  99 #define INIT_STREAM_CMD         0x00000000
 100 #define DUAL_VOLT_OCR_BIT       7
 101 #define SRC                     (1 << 25)
 102 #define SRD                     (1 << 26)
 103 #define SOFTRESET               (1 << 1)
 104 #define RESETDONE               (1 << 0)
 105
 106 /*
 107  * FIXME: Most likely all the data using these _DEVID defines should come
 108  * from the platform_data, or implemented in controller and slot specific
 109  * functions.
 110  */
 111 #define OMAP_MMC1_DEVID         0
 112 #define OMAP_MMC2_DEVID         1
 113 #define OMAP_MMC3_DEVID         2
 114 #define OMAP_MMC4_DEVID         3
 115 #define OMAP_MMC5_DEVID         4
 116
 117 #define MMC_TIMEOUT_MS          20
 118 #define OMAP_MMC_MASTER_CLOCK   96000000
 119 #define DRIVER_NAME             "mmci-omap-hs"
 120
 121 /* Timeouts for entering power saving states on inactivity, msec */
 122 #define OMAP_MMC_DISABLED_TIMEOUT       100
 123 #define OMAP_MMC_SLEEP_TIMEOUT          1000
 124 #define OMAP_MMC_OFF_TIMEOUT            8000
 125
 126 /*
 127  * One controller can have multiple slots, like on some omap boards using
 128  * omap.c controller driver. Luckily this is not currently done on any known
 129  * omap_hsmmc.c device.
 130  */
 131 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 132
 133 /*
 134  * MMC Host controller read/write API's
 135  */
 136 #define OMAP_HSMMC_READ(base, reg)      \
 137         __raw_readl((base) + OMAP_HSMMC_##reg)
 138
 139 #define OMAP_HSMMC_WRITE(base, reg, val) \
 140         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 141
 142 struct omap_hsmmc_host {
 143         struct  device          *dev;
 144         struct  mmc_host        *mmc;
 145         struct  mmc_request     *mrq;
 146         struct  mmc_command     *cmd;
 147         struct  mmc_data        *data;
 148         struct  clk             *fclk;
 149         struct  clk             *iclk;
 150         struct  clk             *dbclk;
 151         /*
 152          * vcc == configured supply
 153          * vcc_aux == optional
 154          *   -  MMC1, supply for DAT4..DAT7
 155          *   -  MMC2/MMC2, external level shifter voltage supply, for
 156          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 157          */
 158         struct  regulator       *vcc;
 159         struct  regulator       *vcc_aux;
 160         struct  semaphore       sem;
 161         struct  work_struct     mmc_carddetect_work;
 162         void    __iomem         *base;
 163         resource_size_t         mapbase;
 164         spinlock_t              irq_lock; /* Prevent races with irq handler */
 165         unsigned long           flags;
 166         unsigned int            id;
 167         unsigned int            dma_len;
 168         unsigned int            dma_sg_idx;
 169         unsigned char           bus_mode;
 170         unsigned char           power_mode;
 171         u32                     *buffer;
 172         u32                     bytesleft;
 173         int                     suspended;
 174         int                     irq;
 175         int                     use_dma, dma_ch;
 176         int                     dma_line_tx, dma_line_rx;
 177         int                     slot_id;
 178         int                     got_dbclk;
 179         int                     response_busy;
 180         int                     context_loss;
 181         int                     dpm_state;
 182         int                     vdd;
 183         int                     protect_card;
 184         int                     reqs_blocked;
 185         int                     use_reg;
 186
 187         struct  omap_mmc_platform_data  *pdata;
 188 };
 189
 190 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 191 {
 192         struct omap_mmc_platform_data *mmc = dev->platform_data;
 193
 194         /* NOTE: assumes card detect signal is active-low */
 195         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 196 }
 197
 198 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 199 {
 200         struct omap_mmc_platform_data *mmc = dev->platform_data;
 201
 202         /* NOTE: assumes write protect signal is active-high */
 203         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 204 }
 205
 206 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 207 {
 208         struct omap_mmc_platform_data *mmc = dev->platform_data;
 209
 210         /* NOTE: assumes card detect signal is active-low */
 211         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 212 }
 213
 214 #ifdef CONFIG_PM
 215
 216 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 217 {
 218         struct omap_mmc_platform_data *mmc = dev->platform_data;
 219
 220         disable_irq(mmc->slots[0].card_detect_irq);
 221         return 0;
 222 }
 223
 224 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 225 {
 226         struct omap_mmc_platform_data *mmc = dev->platform_data;
 227
 228         enable_irq(mmc->slots[0].card_detect_irq);
 229         return 0;
 230 }
 231
 232 #else
 233
 234 #define omap_hsmmc_suspend_cdirq        NULL
 235 #define omap_hsmmc_resume_cdirq         NULL
 236
 237 #endif
 238
 239 #ifdef CONFIG_REGULATOR
 240
 241 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
 242                                   int vdd)
 243 {
 244         struct omap_hsmmc_host *host =
 245                 platform_get_drvdata(to_platform_device(dev));
 246         int ret;
 247
 248         if (mmc_slot(host).before_set_reg)
 249                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 250
 251         if (power_on)
 252                 ret = mmc_regulator_set_ocr(host->vcc, vdd);
 253         else
 254                 ret = mmc_regulator_set_ocr(host->vcc, 0);
 255
 256         if (mmc_slot(host).after_set_reg)
 257                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 258
 259         return ret;
 260 }
 261
 262 static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
 263                                    int vdd)
 264 {
 265         struct omap_hsmmc_host *host =
 266                 platform_get_drvdata(to_platform_device(dev));
 267         int ret = 0;
 268
 269         /*
 270          * If we don't see a Vcc regulator, assume it's a fixed
 271          * voltage always-on regulator.
 272          */
 273         if (!host->vcc)
 274                 return 0;
 275
 276         if (mmc_slot(host).before_set_reg)
 277                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 278
 279         /*
 280          * Assume Vcc regulator is used only to power the card ... OMAP
 281          * VDDS is used to power the pins, optionally with a transceiver to
 282          * support cards using voltages other than VDDS (1.8V nominal).  When a
 283          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 284          *
 285          * In some cases this regulator won't support enable/disable;
 286          * e.g. it's a fixed rail for a WLAN chip.
 287          *
 288          * In other cases vcc_aux switches interface power.  Example, for
 289          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 290          * chips/cards need an interface voltage rail too.
 291          */
 292         if (power_on) {
 293                 ret = mmc_regulator_set_ocr(host->vcc, vdd);
 294                 /* Enable interface voltage rail, if needed */
 295                 if (ret == 0 && host->vcc_aux) {
 296                         ret = regulator_enable(host->vcc_aux);
 297                         if (ret < 0)
 298                                 ret = mmc_regulator_set_ocr(host->vcc, 0);
 299                 }
 300         } else {
 301                 if (host->vcc_aux)
 302                         ret = regulator_disable(host->vcc_aux);
 303                 if (ret == 0)
 304                         ret = mmc_regulator_set_ocr(host->vcc, 0);
 305         }
 306
 307         if (mmc_slot(host).after_set_reg)
 308                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 309
 310         return ret;
 311 }
 312
 313 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
 314                                   int vdd, int cardsleep)
 315 {
 316         struct omap_hsmmc_host *host =
 317                 platform_get_drvdata(to_platform_device(dev));
 318         int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 319
 320         return regulator_set_mode(host->vcc, mode);
 321 }
 322
 323 static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
 324                                    int vdd, int cardsleep)
 325 {
 326         struct omap_hsmmc_host *host =
 327                 platform_get_drvdata(to_platform_device(dev));
 328         int err, mode;
 329
 330         /*
 331          * If we don't see a Vcc regulator, assume it's a fixed
 332          * voltage always-on regulator.
 333          */
 334         if (!host->vcc)
 335                 return 0;
 336
 337         mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 338
 339         if (!host->vcc_aux)
 340                 return regulator_set_mode(host->vcc, mode);
 341
 342         if (cardsleep) {
 343                 /* VCC can be turned off if card is asleep */
 344                 if (sleep)
 345                         err = mmc_regulator_set_ocr(host->vcc, 0);
 346                 else
 347                         err = mmc_regulator_set_ocr(host->vcc, vdd);
 348         } else
 349                 err = regulator_set_mode(host->vcc, mode);
 350         if (err)
 351                 return err;
 352
 353         if (!mmc_slot(host).vcc_aux_disable_is_sleep)
 354                 return regulator_set_mode(host->vcc_aux, mode);
 355
 356         if (sleep)
 357                 return regulator_disable(host->vcc_aux);
 358         else
 359                 return regulator_enable(host->vcc_aux);
 360 }
 361
 362 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 363 {
 364         struct regulator *reg;
 365         int ret = 0;
 366
 367         switch (host->id) {
 368         case OMAP_MMC1_DEVID:
 369                 /* On-chip level shifting via PBIAS0/PBIAS1 */
 370                 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
 371                 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
 372                 break;
 373         case OMAP_MMC2_DEVID:
 374         case OMAP_MMC3_DEVID:
 375                 /* Off-chip level shifting, or none */
 376                 mmc_slot(host).set_power = omap_hsmmc_23_set_power;
 377                 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
 378                 break;
 379         default:
 380                 pr_err("MMC%d configuration not supported!\n", host->id);
 381                 return -EINVAL;
 382         }
 383
 384         reg = regulator_get(host->dev, "vmmc");
 385         if (IS_ERR(reg)) {
 386                 dev_dbg(host->dev, "vmmc regulator missing\n");
 387                 /*
 388                 * HACK: until fixed.c regulator is usable,
 389                 * we don't require a main regulator
 390                 * for MMC2 or MMC3
 391                 */
 392                 if (host->id == OMAP_MMC1_DEVID) {
 393                         ret = PTR_ERR(reg);
 394                         goto err;
 395                 }
 396         } else {
 397                 host->vcc = reg;
 398                 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
 399
 400                 /* Allow an aux regulator */
 401                 reg = regulator_get(host->dev, "vmmc_aux");
 402                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 403
 404                 /*
 405                 * UGLY HACK:  workaround regulator framework bugs.
 406                 * When the bootloader leaves a supply active, it's
 407                 * initialized with zero usecount ... and we can't
 408                 * disable it without first enabling it.  Until the
 409                 * framework is fixed, we need a workaround like this
 410                 * (which is safe for MMC, but not in general).
 411                 */
 412                 if (regulator_is_enabled(host->vcc) > 0) {
 413                         regulator_enable(host->vcc);
 414                         regulator_disable(host->vcc);
 415                 }
 416                 if (host->vcc_aux) {
 417                         if (regulator_is_enabled(reg) > 0) {
 418                                 regulator_enable(reg);
 419                                 regulator_disable(reg);
 420                         }
 421                 }
 422         }
 423
 424         return 0;
 425
 426 err:
 427         mmc_slot(host).set_power = NULL;
 428         mmc_slot(host).set_sleep = NULL;
 429         return ret;
 430 }
 431
 432 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 433 {
 434         regulator_put(host->vcc);
 435         regulator_put(host->vcc_aux);
 436         mmc_slot(host).set_power = NULL;
 437         mmc_slot(host).set_sleep = NULL;
 438 }
 439
 440 static inline int omap_hsmmc_have_reg(void)
 441 {
 442         return 1;
 443 }
 444
 445 #else
 446
 447 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 448 {
 449         return -EINVAL;
 450 }
 451
 452 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 453 {
 454 }
 455
 456 static inline int omap_hsmmc_have_reg(void)
 457 {
 458         return 0;
 459 }
 460
 461 #endif
 462
 463 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 464 {
 465         int ret;
 466
 467         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 468                 pdata->suspend = omap_hsmmc_suspend_cdirq;
 469                 pdata->resume = omap_hsmmc_resume_cdirq;
 470                 if (pdata->slots[0].cover)
 471                         pdata->slots[0].get_cover_state =
 472                                         omap_hsmmc_get_cover_state;
 473                 else
 474                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 475                 pdata->slots[0].card_detect_irq =
 476                                 gpio_to_irq(pdata->slots[0].switch_pin);
 477                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 478                 if (ret)
 479                         return ret;
 480                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 481                 if (ret)
 482                         goto err_free_sp;
 483         } else
 484                 pdata->slots[0].switch_pin = -EINVAL;
 485
 486         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 487                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 488                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 489                 if (ret)
 490                         goto err_free_cd;
 491                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 492                 if (ret)
 493                         goto err_free_wp;
 494         } else
 495                 pdata->slots[0].gpio_wp = -EINVAL;
 496
 497         return 0;
 498
 499 err_free_wp:
 500         gpio_free(pdata->slots[0].gpio_wp);
 501 err_free_cd:
 502         if (gpio_is_valid(pdata->slots[0].switch_pin))
 503 err_free_sp:
 504                 gpio_free(pdata->slots[0].switch_pin);
 505         return ret;
 506 }
 507
 508 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 509 {
 510         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 511                 gpio_free(pdata->slots[0].gpio_wp);
 512         if (gpio_is_valid(pdata->slots[0].switch_pin))
 513                 gpio_free(pdata->slots[0].switch_pin);
 514 }
 515
 516 /*
 517  * Stop clock to the card
 518  */
 519 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 520 {
 521         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 522                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 523         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 524                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 525 }
 526
 527 #ifdef CONFIG_PM
 528
 529 /*
 530  * Restore the MMC host context, if it was lost as result of a
 531  * power state change.
 532  */
 533 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 534 {
 535         struct mmc_ios *ios = &host->mmc->ios;
 536         struct omap_mmc_platform_data *pdata = host->pdata;
 537         int context_loss = 0;
 538         u32 hctl, capa, con;
 539         u16 dsor = 0;
 540         unsigned long timeout;
 541
 542         if (pdata->get_context_loss_count) {
 543                 context_loss = pdata->get_context_loss_count(host->dev);
 544                 if (context_loss < 0)
 545                         return 1;
 546         }
 547
 548         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 549                 context_loss == host->context_loss ? "not " : "");
 550         if (host->context_loss == context_loss)
 551                 return 1;
 552
 553         /* Wait for hardware reset */
 554         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 555         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 556                 && time_before(jiffies, timeout))
 557                 ;
 558
 559         /* Do software reset */
 560         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 561         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 562         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 563                 && time_before(jiffies, timeout))
 564                 ;
 565
 566         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 567                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 568
 569         if (host->id == OMAP_MMC1_DEVID) {
 570                 if (host->power_mode != MMC_POWER_OFF &&
 571                     (1 << ios->vdd) <= MMC_VDD_23_24)
 572                         hctl = SDVS18;
 573                 else
 574                         hctl = SDVS30;
 575                 capa = VS30 | VS18;
 576         } else {
 577                 hctl = SDVS18;
 578                 capa = VS18;
 579         }
 580
 581         OMAP_HSMMC_WRITE(host->base, HCTL,
 582                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 583
 584         OMAP_HSMMC_WRITE(host->base, CAPA,
 585                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 586
 587         OMAP_HSMMC_WRITE(host->base, HCTL,
 588                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 589
 590         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 591         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 592                 && time_before(jiffies, timeout))
 593                 ;
 594
 595         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 596         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 597         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 598
 599         /* Do not initialize card-specific things if the power is off */
 600         if (host->power_mode == MMC_POWER_OFF)
 601                 goto out;
 602
 603         con = OMAP_HSMMC_READ(host->base, CON);
 604         switch (ios->bus_width) {
 605         case MMC_BUS_WIDTH_8:
 606                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 607                 break;
 608         case MMC_BUS_WIDTH_4:
 609                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 610                 OMAP_HSMMC_WRITE(host->base, HCTL,
 611                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 612                 break;
 613         case MMC_BUS_WIDTH_1:
 614                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 615                 OMAP_HSMMC_WRITE(host->base, HCTL,
 616                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 617                 break;
 618         }
 619
 620         if (ios->clock) {
 621                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 622                 if (dsor < 1)
 623                         dsor = 1;
 624
 625                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 626                         dsor++;
 627
 628                 if (dsor > 250)
 629                         dsor = 250;
 630         }
 631
 632         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 633                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 634         OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
 635         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 636                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 637
 638         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 639         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 640                 && time_before(jiffies, timeout))
 641                 ;
 642
 643         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 644                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 645
 646         con = OMAP_HSMMC_READ(host->base, CON);
 647         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 648                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 649         else
 650                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 651 out:
 652         host->context_loss = context_loss;
 653
 654         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 655         return 0;
 656 }
 657
 658 /*
 659  * Save the MMC host context (store the number of power state changes so far).
 660  */
 661 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 662 {
 663         struct omap_mmc_platform_data *pdata = host->pdata;
 664         int context_loss;
 665
 666         if (pdata->get_context_loss_count) {
 667                 context_loss = pdata->get_context_loss_count(host->dev);
 668                 if (context_loss < 0)
 669                         return;
 670                 host->context_loss = context_loss;
 671         }
 672 }
 673
 674 #else
 675
 676 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 677 {
 678         return 0;
 679 }
 680
 681 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 682 {
 683 }
 684
 685 #endif
 686
 687 /*
 688  * Send init stream sequence to card
 689  * before sending IDLE command
 690  */
 691 static void send_init_stream(struct omap_hsmmc_host *host)
 692 {
 693         int reg = 0;
 694         unsigned long timeout;
 695
 696         if (host->protect_card)
 697                 return;
 698
 699         disable_irq(host->irq);
 700         OMAP_HSMMC_WRITE(host->base, CON,
 701                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 702         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 703
 704         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 705         while ((reg != CC) && time_before(jiffies, timeout))
 706                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 707
 708         OMAP_HSMMC_WRITE(host->base, CON,
 709                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 710
 711         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 712         OMAP_HSMMC_READ(host->base, STAT);
 713
 714         enable_irq(host->irq);
 715 }
 716
 717 static inline
 718 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 719 {
 720         int r = 1;
 721
 722         if (mmc_slot(host).get_cover_state)
 723                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 724         return r;
 725 }
 726
 727 static ssize_t
 728 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 729                            char *buf)
 730 {
 731         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 732         struct omap_hsmmc_host *host = mmc_priv(mmc);
 733
 734         return sprintf(buf, "%s\n",
 735                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 736 }
 737
 738 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 739
 740 static ssize_t
 741 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 742                         char *buf)
 743 {
 744         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 745         struct omap_hsmmc_host *host = mmc_priv(mmc);
 746
 747         return sprintf(buf, "%s\n", mmc_slot(host).name);
 748 }
 749
 750 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 751
 752 /*
 753  * Configure the response type and send the cmd.
 754  */
 755 static void
 756 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 757         struct mmc_data *data)
 758 {
 759         int cmdreg = 0, resptype = 0, cmdtype = 0;
 760
 761         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 762                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 763         host->cmd = cmd;
 764
 765         /*
 766          * Clear status bits and enable interrupts
 767          */
 768         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 769         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 770
 771         if (host->use_dma)
 772                 OMAP_HSMMC_WRITE(host->base, IE,
 773                                  INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
 774         else
 775                 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 776
 777         host->response_busy = 0;
 778         if (cmd->flags & MMC_RSP_PRESENT) {
 779                 if (cmd->flags & MMC_RSP_136)
 780                         resptype = 1;
 781                 else if (cmd->flags & MMC_RSP_BUSY) {
 782                         resptype = 3;
 783                         host->response_busy = 1;
 784                 } else
 785                         resptype = 2;
 786         }
 787
 788         /*
 789          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 790          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 791          * a val of 0x3, rest 0x0.
 792          */
 793         if (cmd == host->mrq->stop)
 794                 cmdtype = 0x3;
 795
 796         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 797
 798         if (data) {
 799                 cmdreg |= DP_SELECT | MSBS | BCE;
 800                 if (data->flags & MMC_DATA_READ)
 801                         cmdreg |= DDIR;
 802                 else
 803                         cmdreg &= ~(DDIR);
 804         }
 805
 806         if (host->use_dma)
 807                 cmdreg |= DMA_EN;
 808
 809         /*
 810          * In an interrupt context (i.e. STOP command), the spinlock is unlocked
 811          * by the interrupt handler, otherwise (i.e. for a new request) it is
 812          * unlocked here.
 813          */
 814         if (!in_interrupt())
 815                 spin_unlock_irqrestore(&host->irq_lock, host->flags);
 816
 817         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 818         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 819 }
 820
 821 static int
 822 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 823 {
 824         if (data->flags & MMC_DATA_WRITE)
 825                 return DMA_TO_DEVICE;
 826         else
 827                 return DMA_FROM_DEVICE;
 828 }
 829
 830 /*
 831  * Notify the transfer complete to MMC core
 832  */
 833 static void
 834 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 835 {
 836         if (!data) {
 837                 struct mmc_request *mrq = host->mrq;
 838
 839                 /* TC before CC from CMD6 - don't know why, but it happens */
 840                 if (host->cmd && host->cmd->opcode == 6 &&
 841                     host->response_busy) {
 842                         host->response_busy = 0;
 843                         return;
 844                 }
 845
 846                 host->mrq = NULL;
 847                 mmc_request_done(host->mmc, mrq);
 848                 return;
 849         }
 850
 851         host->data = NULL;
 852
 853         if (host->use_dma && host->dma_ch != -1)
 854                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 855                         omap_hsmmc_get_dma_dir(host, data));
 856
 857         if (!data->error)
 858                 data->bytes_xfered += data->blocks * (data->blksz);
 859         else
 860                 data->bytes_xfered = 0;
 861
 862         if (!data->stop) {
 863                 host->mrq = NULL;
 864                 mmc_request_done(host->mmc, data->mrq);
 865                 return;
 866         }
 867         omap_hsmmc_start_command(host, data->stop, NULL);
 868 }
 869
 870 /*
 871  * Notify the core about command completion
 872  */
 873 static void
 874 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 875 {
 876         host->cmd = NULL;
 877
 878         if (cmd->flags & MMC_RSP_PRESENT) {
 879                 if (cmd->flags & MMC_RSP_136) {
 880                         /* response type 2 */
 881                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 882                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 883                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 884                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 885                 } else {
 886                         /* response types 1, 1b, 3, 4, 5, 6 */
 887                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 888                 }
 889         }
 890         if ((host->data == NULL && !host->response_busy) || cmd->error) {
 891                 host->mrq = NULL;
 892                 mmc_request_done(host->mmc, cmd->mrq);
 893         }
 894 }
 895
 896 /*
 897  * DMA clean up for command errors
 898  */
 899 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 900 {
 901         host->data->error = errno;
 902
 903         if (host->use_dma && host->dma_ch != -1) {
 904                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 905                         omap_hsmmc_get_dma_dir(host, host->data));
 906                 omap_free_dma(host->dma_ch);
 907                 host->dma_ch = -1;
 908                 up(&host->sem);
 909         }
 910         host->data = NULL;
 911 }
 912
 913 /*
 914  * Readable error output
 915  */
 916 #ifdef CONFIG_MMC_DEBUG
 917 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
 918 {
 919         /* --- means reserved bit without definition at documentation */
 920         static const char *omap_hsmmc_status_bits[] = {
 921                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 922                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 923                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 924                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 925         };
 926         char res[256];
 927         char *buf = res;
 928         int len, i;
 929
 930         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 931         buf += len;
 932
 933         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 934                 if (status & (1 << i)) {
 935                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 936                         buf += len;
 937                 }
 938
 939         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 940 }
 941 #endif  /* CONFIG_MMC_DEBUG */
 942
 943 /*
 944  * MMC controller internal state machines reset
 945  *
 946  * Used to reset command or data internal state machines, using respectively
 947  *  SRC or SRD bit of SYSCTL register
 948  * Can be called from interrupt context
 949  */
 950 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 951                                                    unsigned long bit)
 952 {
 953         unsigned long i = 0;
 954         unsigned long limit = (loops_per_jiffy *
 955                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 956
 957         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 958                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 959
 960         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 961                 (i++ < limit))
 962                 cpu_relax();
 963
 964         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 965                 dev_err(mmc_dev(host->mmc),
 966                         "Timeout waiting on controller reset in %s\n",
 967                         __func__);
 968 }
 969
 970 /*
 971  * MMC controller IRQ handler
 972  */
 973 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
 974 {
 975         struct omap_hsmmc_host *host = dev_id;
 976         struct mmc_data *data;
 977         int end_cmd = 0, end_trans = 0, status;
 978
 979         spin_lock(&host->irq_lock);
 980
 981         if (host->mrq == NULL) {
 982                 OMAP_HSMMC_WRITE(host->base, STAT,
 983                         OMAP_HSMMC_READ(host->base, STAT));
 984                 /* Flush posted write */
 985                 OMAP_HSMMC_READ(host->base, STAT);
 986                 spin_unlock(&host->irq_lock);
 987                 return IRQ_HANDLED;
 988         }
 989
 990         data = host->data;
 991         status = OMAP_HSMMC_READ(host->base, STAT);
 992         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 993
 994         if (status & ERR) {
 995 #ifdef CONFIG_MMC_DEBUG
 996                 omap_hsmmc_report_irq(host, status);
 997 #endif
 998                 if ((status & CMD_TIMEOUT) ||
 999                         (status & CMD_CRC)) {
1000                         if (host->cmd) {
1001                                 if (status & CMD_TIMEOUT) {
1002                                         omap_hsmmc_reset_controller_fsm(host,
1003                                                                         SRC);
1004                                         host->cmd->error = -ETIMEDOUT;
1005                                 } else {
1006                                         host->cmd->error = -EILSEQ;
1007                                 }
1008                                 end_cmd = 1;
1009                         }
1010                         if (host->data || host->response_busy) {
1011                                 if (host->data)
1012                                         omap_hsmmc_dma_cleanup(host,
1013                                                                 -ETIMEDOUT);
1014                                 host->response_busy = 0;
1015                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1016                         }
1017                 }
1018                 if ((status & DATA_TIMEOUT) ||
1019                         (status & DATA_CRC)) {
1020                         if (host->data || host->response_busy) {
1021                                 int err = (status & DATA_TIMEOUT) ?
1022                                                 -ETIMEDOUT : -EILSEQ;
1023
1024                                 if (host->data)
1025                                         omap_hsmmc_dma_cleanup(host, err);
1026                                 else
1027                                         host->mrq->cmd->error = err;
1028                                 host->response_busy = 0;
1029                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1030                                 end_trans = 1;
1031                         }
1032                 }
1033                 if (status & CARD_ERR) {
1034                         dev_dbg(mmc_dev(host->mmc),
1035                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1036                         if (host->cmd)
1037                                 end_cmd = 1;
1038                         if (host->data)
1039                                 end_trans = 1;
1040                 }
1041         }
1042
1043         OMAP_HSMMC_WRITE(host->base, STAT, status);
1044         /* Flush posted write */
1045         OMAP_HSMMC_READ(host->base, STAT);
1046
1047         if (end_cmd || ((status & CC) && host->cmd))
1048                 omap_hsmmc_cmd_done(host, host->cmd);
1049         if ((end_trans || (status & TC)) && host->mrq)
1050                 omap_hsmmc_xfer_done(host, data);
1051
1052         spin_unlock(&host->irq_lock);
1053
1054         return IRQ_HANDLED;
1055 }
1056
1057 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1058 {
1059         unsigned long i;
1060
1061         OMAP_HSMMC_WRITE(host->base, HCTL,
1062                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1063         for (i = 0; i < loops_per_jiffy; i++) {
1064                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1065                         break;
1066                 cpu_relax();
1067         }
1068 }
1069
1070 /*
1071  * Switch MMC interface voltage ... only relevant for MMC1.
1072  *
1073  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1074  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1075  * Some chips, like eMMC ones, use internal transceivers.
1076  */
1077 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1078 {
1079         u32 reg_val = 0;
1080         int ret;
1081
1082         /* Disable the clocks */
1083         clk_disable(host->fclk);
1084         clk_disable(host->iclk);
1085         if (host->got_dbclk)
1086                 clk_disable(host->dbclk);
1087
1088         /* Turn the power off */
1089         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1090
1091         /* Turn the power ON with given VDD 1.8 or 3.0v */
1092         if (!ret)
1093                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1094                                                vdd);
1095         clk_enable(host->iclk);
1096         clk_enable(host->fclk);
1097         if (host->got_dbclk)
1098                 clk_enable(host->dbclk);
1099
1100         if (ret != 0)
1101                 goto err;
1102
1103         OMAP_HSMMC_WRITE(host->base, HCTL,
1104                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1105         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1106
1107         /*
1108          * If a MMC dual voltage card is detected, the set_ios fn calls
1109          * this fn with VDD bit set for 1.8V. Upon card removal from the
1110          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1111          *
1112          * Cope with a bit of slop in the range ... per data sheets:
1113          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1114          *    but recommended values are 1.71V to 1.89V
1115          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1116          *    but recommended values are 2.7V to 3.3V
1117          *
1118          * Board setup code shouldn't permit anything very out-of-range.
1119          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1120          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1121          */
1122         if ((1 << vdd) <= MMC_VDD_23_24)
1123                 reg_val |= SDVS18;
1124         else
1125                 reg_val |= SDVS30;
1126
1127         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1128         set_sd_bus_power(host);
1129
1130         return 0;
1131 err:
1132         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1133         return ret;
1134 }
1135
1136 /* Protect the card while the cover is open */
1137 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1138 {
1139         if (!mmc_slot(host).get_cover_state)
1140                 return;
1141
1142         host->reqs_blocked = 0;
1143         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1144                 if (host->protect_card) {
1145                         printk(KERN_INFO "%s: cover is closed, "
1146                                          "card is now accessible\n",
1147                                          mmc_hostname(host->mmc));
1148                         host->protect_card = 0;
1149                 }
1150         } else {
1151                 if (!host->protect_card) {
1152                         printk(KERN_INFO "%s: cover is open, "
1153                                          "card is now inaccessible\n",
1154                                          mmc_hostname(host->mmc));
1155                         host->protect_card = 1;
1156                 }
1157         }
1158 }
1159
1160 /*
1161  * Work Item to notify the core about card insertion/removal
1162  */
1163 static void omap_hsmmc_detect(struct work_struct *work)
1164 {
1165         struct omap_hsmmc_host *host =
1166                 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1167         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1168         int carddetect;
1169
1170         if (host->suspended)
1171                 return;
1172
1173         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1174
1175         if (slot->card_detect)
1176                 carddetect = slot->card_detect(host->dev, host->slot_id);
1177         else {
1178                 omap_hsmmc_protect_card(host);
1179                 carddetect = -ENOSYS;
1180         }
1181
1182         if (carddetect)
1183                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1184         else
1185                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1186 }
1187
1188 /*
1189  * ISR for handling card insertion and removal
1190  */
1191 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1192 {
1193         struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1194
1195         if (host->suspended)
1196                 return IRQ_HANDLED;
1197         schedule_work(&host->mmc_carddetect_work);
1198
1199         return IRQ_HANDLED;
1200 }
1201
1202 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1203                                      struct mmc_data *data)
1204 {
1205         int sync_dev;
1206
1207         if (data->flags & MMC_DATA_WRITE)
1208                 sync_dev = host->dma_line_tx;
1209         else
1210                 sync_dev = host->dma_line_rx;
1211         return sync_dev;
1212 }
1213
1214 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1215                                        struct mmc_data *data,
1216                                        struct scatterlist *sgl)
1217 {
1218         int blksz, nblk, dma_ch;
1219
1220         dma_ch = host->dma_ch;
1221         if (data->flags & MMC_DATA_WRITE) {
1222                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1223                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1224                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1225                         sg_dma_address(sgl), 0, 0);
1226         } else {
1227                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1228                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1229                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1230                         sg_dma_address(sgl), 0, 0);
1231         }
1232
1233         blksz = host->data->blksz;
1234         nblk = sg_dma_len(sgl) / blksz;
1235
1236         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1237                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1238                         omap_hsmmc_get_dma_sync_dev(host, data),
1239                         !(data->flags & MMC_DATA_WRITE));
1240
1241         omap_start_dma(dma_ch);
1242 }
1243
1244 /*
1245  * DMA call back function
1246  */
1247 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data)
1248 {
1249         struct omap_hsmmc_host *host = data;
1250
1251         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
1252                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
1253
1254         if (host->dma_ch < 0)
1255                 return;
1256
1257         host->dma_sg_idx++;
1258         if (host->dma_sg_idx < host->dma_len) {
1259                 /* Fire up the next transfer. */
1260                 omap_hsmmc_config_dma_params(host, host->data,
1261                                            host->data->sg + host->dma_sg_idx);
1262                 return;
1263         }
1264
1265         omap_free_dma(host->dma_ch);
1266         host->dma_ch = -1;
1267         /*
1268          * DMA Callback: run in interrupt context.
1269          * mutex_unlock will throw a kernel warning if used.
1270          */
1271         up(&host->sem);
1272 }
1273
1274 /*
1275  * Routine to configure and start DMA for the MMC card
1276  */
1277 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1278                                         struct mmc_request *req)
1279 {
1280         int dma_ch = 0, ret = 0, err = 1, i;
1281         struct mmc_data *data = req->data;
1282
1283         /* Sanity check: all the SG entries must be aligned by block size. */
1284         for (i = 0; i < data->sg_len; i++) {
1285                 struct scatterlist *sgl;
1286
1287                 sgl = data->sg + i;
1288                 if (sgl->length % data->blksz)
1289                         return -EINVAL;
1290         }
1291         if ((data->blksz % 4) != 0)
1292                 /* REVISIT: The MMC buffer increments only when MSB is written.
1293                  * Return error for blksz which is non multiple of four.
1294                  */
1295                 return -EINVAL;
1296
1297         /*
1298          * If for some reason the DMA transfer is still active,
1299          * we wait for timeout period and free the dma
1300          */
1301         if (host->dma_ch != -1) {
1302                 set_current_state(TASK_UNINTERRUPTIBLE);
1303                 schedule_timeout(100);
1304                 if (down_trylock(&host->sem)) {
1305                         omap_free_dma(host->dma_ch);
1306                         host->dma_ch = -1;
1307                         up(&host->sem);
1308                         return err;
1309                 }
1310         } else {
1311                 if (down_trylock(&host->sem))
1312                         return err;
1313         }
1314
1315         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1316                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1317         if (ret != 0) {
1318                 dev_err(mmc_dev(host->mmc),
1319                         "%s: omap_request_dma() failed with %d\n",
1320                         mmc_hostname(host->mmc), ret);
1321                 return ret;
1322         }
1323
1324         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1325                         data->sg_len, omap_hsmmc_get_dma_dir(host, data));
1326         host->dma_ch = dma_ch;
1327         host->dma_sg_idx = 0;
1328
1329         omap_hsmmc_config_dma_params(host, data, data->sg);
1330
1331         return 0;
1332 }
1333
1334 static void set_data_timeout(struct omap_hsmmc_host *host,
1335                              unsigned int timeout_ns,
1336                              unsigned int timeout_clks)
1337 {
1338         unsigned int timeout, cycle_ns;
1339         uint32_t reg, clkd, dto = 0;
1340
1341         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1342         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1343         if (clkd == 0)
1344                 clkd = 1;
1345
1346         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1347         timeout = timeout_ns / cycle_ns;
1348         timeout += timeout_clks;
1349         if (timeout) {
1350                 while ((timeout & 0x80000000) == 0) {
1351                         dto += 1;
1352                         timeout <<= 1;
1353                 }
1354                 dto = 31 - dto;
1355                 timeout <<= 1;
1356                 if (timeout && dto)
1357                         dto += 1;
1358                 if (dto >= 13)
1359                         dto -= 13;
1360                 else
1361                         dto = 0;
1362                 if (dto > 14)
1363                         dto = 14;
1364         }
1365
1366         reg &= ~DTO_MASK;
1367         reg |= dto << DTO_SHIFT;
1368         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1369 }
1370
1371 /*
1372  * Configure block length for MMC/SD cards and initiate the transfer.
1373  */
1374 static int
1375 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1376 {
1377         int ret;
1378         host->data = req->data;
1379
1380         if (req->data == NULL) {
1381                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1382                 /*
1383                  * Set an arbitrary 100ms data timeout for commands with
1384                  * busy signal.
1385                  */
1386                 if (req->cmd->flags & MMC_RSP_BUSY)
1387                         set_data_timeout(host, 100000000U, 0);
1388                 return 0;
1389         }
1390
1391         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1392                                         | (req->data->blocks << 16));
1393         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1394
1395         if (host->use_dma) {
1396                 ret = omap_hsmmc_start_dma_transfer(host, req);
1397                 if (ret != 0) {
1398                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1399                         return ret;
1400                 }
1401         }
1402         return 0;
1403 }
1404
1405 /*
1406  * Request function. for read/write operation
1407  */
1408 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1409 {
1410         struct omap_hsmmc_host *host = mmc_priv(mmc);
1411         int err;
1412
1413         /*
1414          * Prevent races with the interrupt handler because of unexpected
1415          * interrupts, but not if we are already in interrupt context i.e.
1416          * retries.
1417          */
1418         if (!in_interrupt()) {
1419                 spin_lock_irqsave(&host->irq_lock, host->flags);
1420                 /*
1421                  * Protect the card from I/O if there is a possibility
1422                  * it can be removed.
1423                  */
1424                 if (host->protect_card) {
1425                         if (host->reqs_blocked < 3) {
1426                                 /*
1427                                  * Ensure the controller is left in a consistent
1428                                  * state by resetting the command and data state
1429                                  * machines.
1430                                  */
1431                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1432                                 omap_hsmmc_reset_controller_fsm(host, SRC);
1433                                 host->reqs_blocked += 1;
1434                         }
1435                         req->cmd->error = -EBADF;
1436                         if (req->data)
1437                                 req->data->error = -EBADF;
1438                         spin_unlock_irqrestore(&host->irq_lock, host->flags);
1439                         mmc_request_done(mmc, req);
1440                         return;
1441                 } else if (host->reqs_blocked)
1442                         host->reqs_blocked = 0;
1443         }
1444         WARN_ON(host->mrq != NULL);
1445         host->mrq = req;
1446         err = omap_hsmmc_prepare_data(host, req);
1447         if (err) {
1448                 req->cmd->error = err;
1449                 if (req->data)
1450                         req->data->error = err;
1451                 host->mrq = NULL;
1452                 if (!in_interrupt())
1453                         spin_unlock_irqrestore(&host->irq_lock, host->flags);
1454                 mmc_request_done(mmc, req);
1455                 return;
1456         }
1457
1458         omap_hsmmc_start_command(host, req->cmd, req->data);
1459 }
1460
1461 /* Routine to configure clock values. Exposed API to core */
1462 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1463 {
1464         struct omap_hsmmc_host *host = mmc_priv(mmc);
1465         u16 dsor = 0;
1466         unsigned long regval;
1467         unsigned long timeout;
1468         u32 con;
1469         int do_send_init_stream = 0;
1470
1471         mmc_host_enable(host->mmc);
1472
1473         if (ios->power_mode != host->power_mode) {
1474                 switch (ios->power_mode) {
1475                 case MMC_POWER_OFF:
1476                         mmc_slot(host).set_power(host->dev, host->slot_id,
1477                                                  0, 0);
1478                         host->vdd = 0;
1479                         break;
1480                 case MMC_POWER_UP:
1481                         mmc_slot(host).set_power(host->dev, host->slot_id,
1482                                                  1, ios->vdd);
1483                         host->vdd = ios->vdd;
1484                         break;
1485                 case MMC_POWER_ON:
1486                         do_send_init_stream = 1;
1487                         break;
1488                 }
1489                 host->power_mode = ios->power_mode;
1490         }
1491
1492         /* FIXME: set registers based only on changes to ios */
1493
1494         con = OMAP_HSMMC_READ(host->base, CON);
1495         switch (mmc->ios.bus_width) {
1496         case MMC_BUS_WIDTH_8:
1497                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1498                 break;
1499         case MMC_BUS_WIDTH_4:
1500                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1501                 OMAP_HSMMC_WRITE(host->base, HCTL,
1502                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1503                 break;
1504         case MMC_BUS_WIDTH_1:
1505                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1506                 OMAP_HSMMC_WRITE(host->base, HCTL,
1507                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1508                 break;
1509         }
1510
1511         if (host->id == OMAP_MMC1_DEVID) {
1512                 /* Only MMC1 can interface at 3V without some flavor
1513                  * of external transceiver; but they all handle 1.8V.
1514                  */
1515                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1516                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1517                                 /*
1518                                  * The mmc_select_voltage fn of the core does
1519                                  * not seem to set the power_mode to
1520                                  * MMC_POWER_UP upon recalculating the voltage.
1521                                  * vdd 1.8v.
1522                                  */
1523                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1524                                 dev_dbg(mmc_dev(host->mmc),
1525                                                 "Switch operation failed\n");
1526                 }
1527         }
1528
1529         if (ios->clock) {
1530                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1531                 if (dsor < 1)
1532                         dsor = 1;
1533
1534                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1535                         dsor++;
1536
1537                 if (dsor > 250)
1538                         dsor = 250;
1539         }
1540         omap_hsmmc_stop_clock(host);
1541         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1542         regval = regval & ~(CLKD_MASK);
1543         regval = regval | (dsor << 6) | (DTO << 16);
1544         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1545         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1546                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1547
1548         /* Wait till the ICS bit is set */
1549         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1550         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1551                 && time_before(jiffies, timeout))
1552                 msleep(1);
1553
1554         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1555                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1556
1557         if (do_send_init_stream)
1558                 send_init_stream(host);
1559
1560         con = OMAP_HSMMC_READ(host->base, CON);
1561         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1562                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1563         else
1564                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1565
1566         if (host->power_mode == MMC_POWER_OFF)
1567                 mmc_host_disable(host->mmc);
1568         else
1569                 mmc_host_lazy_disable(host->mmc);
1570 }
1571
1572 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1573 {
1574         struct omap_hsmmc_host *host = mmc_priv(mmc);
1575
1576         if (!mmc_slot(host).card_detect)
1577                 return -ENOSYS;
1578         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1579 }
1580
1581 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1582 {
1583         struct omap_hsmmc_host *host = mmc_priv(mmc);
1584
1585         if (!mmc_slot(host).get_ro)
1586                 return -ENOSYS;
1587         return mmc_slot(host).get_ro(host->dev, 0);
1588 }
1589
1590 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1591 {
1592         u32 hctl, capa, value;
1593
1594         /* Only MMC1 supports 3.0V */
1595         if (host->id == OMAP_MMC1_DEVID) {
1596                 hctl = SDVS30;
1597                 capa = VS30 | VS18;
1598         } else {
1599                 hctl = SDVS18;
1600                 capa = VS18;
1601         }
1602
1603         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1604         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1605
1606         value = OMAP_HSMMC_READ(host->base, CAPA);
1607         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1608
1609         /* Set the controller to AUTO IDLE mode */
1610         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1611         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1612
1613         /* Set SD bus power bit */
1614         set_sd_bus_power(host);
1615 }
1616
1617 /*
1618  * Dynamic power saving handling, FSM:
1619  *   ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1620  *     ^___________|          |                      |
1621  *     |______________________|______________________|
1622  *
1623  * ENABLED:   mmc host is fully functional
1624  * DISABLED:  fclk is off
1625  * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1626  * REGSLEEP:  fclk is off, voltage regulator is asleep
1627  * OFF:       fclk is off, voltage regulator is off
1628  *
1629  * Transition handlers return the timeout for the next state transition
1630  * or negative error.
1631  */
1632
1633 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1634
1635 /* Handler for [ENABLED -> DISABLED] transition */
1636 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1637 {
1638         omap_hsmmc_context_save(host);
1639         clk_disable(host->fclk);
1640         host->dpm_state = DISABLED;
1641
1642         dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1643
1644         if (host->power_mode == MMC_POWER_OFF)
1645                 return 0;
1646
1647         return OMAP_MMC_SLEEP_TIMEOUT;
1648 }
1649
1650 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1651 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1652 {
1653         int err, new_state;
1654
1655         if (!mmc_try_claim_host(host->mmc))
1656                 return 0;
1657
1658         clk_enable(host->fclk);
1659         omap_hsmmc_context_restore(host);
1660         if (mmc_card_can_sleep(host->mmc)) {
1661                 err = mmc_card_sleep(host->mmc);
1662                 if (err < 0) {
1663                         clk_disable(host->fclk);
1664                         mmc_release_host(host->mmc);
1665                         return err;
1666                 }
1667                 new_state = CARDSLEEP;
1668         } else {
1669                 new_state = REGSLEEP;
1670         }
1671         if (mmc_slot(host).set_sleep)
1672                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1673                                          new_state == CARDSLEEP);
1674         /* FIXME: turn off bus power and perhaps interrupts too */
1675         clk_disable(host->fclk);
1676         host->dpm_state = new_state;
1677
1678         mmc_release_host(host->mmc);
1679
1680         dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1681                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1682
1683         if (mmc_slot(host).no_off)
1684                 return 0;
1685
1686         if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1687             mmc_slot(host).card_detect ||
1688             (mmc_slot(host).get_cover_state &&
1689              mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1690                 return OMAP_MMC_OFF_TIMEOUT;
1691
1692         return 0;
1693 }
1694
1695 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1696 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1697 {
1698         if (!mmc_try_claim_host(host->mmc))
1699                 return 0;
1700
1701         if (mmc_slot(host).no_off)
1702                 return 0;
1703
1704         if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1705               mmc_slot(host).card_detect ||
1706               (mmc_slot(host).get_cover_state &&
1707                mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1708                 mmc_release_host(host->mmc);
1709                 return 0;
1710         }
1711
1712         mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1713         host->vdd = 0;
1714         host->power_mode = MMC_POWER_OFF;
1715
1716         dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1717                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1718
1719         host->dpm_state = OFF;
1720
1721         mmc_release_host(host->mmc);
1722
1723         return 0;
1724 }
1725
1726 /* Handler for [DISABLED -> ENABLED] transition */
1727 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1728 {
1729         int err;
1730
1731         err = clk_enable(host->fclk);
1732         if (err < 0)
1733                 return err;
1734
1735         omap_hsmmc_context_restore(host);
1736         host->dpm_state = ENABLED;
1737
1738         dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1739
1740         return 0;
1741 }
1742
1743 /* Handler for [SLEEP -> ENABLED] transition */
1744 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1745 {
1746         if (!mmc_try_claim_host(host->mmc))
1747                 return 0;
1748
1749         clk_enable(host->fclk);
1750         omap_hsmmc_context_restore(host);
1751         if (mmc_slot(host).set_sleep)
1752                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1753                          host->vdd, host->dpm_state == CARDSLEEP);
1754         if (mmc_card_can_sleep(host->mmc))
1755                 mmc_card_awake(host->mmc);
1756
1757         dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1758                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1759
1760         host->dpm_state = ENABLED;
1761
1762         mmc_release_host(host->mmc);
1763
1764         return 0;
1765 }
1766
1767 /* Handler for [OFF -> ENABLED] transition */
1768 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1769 {
1770         clk_enable(host->fclk);
1771
1772         omap_hsmmc_context_restore(host);
1773         omap_hsmmc_conf_bus_power(host);
1774         mmc_power_restore_host(host->mmc);
1775
1776         host->dpm_state = ENABLED;
1777
1778         dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1779
1780         return 0;
1781 }
1782
1783 /*
1784  * Bring MMC host to ENABLED from any other PM state.
1785  */
1786 static int omap_hsmmc_enable(struct mmc_host *mmc)
1787 {
1788         struct omap_hsmmc_host *host = mmc_priv(mmc);
1789
1790         switch (host->dpm_state) {
1791         case DISABLED:
1792                 return omap_hsmmc_disabled_to_enabled(host);
1793         case CARDSLEEP:
1794         case REGSLEEP:
1795                 return omap_hsmmc_sleep_to_enabled(host);
1796         case OFF:
1797                 return omap_hsmmc_off_to_enabled(host);
1798         default:
1799                 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1800                 return -EINVAL;
1801         }
1802 }
1803
1804 /*
1805  * Bring MMC host in PM state (one level deeper).
1806  */
1807 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1808 {
1809         struct omap_hsmmc_host *host = mmc_priv(mmc);
1810
1811         switch (host->dpm_state) {
1812         case ENABLED: {
1813                 int delay;
1814
1815                 delay = omap_hsmmc_enabled_to_disabled(host);
1816                 if (lazy || delay < 0)
1817                         return delay;
1818                 return 0;
1819         }
1820         case DISABLED:
1821                 return omap_hsmmc_disabled_to_sleep(host);
1822         case CARDSLEEP:
1823         case REGSLEEP:
1824                 return omap_hsmmc_sleep_to_off(host);
1825         default:
1826                 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1827                 return -EINVAL;
1828         }
1829 }
1830
1831 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1832 {
1833         struct omap_hsmmc_host *host = mmc_priv(mmc);
1834         int err;
1835
1836         err = clk_enable(host->fclk);
1837         if (err)
1838                 return err;
1839         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1840         omap_hsmmc_context_restore(host);
1841         return 0;
1842 }
1843
1844 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1845 {
1846         struct omap_hsmmc_host *host = mmc_priv(mmc);
1847
1848         omap_hsmmc_context_save(host);
1849         clk_disable(host->fclk);
1850         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1851         return 0;
1852 }
1853
1854 static const struct mmc_host_ops omap_hsmmc_ops = {
1855         .enable = omap_hsmmc_enable_fclk,
1856         .disable = omap_hsmmc_disable_fclk,
1857         .request = omap_hsmmc_request,
1858         .set_ios = omap_hsmmc_set_ios,
1859         .get_cd = omap_hsmmc_get_cd,
1860         .get_ro = omap_hsmmc_get_ro,
1861         /* NYET -- enable_sdio_irq */
1862 };
1863
1864 static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1865         .enable = omap_hsmmc_enable,
1866         .disable = omap_hsmmc_disable,
1867         .request = omap_hsmmc_request,
1868         .set_ios = omap_hsmmc_set_ios,
1869         .get_cd = omap_hsmmc_get_cd,
1870         .get_ro = omap_hsmmc_get_ro,
1871         /* NYET -- enable_sdio_irq */
1872 };
1873
1874 #ifdef CONFIG_DEBUG_FS
1875
1876 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1877 {
1878         struct mmc_host *mmc = s->private;
1879         struct omap_hsmmc_host *host = mmc_priv(mmc);
1880         int context_loss = 0;
1881
1882         if (host->pdata->get_context_loss_count)
1883                 context_loss = host->pdata->get_context_loss_count(host->dev);
1884
1885         seq_printf(s, "mmc%d:\n"
1886                         " enabled:\t%d\n"
1887                         " dpm_state:\t%d\n"
1888                         " nesting_cnt:\t%d\n"
1889                         " ctx_loss:\t%d:%d\n"
1890                         "\nregs:\n",
1891                         mmc->index, mmc->enabled ? 1 : 0,
1892                         host->dpm_state, mmc->nesting_cnt,
1893                         host->context_loss, context_loss);
1894
1895         if (host->suspended || host->dpm_state == OFF) {
1896                 seq_printf(s, "host suspended, can't read registers\n");
1897                 return 0;
1898         }
1899
1900         if (clk_enable(host->fclk) != 0) {
1901                 seq_printf(s, "can't read the regs\n");
1902                 return 0;
1903         }
1904
1905         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1906                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1907         seq_printf(s, "CON:\t\t0x%08x\n",
1908                         OMAP_HSMMC_READ(host->base, CON));
1909         seq_printf(s, "HCTL:\t\t0x%08x\n",
1910                         OMAP_HSMMC_READ(host->base, HCTL));
1911         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1912                         OMAP_HSMMC_READ(host->base, SYSCTL));
1913         seq_printf(s, "IE:\t\t0x%08x\n",
1914                         OMAP_HSMMC_READ(host->base, IE));
1915         seq_printf(s, "ISE:\t\t0x%08x\n",
1916                         OMAP_HSMMC_READ(host->base, ISE));
1917         seq_printf(s, "CAPA:\t\t0x%08x\n",
1918                         OMAP_HSMMC_READ(host->base, CAPA));
1919
1920         clk_disable(host->fclk);
1921
1922         return 0;
1923 }
1924
1925 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1926 {
1927         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1928 }
1929
1930 static const struct file_operations mmc_regs_fops = {
1931         .open           = omap_hsmmc_regs_open,
1932         .read           = seq_read,
1933         .llseek         = seq_lseek,
1934         .release        = single_release,
1935 };
1936
1937 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1938 {
1939         if (mmc->debugfs_root)
1940                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1941                         mmc, &mmc_regs_fops);
1942 }
1943
1944 #else
1945
1946 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1947 {
1948 }
1949
1950 #endif
1951
1952 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1953 {
1954         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1955         struct mmc_host *mmc;
1956         struct omap_hsmmc_host *host = NULL;
1957         struct resource *res;
1958         int ret, irq;
1959
1960         if (pdata == NULL) {
1961                 dev_err(&pdev->dev, "Platform Data is missing\n");
1962                 return -ENXIO;
1963         }
1964
1965         if (pdata->nr_slots == 0) {
1966                 dev_err(&pdev->dev, "No Slots\n");
1967                 return -ENXIO;
1968         }
1969
1970         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1971         irq = platform_get_irq(pdev, 0);
1972         if (res == NULL || irq < 0)
1973                 return -ENXIO;
1974
1975         res = request_mem_region(res->start, res->end - res->start + 1,
1976                                                         pdev->name);
1977         if (res == NULL)
1978                 return -EBUSY;
1979
1980         ret = omap_hsmmc_gpio_init(pdata);
1981         if (ret)
1982                 goto err;
1983
1984         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1985         if (!mmc) {
1986                 ret = -ENOMEM;
1987                 goto err_alloc;
1988         }
1989
1990         host            = mmc_priv(mmc);
1991         host->mmc       = mmc;
1992         host->pdata     = pdata;
1993         host->dev       = &pdev->dev;
1994         host->use_dma   = 1;
1995         host->dev->dma_mask = &pdata->dma_mask;
1996         host->dma_ch    = -1;
1997         host->irq       = irq;
1998         host->id        = pdev->id;
1999         host->slot_id   = 0;
2000         host->mapbase   = res->start;
2001         host->base      = ioremap(host->mapbase, SZ_4K);
2002         host->power_mode = MMC_POWER_OFF;
2003
2004         platform_set_drvdata(pdev, host);
2005         INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
2006
2007         if (mmc_slot(host).power_saving)
2008                 mmc->ops        = &omap_hsmmc_ps_ops;
2009         else
2010                 mmc->ops        = &omap_hsmmc_ops;
2011
2012         /*
2013          * If regulator_disable can only put vcc_aux to sleep then there is
2014          * no off state.
2015          */
2016         if (mmc_slot(host).vcc_aux_disable_is_sleep)
2017                 mmc_slot(host).no_off = 1;
2018
2019         mmc->f_min      = 400000;
2020         mmc->f_max      = 52000000;
2021
2022         sema_init(&host->sem, 1);
2023         spin_lock_init(&host->irq_lock);
2024
2025         host->iclk = clk_get(&pdev->dev, "ick");
2026         if (IS_ERR(host->iclk)) {
2027                 ret = PTR_ERR(host->iclk);
2028                 host->iclk = NULL;
2029                 goto err1;
2030         }
2031         host->fclk = clk_get(&pdev->dev, "fck");
2032         if (IS_ERR(host->fclk)) {
2033                 ret = PTR_ERR(host->fclk);
2034                 host->fclk = NULL;
2035                 clk_put(host->iclk);
2036                 goto err1;
2037         }
2038
2039         omap_hsmmc_context_save(host);
2040
2041         mmc->caps |= MMC_CAP_DISABLE;
2042         mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2043         /* we start off in DISABLED state */
2044         host->dpm_state = DISABLED;
2045
2046         if (mmc_host_enable(host->mmc) != 0) {
2047                 clk_put(host->iclk);
2048                 clk_put(host->fclk);
2049                 goto err1;
2050         }
2051
2052         if (clk_enable(host->iclk) != 0) {
2053                 mmc_host_disable(host->mmc);
2054                 clk_put(host->iclk);
2055                 clk_put(host->fclk);
2056                 goto err1;
2057         }
2058
2059         if (cpu_is_omap2430()) {
2060                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2061                 /*
2062                  * MMC can still work without debounce clock.
2063                  */
2064                 if (IS_ERR(host->dbclk))
2065                         dev_warn(mmc_dev(host->mmc),
2066                                 "Failed to get debounce clock\n");
2067                 else
2068                         host->got_dbclk = 1;
2069
2070                 if (host->got_dbclk)
2071                         if (clk_enable(host->dbclk) != 0)
2072                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2073                                                         " clk failed\n");
2074         }
2075
2076         /* Since we do only SG emulation, we can have as many segs
2077          * as we want. */
2078         mmc->max_phys_segs = 1024;
2079         mmc->max_hw_segs = 1024;
2080
2081         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2082         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2083         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2084         mmc->max_seg_size = mmc->max_req_size;
2085
2086         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2087                      MMC_CAP_WAIT_WHILE_BUSY;
2088
2089         if (mmc_slot(host).wires >= 8)
2090                 mmc->caps |= MMC_CAP_8_BIT_DATA;
2091         else if (mmc_slot(host).wires >= 4)
2092                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2093
2094         if (mmc_slot(host).nonremovable)
2095                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2096
2097         omap_hsmmc_conf_bus_power(host);
2098
2099         /* Select DMA lines */
2100         switch (host->id) {
2101         case OMAP_MMC1_DEVID:
2102                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2103                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2104                 break;
2105         case OMAP_MMC2_DEVID:
2106                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2107                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2108                 break;
2109         case OMAP_MMC3_DEVID:
2110                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2111                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2112                 break;
2113         case OMAP_MMC4_DEVID:
2114                 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2115                 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2116                 break;
2117         case OMAP_MMC5_DEVID:
2118                 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2119                 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2120                 break;
2121         default:
2122                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2123                 goto err_irq;
2124         }
2125
2126         /* Request IRQ for MMC operations */
2127         ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2128                         mmc_hostname(mmc), host);
2129         if (ret) {
2130                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2131                 goto err_irq;
2132         }
2133
2134         if (pdata->init != NULL) {
2135                 if (pdata->init(&pdev->dev) != 0) {
2136                         dev_dbg(mmc_dev(host->mmc),
2137                                 "Unable to configure MMC IRQs\n");
2138                         goto err_irq_cd_init;
2139                 }
2140         }
2141
2142         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2143                 ret = omap_hsmmc_reg_get(host);
2144                 if (ret)
2145                         goto err_reg;
2146                 host->use_reg = 1;
2147         }
2148
2149         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2150
2151         /* Request IRQ for card detect */
2152         if ((mmc_slot(host).card_detect_irq)) {
2153                 ret = request_irq(mmc_slot(host).card_detect_irq,
2154                                   omap_hsmmc_cd_handler,
2155                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2156                                           | IRQF_DISABLED,
2157                                   mmc_hostname(mmc), host);
2158                 if (ret) {
2159                         dev_dbg(mmc_dev(host->mmc),
2160                                 "Unable to grab MMC CD IRQ\n");
2161                         goto err_irq_cd;
2162                 }
2163         }
2164
2165         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
2166         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
2167
2168         mmc_host_lazy_disable(host->mmc);
2169
2170         omap_hsmmc_protect_card(host);
2171
2172         mmc_add_host(mmc);
2173
2174         if (mmc_slot(host).name != NULL) {
2175                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2176                 if (ret < 0)
2177                         goto err_slot_name;
2178         }
2179         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2180                 ret = device_create_file(&mmc->class_dev,
2181                                         &dev_attr_cover_switch);
2182                 if (ret < 0)
2183                         goto err_slot_name;
2184         }
2185
2186         omap_hsmmc_debugfs(mmc);
2187
2188         return 0;
2189
2190 err_slot_name:
2191         mmc_remove_host(mmc);
2192         free_irq(mmc_slot(host).card_detect_irq, host);
2193 err_irq_cd:
2194         if (host->use_reg)
2195                 omap_hsmmc_reg_put(host);
2196 err_reg:
2197         if (host->pdata->cleanup)
2198                 host->pdata->cleanup(&pdev->dev);
2199 err_irq_cd_init:
2200         free_irq(host->irq, host);
2201 err_irq:
2202         mmc_host_disable(host->mmc);
2203         clk_disable(host->iclk);
2204         clk_put(host->fclk);
2205         clk_put(host->iclk);
2206         if (host->got_dbclk) {
2207                 clk_disable(host->dbclk);
2208                 clk_put(host->dbclk);
2209         }
2210 err1:
2211         iounmap(host->base);
2212         platform_set_drvdata(pdev, NULL);
2213         mmc_free_host(mmc);
2214 err_alloc:
2215         omap_hsmmc_gpio_free(pdata);
2216 err:
2217         release_mem_region(res->start, res->end - res->start + 1);
2218         return ret;
2219 }
2220
2221 static int omap_hsmmc_remove(struct platform_device *pdev)
2222 {
2223         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2224         struct resource *res;
2225
2226         if (host) {
2227                 mmc_host_enable(host->mmc);
2228                 mmc_remove_host(host->mmc);
2229                 if (host->use_reg)
2230                         omap_hsmmc_reg_put(host);
2231                 if (host->pdata->cleanup)
2232                         host->pdata->cleanup(&pdev->dev);
2233                 free_irq(host->irq, host);
2234                 if (mmc_slot(host).card_detect_irq)
2235                         free_irq(mmc_slot(host).card_detect_irq, host);
2236                 flush_scheduled_work();
2237
2238                 mmc_host_disable(host->mmc);
2239                 clk_disable(host->iclk);
2240                 clk_put(host->fclk);
2241                 clk_put(host->iclk);
2242                 if (host->got_dbclk) {
2243                         clk_disable(host->dbclk);
2244                         clk_put(host->dbclk);
2245                 }
2246
2247                 mmc_free_host(host->mmc);
2248                 iounmap(host->base);
2249                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2250         }
2251
2252         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2253         if (res)
2254                 release_mem_region(res->start, res->end - res->start + 1);
2255         platform_set_drvdata(pdev, NULL);
2256
2257         return 0;
2258 }
2259
2260 #ifdef CONFIG_PM
2261 static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state)
2262 {
2263         int ret = 0;
2264         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2265
2266         if (host && host->suspended)
2267                 return 0;
2268
2269         if (host) {
2270                 host->suspended = 1;
2271                 if (host->pdata->suspend) {
2272                         ret = host->pdata->suspend(&pdev->dev,
2273                                                         host->slot_id);
2274                         if (ret) {
2275                                 dev_dbg(mmc_dev(host->mmc),
2276                                         "Unable to handle MMC board"
2277                                         " level suspend\n");
2278                                 host->suspended = 0;
2279                                 return ret;
2280                         }
2281                 }
2282                 cancel_work_sync(&host->mmc_carddetect_work);
2283                 mmc_host_enable(host->mmc);
2284                 ret = mmc_suspend_host(host->mmc, state);
2285                 if (ret == 0) {
2286                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
2287                         OMAP_HSMMC_WRITE(host->base, IE, 0);
2288
2289
2290                         OMAP_HSMMC_WRITE(host->base, HCTL,
2291                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2292                         mmc_host_disable(host->mmc);
2293                         clk_disable(host->iclk);
2294                         if (host->got_dbclk)
2295                                 clk_disable(host->dbclk);
2296                 } else {
2297                         host->suspended = 0;
2298                         if (host->pdata->resume) {
2299                                 ret = host->pdata->resume(&pdev->dev,
2300                                                           host->slot_id);
2301                                 if (ret)
2302                                         dev_dbg(mmc_dev(host->mmc),
2303                                                 "Unmask interrupt failed\n");
2304                         }
2305                         mmc_host_disable(host->mmc);
2306                 }
2307
2308         }
2309         return ret;
2310 }
2311
2312 /* Routine to resume the MMC device */
2313 static int omap_hsmmc_resume(struct platform_device *pdev)
2314 {
2315         int ret = 0;
2316         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2317
2318         if (host && !host->suspended)
2319                 return 0;
2320
2321         if (host) {
2322                 ret = clk_enable(host->iclk);
2323                 if (ret)
2324                         goto clk_en_err;
2325
2326                 if (mmc_host_enable(host->mmc) != 0) {
2327                         clk_disable(host->iclk);
2328                         goto clk_en_err;
2329                 }
2330
2331                 if (host->got_dbclk)
2332                         clk_enable(host->dbclk);
2333
2334                 omap_hsmmc_conf_bus_power(host);
2335
2336                 if (host->pdata->resume) {
2337                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2338                         if (ret)
2339                                 dev_dbg(mmc_dev(host->mmc),
2340                                         "Unmask interrupt failed\n");
2341                 }
2342
2343                 omap_hsmmc_protect_card(host);
2344
2345                 /* Notify the core to resume the host */
2346                 ret = mmc_resume_host(host->mmc);
2347                 if (ret == 0)
2348                         host->suspended = 0;
2349
2350                 mmc_host_lazy_disable(host->mmc);
2351         }
2352
2353         return ret;
2354
2355 clk_en_err:
2356         dev_dbg(mmc_dev(host->mmc),
2357                 "Failed to enable MMC clocks during resume\n");
2358         return ret;
2359 }
2360
2361 #else
2362 #define omap_hsmmc_suspend      NULL
2363 #define omap_hsmmc_resume               NULL
2364 #endif
2365
2366 static struct platform_driver omap_hsmmc_driver = {
2367         .remove         = omap_hsmmc_remove,
2368         .suspend        = omap_hsmmc_suspend,
2369         .resume         = omap_hsmmc_resume,
2370         .driver         = {
2371                 .name = DRIVER_NAME,
2372                 .owner = THIS_MODULE,
2373         },
2374 };
2375
2376 static int __init omap_hsmmc_init(void)
2377 {
2378         /* Register the MMC driver */
2379         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2380 }
2381
2382 static void __exit omap_hsmmc_cleanup(void)
2383 {
2384         /* Unregister MMC driver */
2385         platform_driver_unregister(&omap_hsmmc_driver);
2386 }
2387
2388 module_init(omap_hsmmc_init);
2389 module_exit(omap_hsmmc_cleanup);
2390
2391 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2392 MODULE_LICENSE("GPL");
2393 MODULE_ALIAS("platform:" DRIVER_NAME);
2394 MODULE_AUTHOR("Texas Instruments Inc");