2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/mmc/mmc.h>
33 #include <linux/semaphore.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
38 #include <mach/hardware.h>
39 #include <plat/board.h>
43 /* OMAP HSMMC Host Controller Registers */
44 #define OMAP_HSMMC_SYSCONFIG 0x0010
45 #define OMAP_HSMMC_SYSSTATUS 0x0014
46 #define OMAP_HSMMC_CON 0x002C
47 #define OMAP_HSMMC_BLK 0x0104
48 #define OMAP_HSMMC_ARG 0x0108
49 #define OMAP_HSMMC_CMD 0x010C
50 #define OMAP_HSMMC_RSP10 0x0110
51 #define OMAP_HSMMC_RSP32 0x0114
52 #define OMAP_HSMMC_RSP54 0x0118
53 #define OMAP_HSMMC_RSP76 0x011C
54 #define OMAP_HSMMC_DATA 0x0120
55 #define OMAP_HSMMC_HCTL 0x0128
56 #define OMAP_HSMMC_SYSCTL 0x012C
57 #define OMAP_HSMMC_STAT 0x0130
58 #define OMAP_HSMMC_IE 0x0134
59 #define OMAP_HSMMC_ISE 0x0138
60 #define OMAP_HSMMC_CAPA 0x0140
62 #define VS18 (1 << 26)
63 #define VS30 (1 << 25)
64 #define SDVS18 (0x5 << 9)
65 #define SDVS30 (0x6 << 9)
66 #define SDVS33 (0x7 << 9)
67 #define SDVS_MASK 0x00000E00
68 #define SDVSCLR 0xFFFFF1FF
69 #define SDVSDET 0x00000400
76 #define CLKD_MASK 0x0000FFC0
78 #define DTO_MASK 0x000F0000
80 #define INT_EN_MASK 0x307F0033
81 #define BWR_ENABLE (1 << 4)
82 #define BRR_ENABLE (1 << 5)
83 #define DTO_ENABLE (1 << 20)
84 #define INIT_STREAM (1 << 1)
85 #define DP_SELECT (1 << 21)
90 #define FOUR_BIT (1 << 1)
96 #define CMD_TIMEOUT (1 << 16)
97 #define DATA_TIMEOUT (1 << 20)
98 #define CMD_CRC (1 << 17)
99 #define DATA_CRC (1 << 21)
100 #define CARD_ERR (1 << 28)
101 #define STAT_CLEAR 0xFFFFFFFF
102 #define INIT_STREAM_CMD 0x00000000
103 #define DUAL_VOLT_OCR_BIT 7
104 #define SRC (1 << 25)
105 #define SRD (1 << 26)
106 #define SOFTRESET (1 << 1)
107 #define RESETDONE (1 << 0)
110 * FIXME: Most likely all the data using these _DEVID defines should come
111 * from the platform_data, or implemented in controller and slot specific
114 #define OMAP_MMC1_DEVID 0
115 #define OMAP_MMC2_DEVID 1
116 #define OMAP_MMC3_DEVID 2
117 #define OMAP_MMC4_DEVID 3
118 #define OMAP_MMC5_DEVID 4
120 #define MMC_AUTOSUSPEND_DELAY 100
121 #define MMC_TIMEOUT_MS 20
122 #define OMAP_MMC_MASTER_CLOCK 96000000
123 #define OMAP_MMC_MIN_CLOCK 400000
124 #define OMAP_MMC_MAX_CLOCK 52000000
125 #define DRIVER_NAME "omap_hsmmc"
128 * One controller can have multiple slots, like on some omap boards using
129 * omap.c controller driver. Luckily this is not currently done on any known
130 * omap_hsmmc.c device.
132 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
135 * MMC Host controller read/write API's
137 #define OMAP_HSMMC_READ(base, reg) \
138 __raw_readl((base) + OMAP_HSMMC_##reg)
140 #define OMAP_HSMMC_WRITE(base, reg, val) \
141 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143 struct omap_hsmmc_next {
144 unsigned int dma_len;
148 struct omap_hsmmc_host {
150 struct mmc_host *mmc;
151 struct mmc_request *mrq;
152 struct mmc_command *cmd;
153 struct mmc_data *data;
157 * vcc == configured supply
158 * vcc_aux == optional
159 * - MMC1, supply for DAT4..DAT7
160 * - MMC2/MMC2, external level shifter voltage supply, for
161 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
163 struct regulator *vcc;
164 struct regulator *vcc_aux;
166 resource_size_t mapbase;
167 spinlock_t irq_lock; /* Prevent races with irq handler */
169 unsigned int dma_len;
170 unsigned int dma_sg_idx;
171 unsigned char bus_mode;
172 unsigned char power_mode;
178 int dma_ch_tx, dma_ch_rx;
179 int dma_line_tx, dma_line_rx;
190 struct omap_hsmmc_next next_data;
192 struct omap_mmc_platform_data *pdata;
195 static int omap_hsmmc_card_detect(struct device *dev, int slot)
197 struct omap_mmc_platform_data *mmc = dev->platform_data;
199 /* NOTE: assumes card detect signal is active-low */
200 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
203 static int omap_hsmmc_get_wp(struct device *dev, int slot)
205 struct omap_mmc_platform_data *mmc = dev->platform_data;
207 /* NOTE: assumes write protect signal is active-high */
208 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
211 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
213 struct omap_mmc_platform_data *mmc = dev->platform_data;
215 /* NOTE: assumes card detect signal is active-low */
216 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
221 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
223 struct omap_mmc_platform_data *mmc = dev->platform_data;
225 disable_irq(mmc->slots[0].card_detect_irq);
229 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
231 struct omap_mmc_platform_data *mmc = dev->platform_data;
233 enable_irq(mmc->slots[0].card_detect_irq);
239 #define omap_hsmmc_suspend_cdirq NULL
240 #define omap_hsmmc_resume_cdirq NULL
244 #ifdef CONFIG_REGULATOR
246 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
249 struct omap_hsmmc_host *host =
250 platform_get_drvdata(to_platform_device(dev));
253 if (mmc_slot(host).before_set_reg)
254 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
257 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
259 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
261 if (mmc_slot(host).after_set_reg)
262 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
267 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
270 struct omap_hsmmc_host *host =
271 platform_get_drvdata(to_platform_device(dev));
275 * If we don't see a Vcc regulator, assume it's a fixed
276 * voltage always-on regulator.
281 if (mmc_slot(host).before_set_reg)
282 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
285 * Assume Vcc regulator is used only to power the card ... OMAP
286 * VDDS is used to power the pins, optionally with a transceiver to
287 * support cards using voltages other than VDDS (1.8V nominal). When a
288 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
290 * In some cases this regulator won't support enable/disable;
291 * e.g. it's a fixed rail for a WLAN chip.
293 * In other cases vcc_aux switches interface power. Example, for
294 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
295 * chips/cards need an interface voltage rail too.
298 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
299 /* Enable interface voltage rail, if needed */
300 if (ret == 0 && host->vcc_aux) {
301 ret = regulator_enable(host->vcc_aux);
303 ret = mmc_regulator_set_ocr(host->mmc,
307 /* Shut down the rail */
309 ret = regulator_disable(host->vcc_aux);
311 /* Then proceed to shut down the local regulator */
312 ret = mmc_regulator_set_ocr(host->mmc,
317 if (mmc_slot(host).after_set_reg)
318 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
323 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
329 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
330 int vdd, int cardsleep)
332 struct omap_hsmmc_host *host =
333 platform_get_drvdata(to_platform_device(dev));
334 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
336 return regulator_set_mode(host->vcc, mode);
339 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
340 int vdd, int cardsleep)
342 struct omap_hsmmc_host *host =
343 platform_get_drvdata(to_platform_device(dev));
347 * If we don't see a Vcc regulator, assume it's a fixed
348 * voltage always-on regulator.
353 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
356 return regulator_set_mode(host->vcc, mode);
359 /* VCC can be turned off if card is asleep */
361 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
363 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
365 err = regulator_set_mode(host->vcc, mode);
369 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
370 return regulator_set_mode(host->vcc_aux, mode);
373 return regulator_disable(host->vcc_aux);
375 return regulator_enable(host->vcc_aux);
378 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
379 int vdd, int cardsleep)
384 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
386 struct regulator *reg;
391 case OMAP_MMC1_DEVID:
392 /* On-chip level shifting via PBIAS0/PBIAS1 */
393 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
394 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
396 case OMAP_MMC2_DEVID:
397 case OMAP_MMC3_DEVID:
398 case OMAP_MMC5_DEVID:
399 /* Off-chip level shifting, or none */
400 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
401 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
403 case OMAP_MMC4_DEVID:
404 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
405 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
407 pr_err("MMC%d configuration not supported!\n", host->id);
411 reg = regulator_get(host->dev, "vmmc");
413 dev_dbg(host->dev, "vmmc regulator missing\n");
415 * HACK: until fixed.c regulator is usable,
416 * we don't require a main regulator
419 if (host->id == OMAP_MMC1_DEVID) {
425 ocr_value = mmc_regulator_get_ocrmask(reg);
426 if (!mmc_slot(host).ocr_mask) {
427 mmc_slot(host).ocr_mask = ocr_value;
429 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
430 pr_err("MMC%d ocrmask %x is not supported\n",
431 host->id, mmc_slot(host).ocr_mask);
432 mmc_slot(host).ocr_mask = 0;
437 /* Allow an aux regulator */
438 reg = regulator_get(host->dev, "vmmc_aux");
439 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
441 /* For eMMC do not power off when not in sleep state */
442 if (mmc_slot(host).no_regulator_off_init)
445 * UGLY HACK: workaround regulator framework bugs.
446 * When the bootloader leaves a supply active, it's
447 * initialized with zero usecount ... and we can't
448 * disable it without first enabling it. Until the
449 * framework is fixed, we need a workaround like this
450 * (which is safe for MMC, but not in general).
452 if (regulator_is_enabled(host->vcc) > 0 ||
453 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
454 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
456 mmc_slot(host).set_power(host->dev, host->slot_id,
458 mmc_slot(host).set_power(host->dev, host->slot_id,
466 mmc_slot(host).set_power = NULL;
467 mmc_slot(host).set_sleep = NULL;
471 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
473 regulator_put(host->vcc);
474 regulator_put(host->vcc_aux);
475 mmc_slot(host).set_power = NULL;
476 mmc_slot(host).set_sleep = NULL;
479 static inline int omap_hsmmc_have_reg(void)
486 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
491 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
495 static inline int omap_hsmmc_have_reg(void)
502 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
506 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
507 if (pdata->slots[0].cover)
508 pdata->slots[0].get_cover_state =
509 omap_hsmmc_get_cover_state;
511 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
512 pdata->slots[0].card_detect_irq =
513 gpio_to_irq(pdata->slots[0].switch_pin);
514 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
517 ret = gpio_direction_input(pdata->slots[0].switch_pin);
521 pdata->slots[0].switch_pin = -EINVAL;
523 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
524 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
525 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
528 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
532 pdata->slots[0].gpio_wp = -EINVAL;
537 gpio_free(pdata->slots[0].gpio_wp);
539 if (gpio_is_valid(pdata->slots[0].switch_pin))
541 gpio_free(pdata->slots[0].switch_pin);
545 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
547 if (gpio_is_valid(pdata->slots[0].gpio_wp))
548 gpio_free(pdata->slots[0].gpio_wp);
549 if (gpio_is_valid(pdata->slots[0].switch_pin))
550 gpio_free(pdata->slots[0].switch_pin);
554 * Start clock to the card
556 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
558 OMAP_HSMMC_WRITE(host->base, SYSCTL,
559 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
563 * Stop clock to the card
565 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
567 OMAP_HSMMC_WRITE(host->base, SYSCTL,
568 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
569 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
570 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
573 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
574 struct mmc_command *cmd)
576 unsigned int irq_mask;
579 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
581 irq_mask = INT_EN_MASK;
583 /* Disable timeout for erases */
584 if (cmd->opcode == MMC_ERASE)
585 irq_mask &= ~DTO_ENABLE;
587 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
588 OMAP_HSMMC_WRITE(host->base, ISE, host->use_dma ? irq_mask : 0);
589 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
592 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
594 OMAP_HSMMC_WRITE(host->base, ISE, 0);
595 OMAP_HSMMC_WRITE(host->base, IE, 0);
596 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
599 /* Calculate divisor for the given clock frequency */
600 static u16 calc_divisor(struct mmc_ios *ios)
605 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
613 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
615 struct mmc_ios *ios = &host->mmc->ios;
616 unsigned long regval;
617 unsigned long timeout;
619 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
621 omap_hsmmc_stop_clock(host);
623 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
624 regval = regval & ~(CLKD_MASK | DTO_MASK);
625 regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
626 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
627 OMAP_HSMMC_WRITE(host->base, SYSCTL,
628 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
630 /* Wait till the ICS bit is set */
631 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
632 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
633 && time_before(jiffies, timeout))
636 omap_hsmmc_start_clock(host);
639 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
641 struct mmc_ios *ios = &host->mmc->ios;
644 con = OMAP_HSMMC_READ(host->base, CON);
645 switch (ios->bus_width) {
646 case MMC_BUS_WIDTH_8:
647 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
649 case MMC_BUS_WIDTH_4:
650 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
651 OMAP_HSMMC_WRITE(host->base, HCTL,
652 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
654 case MMC_BUS_WIDTH_1:
655 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
656 OMAP_HSMMC_WRITE(host->base, HCTL,
657 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
662 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
664 struct mmc_ios *ios = &host->mmc->ios;
667 con = OMAP_HSMMC_READ(host->base, CON);
668 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
669 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
671 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
677 * Restore the MMC host context, if it was lost as result of a
678 * power state change.
680 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
682 struct mmc_ios *ios = &host->mmc->ios;
683 struct omap_mmc_platform_data *pdata = host->pdata;
684 int context_loss = 0;
686 unsigned long timeout;
688 if (pdata->get_context_loss_count) {
689 context_loss = pdata->get_context_loss_count(host->dev);
690 if (context_loss < 0)
694 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
695 context_loss == host->context_loss ? "not " : "");
696 if (host->context_loss == context_loss)
699 /* Wait for hardware reset */
700 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
701 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
702 && time_before(jiffies, timeout))
705 /* Do software reset */
706 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
707 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
708 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
709 && time_before(jiffies, timeout))
712 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
713 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
715 if (host->id == OMAP_MMC1_DEVID) {
716 if (host->power_mode != MMC_POWER_OFF &&
717 (1 << ios->vdd) <= MMC_VDD_23_24)
727 OMAP_HSMMC_WRITE(host->base, HCTL,
728 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
730 OMAP_HSMMC_WRITE(host->base, CAPA,
731 OMAP_HSMMC_READ(host->base, CAPA) | capa);
733 OMAP_HSMMC_WRITE(host->base, HCTL,
734 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
736 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
737 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
738 && time_before(jiffies, timeout))
741 omap_hsmmc_disable_irq(host);
743 /* Do not initialize card-specific things if the power is off */
744 if (host->power_mode == MMC_POWER_OFF)
747 omap_hsmmc_set_bus_width(host);
749 omap_hsmmc_set_clock(host);
751 omap_hsmmc_set_bus_mode(host);
754 host->context_loss = context_loss;
756 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
761 * Save the MMC host context (store the number of power state changes so far).
763 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
765 struct omap_mmc_platform_data *pdata = host->pdata;
768 if (pdata->get_context_loss_count) {
769 context_loss = pdata->get_context_loss_count(host->dev);
770 if (context_loss < 0)
772 host->context_loss = context_loss;
778 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
783 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
790 * Send init stream sequence to card
791 * before sending IDLE command
793 static void send_init_stream(struct omap_hsmmc_host *host)
796 unsigned long timeout;
798 if (host->protect_card)
801 disable_irq(host->irq);
803 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
804 OMAP_HSMMC_WRITE(host->base, CON,
805 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
806 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
808 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
809 while ((reg != CC) && time_before(jiffies, timeout))
810 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
812 OMAP_HSMMC_WRITE(host->base, CON,
813 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
815 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
816 OMAP_HSMMC_READ(host->base, STAT);
818 enable_irq(host->irq);
822 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
826 if (mmc_slot(host).get_cover_state)
827 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
832 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
835 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
836 struct omap_hsmmc_host *host = mmc_priv(mmc);
838 return sprintf(buf, "%s\n",
839 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
842 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
845 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
848 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
849 struct omap_hsmmc_host *host = mmc_priv(mmc);
851 return sprintf(buf, "%s\n", mmc_slot(host).name);
854 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
856 /* for hosts with 35xx erratum 2.1.1.128 */
858 omap_hsmmc_show_unsafe_read(struct device *dev, struct device_attribute *attr,
861 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
864 if (!(mmc->caps2 & MMC_CAP2_NO_MULTI_READ)) {
866 if (mmc->f_max == OMAP_MMC_MAX_CLOCK)
870 return sprintf(buf, "%d\n", val);
874 omap_hsmmc_set_unsafe_read(struct device *dev, struct device_attribute *attr,
875 const char *buf, size_t count)
877 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
881 ret = strict_strtoul(buf, 0, &val);
887 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
888 mmc->f_max = OMAP_MMC_MAX_CLOCK;
891 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
892 mmc->f_max = 32000000;
895 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
896 mmc->f_max = OMAP_MMC_MAX_CLOCK;
902 static DEVICE_ATTR(unsafe_read, S_IWUSR | S_IRUGO,
903 omap_hsmmc_show_unsafe_read, omap_hsmmc_set_unsafe_read);
906 * Configure the response type and send the cmd.
909 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
910 struct mmc_data *data)
912 int cmdreg = 0, resptype = 0, cmdtype = 0;
914 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
915 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
918 omap_hsmmc_enable_irq(host, cmd);
920 host->response_busy = 0;
921 if (cmd->flags & MMC_RSP_PRESENT) {
922 if (cmd->flags & MMC_RSP_136)
924 else if (cmd->flags & MMC_RSP_BUSY) {
926 host->response_busy = 1;
932 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
933 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
934 * a val of 0x3, rest 0x0.
936 if (cmd == host->mrq->stop)
939 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
942 cmdreg |= DP_SELECT | MSBS | BCE;
943 if (data->flags & MMC_DATA_READ)
952 host->req_in_progress = 1;
954 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
955 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
959 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
961 if (data->flags & MMC_DATA_WRITE)
962 return DMA_TO_DEVICE;
964 return DMA_FROM_DEVICE;
967 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
971 spin_lock(&host->irq_lock);
972 host->req_in_progress = 0;
973 dma_ch = host->dma_ch;
974 spin_unlock(&host->irq_lock);
976 omap_hsmmc_disable_irq(host);
977 /* Do not complete the request if DMA is still in progress */
978 if (mrq->data && host->use_dma && dma_ch != -1)
981 mmc_request_done(host->mmc, mrq);
985 * Notify the transfer complete to MMC core
988 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
991 struct mmc_request *mrq = host->mrq;
993 /* TC before CC from CMD6 - don't know why, but it happens */
994 if (host->cmd && host->cmd->opcode == 6 &&
995 host->response_busy) {
996 host->response_busy = 0;
1000 omap_hsmmc_request_done(host, mrq);
1007 data->bytes_xfered += data->blocks * (data->blksz);
1009 data->bytes_xfered = 0;
1012 omap_hsmmc_request_done(host, data->mrq);
1015 omap_hsmmc_start_command(host, data->stop, NULL);
1019 * Notify the core about command completion
1022 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
1026 if (cmd->flags & MMC_RSP_PRESENT) {
1027 if (cmd->flags & MMC_RSP_136) {
1028 /* response type 2 */
1029 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1030 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1031 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1032 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1034 /* response types 1, 1b, 3, 4, 5, 6 */
1035 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1038 if ((host->data == NULL && !host->response_busy) || cmd->error)
1039 omap_hsmmc_request_done(host, cmd->mrq);
1043 * DMA clean up for command errors
1045 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1049 host->data->error = errno;
1051 spin_lock(&host->irq_lock);
1052 dma_ch = host->dma_ch;
1054 spin_unlock(&host->irq_lock);
1056 if (host->use_dma && dma_ch != -1) {
1057 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1059 omap_hsmmc_get_dma_dir(host, host->data));
1060 host->data->host_cookie = 0;
1066 * Readable error output
1068 #ifdef CONFIG_MMC_DEBUG
1069 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1071 /* --- means reserved bit without definition at documentation */
1072 static const char *omap_hsmmc_status_bits[] = {
1073 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1074 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1075 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1076 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1082 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1085 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1086 if (status & (1 << i)) {
1087 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1091 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1094 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1098 #endif /* CONFIG_MMC_DEBUG */
1101 * MMC controller internal state machines reset
1103 * Used to reset command or data internal state machines, using respectively
1104 * SRC or SRD bit of SYSCTL register
1105 * Can be called from interrupt context
1107 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1110 unsigned long i = 0;
1111 unsigned long limit = (loops_per_jiffy *
1112 msecs_to_jiffies(MMC_TIMEOUT_MS));
1114 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1115 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1118 * OMAP4 ES2 and greater has an updated reset logic.
1119 * Monitor a 0->1 transition first
1121 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1122 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1128 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1132 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1133 dev_err(mmc_dev(host->mmc),
1134 "Timeout waiting on controller reset in %s\n",
1138 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1140 struct mmc_data *data;
1141 int end_cmd = 0, end_trans = 0;
1143 if (unlikely(!host->req_in_progress)) {
1144 OMAP_HSMMC_WRITE(host->base, STAT, status);
1149 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1151 if (unlikely(status & ERR)) {
1152 omap_hsmmc_dbg_report_irq(host, status);
1153 if ((status & CMD_TIMEOUT) ||
1154 (status & CMD_CRC)) {
1156 if (status & CMD_TIMEOUT) {
1157 omap_hsmmc_reset_controller_fsm(host,
1159 host->cmd->error = -ETIMEDOUT;
1161 host->cmd->error = -EILSEQ;
1165 if (host->data || host->response_busy) {
1167 omap_hsmmc_dma_cleanup(host,
1169 host->response_busy = 0;
1170 omap_hsmmc_reset_controller_fsm(host, SRD);
1173 if ((status & DATA_TIMEOUT) ||
1174 (status & DATA_CRC)) {
1175 if (host->data || host->response_busy) {
1176 int err = (status & DATA_TIMEOUT) ?
1177 -ETIMEDOUT : -EILSEQ;
1180 omap_hsmmc_dma_cleanup(host, err);
1182 host->mrq->cmd->error = err;
1183 host->response_busy = 0;
1184 omap_hsmmc_reset_controller_fsm(host, SRD);
1188 if (status & CARD_ERR) {
1189 dev_dbg(mmc_dev(host->mmc),
1190 "Ignoring card err CMD%d\n", host->cmd->opcode);
1198 OMAP_HSMMC_WRITE(host->base, STAT, status);
1200 if (end_cmd || ((status & CC) && host->cmd))
1201 omap_hsmmc_cmd_done(host, host->cmd);
1202 if ((end_trans || (status & TC)) && host->mrq)
1203 omap_hsmmc_xfer_done(host, data);
1207 * MMC controller IRQ handler
1209 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1211 struct omap_hsmmc_host *host = dev_id;
1214 status = OMAP_HSMMC_READ(host->base, STAT);
1216 omap_hsmmc_do_irq(host, status);
1217 /* Flush posted write */
1218 status = OMAP_HSMMC_READ(host->base, STAT);
1219 } while (status & INT_EN_MASK);
1224 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1228 OMAP_HSMMC_WRITE(host->base, HCTL,
1229 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1230 for (i = 0; i < loops_per_jiffy; i++) {
1231 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1238 * Switch MMC interface voltage ... only relevant for MMC1.
1240 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1241 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1242 * Some chips, like eMMC ones, use internal transceivers.
1244 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1249 /* Disable the clocks */
1250 pm_runtime_put_sync(host->dev);
1251 if (host->got_dbclk)
1252 clk_disable(host->dbclk);
1254 /* Turn the power off */
1255 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1257 /* Turn the power ON with given VDD 1.8 or 3.0v */
1259 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1261 pm_runtime_get_sync(host->dev);
1262 if (host->got_dbclk)
1263 clk_enable(host->dbclk);
1268 OMAP_HSMMC_WRITE(host->base, HCTL,
1269 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1270 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1273 * If a MMC dual voltage card is detected, the set_ios fn calls
1274 * this fn with VDD bit set for 1.8V. Upon card removal from the
1275 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1277 * Cope with a bit of slop in the range ... per data sheets:
1278 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1279 * but recommended values are 1.71V to 1.89V
1280 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1281 * but recommended values are 2.7V to 3.3V
1283 * Board setup code shouldn't permit anything very out-of-range.
1284 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1285 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1287 if ((1 << vdd) <= MMC_VDD_23_24)
1292 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1293 set_sd_bus_power(host);
1297 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1301 /* Protect the card while the cover is open */
1302 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1304 if (!mmc_slot(host).get_cover_state)
1307 host->reqs_blocked = 0;
1308 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1309 if (host->protect_card) {
1310 pr_info("%s: cover is closed, "
1311 "card is now accessible\n",
1312 mmc_hostname(host->mmc));
1313 host->protect_card = 0;
1316 if (!host->protect_card) {
1317 pr_info("%s: cover is open, "
1318 "card is now inaccessible\n",
1319 mmc_hostname(host->mmc));
1320 host->protect_card = 1;
1326 * irq handler to notify the core about card insertion/removal
1328 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1330 struct omap_hsmmc_host *host = dev_id;
1331 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1334 if (host->suspended)
1337 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1339 if (slot->card_detect)
1340 carddetect = slot->card_detect(host->dev, host->slot_id);
1342 omap_hsmmc_protect_card(host);
1343 carddetect = -ENOSYS;
1347 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1349 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1353 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1354 struct mmc_data *data)
1358 if (data->flags & MMC_DATA_WRITE)
1359 sync_dev = host->dma_line_tx;
1361 sync_dev = host->dma_line_rx;
1365 static void omap_hsmmc_config_dma_params_once(struct omap_hsmmc_host *host,
1366 struct mmc_data *data,
1369 if (data->flags & MMC_DATA_WRITE) {
1370 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1371 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1372 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_16);
1373 omap_set_dma_src_data_pack(dma_ch, 1);
1375 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1376 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1377 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_16);
1378 omap_set_dma_dest_data_pack(dma_ch, 1);
1379 omap_set_dma_write_mode(dma_ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
1383 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1384 struct mmc_data *data,
1385 struct scatterlist *sgl)
1387 int blksz, nblk, dma_ch, sync;
1389 dma_ch = host->dma_ch;
1390 if (data->flags & MMC_DATA_WRITE) {
1391 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1392 sg_dma_address(sgl), 0, 0);
1393 sync = OMAP_DMA_DST_SYNC_PREFETCH;
1395 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1396 sg_dma_address(sgl), 0, 0);
1397 sync = OMAP_DMA_SRC_SYNC;
1400 blksz = host->data->blksz;
1401 nblk = sg_dma_len(sgl) / blksz;
1403 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1404 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1405 omap_hsmmc_get_dma_sync_dev(host, data), sync);
1407 omap_start_dma(dma_ch);
1411 * DMA call back function
1413 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1415 struct omap_hsmmc_host *host = cb_data;
1416 struct mmc_data *data;
1417 int req_in_progress;
1419 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1420 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1425 spin_lock(&host->irq_lock);
1426 if (host->dma_ch < 0) {
1427 spin_unlock(&host->irq_lock);
1431 data = host->mrq->data;
1433 if (host->dma_sg_idx < host->dma_len) {
1434 /* Fire up the next transfer. */
1435 omap_hsmmc_config_dma_params(host, data,
1436 data->sg + host->dma_sg_idx);
1437 spin_unlock(&host->irq_lock);
1441 if (!data->host_cookie)
1442 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1443 omap_hsmmc_get_dma_dir(host, data));
1445 req_in_progress = host->req_in_progress;
1447 spin_unlock(&host->irq_lock);
1449 /* If DMA has finished after TC, complete the request */
1450 if (!req_in_progress) {
1451 struct mmc_request *mrq = host->mrq;
1454 mmc_request_done(host->mmc, mrq);
1458 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1459 struct mmc_data *data,
1460 struct omap_hsmmc_next *next)
1464 if (unlikely(!next && data->host_cookie &&
1465 data->host_cookie != host->next_data.cookie)) {
1466 pr_warning("[%s] invalid cookie: data->host_cookie %d"
1467 " host->next_data.cookie %d\n",
1468 __func__, data->host_cookie, host->next_data.cookie);
1469 data->host_cookie = 0;
1472 /* Check if next job is already prepared */
1474 (!next && data->host_cookie != host->next_data.cookie)) {
1475 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1477 omap_hsmmc_get_dma_dir(host, data));
1480 dma_len = host->next_data.dma_len;
1481 host->next_data.dma_len = 0;
1485 if (unlikely(dma_len == 0))
1489 next->dma_len = dma_len;
1490 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1492 host->dma_len = dma_len;
1498 * Routine to configure and start DMA for the MMC card
1500 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1501 struct mmc_request *req)
1503 int dma_ch = 0, ret = 0, i;
1504 struct mmc_data *data = req->data;
1506 /* Sanity check: all the SG entries must be aligned by block size. */
1507 for (i = 0; i < data->sg_len; i++) {
1508 struct scatterlist *sgl;
1511 if (unlikely(sgl->length % data->blksz))
1514 if (unlikely((data->blksz % 4) != 0))
1515 /* REVISIT: The MMC buffer increments only when MSB is written.
1516 * Return error for blksz which is non multiple of four.
1520 BUG_ON(host->dma_ch != -1);
1522 if (data->flags & MMC_DATA_WRITE)
1523 dma_ch = host->dma_ch_tx;
1525 dma_ch = host->dma_ch_rx;
1528 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1529 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1530 if (unlikely(ret != 0)) {
1531 dev_err(mmc_dev(host->mmc),
1532 "%s: omap_request_dma() failed with %d\n",
1533 mmc_hostname(host->mmc), ret);
1537 omap_hsmmc_config_dma_params_once(host, data, dma_ch);
1539 if (data->flags & MMC_DATA_WRITE)
1540 host->dma_ch_tx = dma_ch;
1542 host->dma_ch_rx = dma_ch;
1545 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1549 host->dma_ch = dma_ch;
1550 host->dma_sg_idx = 0;
1552 omap_hsmmc_config_dma_params(host, data, data->sg);
1557 /* pandora wifi small transfer hack */
1558 static int check_mmc3_dma_hack(struct omap_hsmmc_host *host,
1559 struct mmc_request *req)
1561 if (req->data != NULL && req->data->sg_len == 1
1562 && req->data->sg->length <= 16)
1569 * Configure block length for MMC/SD cards and initiate the transfer.
1572 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1575 host->data = req->data;
1577 if (req->data == NULL) {
1578 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1582 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1583 | (req->data->blocks << 16));
1585 if (host->use_dma) {
1586 ret = omap_hsmmc_start_dma_transfer(host, req);
1588 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1595 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1598 struct omap_hsmmc_host *host = mmc_priv(mmc);
1599 struct mmc_data *data = mrq->data;
1601 if (host->use_dma) {
1602 if (data->host_cookie)
1603 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1605 omap_hsmmc_get_dma_dir(host, data));
1606 data->host_cookie = 0;
1610 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1613 struct omap_hsmmc_host *host = mmc_priv(mmc);
1614 int use_dma = host->use_dma;
1616 if (mrq->data->host_cookie) {
1617 mrq->data->host_cookie = 0;
1621 if (host->id == OMAP_MMC3_DEVID)
1622 use_dma = check_mmc3_dma_hack(host, mrq);
1624 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1626 mrq->data->host_cookie = 0;
1629 #define BWR (1 << 4)
1630 #define BRR (1 << 5)
1632 static noinline void omap_hsmmc_request_do_pio(struct mmc_host *mmc,
1633 struct mmc_request *req)
1635 struct omap_hsmmc_host *host = mmc_priv(mmc);
1636 u32 *data = sg_virt(req->data->sg);
1637 u32 len = req->data->sg->length;
1641 for (i = 0; i < 10000000; i++) {
1642 stat = OMAP_HSMMC_READ(host->base, STAT);
1646 //dev_err(mmc_dev(host->mmc), "stat %x, l %d\n", stat, i);
1648 if (stat & (DATA_TIMEOUT | DATA_CRC))
1649 omap_hsmmc_reset_controller_fsm(host, SRD);
1653 req->data->error = -EINVAL; // ?
1654 omap_hsmmc_xfer_done(host, host->data);
1658 if (req->data->flags & MMC_DATA_WRITE) {
1659 while (len > 0 && (stat & BWR)) {
1660 OMAP_HSMMC_WRITE(host->base, DATA, *data++);
1664 while (len > 0 && (stat & BRR)) {
1665 *data++ = OMAP_HSMMC_READ(host->base, DATA);
1670 if ((stat & CC) && host->cmd)
1671 omap_hsmmc_cmd_done(host, host->cmd);
1672 if ((stat & TC) && host->mrq) {
1673 omap_hsmmc_xfer_done(host, host->data);
1680 req->data->error = -ETIMEDOUT;
1681 omap_hsmmc_xfer_done(host, req->data);
1686 * Request function. for read/write operation
1688 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1690 struct omap_hsmmc_host *host = mmc_priv(mmc);
1693 BUG_ON(host->req_in_progress);
1694 BUG_ON(host->dma_ch != -1);
1695 if (unlikely(host->protect_card)) {
1696 if (host->reqs_blocked < 3) {
1698 * Ensure the controller is left in a consistent
1699 * state by resetting the command and data state
1702 omap_hsmmc_reset_controller_fsm(host, SRD);
1703 omap_hsmmc_reset_controller_fsm(host, SRC);
1704 host->reqs_blocked += 1;
1706 req->cmd->error = -EBADF;
1708 req->data->error = -EBADF;
1709 req->cmd->retries = 0;
1710 mmc_request_done(mmc, req);
1712 } else if (host->reqs_blocked)
1713 host->reqs_blocked = 0;
1715 /* pandora wifi hack... */
1716 if (host->id == OMAP_MMC3_DEVID)
1717 host->use_dma = check_mmc3_dma_hack(host, req);
1719 WARN_ON(host->mrq != NULL);
1721 err = omap_hsmmc_prepare_data(host, req);
1722 if (unlikely(err)) {
1723 req->cmd->error = err;
1725 req->data->error = err;
1727 mmc_request_done(mmc, req);
1731 omap_hsmmc_start_command(host, req->cmd, req->data);
1733 if (host->use_dma == 0)
1734 omap_hsmmc_request_do_pio(mmc, req);
1737 /* Routine to configure clock values. Exposed API to core */
1738 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1740 struct omap_hsmmc_host *host = mmc_priv(mmc);
1741 int do_send_init_stream = 0;
1743 pm_runtime_get_sync(host->dev);
1745 if (ios->power_mode != host->power_mode) {
1746 switch (ios->power_mode) {
1748 mmc_slot(host).set_power(host->dev, host->slot_id,
1753 mmc_slot(host).set_power(host->dev, host->slot_id,
1755 host->vdd = ios->vdd;
1758 do_send_init_stream = 1;
1761 host->power_mode = ios->power_mode;
1764 /* FIXME: set registers based only on changes to ios */
1766 omap_hsmmc_set_bus_width(host);
1768 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1769 /* Only MMC1 can interface at 3V without some flavor
1770 * of external transceiver; but they all handle 1.8V.
1772 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1773 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1775 * The mmc_select_voltage fn of the core does
1776 * not seem to set the power_mode to
1777 * MMC_POWER_UP upon recalculating the voltage.
1780 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1781 dev_dbg(mmc_dev(host->mmc),
1782 "Switch operation failed\n");
1786 omap_hsmmc_set_clock(host);
1788 if (do_send_init_stream)
1789 send_init_stream(host);
1791 omap_hsmmc_set_bus_mode(host);
1793 pm_runtime_put_autosuspend(host->dev);
1796 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1798 struct omap_hsmmc_host *host = mmc_priv(mmc);
1800 if (!mmc_slot(host).card_detect)
1802 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1805 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1807 struct omap_hsmmc_host *host = mmc_priv(mmc);
1809 if (!mmc_slot(host).get_ro)
1811 return mmc_slot(host).get_ro(host->dev, 0);
1814 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1816 struct omap_hsmmc_host *host = mmc_priv(mmc);
1818 if (mmc_slot(host).init_card)
1819 mmc_slot(host).init_card(card);
1822 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1824 u32 hctl, capa, value;
1826 /* Only MMC1 supports 3.0V */
1827 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1835 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1836 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1838 value = OMAP_HSMMC_READ(host->base, CAPA);
1839 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1841 /* Set the controller to AUTO IDLE mode */
1842 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1843 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1845 /* Set SD bus power bit */
1846 set_sd_bus_power(host);
1849 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1851 struct omap_hsmmc_host *host = mmc_priv(mmc);
1853 pm_runtime_get_sync(host->dev);
1858 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1860 struct omap_hsmmc_host *host = mmc_priv(mmc);
1862 pm_runtime_mark_last_busy(host->dev);
1863 pm_runtime_put_autosuspend(host->dev);
1868 static const struct mmc_host_ops omap_hsmmc_ops = {
1869 .enable = omap_hsmmc_enable_fclk,
1870 .disable = omap_hsmmc_disable_fclk,
1871 .post_req = omap_hsmmc_post_req,
1872 .pre_req = omap_hsmmc_pre_req,
1873 .request = omap_hsmmc_request,
1874 .set_ios = omap_hsmmc_set_ios,
1875 .get_cd = omap_hsmmc_get_cd,
1876 .get_ro = omap_hsmmc_get_ro,
1877 .init_card = omap_hsmmc_init_card,
1878 /* NYET -- enable_sdio_irq */
1881 #ifdef CONFIG_DEBUG_FS
1883 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1885 struct mmc_host *mmc = s->private;
1886 struct omap_hsmmc_host *host = mmc_priv(mmc);
1887 int context_loss = 0;
1889 if (host->pdata->get_context_loss_count)
1890 context_loss = host->pdata->get_context_loss_count(host->dev);
1892 seq_printf(s, "mmc%d:\n"
1895 " nesting_cnt:\t%d\n"
1896 " ctx_loss:\t%d:%d\n"
1898 mmc->index, mmc->enabled ? 1 : 0,
1899 host->dpm_state, mmc->nesting_cnt,
1900 host->context_loss, context_loss);
1902 if (host->suspended) {
1903 seq_printf(s, "host suspended, can't read registers\n");
1907 pm_runtime_get_sync(host->dev);
1909 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1910 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1911 seq_printf(s, "CON:\t\t0x%08x\n",
1912 OMAP_HSMMC_READ(host->base, CON));
1913 seq_printf(s, "HCTL:\t\t0x%08x\n",
1914 OMAP_HSMMC_READ(host->base, HCTL));
1915 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1916 OMAP_HSMMC_READ(host->base, SYSCTL));
1917 seq_printf(s, "IE:\t\t0x%08x\n",
1918 OMAP_HSMMC_READ(host->base, IE));
1919 seq_printf(s, "ISE:\t\t0x%08x\n",
1920 OMAP_HSMMC_READ(host->base, ISE));
1921 seq_printf(s, "CAPA:\t\t0x%08x\n",
1922 OMAP_HSMMC_READ(host->base, CAPA));
1924 pm_runtime_mark_last_busy(host->dev);
1925 pm_runtime_put_autosuspend(host->dev);
1930 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1932 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1935 static const struct file_operations mmc_regs_fops = {
1936 .open = omap_hsmmc_regs_open,
1938 .llseek = seq_lseek,
1939 .release = single_release,
1942 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1944 if (mmc->debugfs_root)
1945 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1946 mmc, &mmc_regs_fops);
1951 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1957 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1959 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1960 struct mmc_host *mmc;
1961 struct omap_hsmmc_host *host = NULL;
1962 struct resource *res;
1965 if (pdata == NULL) {
1966 dev_err(&pdev->dev, "Platform Data is missing\n");
1970 if (pdata->nr_slots == 0) {
1971 dev_err(&pdev->dev, "No Slots\n");
1975 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1976 irq = platform_get_irq(pdev, 0);
1977 if (res == NULL || irq < 0)
1980 res->start += pdata->reg_offset;
1981 res->end += pdata->reg_offset;
1982 res = request_mem_region(res->start, resource_size(res), pdev->name);
1986 ret = omap_hsmmc_gpio_init(pdata);
1990 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1996 host = mmc_priv(mmc);
1998 host->pdata = pdata;
1999 host->dev = &pdev->dev;
2001 host->dev->dma_mask = &pdata->dma_mask;
2003 host->dma_ch_tx = -1;
2004 host->dma_ch_rx = -1;
2006 host->id = pdev->id;
2008 host->mapbase = res->start;
2009 host->base = ioremap(host->mapbase, SZ_4K);
2010 host->power_mode = MMC_POWER_OFF;
2011 host->next_data.cookie = 1;
2013 platform_set_drvdata(pdev, host);
2015 mmc->ops = &omap_hsmmc_ops;
2018 * If regulator_disable can only put vcc_aux to sleep then there is
2021 if (mmc_slot(host).vcc_aux_disable_is_sleep)
2022 mmc_slot(host).no_off = 1;
2024 mmc->f_min = OMAP_MMC_MIN_CLOCK;
2025 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2027 spin_lock_init(&host->irq_lock);
2029 host->fclk = clk_get(&pdev->dev, "fck");
2030 if (IS_ERR(host->fclk)) {
2031 ret = PTR_ERR(host->fclk);
2036 omap_hsmmc_context_save(host);
2038 mmc->caps |= MMC_CAP_DISABLE;
2040 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2041 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2042 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
2045 pm_runtime_enable(host->dev);
2046 pm_runtime_get_sync(host->dev);
2047 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2048 pm_runtime_use_autosuspend(host->dev);
2050 if (cpu_is_omap2430()) {
2051 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2053 * MMC can still work without debounce clock.
2055 if (IS_ERR(host->dbclk))
2056 dev_warn(mmc_dev(host->mmc),
2057 "Failed to get debounce clock\n");
2059 host->got_dbclk = 1;
2061 if (host->got_dbclk)
2062 if (clk_enable(host->dbclk) != 0)
2063 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2067 /* Since we do only SG emulation, we can have as many segs
2069 mmc->max_segs = 1024;
2071 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2072 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2073 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2074 mmc->max_seg_size = mmc->max_req_size;
2076 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2077 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2079 mmc->caps |= mmc_slot(host).caps;
2080 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2081 mmc->caps |= MMC_CAP_4_BIT_DATA;
2083 if (mmc_slot(host).nonremovable)
2084 mmc->caps |= MMC_CAP_NONREMOVABLE;
2086 omap_hsmmc_conf_bus_power(host);
2088 /* Select DMA lines */
2090 case OMAP_MMC1_DEVID:
2091 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2092 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2094 case OMAP_MMC2_DEVID:
2095 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2096 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2098 case OMAP_MMC3_DEVID:
2099 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2100 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2102 case OMAP_MMC4_DEVID:
2103 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2104 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2106 case OMAP_MMC5_DEVID:
2107 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2108 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2111 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2115 /* Request IRQ for MMC operations */
2116 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
2117 mmc_hostname(mmc), host);
2119 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2123 if (pdata->init != NULL) {
2124 if (pdata->init(&pdev->dev) != 0) {
2125 dev_dbg(mmc_dev(host->mmc),
2126 "Unable to configure MMC IRQs\n");
2127 goto err_irq_cd_init;
2131 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2132 ret = omap_hsmmc_reg_get(host);
2138 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2140 /* Request IRQ for card detect */
2141 if ((mmc_slot(host).card_detect_irq)) {
2142 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
2145 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2146 mmc_hostname(mmc), host);
2148 dev_dbg(mmc_dev(host->mmc),
2149 "Unable to grab MMC CD IRQ\n");
2152 pdata->suspend = omap_hsmmc_suspend_cdirq;
2153 pdata->resume = omap_hsmmc_resume_cdirq;
2156 omap_hsmmc_disable_irq(host);
2158 omap_hsmmc_protect_card(host);
2162 if (mmc_slot(host).name != NULL) {
2163 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2167 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2168 ret = device_create_file(&mmc->class_dev,
2169 &dev_attr_cover_switch);
2174 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2175 ret = device_create_file(&mmc->class_dev, &dev_attr_unsafe_read);
2177 /* MMC_CAP2_NO_MULTI_READ makes it crawl, try a different workaround */
2178 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
2180 mmc->f_max = 32000000;
2183 omap_hsmmc_debugfs(mmc);
2184 pm_runtime_mark_last_busy(host->dev);
2185 pm_runtime_put_autosuspend(host->dev);
2190 mmc_remove_host(mmc);
2191 free_irq(mmc_slot(host).card_detect_irq, host);
2194 omap_hsmmc_reg_put(host);
2196 if (host->pdata->cleanup)
2197 host->pdata->cleanup(&pdev->dev);
2199 free_irq(host->irq, host);
2201 pm_runtime_mark_last_busy(host->dev);
2202 pm_runtime_put_autosuspend(host->dev);
2203 clk_put(host->fclk);
2204 if (host->got_dbclk) {
2205 clk_disable(host->dbclk);
2206 clk_put(host->dbclk);
2209 iounmap(host->base);
2210 platform_set_drvdata(pdev, NULL);
2213 omap_hsmmc_gpio_free(pdata);
2215 release_mem_region(res->start, resource_size(res));
2219 static int omap_hsmmc_remove(struct platform_device *pdev)
2221 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2222 struct resource *res;
2225 pm_runtime_get_sync(host->dev);
2226 mmc_remove_host(host->mmc);
2228 omap_hsmmc_reg_put(host);
2229 if (host->pdata->cleanup)
2230 host->pdata->cleanup(&pdev->dev);
2231 free_irq(host->irq, host);
2232 if (mmc_slot(host).card_detect_irq)
2233 free_irq(mmc_slot(host).card_detect_irq, host);
2235 pm_runtime_put_sync(host->dev);
2236 pm_runtime_disable(host->dev);
2237 clk_put(host->fclk);
2238 if (host->got_dbclk) {
2239 clk_disable(host->dbclk);
2240 clk_put(host->dbclk);
2243 mmc_free_host(host->mmc);
2244 iounmap(host->base);
2245 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2248 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2250 release_mem_region(res->start, resource_size(res));
2251 platform_set_drvdata(pdev, NULL);
2257 static int omap_hsmmc_suspend(struct device *dev)
2260 struct platform_device *pdev = to_platform_device(dev);
2261 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2263 if (host && host->suspended)
2267 pm_runtime_get_sync(host->dev);
2268 host->suspended = 1;
2269 if (host->pdata->suspend) {
2270 ret = host->pdata->suspend(&pdev->dev,
2273 dev_dbg(mmc_dev(host->mmc),
2274 "Unable to handle MMC board"
2275 " level suspend\n");
2276 host->suspended = 0;
2280 ret = mmc_suspend_host(host->mmc);
2283 omap_hsmmc_disable_irq(host);
2284 OMAP_HSMMC_WRITE(host->base, HCTL,
2285 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2286 if (host->got_dbclk)
2287 clk_disable(host->dbclk);
2289 host->suspended = 0;
2290 if (host->pdata->resume) {
2291 if (host->pdata->resume(&pdev->dev, host->slot_id))
2292 dev_dbg(mmc_dev(host->mmc),
2293 "Unmask interrupt failed\n");
2296 pm_runtime_put_sync(host->dev);
2301 /* Routine to resume the MMC device */
2302 static int omap_hsmmc_resume(struct device *dev)
2305 struct platform_device *pdev = to_platform_device(dev);
2306 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2308 if (host && !host->suspended)
2312 pm_runtime_get_sync(host->dev);
2314 if (host->got_dbclk)
2315 clk_enable(host->dbclk);
2317 omap_hsmmc_conf_bus_power(host);
2319 if (host->pdata->resume) {
2320 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2322 dev_dbg(mmc_dev(host->mmc),
2323 "Unmask interrupt failed\n");
2326 omap_hsmmc_protect_card(host);
2328 /* Notify the core to resume the host */
2329 ret = mmc_resume_host(host->mmc);
2331 host->suspended = 0;
2333 pm_runtime_mark_last_busy(host->dev);
2334 pm_runtime_put_autosuspend(host->dev);
2342 #define omap_hsmmc_suspend NULL
2343 #define omap_hsmmc_resume NULL
2346 static int omap_hsmmc_runtime_suspend(struct device *dev)
2348 struct omap_hsmmc_host *host;
2351 host = platform_get_drvdata(to_platform_device(dev));
2352 omap_hsmmc_context_save(host);
2354 dma_ch = xchg(&host->dma_ch_tx, -1);
2356 omap_free_dma(dma_ch);
2358 dma_ch = xchg(&host->dma_ch_rx, -1);
2360 omap_free_dma(dma_ch);
2362 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2367 static int omap_hsmmc_runtime_resume(struct device *dev)
2369 struct omap_hsmmc_host *host;
2371 host = platform_get_drvdata(to_platform_device(dev));
2372 omap_hsmmc_context_restore(host);
2373 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2378 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2379 .suspend = omap_hsmmc_suspend,
2380 .resume = omap_hsmmc_resume,
2381 .runtime_suspend = omap_hsmmc_runtime_suspend,
2382 .runtime_resume = omap_hsmmc_runtime_resume,
2385 static struct platform_driver omap_hsmmc_driver = {
2386 .remove = omap_hsmmc_remove,
2388 .name = DRIVER_NAME,
2389 .owner = THIS_MODULE,
2390 .pm = &omap_hsmmc_dev_pm_ops,
2394 static int __init omap_hsmmc_init(void)
2396 /* Register the MMC driver */
2397 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2400 static void __exit omap_hsmmc_cleanup(void)
2402 /* Unregister MMC driver */
2403 platform_driver_unregister(&omap_hsmmc_driver);
2406 module_init(omap_hsmmc_init);
2407 module_exit(omap_hsmmc_cleanup);
2409 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2410 MODULE_LICENSE("GPL");
2411 MODULE_ALIAS("platform:" DRIVER_NAME);
2412 MODULE_AUTHOR("Texas Instruments Inc");