348f577b66cf2753a78cc2518a4f3cc49eae95ec
[pandora-kernel.git] / drivers / mmc / host / omap_hsmmc.c
1 /*
2  * drivers/mmc/host/omap_hsmmc.c
3  *
4  * Driver for OMAP2430/3430 MMC controller.
5  *
6  * Copyright (C) 2007 Texas Instruments.
7  *
8  * Authors:
9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
10  *      Madhusudhan             <madhu.cr@ti.com>
11  *      Mohit Jalori            <mjalori@ti.com>
12  *
13  * This file is licensed under the terms of the GNU General Public License
14  * version 2. This program is licensed "as is" without any warranty of any
15  * kind, whether express or implied.
16  */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/io.h>
33 #include <linux/semaphore.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
37 #include <plat/dma.h>
38 #include <mach/hardware.h>
39 #include <plat/board.h>
40 #include <plat/mmc.h>
41 #include <plat/cpu.h>
42
43 /* OMAP HSMMC Host Controller Registers */
44 #define OMAP_HSMMC_SYSCONFIG    0x0010
45 #define OMAP_HSMMC_SYSSTATUS    0x0014
46 #define OMAP_HSMMC_CON          0x002C
47 #define OMAP_HSMMC_BLK          0x0104
48 #define OMAP_HSMMC_ARG          0x0108
49 #define OMAP_HSMMC_CMD          0x010C
50 #define OMAP_HSMMC_RSP10        0x0110
51 #define OMAP_HSMMC_RSP32        0x0114
52 #define OMAP_HSMMC_RSP54        0x0118
53 #define OMAP_HSMMC_RSP76        0x011C
54 #define OMAP_HSMMC_DATA         0x0120
55 #define OMAP_HSMMC_HCTL         0x0128
56 #define OMAP_HSMMC_SYSCTL       0x012C
57 #define OMAP_HSMMC_STAT         0x0130
58 #define OMAP_HSMMC_IE           0x0134
59 #define OMAP_HSMMC_ISE          0x0138
60 #define OMAP_HSMMC_CAPA         0x0140
61
62 #define VS18                    (1 << 26)
63 #define VS30                    (1 << 25)
64 #define SDVS18                  (0x5 << 9)
65 #define SDVS30                  (0x6 << 9)
66 #define SDVS33                  (0x7 << 9)
67 #define SDVS_MASK               0x00000E00
68 #define SDVSCLR                 0xFFFFF1FF
69 #define SDVSDET                 0x00000400
70 #define AUTOIDLE                0x1
71 #define SDBP                    (1 << 8)
72 #define DTO                     0xe
73 #define ICE                     0x1
74 #define ICS                     0x2
75 #define CEN                     (1 << 2)
76 #define CLKD_MASK               0x0000FFC0
77 #define CLKD_SHIFT              6
78 #define DTO_MASK                0x000F0000
79 #define DTO_SHIFT               16
80 #define INT_EN_MASK             0x307F0033
81 #define BWR_ENABLE              (1 << 4)
82 #define BRR_ENABLE              (1 << 5)
83 #define DTO_ENABLE              (1 << 20)
84 #define INIT_STREAM             (1 << 1)
85 #define DP_SELECT               (1 << 21)
86 #define DDIR                    (1 << 4)
87 #define DMA_EN                  0x1
88 #define MSBS                    (1 << 5)
89 #define BCE                     (1 << 1)
90 #define FOUR_BIT                (1 << 1)
91 #define DW8                     (1 << 5)
92 #define CC                      0x1
93 #define TC                      0x02
94 #define OD                      0x1
95 #define ERR                     (1 << 15)
96 #define CMD_TIMEOUT             (1 << 16)
97 #define DATA_TIMEOUT            (1 << 20)
98 #define CMD_CRC                 (1 << 17)
99 #define DATA_CRC                (1 << 21)
100 #define CARD_ERR                (1 << 28)
101 #define STAT_CLEAR              0xFFFFFFFF
102 #define INIT_STREAM_CMD         0x00000000
103 #define DUAL_VOLT_OCR_BIT       7
104 #define SRC                     (1 << 25)
105 #define SRD                     (1 << 26)
106 #define SOFTRESET               (1 << 1)
107 #define RESETDONE               (1 << 0)
108
109 /*
110  * FIXME: Most likely all the data using these _DEVID defines should come
111  * from the platform_data, or implemented in controller and slot specific
112  * functions.
113  */
114 #define OMAP_MMC1_DEVID         0
115 #define OMAP_MMC2_DEVID         1
116 #define OMAP_MMC3_DEVID         2
117 #define OMAP_MMC4_DEVID         3
118 #define OMAP_MMC5_DEVID         4
119
120 #define MMC_AUTOSUSPEND_DELAY   100
121 #define MMC_TIMEOUT_MS          20
122 #define OMAP_MMC_MASTER_CLOCK   96000000
123 #define OMAP_MMC_MIN_CLOCK      400000
124 #define OMAP_MMC_MAX_CLOCK      52000000
125 #define DRIVER_NAME             "omap_hsmmc"
126
127 /*
128  * One controller can have multiple slots, like on some omap boards using
129  * omap.c controller driver. Luckily this is not currently done on any known
130  * omap_hsmmc.c device.
131  */
132 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
133
134 /*
135  * MMC Host controller read/write API's
136  */
137 #define OMAP_HSMMC_READ(base, reg)      \
138         __raw_readl((base) + OMAP_HSMMC_##reg)
139
140 #define OMAP_HSMMC_WRITE(base, reg, val) \
141         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
142
143 struct omap_hsmmc_next {
144         unsigned int    dma_len;
145         s32             cookie;
146 };
147
148 struct omap_hsmmc_host {
149         struct  device          *dev;
150         struct  mmc_host        *mmc;
151         struct  mmc_request     *mrq;
152         struct  mmc_command     *cmd;
153         struct  mmc_data        *data;
154         struct  clk             *fclk;
155         struct  clk             *dbclk;
156         /*
157          * vcc == configured supply
158          * vcc_aux == optional
159          *   -  MMC1, supply for DAT4..DAT7
160          *   -  MMC2/MMC2, external level shifter voltage supply, for
161          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
162          */
163         struct  regulator       *vcc;
164         struct  regulator       *vcc_aux;
165         void    __iomem         *base;
166         resource_size_t         mapbase;
167         spinlock_t              irq_lock; /* Prevent races with irq handler */
168         unsigned int            id;
169         unsigned int            dma_len;
170         unsigned int            dma_sg_idx;
171         unsigned char           bus_mode;
172         unsigned char           power_mode;
173         u32                     *buffer;
174         u32                     bytesleft;
175         int                     suspended;
176         int                     irq;
177         int                     use_dma, dma_ch;
178         int                     dma_ch_tx, dma_ch_rx;
179         int                     dma_line_tx, dma_line_rx;
180         int                     slot_id;
181         int                     got_dbclk;
182         int                     response_busy;
183         int                     context_loss;
184         int                     dpm_state;
185         int                     vdd;
186         int                     protect_card;
187         int                     reqs_blocked;
188         int                     use_reg;
189         int                     req_in_progress;
190         struct omap_hsmmc_next  next_data;
191
192         struct  omap_mmc_platform_data  *pdata;
193 };
194
195 static int omap_hsmmc_card_detect(struct device *dev, int slot)
196 {
197         struct omap_mmc_platform_data *mmc = dev->platform_data;
198
199         /* NOTE: assumes card detect signal is active-low */
200         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
201 }
202
203 static int omap_hsmmc_get_wp(struct device *dev, int slot)
204 {
205         struct omap_mmc_platform_data *mmc = dev->platform_data;
206
207         /* NOTE: assumes write protect signal is active-high */
208         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
209 }
210
211 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
212 {
213         struct omap_mmc_platform_data *mmc = dev->platform_data;
214
215         /* NOTE: assumes card detect signal is active-low */
216         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
217 }
218
219 #ifdef CONFIG_PM
220
221 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
222 {
223         struct omap_mmc_platform_data *mmc = dev->platform_data;
224
225         disable_irq(mmc->slots[0].card_detect_irq);
226         return 0;
227 }
228
229 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
230 {
231         struct omap_mmc_platform_data *mmc = dev->platform_data;
232
233         enable_irq(mmc->slots[0].card_detect_irq);
234         return 0;
235 }
236
237 #else
238
239 #define omap_hsmmc_suspend_cdirq        NULL
240 #define omap_hsmmc_resume_cdirq         NULL
241
242 #endif
243
244 #ifdef CONFIG_REGULATOR
245
246 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
247                                   int vdd)
248 {
249         struct omap_hsmmc_host *host =
250                 platform_get_drvdata(to_platform_device(dev));
251         int ret;
252
253         if (mmc_slot(host).before_set_reg)
254                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
255
256         if (power_on)
257                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
258         else
259                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
260
261         if (mmc_slot(host).after_set_reg)
262                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
263
264         return ret;
265 }
266
267 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
268                                    int vdd)
269 {
270         struct omap_hsmmc_host *host =
271                 platform_get_drvdata(to_platform_device(dev));
272         int ret = 0;
273
274         /*
275          * If we don't see a Vcc regulator, assume it's a fixed
276          * voltage always-on regulator.
277          */
278         if (!host->vcc)
279                 return 0;
280
281         if (mmc_slot(host).before_set_reg)
282                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
283
284         /*
285          * Assume Vcc regulator is used only to power the card ... OMAP
286          * VDDS is used to power the pins, optionally with a transceiver to
287          * support cards using voltages other than VDDS (1.8V nominal).  When a
288          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
289          *
290          * In some cases this regulator won't support enable/disable;
291          * e.g. it's a fixed rail for a WLAN chip.
292          *
293          * In other cases vcc_aux switches interface power.  Example, for
294          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
295          * chips/cards need an interface voltage rail too.
296          */
297         if (power_on) {
298                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
299                 /* Enable interface voltage rail, if needed */
300                 if (ret == 0 && host->vcc_aux) {
301                         ret = regulator_enable(host->vcc_aux);
302                         if (ret < 0)
303                                 ret = mmc_regulator_set_ocr(host->mmc,
304                                                         host->vcc, 0);
305                 }
306         } else {
307                 /* Shut down the rail */
308                 if (host->vcc_aux)
309                         ret = regulator_disable(host->vcc_aux);
310                 if (!ret) {
311                         /* Then proceed to shut down the local regulator */
312                         ret = mmc_regulator_set_ocr(host->mmc,
313                                                 host->vcc, 0);
314                 }
315         }
316
317         if (mmc_slot(host).after_set_reg)
318                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
319
320         return ret;
321 }
322
323 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
324                                         int vdd)
325 {
326         return 0;
327 }
328
329 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
330                                   int vdd, int cardsleep)
331 {
332         struct omap_hsmmc_host *host =
333                 platform_get_drvdata(to_platform_device(dev));
334         int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
335
336         return regulator_set_mode(host->vcc, mode);
337 }
338
339 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
340                                    int vdd, int cardsleep)
341 {
342         struct omap_hsmmc_host *host =
343                 platform_get_drvdata(to_platform_device(dev));
344         int err, mode;
345
346         /*
347          * If we don't see a Vcc regulator, assume it's a fixed
348          * voltage always-on regulator.
349          */
350         if (!host->vcc)
351                 return 0;
352
353         mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
354
355         if (!host->vcc_aux)
356                 return regulator_set_mode(host->vcc, mode);
357
358         if (cardsleep) {
359                 /* VCC can be turned off if card is asleep */
360                 if (sleep)
361                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
362                 else
363                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
364         } else
365                 err = regulator_set_mode(host->vcc, mode);
366         if (err)
367                 return err;
368
369         if (!mmc_slot(host).vcc_aux_disable_is_sleep)
370                 return regulator_set_mode(host->vcc_aux, mode);
371
372         if (sleep)
373                 return regulator_disable(host->vcc_aux);
374         else
375                 return regulator_enable(host->vcc_aux);
376 }
377
378 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
379                                         int vdd, int cardsleep)
380 {
381         return 0;
382 }
383
384 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
385 {
386         struct regulator *reg;
387         int ret = 0;
388         int ocr_value = 0;
389
390         switch (host->id) {
391         case OMAP_MMC1_DEVID:
392                 /* On-chip level shifting via PBIAS0/PBIAS1 */
393                 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
394                 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
395                 break;
396         case OMAP_MMC2_DEVID:
397         case OMAP_MMC3_DEVID:
398         case OMAP_MMC5_DEVID:
399                 /* Off-chip level shifting, or none */
400                 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
401                 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
402                 break;
403         case OMAP_MMC4_DEVID:
404                 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
405                 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
406         default:
407                 pr_err("MMC%d configuration not supported!\n", host->id);
408                 return -EINVAL;
409         }
410
411         reg = regulator_get(host->dev, "vmmc");
412         if (IS_ERR(reg)) {
413                 dev_dbg(host->dev, "vmmc regulator missing\n");
414                 /*
415                 * HACK: until fixed.c regulator is usable,
416                 * we don't require a main regulator
417                 * for MMC2 or MMC3
418                 */
419                 if (host->id == OMAP_MMC1_DEVID) {
420                         ret = PTR_ERR(reg);
421                         goto err;
422                 }
423         } else {
424                 host->vcc = reg;
425                 ocr_value = mmc_regulator_get_ocrmask(reg);
426                 if (!mmc_slot(host).ocr_mask) {
427                         mmc_slot(host).ocr_mask = ocr_value;
428                 } else {
429                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
430                                 pr_err("MMC%d ocrmask %x is not supported\n",
431                                         host->id, mmc_slot(host).ocr_mask);
432                                 mmc_slot(host).ocr_mask = 0;
433                                 return -EINVAL;
434                         }
435                 }
436
437                 /* Allow an aux regulator */
438                 reg = regulator_get(host->dev, "vmmc_aux");
439                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
440
441                 /* For eMMC do not power off when not in sleep state */
442                 if (mmc_slot(host).no_regulator_off_init)
443                         return 0;
444                 /*
445                 * UGLY HACK:  workaround regulator framework bugs.
446                 * When the bootloader leaves a supply active, it's
447                 * initialized with zero usecount ... and we can't
448                 * disable it without first enabling it.  Until the
449                 * framework is fixed, we need a workaround like this
450                 * (which is safe for MMC, but not in general).
451                 */
452                 if (regulator_is_enabled(host->vcc) > 0 ||
453                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
454                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
455
456                         mmc_slot(host).set_power(host->dev, host->slot_id,
457                                                  1, vdd);
458                         mmc_slot(host).set_power(host->dev, host->slot_id,
459                                                  0, 0);
460                 }
461         }
462
463         return 0;
464
465 err:
466         mmc_slot(host).set_power = NULL;
467         mmc_slot(host).set_sleep = NULL;
468         return ret;
469 }
470
471 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
472 {
473         regulator_put(host->vcc);
474         regulator_put(host->vcc_aux);
475         mmc_slot(host).set_power = NULL;
476         mmc_slot(host).set_sleep = NULL;
477 }
478
479 static inline int omap_hsmmc_have_reg(void)
480 {
481         return 1;
482 }
483
484 #else
485
486 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
487 {
488         return -EINVAL;
489 }
490
491 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
492 {
493 }
494
495 static inline int omap_hsmmc_have_reg(void)
496 {
497         return 0;
498 }
499
500 #endif
501
502 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
503 {
504         int ret;
505
506         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
507                 if (pdata->slots[0].cover)
508                         pdata->slots[0].get_cover_state =
509                                         omap_hsmmc_get_cover_state;
510                 else
511                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
512                 pdata->slots[0].card_detect_irq =
513                                 gpio_to_irq(pdata->slots[0].switch_pin);
514                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
515                 if (ret)
516                         return ret;
517                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
518                 if (ret)
519                         goto err_free_sp;
520         } else
521                 pdata->slots[0].switch_pin = -EINVAL;
522
523         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
524                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
525                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
526                 if (ret)
527                         goto err_free_cd;
528                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
529                 if (ret)
530                         goto err_free_wp;
531         } else
532                 pdata->slots[0].gpio_wp = -EINVAL;
533
534         return 0;
535
536 err_free_wp:
537         gpio_free(pdata->slots[0].gpio_wp);
538 err_free_cd:
539         if (gpio_is_valid(pdata->slots[0].switch_pin))
540 err_free_sp:
541                 gpio_free(pdata->slots[0].switch_pin);
542         return ret;
543 }
544
545 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
546 {
547         if (gpio_is_valid(pdata->slots[0].gpio_wp))
548                 gpio_free(pdata->slots[0].gpio_wp);
549         if (gpio_is_valid(pdata->slots[0].switch_pin))
550                 gpio_free(pdata->slots[0].switch_pin);
551 }
552
553 /*
554  * Start clock to the card
555  */
556 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
557 {
558         OMAP_HSMMC_WRITE(host->base, SYSCTL,
559                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
560 }
561
562 /*
563  * Stop clock to the card
564  */
565 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
566 {
567         OMAP_HSMMC_WRITE(host->base, SYSCTL,
568                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
569         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
570                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
571 }
572
573 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
574                                   struct mmc_command *cmd)
575 {
576         unsigned int irq_mask;
577
578         if (host->use_dma)
579                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
580         else
581                 irq_mask = INT_EN_MASK;
582
583         /* Disable timeout for erases */
584         if (cmd->opcode == MMC_ERASE)
585                 irq_mask &= ~DTO_ENABLE;
586
587         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
588         OMAP_HSMMC_WRITE(host->base, ISE, host->use_dma ? irq_mask : 0);
589         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
590 }
591
592 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
593 {
594         OMAP_HSMMC_WRITE(host->base, ISE, 0);
595         OMAP_HSMMC_WRITE(host->base, IE, 0);
596         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
597 }
598
599 /* Calculate divisor for the given clock frequency */
600 static u16 calc_divisor(struct mmc_ios *ios)
601 {
602         u16 dsor = 0;
603
604         if (ios->clock) {
605                 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
606                 if (dsor > 250)
607                         dsor = 250;
608         }
609
610         return dsor;
611 }
612
613 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
614 {
615         struct mmc_ios *ios = &host->mmc->ios;
616         unsigned long regval;
617         unsigned long timeout;
618
619         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
620
621         omap_hsmmc_stop_clock(host);
622
623         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
624         regval = regval & ~(CLKD_MASK | DTO_MASK);
625         regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
626         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
627         OMAP_HSMMC_WRITE(host->base, SYSCTL,
628                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
629
630         /* Wait till the ICS bit is set */
631         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
632         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
633                 && time_before(jiffies, timeout))
634                 cpu_relax();
635
636         omap_hsmmc_start_clock(host);
637 }
638
639 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
640 {
641         struct mmc_ios *ios = &host->mmc->ios;
642         u32 con;
643
644         con = OMAP_HSMMC_READ(host->base, CON);
645         switch (ios->bus_width) {
646         case MMC_BUS_WIDTH_8:
647                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
648                 break;
649         case MMC_BUS_WIDTH_4:
650                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
651                 OMAP_HSMMC_WRITE(host->base, HCTL,
652                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
653                 break;
654         case MMC_BUS_WIDTH_1:
655                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
656                 OMAP_HSMMC_WRITE(host->base, HCTL,
657                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
658                 break;
659         }
660 }
661
662 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
663 {
664         struct mmc_ios *ios = &host->mmc->ios;
665         u32 con;
666
667         con = OMAP_HSMMC_READ(host->base, CON);
668         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
669                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
670         else
671                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
672 }
673
674 #ifdef CONFIG_PM
675
676 /*
677  * Restore the MMC host context, if it was lost as result of a
678  * power state change.
679  */
680 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
681 {
682         struct mmc_ios *ios = &host->mmc->ios;
683         struct omap_mmc_platform_data *pdata = host->pdata;
684         int context_loss = 0;
685         u32 hctl, capa;
686         unsigned long timeout;
687
688         if (pdata->get_context_loss_count) {
689                 context_loss = pdata->get_context_loss_count(host->dev);
690                 if (context_loss < 0)
691                         return 1;
692         }
693
694         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
695                 context_loss == host->context_loss ? "not " : "");
696         if (host->context_loss == context_loss)
697                 return 1;
698
699         /* Wait for hardware reset */
700         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
701         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
702                 && time_before(jiffies, timeout))
703                 ;
704
705         /* Do software reset */
706         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
707         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
708         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
709                 && time_before(jiffies, timeout))
710                 ;
711
712         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
713                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
714
715         if (host->id == OMAP_MMC1_DEVID) {
716                 if (host->power_mode != MMC_POWER_OFF &&
717                     (1 << ios->vdd) <= MMC_VDD_23_24)
718                         hctl = SDVS18;
719                 else
720                         hctl = SDVS30;
721                 capa = VS30 | VS18;
722         } else {
723                 hctl = SDVS18;
724                 capa = VS18;
725         }
726
727         OMAP_HSMMC_WRITE(host->base, HCTL,
728                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
729
730         OMAP_HSMMC_WRITE(host->base, CAPA,
731                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
732
733         OMAP_HSMMC_WRITE(host->base, HCTL,
734                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
735
736         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
737         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
738                 && time_before(jiffies, timeout))
739                 ;
740
741         omap_hsmmc_disable_irq(host);
742
743         /* Do not initialize card-specific things if the power is off */
744         if (host->power_mode == MMC_POWER_OFF)
745                 goto out;
746
747         omap_hsmmc_set_bus_width(host);
748
749         omap_hsmmc_set_clock(host);
750
751         omap_hsmmc_set_bus_mode(host);
752
753 out:
754         host->context_loss = context_loss;
755
756         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
757         return 0;
758 }
759
760 /*
761  * Save the MMC host context (store the number of power state changes so far).
762  */
763 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
764 {
765         struct omap_mmc_platform_data *pdata = host->pdata;
766         int context_loss;
767
768         if (pdata->get_context_loss_count) {
769                 context_loss = pdata->get_context_loss_count(host->dev);
770                 if (context_loss < 0)
771                         return;
772                 host->context_loss = context_loss;
773         }
774 }
775
776 #else
777
778 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
779 {
780         return 0;
781 }
782
783 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
784 {
785 }
786
787 #endif
788
789 /*
790  * Send init stream sequence to card
791  * before sending IDLE command
792  */
793 static void send_init_stream(struct omap_hsmmc_host *host)
794 {
795         int reg = 0;
796         unsigned long timeout;
797
798         if (host->protect_card)
799                 return;
800
801         disable_irq(host->irq);
802
803         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
804         OMAP_HSMMC_WRITE(host->base, CON,
805                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
806         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
807
808         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
809         while ((reg != CC) && time_before(jiffies, timeout))
810                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
811
812         OMAP_HSMMC_WRITE(host->base, CON,
813                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
814
815         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
816         OMAP_HSMMC_READ(host->base, STAT);
817
818         enable_irq(host->irq);
819 }
820
821 static inline
822 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
823 {
824         int r = 1;
825
826         if (mmc_slot(host).get_cover_state)
827                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
828         return r;
829 }
830
831 static ssize_t
832 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
833                            char *buf)
834 {
835         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
836         struct omap_hsmmc_host *host = mmc_priv(mmc);
837
838         return sprintf(buf, "%s\n",
839                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
840 }
841
842 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
843
844 static ssize_t
845 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
846                         char *buf)
847 {
848         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
849         struct omap_hsmmc_host *host = mmc_priv(mmc);
850
851         return sprintf(buf, "%s\n", mmc_slot(host).name);
852 }
853
854 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
855
856 /* for hosts with 35xx erratum 2.1.1.128 */
857 static ssize_t
858 omap_hsmmc_show_unsafe_read(struct device *dev, struct device_attribute *attr,
859                         char *buf)
860 {
861         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
862         int val = 0;
863
864         if (!(mmc->caps2 & MMC_CAP2_NO_MULTI_READ)) {
865                 val = 1;
866                 if (mmc->f_max == OMAP_MMC_MAX_CLOCK)
867                         val = 2;
868         }
869
870         return sprintf(buf, "%d\n", val);
871 }
872
873 static ssize_t
874 omap_hsmmc_set_unsafe_read(struct device *dev, struct device_attribute *attr,
875                 const char *buf, size_t count)
876 {
877         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
878         unsigned long val;
879         int ret;
880
881         ret = strict_strtoul(buf, 0, &val);
882         if (ret)
883                 return -EINVAL;
884
885         switch (val) {
886         case 0:
887                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
888                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
889                 break;
890         case 1:
891                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
892                 mmc->f_max = 32000000;
893                 break;
894         case 2:
895                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
896                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
897                 break;
898         }
899
900         return count;
901 }
902 static DEVICE_ATTR(unsafe_read, S_IWUSR | S_IRUGO,
903         omap_hsmmc_show_unsafe_read, omap_hsmmc_set_unsafe_read);
904
905 /*
906  * Configure the response type and send the cmd.
907  */
908 static void
909 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
910         struct mmc_data *data)
911 {
912         int cmdreg = 0, resptype = 0, cmdtype = 0;
913
914         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
915                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
916         host->cmd = cmd;
917
918         omap_hsmmc_enable_irq(host, cmd);
919
920         host->response_busy = 0;
921         if (cmd->flags & MMC_RSP_PRESENT) {
922                 if (cmd->flags & MMC_RSP_136)
923                         resptype = 1;
924                 else if (cmd->flags & MMC_RSP_BUSY) {
925                         resptype = 3;
926                         host->response_busy = 1;
927                 } else
928                         resptype = 2;
929         }
930
931         /*
932          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
933          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
934          * a val of 0x3, rest 0x0.
935          */
936         if (cmd == host->mrq->stop)
937                 cmdtype = 0x3;
938
939         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
940
941         if (data) {
942                 cmdreg |= DP_SELECT | MSBS | BCE;
943                 if (data->flags & MMC_DATA_READ)
944                         cmdreg |= DDIR;
945                 else
946                         cmdreg &= ~(DDIR);
947         }
948
949         if (host->use_dma)
950                 cmdreg |= DMA_EN;
951
952         host->req_in_progress = 1;
953
954         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
955         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
956 }
957
958 static int
959 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
960 {
961         if (data->flags & MMC_DATA_WRITE)
962                 return DMA_TO_DEVICE;
963         else
964                 return DMA_FROM_DEVICE;
965 }
966
967 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
968 {
969         int dma_ch;
970
971         spin_lock(&host->irq_lock);
972         host->req_in_progress = 0;
973         dma_ch = host->dma_ch;
974         spin_unlock(&host->irq_lock);
975
976         omap_hsmmc_disable_irq(host);
977         /* Do not complete the request if DMA is still in progress */
978         if (mrq->data && host->use_dma && dma_ch != -1)
979                 return;
980         host->mrq = NULL;
981         mmc_request_done(host->mmc, mrq);
982 }
983
984 /*
985  * Notify the transfer complete to MMC core
986  */
987 static void
988 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
989 {
990         if (!data) {
991                 struct mmc_request *mrq = host->mrq;
992
993                 /* TC before CC from CMD6 - don't know why, but it happens */
994                 if (host->cmd && host->cmd->opcode == 6 &&
995                     host->response_busy) {
996                         host->response_busy = 0;
997                         return;
998                 }
999
1000                 omap_hsmmc_request_done(host, mrq);
1001                 return;
1002         }
1003
1004         host->data = NULL;
1005
1006         if (!data->error)
1007                 data->bytes_xfered += data->blocks * (data->blksz);
1008         else
1009                 data->bytes_xfered = 0;
1010
1011         if (!data->stop) {
1012                 omap_hsmmc_request_done(host, data->mrq);
1013                 return;
1014         }
1015         omap_hsmmc_start_command(host, data->stop, NULL);
1016 }
1017
1018 /*
1019  * Notify the core about command completion
1020  */
1021 static void
1022 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
1023 {
1024         host->cmd = NULL;
1025
1026         if (cmd->flags & MMC_RSP_PRESENT) {
1027                 if (cmd->flags & MMC_RSP_136) {
1028                         /* response type 2 */
1029                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1030                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1031                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1032                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1033                 } else {
1034                         /* response types 1, 1b, 3, 4, 5, 6 */
1035                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1036                 }
1037         }
1038         if ((host->data == NULL && !host->response_busy) || cmd->error)
1039                 omap_hsmmc_request_done(host, cmd->mrq);
1040 }
1041
1042 /*
1043  * DMA clean up for command errors
1044  */
1045 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1046 {
1047         int dma_ch;
1048
1049         host->data->error = errno;
1050
1051         spin_lock(&host->irq_lock);
1052         dma_ch = host->dma_ch;
1053         host->dma_ch = -1;
1054         spin_unlock(&host->irq_lock);
1055
1056         if (host->use_dma && dma_ch != -1) {
1057                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1058                         host->data->sg_len,
1059                         omap_hsmmc_get_dma_dir(host, host->data));
1060                 host->data->host_cookie = 0;
1061         }
1062         host->data = NULL;
1063 }
1064
1065 /*
1066  * Readable error output
1067  */
1068 #ifdef CONFIG_MMC_DEBUG
1069 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1070 {
1071         /* --- means reserved bit without definition at documentation */
1072         static const char *omap_hsmmc_status_bits[] = {
1073                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1074                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1075                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1076                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1077         };
1078         char res[256];
1079         char *buf = res;
1080         int len, i;
1081
1082         len = sprintf(buf, "MMC IRQ 0x%x :", status);
1083         buf += len;
1084
1085         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1086                 if (status & (1 << i)) {
1087                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1088                         buf += len;
1089                 }
1090
1091         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1092 }
1093 #else
1094 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1095                                              u32 status)
1096 {
1097 }
1098 #endif  /* CONFIG_MMC_DEBUG */
1099
1100 /*
1101  * MMC controller internal state machines reset
1102  *
1103  * Used to reset command or data internal state machines, using respectively
1104  *  SRC or SRD bit of SYSCTL register
1105  * Can be called from interrupt context
1106  */
1107 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1108                                                    unsigned long bit)
1109 {
1110         unsigned long i = 0;
1111         unsigned long limit = (loops_per_jiffy *
1112                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
1113
1114         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1115                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1116
1117         /*
1118          * OMAP4 ES2 and greater has an updated reset logic.
1119          * Monitor a 0->1 transition first
1120          */
1121         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1122                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1123                                         && (i++ < limit))
1124                         cpu_relax();
1125         }
1126         i = 0;
1127
1128         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1129                 (i++ < limit))
1130                 cpu_relax();
1131
1132         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1133                 dev_err(mmc_dev(host->mmc),
1134                         "Timeout waiting on controller reset in %s\n",
1135                         __func__);
1136 }
1137
1138 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1139 {
1140         struct mmc_data *data;
1141         int end_cmd = 0, end_trans = 0;
1142
1143         if (unlikely(!host->req_in_progress)) {
1144                 OMAP_HSMMC_WRITE(host->base, STAT, status);
1145                 return;
1146         }
1147
1148         data = host->data;
1149         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1150
1151         if (unlikely(status & ERR)) {
1152                 omap_hsmmc_dbg_report_irq(host, status);
1153                 if ((status & CMD_TIMEOUT) ||
1154                         (status & CMD_CRC)) {
1155                         if (host->cmd) {
1156                                 if (status & CMD_TIMEOUT) {
1157                                         omap_hsmmc_reset_controller_fsm(host,
1158                                                                         SRC);
1159                                         host->cmd->error = -ETIMEDOUT;
1160                                 } else {
1161                                         host->cmd->error = -EILSEQ;
1162                                 }
1163                                 end_cmd = 1;
1164                         }
1165                         if (host->data || host->response_busy) {
1166                                 if (host->data)
1167                                         omap_hsmmc_dma_cleanup(host,
1168                                                                 -ETIMEDOUT);
1169                                 host->response_busy = 0;
1170                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1171                         }
1172                 }
1173                 if ((status & DATA_TIMEOUT) ||
1174                         (status & DATA_CRC)) {
1175                         if (host->data || host->response_busy) {
1176                                 int err = (status & DATA_TIMEOUT) ?
1177                                                 -ETIMEDOUT : -EILSEQ;
1178
1179                                 if (host->data)
1180                                         omap_hsmmc_dma_cleanup(host, err);
1181                                 else
1182                                         host->mrq->cmd->error = err;
1183                                 host->response_busy = 0;
1184                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1185                                 end_trans = 1;
1186                         }
1187                 }
1188                 if (status & CARD_ERR) {
1189                         dev_dbg(mmc_dev(host->mmc),
1190                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1191                         if (host->cmd)
1192                                 end_cmd = 1;
1193                         if (host->data)
1194                                 end_trans = 1;
1195                 }
1196         }
1197
1198         OMAP_HSMMC_WRITE(host->base, STAT, status);
1199
1200         if (end_cmd || ((status & CC) && host->cmd))
1201                 omap_hsmmc_cmd_done(host, host->cmd);
1202         if ((end_trans || (status & TC)) && host->mrq)
1203                 omap_hsmmc_xfer_done(host, data);
1204 }
1205
1206 /*
1207  * MMC controller IRQ handler
1208  */
1209 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1210 {
1211         struct omap_hsmmc_host *host = dev_id;
1212         int status;
1213
1214         status = OMAP_HSMMC_READ(host->base, STAT);
1215         do {
1216                 omap_hsmmc_do_irq(host, status);
1217                 /* Flush posted write */
1218                 status = OMAP_HSMMC_READ(host->base, STAT);
1219         } while (status & INT_EN_MASK);
1220
1221         return IRQ_HANDLED;
1222 }
1223
1224 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1225 {
1226         unsigned long i;
1227
1228         OMAP_HSMMC_WRITE(host->base, HCTL,
1229                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1230         for (i = 0; i < loops_per_jiffy; i++) {
1231                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1232                         break;
1233                 cpu_relax();
1234         }
1235 }
1236
1237 /*
1238  * Switch MMC interface voltage ... only relevant for MMC1.
1239  *
1240  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1241  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1242  * Some chips, like eMMC ones, use internal transceivers.
1243  */
1244 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1245 {
1246         u32 reg_val = 0;
1247         int ret;
1248
1249         /* Disable the clocks */
1250         pm_runtime_put_sync(host->dev);
1251         if (host->got_dbclk)
1252                 clk_disable(host->dbclk);
1253
1254         /* Turn the power off */
1255         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1256
1257         /* Turn the power ON with given VDD 1.8 or 3.0v */
1258         if (!ret)
1259                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1260                                                vdd);
1261         pm_runtime_get_sync(host->dev);
1262         if (host->got_dbclk)
1263                 clk_enable(host->dbclk);
1264
1265         if (ret != 0)
1266                 goto err;
1267
1268         OMAP_HSMMC_WRITE(host->base, HCTL,
1269                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1270         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1271
1272         /*
1273          * If a MMC dual voltage card is detected, the set_ios fn calls
1274          * this fn with VDD bit set for 1.8V. Upon card removal from the
1275          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1276          *
1277          * Cope with a bit of slop in the range ... per data sheets:
1278          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1279          *    but recommended values are 1.71V to 1.89V
1280          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1281          *    but recommended values are 2.7V to 3.3V
1282          *
1283          * Board setup code shouldn't permit anything very out-of-range.
1284          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1285          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1286          */
1287         if ((1 << vdd) <= MMC_VDD_23_24)
1288                 reg_val |= SDVS18;
1289         else
1290                 reg_val |= SDVS30;
1291
1292         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1293         set_sd_bus_power(host);
1294
1295         return 0;
1296 err:
1297         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1298         return ret;
1299 }
1300
1301 /* Protect the card while the cover is open */
1302 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1303 {
1304         if (!mmc_slot(host).get_cover_state)
1305                 return;
1306
1307         host->reqs_blocked = 0;
1308         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1309                 if (host->protect_card) {
1310                         pr_info("%s: cover is closed, "
1311                                          "card is now accessible\n",
1312                                          mmc_hostname(host->mmc));
1313                         host->protect_card = 0;
1314                 }
1315         } else {
1316                 if (!host->protect_card) {
1317                         pr_info("%s: cover is open, "
1318                                          "card is now inaccessible\n",
1319                                          mmc_hostname(host->mmc));
1320                         host->protect_card = 1;
1321                 }
1322         }
1323 }
1324
1325 /*
1326  * irq handler to notify the core about card insertion/removal
1327  */
1328 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1329 {
1330         struct omap_hsmmc_host *host = dev_id;
1331         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1332         int carddetect;
1333
1334         if (host->suspended)
1335                 return IRQ_HANDLED;
1336
1337         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1338
1339         if (slot->card_detect)
1340                 carddetect = slot->card_detect(host->dev, host->slot_id);
1341         else {
1342                 omap_hsmmc_protect_card(host);
1343                 carddetect = -ENOSYS;
1344         }
1345
1346         if (carddetect)
1347                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1348         else
1349                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1350         return IRQ_HANDLED;
1351 }
1352
1353 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1354                                      struct mmc_data *data)
1355 {
1356         int sync_dev;
1357
1358         if (data->flags & MMC_DATA_WRITE)
1359                 sync_dev = host->dma_line_tx;
1360         else
1361                 sync_dev = host->dma_line_rx;
1362         return sync_dev;
1363 }
1364
1365 static void omap_hsmmc_config_dma_params_once(struct omap_hsmmc_host *host,
1366                                               struct mmc_data *data,
1367                                               int dma_ch)
1368 {
1369         if (data->flags & MMC_DATA_WRITE) {
1370                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1371                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1372                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_16);
1373                 omap_set_dma_src_data_pack(dma_ch, 1);
1374         } else {
1375                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1376                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1377                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_16);
1378                 omap_set_dma_dest_data_pack(dma_ch, 1);
1379                 omap_set_dma_write_mode(dma_ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
1380         }
1381 }
1382
1383 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1384                                        struct mmc_data *data,
1385                                        struct scatterlist *sgl)
1386 {
1387         int blksz, nblk, dma_ch, sync;
1388
1389         dma_ch = host->dma_ch;
1390         if (data->flags & MMC_DATA_WRITE) {
1391                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1392                         sg_dma_address(sgl), 0, 0);
1393                 sync = OMAP_DMA_DST_SYNC_PREFETCH;
1394         } else {
1395                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1396                         sg_dma_address(sgl), 0, 0);
1397                 sync = OMAP_DMA_SRC_SYNC;
1398         }
1399
1400         blksz = host->data->blksz;
1401         nblk = sg_dma_len(sgl) / blksz;
1402
1403         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1404                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1405                         omap_hsmmc_get_dma_sync_dev(host, data), sync);
1406
1407         omap_start_dma(dma_ch);
1408 }
1409
1410 /*
1411  * DMA call back function
1412  */
1413 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1414 {
1415         struct omap_hsmmc_host *host = cb_data;
1416         struct mmc_data *data;
1417         int req_in_progress;
1418
1419         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1420                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1421                         ch_status);
1422                 return;
1423         }
1424
1425         spin_lock(&host->irq_lock);
1426         if (host->dma_ch < 0) {
1427                 spin_unlock(&host->irq_lock);
1428                 return;
1429         }
1430
1431         data = host->mrq->data;
1432         host->dma_sg_idx++;
1433         if (host->dma_sg_idx < host->dma_len) {
1434                 /* Fire up the next transfer. */
1435                 omap_hsmmc_config_dma_params(host, data,
1436                                            data->sg + host->dma_sg_idx);
1437                 spin_unlock(&host->irq_lock);
1438                 return;
1439         }
1440
1441         if (!data->host_cookie)
1442                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1443                              omap_hsmmc_get_dma_dir(host, data));
1444
1445         req_in_progress = host->req_in_progress;
1446         host->dma_ch = -1;
1447         spin_unlock(&host->irq_lock);
1448
1449         /* If DMA has finished after TC, complete the request */
1450         if (!req_in_progress) {
1451                 struct mmc_request *mrq = host->mrq;
1452
1453                 host->mrq = NULL;
1454                 mmc_request_done(host->mmc, mrq);
1455         }
1456 }
1457
1458 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1459                                        struct mmc_data *data,
1460                                        struct omap_hsmmc_next *next)
1461 {
1462         int dma_len;
1463
1464         if (unlikely(!next && data->host_cookie &&
1465             data->host_cookie != host->next_data.cookie)) {
1466                 pr_warning("[%s] invalid cookie: data->host_cookie %d"
1467                        " host->next_data.cookie %d\n",
1468                        __func__, data->host_cookie, host->next_data.cookie);
1469                 data->host_cookie = 0;
1470         }
1471
1472         /* Check if next job is already prepared */
1473         if (next ||
1474             (!next && data->host_cookie != host->next_data.cookie)) {
1475                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1476                                      data->sg_len,
1477                                      omap_hsmmc_get_dma_dir(host, data));
1478
1479         } else {
1480                 dma_len = host->next_data.dma_len;
1481                 host->next_data.dma_len = 0;
1482         }
1483
1484
1485         if (unlikely(dma_len == 0))
1486                 return -EINVAL;
1487
1488         if (next) {
1489                 next->dma_len = dma_len;
1490                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1491         } else
1492                 host->dma_len = dma_len;
1493
1494         return 0;
1495 }
1496
1497 /*
1498  * Routine to configure and start DMA for the MMC card
1499  */
1500 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1501                                         struct mmc_request *req)
1502 {
1503         int dma_ch = 0, ret = 0, i;
1504         struct mmc_data *data = req->data;
1505
1506         /* Sanity check: all the SG entries must be aligned by block size. */
1507         for (i = 0; i < data->sg_len; i++) {
1508                 struct scatterlist *sgl;
1509
1510                 sgl = data->sg + i;
1511                 if (unlikely(sgl->length % data->blksz))
1512                         return -EINVAL;
1513         }
1514         if (unlikely((data->blksz % 4) != 0))
1515                 /* REVISIT: The MMC buffer increments only when MSB is written.
1516                  * Return error for blksz which is non multiple of four.
1517                  */
1518                 return -EINVAL;
1519
1520         BUG_ON(host->dma_ch != -1);
1521
1522         if (data->flags & MMC_DATA_WRITE)
1523                 dma_ch = host->dma_ch_tx;
1524         else
1525                 dma_ch = host->dma_ch_rx;
1526
1527         if (dma_ch == -1) {
1528                 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1529                                        "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1530                 if (unlikely(ret != 0)) {
1531                         dev_err(mmc_dev(host->mmc),
1532                                 "%s: omap_request_dma() failed with %d\n",
1533                                 mmc_hostname(host->mmc), ret);
1534                         return ret;
1535                 }
1536
1537                 omap_hsmmc_config_dma_params_once(host, data, dma_ch);
1538
1539                 if (data->flags & MMC_DATA_WRITE)
1540                         host->dma_ch_tx = dma_ch;
1541                 else
1542                         host->dma_ch_rx = dma_ch;
1543         }
1544
1545         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1546         if (unlikely(ret))
1547                 return ret;
1548
1549         host->dma_ch = dma_ch;
1550         host->dma_sg_idx = 0;
1551
1552         omap_hsmmc_config_dma_params(host, data, data->sg);
1553
1554         return 0;
1555 }
1556
1557 /* pandora wifi small transfer hack */
1558 static int check_mmc3_dma_hack(struct omap_hsmmc_host *host,
1559                                struct mmc_request *req)
1560 {
1561         if (req->data != NULL && req->data->sg_len == 1
1562             && req->data->sg->length <= 16)
1563                 return 0;
1564         else
1565                 return 1;
1566 }
1567
1568 /*
1569  * Configure block length for MMC/SD cards and initiate the transfer.
1570  */
1571 static int
1572 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1573 {
1574         int ret;
1575         host->data = req->data;
1576
1577         if (req->data == NULL) {
1578                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1579                 return 0;
1580         }
1581
1582         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1583                                         | (req->data->blocks << 16));
1584
1585         if (host->use_dma) {
1586                 ret = omap_hsmmc_start_dma_transfer(host, req);
1587                 if (ret != 0) {
1588                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1589                         return ret;
1590                 }
1591         }
1592         return 0;
1593 }
1594
1595 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1596                                 int err)
1597 {
1598         struct omap_hsmmc_host *host = mmc_priv(mmc);
1599         struct mmc_data *data = mrq->data;
1600
1601         if (host->use_dma) {
1602                 if (data->host_cookie)
1603                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1604                                      data->sg_len,
1605                                      omap_hsmmc_get_dma_dir(host, data));
1606                 data->host_cookie = 0;
1607         }
1608 }
1609
1610 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1611                                bool is_first_req)
1612 {
1613         struct omap_hsmmc_host *host = mmc_priv(mmc);
1614         int use_dma = host->use_dma;
1615
1616         if (mrq->data->host_cookie) {
1617                 mrq->data->host_cookie = 0;
1618                 return ;
1619         }
1620
1621         if (host->id == OMAP_MMC3_DEVID)
1622                 use_dma = check_mmc3_dma_hack(host, mrq);
1623         if (use_dma)
1624                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1625                                                 &host->next_data))
1626                         mrq->data->host_cookie = 0;
1627 }
1628
1629 #define BWR (1 << 4)
1630 #define BRR (1 << 5)
1631
1632 static noinline void omap_hsmmc_request_do_pio(struct mmc_host *mmc,
1633         struct mmc_request *req)
1634 {
1635         struct omap_hsmmc_host *host = mmc_priv(mmc);
1636         u32 *data = sg_virt(req->data->sg);
1637         u32 len = req->data->sg->length;
1638         int stat;
1639         int i;
1640
1641         for (i = 0; i < 10000000; i++) {
1642                 stat = OMAP_HSMMC_READ(host->base, STAT);
1643                 if (stat == 0)
1644                         continue;
1645
1646                 //dev_err(mmc_dev(host->mmc), "stat %x, l %d\n", stat, i);
1647
1648                 if (stat & (DATA_TIMEOUT | DATA_CRC))
1649                         omap_hsmmc_reset_controller_fsm(host, SRD);
1650
1651                 if (stat & ERR) {
1652                         req->cmd->error =
1653                         req->data->error = -EINVAL; // ?
1654                         omap_hsmmc_xfer_done(host, host->data);
1655                         return;
1656                 }
1657         
1658                 if (req->data->flags & MMC_DATA_WRITE) {
1659                         while (len > 0 && (stat & BWR)) {
1660                                 OMAP_HSMMC_WRITE(host->base, DATA, *data++);
1661                                 len -= 4;
1662                         }
1663                 } else {
1664                         while (len > 0 && (stat & BRR)) {
1665                                 *data++ = OMAP_HSMMC_READ(host->base, DATA);
1666                                 len -= 4;
1667                         }
1668                 }
1669
1670                 if ((stat & CC) && host->cmd)
1671                         omap_hsmmc_cmd_done(host, host->cmd);
1672                 if ((stat & TC) && host->mrq) {
1673                         omap_hsmmc_xfer_done(host, host->data);
1674                         break;
1675                 }
1676         }
1677
1678         if (len > 0) {
1679                 req->cmd->error =
1680                 req->data->error = -ETIMEDOUT;
1681                 omap_hsmmc_xfer_done(host, req->data);
1682         }
1683 }
1684
1685 /*
1686  * Request function. for read/write operation
1687  */
1688 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1689 {
1690         struct omap_hsmmc_host *host = mmc_priv(mmc);
1691         int err;
1692
1693         BUG_ON(host->req_in_progress);
1694         BUG_ON(host->dma_ch != -1);
1695         if (unlikely(host->protect_card)) {
1696                 if (host->reqs_blocked < 3) {
1697                         /*
1698                          * Ensure the controller is left in a consistent
1699                          * state by resetting the command and data state
1700                          * machines.
1701                          */
1702                         omap_hsmmc_reset_controller_fsm(host, SRD);
1703                         omap_hsmmc_reset_controller_fsm(host, SRC);
1704                         host->reqs_blocked += 1;
1705                 }
1706                 req->cmd->error = -EBADF;
1707                 if (req->data)
1708                         req->data->error = -EBADF;
1709                 req->cmd->retries = 0;
1710                 mmc_request_done(mmc, req);
1711                 return;
1712         } else if (host->reqs_blocked)
1713                 host->reqs_blocked = 0;
1714
1715         /* pandora wifi hack... */
1716         if (host->id == OMAP_MMC3_DEVID)
1717                 host->use_dma = check_mmc3_dma_hack(host, req);
1718
1719         WARN_ON(host->mrq != NULL);
1720         host->mrq = req;
1721         err = omap_hsmmc_prepare_data(host, req);
1722         if (unlikely(err)) {
1723                 req->cmd->error = err;
1724                 if (req->data)
1725                         req->data->error = err;
1726                 host->mrq = NULL;
1727                 mmc_request_done(mmc, req);
1728                 return;
1729         }
1730
1731         omap_hsmmc_start_command(host, req->cmd, req->data);
1732
1733         if (host->use_dma == 0)
1734                 omap_hsmmc_request_do_pio(mmc, req);
1735 }
1736
1737 /* Routine to configure clock values. Exposed API to core */
1738 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1739 {
1740         struct omap_hsmmc_host *host = mmc_priv(mmc);
1741         int do_send_init_stream = 0;
1742
1743         pm_runtime_get_sync(host->dev);
1744
1745         if (ios->power_mode != host->power_mode) {
1746                 switch (ios->power_mode) {
1747                 case MMC_POWER_OFF:
1748                         mmc_slot(host).set_power(host->dev, host->slot_id,
1749                                                  0, 0);
1750                         host->vdd = 0;
1751                         break;
1752                 case MMC_POWER_UP:
1753                         mmc_slot(host).set_power(host->dev, host->slot_id,
1754                                                  1, ios->vdd);
1755                         host->vdd = ios->vdd;
1756                         break;
1757                 case MMC_POWER_ON:
1758                         do_send_init_stream = 1;
1759                         break;
1760                 }
1761                 host->power_mode = ios->power_mode;
1762         }
1763
1764         /* FIXME: set registers based only on changes to ios */
1765
1766         omap_hsmmc_set_bus_width(host);
1767
1768         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1769                 /* Only MMC1 can interface at 3V without some flavor
1770                  * of external transceiver; but they all handle 1.8V.
1771                  */
1772                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1773                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1774                                 /*
1775                                  * The mmc_select_voltage fn of the core does
1776                                  * not seem to set the power_mode to
1777                                  * MMC_POWER_UP upon recalculating the voltage.
1778                                  * vdd 1.8v.
1779                                  */
1780                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1781                                 dev_dbg(mmc_dev(host->mmc),
1782                                                 "Switch operation failed\n");
1783                 }
1784         }
1785
1786         omap_hsmmc_set_clock(host);
1787
1788         if (do_send_init_stream)
1789                 send_init_stream(host);
1790
1791         omap_hsmmc_set_bus_mode(host);
1792
1793         pm_runtime_put_autosuspend(host->dev);
1794 }
1795
1796 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1797 {
1798         struct omap_hsmmc_host *host = mmc_priv(mmc);
1799
1800         if (!mmc_slot(host).card_detect)
1801                 return -ENOSYS;
1802         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1803 }
1804
1805 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1806 {
1807         struct omap_hsmmc_host *host = mmc_priv(mmc);
1808
1809         if (!mmc_slot(host).get_ro)
1810                 return -ENOSYS;
1811         return mmc_slot(host).get_ro(host->dev, 0);
1812 }
1813
1814 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1815 {
1816         struct omap_hsmmc_host *host = mmc_priv(mmc);
1817
1818         if (mmc_slot(host).init_card)
1819                 mmc_slot(host).init_card(card);
1820 }
1821
1822 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1823 {
1824         u32 hctl, capa, value;
1825
1826         /* Only MMC1 supports 3.0V */
1827         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1828                 hctl = SDVS30;
1829                 capa = VS30 | VS18;
1830         } else {
1831                 hctl = SDVS18;
1832                 capa = VS18;
1833         }
1834
1835         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1836         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1837
1838         value = OMAP_HSMMC_READ(host->base, CAPA);
1839         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1840
1841         /* Set the controller to AUTO IDLE mode */
1842         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1843         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1844
1845         /* Set SD bus power bit */
1846         set_sd_bus_power(host);
1847 }
1848
1849 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1850 {
1851         struct omap_hsmmc_host *host = mmc_priv(mmc);
1852
1853         pm_runtime_get_sync(host->dev);
1854
1855         return 0;
1856 }
1857
1858 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1859 {
1860         struct omap_hsmmc_host *host = mmc_priv(mmc);
1861
1862         pm_runtime_mark_last_busy(host->dev);
1863         pm_runtime_put_autosuspend(host->dev);
1864
1865         return 0;
1866 }
1867
1868 static const struct mmc_host_ops omap_hsmmc_ops = {
1869         .enable = omap_hsmmc_enable_fclk,
1870         .disable = omap_hsmmc_disable_fclk,
1871         .post_req = omap_hsmmc_post_req,
1872         .pre_req = omap_hsmmc_pre_req,
1873         .request = omap_hsmmc_request,
1874         .set_ios = omap_hsmmc_set_ios,
1875         .get_cd = omap_hsmmc_get_cd,
1876         .get_ro = omap_hsmmc_get_ro,
1877         .init_card = omap_hsmmc_init_card,
1878         /* NYET -- enable_sdio_irq */
1879 };
1880
1881 #ifdef CONFIG_DEBUG_FS
1882
1883 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1884 {
1885         struct mmc_host *mmc = s->private;
1886         struct omap_hsmmc_host *host = mmc_priv(mmc);
1887         int context_loss = 0;
1888
1889         if (host->pdata->get_context_loss_count)
1890                 context_loss = host->pdata->get_context_loss_count(host->dev);
1891
1892         seq_printf(s, "mmc%d:\n"
1893                         " enabled:\t%d\n"
1894                         " dpm_state:\t%d\n"
1895                         " nesting_cnt:\t%d\n"
1896                         " ctx_loss:\t%d:%d\n"
1897                         "\nregs:\n",
1898                         mmc->index, mmc->enabled ? 1 : 0,
1899                         host->dpm_state, mmc->nesting_cnt,
1900                         host->context_loss, context_loss);
1901
1902         if (host->suspended) {
1903                 seq_printf(s, "host suspended, can't read registers\n");
1904                 return 0;
1905         }
1906
1907         pm_runtime_get_sync(host->dev);
1908
1909         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1910                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1911         seq_printf(s, "CON:\t\t0x%08x\n",
1912                         OMAP_HSMMC_READ(host->base, CON));
1913         seq_printf(s, "HCTL:\t\t0x%08x\n",
1914                         OMAP_HSMMC_READ(host->base, HCTL));
1915         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1916                         OMAP_HSMMC_READ(host->base, SYSCTL));
1917         seq_printf(s, "IE:\t\t0x%08x\n",
1918                         OMAP_HSMMC_READ(host->base, IE));
1919         seq_printf(s, "ISE:\t\t0x%08x\n",
1920                         OMAP_HSMMC_READ(host->base, ISE));
1921         seq_printf(s, "CAPA:\t\t0x%08x\n",
1922                         OMAP_HSMMC_READ(host->base, CAPA));
1923
1924         pm_runtime_mark_last_busy(host->dev);
1925         pm_runtime_put_autosuspend(host->dev);
1926
1927         return 0;
1928 }
1929
1930 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1931 {
1932         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1933 }
1934
1935 static const struct file_operations mmc_regs_fops = {
1936         .open           = omap_hsmmc_regs_open,
1937         .read           = seq_read,
1938         .llseek         = seq_lseek,
1939         .release        = single_release,
1940 };
1941
1942 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1943 {
1944         if (mmc->debugfs_root)
1945                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1946                         mmc, &mmc_regs_fops);
1947 }
1948
1949 #else
1950
1951 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1952 {
1953 }
1954
1955 #endif
1956
1957 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1958 {
1959         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1960         struct mmc_host *mmc;
1961         struct omap_hsmmc_host *host = NULL;
1962         struct resource *res;
1963         int ret, irq;
1964
1965         if (pdata == NULL) {
1966                 dev_err(&pdev->dev, "Platform Data is missing\n");
1967                 return -ENXIO;
1968         }
1969
1970         if (pdata->nr_slots == 0) {
1971                 dev_err(&pdev->dev, "No Slots\n");
1972                 return -ENXIO;
1973         }
1974
1975         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1976         irq = platform_get_irq(pdev, 0);
1977         if (res == NULL || irq < 0)
1978                 return -ENXIO;
1979
1980         res->start += pdata->reg_offset;
1981         res->end += pdata->reg_offset;
1982         res = request_mem_region(res->start, resource_size(res), pdev->name);
1983         if (res == NULL)
1984                 return -EBUSY;
1985
1986         ret = omap_hsmmc_gpio_init(pdata);
1987         if (ret)
1988                 goto err;
1989
1990         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1991         if (!mmc) {
1992                 ret = -ENOMEM;
1993                 goto err_alloc;
1994         }
1995
1996         host            = mmc_priv(mmc);
1997         host->mmc       = mmc;
1998         host->pdata     = pdata;
1999         host->dev       = &pdev->dev;
2000         host->use_dma   = 1;
2001         host->dev->dma_mask = &pdata->dma_mask;
2002         host->dma_ch    = -1;
2003         host->dma_ch_tx = -1;
2004         host->dma_ch_rx = -1;
2005         host->irq       = irq;
2006         host->id        = pdev->id;
2007         host->slot_id   = 0;
2008         host->mapbase   = res->start;
2009         host->base      = ioremap(host->mapbase, SZ_4K);
2010         host->power_mode = MMC_POWER_OFF;
2011         host->next_data.cookie = 1;
2012
2013         platform_set_drvdata(pdev, host);
2014
2015         mmc->ops        = &omap_hsmmc_ops;
2016
2017         /*
2018          * If regulator_disable can only put vcc_aux to sleep then there is
2019          * no off state.
2020          */
2021         if (mmc_slot(host).vcc_aux_disable_is_sleep)
2022                 mmc_slot(host).no_off = 1;
2023
2024         mmc->f_min      = OMAP_MMC_MIN_CLOCK;
2025         mmc->f_max      = OMAP_MMC_MAX_CLOCK;
2026
2027         spin_lock_init(&host->irq_lock);
2028
2029         host->fclk = clk_get(&pdev->dev, "fck");
2030         if (IS_ERR(host->fclk)) {
2031                 ret = PTR_ERR(host->fclk);
2032                 host->fclk = NULL;
2033                 goto err1;
2034         }
2035
2036         omap_hsmmc_context_save(host);
2037
2038         mmc->caps |= MMC_CAP_DISABLE;
2039
2040         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2041                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2042                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
2043         }
2044
2045         pm_runtime_enable(host->dev);
2046         pm_runtime_get_sync(host->dev);
2047         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2048         pm_runtime_use_autosuspend(host->dev);
2049
2050         if (cpu_is_omap2430()) {
2051                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2052                 /*
2053                  * MMC can still work without debounce clock.
2054                  */
2055                 if (IS_ERR(host->dbclk))
2056                         dev_warn(mmc_dev(host->mmc),
2057                                 "Failed to get debounce clock\n");
2058                 else
2059                         host->got_dbclk = 1;
2060
2061                 if (host->got_dbclk)
2062                         if (clk_enable(host->dbclk) != 0)
2063                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2064                                                         " clk failed\n");
2065         }
2066
2067         /* Since we do only SG emulation, we can have as many segs
2068          * as we want. */
2069         mmc->max_segs = 1024;
2070
2071         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2072         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2073         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2074         mmc->max_seg_size = mmc->max_req_size;
2075
2076         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2077                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2078
2079         mmc->caps |= mmc_slot(host).caps;
2080         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2081                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2082
2083         if (mmc_slot(host).nonremovable)
2084                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2085
2086         omap_hsmmc_conf_bus_power(host);
2087
2088         /* Select DMA lines */
2089         switch (host->id) {
2090         case OMAP_MMC1_DEVID:
2091                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2092                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2093                 break;
2094         case OMAP_MMC2_DEVID:
2095                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2096                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2097                 break;
2098         case OMAP_MMC3_DEVID:
2099                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2100                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2101                 break;
2102         case OMAP_MMC4_DEVID:
2103                 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2104                 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2105                 break;
2106         case OMAP_MMC5_DEVID:
2107                 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2108                 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2109                 break;
2110         default:
2111                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2112                 goto err_irq;
2113         }
2114
2115         /* Request IRQ for MMC operations */
2116         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
2117                         mmc_hostname(mmc), host);
2118         if (ret) {
2119                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2120                 goto err_irq;
2121         }
2122
2123         if (pdata->init != NULL) {
2124                 if (pdata->init(&pdev->dev) != 0) {
2125                         dev_dbg(mmc_dev(host->mmc),
2126                                 "Unable to configure MMC IRQs\n");
2127                         goto err_irq_cd_init;
2128                 }
2129         }
2130
2131         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2132                 ret = omap_hsmmc_reg_get(host);
2133                 if (ret)
2134                         goto err_reg;
2135                 host->use_reg = 1;
2136         }
2137
2138         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2139
2140         /* Request IRQ for card detect */
2141         if ((mmc_slot(host).card_detect_irq)) {
2142                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
2143                                            NULL,
2144                                            omap_hsmmc_detect,
2145                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2146                                            mmc_hostname(mmc), host);
2147                 if (ret) {
2148                         dev_dbg(mmc_dev(host->mmc),
2149                                 "Unable to grab MMC CD IRQ\n");
2150                         goto err_irq_cd;
2151                 }
2152                 pdata->suspend = omap_hsmmc_suspend_cdirq;
2153                 pdata->resume = omap_hsmmc_resume_cdirq;
2154         }
2155
2156         omap_hsmmc_disable_irq(host);
2157
2158         omap_hsmmc_protect_card(host);
2159
2160         mmc_add_host(mmc);
2161
2162         if (mmc_slot(host).name != NULL) {
2163                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2164                 if (ret < 0)
2165                         goto err_slot_name;
2166         }
2167         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2168                 ret = device_create_file(&mmc->class_dev,
2169                                         &dev_attr_cover_switch);
2170                 if (ret < 0)
2171                         goto err_slot_name;
2172         }
2173
2174         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2175                 ret = device_create_file(&mmc->class_dev, &dev_attr_unsafe_read);
2176
2177                 /* MMC_CAP2_NO_MULTI_READ makes it crawl, try a different workaround */
2178                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
2179                 mmc->max_segs = 1;
2180                 mmc->f_max = 32000000;
2181         }
2182
2183         omap_hsmmc_debugfs(mmc);
2184         pm_runtime_mark_last_busy(host->dev);
2185         pm_runtime_put_autosuspend(host->dev);
2186
2187         return 0;
2188
2189 err_slot_name:
2190         mmc_remove_host(mmc);
2191         free_irq(mmc_slot(host).card_detect_irq, host);
2192 err_irq_cd:
2193         if (host->use_reg)
2194                 omap_hsmmc_reg_put(host);
2195 err_reg:
2196         if (host->pdata->cleanup)
2197                 host->pdata->cleanup(&pdev->dev);
2198 err_irq_cd_init:
2199         free_irq(host->irq, host);
2200 err_irq:
2201         pm_runtime_mark_last_busy(host->dev);
2202         pm_runtime_put_autosuspend(host->dev);
2203         clk_put(host->fclk);
2204         if (host->got_dbclk) {
2205                 clk_disable(host->dbclk);
2206                 clk_put(host->dbclk);
2207         }
2208 err1:
2209         iounmap(host->base);
2210         platform_set_drvdata(pdev, NULL);
2211         mmc_free_host(mmc);
2212 err_alloc:
2213         omap_hsmmc_gpio_free(pdata);
2214 err:
2215         release_mem_region(res->start, resource_size(res));
2216         return ret;
2217 }
2218
2219 static int omap_hsmmc_remove(struct platform_device *pdev)
2220 {
2221         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2222         struct resource *res;
2223
2224         if (host) {
2225                 pm_runtime_get_sync(host->dev);
2226                 mmc_remove_host(host->mmc);
2227                 if (host->use_reg)
2228                         omap_hsmmc_reg_put(host);
2229                 if (host->pdata->cleanup)
2230                         host->pdata->cleanup(&pdev->dev);
2231                 free_irq(host->irq, host);
2232                 if (mmc_slot(host).card_detect_irq)
2233                         free_irq(mmc_slot(host).card_detect_irq, host);
2234
2235                 pm_runtime_put_sync(host->dev);
2236                 pm_runtime_disable(host->dev);
2237                 clk_put(host->fclk);
2238                 if (host->got_dbclk) {
2239                         clk_disable(host->dbclk);
2240                         clk_put(host->dbclk);
2241                 }
2242
2243                 mmc_free_host(host->mmc);
2244                 iounmap(host->base);
2245                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2246         }
2247
2248         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2249         if (res)
2250                 release_mem_region(res->start, resource_size(res));
2251         platform_set_drvdata(pdev, NULL);
2252
2253         return 0;
2254 }
2255
2256 #ifdef CONFIG_PM
2257 static int omap_hsmmc_suspend(struct device *dev)
2258 {
2259         int ret = 0;
2260         struct platform_device *pdev = to_platform_device(dev);
2261         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2262
2263         if (host && host->suspended)
2264                 return 0;
2265
2266         if (host) {
2267                 pm_runtime_get_sync(host->dev);
2268                 host->suspended = 1;
2269                 if (host->pdata->suspend) {
2270                         ret = host->pdata->suspend(&pdev->dev,
2271                                                         host->slot_id);
2272                         if (ret) {
2273                                 dev_dbg(mmc_dev(host->mmc),
2274                                         "Unable to handle MMC board"
2275                                         " level suspend\n");
2276                                 host->suspended = 0;
2277                                 return ret;
2278                         }
2279                 }
2280                 ret = mmc_suspend_host(host->mmc);
2281
2282                 if (ret == 0) {
2283                         omap_hsmmc_disable_irq(host);
2284                         OMAP_HSMMC_WRITE(host->base, HCTL,
2285                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2286                         if (host->got_dbclk)
2287                                 clk_disable(host->dbclk);
2288                 } else {
2289                         host->suspended = 0;
2290                         if (host->pdata->resume) {
2291                                 if (host->pdata->resume(&pdev->dev, host->slot_id))
2292                                         dev_dbg(mmc_dev(host->mmc),
2293                                                 "Unmask interrupt failed\n");
2294                         }
2295                 }
2296                 pm_runtime_put_sync(host->dev);
2297         }
2298         return ret;
2299 }
2300
2301 /* Routine to resume the MMC device */
2302 static int omap_hsmmc_resume(struct device *dev)
2303 {
2304         int ret = 0;
2305         struct platform_device *pdev = to_platform_device(dev);
2306         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2307
2308         if (host && !host->suspended)
2309                 return 0;
2310
2311         if (host) {
2312                 pm_runtime_get_sync(host->dev);
2313
2314                 if (host->got_dbclk)
2315                         clk_enable(host->dbclk);
2316
2317                 omap_hsmmc_conf_bus_power(host);
2318
2319                 if (host->pdata->resume) {
2320                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2321                         if (ret)
2322                                 dev_dbg(mmc_dev(host->mmc),
2323                                         "Unmask interrupt failed\n");
2324                 }
2325
2326                 omap_hsmmc_protect_card(host);
2327
2328                 /* Notify the core to resume the host */
2329                 ret = mmc_resume_host(host->mmc);
2330                 if (ret == 0)
2331                         host->suspended = 0;
2332
2333                 pm_runtime_mark_last_busy(host->dev);
2334                 pm_runtime_put_autosuspend(host->dev);
2335         }
2336
2337         return ret;
2338
2339 }
2340
2341 #else
2342 #define omap_hsmmc_suspend      NULL
2343 #define omap_hsmmc_resume               NULL
2344 #endif
2345
2346 static int omap_hsmmc_runtime_suspend(struct device *dev)
2347 {
2348         struct omap_hsmmc_host *host;
2349         int dma_ch;
2350
2351         host = platform_get_drvdata(to_platform_device(dev));
2352         omap_hsmmc_context_save(host);
2353
2354         dma_ch = xchg(&host->dma_ch_tx, -1);
2355         if (dma_ch != -1)
2356                 omap_free_dma(dma_ch);
2357
2358         dma_ch = xchg(&host->dma_ch_rx, -1);
2359         if (dma_ch != -1)
2360                 omap_free_dma(dma_ch);
2361
2362         dev_dbg(mmc_dev(host->mmc), "disabled\n");
2363
2364         return 0;
2365 }
2366
2367 static int omap_hsmmc_runtime_resume(struct device *dev)
2368 {
2369         struct omap_hsmmc_host *host;
2370
2371         host = platform_get_drvdata(to_platform_device(dev));
2372         omap_hsmmc_context_restore(host);
2373         dev_dbg(mmc_dev(host->mmc), "enabled\n");
2374
2375         return 0;
2376 }
2377
2378 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2379         .suspend        = omap_hsmmc_suspend,
2380         .resume         = omap_hsmmc_resume,
2381         .runtime_suspend = omap_hsmmc_runtime_suspend,
2382         .runtime_resume = omap_hsmmc_runtime_resume,
2383 };
2384
2385 static struct platform_driver omap_hsmmc_driver = {
2386         .remove         = omap_hsmmc_remove,
2387         .driver         = {
2388                 .name = DRIVER_NAME,
2389                 .owner = THIS_MODULE,
2390                 .pm = &omap_hsmmc_dev_pm_ops,
2391         },
2392 };
2393
2394 static int __init omap_hsmmc_init(void)
2395 {
2396         /* Register the MMC driver */
2397         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2398 }
2399
2400 static void __exit omap_hsmmc_cleanup(void)
2401 {
2402         /* Unregister MMC driver */
2403         platform_driver_unregister(&omap_hsmmc_driver);
2404 }
2405
2406 module_init(omap_hsmmc_init);
2407 module_exit(omap_hsmmc_cleanup);
2408
2409 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2410 MODULE_LICENSE("GPL");
2411 MODULE_ALIAS("platform:" DRIVER_NAME);
2412 MODULE_AUTHOR("Texas Instruments Inc");