omap_hsmmc: try to avoid reading the card too early
[pandora-kernel.git] / drivers / mmc / host / omap_hsmmc.c
1 /*
2  * drivers/mmc/host/omap_hsmmc.c
3  *
4  * Driver for OMAP2430/3430 MMC controller.
5  *
6  * Copyright (C) 2007 Texas Instruments.
7  *
8  * Authors:
9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
10  *      Madhusudhan             <madhu.cr@ti.com>
11  *      Mohit Jalori            <mjalori@ti.com>
12  *
13  * This file is licensed under the terms of the GNU General Public License
14  * version 2. This program is licensed "as is" without any warranty of any
15  * kind, whether express or implied.
16  */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/io.h>
33 #include <linux/semaphore.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
37 #include <plat/dma.h>
38 #include <mach/hardware.h>
39 #include <plat/board.h>
40 #include <plat/mmc.h>
41 #include <plat/cpu.h>
42
43 /* OMAP HSMMC Host Controller Registers */
44 #define OMAP_HSMMC_SYSCONFIG    0x0010
45 #define OMAP_HSMMC_SYSSTATUS    0x0014
46 #define OMAP_HSMMC_CON          0x002C
47 #define OMAP_HSMMC_BLK          0x0104
48 #define OMAP_HSMMC_ARG          0x0108
49 #define OMAP_HSMMC_CMD          0x010C
50 #define OMAP_HSMMC_RSP10        0x0110
51 #define OMAP_HSMMC_RSP32        0x0114
52 #define OMAP_HSMMC_RSP54        0x0118
53 #define OMAP_HSMMC_RSP76        0x011C
54 #define OMAP_HSMMC_DATA         0x0120
55 #define OMAP_HSMMC_HCTL         0x0128
56 #define OMAP_HSMMC_SYSCTL       0x012C
57 #define OMAP_HSMMC_STAT         0x0130
58 #define OMAP_HSMMC_IE           0x0134
59 #define OMAP_HSMMC_ISE          0x0138
60 #define OMAP_HSMMC_CAPA         0x0140
61
62 #define VS18                    (1 << 26)
63 #define VS30                    (1 << 25)
64 #define SDVS18                  (0x5 << 9)
65 #define SDVS30                  (0x6 << 9)
66 #define SDVS33                  (0x7 << 9)
67 #define SDVS_MASK               0x00000E00
68 #define SDVSCLR                 0xFFFFF1FF
69 #define SDVSDET                 0x00000400
70 #define AUTOIDLE                0x1
71 #define SDBP                    (1 << 8)
72 #define DTO                     0xe
73 #define ICE                     0x1
74 #define ICS                     0x2
75 #define CEN                     (1 << 2)
76 #define CLKD_MASK               0x0000FFC0
77 #define CLKD_SHIFT              6
78 #define DTO_MASK                0x000F0000
79 #define DTO_SHIFT               16
80 #define INT_EN_MASK             0x307F0033
81 #define BWR_ENABLE              (1 << 4)
82 #define BRR_ENABLE              (1 << 5)
83 #define DTO_ENABLE              (1 << 20)
84 #define INIT_STREAM             (1 << 1)
85 #define DP_SELECT               (1 << 21)
86 #define DDIR                    (1 << 4)
87 #define DMA_EN                  0x1
88 #define MSBS                    (1 << 5)
89 #define BCE                     (1 << 1)
90 #define FOUR_BIT                (1 << 1)
91 #define DW8                     (1 << 5)
92 #define CC                      0x1
93 #define TC                      0x02
94 #define OD                      0x1
95 #define ERR                     (1 << 15)
96 #define CMD_TIMEOUT             (1 << 16)
97 #define DATA_TIMEOUT            (1 << 20)
98 #define CMD_CRC                 (1 << 17)
99 #define DATA_CRC                (1 << 21)
100 #define CARD_ERR                (1 << 28)
101 #define STAT_CLEAR              0xFFFFFFFF
102 #define INIT_STREAM_CMD         0x00000000
103 #define DUAL_VOLT_OCR_BIT       7
104 #define SRC                     (1 << 25)
105 #define SRD                     (1 << 26)
106 #define SOFTRESET               (1 << 1)
107 #define RESETDONE               (1 << 0)
108
109 /*
110  * FIXME: Most likely all the data using these _DEVID defines should come
111  * from the platform_data, or implemented in controller and slot specific
112  * functions.
113  */
114 #define OMAP_MMC1_DEVID         0
115 #define OMAP_MMC2_DEVID         1
116 #define OMAP_MMC3_DEVID         2
117 #define OMAP_MMC4_DEVID         3
118 #define OMAP_MMC5_DEVID         4
119
120 #define MMC_AUTOSUSPEND_DELAY   100
121 #define MMC_TIMEOUT_MS          20
122 #define OMAP_MMC_MASTER_CLOCK   96000000
123 #define OMAP_MMC_MIN_CLOCK      400000
124 #define OMAP_MMC_MAX_CLOCK      52000000
125 #define DRIVER_NAME             "omap_hsmmc"
126
127 /*
128  * One controller can have multiple slots, like on some omap boards using
129  * omap.c controller driver. Luckily this is not currently done on any known
130  * omap_hsmmc.c device.
131  */
132 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
133
134 /*
135  * MMC Host controller read/write API's
136  */
137 #define OMAP_HSMMC_READ(base, reg)      \
138         __raw_readl((base) + OMAP_HSMMC_##reg)
139
140 #define OMAP_HSMMC_WRITE(base, reg, val) \
141         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
142
143 struct omap_hsmmc_next {
144         unsigned int    dma_len;
145         s32             cookie;
146 };
147
148 struct omap_hsmmc_host {
149         struct  device          *dev;
150         struct  mmc_host        *mmc;
151         struct  mmc_request     *mrq;
152         struct  mmc_command     *cmd;
153         struct  mmc_data        *data;
154         struct  clk             *fclk;
155         struct  clk             *dbclk;
156         /*
157          * vcc == configured supply
158          * vcc_aux == optional
159          *   -  MMC1, supply for DAT4..DAT7
160          *   -  MMC2/MMC2, external level shifter voltage supply, for
161          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
162          */
163         struct  regulator       *vcc;
164         struct  regulator       *vcc_aux;
165         void    __iomem         *base;
166         resource_size_t         mapbase;
167         spinlock_t              irq_lock; /* Prevent races with irq handler */
168         unsigned int            id;
169         unsigned int            dma_len;
170         unsigned int            dma_sg_idx;
171         unsigned char           bus_mode;
172         unsigned char           power_mode;
173         u32                     *buffer;
174         u32                     bytesleft;
175         int                     suspended;
176         int                     irq;
177         int                     use_dma, dma_ch;
178         int                     dma_ch_tx, dma_ch_rx;
179         int                     dma_line_tx, dma_line_rx;
180         int                     slot_id;
181         int                     got_dbclk;
182         int                     response_busy;
183         int                     context_loss;
184         int                     dpm_state;
185         int                     vdd;
186         int                     protect_card;
187         int                     reqs_blocked;
188         int                     use_reg;
189         int                     req_in_progress;
190         struct omap_hsmmc_next  next_data;
191
192         struct  omap_mmc_platform_data  *pdata;
193 };
194
195 static int omap_hsmmc_card_detect(struct device *dev, int slot)
196 {
197         struct omap_mmc_platform_data *mmc = dev->platform_data;
198         int val1, val2;
199
200         /* NOTE: assumes card detect signal is active-low */
201         do {
202                 val1 = gpio_get_value_cansleep(mmc->slots[0].switch_pin);
203                 val2 = gpio_get_value_cansleep(mmc->slots[0].switch_pin);
204         }
205         while (val1 != val2);
206
207         return !val1;
208 }
209
210 static int omap_hsmmc_get_wp(struct device *dev, int slot)
211 {
212         struct omap_mmc_platform_data *mmc = dev->platform_data;
213
214         /* NOTE: assumes write protect signal is active-high */
215         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
216 }
217
218 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
219 {
220         struct omap_mmc_platform_data *mmc = dev->platform_data;
221
222         /* NOTE: assumes card detect signal is active-low */
223         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
224 }
225
226 #ifdef CONFIG_PM
227
228 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
229 {
230         struct omap_mmc_platform_data *mmc = dev->platform_data;
231
232         disable_irq(mmc->slots[0].card_detect_irq);
233         return 0;
234 }
235
236 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
237 {
238         struct omap_mmc_platform_data *mmc = dev->platform_data;
239
240         enable_irq(mmc->slots[0].card_detect_irq);
241         return 0;
242 }
243
244 #else
245
246 #define omap_hsmmc_suspend_cdirq        NULL
247 #define omap_hsmmc_resume_cdirq         NULL
248
249 #endif
250
251 #ifdef CONFIG_REGULATOR
252
253 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
254                                   int vdd)
255 {
256         struct omap_hsmmc_host *host =
257                 platform_get_drvdata(to_platform_device(dev));
258         int ret;
259
260         if (mmc_slot(host).before_set_reg)
261                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
262
263         if (power_on)
264                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
265         else
266                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
267
268         if (mmc_slot(host).after_set_reg)
269                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
270
271         return ret;
272 }
273
274 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
275                                    int vdd)
276 {
277         struct omap_hsmmc_host *host =
278                 platform_get_drvdata(to_platform_device(dev));
279         int ret = 0;
280
281         /*
282          * If we don't see a Vcc regulator, assume it's a fixed
283          * voltage always-on regulator.
284          */
285         if (!host->vcc)
286                 return 0;
287
288         if (mmc_slot(host).before_set_reg)
289                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
290
291         /*
292          * Assume Vcc regulator is used only to power the card ... OMAP
293          * VDDS is used to power the pins, optionally with a transceiver to
294          * support cards using voltages other than VDDS (1.8V nominal).  When a
295          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
296          *
297          * In some cases this regulator won't support enable/disable;
298          * e.g. it's a fixed rail for a WLAN chip.
299          *
300          * In other cases vcc_aux switches interface power.  Example, for
301          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
302          * chips/cards need an interface voltage rail too.
303          */
304         if (power_on) {
305                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
306                 /* Enable interface voltage rail, if needed */
307                 if (ret == 0 && host->vcc_aux) {
308                         ret = regulator_enable(host->vcc_aux);
309                         if (ret < 0)
310                                 ret = mmc_regulator_set_ocr(host->mmc,
311                                                         host->vcc, 0);
312                 }
313         } else {
314                 /* Shut down the rail */
315                 if (host->vcc_aux)
316                         ret = regulator_disable(host->vcc_aux);
317                 if (!ret) {
318                         /* Then proceed to shut down the local regulator */
319                         ret = mmc_regulator_set_ocr(host->mmc,
320                                                 host->vcc, 0);
321                 }
322         }
323
324         if (mmc_slot(host).after_set_reg)
325                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
326
327         return ret;
328 }
329
330 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
331                                         int vdd)
332 {
333         return 0;
334 }
335
336 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
337                                   int vdd, int cardsleep)
338 {
339         struct omap_hsmmc_host *host =
340                 platform_get_drvdata(to_platform_device(dev));
341         int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
342
343         return regulator_set_mode(host->vcc, mode);
344 }
345
346 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
347                                    int vdd, int cardsleep)
348 {
349         struct omap_hsmmc_host *host =
350                 platform_get_drvdata(to_platform_device(dev));
351         int err, mode;
352
353         /*
354          * If we don't see a Vcc regulator, assume it's a fixed
355          * voltage always-on regulator.
356          */
357         if (!host->vcc)
358                 return 0;
359
360         mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
361
362         if (!host->vcc_aux)
363                 return regulator_set_mode(host->vcc, mode);
364
365         if (cardsleep) {
366                 /* VCC can be turned off if card is asleep */
367                 if (sleep)
368                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
369                 else
370                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
371         } else
372                 err = regulator_set_mode(host->vcc, mode);
373         if (err)
374                 return err;
375
376         if (!mmc_slot(host).vcc_aux_disable_is_sleep)
377                 return regulator_set_mode(host->vcc_aux, mode);
378
379         if (sleep)
380                 return regulator_disable(host->vcc_aux);
381         else
382                 return regulator_enable(host->vcc_aux);
383 }
384
385 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
386                                         int vdd, int cardsleep)
387 {
388         return 0;
389 }
390
391 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
392 {
393         struct regulator *reg;
394         int ret = 0;
395         int ocr_value = 0;
396
397         switch (host->id) {
398         case OMAP_MMC1_DEVID:
399                 /* On-chip level shifting via PBIAS0/PBIAS1 */
400                 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
401                 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
402                 break;
403         case OMAP_MMC2_DEVID:
404         case OMAP_MMC3_DEVID:
405         case OMAP_MMC5_DEVID:
406                 /* Off-chip level shifting, or none */
407                 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
408                 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
409                 break;
410         case OMAP_MMC4_DEVID:
411                 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
412                 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
413         default:
414                 pr_err("MMC%d configuration not supported!\n", host->id);
415                 return -EINVAL;
416         }
417
418         reg = regulator_get(host->dev, "vmmc");
419         if (IS_ERR(reg)) {
420                 dev_dbg(host->dev, "vmmc regulator missing\n");
421                 /*
422                 * HACK: until fixed.c regulator is usable,
423                 * we don't require a main regulator
424                 * for MMC2 or MMC3
425                 */
426                 if (host->id == OMAP_MMC1_DEVID) {
427                         ret = PTR_ERR(reg);
428                         goto err;
429                 }
430         } else {
431                 host->vcc = reg;
432                 ocr_value = mmc_regulator_get_ocrmask(reg);
433                 if (!mmc_slot(host).ocr_mask) {
434                         mmc_slot(host).ocr_mask = ocr_value;
435                 } else {
436                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
437                                 pr_err("MMC%d ocrmask %x is not supported\n",
438                                         host->id, mmc_slot(host).ocr_mask);
439                                 mmc_slot(host).ocr_mask = 0;
440                                 return -EINVAL;
441                         }
442                 }
443
444                 /* Allow an aux regulator */
445                 reg = regulator_get(host->dev, "vmmc_aux");
446                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
447
448                 /* For eMMC do not power off when not in sleep state */
449                 if (mmc_slot(host).no_regulator_off_init)
450                         return 0;
451                 /*
452                 * UGLY HACK:  workaround regulator framework bugs.
453                 * When the bootloader leaves a supply active, it's
454                 * initialized with zero usecount ... and we can't
455                 * disable it without first enabling it.  Until the
456                 * framework is fixed, we need a workaround like this
457                 * (which is safe for MMC, but not in general).
458                 */
459                 if (regulator_is_enabled(host->vcc) > 0 ||
460                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
461                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
462
463                         mmc_slot(host).set_power(host->dev, host->slot_id,
464                                                  1, vdd);
465                         mmc_slot(host).set_power(host->dev, host->slot_id,
466                                                  0, 0);
467                 }
468         }
469
470         return 0;
471
472 err:
473         mmc_slot(host).set_power = NULL;
474         mmc_slot(host).set_sleep = NULL;
475         return ret;
476 }
477
478 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
479 {
480         regulator_put(host->vcc);
481         regulator_put(host->vcc_aux);
482         mmc_slot(host).set_power = NULL;
483         mmc_slot(host).set_sleep = NULL;
484 }
485
486 static inline int omap_hsmmc_have_reg(void)
487 {
488         return 1;
489 }
490
491 #else
492
493 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
494 {
495         return -EINVAL;
496 }
497
498 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
499 {
500 }
501
502 static inline int omap_hsmmc_have_reg(void)
503 {
504         return 0;
505 }
506
507 #endif
508
509 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
510 {
511         int ret;
512
513         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
514                 if (pdata->slots[0].cover)
515                         pdata->slots[0].get_cover_state =
516                                         omap_hsmmc_get_cover_state;
517                 else
518                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
519                 pdata->slots[0].card_detect_irq =
520                                 gpio_to_irq(pdata->slots[0].switch_pin);
521                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
522                 if (ret)
523                         return ret;
524                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
525                 if (ret)
526                         goto err_free_sp;
527         } else
528                 pdata->slots[0].switch_pin = -EINVAL;
529
530         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
531                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
532                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
533                 if (ret)
534                         goto err_free_cd;
535                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
536                 if (ret)
537                         goto err_free_wp;
538         } else
539                 pdata->slots[0].gpio_wp = -EINVAL;
540
541         return 0;
542
543 err_free_wp:
544         gpio_free(pdata->slots[0].gpio_wp);
545 err_free_cd:
546         if (gpio_is_valid(pdata->slots[0].switch_pin))
547 err_free_sp:
548                 gpio_free(pdata->slots[0].switch_pin);
549         return ret;
550 }
551
552 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
553 {
554         if (gpio_is_valid(pdata->slots[0].gpio_wp))
555                 gpio_free(pdata->slots[0].gpio_wp);
556         if (gpio_is_valid(pdata->slots[0].switch_pin))
557                 gpio_free(pdata->slots[0].switch_pin);
558 }
559
560 /*
561  * Start clock to the card
562  */
563 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
564 {
565         OMAP_HSMMC_WRITE(host->base, SYSCTL,
566                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
567 }
568
569 /*
570  * Stop clock to the card
571  */
572 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
573 {
574         OMAP_HSMMC_WRITE(host->base, SYSCTL,
575                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
576         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
577                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
578 }
579
580 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
581                                   struct mmc_command *cmd)
582 {
583         unsigned int irq_mask;
584
585         if (host->use_dma)
586                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
587         else
588                 irq_mask = INT_EN_MASK;
589
590         /* Disable timeout for erases */
591         if (cmd->opcode == MMC_ERASE)
592                 irq_mask &= ~DTO_ENABLE;
593
594         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
595         OMAP_HSMMC_WRITE(host->base, ISE, host->use_dma ? irq_mask : 0);
596         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
597 }
598
599 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
600 {
601         OMAP_HSMMC_WRITE(host->base, ISE, 0);
602         OMAP_HSMMC_WRITE(host->base, IE, 0);
603         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
604 }
605
606 /* Calculate divisor for the given clock frequency */
607 static u16 calc_divisor(struct mmc_ios *ios)
608 {
609         u16 dsor = 0;
610
611         if (ios->clock) {
612                 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
613                 if (dsor > 250)
614                         dsor = 250;
615         }
616
617         return dsor;
618 }
619
620 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
621 {
622         struct mmc_ios *ios = &host->mmc->ios;
623         unsigned long regval;
624         unsigned long timeout;
625
626         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
627
628         omap_hsmmc_stop_clock(host);
629
630         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
631         regval = regval & ~(CLKD_MASK | DTO_MASK);
632         regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
633         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
634         OMAP_HSMMC_WRITE(host->base, SYSCTL,
635                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
636
637         /* Wait till the ICS bit is set */
638         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
639         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
640                 && time_before(jiffies, timeout))
641                 cpu_relax();
642
643         omap_hsmmc_start_clock(host);
644 }
645
646 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
647 {
648         struct mmc_ios *ios = &host->mmc->ios;
649         u32 con;
650
651         con = OMAP_HSMMC_READ(host->base, CON);
652         switch (ios->bus_width) {
653         case MMC_BUS_WIDTH_8:
654                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
655                 break;
656         case MMC_BUS_WIDTH_4:
657                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
658                 OMAP_HSMMC_WRITE(host->base, HCTL,
659                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
660                 break;
661         case MMC_BUS_WIDTH_1:
662                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
663                 OMAP_HSMMC_WRITE(host->base, HCTL,
664                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
665                 break;
666         }
667 }
668
669 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
670 {
671         struct mmc_ios *ios = &host->mmc->ios;
672         u32 con;
673
674         con = OMAP_HSMMC_READ(host->base, CON);
675         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
676                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
677         else
678                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
679 }
680
681 #ifdef CONFIG_PM
682
683 /*
684  * Restore the MMC host context, if it was lost as result of a
685  * power state change.
686  */
687 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
688 {
689         struct mmc_ios *ios = &host->mmc->ios;
690         struct omap_mmc_platform_data *pdata = host->pdata;
691         int context_loss = 0;
692         u32 hctl, capa;
693         unsigned long timeout;
694
695         if (pdata->get_context_loss_count) {
696                 context_loss = pdata->get_context_loss_count(host->dev);
697                 if (context_loss < 0)
698                         return 1;
699         }
700
701         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
702                 context_loss == host->context_loss ? "not " : "");
703         if (host->context_loss == context_loss)
704                 return 1;
705
706         /* Wait for hardware reset */
707         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
708         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
709                 && time_before(jiffies, timeout))
710                 ;
711
712         /* Do software reset */
713         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
714         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
715         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
716                 && time_before(jiffies, timeout))
717                 ;
718
719         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
720                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
721
722         if (host->id == OMAP_MMC1_DEVID) {
723                 if (host->power_mode != MMC_POWER_OFF &&
724                     (1 << ios->vdd) <= MMC_VDD_23_24)
725                         hctl = SDVS18;
726                 else
727                         hctl = SDVS30;
728                 capa = VS30 | VS18;
729         } else {
730                 hctl = SDVS18;
731                 capa = VS18;
732         }
733
734         OMAP_HSMMC_WRITE(host->base, HCTL,
735                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
736
737         OMAP_HSMMC_WRITE(host->base, CAPA,
738                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
739
740         OMAP_HSMMC_WRITE(host->base, HCTL,
741                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
742
743         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
744         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
745                 && time_before(jiffies, timeout))
746                 ;
747
748         omap_hsmmc_disable_irq(host);
749
750         /* Do not initialize card-specific things if the power is off */
751         if (host->power_mode == MMC_POWER_OFF)
752                 goto out;
753
754         omap_hsmmc_set_bus_width(host);
755
756         omap_hsmmc_set_clock(host);
757
758         omap_hsmmc_set_bus_mode(host);
759
760 out:
761         host->context_loss = context_loss;
762
763         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
764         return 0;
765 }
766
767 /*
768  * Save the MMC host context (store the number of power state changes so far).
769  */
770 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
771 {
772         struct omap_mmc_platform_data *pdata = host->pdata;
773         int context_loss;
774
775         if (pdata->get_context_loss_count) {
776                 context_loss = pdata->get_context_loss_count(host->dev);
777                 if (context_loss < 0)
778                         return;
779                 host->context_loss = context_loss;
780         }
781 }
782
783 #else
784
785 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
786 {
787         return 0;
788 }
789
790 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
791 {
792 }
793
794 #endif
795
796 /*
797  * Send init stream sequence to card
798  * before sending IDLE command
799  */
800 static void send_init_stream(struct omap_hsmmc_host *host)
801 {
802         int reg = 0;
803         unsigned long timeout;
804
805         if (host->protect_card)
806                 return;
807
808         disable_irq(host->irq);
809
810         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
811         OMAP_HSMMC_WRITE(host->base, CON,
812                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
813         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
814
815         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
816         while ((reg != CC) && time_before(jiffies, timeout))
817                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
818
819         OMAP_HSMMC_WRITE(host->base, CON,
820                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
821
822         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
823         OMAP_HSMMC_READ(host->base, STAT);
824
825         enable_irq(host->irq);
826 }
827
828 static inline
829 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
830 {
831         int r = 1;
832
833         if (mmc_slot(host).get_cover_state)
834                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
835         return r;
836 }
837
838 static ssize_t
839 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
840                            char *buf)
841 {
842         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
843         struct omap_hsmmc_host *host = mmc_priv(mmc);
844
845         return sprintf(buf, "%s\n",
846                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
847 }
848
849 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
850
851 static ssize_t
852 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
853                         char *buf)
854 {
855         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
856         struct omap_hsmmc_host *host = mmc_priv(mmc);
857
858         return sprintf(buf, "%s\n", mmc_slot(host).name);
859 }
860
861 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
862
863 /* for hosts with 35xx erratum 2.1.1.128 */
864 static ssize_t
865 omap_hsmmc_show_unsafe_read(struct device *dev, struct device_attribute *attr,
866                         char *buf)
867 {
868         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
869         int val = 0;
870
871         if (!(mmc->caps2 & MMC_CAP2_NO_MULTI_READ)) {
872                 val = 1;
873                 if (mmc->f_max == OMAP_MMC_MAX_CLOCK)
874                         val = 2;
875         }
876
877         return sprintf(buf, "%d\n", val);
878 }
879
880 static ssize_t
881 omap_hsmmc_set_unsafe_read(struct device *dev, struct device_attribute *attr,
882                 const char *buf, size_t count)
883 {
884         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
885         unsigned long val;
886         int ret;
887
888         ret = strict_strtoul(buf, 0, &val);
889         if (ret)
890                 return -EINVAL;
891
892         switch (val) {
893         case 0:
894                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
895                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
896                 break;
897         case 1:
898                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
899                 mmc->f_max = 32000000;
900                 break;
901         case 2:
902                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
903                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
904                 break;
905         }
906
907         return count;
908 }
909 static DEVICE_ATTR(unsafe_read, S_IWUSR | S_IRUGO,
910         omap_hsmmc_show_unsafe_read, omap_hsmmc_set_unsafe_read);
911
912 /*
913  * Configure the response type and send the cmd.
914  */
915 static void
916 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
917         struct mmc_data *data)
918 {
919         int cmdreg = 0, resptype = 0, cmdtype = 0;
920
921         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
922                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
923         host->cmd = cmd;
924
925         omap_hsmmc_enable_irq(host, cmd);
926
927         host->response_busy = 0;
928         if (cmd->flags & MMC_RSP_PRESENT) {
929                 if (cmd->flags & MMC_RSP_136)
930                         resptype = 1;
931                 else if (cmd->flags & MMC_RSP_BUSY) {
932                         resptype = 3;
933                         host->response_busy = 1;
934                 } else
935                         resptype = 2;
936         }
937
938         /*
939          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
940          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
941          * a val of 0x3, rest 0x0.
942          */
943         if (cmd == host->mrq->stop)
944                 cmdtype = 0x3;
945
946         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
947
948         if (data) {
949                 cmdreg |= DP_SELECT | MSBS | BCE;
950                 if (data->flags & MMC_DATA_READ)
951                         cmdreg |= DDIR;
952                 else
953                         cmdreg &= ~(DDIR);
954         }
955
956         if (host->use_dma)
957                 cmdreg |= DMA_EN;
958
959         host->req_in_progress = 1;
960
961         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
962         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
963 }
964
965 static int
966 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
967 {
968         if (data->flags & MMC_DATA_WRITE)
969                 return DMA_TO_DEVICE;
970         else
971                 return DMA_FROM_DEVICE;
972 }
973
974 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
975 {
976         int dma_ch;
977
978         spin_lock(&host->irq_lock);
979         host->req_in_progress = 0;
980         dma_ch = host->dma_ch;
981         spin_unlock(&host->irq_lock);
982
983         omap_hsmmc_disable_irq(host);
984         /* Do not complete the request if DMA is still in progress */
985         if (mrq->data && host->use_dma && dma_ch != -1)
986                 return;
987         host->mrq = NULL;
988         mmc_request_done(host->mmc, mrq);
989 }
990
991 /*
992  * Notify the transfer complete to MMC core
993  */
994 static void
995 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
996 {
997         if (!data) {
998                 struct mmc_request *mrq = host->mrq;
999
1000                 /* TC before CC from CMD6 - don't know why, but it happens */
1001                 if (host->cmd && host->cmd->opcode == 6 &&
1002                     host->response_busy) {
1003                         host->response_busy = 0;
1004                         return;
1005                 }
1006
1007                 omap_hsmmc_request_done(host, mrq);
1008                 return;
1009         }
1010
1011         host->data = NULL;
1012
1013         if (!data->error)
1014                 data->bytes_xfered += data->blocks * (data->blksz);
1015         else
1016                 data->bytes_xfered = 0;
1017
1018         if (!data->stop) {
1019                 omap_hsmmc_request_done(host, data->mrq);
1020                 return;
1021         }
1022         omap_hsmmc_start_command(host, data->stop, NULL);
1023 }
1024
1025 /*
1026  * Notify the core about command completion
1027  */
1028 static void
1029 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
1030 {
1031         host->cmd = NULL;
1032
1033         if (cmd->flags & MMC_RSP_PRESENT) {
1034                 if (cmd->flags & MMC_RSP_136) {
1035                         /* response type 2 */
1036                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1037                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1038                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1039                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1040                 } else {
1041                         /* response types 1, 1b, 3, 4, 5, 6 */
1042                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1043                 }
1044         }
1045         if ((host->data == NULL && !host->response_busy) || cmd->error)
1046                 omap_hsmmc_request_done(host, cmd->mrq);
1047 }
1048
1049 static void omap_hsmmc_free_dma(struct omap_hsmmc_host *host)
1050 {
1051         int dma_ch;
1052
1053         dma_ch = xchg(&host->dma_ch_tx, -1);
1054         if (dma_ch != -1)
1055                 omap_free_dma(dma_ch);
1056
1057         dma_ch = xchg(&host->dma_ch_rx, -1);
1058         if (dma_ch != -1)
1059                 omap_free_dma(dma_ch);
1060 }
1061
1062 /*
1063  * DMA clean up for command errors
1064  */
1065 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1066 {
1067         int dma_ch;
1068
1069         host->data->error = errno;
1070
1071         spin_lock(&host->irq_lock);
1072         dma_ch = host->dma_ch;
1073         host->dma_ch = -1;
1074         spin_unlock(&host->irq_lock);
1075
1076         if (host->use_dma && dma_ch != -1) {
1077                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1078                         host->data->sg_len,
1079                         omap_hsmmc_get_dma_dir(host, host->data));
1080                 host->data->host_cookie = 0;
1081         }
1082         omap_hsmmc_free_dma(host);
1083         host->data = NULL;
1084 }
1085
1086 /*
1087  * Readable error output
1088  */
1089 #ifdef CONFIG_MMC_DEBUG
1090 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1091 {
1092         /* --- means reserved bit without definition at documentation */
1093         static const char *omap_hsmmc_status_bits[] = {
1094                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1095                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1096                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1097                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1098         };
1099         char res[256];
1100         char *buf = res;
1101         int len, i;
1102
1103         len = sprintf(buf, "MMC IRQ 0x%x :", status);
1104         buf += len;
1105
1106         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1107                 if (status & (1 << i)) {
1108                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1109                         buf += len;
1110                 }
1111
1112         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1113 }
1114 #else
1115 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1116                                              u32 status)
1117 {
1118 }
1119 #endif  /* CONFIG_MMC_DEBUG */
1120
1121 /*
1122  * MMC controller internal state machines reset
1123  *
1124  * Used to reset command or data internal state machines, using respectively
1125  *  SRC or SRD bit of SYSCTL register
1126  * Can be called from interrupt context
1127  */
1128 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1129                                                    unsigned long bit)
1130 {
1131         unsigned long i = 0;
1132         unsigned long limit = (loops_per_jiffy *
1133                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
1134
1135         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1136                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1137
1138         /*
1139          * OMAP4 ES2 and greater has an updated reset logic.
1140          * Monitor a 0->1 transition first
1141          */
1142         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1143                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1144                                         && (i++ < limit))
1145                         cpu_relax();
1146         }
1147         i = 0;
1148
1149         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1150                 (i++ < limit))
1151                 cpu_relax();
1152
1153         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1154                 dev_err(mmc_dev(host->mmc),
1155                         "Timeout waiting on controller reset in %s\n",
1156                         __func__);
1157 }
1158
1159 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1160 {
1161         struct mmc_data *data;
1162         int end_cmd = 0, end_trans = 0;
1163
1164         if (unlikely(!host->req_in_progress)) {
1165                 OMAP_HSMMC_WRITE(host->base, STAT, status);
1166                 return;
1167         }
1168
1169         data = host->data;
1170         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1171
1172         if (unlikely(status & ERR)) {
1173                 omap_hsmmc_dbg_report_irq(host, status);
1174                 if ((status & CMD_TIMEOUT) ||
1175                         (status & CMD_CRC)) {
1176                         if (host->cmd) {
1177                                 if (status & CMD_TIMEOUT) {
1178                                         omap_hsmmc_reset_controller_fsm(host,
1179                                                                         SRC);
1180                                         host->cmd->error = -ETIMEDOUT;
1181                                 } else {
1182                                         host->cmd->error = -EILSEQ;
1183                                 }
1184                                 end_cmd = 1;
1185                         }
1186                         if (host->data || host->response_busy) {
1187                                 if (host->data)
1188                                         omap_hsmmc_dma_cleanup(host,
1189                                                                 -ETIMEDOUT);
1190                                 host->response_busy = 0;
1191                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1192                         }
1193                 }
1194                 if ((status & DATA_TIMEOUT) ||
1195                         (status & DATA_CRC)) {
1196                         if (host->data || host->response_busy) {
1197                                 int err = (status & DATA_TIMEOUT) ?
1198                                                 -ETIMEDOUT : -EILSEQ;
1199
1200                                 if (host->data)
1201                                         omap_hsmmc_dma_cleanup(host, err);
1202                                 else
1203                                         host->mrq->cmd->error = err;
1204                                 host->response_busy = 0;
1205                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1206                                 end_trans = 1;
1207                         }
1208                 }
1209                 if (status & CARD_ERR) {
1210                         dev_dbg(mmc_dev(host->mmc),
1211                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1212                         if (host->cmd)
1213                                 end_cmd = 1;
1214                         if (host->data)
1215                                 end_trans = 1;
1216                 }
1217         }
1218
1219         OMAP_HSMMC_WRITE(host->base, STAT, status);
1220
1221         if (end_cmd || ((status & CC) && host->cmd))
1222                 omap_hsmmc_cmd_done(host, host->cmd);
1223         if ((end_trans || (status & TC)) && host->mrq)
1224                 omap_hsmmc_xfer_done(host, data);
1225 }
1226
1227 /*
1228  * MMC controller IRQ handler
1229  */
1230 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1231 {
1232         struct omap_hsmmc_host *host = dev_id;
1233         int status;
1234
1235         status = OMAP_HSMMC_READ(host->base, STAT);
1236         do {
1237                 omap_hsmmc_do_irq(host, status);
1238                 /* Flush posted write */
1239                 status = OMAP_HSMMC_READ(host->base, STAT);
1240         } while (status & INT_EN_MASK);
1241
1242         return IRQ_HANDLED;
1243 }
1244
1245 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1246 {
1247         unsigned long i;
1248
1249         OMAP_HSMMC_WRITE(host->base, HCTL,
1250                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1251         for (i = 0; i < loops_per_jiffy; i++) {
1252                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1253                         break;
1254                 cpu_relax();
1255         }
1256 }
1257
1258 /*
1259  * Switch MMC interface voltage ... only relevant for MMC1.
1260  *
1261  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1262  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1263  * Some chips, like eMMC ones, use internal transceivers.
1264  */
1265 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1266 {
1267         u32 reg_val = 0;
1268         int ret;
1269
1270         /* Disable the clocks */
1271         pm_runtime_put_sync(host->dev);
1272         if (host->got_dbclk)
1273                 clk_disable(host->dbclk);
1274
1275         /* Turn the power off */
1276         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1277
1278         /* Turn the power ON with given VDD 1.8 or 3.0v */
1279         if (!ret)
1280                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1281                                                vdd);
1282         pm_runtime_get_sync(host->dev);
1283         if (host->got_dbclk)
1284                 clk_enable(host->dbclk);
1285
1286         if (ret != 0)
1287                 goto err;
1288
1289         OMAP_HSMMC_WRITE(host->base, HCTL,
1290                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1291         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1292
1293         /*
1294          * If a MMC dual voltage card is detected, the set_ios fn calls
1295          * this fn with VDD bit set for 1.8V. Upon card removal from the
1296          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1297          *
1298          * Cope with a bit of slop in the range ... per data sheets:
1299          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1300          *    but recommended values are 1.71V to 1.89V
1301          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1302          *    but recommended values are 2.7V to 3.3V
1303          *
1304          * Board setup code shouldn't permit anything very out-of-range.
1305          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1306          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1307          */
1308         if ((1 << vdd) <= MMC_VDD_23_24)
1309                 reg_val |= SDVS18;
1310         else
1311                 reg_val |= SDVS30;
1312
1313         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1314         set_sd_bus_power(host);
1315
1316         return 0;
1317 err:
1318         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1319         return ret;
1320 }
1321
1322 /* Protect the card while the cover is open */
1323 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1324 {
1325         if (!mmc_slot(host).get_cover_state)
1326                 return;
1327
1328         host->reqs_blocked = 0;
1329         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1330                 if (host->protect_card) {
1331                         pr_info("%s: cover is closed, "
1332                                          "card is now accessible\n",
1333                                          mmc_hostname(host->mmc));
1334                         host->protect_card = 0;
1335                 }
1336         } else {
1337                 if (!host->protect_card) {
1338                         pr_info("%s: cover is open, "
1339                                          "card is now inaccessible\n",
1340                                          mmc_hostname(host->mmc));
1341                         host->protect_card = 1;
1342                 }
1343         }
1344 }
1345
1346 /*
1347  * irq handler to notify the core about card insertion/removal
1348  */
1349 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1350 {
1351         struct omap_hsmmc_host *host = dev_id;
1352         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1353         int carddetect;
1354
1355         if (host->suspended)
1356                 return IRQ_HANDLED;
1357
1358         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1359
1360         if (slot->card_detect)
1361                 carddetect = slot->card_detect(host->dev, host->slot_id);
1362         else {
1363                 omap_hsmmc_protect_card(host);
1364                 carddetect = -ENOSYS;
1365         }
1366
1367         if (carddetect)
1368                 mmc_detect_change(host->mmc, (HZ * 500) / 1000);
1369         else
1370                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1371         return IRQ_HANDLED;
1372 }
1373
1374 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1375                                      struct mmc_data *data)
1376 {
1377         int sync_dev;
1378
1379         if (data->flags & MMC_DATA_WRITE)
1380                 sync_dev = host->dma_line_tx;
1381         else
1382                 sync_dev = host->dma_line_rx;
1383         return sync_dev;
1384 }
1385
1386 static void omap_hsmmc_config_dma_params_once(struct omap_hsmmc_host *host,
1387                                               struct mmc_data *data,
1388                                               int dma_ch)
1389 {
1390         /* pandora hack: only benefits wifi, so only set there, just in case */
1391         if (host->id != OMAP_MMC3_DEVID)
1392                 return;
1393
1394         if (data->flags & MMC_DATA_WRITE) {
1395                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_16);
1396                 omap_set_dma_src_data_pack(dma_ch, 1);
1397         } else {
1398                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_16);
1399                 omap_set_dma_dest_data_pack(dma_ch, 1);
1400         }
1401 }
1402
1403 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1404                                        struct mmc_data *data,
1405                                        struct scatterlist *sgl)
1406 {
1407         int blksz, nblk, dma_ch, sync;
1408
1409         dma_ch = host->dma_ch;
1410         if (data->flags & MMC_DATA_WRITE) {
1411                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1412                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1413                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1414                         sg_dma_address(sgl), 0, 0);
1415                 sync = OMAP_DMA_DST_SYNC;
1416         } else {
1417                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1418                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1419                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1420                         sg_dma_address(sgl), 0, 0);
1421                 sync = OMAP_DMA_SRC_SYNC;
1422         }
1423
1424         blksz = host->data->blksz;
1425         nblk = sg_dma_len(sgl) / blksz;
1426
1427         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1428                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1429                         omap_hsmmc_get_dma_sync_dev(host, data), sync);
1430
1431         omap_start_dma(dma_ch);
1432 }
1433
1434 /*
1435  * DMA call back function
1436  */
1437 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1438 {
1439         struct omap_hsmmc_host *host = cb_data;
1440         struct mmc_data *data;
1441         int req_in_progress;
1442
1443         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1444                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1445                         ch_status);
1446                 return;
1447         }
1448
1449         spin_lock(&host->irq_lock);
1450         if (host->dma_ch < 0) {
1451                 spin_unlock(&host->irq_lock);
1452                 return;
1453         }
1454
1455         data = host->mrq->data;
1456         host->dma_sg_idx++;
1457         if (host->dma_sg_idx < host->dma_len) {
1458                 /* Fire up the next transfer. */
1459                 omap_hsmmc_config_dma_params(host, data,
1460                                            data->sg + host->dma_sg_idx);
1461                 spin_unlock(&host->irq_lock);
1462                 return;
1463         }
1464
1465         if (!data->host_cookie)
1466                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1467                              omap_hsmmc_get_dma_dir(host, data));
1468
1469         req_in_progress = host->req_in_progress;
1470         host->dma_ch = -1;
1471         spin_unlock(&host->irq_lock);
1472
1473         /* If DMA has finished after TC, complete the request */
1474         if (!req_in_progress) {
1475                 struct mmc_request *mrq = host->mrq;
1476
1477                 host->mrq = NULL;
1478                 mmc_request_done(host->mmc, mrq);
1479         }
1480 }
1481
1482 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1483                                        struct mmc_data *data,
1484                                        struct omap_hsmmc_next *next)
1485 {
1486         int dma_len;
1487
1488         if (unlikely(!next && data->host_cookie &&
1489             data->host_cookie != host->next_data.cookie)) {
1490                 pr_warning("[%s] invalid cookie: data->host_cookie %d"
1491                        " host->next_data.cookie %d\n",
1492                        __func__, data->host_cookie, host->next_data.cookie);
1493                 data->host_cookie = 0;
1494         }
1495
1496         /* Check if next job is already prepared */
1497         if (next ||
1498             (!next && data->host_cookie != host->next_data.cookie)) {
1499                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1500                                      data->sg_len,
1501                                      omap_hsmmc_get_dma_dir(host, data));
1502
1503         } else {
1504                 dma_len = host->next_data.dma_len;
1505                 host->next_data.dma_len = 0;
1506         }
1507
1508
1509         if (unlikely(dma_len == 0))
1510                 return -EINVAL;
1511
1512         if (next) {
1513                 next->dma_len = dma_len;
1514                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1515         } else
1516                 host->dma_len = dma_len;
1517
1518         return 0;
1519 }
1520
1521 /*
1522  * Routine to configure and start DMA for the MMC card
1523  */
1524 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1525                                         struct mmc_request *req)
1526 {
1527         int dma_ch = 0, ret = 0, i;
1528         struct mmc_data *data = req->data;
1529
1530         /* Sanity check: all the SG entries must be aligned by block size. */
1531         for (i = 0; i < data->sg_len; i++) {
1532                 struct scatterlist *sgl;
1533
1534                 sgl = data->sg + i;
1535                 if (unlikely(sgl->length % data->blksz))
1536                         return -EINVAL;
1537         }
1538         if (unlikely((data->blksz % 4) != 0))
1539                 /* REVISIT: The MMC buffer increments only when MSB is written.
1540                  * Return error for blksz which is non multiple of four.
1541                  */
1542                 return -EINVAL;
1543
1544         BUG_ON(host->dma_ch != -1);
1545
1546         if (data->flags & MMC_DATA_WRITE)
1547                 dma_ch = host->dma_ch_tx;
1548         else
1549                 dma_ch = host->dma_ch_rx;
1550
1551         if (dma_ch == -1) {
1552                 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1553                                        "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1554                 if (unlikely(ret != 0)) {
1555                         dev_err(mmc_dev(host->mmc),
1556                                 "%s: omap_request_dma() failed with %d\n",
1557                                 mmc_hostname(host->mmc), ret);
1558                         return ret;
1559                 }
1560
1561                 omap_hsmmc_config_dma_params_once(host, data, dma_ch);
1562
1563                 if (data->flags & MMC_DATA_WRITE)
1564                         host->dma_ch_tx = dma_ch;
1565                 else
1566                         host->dma_ch_rx = dma_ch;
1567         }
1568
1569         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1570         if (unlikely(ret))
1571                 return ret;
1572
1573         host->dma_ch = dma_ch;
1574         host->dma_sg_idx = 0;
1575
1576         omap_hsmmc_config_dma_params(host, data, data->sg);
1577
1578         return 0;
1579 }
1580
1581 /* pandora wifi small transfer hack */
1582 static int check_mmc3_dma_hack(struct omap_hsmmc_host *host,
1583                                struct mmc_request *req)
1584 {
1585         if (req->data != NULL && req->data->sg_len == 1
1586             && req->data->sg->length <= 16)
1587                 return 0;
1588         else
1589                 return 1;
1590 }
1591
1592 /*
1593  * Configure block length for MMC/SD cards and initiate the transfer.
1594  */
1595 static int
1596 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1597 {
1598         int ret;
1599         host->data = req->data;
1600
1601         if (req->data == NULL) {
1602                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1603                 return 0;
1604         }
1605
1606         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1607                                         | (req->data->blocks << 16));
1608
1609         if (host->use_dma) {
1610                 ret = omap_hsmmc_start_dma_transfer(host, req);
1611                 if (ret != 0) {
1612                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1613                         return ret;
1614                 }
1615         }
1616         return 0;
1617 }
1618
1619 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1620                                 int err)
1621 {
1622         struct omap_hsmmc_host *host = mmc_priv(mmc);
1623         struct mmc_data *data = mrq->data;
1624
1625         if (host->use_dma) {
1626                 if (data->host_cookie)
1627                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1628                                      data->sg_len,
1629                                      omap_hsmmc_get_dma_dir(host, data));
1630                 data->host_cookie = 0;
1631         }
1632 }
1633
1634 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1635                                bool is_first_req)
1636 {
1637         struct omap_hsmmc_host *host = mmc_priv(mmc);
1638         int use_dma = host->use_dma;
1639
1640         if (mrq->data->host_cookie) {
1641                 mrq->data->host_cookie = 0;
1642                 return ;
1643         }
1644
1645         if (host->id == OMAP_MMC3_DEVID)
1646                 use_dma = check_mmc3_dma_hack(host, mrq);
1647         if (use_dma)
1648                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1649                                                 &host->next_data))
1650                         mrq->data->host_cookie = 0;
1651 }
1652
1653 #define BWR (1 << 4)
1654 #define BRR (1 << 5)
1655
1656 static noinline void omap_hsmmc_request_do_pio(struct mmc_host *mmc,
1657         struct mmc_request *req)
1658 {
1659         struct omap_hsmmc_host *host = mmc_priv(mmc);
1660         u32 *data = sg_virt(req->data->sg);
1661         u32 len = req->data->sg->length;
1662         int stat;
1663         int i;
1664
1665         for (i = 0; i < 10000000; i++) {
1666                 stat = OMAP_HSMMC_READ(host->base, STAT);
1667                 if (stat == 0)
1668                         continue;
1669
1670                 //dev_err(mmc_dev(host->mmc), "stat %x, l %d\n", stat, i);
1671
1672                 if (stat & (DATA_TIMEOUT | DATA_CRC))
1673                         omap_hsmmc_reset_controller_fsm(host, SRD);
1674
1675                 if (stat & ERR) {
1676                         req->cmd->error =
1677                         req->data->error = -EINVAL; // ?
1678                         omap_hsmmc_xfer_done(host, host->data);
1679                         return;
1680                 }
1681         
1682                 if (req->data->flags & MMC_DATA_WRITE) {
1683                         while (len > 0 && (stat & BWR)) {
1684                                 OMAP_HSMMC_WRITE(host->base, DATA, *data++);
1685                                 len -= 4;
1686                         }
1687                 } else {
1688                         while (len > 0 && (stat & BRR)) {
1689                                 *data++ = OMAP_HSMMC_READ(host->base, DATA);
1690                                 len -= 4;
1691                         }
1692                 }
1693
1694                 if ((stat & CC) && host->cmd)
1695                         omap_hsmmc_cmd_done(host, host->cmd);
1696                 if ((stat & TC) && host->mrq) {
1697                         omap_hsmmc_xfer_done(host, host->data);
1698                         break;
1699                 }
1700         }
1701
1702         if (len > 0) {
1703                 req->cmd->error =
1704                 req->data->error = -ETIMEDOUT;
1705                 omap_hsmmc_xfer_done(host, req->data);
1706         }
1707 }
1708
1709 /*
1710  * Request function. for read/write operation
1711  */
1712 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1713 {
1714         struct omap_hsmmc_host *host = mmc_priv(mmc);
1715         int err;
1716
1717         BUG_ON(host->req_in_progress);
1718         BUG_ON(host->dma_ch != -1);
1719         if (unlikely(host->protect_card)) {
1720                 if (host->reqs_blocked < 3) {
1721                         /*
1722                          * Ensure the controller is left in a consistent
1723                          * state by resetting the command and data state
1724                          * machines.
1725                          */
1726                         omap_hsmmc_reset_controller_fsm(host, SRD);
1727                         omap_hsmmc_reset_controller_fsm(host, SRC);
1728                         host->reqs_blocked += 1;
1729                 }
1730                 req->cmd->error = -EBADF;
1731                 if (req->data)
1732                         req->data->error = -EBADF;
1733                 req->cmd->retries = 0;
1734                 mmc_request_done(mmc, req);
1735                 return;
1736         } else if (host->reqs_blocked)
1737                 host->reqs_blocked = 0;
1738
1739         /* pandora wifi hack... */
1740         if (host->id == OMAP_MMC3_DEVID)
1741                 host->use_dma = check_mmc3_dma_hack(host, req);
1742
1743         WARN_ON(host->mrq != NULL);
1744         host->mrq = req;
1745         err = omap_hsmmc_prepare_data(host, req);
1746         if (unlikely(err)) {
1747                 req->cmd->error = err;
1748                 if (req->data)
1749                         req->data->error = err;
1750                 host->mrq = NULL;
1751                 mmc_request_done(mmc, req);
1752                 return;
1753         }
1754
1755         omap_hsmmc_start_command(host, req->cmd, req->data);
1756
1757         if (host->use_dma == 0)
1758                 omap_hsmmc_request_do_pio(mmc, req);
1759 }
1760
1761 /* Routine to configure clock values. Exposed API to core */
1762 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1763 {
1764         struct omap_hsmmc_host *host = mmc_priv(mmc);
1765         int do_send_init_stream = 0;
1766
1767         pm_runtime_get_sync(host->dev);
1768
1769         if (ios->power_mode != host->power_mode) {
1770                 switch (ios->power_mode) {
1771                 case MMC_POWER_OFF:
1772                         mmc_slot(host).set_power(host->dev, host->slot_id,
1773                                                  0, 0);
1774                         host->vdd = 0;
1775                         break;
1776                 case MMC_POWER_UP:
1777                         mmc_slot(host).set_power(host->dev, host->slot_id,
1778                                                  1, ios->vdd);
1779                         host->vdd = ios->vdd;
1780                         break;
1781                 case MMC_POWER_ON:
1782                         do_send_init_stream = 1;
1783                         break;
1784                 }
1785                 host->power_mode = ios->power_mode;
1786         }
1787
1788         /* FIXME: set registers based only on changes to ios */
1789
1790         omap_hsmmc_set_bus_width(host);
1791
1792         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1793                 /* Only MMC1 can interface at 3V without some flavor
1794                  * of external transceiver; but they all handle 1.8V.
1795                  */
1796                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1797                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1798                                 /*
1799                                  * The mmc_select_voltage fn of the core does
1800                                  * not seem to set the power_mode to
1801                                  * MMC_POWER_UP upon recalculating the voltage.
1802                                  * vdd 1.8v.
1803                                  */
1804                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1805                                 dev_dbg(mmc_dev(host->mmc),
1806                                                 "Switch operation failed\n");
1807                 }
1808         }
1809
1810         omap_hsmmc_set_clock(host);
1811
1812         if (do_send_init_stream)
1813                 send_init_stream(host);
1814
1815         omap_hsmmc_set_bus_mode(host);
1816
1817         pm_runtime_put_autosuspend(host->dev);
1818 }
1819
1820 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1821 {
1822         struct omap_hsmmc_host *host = mmc_priv(mmc);
1823
1824         if (!mmc_slot(host).card_detect)
1825                 return -ENOSYS;
1826         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1827 }
1828
1829 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1830 {
1831         struct omap_hsmmc_host *host = mmc_priv(mmc);
1832
1833         if (!mmc_slot(host).get_ro)
1834                 return -ENOSYS;
1835         return mmc_slot(host).get_ro(host->dev, 0);
1836 }
1837
1838 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1839 {
1840         struct omap_hsmmc_host *host = mmc_priv(mmc);
1841
1842         if (mmc_slot(host).init_card)
1843                 mmc_slot(host).init_card(card);
1844 }
1845
1846 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1847 {
1848         u32 hctl, capa, value;
1849
1850         /* Only MMC1 supports 3.0V */
1851         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1852                 hctl = SDVS30;
1853                 capa = VS30 | VS18;
1854         } else {
1855                 hctl = SDVS18;
1856                 capa = VS18;
1857         }
1858
1859         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1860         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1861
1862         value = OMAP_HSMMC_READ(host->base, CAPA);
1863         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1864
1865         /* Set the controller to AUTO IDLE mode */
1866         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1867         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1868
1869         /* Set SD bus power bit */
1870         set_sd_bus_power(host);
1871 }
1872
1873 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1874 {
1875         struct omap_hsmmc_host *host = mmc_priv(mmc);
1876
1877         pm_runtime_get_sync(host->dev);
1878
1879         return 0;
1880 }
1881
1882 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1883 {
1884         struct omap_hsmmc_host *host = mmc_priv(mmc);
1885
1886         pm_runtime_mark_last_busy(host->dev);
1887         pm_runtime_put_autosuspend(host->dev);
1888
1889         return 0;
1890 }
1891
1892 static const struct mmc_host_ops omap_hsmmc_ops = {
1893         .enable = omap_hsmmc_enable_fclk,
1894         .disable = omap_hsmmc_disable_fclk,
1895         .post_req = omap_hsmmc_post_req,
1896         .pre_req = omap_hsmmc_pre_req,
1897         .request = omap_hsmmc_request,
1898         .set_ios = omap_hsmmc_set_ios,
1899         .get_cd = omap_hsmmc_get_cd,
1900         .get_ro = omap_hsmmc_get_ro,
1901         .init_card = omap_hsmmc_init_card,
1902         /* NYET -- enable_sdio_irq */
1903 };
1904
1905 #ifdef CONFIG_DEBUG_FS
1906
1907 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1908 {
1909         struct mmc_host *mmc = s->private;
1910         struct omap_hsmmc_host *host = mmc_priv(mmc);
1911         int context_loss = 0;
1912
1913         if (host->pdata->get_context_loss_count)
1914                 context_loss = host->pdata->get_context_loss_count(host->dev);
1915
1916         seq_printf(s, "mmc%d:\n"
1917                         " enabled:\t%d\n"
1918                         " dpm_state:\t%d\n"
1919                         " nesting_cnt:\t%d\n"
1920                         " ctx_loss:\t%d:%d\n"
1921                         "\nregs:\n",
1922                         mmc->index, mmc->enabled ? 1 : 0,
1923                         host->dpm_state, mmc->nesting_cnt,
1924                         host->context_loss, context_loss);
1925
1926         if (host->suspended) {
1927                 seq_printf(s, "host suspended, can't read registers\n");
1928                 return 0;
1929         }
1930
1931         pm_runtime_get_sync(host->dev);
1932
1933         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1934                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1935         seq_printf(s, "CON:\t\t0x%08x\n",
1936                         OMAP_HSMMC_READ(host->base, CON));
1937         seq_printf(s, "HCTL:\t\t0x%08x\n",
1938                         OMAP_HSMMC_READ(host->base, HCTL));
1939         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1940                         OMAP_HSMMC_READ(host->base, SYSCTL));
1941         seq_printf(s, "IE:\t\t0x%08x\n",
1942                         OMAP_HSMMC_READ(host->base, IE));
1943         seq_printf(s, "ISE:\t\t0x%08x\n",
1944                         OMAP_HSMMC_READ(host->base, ISE));
1945         seq_printf(s, "CAPA:\t\t0x%08x\n",
1946                         OMAP_HSMMC_READ(host->base, CAPA));
1947
1948         pm_runtime_mark_last_busy(host->dev);
1949         pm_runtime_put_autosuspend(host->dev);
1950
1951         return 0;
1952 }
1953
1954 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1955 {
1956         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1957 }
1958
1959 static const struct file_operations mmc_regs_fops = {
1960         .open           = omap_hsmmc_regs_open,
1961         .read           = seq_read,
1962         .llseek         = seq_lseek,
1963         .release        = single_release,
1964 };
1965
1966 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1967 {
1968         if (mmc->debugfs_root)
1969                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1970                         mmc, &mmc_regs_fops);
1971 }
1972
1973 #else
1974
1975 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1976 {
1977 }
1978
1979 #endif
1980
1981 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1982 {
1983         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1984         struct mmc_host *mmc;
1985         struct omap_hsmmc_host *host = NULL;
1986         struct resource *res;
1987         int ret, irq;
1988
1989         if (pdata == NULL) {
1990                 dev_err(&pdev->dev, "Platform Data is missing\n");
1991                 return -ENXIO;
1992         }
1993
1994         if (pdata->nr_slots == 0) {
1995                 dev_err(&pdev->dev, "No Slots\n");
1996                 return -ENXIO;
1997         }
1998
1999         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2000         irq = platform_get_irq(pdev, 0);
2001         if (res == NULL || irq < 0)
2002                 return -ENXIO;
2003
2004         res->start += pdata->reg_offset;
2005         res->end += pdata->reg_offset;
2006         res = request_mem_region(res->start, resource_size(res), pdev->name);
2007         if (res == NULL)
2008                 return -EBUSY;
2009
2010         ret = omap_hsmmc_gpio_init(pdata);
2011         if (ret)
2012                 goto err;
2013
2014         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2015         if (!mmc) {
2016                 ret = -ENOMEM;
2017                 goto err_alloc;
2018         }
2019
2020         host            = mmc_priv(mmc);
2021         host->mmc       = mmc;
2022         host->pdata     = pdata;
2023         host->dev       = &pdev->dev;
2024         host->use_dma   = 1;
2025         host->dev->dma_mask = &pdata->dma_mask;
2026         host->dma_ch    = -1;
2027         host->dma_ch_tx = -1;
2028         host->dma_ch_rx = -1;
2029         host->irq       = irq;
2030         host->id        = pdev->id;
2031         host->slot_id   = 0;
2032         host->mapbase   = res->start;
2033         host->base      = ioremap(host->mapbase, SZ_4K);
2034         host->power_mode = MMC_POWER_OFF;
2035         host->next_data.cookie = 1;
2036
2037         platform_set_drvdata(pdev, host);
2038
2039         mmc->ops        = &omap_hsmmc_ops;
2040
2041         /*
2042          * If regulator_disable can only put vcc_aux to sleep then there is
2043          * no off state.
2044          */
2045         if (mmc_slot(host).vcc_aux_disable_is_sleep)
2046                 mmc_slot(host).no_off = 1;
2047
2048         mmc->f_min      = OMAP_MMC_MIN_CLOCK;
2049         mmc->f_max      = OMAP_MMC_MAX_CLOCK;
2050
2051         spin_lock_init(&host->irq_lock);
2052
2053         host->fclk = clk_get(&pdev->dev, "fck");
2054         if (IS_ERR(host->fclk)) {
2055                 ret = PTR_ERR(host->fclk);
2056                 host->fclk = NULL;
2057                 goto err1;
2058         }
2059
2060         omap_hsmmc_context_save(host);
2061
2062         mmc->caps |= MMC_CAP_DISABLE;
2063
2064         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2065                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2066                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
2067         }
2068
2069         pm_runtime_enable(host->dev);
2070         pm_runtime_get_sync(host->dev);
2071         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2072         pm_runtime_use_autosuspend(host->dev);
2073
2074         if (cpu_is_omap2430()) {
2075                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2076                 /*
2077                  * MMC can still work without debounce clock.
2078                  */
2079                 if (IS_ERR(host->dbclk))
2080                         dev_warn(mmc_dev(host->mmc),
2081                                 "Failed to get debounce clock\n");
2082                 else
2083                         host->got_dbclk = 1;
2084
2085                 if (host->got_dbclk)
2086                         if (clk_enable(host->dbclk) != 0)
2087                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2088                                                         " clk failed\n");
2089         }
2090
2091         /* Since we do only SG emulation, we can have as many segs
2092          * as we want. */
2093         mmc->max_segs = 1024;
2094
2095         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2096         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2097         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2098         mmc->max_seg_size = mmc->max_req_size;
2099
2100         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2101                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2102
2103         mmc->caps |= mmc_slot(host).caps;
2104         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2105                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2106
2107         if (mmc_slot(host).nonremovable)
2108                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2109
2110         omap_hsmmc_conf_bus_power(host);
2111
2112         /* Select DMA lines */
2113         switch (host->id) {
2114         case OMAP_MMC1_DEVID:
2115                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2116                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2117                 break;
2118         case OMAP_MMC2_DEVID:
2119                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2120                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2121                 break;
2122         case OMAP_MMC3_DEVID:
2123                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2124                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2125                 break;
2126         case OMAP_MMC4_DEVID:
2127                 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2128                 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2129                 break;
2130         case OMAP_MMC5_DEVID:
2131                 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2132                 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2133                 break;
2134         default:
2135                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2136                 goto err_irq;
2137         }
2138
2139         /* Request IRQ for MMC operations */
2140         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
2141                         mmc_hostname(mmc), host);
2142         if (ret) {
2143                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2144                 goto err_irq;
2145         }
2146
2147         if (pdata->init != NULL) {
2148                 if (pdata->init(&pdev->dev) != 0) {
2149                         dev_dbg(mmc_dev(host->mmc),
2150                                 "Unable to configure MMC IRQs\n");
2151                         goto err_irq_cd_init;
2152                 }
2153         }
2154
2155         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2156                 ret = omap_hsmmc_reg_get(host);
2157                 if (ret)
2158                         goto err_reg;
2159                 host->use_reg = 1;
2160         }
2161
2162         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2163
2164         /* Request IRQ for card detect */
2165         if ((mmc_slot(host).card_detect_irq)) {
2166                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
2167                                            NULL,
2168                                            omap_hsmmc_detect,
2169                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2170                                            mmc_hostname(mmc), host);
2171                 if (ret) {
2172                         dev_dbg(mmc_dev(host->mmc),
2173                                 "Unable to grab MMC CD IRQ\n");
2174                         goto err_irq_cd;
2175                 }
2176                 pdata->suspend = omap_hsmmc_suspend_cdirq;
2177                 pdata->resume = omap_hsmmc_resume_cdirq;
2178         }
2179
2180         omap_hsmmc_disable_irq(host);
2181
2182         omap_hsmmc_protect_card(host);
2183
2184         mmc_add_host(mmc);
2185
2186         if (mmc_slot(host).name != NULL) {
2187                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2188                 if (ret < 0)
2189                         goto err_slot_name;
2190         }
2191         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2192                 ret = device_create_file(&mmc->class_dev,
2193                                         &dev_attr_cover_switch);
2194                 if (ret < 0)
2195                         goto err_slot_name;
2196         }
2197
2198         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2199                 ret = device_create_file(&mmc->class_dev, &dev_attr_unsafe_read);
2200
2201                 /* MMC_CAP2_NO_MULTI_READ makes it crawl, try a different workaround */
2202                 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
2203                 mmc->max_segs = 1;
2204                 mmc->f_max = 32000000;
2205         }
2206
2207         omap_hsmmc_debugfs(mmc);
2208         pm_runtime_mark_last_busy(host->dev);
2209         pm_runtime_put_autosuspend(host->dev);
2210
2211         return 0;
2212
2213 err_slot_name:
2214         mmc_remove_host(mmc);
2215         free_irq(mmc_slot(host).card_detect_irq, host);
2216 err_irq_cd:
2217         if (host->use_reg)
2218                 omap_hsmmc_reg_put(host);
2219 err_reg:
2220         if (host->pdata->cleanup)
2221                 host->pdata->cleanup(&pdev->dev);
2222 err_irq_cd_init:
2223         free_irq(host->irq, host);
2224 err_irq:
2225         pm_runtime_mark_last_busy(host->dev);
2226         pm_runtime_put_autosuspend(host->dev);
2227         clk_put(host->fclk);
2228         if (host->got_dbclk) {
2229                 clk_disable(host->dbclk);
2230                 clk_put(host->dbclk);
2231         }
2232 err1:
2233         iounmap(host->base);
2234         platform_set_drvdata(pdev, NULL);
2235         mmc_free_host(mmc);
2236 err_alloc:
2237         omap_hsmmc_gpio_free(pdata);
2238 err:
2239         release_mem_region(res->start, resource_size(res));
2240         return ret;
2241 }
2242
2243 static int omap_hsmmc_remove(struct platform_device *pdev)
2244 {
2245         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2246         struct resource *res;
2247
2248         if (host) {
2249                 pm_runtime_get_sync(host->dev);
2250                 mmc_remove_host(host->mmc);
2251                 if (host->use_reg)
2252                         omap_hsmmc_reg_put(host);
2253                 if (host->pdata->cleanup)
2254                         host->pdata->cleanup(&pdev->dev);
2255                 free_irq(host->irq, host);
2256                 if (mmc_slot(host).card_detect_irq)
2257                         free_irq(mmc_slot(host).card_detect_irq, host);
2258
2259                 pm_runtime_put_sync(host->dev);
2260                 pm_runtime_disable(host->dev);
2261                 clk_put(host->fclk);
2262                 if (host->got_dbclk) {
2263                         clk_disable(host->dbclk);
2264                         clk_put(host->dbclk);
2265                 }
2266
2267                 mmc_free_host(host->mmc);
2268                 iounmap(host->base);
2269                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2270         }
2271
2272         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2273         if (res)
2274                 release_mem_region(res->start, resource_size(res));
2275         platform_set_drvdata(pdev, NULL);
2276
2277         return 0;
2278 }
2279
2280 #ifdef CONFIG_PM
2281 static int omap_hsmmc_suspend(struct device *dev)
2282 {
2283         int ret = 0;
2284         struct platform_device *pdev = to_platform_device(dev);
2285         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2286
2287         if (host && host->suspended)
2288                 return 0;
2289
2290         if (host) {
2291                 pm_runtime_get_sync(host->dev);
2292                 host->suspended = 1;
2293                 if (host->pdata->suspend) {
2294                         ret = host->pdata->suspend(&pdev->dev,
2295                                                         host->slot_id);
2296                         if (ret) {
2297                                 dev_dbg(mmc_dev(host->mmc),
2298                                         "Unable to handle MMC board"
2299                                         " level suspend\n");
2300                                 host->suspended = 0;
2301                                 return ret;
2302                         }
2303                 }
2304                 ret = mmc_suspend_host(host->mmc);
2305
2306                 if (ret == 0) {
2307                         omap_hsmmc_disable_irq(host);
2308                         OMAP_HSMMC_WRITE(host->base, HCTL,
2309                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2310                         if (host->got_dbclk)
2311                                 clk_disable(host->dbclk);
2312                 } else {
2313                         host->suspended = 0;
2314                         if (host->pdata->resume) {
2315                                 if (host->pdata->resume(&pdev->dev, host->slot_id))
2316                                         dev_dbg(mmc_dev(host->mmc),
2317                                                 "Unmask interrupt failed\n");
2318                         }
2319                 }
2320                 pm_runtime_put_sync(host->dev);
2321         }
2322         return ret;
2323 }
2324
2325 /* Routine to resume the MMC device */
2326 static int omap_hsmmc_resume(struct device *dev)
2327 {
2328         int ret = 0;
2329         struct platform_device *pdev = to_platform_device(dev);
2330         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2331
2332         if (host && !host->suspended)
2333                 return 0;
2334
2335         if (host) {
2336                 pm_runtime_get_sync(host->dev);
2337
2338                 if (host->got_dbclk)
2339                         clk_enable(host->dbclk);
2340
2341                 omap_hsmmc_conf_bus_power(host);
2342
2343                 if (host->pdata->resume) {
2344                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2345                         if (ret)
2346                                 dev_dbg(mmc_dev(host->mmc),
2347                                         "Unmask interrupt failed\n");
2348                 }
2349
2350                 omap_hsmmc_protect_card(host);
2351
2352                 /* Notify the core to resume the host */
2353                 ret = mmc_resume_host(host->mmc);
2354                 if (ret == 0)
2355                         host->suspended = 0;
2356
2357                 pm_runtime_mark_last_busy(host->dev);
2358                 pm_runtime_put_autosuspend(host->dev);
2359         }
2360
2361         return ret;
2362
2363 }
2364
2365 #else
2366 #define omap_hsmmc_suspend      NULL
2367 #define omap_hsmmc_resume               NULL
2368 #endif
2369
2370 static int omap_hsmmc_runtime_suspend(struct device *dev)
2371 {
2372         struct omap_hsmmc_host *host;
2373
2374         host = platform_get_drvdata(to_platform_device(dev));
2375         omap_hsmmc_context_save(host);
2376
2377         omap_hsmmc_free_dma(host);
2378
2379         dev_dbg(mmc_dev(host->mmc), "disabled\n");
2380
2381         return 0;
2382 }
2383
2384 static int omap_hsmmc_runtime_resume(struct device *dev)
2385 {
2386         struct omap_hsmmc_host *host;
2387
2388         host = platform_get_drvdata(to_platform_device(dev));
2389         omap_hsmmc_context_restore(host);
2390         dev_dbg(mmc_dev(host->mmc), "enabled\n");
2391
2392         return 0;
2393 }
2394
2395 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2396         .suspend        = omap_hsmmc_suspend,
2397         .resume         = omap_hsmmc_resume,
2398         .runtime_suspend = omap_hsmmc_runtime_suspend,
2399         .runtime_resume = omap_hsmmc_runtime_resume,
2400 };
2401
2402 static struct platform_driver omap_hsmmc_driver = {
2403         .remove         = omap_hsmmc_remove,
2404         .driver         = {
2405                 .name = DRIVER_NAME,
2406                 .owner = THIS_MODULE,
2407                 .pm = &omap_hsmmc_dev_pm_ops,
2408         },
2409 };
2410
2411 static int __init omap_hsmmc_init(void)
2412 {
2413         /* Register the MMC driver */
2414         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2415 }
2416
2417 static void __exit omap_hsmmc_cleanup(void)
2418 {
2419         /* Unregister MMC driver */
2420         platform_driver_unregister(&omap_hsmmc_driver);
2421 }
2422
2423 module_init(omap_hsmmc_init);
2424 module_exit(omap_hsmmc_cleanup);
2425
2426 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2427 MODULE_LICENSE("GPL");
2428 MODULE_ALIAS("platform:" DRIVER_NAME);
2429 MODULE_AUTHOR("Texas Instruments Inc");