drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/core.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/io.h>
  33 #include <linux/semaphore.h>
  34 #include <linux/gpio.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/pm_runtime.h>
  37 #include <plat/dma.h>
  38 #include <mach/hardware.h>
  39 #include <plat/board.h>
  40 #include <plat/mmc.h>
  41 #include <plat/cpu.h>
  42
  43 /* OMAP HSMMC Host Controller Registers */
  44 #define OMAP_HSMMC_SYSCONFIG    0x0010
  45 #define OMAP_HSMMC_SYSSTATUS    0x0014
  46 #define OMAP_HSMMC_CON          0x002C
  47 #define OMAP_HSMMC_BLK          0x0104
  48 #define OMAP_HSMMC_ARG          0x0108
  49 #define OMAP_HSMMC_CMD          0x010C
  50 #define OMAP_HSMMC_RSP10        0x0110
  51 #define OMAP_HSMMC_RSP32        0x0114
  52 #define OMAP_HSMMC_RSP54        0x0118
  53 #define OMAP_HSMMC_RSP76        0x011C
  54 #define OMAP_HSMMC_DATA         0x0120
  55 #define OMAP_HSMMC_HCTL         0x0128
  56 #define OMAP_HSMMC_SYSCTL       0x012C
  57 #define OMAP_HSMMC_STAT         0x0130
  58 #define OMAP_HSMMC_IE           0x0134
  59 #define OMAP_HSMMC_ISE          0x0138
  60 #define OMAP_HSMMC_CAPA         0x0140
  61
  62 #define VS18                    (1 << 26)
  63 #define VS30                    (1 << 25)
  64 #define SDVS18                  (0x5 << 9)
  65 #define SDVS30                  (0x6 << 9)
  66 #define SDVS33                  (0x7 << 9)
  67 #define SDVS_MASK               0x00000E00
  68 #define SDVSCLR                 0xFFFFF1FF
  69 #define SDVSDET                 0x00000400
  70 #define AUTOIDLE                0x1
  71 #define SDBP                    (1 << 8)
  72 #define DTO                     0xe
  73 #define ICE                     0x1
  74 #define ICS                     0x2
  75 #define CEN                     (1 << 2)
  76 #define CLKD_MASK               0x0000FFC0
  77 #define CLKD_SHIFT              6
  78 #define DTO_MASK                0x000F0000
  79 #define DTO_SHIFT               16
  80 #define INT_EN_MASK             0x307F0033
  81 #define BWR_ENABLE              (1 << 4)
  82 #define BRR_ENABLE              (1 << 5)
  83 #define DTO_ENABLE              (1 << 20)
  84 #define INIT_STREAM             (1 << 1)
  85 #define DP_SELECT               (1 << 21)
  86 #define DDIR                    (1 << 4)
  87 #define DMA_EN                  0x1
  88 #define MSBS                    (1 << 5)
  89 #define BCE                     (1 << 1)
  90 #define FOUR_BIT                (1 << 1)
  91 #define DW8                     (1 << 5)
  92 #define CC                      0x1
  93 #define TC                      0x02
  94 #define OD                      0x1
  95 #define ERR                     (1 << 15)
  96 #define CMD_TIMEOUT             (1 << 16)
  97 #define DATA_TIMEOUT            (1 << 20)
  98 #define CMD_CRC                 (1 << 17)
  99 #define DATA_CRC                (1 << 21)
 100 #define CARD_ERR                (1 << 28)
 101 #define STAT_CLEAR              0xFFFFFFFF
 102 #define INIT_STREAM_CMD         0x00000000
 103 #define DUAL_VOLT_OCR_BIT       7
 104 #define SRC                     (1 << 25)
 105 #define SRD                     (1 << 26)
 106 #define SOFTRESET               (1 << 1)
 107 #define RESETDONE               (1 << 0)
 108
 109 /*
 110  * FIXME: Most likely all the data using these _DEVID defines should come
 111  * from the platform_data, or implemented in controller and slot specific
 112  * functions.
 113  */
 114 #define OMAP_MMC1_DEVID         0
 115 #define OMAP_MMC2_DEVID         1
 116 #define OMAP_MMC3_DEVID         2
 117 #define OMAP_MMC4_DEVID         3
 118 #define OMAP_MMC5_DEVID         4
 119
 120 #define MMC_AUTOSUSPEND_DELAY   100
 121 #define MMC_TIMEOUT_MS          20
 122 #define OMAP_MMC_MASTER_CLOCK   96000000
 123 #define DRIVER_NAME             "omap_hsmmc"
 124
 125 /*
 126  * One controller can have multiple slots, like on some omap boards using
 127  * omap.c controller driver. Luckily this is not currently done on any known
 128  * omap_hsmmc.c device.
 129  */
 130 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 131
 132 /*
 133  * MMC Host controller read/write API's
 134  */
 135 #define OMAP_HSMMC_READ(base, reg)      \
 136         __raw_readl((base) + OMAP_HSMMC_##reg)
 137
 138 #define OMAP_HSMMC_WRITE(base, reg, val) \
 139         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 140
 141 struct omap_hsmmc_next {
 142         unsigned int    dma_len;
 143         s32             cookie;
 144 };
 145
 146 struct omap_hsmmc_host {
 147         struct  device          *dev;
 148         struct  mmc_host        *mmc;
 149         struct  mmc_request     *mrq;
 150         struct  mmc_command     *cmd;
 151         struct  mmc_data        *data;
 152         struct  clk             *fclk;
 153         struct  clk             *dbclk;
 154         /*
 155          * vcc == configured supply
 156          * vcc_aux == optional
 157          *   -  MMC1, supply for DAT4..DAT7
 158          *   -  MMC2/MMC2, external level shifter voltage supply, for
 159          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 160          */
 161         struct  regulator       *vcc;
 162         struct  regulator       *vcc_aux;
 163         struct  work_struct     mmc_carddetect_work;
 164         void    __iomem         *base;
 165         resource_size_t         mapbase;
 166         spinlock_t              irq_lock; /* Prevent races with irq handler */
 167         unsigned int            id;
 168         unsigned int            dma_len;
 169         unsigned int            dma_sg_idx;
 170         unsigned char           bus_mode;
 171         unsigned char           power_mode;
 172         u32                     *buffer;
 173         u32                     bytesleft;
 174         int                     suspended;
 175         int                     irq;
 176         int                     use_dma, dma_ch;
 177         int                     dma_line_tx, dma_line_rx;
 178         int                     slot_id;
 179         int                     got_dbclk;
 180         int                     response_busy;
 181         int                     context_loss;
 182         int                     dpm_state;
 183         int                     vdd;
 184         int                     protect_card;
 185         int                     reqs_blocked;
 186         int                     use_reg;
 187         int                     req_in_progress;
 188         struct omap_hsmmc_next  next_data;
 189
 190         struct  omap_mmc_platform_data  *pdata;
 191 };
 192
 193 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 194 {
 195         struct omap_mmc_platform_data *mmc = dev->platform_data;
 196
 197         /* NOTE: assumes card detect signal is active-low */
 198         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 199 }
 200
 201 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 202 {
 203         struct omap_mmc_platform_data *mmc = dev->platform_data;
 204
 205         /* NOTE: assumes write protect signal is active-high */
 206         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 207 }
 208
 209 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 210 {
 211         struct omap_mmc_platform_data *mmc = dev->platform_data;
 212
 213         /* NOTE: assumes card detect signal is active-low */
 214         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 215 }
 216
 217 #ifdef CONFIG_PM
 218
 219 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 220 {
 221         struct omap_mmc_platform_data *mmc = dev->platform_data;
 222
 223         disable_irq(mmc->slots[0].card_detect_irq);
 224         return 0;
 225 }
 226
 227 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 228 {
 229         struct omap_mmc_platform_data *mmc = dev->platform_data;
 230
 231         enable_irq(mmc->slots[0].card_detect_irq);
 232         return 0;
 233 }
 234
 235 #else
 236
 237 #define omap_hsmmc_suspend_cdirq        NULL
 238 #define omap_hsmmc_resume_cdirq         NULL
 239
 240 #endif
 241
 242 #ifdef CONFIG_REGULATOR
 243
 244 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
 245                                   int vdd)
 246 {
 247         struct omap_hsmmc_host *host =
 248                 platform_get_drvdata(to_platform_device(dev));
 249         int ret;
 250
 251         if (mmc_slot(host).before_set_reg)
 252                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 253
 254         if (power_on)
 255                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 256         else
 257                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
 258
 259         if (mmc_slot(host).after_set_reg)
 260                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 261
 262         return ret;
 263 }
 264
 265 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
 266                                    int vdd)
 267 {
 268         struct omap_hsmmc_host *host =
 269                 platform_get_drvdata(to_platform_device(dev));
 270         int ret = 0;
 271
 272         /*
 273          * If we don't see a Vcc regulator, assume it's a fixed
 274          * voltage always-on regulator.
 275          */
 276         if (!host->vcc)
 277                 return 0;
 278
 279         if (mmc_slot(host).before_set_reg)
 280                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 281
 282         /*
 283          * Assume Vcc regulator is used only to power the card ... OMAP
 284          * VDDS is used to power the pins, optionally with a transceiver to
 285          * support cards using voltages other than VDDS (1.8V nominal).  When a
 286          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 287          *
 288          * In some cases this regulator won't support enable/disable;
 289          * e.g. it's a fixed rail for a WLAN chip.
 290          *
 291          * In other cases vcc_aux switches interface power.  Example, for
 292          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 293          * chips/cards need an interface voltage rail too.
 294          */
 295         if (power_on) {
 296                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 297                 /* Enable interface voltage rail, if needed */
 298                 if (ret == 0 && host->vcc_aux) {
 299                         ret = regulator_enable(host->vcc_aux);
 300                         if (ret < 0)
 301                                 ret = mmc_regulator_set_ocr(host->mmc,
 302                                                         host->vcc, 0);
 303                 }
 304         } else {
 305                 /* Shut down the rail */
 306                 if (host->vcc_aux)
 307                         ret = regulator_disable(host->vcc_aux);
 308                 if (!ret) {
 309                         /* Then proceed to shut down the local regulator */
 310                         ret = mmc_regulator_set_ocr(host->mmc,
 311                                                 host->vcc, 0);
 312                 }
 313         }
 314
 315         if (mmc_slot(host).after_set_reg)
 316                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 317
 318         return ret;
 319 }
 320
 321 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
 322                                         int vdd)
 323 {
 324         return 0;
 325 }
 326
 327 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
 328                                   int vdd, int cardsleep)
 329 {
 330         struct omap_hsmmc_host *host =
 331                 platform_get_drvdata(to_platform_device(dev));
 332         int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 333
 334         return regulator_set_mode(host->vcc, mode);
 335 }
 336
 337 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
 338                                    int vdd, int cardsleep)
 339 {
 340         struct omap_hsmmc_host *host =
 341                 platform_get_drvdata(to_platform_device(dev));
 342         int err, mode;
 343
 344         /*
 345          * If we don't see a Vcc regulator, assume it's a fixed
 346          * voltage always-on regulator.
 347          */
 348         if (!host->vcc)
 349                 return 0;
 350
 351         mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
 352
 353         if (!host->vcc_aux)
 354                 return regulator_set_mode(host->vcc, mode);
 355
 356         if (cardsleep) {
 357                 /* VCC can be turned off if card is asleep */
 358                 if (sleep)
 359                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
 360                 else
 361                         err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 362         } else
 363                 err = regulator_set_mode(host->vcc, mode);
 364         if (err)
 365                 return err;
 366
 367         if (!mmc_slot(host).vcc_aux_disable_is_sleep)
 368                 return regulator_set_mode(host->vcc_aux, mode);
 369
 370         if (sleep)
 371                 return regulator_disable(host->vcc_aux);
 372         else
 373                 return regulator_enable(host->vcc_aux);
 374 }
 375
 376 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
 377                                         int vdd, int cardsleep)
 378 {
 379         return 0;
 380 }
 381
 382 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 383 {
 384         struct regulator *reg;
 385         int ret = 0;
 386         int ocr_value = 0;
 387
 388         switch (host->id) {
 389         case OMAP_MMC1_DEVID:
 390                 /* On-chip level shifting via PBIAS0/PBIAS1 */
 391                 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
 392                 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
 393                 break;
 394         case OMAP_MMC2_DEVID:
 395         case OMAP_MMC3_DEVID:
 396         case OMAP_MMC5_DEVID:
 397                 /* Off-chip level shifting, or none */
 398                 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
 399                 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
 400                 break;
 401         case OMAP_MMC4_DEVID:
 402                 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
 403                 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
 404         default:
 405                 pr_err("MMC%d configuration not supported!\n", host->id);
 406                 return -EINVAL;
 407         }
 408
 409         reg = regulator_get(host->dev, "vmmc");
 410         if (IS_ERR(reg)) {
 411                 dev_dbg(host->dev, "vmmc regulator missing\n");
 412                 /*
 413                 * HACK: until fixed.c regulator is usable,
 414                 * we don't require a main regulator
 415                 * for MMC2 or MMC3
 416                 */
 417                 if (host->id == OMAP_MMC1_DEVID) {
 418                         ret = PTR_ERR(reg);
 419                         goto err;
 420                 }
 421         } else {
 422                 host->vcc = reg;
 423                 ocr_value = mmc_regulator_get_ocrmask(reg);
 424                 if (!mmc_slot(host).ocr_mask) {
 425                         mmc_slot(host).ocr_mask = ocr_value;
 426                 } else {
 427                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 428                                 pr_err("MMC%d ocrmask %x is not supported\n",
 429                                         host->id, mmc_slot(host).ocr_mask);
 430                                 mmc_slot(host).ocr_mask = 0;
 431                                 return -EINVAL;
 432                         }
 433                 }
 434
 435                 /* Allow an aux regulator */
 436                 reg = regulator_get(host->dev, "vmmc_aux");
 437                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 438
 439                 /* For eMMC do not power off when not in sleep state */
 440                 if (mmc_slot(host).no_regulator_off_init)
 441                         return 0;
 442                 /*
 443                 * UGLY HACK:  workaround regulator framework bugs.
 444                 * When the bootloader leaves a supply active, it's
 445                 * initialized with zero usecount ... and we can't
 446                 * disable it without first enabling it.  Until the
 447                 * framework is fixed, we need a workaround like this
 448                 * (which is safe for MMC, but not in general).
 449                 */
 450                 if (regulator_is_enabled(host->vcc) > 0) {
 451                         regulator_enable(host->vcc);
 452                         regulator_disable(host->vcc);
 453                 }
 454                 if (host->vcc_aux) {
 455                         if (regulator_is_enabled(reg) > 0) {
 456                                 regulator_enable(reg);
 457                                 regulator_disable(reg);
 458                         }
 459                 }
 460         }
 461
 462         return 0;
 463
 464 err:
 465         mmc_slot(host).set_power = NULL;
 466         mmc_slot(host).set_sleep = NULL;
 467         return ret;
 468 }
 469
 470 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 471 {
 472         regulator_put(host->vcc);
 473         regulator_put(host->vcc_aux);
 474         mmc_slot(host).set_power = NULL;
 475         mmc_slot(host).set_sleep = NULL;
 476 }
 477
 478 static inline int omap_hsmmc_have_reg(void)
 479 {
 480         return 1;
 481 }
 482
 483 #else
 484
 485 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 486 {
 487         return -EINVAL;
 488 }
 489
 490 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 491 {
 492 }
 493
 494 static inline int omap_hsmmc_have_reg(void)
 495 {
 496         return 0;
 497 }
 498
 499 #endif
 500
 501 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 502 {
 503         int ret;
 504
 505         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 506                 if (pdata->slots[0].cover)
 507                         pdata->slots[0].get_cover_state =
 508                                         omap_hsmmc_get_cover_state;
 509                 else
 510                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 511                 pdata->slots[0].card_detect_irq =
 512                                 gpio_to_irq(pdata->slots[0].switch_pin);
 513                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 514                 if (ret)
 515                         return ret;
 516                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 517                 if (ret)
 518                         goto err_free_sp;
 519         } else
 520                 pdata->slots[0].switch_pin = -EINVAL;
 521
 522         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 523                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 524                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 525                 if (ret)
 526                         goto err_free_cd;
 527                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 528                 if (ret)
 529                         goto err_free_wp;
 530         } else
 531                 pdata->slots[0].gpio_wp = -EINVAL;
 532
 533         return 0;
 534
 535 err_free_wp:
 536         gpio_free(pdata->slots[0].gpio_wp);
 537 err_free_cd:
 538         if (gpio_is_valid(pdata->slots[0].switch_pin))
 539 err_free_sp:
 540                 gpio_free(pdata->slots[0].switch_pin);
 541         return ret;
 542 }
 543
 544 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 545 {
 546         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 547                 gpio_free(pdata->slots[0].gpio_wp);
 548         if (gpio_is_valid(pdata->slots[0].switch_pin))
 549                 gpio_free(pdata->slots[0].switch_pin);
 550 }
 551
 552 /*
 553  * Stop clock to the card
 554  */
 555 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 556 {
 557         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 558                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 559         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 560                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 561 }
 562
 563 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 564                                   struct mmc_command *cmd)
 565 {
 566         unsigned int irq_mask;
 567
 568         if (host->use_dma)
 569                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 570         else
 571                 irq_mask = INT_EN_MASK;
 572
 573         /* Disable timeout for erases */
 574         if (cmd->opcode == MMC_ERASE)
 575                 irq_mask &= ~DTO_ENABLE;
 576
 577         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 578         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 579         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 580 }
 581
 582 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 583 {
 584         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 585         OMAP_HSMMC_WRITE(host->base, IE, 0);
 586         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 587 }
 588
 589 #ifdef CONFIG_PM
 590
 591 /*
 592  * Restore the MMC host context, if it was lost as result of a
 593  * power state change.
 594  */
 595 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 596 {
 597         struct mmc_ios *ios = &host->mmc->ios;
 598         struct omap_mmc_platform_data *pdata = host->pdata;
 599         int context_loss = 0;
 600         u32 hctl, capa, con;
 601         u16 dsor = 0;
 602         unsigned long timeout;
 603
 604         if (pdata->get_context_loss_count) {
 605                 context_loss = pdata->get_context_loss_count(host->dev);
 606                 if (context_loss < 0)
 607                         return 1;
 608         }
 609
 610         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 611                 context_loss == host->context_loss ? "not " : "");
 612         if (host->context_loss == context_loss)
 613                 return 1;
 614
 615         /* Wait for hardware reset */
 616         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 617         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 618                 && time_before(jiffies, timeout))
 619                 ;
 620
 621         /* Do software reset */
 622         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 623         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 624         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 625                 && time_before(jiffies, timeout))
 626                 ;
 627
 628         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 629                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 630
 631         if (host->id == OMAP_MMC1_DEVID) {
 632                 if (host->power_mode != MMC_POWER_OFF &&
 633                     (1 << ios->vdd) <= MMC_VDD_23_24)
 634                         hctl = SDVS18;
 635                 else
 636                         hctl = SDVS30;
 637                 capa = VS30 | VS18;
 638         } else {
 639                 hctl = SDVS18;
 640                 capa = VS18;
 641         }
 642
 643         OMAP_HSMMC_WRITE(host->base, HCTL,
 644                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 645
 646         OMAP_HSMMC_WRITE(host->base, CAPA,
 647                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 648
 649         OMAP_HSMMC_WRITE(host->base, HCTL,
 650                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 651
 652         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 653         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 654                 && time_before(jiffies, timeout))
 655                 ;
 656
 657         omap_hsmmc_disable_irq(host);
 658
 659         /* Do not initialize card-specific things if the power is off */
 660         if (host->power_mode == MMC_POWER_OFF)
 661                 goto out;
 662
 663         con = OMAP_HSMMC_READ(host->base, CON);
 664         switch (ios->bus_width) {
 665         case MMC_BUS_WIDTH_8:
 666                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 667                 break;
 668         case MMC_BUS_WIDTH_4:
 669                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 670                 OMAP_HSMMC_WRITE(host->base, HCTL,
 671                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 672                 break;
 673         case MMC_BUS_WIDTH_1:
 674                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 675                 OMAP_HSMMC_WRITE(host->base, HCTL,
 676                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 677                 break;
 678         }
 679
 680         if (ios->clock) {
 681                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 682                 if (dsor < 1)
 683                         dsor = 1;
 684
 685                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 686                         dsor++;
 687
 688                 if (dsor > 250)
 689                         dsor = 250;
 690         }
 691
 692         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 693                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 694         OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
 695         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 696                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 697
 698         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 699         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 700                 && time_before(jiffies, timeout))
 701                 ;
 702
 703         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 704                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 705
 706         con = OMAP_HSMMC_READ(host->base, CON);
 707         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 708                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 709         else
 710                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 711 out:
 712         host->context_loss = context_loss;
 713
 714         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 715         return 0;
 716 }
 717
 718 /*
 719  * Save the MMC host context (store the number of power state changes so far).
 720  */
 721 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 722 {
 723         struct omap_mmc_platform_data *pdata = host->pdata;
 724         int context_loss;
 725
 726         if (pdata->get_context_loss_count) {
 727                 context_loss = pdata->get_context_loss_count(host->dev);
 728                 if (context_loss < 0)
 729                         return;
 730                 host->context_loss = context_loss;
 731         }
 732 }
 733
 734 #else
 735
 736 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 737 {
 738         return 0;
 739 }
 740
 741 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 742 {
 743 }
 744
 745 #endif
 746
 747 /*
 748  * Send init stream sequence to card
 749  * before sending IDLE command
 750  */
 751 static void send_init_stream(struct omap_hsmmc_host *host)
 752 {
 753         int reg = 0;
 754         unsigned long timeout;
 755
 756         if (host->protect_card)
 757                 return;
 758
 759         disable_irq(host->irq);
 760
 761         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 762         OMAP_HSMMC_WRITE(host->base, CON,
 763                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 764         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 765
 766         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 767         while ((reg != CC) && time_before(jiffies, timeout))
 768                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 769
 770         OMAP_HSMMC_WRITE(host->base, CON,
 771                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 772
 773         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 774         OMAP_HSMMC_READ(host->base, STAT);
 775
 776         enable_irq(host->irq);
 777 }
 778
 779 static inline
 780 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 781 {
 782         int r = 1;
 783
 784         if (mmc_slot(host).get_cover_state)
 785                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 786         return r;
 787 }
 788
 789 static ssize_t
 790 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 791                            char *buf)
 792 {
 793         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 794         struct omap_hsmmc_host *host = mmc_priv(mmc);
 795
 796         return sprintf(buf, "%s\n",
 797                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 798 }
 799
 800 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 801
 802 static ssize_t
 803 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 804                         char *buf)
 805 {
 806         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 807         struct omap_hsmmc_host *host = mmc_priv(mmc);
 808
 809         return sprintf(buf, "%s\n", mmc_slot(host).name);
 810 }
 811
 812 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 813
 814 /*
 815  * Configure the response type and send the cmd.
 816  */
 817 static void
 818 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 819         struct mmc_data *data)
 820 {
 821         int cmdreg = 0, resptype = 0, cmdtype = 0;
 822
 823         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 824                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 825         host->cmd = cmd;
 826
 827         omap_hsmmc_enable_irq(host, cmd);
 828
 829         host->response_busy = 0;
 830         if (cmd->flags & MMC_RSP_PRESENT) {
 831                 if (cmd->flags & MMC_RSP_136)
 832                         resptype = 1;
 833                 else if (cmd->flags & MMC_RSP_BUSY) {
 834                         resptype = 3;
 835                         host->response_busy = 1;
 836                 } else
 837                         resptype = 2;
 838         }
 839
 840         /*
 841          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 842          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 843          * a val of 0x3, rest 0x0.
 844          */
 845         if (cmd == host->mrq->stop)
 846                 cmdtype = 0x3;
 847
 848         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 849
 850         if (data) {
 851                 cmdreg |= DP_SELECT | MSBS | BCE;
 852                 if (data->flags & MMC_DATA_READ)
 853                         cmdreg |= DDIR;
 854                 else
 855                         cmdreg &= ~(DDIR);
 856         }
 857
 858         if (host->use_dma)
 859                 cmdreg |= DMA_EN;
 860
 861         host->req_in_progress = 1;
 862
 863         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 864         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 865 }
 866
 867 static int
 868 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 869 {
 870         if (data->flags & MMC_DATA_WRITE)
 871                 return DMA_TO_DEVICE;
 872         else
 873                 return DMA_FROM_DEVICE;
 874 }
 875
 876 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 877 {
 878         int dma_ch;
 879
 880         spin_lock(&host->irq_lock);
 881         host->req_in_progress = 0;
 882         dma_ch = host->dma_ch;
 883         spin_unlock(&host->irq_lock);
 884
 885         omap_hsmmc_disable_irq(host);
 886         /* Do not complete the request if DMA is still in progress */
 887         if (mrq->data && host->use_dma && dma_ch != -1)
 888                 return;
 889         host->mrq = NULL;
 890         mmc_request_done(host->mmc, mrq);
 891 }
 892
 893 /*
 894  * Notify the transfer complete to MMC core
 895  */
 896 static void
 897 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 898 {
 899         if (!data) {
 900                 struct mmc_request *mrq = host->mrq;
 901
 902                 /* TC before CC from CMD6 - don't know why, but it happens */
 903                 if (host->cmd && host->cmd->opcode == 6 &&
 904                     host->response_busy) {
 905                         host->response_busy = 0;
 906                         return;
 907                 }
 908
 909                 omap_hsmmc_request_done(host, mrq);
 910                 return;
 911         }
 912
 913         host->data = NULL;
 914
 915         if (!data->error)
 916                 data->bytes_xfered += data->blocks * (data->blksz);
 917         else
 918                 data->bytes_xfered = 0;
 919
 920         if (!data->stop) {
 921                 omap_hsmmc_request_done(host, data->mrq);
 922                 return;
 923         }
 924         omap_hsmmc_start_command(host, data->stop, NULL);
 925 }
 926
 927 /*
 928  * Notify the core about command completion
 929  */
 930 static void
 931 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 932 {
 933         host->cmd = NULL;
 934
 935         if (cmd->flags & MMC_RSP_PRESENT) {
 936                 if (cmd->flags & MMC_RSP_136) {
 937                         /* response type 2 */
 938                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 939                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 940                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 941                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 942                 } else {
 943                         /* response types 1, 1b, 3, 4, 5, 6 */
 944                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 945                 }
 946         }
 947         if ((host->data == NULL && !host->response_busy) || cmd->error)
 948                 omap_hsmmc_request_done(host, cmd->mrq);
 949 }
 950
 951 /*
 952  * DMA clean up for command errors
 953  */
 954 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 955 {
 956         int dma_ch;
 957
 958         host->data->error = errno;
 959
 960         spin_lock(&host->irq_lock);
 961         dma_ch = host->dma_ch;
 962         host->dma_ch = -1;
 963         spin_unlock(&host->irq_lock);
 964
 965         if (host->use_dma && dma_ch != -1) {
 966                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
 967                         host->data->sg_len,
 968                         omap_hsmmc_get_dma_dir(host, host->data));
 969                 omap_free_dma(dma_ch);
 970         }
 971         host->data = NULL;
 972 }
 973
 974 /*
 975  * Readable error output
 976  */
 977 #ifdef CONFIG_MMC_DEBUG
 978 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 979 {
 980         /* --- means reserved bit without definition at documentation */
 981         static const char *omap_hsmmc_status_bits[] = {
 982                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 983                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 984                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 985                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 986         };
 987         char res[256];
 988         char *buf = res;
 989         int len, i;
 990
 991         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 992         buf += len;
 993
 994         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 995                 if (status & (1 << i)) {
 996                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 997                         buf += len;
 998                 }
 999
1000         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1001 }
1002 #else
1003 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1004                                              u32 status)
1005 {
1006 }
1007 #endif  /* CONFIG_MMC_DEBUG */
1008
1009 /*
1010  * MMC controller internal state machines reset
1011  *
1012  * Used to reset command or data internal state machines, using respectively
1013  *  SRC or SRD bit of SYSCTL register
1014  * Can be called from interrupt context
1015  */
1016 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1017                                                    unsigned long bit)
1018 {
1019         unsigned long i = 0;
1020         unsigned long limit = (loops_per_jiffy *
1021                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
1022
1023         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1024                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1025
1026         /*
1027          * OMAP4 ES2 and greater has an updated reset logic.
1028          * Monitor a 0->1 transition first
1029          */
1030         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1031                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1032                                         && (i++ < limit))
1033                         cpu_relax();
1034         }
1035         i = 0;
1036
1037         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1038                 (i++ < limit))
1039                 cpu_relax();
1040
1041         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1042                 dev_err(mmc_dev(host->mmc),
1043                         "Timeout waiting on controller reset in %s\n",
1044                         __func__);
1045 }
1046
1047 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1048 {
1049         struct mmc_data *data;
1050         int end_cmd = 0, end_trans = 0;
1051
1052         if (!host->req_in_progress) {
1053                 do {
1054                         OMAP_HSMMC_WRITE(host->base, STAT, status);
1055                         /* Flush posted write */
1056                         status = OMAP_HSMMC_READ(host->base, STAT);
1057                 } while (status & INT_EN_MASK);
1058                 return;
1059         }
1060
1061         data = host->data;
1062         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1063
1064         if (status & ERR) {
1065                 omap_hsmmc_dbg_report_irq(host, status);
1066                 if ((status & CMD_TIMEOUT) ||
1067                         (status & CMD_CRC)) {
1068                         if (host->cmd) {
1069                                 if (status & CMD_TIMEOUT) {
1070                                         omap_hsmmc_reset_controller_fsm(host,
1071                                                                         SRC);
1072                                         host->cmd->error = -ETIMEDOUT;
1073                                 } else {
1074                                         host->cmd->error = -EILSEQ;
1075                                 }
1076                                 end_cmd = 1;
1077                         }
1078                         if (host->data || host->response_busy) {
1079                                 if (host->data)
1080                                         omap_hsmmc_dma_cleanup(host,
1081                                                                 -ETIMEDOUT);
1082                                 host->response_busy = 0;
1083                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1084                         }
1085                 }
1086                 if ((status & DATA_TIMEOUT) ||
1087                         (status & DATA_CRC)) {
1088                         if (host->data || host->response_busy) {
1089                                 int err = (status & DATA_TIMEOUT) ?
1090                                                 -ETIMEDOUT : -EILSEQ;
1091
1092                                 if (host->data)
1093                                         omap_hsmmc_dma_cleanup(host, err);
1094                                 else
1095                                         host->mrq->cmd->error = err;
1096                                 host->response_busy = 0;
1097                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1098                                 end_trans = 1;
1099                         }
1100                 }
1101                 if (status & CARD_ERR) {
1102                         dev_dbg(mmc_dev(host->mmc),
1103                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1104                         if (host->cmd)
1105                                 end_cmd = 1;
1106                         if (host->data)
1107                                 end_trans = 1;
1108                 }
1109         }
1110
1111         OMAP_HSMMC_WRITE(host->base, STAT, status);
1112
1113         if (end_cmd || ((status & CC) && host->cmd))
1114                 omap_hsmmc_cmd_done(host, host->cmd);
1115         if ((end_trans || (status & TC)) && host->mrq)
1116                 omap_hsmmc_xfer_done(host, data);
1117 }
1118
1119 /*
1120  * MMC controller IRQ handler
1121  */
1122 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1123 {
1124         struct omap_hsmmc_host *host = dev_id;
1125         int status;
1126
1127         status = OMAP_HSMMC_READ(host->base, STAT);
1128         do {
1129                 omap_hsmmc_do_irq(host, status);
1130                 /* Flush posted write */
1131                 status = OMAP_HSMMC_READ(host->base, STAT);
1132         } while (status & INT_EN_MASK);
1133
1134         return IRQ_HANDLED;
1135 }
1136
1137 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1138 {
1139         unsigned long i;
1140
1141         OMAP_HSMMC_WRITE(host->base, HCTL,
1142                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1143         for (i = 0; i < loops_per_jiffy; i++) {
1144                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1145                         break;
1146                 cpu_relax();
1147         }
1148 }
1149
1150 /*
1151  * Switch MMC interface voltage ... only relevant for MMC1.
1152  *
1153  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1154  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1155  * Some chips, like eMMC ones, use internal transceivers.
1156  */
1157 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1158 {
1159         u32 reg_val = 0;
1160         int ret;
1161
1162         /* Disable the clocks */
1163         pm_runtime_put_sync(host->dev);
1164         if (host->got_dbclk)
1165                 clk_disable(host->dbclk);
1166
1167         /* Turn the power off */
1168         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1169
1170         /* Turn the power ON with given VDD 1.8 or 3.0v */
1171         if (!ret)
1172                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1173                                                vdd);
1174         pm_runtime_get_sync(host->dev);
1175         if (host->got_dbclk)
1176                 clk_enable(host->dbclk);
1177
1178         if (ret != 0)
1179                 goto err;
1180
1181         OMAP_HSMMC_WRITE(host->base, HCTL,
1182                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1183         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1184
1185         /*
1186          * If a MMC dual voltage card is detected, the set_ios fn calls
1187          * this fn with VDD bit set for 1.8V. Upon card removal from the
1188          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1189          *
1190          * Cope with a bit of slop in the range ... per data sheets:
1191          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1192          *    but recommended values are 1.71V to 1.89V
1193          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1194          *    but recommended values are 2.7V to 3.3V
1195          *
1196          * Board setup code shouldn't permit anything very out-of-range.
1197          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1198          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1199          */
1200         if ((1 << vdd) <= MMC_VDD_23_24)
1201                 reg_val |= SDVS18;
1202         else
1203                 reg_val |= SDVS30;
1204
1205         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1206         set_sd_bus_power(host);
1207
1208         return 0;
1209 err:
1210         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1211         return ret;
1212 }
1213
1214 /* Protect the card while the cover is open */
1215 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1216 {
1217         if (!mmc_slot(host).get_cover_state)
1218                 return;
1219
1220         host->reqs_blocked = 0;
1221         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1222                 if (host->protect_card) {
1223                         printk(KERN_INFO "%s: cover is closed, "
1224                                          "card is now accessible\n",
1225                                          mmc_hostname(host->mmc));
1226                         host->protect_card = 0;
1227                 }
1228         } else {
1229                 if (!host->protect_card) {
1230                         printk(KERN_INFO "%s: cover is open, "
1231                                          "card is now inaccessible\n",
1232                                          mmc_hostname(host->mmc));
1233                         host->protect_card = 1;
1234                 }
1235         }
1236 }
1237
1238 /*
1239  * Work Item to notify the core about card insertion/removal
1240  */
1241 static void omap_hsmmc_detect(struct work_struct *work)
1242 {
1243         struct omap_hsmmc_host *host =
1244                 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1245         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1246         int carddetect;
1247
1248         if (host->suspended)
1249                 return;
1250
1251         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1252
1253         if (slot->card_detect)
1254                 carddetect = slot->card_detect(host->dev, host->slot_id);
1255         else {
1256                 omap_hsmmc_protect_card(host);
1257                 carddetect = -ENOSYS;
1258         }
1259
1260         if (carddetect)
1261                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1262         else
1263                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1264 }
1265
1266 /*
1267  * ISR for handling card insertion and removal
1268  */
1269 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1270 {
1271         struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1272
1273         if (host->suspended)
1274                 return IRQ_HANDLED;
1275         schedule_work(&host->mmc_carddetect_work);
1276
1277         return IRQ_HANDLED;
1278 }
1279
1280 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1281                                      struct mmc_data *data)
1282 {
1283         int sync_dev;
1284
1285         if (data->flags & MMC_DATA_WRITE)
1286                 sync_dev = host->dma_line_tx;
1287         else
1288                 sync_dev = host->dma_line_rx;
1289         return sync_dev;
1290 }
1291
1292 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1293                                        struct mmc_data *data,
1294                                        struct scatterlist *sgl)
1295 {
1296         int blksz, nblk, dma_ch;
1297
1298         dma_ch = host->dma_ch;
1299         if (data->flags & MMC_DATA_WRITE) {
1300                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1301                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1302                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1303                         sg_dma_address(sgl), 0, 0);
1304         } else {
1305                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1306                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1307                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1308                         sg_dma_address(sgl), 0, 0);
1309         }
1310
1311         blksz = host->data->blksz;
1312         nblk = sg_dma_len(sgl) / blksz;
1313
1314         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1315                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1316                         omap_hsmmc_get_dma_sync_dev(host, data),
1317                         !(data->flags & MMC_DATA_WRITE));
1318
1319         omap_start_dma(dma_ch);
1320 }
1321
1322 /*
1323  * DMA call back function
1324  */
1325 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1326 {
1327         struct omap_hsmmc_host *host = cb_data;
1328         struct mmc_data *data = host->mrq->data;
1329         int dma_ch, req_in_progress;
1330
1331         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1332                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1333                         ch_status);
1334                 return;
1335         }
1336
1337         spin_lock(&host->irq_lock);
1338         if (host->dma_ch < 0) {
1339                 spin_unlock(&host->irq_lock);
1340                 return;
1341         }
1342
1343         host->dma_sg_idx++;
1344         if (host->dma_sg_idx < host->dma_len) {
1345                 /* Fire up the next transfer. */
1346                 omap_hsmmc_config_dma_params(host, data,
1347                                            data->sg + host->dma_sg_idx);
1348                 spin_unlock(&host->irq_lock);
1349                 return;
1350         }
1351
1352         if (!data->host_cookie)
1353                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1354                              omap_hsmmc_get_dma_dir(host, data));
1355
1356         req_in_progress = host->req_in_progress;
1357         dma_ch = host->dma_ch;
1358         host->dma_ch = -1;
1359         spin_unlock(&host->irq_lock);
1360
1361         omap_free_dma(dma_ch);
1362
1363         /* If DMA has finished after TC, complete the request */
1364         if (!req_in_progress) {
1365                 struct mmc_request *mrq = host->mrq;
1366
1367                 host->mrq = NULL;
1368                 mmc_request_done(host->mmc, mrq);
1369         }
1370 }
1371
1372 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1373                                        struct mmc_data *data,
1374                                        struct omap_hsmmc_next *next)
1375 {
1376         int dma_len;
1377
1378         if (!next && data->host_cookie &&
1379             data->host_cookie != host->next_data.cookie) {
1380                 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
1381                        " host->next_data.cookie %d\n",
1382                        __func__, data->host_cookie, host->next_data.cookie);
1383                 data->host_cookie = 0;
1384         }
1385
1386         /* Check if next job is already prepared */
1387         if (next ||
1388             (!next && data->host_cookie != host->next_data.cookie)) {
1389                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1390                                      data->sg_len,
1391                                      omap_hsmmc_get_dma_dir(host, data));
1392
1393         } else {
1394                 dma_len = host->next_data.dma_len;
1395                 host->next_data.dma_len = 0;
1396         }
1397
1398
1399         if (dma_len == 0)
1400                 return -EINVAL;
1401
1402         if (next) {
1403                 next->dma_len = dma_len;
1404                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1405         } else
1406                 host->dma_len = dma_len;
1407
1408         return 0;
1409 }
1410
1411 /*
1412  * Routine to configure and start DMA for the MMC card
1413  */
1414 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1415                                         struct mmc_request *req)
1416 {
1417         int dma_ch = 0, ret = 0, i;
1418         struct mmc_data *data = req->data;
1419
1420         /* Sanity check: all the SG entries must be aligned by block size. */
1421         for (i = 0; i < data->sg_len; i++) {
1422                 struct scatterlist *sgl;
1423
1424                 sgl = data->sg + i;
1425                 if (sgl->length % data->blksz)
1426                         return -EINVAL;
1427         }
1428         if ((data->blksz % 4) != 0)
1429                 /* REVISIT: The MMC buffer increments only when MSB is written.
1430                  * Return error for blksz which is non multiple of four.
1431                  */
1432                 return -EINVAL;
1433
1434         BUG_ON(host->dma_ch != -1);
1435
1436         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1437                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1438         if (ret != 0) {
1439                 dev_err(mmc_dev(host->mmc),
1440                         "%s: omap_request_dma() failed with %d\n",
1441                         mmc_hostname(host->mmc), ret);
1442                 return ret;
1443         }
1444         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1445         if (ret)
1446                 return ret;
1447
1448         host->dma_ch = dma_ch;
1449         host->dma_sg_idx = 0;
1450
1451         omap_hsmmc_config_dma_params(host, data, data->sg);
1452
1453         return 0;
1454 }
1455
1456 static void set_data_timeout(struct omap_hsmmc_host *host,
1457                              unsigned int timeout_ns,
1458                              unsigned int timeout_clks)
1459 {
1460         unsigned int timeout, cycle_ns;
1461         uint32_t reg, clkd, dto = 0;
1462
1463         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1464         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1465         if (clkd == 0)
1466                 clkd = 1;
1467
1468         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1469         timeout = timeout_ns / cycle_ns;
1470         timeout += timeout_clks;
1471         if (timeout) {
1472                 while ((timeout & 0x80000000) == 0) {
1473                         dto += 1;
1474                         timeout <<= 1;
1475                 }
1476                 dto = 31 - dto;
1477                 timeout <<= 1;
1478                 if (timeout && dto)
1479                         dto += 1;
1480                 if (dto >= 13)
1481                         dto -= 13;
1482                 else
1483                         dto = 0;
1484                 if (dto > 14)
1485                         dto = 14;
1486         }
1487
1488         reg &= ~DTO_MASK;
1489         reg |= dto << DTO_SHIFT;
1490         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1491 }
1492
1493 /*
1494  * Configure block length for MMC/SD cards and initiate the transfer.
1495  */
1496 static int
1497 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1498 {
1499         int ret;
1500         host->data = req->data;
1501
1502         if (req->data == NULL) {
1503                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1504                 /*
1505                  * Set an arbitrary 100ms data timeout for commands with
1506                  * busy signal.
1507                  */
1508                 if (req->cmd->flags & MMC_RSP_BUSY)
1509                         set_data_timeout(host, 100000000U, 0);
1510                 return 0;
1511         }
1512
1513         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1514                                         | (req->data->blocks << 16));
1515         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1516
1517         if (host->use_dma) {
1518                 ret = omap_hsmmc_start_dma_transfer(host, req);
1519                 if (ret != 0) {
1520                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1521                         return ret;
1522                 }
1523         }
1524         return 0;
1525 }
1526
1527 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1528                                 int err)
1529 {
1530         struct omap_hsmmc_host *host = mmc_priv(mmc);
1531         struct mmc_data *data = mrq->data;
1532
1533         if (host->use_dma) {
1534                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1535                              omap_hsmmc_get_dma_dir(host, data));
1536                 data->host_cookie = 0;
1537         }
1538 }
1539
1540 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1541                                bool is_first_req)
1542 {
1543         struct omap_hsmmc_host *host = mmc_priv(mmc);
1544
1545         if (mrq->data->host_cookie) {
1546                 mrq->data->host_cookie = 0;
1547                 return ;
1548         }
1549
1550         if (host->use_dma)
1551                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1552                                                 &host->next_data))
1553                         mrq->data->host_cookie = 0;
1554 }
1555
1556 /*
1557  * Request function. for read/write operation
1558  */
1559 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1560 {
1561         struct omap_hsmmc_host *host = mmc_priv(mmc);
1562         int err;
1563
1564         BUG_ON(host->req_in_progress);
1565         BUG_ON(host->dma_ch != -1);
1566         if (host->protect_card) {
1567                 if (host->reqs_blocked < 3) {
1568                         /*
1569                          * Ensure the controller is left in a consistent
1570                          * state by resetting the command and data state
1571                          * machines.
1572                          */
1573                         omap_hsmmc_reset_controller_fsm(host, SRD);
1574                         omap_hsmmc_reset_controller_fsm(host, SRC);
1575                         host->reqs_blocked += 1;
1576                 }
1577                 req->cmd->error = -EBADF;
1578                 if (req->data)
1579                         req->data->error = -EBADF;
1580                 req->cmd->retries = 0;
1581                 mmc_request_done(mmc, req);
1582                 return;
1583         } else if (host->reqs_blocked)
1584                 host->reqs_blocked = 0;
1585         WARN_ON(host->mrq != NULL);
1586         host->mrq = req;
1587         err = omap_hsmmc_prepare_data(host, req);
1588         if (err) {
1589                 req->cmd->error = err;
1590                 if (req->data)
1591                         req->data->error = err;
1592                 host->mrq = NULL;
1593                 mmc_request_done(mmc, req);
1594                 return;
1595         }
1596
1597         omap_hsmmc_start_command(host, req->cmd, req->data);
1598 }
1599
1600 /* Routine to configure clock values. Exposed API to core */
1601 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1602 {
1603         struct omap_hsmmc_host *host = mmc_priv(mmc);
1604         u16 dsor = 0;
1605         unsigned long regval;
1606         unsigned long timeout;
1607         u32 con;
1608         int do_send_init_stream = 0;
1609
1610         pm_runtime_get_sync(host->dev);
1611
1612         if (ios->power_mode != host->power_mode) {
1613                 switch (ios->power_mode) {
1614                 case MMC_POWER_OFF:
1615                         mmc_slot(host).set_power(host->dev, host->slot_id,
1616                                                  0, 0);
1617                         host->vdd = 0;
1618                         break;
1619                 case MMC_POWER_UP:
1620                         mmc_slot(host).set_power(host->dev, host->slot_id,
1621                                                  1, ios->vdd);
1622                         host->vdd = ios->vdd;
1623                         break;
1624                 case MMC_POWER_ON:
1625                         do_send_init_stream = 1;
1626                         break;
1627                 }
1628                 host->power_mode = ios->power_mode;
1629         }
1630
1631         /* FIXME: set registers based only on changes to ios */
1632
1633         con = OMAP_HSMMC_READ(host->base, CON);
1634         switch (mmc->ios.bus_width) {
1635         case MMC_BUS_WIDTH_8:
1636                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1637                 break;
1638         case MMC_BUS_WIDTH_4:
1639                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1640                 OMAP_HSMMC_WRITE(host->base, HCTL,
1641                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1642                 break;
1643         case MMC_BUS_WIDTH_1:
1644                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1645                 OMAP_HSMMC_WRITE(host->base, HCTL,
1646                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1647                 break;
1648         }
1649
1650         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1651                 /* Only MMC1 can interface at 3V without some flavor
1652                  * of external transceiver; but they all handle 1.8V.
1653                  */
1654                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1655                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1656                                 /*
1657                                  * The mmc_select_voltage fn of the core does
1658                                  * not seem to set the power_mode to
1659                                  * MMC_POWER_UP upon recalculating the voltage.
1660                                  * vdd 1.8v.
1661                                  */
1662                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1663                                 dev_dbg(mmc_dev(host->mmc),
1664                                                 "Switch operation failed\n");
1665                 }
1666         }
1667
1668         if (ios->clock) {
1669                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1670                 if (dsor < 1)
1671                         dsor = 1;
1672
1673                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1674                         dsor++;
1675
1676                 if (dsor > 250)
1677                         dsor = 250;
1678         }
1679         omap_hsmmc_stop_clock(host);
1680         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1681         regval = regval & ~(CLKD_MASK);
1682         regval = regval | (dsor << 6) | (DTO << 16);
1683         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1684         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1685                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1686
1687         /* Wait till the ICS bit is set */
1688         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1689         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1690                 && time_before(jiffies, timeout))
1691                 msleep(1);
1692
1693         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1694                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1695
1696         if (do_send_init_stream)
1697                 send_init_stream(host);
1698
1699         con = OMAP_HSMMC_READ(host->base, CON);
1700         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1701                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1702         else
1703                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1704
1705         pm_runtime_put_autosuspend(host->dev);
1706 }
1707
1708 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1709 {
1710         struct omap_hsmmc_host *host = mmc_priv(mmc);
1711
1712         if (!mmc_slot(host).card_detect)
1713                 return -ENOSYS;
1714         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1715 }
1716
1717 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1718 {
1719         struct omap_hsmmc_host *host = mmc_priv(mmc);
1720
1721         if (!mmc_slot(host).get_ro)
1722                 return -ENOSYS;
1723         return mmc_slot(host).get_ro(host->dev, 0);
1724 }
1725
1726 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1727 {
1728         struct omap_hsmmc_host *host = mmc_priv(mmc);
1729
1730         if (mmc_slot(host).init_card)
1731                 mmc_slot(host).init_card(card);
1732 }
1733
1734 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1735 {
1736         u32 hctl, capa, value;
1737
1738         /* Only MMC1 supports 3.0V */
1739         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1740                 hctl = SDVS30;
1741                 capa = VS30 | VS18;
1742         } else {
1743                 hctl = SDVS18;
1744                 capa = VS18;
1745         }
1746
1747         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1748         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1749
1750         value = OMAP_HSMMC_READ(host->base, CAPA);
1751         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1752
1753         /* Set the controller to AUTO IDLE mode */
1754         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1755         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1756
1757         /* Set SD bus power bit */
1758         set_sd_bus_power(host);
1759 }
1760
1761 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1762 {
1763         struct omap_hsmmc_host *host = mmc_priv(mmc);
1764
1765         pm_runtime_get_sync(host->dev);
1766
1767         return 0;
1768 }
1769
1770 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1771 {
1772         struct omap_hsmmc_host *host = mmc_priv(mmc);
1773
1774         pm_runtime_mark_last_busy(host->dev);
1775         pm_runtime_put_autosuspend(host->dev);
1776
1777         return 0;
1778 }
1779
1780 static const struct mmc_host_ops omap_hsmmc_ops = {
1781         .enable = omap_hsmmc_enable_fclk,
1782         .disable = omap_hsmmc_disable_fclk,
1783         .post_req = omap_hsmmc_post_req,
1784         .pre_req = omap_hsmmc_pre_req,
1785         .request = omap_hsmmc_request,
1786         .set_ios = omap_hsmmc_set_ios,
1787         .get_cd = omap_hsmmc_get_cd,
1788         .get_ro = omap_hsmmc_get_ro,
1789         .init_card = omap_hsmmc_init_card,
1790         /* NYET -- enable_sdio_irq */
1791 };
1792
1793 #ifdef CONFIG_DEBUG_FS
1794
1795 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1796 {
1797         struct mmc_host *mmc = s->private;
1798         struct omap_hsmmc_host *host = mmc_priv(mmc);
1799         int context_loss = 0;
1800
1801         if (host->pdata->get_context_loss_count)
1802                 context_loss = host->pdata->get_context_loss_count(host->dev);
1803
1804         seq_printf(s, "mmc%d:\n"
1805                         " enabled:\t%d\n"
1806                         " dpm_state:\t%d\n"
1807                         " nesting_cnt:\t%d\n"
1808                         " ctx_loss:\t%d:%d\n"
1809                         "\nregs:\n",
1810                         mmc->index, mmc->enabled ? 1 : 0,
1811                         host->dpm_state, mmc->nesting_cnt,
1812                         host->context_loss, context_loss);
1813
1814         if (host->suspended) {
1815                 seq_printf(s, "host suspended, can't read registers\n");
1816                 return 0;
1817         }
1818
1819         pm_runtime_get_sync(host->dev);
1820
1821         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1822                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1823         seq_printf(s, "CON:\t\t0x%08x\n",
1824                         OMAP_HSMMC_READ(host->base, CON));
1825         seq_printf(s, "HCTL:\t\t0x%08x\n",
1826                         OMAP_HSMMC_READ(host->base, HCTL));
1827         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1828                         OMAP_HSMMC_READ(host->base, SYSCTL));
1829         seq_printf(s, "IE:\t\t0x%08x\n",
1830                         OMAP_HSMMC_READ(host->base, IE));
1831         seq_printf(s, "ISE:\t\t0x%08x\n",
1832                         OMAP_HSMMC_READ(host->base, ISE));
1833         seq_printf(s, "CAPA:\t\t0x%08x\n",
1834                         OMAP_HSMMC_READ(host->base, CAPA));
1835
1836         pm_runtime_mark_last_busy(host->dev);
1837         pm_runtime_put_autosuspend(host->dev);
1838
1839         return 0;
1840 }
1841
1842 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1843 {
1844         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1845 }
1846
1847 static const struct file_operations mmc_regs_fops = {
1848         .open           = omap_hsmmc_regs_open,
1849         .read           = seq_read,
1850         .llseek         = seq_lseek,
1851         .release        = single_release,
1852 };
1853
1854 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1855 {
1856         if (mmc->debugfs_root)
1857                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1858                         mmc, &mmc_regs_fops);
1859 }
1860
1861 #else
1862
1863 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1864 {
1865 }
1866
1867 #endif
1868
1869 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1870 {
1871         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1872         struct mmc_host *mmc;
1873         struct omap_hsmmc_host *host = NULL;
1874         struct resource *res;
1875         int ret, irq;
1876
1877         if (pdata == NULL) {
1878                 dev_err(&pdev->dev, "Platform Data is missing\n");
1879                 return -ENXIO;
1880         }
1881
1882         if (pdata->nr_slots == 0) {
1883                 dev_err(&pdev->dev, "No Slots\n");
1884                 return -ENXIO;
1885         }
1886
1887         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1888         irq = platform_get_irq(pdev, 0);
1889         if (res == NULL || irq < 0)
1890                 return -ENXIO;
1891
1892         res->start += pdata->reg_offset;
1893         res->end += pdata->reg_offset;
1894         res = request_mem_region(res->start, resource_size(res), pdev->name);
1895         if (res == NULL)
1896                 return -EBUSY;
1897
1898         ret = omap_hsmmc_gpio_init(pdata);
1899         if (ret)
1900                 goto err;
1901
1902         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1903         if (!mmc) {
1904                 ret = -ENOMEM;
1905                 goto err_alloc;
1906         }
1907
1908         host            = mmc_priv(mmc);
1909         host->mmc       = mmc;
1910         host->pdata     = pdata;
1911         host->dev       = &pdev->dev;
1912         host->use_dma   = 1;
1913         host->dev->dma_mask = &pdata->dma_mask;
1914         host->dma_ch    = -1;
1915         host->irq       = irq;
1916         host->id        = pdev->id;
1917         host->slot_id   = 0;
1918         host->mapbase   = res->start;
1919         host->base      = ioremap(host->mapbase, SZ_4K);
1920         host->power_mode = MMC_POWER_OFF;
1921         host->next_data.cookie = 1;
1922
1923         platform_set_drvdata(pdev, host);
1924         INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1925
1926         mmc->ops        = &omap_hsmmc_ops;
1927
1928         /*
1929          * If regulator_disable can only put vcc_aux to sleep then there is
1930          * no off state.
1931          */
1932         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1933                 mmc_slot(host).no_off = 1;
1934
1935         mmc->f_min      = 400000;
1936         mmc->f_max      = 52000000;
1937
1938         spin_lock_init(&host->irq_lock);
1939
1940         host->fclk = clk_get(&pdev->dev, "fck");
1941         if (IS_ERR(host->fclk)) {
1942                 ret = PTR_ERR(host->fclk);
1943                 host->fclk = NULL;
1944                 goto err1;
1945         }
1946
1947         omap_hsmmc_context_save(host);
1948
1949         mmc->caps |= MMC_CAP_DISABLE;
1950
1951         pm_runtime_enable(host->dev);
1952         pm_runtime_get_sync(host->dev);
1953         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1954         pm_runtime_use_autosuspend(host->dev);
1955
1956         if (cpu_is_omap2430()) {
1957                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1958                 /*
1959                  * MMC can still work without debounce clock.
1960                  */
1961                 if (IS_ERR(host->dbclk))
1962                         dev_warn(mmc_dev(host->mmc),
1963                                 "Failed to get debounce clock\n");
1964                 else
1965                         host->got_dbclk = 1;
1966
1967                 if (host->got_dbclk)
1968                         if (clk_enable(host->dbclk) != 0)
1969                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1970                                                         " clk failed\n");
1971         }
1972
1973         /* Since we do only SG emulation, we can have as many segs
1974          * as we want. */
1975         mmc->max_segs = 1024;
1976
1977         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1978         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1979         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1980         mmc->max_seg_size = mmc->max_req_size;
1981
1982         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1983                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1984
1985         mmc->caps |= mmc_slot(host).caps;
1986         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1987                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1988
1989         if (mmc_slot(host).nonremovable)
1990                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1991
1992         omap_hsmmc_conf_bus_power(host);
1993
1994         /* Select DMA lines */
1995         switch (host->id) {
1996         case OMAP_MMC1_DEVID:
1997                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1998                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1999                 break;
2000         case OMAP_MMC2_DEVID:
2001                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2002                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2003                 break;
2004         case OMAP_MMC3_DEVID:
2005                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2006                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2007                 break;
2008         case OMAP_MMC4_DEVID:
2009                 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2010                 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2011                 break;
2012         case OMAP_MMC5_DEVID:
2013                 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2014                 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2015                 break;
2016         default:
2017                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2018                 goto err_irq;
2019         }
2020
2021         /* Request IRQ for MMC operations */
2022         ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2023                         mmc_hostname(mmc), host);
2024         if (ret) {
2025                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2026                 goto err_irq;
2027         }
2028
2029         if (pdata->init != NULL) {
2030                 if (pdata->init(&pdev->dev) != 0) {
2031                         dev_dbg(mmc_dev(host->mmc),
2032                                 "Unable to configure MMC IRQs\n");
2033                         goto err_irq_cd_init;
2034                 }
2035         }
2036
2037         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2038                 ret = omap_hsmmc_reg_get(host);
2039                 if (ret)
2040                         goto err_reg;
2041                 host->use_reg = 1;
2042         }
2043
2044         mmc->ocr_avail = mmc_slot(host).ocr_mask;
2045
2046         /* Request IRQ for card detect */
2047         if ((mmc_slot(host).card_detect_irq)) {
2048                 ret = request_irq(mmc_slot(host).card_detect_irq,
2049                                   omap_hsmmc_cd_handler,
2050                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2051                                           | IRQF_DISABLED,
2052                                   mmc_hostname(mmc), host);
2053                 if (ret) {
2054                         dev_dbg(mmc_dev(host->mmc),
2055                                 "Unable to grab MMC CD IRQ\n");
2056                         goto err_irq_cd;
2057                 }
2058                 pdata->suspend = omap_hsmmc_suspend_cdirq;
2059                 pdata->resume = omap_hsmmc_resume_cdirq;
2060         }
2061
2062         omap_hsmmc_disable_irq(host);
2063
2064         omap_hsmmc_protect_card(host);
2065
2066         mmc_add_host(mmc);
2067
2068         if (mmc_slot(host).name != NULL) {
2069                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2070                 if (ret < 0)
2071                         goto err_slot_name;
2072         }
2073         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2074                 ret = device_create_file(&mmc->class_dev,
2075                                         &dev_attr_cover_switch);
2076                 if (ret < 0)
2077                         goto err_slot_name;
2078         }
2079
2080         omap_hsmmc_debugfs(mmc);
2081         pm_runtime_mark_last_busy(host->dev);
2082         pm_runtime_put_autosuspend(host->dev);
2083
2084         return 0;
2085
2086 err_slot_name:
2087         mmc_remove_host(mmc);
2088         free_irq(mmc_slot(host).card_detect_irq, host);
2089 err_irq_cd:
2090         if (host->use_reg)
2091                 omap_hsmmc_reg_put(host);
2092 err_reg:
2093         if (host->pdata->cleanup)
2094                 host->pdata->cleanup(&pdev->dev);
2095 err_irq_cd_init:
2096         free_irq(host->irq, host);
2097 err_irq:
2098         pm_runtime_mark_last_busy(host->dev);
2099         pm_runtime_put_autosuspend(host->dev);
2100         clk_put(host->fclk);
2101         if (host->got_dbclk) {
2102                 clk_disable(host->dbclk);
2103                 clk_put(host->dbclk);
2104         }
2105 err1:
2106         iounmap(host->base);
2107         platform_set_drvdata(pdev, NULL);
2108         mmc_free_host(mmc);
2109 err_alloc:
2110         omap_hsmmc_gpio_free(pdata);
2111 err:
2112         release_mem_region(res->start, resource_size(res));
2113         return ret;
2114 }
2115
2116 static int omap_hsmmc_remove(struct platform_device *pdev)
2117 {
2118         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2119         struct resource *res;
2120
2121         if (host) {
2122                 pm_runtime_get_sync(host->dev);
2123                 mmc_remove_host(host->mmc);
2124                 if (host->use_reg)
2125                         omap_hsmmc_reg_put(host);
2126                 if (host->pdata->cleanup)
2127                         host->pdata->cleanup(&pdev->dev);
2128                 free_irq(host->irq, host);
2129                 if (mmc_slot(host).card_detect_irq)
2130                         free_irq(mmc_slot(host).card_detect_irq, host);
2131                 flush_work_sync(&host->mmc_carddetect_work);
2132
2133                 pm_runtime_put_sync(host->dev);
2134                 pm_runtime_disable(host->dev);
2135                 clk_put(host->fclk);
2136                 if (host->got_dbclk) {
2137                         clk_disable(host->dbclk);
2138                         clk_put(host->dbclk);
2139                 }
2140
2141                 mmc_free_host(host->mmc);
2142                 iounmap(host->base);
2143                 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2144         }
2145
2146         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2147         if (res)
2148                 release_mem_region(res->start, resource_size(res));
2149         platform_set_drvdata(pdev, NULL);
2150
2151         return 0;
2152 }
2153
2154 #ifdef CONFIG_PM
2155 static int omap_hsmmc_suspend(struct device *dev)
2156 {
2157         int ret = 0;
2158         struct platform_device *pdev = to_platform_device(dev);
2159         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2160
2161         if (host && host->suspended)
2162                 return 0;
2163
2164         if (host) {
2165                 pm_runtime_get_sync(host->dev);
2166                 host->suspended = 1;
2167                 if (host->pdata->suspend) {
2168                         ret = host->pdata->suspend(&pdev->dev,
2169                                                         host->slot_id);
2170                         if (ret) {
2171                                 dev_dbg(mmc_dev(host->mmc),
2172                                         "Unable to handle MMC board"
2173                                         " level suspend\n");
2174                                 host->suspended = 0;
2175                                 return ret;
2176                         }
2177                 }
2178                 cancel_work_sync(&host->mmc_carddetect_work);
2179                 ret = mmc_suspend_host(host->mmc);
2180
2181                 if (ret == 0) {
2182                         omap_hsmmc_disable_irq(host);
2183                         OMAP_HSMMC_WRITE(host->base, HCTL,
2184                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2185                         if (host->got_dbclk)
2186                                 clk_disable(host->dbclk);
2187                 } else {
2188                         host->suspended = 0;
2189                         if (host->pdata->resume) {
2190                                 ret = host->pdata->resume(&pdev->dev,
2191                                                           host->slot_id);
2192                                 if (ret)
2193                                         dev_dbg(mmc_dev(host->mmc),
2194                                                 "Unmask interrupt failed\n");
2195                         }
2196                 }
2197                 pm_runtime_put_sync(host->dev);
2198         }
2199         return ret;
2200 }
2201
2202 /* Routine to resume the MMC device */
2203 static int omap_hsmmc_resume(struct device *dev)
2204 {
2205         int ret = 0;
2206         struct platform_device *pdev = to_platform_device(dev);
2207         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2208
2209         if (host && !host->suspended)
2210                 return 0;
2211
2212         if (host) {
2213                 pm_runtime_get_sync(host->dev);
2214
2215                 if (host->got_dbclk)
2216                         clk_enable(host->dbclk);
2217
2218                 omap_hsmmc_conf_bus_power(host);
2219
2220                 if (host->pdata->resume) {
2221                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
2222                         if (ret)
2223                                 dev_dbg(mmc_dev(host->mmc),
2224                                         "Unmask interrupt failed\n");
2225                 }
2226
2227                 omap_hsmmc_protect_card(host);
2228
2229                 /* Notify the core to resume the host */
2230                 ret = mmc_resume_host(host->mmc);
2231                 if (ret == 0)
2232                         host->suspended = 0;
2233
2234                 pm_runtime_mark_last_busy(host->dev);
2235                 pm_runtime_put_autosuspend(host->dev);
2236         }
2237
2238         return ret;
2239
2240 }
2241
2242 #else
2243 #define omap_hsmmc_suspend      NULL
2244 #define omap_hsmmc_resume               NULL
2245 #endif
2246
2247 static int omap_hsmmc_runtime_suspend(struct device *dev)
2248 {
2249         struct omap_hsmmc_host *host;
2250
2251         host = platform_get_drvdata(to_platform_device(dev));
2252         omap_hsmmc_context_save(host);
2253         dev_dbg(mmc_dev(host->mmc), "disabled\n");
2254
2255         return 0;
2256 }
2257
2258 static int omap_hsmmc_runtime_resume(struct device *dev)
2259 {
2260         struct omap_hsmmc_host *host;
2261
2262         host = platform_get_drvdata(to_platform_device(dev));
2263         omap_hsmmc_context_restore(host);
2264         dev_dbg(mmc_dev(host->mmc), "enabled\n");
2265
2266         return 0;
2267 }
2268
2269 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2270         .suspend        = omap_hsmmc_suspend,
2271         .resume         = omap_hsmmc_resume,
2272         .runtime_suspend = omap_hsmmc_runtime_suspend,
2273         .runtime_resume = omap_hsmmc_runtime_resume,
2274 };
2275
2276 static struct platform_driver omap_hsmmc_driver = {
2277         .remove         = omap_hsmmc_remove,
2278         .driver         = {
2279                 .name = DRIVER_NAME,
2280                 .owner = THIS_MODULE,
2281                 .pm = &omap_hsmmc_dev_pm_ops,
2282         },
2283 };
2284
2285 static int __init omap_hsmmc_init(void)
2286 {
2287         /* Register the MMC driver */
2288         return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2289 }
2290
2291 static void __exit omap_hsmmc_cleanup(void)
2292 {
2293         /* Unregister MMC driver */
2294         platform_driver_unregister(&omap_hsmmc_driver);
2295 }
2296
2297 module_init(omap_hsmmc_init);
2298 module_exit(omap_hsmmc_cleanup);
2299
2300 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2301 MODULE_LICENSE("GPL");
2302 MODULE_ALIAS("platform:" DRIVER_NAME);
2303 MODULE_AUTHOR("Texas Instruments Inc");