2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
4 * Copyright (C) 2007 Google Inc,
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 * Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Author: San Mehat (san@android.com)
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/highmem.h>
27 #include <linux/log2.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/mmc/sdio.h>
31 #include <linux/clk.h>
32 #include <linux/scatterlist.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/debugfs.h>
37 #include <linux/memory.h>
38 #include <linux/gfp.h>
39 #include <linux/gpio.h>
41 #include <asm/cacheflush.h>
42 #include <asm/div64.h>
43 #include <asm/sizes.h>
46 #include <mach/msm_iomap.h>
52 #define DRIVER_NAME "msm-sdcc"
54 #define BUSCLK_PWRSAVE 1
55 #define BUSCLK_TIMEOUT (HZ)
56 static unsigned int msmsdcc_fmin = 144000;
57 static unsigned int msmsdcc_fmax = 50000000;
58 static unsigned int msmsdcc_4bit = 1;
59 static unsigned int msmsdcc_pwrsave = 1;
60 static unsigned int msmsdcc_piopoll = 1;
61 static unsigned int msmsdcc_sdioirq;
63 #define PIO_SPINMAX 30
64 #define CMD_SPINMAX 20
68 msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
70 WARN_ON(!host->clks_on);
72 BUG_ON(host->curr.mrq);
75 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
77 del_timer_sync(&host->busclk_timer);
78 /* Need to check clks_on again in case the busclk
82 clk_disable(host->clk);
83 clk_disable(host->pclk);
90 msmsdcc_enable_clocks(struct msmsdcc_host *host)
94 del_timer_sync(&host->busclk_timer);
97 rc = clk_enable(host->pclk);
100 rc = clk_enable(host->clk);
102 clk_disable(host->pclk);
105 udelay(1 + ((3 * USEC_PER_SEC) /
106 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
112 static inline unsigned int
113 msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
115 return readl(host->base + reg);
119 msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
121 writel(data, host->base + reg);
122 /* 3 clk delay required! */
123 udelay(1 + ((3 * USEC_PER_SEC) /
124 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
128 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
131 static void msmsdcc_reset_and_restore(struct msmsdcc_host *host)
137 /* Save the controller state */
138 mci_clk = readl(host->base + MMCICLOCK);
139 mci_mask0 = readl(host->base + MMCIMASK0);
141 /* Reset the controller */
142 ret = clk_reset(host->clk, CLK_RESET_ASSERT);
144 pr_err("%s: Clock assert failed at %u Hz with err %d\n",
145 mmc_hostname(host->mmc), host->clk_rate, ret);
147 ret = clk_reset(host->clk, CLK_RESET_DEASSERT);
149 pr_err("%s: Clock deassert failed at %u Hz with err %d\n",
150 mmc_hostname(host->mmc), host->clk_rate, ret);
152 pr_info("%s: Controller has been re-initialiazed\n",
153 mmc_hostname(host->mmc));
155 /* Restore the contoller state */
156 writel(host->pwr, host->base + MMCIPOWER);
157 writel(mci_clk, host->base + MMCICLOCK);
158 writel(mci_mask0, host->base + MMCIMASK0);
159 ret = clk_set_rate(host->clk, host->clk_rate);
161 pr_err("%s: Failed to set clk rate %u Hz (%d)\n",
162 mmc_hostname(host->mmc), host->clk_rate, ret);
166 msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
168 BUG_ON(host->curr.data);
170 host->curr.mrq = NULL;
171 host->curr.cmd = NULL;
174 mrq->data->bytes_xfered = host->curr.data_xfered;
175 if (mrq->cmd->error == -ETIMEDOUT)
179 msmsdcc_disable_clocks(host, 1);
182 * Need to drop the host lock here; mmc_request_done may call
183 * back into the driver...
185 spin_unlock(&host->lock);
186 mmc_request_done(host->mmc, mrq);
187 spin_lock(&host->lock);
191 msmsdcc_stop_data(struct msmsdcc_host *host)
193 host->curr.data = NULL;
194 host->curr.got_dataend = 0;
197 uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
199 return host->memres->start + MMCIFIFO;
203 msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
204 msmsdcc_writel(host, arg, MMCIARGUMENT);
205 msmsdcc_writel(host, c, MMCICOMMAND);
209 msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
211 struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
213 msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
214 msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
216 msmsdcc_writel(host, host->cmd_pio_irqmask, MMCIMASK1);
217 msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
220 msmsdcc_start_command_exec(host,
221 (u32) host->cmd_cmd->arg,
224 host->dma.active = 1;
228 msmsdcc_dma_complete_tlet(unsigned long data)
230 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
232 struct mmc_request *mrq;
233 struct msm_dmov_errdata err;
235 spin_lock_irqsave(&host->lock, flags);
236 host->dma.active = 0;
239 mrq = host->curr.mrq;
243 if (!(host->dma.result & DMOV_RSLT_VALID)) {
244 pr_err("msmsdcc: Invalid DataMover result\n");
248 if (host->dma.result & DMOV_RSLT_DONE) {
249 host->curr.data_xfered = host->curr.xfer_size;
252 if (host->dma.result & DMOV_RSLT_ERROR)
253 pr_err("%s: DMA error (0x%.8x)\n",
254 mmc_hostname(host->mmc), host->dma.result);
255 if (host->dma.result & DMOV_RSLT_FLUSH)
256 pr_err("%s: DMA channel flushed (0x%.8x)\n",
257 mmc_hostname(host->mmc), host->dma.result);
259 pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
260 err.flush[0], err.flush[1], err.flush[2],
261 err.flush[3], err.flush[4], err.flush[5]);
263 msmsdcc_reset_and_restore(host);
264 if (!mrq->data->error)
265 mrq->data->error = -EIO;
267 dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
273 if (host->curr.got_dataend || mrq->data->error) {
276 * If we've already gotten our DATAEND / DATABLKEND
277 * for this request, then complete it through here.
279 msmsdcc_stop_data(host);
281 if (!mrq->data->error)
282 host->curr.data_xfered = host->curr.xfer_size;
283 if (!mrq->data->stop || mrq->cmd->error) {
284 host->curr.mrq = NULL;
285 host->curr.cmd = NULL;
286 mrq->data->bytes_xfered = host->curr.data_xfered;
288 spin_unlock_irqrestore(&host->lock, flags);
290 msmsdcc_disable_clocks(host, 1);
292 mmc_request_done(host->mmc, mrq);
295 msmsdcc_start_command(host, mrq->data->stop, 0);
299 spin_unlock_irqrestore(&host->lock, flags);
304 msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
306 struct msm_dmov_errdata *err)
308 struct msmsdcc_dma_data *dma_data =
309 container_of(cmd, struct msmsdcc_dma_data, hdr);
310 struct msmsdcc_host *host = dma_data->host;
312 dma_data->result = result;
314 memcpy(&dma_data->err, err, sizeof(struct msm_dmov_errdata));
316 tasklet_schedule(&host->dma_tlet);
319 static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
321 if (host->dma.channel == -1)
324 if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
326 if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
331 static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
333 struct msmsdcc_nc_dmadata *nc;
339 struct scatterlist *sg = data->sg;
341 rc = validate_dma(host, data);
345 host->dma.sg = data->sg;
346 host->dma.num_ents = data->sg_len;
348 BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
352 switch (host->pdev_id) {
354 crci = MSMSDCC_CRCI_SDC1;
357 crci = MSMSDCC_CRCI_SDC2;
360 crci = MSMSDCC_CRCI_SDC3;
363 crci = MSMSDCC_CRCI_SDC4;
367 host->dma.num_ents = 0;
371 if (data->flags & MMC_DATA_READ)
372 host->dma.dir = DMA_FROM_DEVICE;
374 host->dma.dir = DMA_TO_DEVICE;
376 host->curr.user_pages = 0;
380 /* location of command block must be 64 bit aligned */
381 BUG_ON(host->dma.cmd_busaddr & 0x07);
383 nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
384 host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
385 DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
386 host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
388 n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
389 host->dma.num_ents, host->dma.dir);
391 printk(KERN_ERR "%s: Unable to map in all sg elements\n",
392 mmc_hostname(host->mmc));
394 host->dma.num_ents = 0;
398 for_each_sg(host->dma.sg, sg, n, i) {
400 box->cmd = CMD_MODE_BOX;
404 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
405 (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
406 (sg_dma_len(sg) / MCI_FIFOSIZE) ;
408 if (data->flags & MMC_DATA_READ) {
409 box->src_row_addr = msmsdcc_fifo_addr(host);
410 box->dst_row_addr = sg_dma_address(sg);
412 box->src_dst_len = (MCI_FIFOSIZE << 16) |
414 box->row_offset = MCI_FIFOSIZE;
416 box->num_rows = rows * ((1 << 16) + 1);
417 box->cmd |= CMD_SRC_CRCI(crci);
419 box->src_row_addr = sg_dma_address(sg);
420 box->dst_row_addr = msmsdcc_fifo_addr(host);
422 box->src_dst_len = (MCI_FIFOSIZE << 16) |
424 box->row_offset = (MCI_FIFOSIZE << 16);
426 box->num_rows = rows * ((1 << 16) + 1);
427 box->cmd |= CMD_DST_CRCI(crci);
436 snoop_cccr_abort(struct mmc_command *cmd)
438 if ((cmd->opcode == 52) &&
439 (cmd->arg & 0x80000000) &&
440 (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT))
446 msmsdcc_start_command_deferred(struct msmsdcc_host *host,
447 struct mmc_command *cmd, u32 *c)
449 *c |= (cmd->opcode | MCI_CPSM_ENABLE);
451 if (cmd->flags & MMC_RSP_PRESENT) {
452 if (cmd->flags & MMC_RSP_136)
453 *c |= MCI_CPSM_LONGRSP;
454 *c |= MCI_CPSM_RESPONSE;
458 *c |= MCI_CPSM_INTERRUPT;
460 if ((((cmd->opcode == 17) || (cmd->opcode == 18)) ||
461 ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
463 *c |= MCI_CSPM_DATCMD;
465 if (host->prog_scan && (cmd->opcode == 12)) {
466 *c |= MCI_CPSM_PROGENA;
467 host->prog_enable = true;
470 if (cmd == cmd->mrq->stop)
471 *c |= MCI_CSPM_MCIABORT;
473 if (snoop_cccr_abort(cmd))
474 *c |= MCI_CSPM_MCIABORT;
476 if (host->curr.cmd != NULL) {
477 printk(KERN_ERR "%s: Overlapping command requests\n",
478 mmc_hostname(host->mmc));
480 host->curr.cmd = cmd;
484 msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
485 struct mmc_command *cmd, u32 c)
487 unsigned int datactrl, timeout;
488 unsigned long long clks;
489 unsigned int pio_irqmask = 0;
491 host->curr.data = data;
492 host->curr.xfer_size = data->blksz * data->blocks;
493 host->curr.xfer_remain = host->curr.xfer_size;
494 host->curr.data_xfered = 0;
495 host->curr.got_dataend = 0;
497 memset(&host->pio, 0, sizeof(host->pio));
499 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
501 if (!msmsdcc_config_dma(host, data))
502 datactrl |= MCI_DPSM_DMAENABLE;
504 host->pio.sg = data->sg;
505 host->pio.sg_len = data->sg_len;
506 host->pio.sg_off = 0;
508 if (data->flags & MMC_DATA_READ) {
509 pio_irqmask = MCI_RXFIFOHALFFULLMASK;
510 if (host->curr.xfer_remain < MCI_FIFOSIZE)
511 pio_irqmask |= MCI_RXDATAAVLBLMASK;
513 pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
516 if (data->flags & MMC_DATA_READ)
517 datactrl |= MCI_DPSM_DIRECTION;
519 clks = (unsigned long long)data->timeout_ns * host->clk_rate;
520 do_div(clks, NSEC_PER_SEC);
521 timeout = data->timeout_clks + (unsigned int)clks*2 ;
523 if (datactrl & MCI_DPSM_DMAENABLE) {
524 /* Save parameters for the exec function */
525 host->cmd_timeout = timeout;
526 host->cmd_pio_irqmask = pio_irqmask;
527 host->cmd_datactrl = datactrl;
530 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
531 host->dma.hdr.data = (void *)host;
535 msmsdcc_start_command_deferred(host, cmd, &c);
538 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
539 if (data->flags & MMC_DATA_WRITE)
540 host->prog_scan = true;
542 msmsdcc_writel(host, timeout, MMCIDATATIMER);
544 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
546 msmsdcc_writel(host, pio_irqmask, MMCIMASK1);
547 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
550 /* Daisy-chain the command if requested */
551 msmsdcc_start_command(host, cmd, c);
557 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
559 if (cmd == cmd->mrq->stop)
560 c |= MCI_CSPM_MCIABORT;
564 msmsdcc_start_command_deferred(host, cmd, &c);
565 msmsdcc_start_command_exec(host, cmd->arg, c);
569 msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
572 if (status & MCI_DATACRCFAIL) {
573 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
574 pr_err("%s: opcode 0x%.8x\n", __func__,
575 data->mrq->cmd->opcode);
576 pr_err("%s: blksz %d, blocks %d\n", __func__,
577 data->blksz, data->blocks);
578 data->error = -EILSEQ;
579 } else if (status & MCI_DATATIMEOUT) {
580 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
581 data->error = -ETIMEDOUT;
582 } else if (status & MCI_RXOVERRUN) {
583 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
585 } else if (status & MCI_TXUNDERRUN) {
586 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
589 pr_err("%s: Unknown error (0x%.8x)\n",
590 mmc_hostname(host->mmc), status);
597 msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
599 uint32_t *ptr = (uint32_t *) buffer;
603 remain = ((remain >> 2) + 1) << 2;
605 while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
606 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
608 count += sizeof(uint32_t);
610 remain -= sizeof(uint32_t);
618 msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
619 unsigned int remain, u32 status)
621 void __iomem *base = host->base;
625 unsigned int count, maxcnt, sz;
627 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
629 count = min(remain, maxcnt);
631 sz = count % 4 ? (count >> 2) + 1 : (count >> 2);
632 writesl(base + MMCIFIFO, ptr, sz);
639 status = msmsdcc_readl(host, MMCISTATUS);
640 } while (status & MCI_TXFIFOHALFEMPTY);
646 msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
649 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
658 msmsdcc_pio_irq(int irq, void *dev_id)
660 struct msmsdcc_host *host = dev_id;
663 status = msmsdcc_readl(host, MMCISTATUS);
667 unsigned int remain, len;
670 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
671 if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
674 if (msmsdcc_spin_on_status(host,
675 (MCI_TXFIFOHALFEMPTY |
682 /* Map the current scatter buffer */
683 local_irq_save(flags);
684 buffer = kmap_atomic(sg_page(host->pio.sg),
685 KM_BIO_SRC_IRQ) + host->pio.sg->offset;
686 buffer += host->pio.sg_off;
687 remain = host->pio.sg->length - host->pio.sg_off;
689 if (status & MCI_RXACTIVE)
690 len = msmsdcc_pio_read(host, buffer, remain);
691 if (status & MCI_TXACTIVE)
692 len = msmsdcc_pio_write(host, buffer, remain, status);
694 /* Unmap the buffer */
695 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
696 local_irq_restore(flags);
698 host->pio.sg_off += len;
699 host->curr.xfer_remain -= len;
700 host->curr.data_xfered += len;
704 /* This sg page is full - do some housekeeping */
705 if (status & MCI_RXACTIVE && host->curr.user_pages)
706 flush_dcache_page(sg_page(host->pio.sg));
708 if (!--host->pio.sg_len) {
709 memset(&host->pio, 0, sizeof(host->pio));
713 /* Advance to next sg */
715 host->pio.sg_off = 0;
718 status = msmsdcc_readl(host, MMCISTATUS);
721 if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
722 msmsdcc_writel(host, MCI_RXDATAAVLBLMASK, MMCIMASK1);
724 if (!host->curr.xfer_remain)
725 msmsdcc_writel(host, 0, MMCIMASK1);
730 static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
732 struct mmc_command *cmd = host->curr.cmd;
734 host->curr.cmd = NULL;
735 cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
736 cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
737 cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
738 cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
740 if (status & MCI_CMDTIMEOUT) {
741 cmd->error = -ETIMEDOUT;
742 } else if (status & MCI_CMDCRCFAIL &&
743 cmd->flags & MMC_RSP_CRC) {
744 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
745 cmd->error = -EILSEQ;
748 if (!cmd->data || cmd->error) {
749 if (host->curr.data && host->dma.sg)
750 msm_dmov_stop_cmd(host->dma.channel,
752 else if (host->curr.data) { /* Non DMA */
753 msmsdcc_reset_and_restore(host);
754 msmsdcc_stop_data(host);
755 msmsdcc_request_end(host, cmd->mrq);
756 } else { /* host->data == NULL */
757 if (!cmd->error && host->prog_enable) {
758 if (status & MCI_PROGDONE) {
759 host->prog_scan = false;
760 host->prog_enable = false;
761 msmsdcc_request_end(host, cmd->mrq);
763 host->curr.cmd = cmd;
766 if (host->prog_enable) {
767 host->prog_scan = false;
768 host->prog_enable = false;
770 msmsdcc_request_end(host, cmd->mrq);
773 } else if (cmd->data)
774 if (!(cmd->data->flags & MMC_DATA_READ))
775 msmsdcc_start_data(host, cmd->data,
780 msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
783 struct mmc_data *data = host->curr.data;
785 if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
786 MCI_CMDTIMEOUT | MCI_PROGDONE) && host->curr.cmd) {
787 msmsdcc_do_cmdirq(host, status);
793 /* Check for data errors */
794 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
795 MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
796 msmsdcc_data_err(host, data, status);
797 host->curr.data_xfered = 0;
799 msm_dmov_stop_cmd(host->dma.channel,
802 msmsdcc_reset_and_restore(host);
804 msmsdcc_stop_data(host);
806 msmsdcc_request_end(host, data->mrq);
808 msmsdcc_start_command(host, data->stop, 0);
812 /* Check for data done */
813 if (!host->curr.got_dataend && (status & MCI_DATAEND))
814 host->curr.got_dataend = 1;
817 * If DMA is still in progress, we complete via the completion handler
819 if (host->curr.got_dataend && !host->dma.busy) {
821 * There appears to be an issue in the controller where
822 * if you request a small block transfer (< fifo size),
823 * you may get your DATAEND/DATABLKEND irq without the
826 * Check to see if there is still data to be read,
827 * and simulate a PIO irq.
829 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
830 msmsdcc_pio_irq(1, host);
832 msmsdcc_stop_data(host);
834 host->curr.data_xfered = host->curr.xfer_size;
837 msmsdcc_request_end(host, data->mrq);
839 msmsdcc_start_command(host, data->stop, 0);
844 msmsdcc_irq(int irq, void *dev_id)
846 struct msmsdcc_host *host = dev_id;
847 void __iomem *base = host->base;
852 spin_lock(&host->lock);
855 status = msmsdcc_readl(host, MMCISTATUS);
856 status &= msmsdcc_readl(host, MMCIMASK0);
857 msmsdcc_writel(host, status, MMCICLEAR);
859 if (status & MCI_SDIOINTR)
860 status &= ~MCI_SDIOINTR;
865 msmsdcc_handle_irq_data(host, status, base);
867 if (status & MCI_SDIOINTOPER) {
869 status &= ~MCI_SDIOINTOPER;
874 spin_unlock(&host->lock);
877 * We have to delay handling the card interrupt as it calls
878 * back into the driver.
881 mmc_signal_sdio_irq(host->mmc);
883 return IRQ_RETVAL(ret);
887 msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
889 struct msmsdcc_host *host = mmc_priv(mmc);
892 WARN_ON(host->curr.mrq != NULL);
893 WARN_ON(host->pwr == 0);
895 spin_lock_irqsave(&host->lock, flags);
900 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
902 mrq->data->bytes_xfered = mrq->data->blksz *
905 mrq->cmd->error = -ENOMEDIUM;
907 spin_unlock_irqrestore(&host->lock, flags);
908 mmc_request_done(mmc, mrq);
912 msmsdcc_enable_clocks(host);
914 host->curr.mrq = mrq;
916 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
917 /* Queue/read data, daisy-chain command when data starts */
918 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
920 msmsdcc_start_command(host, mrq->cmd, 0);
922 if (host->cmdpoll && !msmsdcc_spin_on_status(host,
923 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
925 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
926 msmsdcc_do_cmdirq(host, status);
928 MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
930 host->stats.cmdpoll_hits++;
932 host->stats.cmdpoll_misses++;
934 spin_unlock_irqrestore(&host->lock, flags);
937 static void msmsdcc_setup_gpio(struct msmsdcc_host *host, bool enable)
939 struct msm_mmc_gpio_data *curr;
942 if (!host->plat->gpio_data || host->gpio_config_status == enable)
945 curr = host->plat->gpio_data;
946 for (i = 0; i < curr->size; i++) {
948 rc = gpio_request(curr->gpio[i].no,
951 pr_err("%s: gpio_request(%d, %s) failed %d\n",
952 mmc_hostname(host->mmc),
954 curr->gpio[i].name, rc);
958 gpio_free(curr->gpio[i].no);
961 host->gpio_config_status = enable;
966 gpio_free(curr->gpio[i].no);
970 msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
972 struct msmsdcc_host *host = mmc_priv(mmc);
973 u32 clk = 0, pwr = 0;
977 spin_lock_irqsave(&host->lock, flags);
979 msmsdcc_enable_clocks(host);
981 spin_unlock_irqrestore(&host->lock, flags);
984 if (ios->clock != host->clk_rate) {
985 rc = clk_set_rate(host->clk, ios->clock);
987 pr_err("%s: Error setting clock rate (%d)\n",
988 mmc_hostname(host->mmc), rc);
990 host->clk_rate = ios->clock;
992 clk |= MCI_CLK_ENABLE;
995 if (ios->bus_width == MMC_BUS_WIDTH_4)
996 clk |= (2 << 10); /* Set WIDEBUS */
998 if (ios->clock > 400000 && msmsdcc_pwrsave)
999 clk |= (1 << 9); /* PWRSAVE */
1001 clk |= (1 << 12); /* FLOW_ENA */
1002 clk |= (1 << 15); /* feedback clock */
1004 if (host->plat->translate_vdd)
1005 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
1007 switch (ios->power_mode) {
1009 msmsdcc_setup_gpio(host, false);
1013 msmsdcc_setup_gpio(host, true);
1020 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1023 msmsdcc_writel(host, clk, MMCICLOCK);
1025 if (host->pwr != pwr) {
1027 msmsdcc_writel(host, pwr, MMCIPOWER);
1030 spin_lock_irqsave(&host->lock, flags);
1031 msmsdcc_disable_clocks(host, 1);
1032 spin_unlock_irqrestore(&host->lock, flags);
1036 static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1038 struct msmsdcc_host *host = mmc_priv(mmc);
1039 unsigned long flags;
1042 spin_lock_irqsave(&host->lock, flags);
1043 if (msmsdcc_sdioirq == 1) {
1044 status = msmsdcc_readl(host, MMCIMASK0);
1046 status |= MCI_SDIOINTOPERMASK;
1048 status &= ~MCI_SDIOINTOPERMASK;
1049 host->saved_irq0mask = status;
1050 msmsdcc_writel(host, status, MMCIMASK0);
1052 spin_unlock_irqrestore(&host->lock, flags);
1055 static void msmsdcc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1057 struct msmsdcc_host *host = mmc_priv(mmc);
1059 if (host->plat->init_card)
1060 host->plat->init_card(card);
1063 static const struct mmc_host_ops msmsdcc_ops = {
1064 .request = msmsdcc_request,
1065 .set_ios = msmsdcc_set_ios,
1066 .enable_sdio_irq = msmsdcc_enable_sdio_irq,
1067 .init_card = msmsdcc_init_card,
1071 msmsdcc_check_status(unsigned long data)
1073 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
1074 unsigned int status;
1076 if (!host->plat->status) {
1077 mmc_detect_change(host->mmc, 0);
1081 status = host->plat->status(mmc_dev(host->mmc));
1082 host->eject = !status;
1083 if (status ^ host->oldstat) {
1084 pr_info("%s: Slot status change detected (%d -> %d)\n",
1085 mmc_hostname(host->mmc), host->oldstat, status);
1087 mmc_detect_change(host->mmc, (5 * HZ) / 2);
1089 mmc_detect_change(host->mmc, 0);
1092 host->oldstat = status;
1095 if (host->timer.function)
1096 mod_timer(&host->timer, jiffies + HZ);
1100 msmsdcc_platform_status_irq(int irq, void *dev_id)
1102 struct msmsdcc_host *host = dev_id;
1104 printk(KERN_DEBUG "%s: %d\n", __func__, irq);
1105 msmsdcc_check_status((unsigned long) host);
1110 msmsdcc_status_notify_cb(int card_present, void *dev_id)
1112 struct msmsdcc_host *host = dev_id;
1114 printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
1116 msmsdcc_check_status((unsigned long) host);
1120 msmsdcc_busclk_expired(unsigned long _data)
1122 struct msmsdcc_host *host = (struct msmsdcc_host *) _data;
1125 msmsdcc_disable_clocks(host, 0);
1129 msmsdcc_init_dma(struct msmsdcc_host *host)
1131 memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1132 host->dma.host = host;
1133 host->dma.channel = -1;
1138 host->dma.nc = dma_alloc_coherent(NULL,
1139 sizeof(struct msmsdcc_nc_dmadata),
1140 &host->dma.nc_busaddr,
1142 if (host->dma.nc == NULL) {
1143 pr_err("Unable to allocate DMA buffer\n");
1146 memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1147 host->dma.cmd_busaddr = host->dma.nc_busaddr;
1148 host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1149 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
1150 host->dma.channel = host->dmares->start;
1156 msmsdcc_probe(struct platform_device *pdev)
1158 struct msm_mmc_platform_data *plat = pdev->dev.platform_data;
1159 struct msmsdcc_host *host;
1160 struct mmc_host *mmc;
1161 struct resource *cmd_irqres = NULL;
1162 struct resource *stat_irqres = NULL;
1163 struct resource *memres = NULL;
1164 struct resource *dmares = NULL;
1167 /* must have platform data */
1169 pr_err("%s: Platform data not available\n", __func__);
1174 if (pdev->id < 1 || pdev->id > 4)
1177 if (pdev->resource == NULL || pdev->num_resources < 2) {
1178 pr_err("%s: Invalid resource\n", __func__);
1182 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1184 cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1186 stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1189 if (!cmd_irqres || !memres) {
1190 pr_err("%s: Invalid resource\n", __func__);
1195 * Setup our host structure
1198 mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1204 host = mmc_priv(mmc);
1205 host->pdev_id = pdev->id;
1208 host->curr.cmd = NULL;
1212 host->base = ioremap(memres->start, PAGE_SIZE);
1218 host->cmd_irqres = cmd_irqres;
1219 host->memres = memres;
1220 host->dmares = dmares;
1221 spin_lock_init(&host->lock);
1223 tasklet_init(&host->dma_tlet, msmsdcc_dma_complete_tlet,
1224 (unsigned long)host);
1229 ret = msmsdcc_init_dma(host);
1233 /* Get our clocks */
1234 host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1235 if (IS_ERR(host->pclk)) {
1236 ret = PTR_ERR(host->pclk);
1240 host->clk = clk_get(&pdev->dev, "sdc_clk");
1241 if (IS_ERR(host->clk)) {
1242 ret = PTR_ERR(host->clk);
1246 ret = clk_set_rate(host->clk, msmsdcc_fmin);
1248 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
1253 ret = msmsdcc_enable_clocks(host);
1257 host->pclk_rate = clk_get_rate(host->pclk);
1258 host->clk_rate = clk_get_rate(host->clk);
1261 * Setup MMC host structure
1263 mmc->ops = &msmsdcc_ops;
1264 mmc->f_min = msmsdcc_fmin;
1265 mmc->f_max = msmsdcc_fmax;
1266 mmc->ocr_avail = plat->ocr_mask;
1269 mmc->caps |= MMC_CAP_4_BIT_DATA;
1270 if (msmsdcc_sdioirq)
1271 mmc->caps |= MMC_CAP_SDIO_IRQ;
1272 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1274 mmc->max_segs = NR_SG;
1275 mmc->max_blk_size = 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1276 mmc->max_blk_count = 65536;
1278 mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */
1279 mmc->max_seg_size = mmc->max_req_size;
1281 msmsdcc_writel(host, 0, MMCIMASK0);
1282 msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
1284 msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
1285 host->saved_irq0mask = MCI_IRQENABLE;
1288 * Setup card detect change
1291 memset(&host->timer, 0, sizeof(host->timer));
1293 if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1294 unsigned long irqflags = IRQF_SHARED |
1295 (stat_irqres->flags & IRQF_TRIGGER_MASK);
1297 host->stat_irq = stat_irqres->start;
1298 ret = request_irq(host->stat_irq,
1299 msmsdcc_platform_status_irq,
1301 DRIVER_NAME " (slot)",
1304 pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1305 mmc_hostname(mmc), host->stat_irq, ret);
1308 } else if (plat->register_status_notify) {
1309 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1310 } else if (!plat->status)
1311 pr_err("%s: No card detect facilities available\n",
1314 init_timer(&host->timer);
1315 host->timer.data = (unsigned long)host;
1316 host->timer.function = msmsdcc_check_status;
1317 host->timer.expires = jiffies + HZ;
1318 add_timer(&host->timer);
1322 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1323 host->eject = !host->oldstat;
1326 init_timer(&host->busclk_timer);
1327 host->busclk_timer.data = (unsigned long) host;
1328 host->busclk_timer.function = msmsdcc_busclk_expired;
1330 ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1331 DRIVER_NAME " (cmd)", host);
1335 ret = request_irq(cmd_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1336 DRIVER_NAME " (pio)", host);
1340 mmc_set_drvdata(pdev, mmc);
1343 pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1344 mmc_hostname(mmc), (unsigned long long)memres->start,
1345 (unsigned int) cmd_irqres->start,
1346 (unsigned int) host->stat_irq, host->dma.channel);
1347 pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1348 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1349 pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1350 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1351 pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1352 pr_info("%s: Power save feature enable = %d\n",
1353 mmc_hostname(mmc), msmsdcc_pwrsave);
1355 if (host->dma.channel != -1) {
1356 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1357 mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1358 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1359 mmc_hostname(mmc), host->dma.cmd_busaddr,
1360 host->dma.cmdptr_busaddr);
1362 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
1363 if (host->timer.function)
1364 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
1368 free_irq(cmd_irqres->start, host);
1371 free_irq(host->stat_irq, host);
1373 msmsdcc_disable_clocks(host, 0);
1377 clk_put(host->pclk);
1379 dma_free_coherent(NULL, sizeof(struct msmsdcc_nc_dmadata),
1380 host->dma.nc, host->dma.nc_busaddr);
1382 tasklet_kill(&host->dma_tlet);
1383 iounmap(host->base);
1391 #ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
1393 do_resume_work(struct work_struct *work)
1395 struct msmsdcc_host *host =
1396 container_of(work, struct msmsdcc_host, resume_task);
1397 struct mmc_host *mmc = host->mmc;
1400 mmc_resume_host(mmc);
1402 enable_irq(host->stat_irq);
1409 msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1411 struct mmc_host *mmc = mmc_get_drvdata(dev);
1415 struct msmsdcc_host *host = mmc_priv(mmc);
1418 disable_irq(host->stat_irq);
1420 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1421 rc = mmc_suspend_host(mmc);
1423 msmsdcc_writel(host, 0, MMCIMASK0);
1425 msmsdcc_disable_clocks(host, 0);
1431 msmsdcc_resume(struct platform_device *dev)
1433 struct mmc_host *mmc = mmc_get_drvdata(dev);
1436 struct msmsdcc_host *host = mmc_priv(mmc);
1438 msmsdcc_enable_clocks(host);
1440 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
1442 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1443 mmc_resume_host(mmc);
1445 enable_irq(host->stat_irq);
1447 msmsdcc_disable_clocks(host, 1);
1453 #define msmsdcc_suspend 0
1454 #define msmsdcc_resume 0
1457 static struct platform_driver msmsdcc_driver = {
1458 .probe = msmsdcc_probe,
1459 .suspend = msmsdcc_suspend,
1460 .resume = msmsdcc_resume,
1466 static int __init msmsdcc_init(void)
1468 return platform_driver_register(&msmsdcc_driver);
1471 static void __exit msmsdcc_exit(void)
1473 platform_driver_unregister(&msmsdcc_driver);
1476 module_init(msmsdcc_init);
1477 module_exit(msmsdcc_exit);
1479 MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1480 MODULE_LICENSE("GPL");