drivers/mmc/host/msm_sdcc.c

   1 /*
   2  *  linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
   3  *
   4  *  Copyright (C) 2007 Google Inc,
   5  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
   6  *  Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Based on mmci.c
  13  *
  14  * Author: San Mehat (san@android.com)
  15  *
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/init.h>
  21 #include <linux/ioport.h>
  22 #include <linux/device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/err.h>
  26 #include <linux/highmem.h>
  27 #include <linux/log2.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/mmc/card.h>
  30 #include <linux/mmc/sdio.h>
  31 #include <linux/clk.h>
  32 #include <linux/scatterlist.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/debugfs.h>
  36 #include <linux/io.h>
  37 #include <linux/memory.h>
  38 #include <linux/gfp.h>
  39
  40 #include <asm/cacheflush.h>
  41 #include <asm/div64.h>
  42 #include <asm/sizes.h>
  43
  44 #include <mach/mmc.h>
  45 #include <mach/msm_iomap.h>
  46 #include <mach/dma.h>
  47
  48 #include "msm_sdcc.h"
  49
  50 #define DRIVER_NAME "msm-sdcc"
  51
  52 #define BUSCLK_PWRSAVE 1
  53 #define BUSCLK_TIMEOUT (HZ)
  54 static unsigned int msmsdcc_fmin = 144000;
  55 static unsigned int msmsdcc_fmax = 50000000;
  56 static unsigned int msmsdcc_4bit = 1;
  57 static unsigned int msmsdcc_pwrsave = 1;
  58 static unsigned int msmsdcc_piopoll = 1;
  59 static unsigned int msmsdcc_sdioirq;
  60
  61 #define PIO_SPINMAX 30
  62 #define CMD_SPINMAX 20
  63
  64
  65 static inline void
  66 msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
  67 {
  68         WARN_ON(!host->clks_on);
  69
  70         BUG_ON(host->curr.mrq);
  71
  72         if (deferr) {
  73                 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
  74         } else {
  75                 del_timer_sync(&host->busclk_timer);
  76                 /* Need to check clks_on again in case the busclk
  77                  * timer fired
  78                  */
  79                 if (host->clks_on) {
  80                         clk_disable(host->clk);
  81                         clk_disable(host->pclk);
  82                         host->clks_on = 0;
  83                 }
  84         }
  85 }
  86
  87 static inline int
  88 msmsdcc_enable_clocks(struct msmsdcc_host *host)
  89 {
  90         int rc;
  91
  92         del_timer_sync(&host->busclk_timer);
  93
  94         if (!host->clks_on) {
  95                 rc = clk_enable(host->pclk);
  96                 if (rc)
  97                         return rc;
  98                 rc = clk_enable(host->clk);
  99                 if (rc) {
 100                         clk_disable(host->pclk);
 101                         return rc;
 102                 }
 103                 udelay(1 + ((3 * USEC_PER_SEC) /
 104                        (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
 105                 host->clks_on = 1;
 106         }
 107         return 0;
 108 }
 109
 110 static inline unsigned int
 111 msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
 112 {
 113         return readl(host->base + reg);
 114 }
 115
 116 static inline void
 117 msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
 118 {
 119         writel(data, host->base + reg);
 120         /* 3 clk delay required! */
 121         udelay(1 + ((3 * USEC_PER_SEC) /
 122                (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
 123 }
 124
 125 static void
 126 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
 127                       u32 c);
 128
 129 static void
 130 msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
 131 {
 132         BUG_ON(host->curr.data);
 133
 134         host->curr.mrq = NULL;
 135         host->curr.cmd = NULL;
 136
 137         if (mrq->data)
 138                 mrq->data->bytes_xfered = host->curr.data_xfered;
 139         if (mrq->cmd->error == -ETIMEDOUT)
 140                 mdelay(5);
 141
 142 #if BUSCLK_PWRSAVE
 143         msmsdcc_disable_clocks(host, 1);
 144 #endif
 145         /*
 146          * Need to drop the host lock here; mmc_request_done may call
 147          * back into the driver...
 148          */
 149         spin_unlock(&host->lock);
 150         mmc_request_done(host->mmc, mrq);
 151         spin_lock(&host->lock);
 152 }
 153
 154 static void
 155 msmsdcc_stop_data(struct msmsdcc_host *host)
 156 {
 157         host->curr.data = NULL;
 158         host->curr.got_dataend = host->curr.got_datablkend = 0;
 159 }
 160
 161 uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
 162 {
 163         return host->memres->start + MMCIFIFO;
 164 }
 165
 166 static inline void
 167 msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
 168        msmsdcc_writel(host, arg, MMCIARGUMENT);
 169        msmsdcc_writel(host, c, MMCICOMMAND);
 170 }
 171
 172 static void
 173 msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
 174 {
 175         struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
 176
 177         msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
 178         msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
 179                        MMCIDATALENGTH);
 180         msmsdcc_writel(host, host->cmd_pio_irqmask, MMCIMASK1);
 181         msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
 182
 183         if (host->cmd_cmd) {
 184                 msmsdcc_start_command_exec(host,
 185                                            (u32) host->cmd_cmd->arg,
 186                                            (u32) host->cmd_c);
 187         }
 188         host->dma.active = 1;
 189 }
 190
 191 static void
 192 msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
 193                           unsigned int result,
 194                           struct msm_dmov_errdata *err)
 195 {
 196         struct msmsdcc_dma_data *dma_data =
 197                 container_of(cmd, struct msmsdcc_dma_data, hdr);
 198         struct msmsdcc_host     *host = dma_data->host;
 199         unsigned long           flags;
 200         struct mmc_request      *mrq;
 201
 202         spin_lock_irqsave(&host->lock, flags);
 203         host->dma.active = 0;
 204
 205         mrq = host->curr.mrq;
 206         BUG_ON(!mrq);
 207         WARN_ON(!mrq->data);
 208
 209         if (!(result & DMOV_RSLT_VALID)) {
 210                 pr_err("msmsdcc: Invalid DataMover result\n");
 211                 goto out;
 212         }
 213
 214         if (result & DMOV_RSLT_DONE) {
 215                 host->curr.data_xfered = host->curr.xfer_size;
 216         } else {
 217                 /* Error or flush  */
 218                 if (result & DMOV_RSLT_ERROR)
 219                         pr_err("%s: DMA error (0x%.8x)\n",
 220                                mmc_hostname(host->mmc), result);
 221                 if (result & DMOV_RSLT_FLUSH)
 222                         pr_err("%s: DMA channel flushed (0x%.8x)\n",
 223                                mmc_hostname(host->mmc), result);
 224                 if (err)
 225                         pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
 226                                err->flush[0], err->flush[1], err->flush[2],
 227                                err->flush[3], err->flush[4], err->flush[5]);
 228                 if (!mrq->data->error)
 229                         mrq->data->error = -EIO;
 230         }
 231         dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
 232                      host->dma.dir);
 233
 234         if (host->curr.user_pages) {
 235                 struct scatterlist *sg = host->dma.sg;
 236                 int i;
 237
 238                 for (i = 0; i < host->dma.num_ents; i++)
 239                         flush_dcache_page(sg_page(sg++));
 240         }
 241
 242         host->dma.sg = NULL;
 243         host->dma.busy = 0;
 244
 245         if ((host->curr.got_dataend && host->curr.got_datablkend)
 246              || mrq->data->error) {
 247
 248                 /*
 249                  * If we've already gotten our DATAEND / DATABLKEND
 250                  * for this request, then complete it through here.
 251                  */
 252                 msmsdcc_stop_data(host);
 253
 254                 if (!mrq->data->error)
 255                         host->curr.data_xfered = host->curr.xfer_size;
 256                 if (!mrq->data->stop || mrq->cmd->error) {
 257                         host->curr.mrq = NULL;
 258                         host->curr.cmd = NULL;
 259                         mrq->data->bytes_xfered = host->curr.data_xfered;
 260
 261                         spin_unlock_irqrestore(&host->lock, flags);
 262 #if BUSCLK_PWRSAVE
 263                         msmsdcc_disable_clocks(host, 1);
 264 #endif
 265                         mmc_request_done(host->mmc, mrq);
 266                         return;
 267                 } else
 268                         msmsdcc_start_command(host, mrq->data->stop, 0);
 269         }
 270
 271 out:
 272         spin_unlock_irqrestore(&host->lock, flags);
 273         return;
 274 }
 275
 276 static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
 277 {
 278         if (host->dma.channel == -1)
 279                 return -ENOENT;
 280
 281         if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
 282                 return -EINVAL;
 283         if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
 284                 return -EINVAL;
 285         return 0;
 286 }
 287
 288 static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
 289 {
 290         struct msmsdcc_nc_dmadata *nc;
 291         dmov_box *box;
 292         uint32_t rows;
 293         uint32_t crci;
 294         unsigned int n;
 295         int i, rc;
 296         struct scatterlist *sg = data->sg;
 297
 298         rc = validate_dma(host, data);
 299         if (rc)
 300                 return rc;
 301
 302         host->dma.sg = data->sg;
 303         host->dma.num_ents = data->sg_len;
 304
 305        BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
 306
 307         nc = host->dma.nc;
 308
 309         switch (host->pdev_id) {
 310         case 1:
 311                 crci = MSMSDCC_CRCI_SDC1;
 312                 break;
 313         case 2:
 314                 crci = MSMSDCC_CRCI_SDC2;
 315                 break;
 316         case 3:
 317                 crci = MSMSDCC_CRCI_SDC3;
 318                 break;
 319         case 4:
 320                 crci = MSMSDCC_CRCI_SDC4;
 321                 break;
 322         default:
 323                 host->dma.sg = NULL;
 324                 host->dma.num_ents = 0;
 325                 return -ENOENT;
 326         }
 327
 328         if (data->flags & MMC_DATA_READ)
 329                 host->dma.dir = DMA_FROM_DEVICE;
 330         else
 331                 host->dma.dir = DMA_TO_DEVICE;
 332
 333         host->curr.user_pages = 0;
 334
 335         box = &nc->cmd[0];
 336         for (i = 0; i < host->dma.num_ents; i++) {
 337                 box->cmd = CMD_MODE_BOX;
 338
 339         /* Initialize sg dma address */
 340         sg->dma_address = page_to_dma(mmc_dev(host->mmc), sg_page(sg))
 341                                 + sg->offset;
 342
 343         if (i == (host->dma.num_ents - 1))
 344                         box->cmd |= CMD_LC;
 345                 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
 346                         (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
 347                         (sg_dma_len(sg) / MCI_FIFOSIZE) ;
 348
 349                 if (data->flags & MMC_DATA_READ) {
 350                         box->src_row_addr = msmsdcc_fifo_addr(host);
 351                         box->dst_row_addr = sg_dma_address(sg);
 352
 353                         box->src_dst_len = (MCI_FIFOSIZE << 16) |
 354                                            (MCI_FIFOSIZE);
 355                         box->row_offset = MCI_FIFOSIZE;
 356
 357                         box->num_rows = rows * ((1 << 16) + 1);
 358                         box->cmd |= CMD_SRC_CRCI(crci);
 359                 } else {
 360                         box->src_row_addr = sg_dma_address(sg);
 361                         box->dst_row_addr = msmsdcc_fifo_addr(host);
 362
 363                         box->src_dst_len = (MCI_FIFOSIZE << 16) |
 364                                            (MCI_FIFOSIZE);
 365                         box->row_offset = (MCI_FIFOSIZE << 16);
 366
 367                         box->num_rows = rows * ((1 << 16) + 1);
 368                         box->cmd |= CMD_DST_CRCI(crci);
 369                 }
 370                 box++;
 371                 sg++;
 372         }
 373
 374         /* location of command block must be 64 bit aligned */
 375         BUG_ON(host->dma.cmd_busaddr & 0x07);
 376
 377         nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
 378         host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
 379                                DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
 380         host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
 381
 382         n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
 383                         host->dma.num_ents, host->dma.dir);
 384 /* dsb inside dma_map_sg will write nc out to mem as well */
 385
 386         if (n != host->dma.num_ents) {
 387                 printk(KERN_ERR "%s: Unable to map in all sg elements\n",
 388                         mmc_hostname(host->mmc));
 389                 host->dma.sg = NULL;
 390                 host->dma.num_ents = 0;
 391                 return -ENOMEM;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static int
 398 snoop_cccr_abort(struct mmc_command *cmd)
 399 {
 400         if ((cmd->opcode == 52) &&
 401             (cmd->arg & 0x80000000) &&
 402             (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT))
 403                 return 1;
 404         return 0;
 405 }
 406
 407 static void
 408 msmsdcc_start_command_deferred(struct msmsdcc_host *host,
 409                                 struct mmc_command *cmd, u32 *c)
 410 {
 411         *c |= (cmd->opcode | MCI_CPSM_ENABLE);
 412
 413         if (cmd->flags & MMC_RSP_PRESENT) {
 414                 if (cmd->flags & MMC_RSP_136)
 415                         *c |= MCI_CPSM_LONGRSP;
 416                 *c |= MCI_CPSM_RESPONSE;
 417         }
 418
 419         if (/*interrupt*/0)
 420                 *c |= MCI_CPSM_INTERRUPT;
 421
 422         if ((((cmd->opcode == 17) || (cmd->opcode == 18))  ||
 423              ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
 424               (cmd->opcode == 53))
 425                 *c |= MCI_CSPM_DATCMD;
 426
 427         if (cmd == cmd->mrq->stop)
 428                 *c |= MCI_CSPM_MCIABORT;
 429
 430         if (snoop_cccr_abort(cmd))
 431                 *c |= MCI_CSPM_MCIABORT;
 432
 433         if (host->curr.cmd != NULL) {
 434                 printk(KERN_ERR "%s: Overlapping command requests\n",
 435                         mmc_hostname(host->mmc));
 436         }
 437         host->curr.cmd = cmd;
 438 }
 439
 440 static void
 441 msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
 442                         struct mmc_command *cmd, u32 c)
 443 {
 444         unsigned int datactrl, timeout;
 445         unsigned long long clks;
 446         unsigned int pio_irqmask = 0;
 447
 448         host->curr.data = data;
 449         host->curr.xfer_size = data->blksz * data->blocks;
 450         host->curr.xfer_remain = host->curr.xfer_size;
 451         host->curr.data_xfered = 0;
 452         host->curr.got_dataend = 0;
 453         host->curr.got_datablkend = 0;
 454
 455         memset(&host->pio, 0, sizeof(host->pio));
 456
 457         datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
 458
 459         if (!msmsdcc_config_dma(host, data))
 460                 datactrl |= MCI_DPSM_DMAENABLE;
 461         else {
 462                 host->pio.sg = data->sg;
 463                 host->pio.sg_len = data->sg_len;
 464                 host->pio.sg_off = 0;
 465
 466                 if (data->flags & MMC_DATA_READ) {
 467                         pio_irqmask = MCI_RXFIFOHALFFULLMASK;
 468                         if (host->curr.xfer_remain < MCI_FIFOSIZE)
 469                                 pio_irqmask |= MCI_RXDATAAVLBLMASK;
 470                 } else
 471                         pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
 472         }
 473
 474         if (data->flags & MMC_DATA_READ)
 475                 datactrl |= MCI_DPSM_DIRECTION;
 476
 477         clks = (unsigned long long)data->timeout_ns * host->clk_rate;
 478         do_div(clks, NSEC_PER_SEC);
 479         timeout = data->timeout_clks + (unsigned int)clks*2 ;
 480
 481         if (datactrl & MCI_DPSM_DMAENABLE) {
 482                 /* Save parameters for the exec function */
 483                 host->cmd_timeout = timeout;
 484                 host->cmd_pio_irqmask = pio_irqmask;
 485                 host->cmd_datactrl = datactrl;
 486                 host->cmd_cmd = cmd;
 487
 488                 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
 489                 host->dma.hdr.data = (void *)host;
 490                 host->dma.busy = 1;
 491
 492                 if (cmd) {
 493                         msmsdcc_start_command_deferred(host, cmd, &c);
 494                         host->cmd_c = c;
 495                 }
 496                 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
 497         } else {
 498                 msmsdcc_writel(host, timeout, MMCIDATATIMER);
 499
 500                 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
 501
 502                 msmsdcc_writel(host, pio_irqmask, MMCIMASK1);
 503                 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
 504
 505                 if (cmd) {
 506                         /* Daisy-chain the command if requested */
 507                         msmsdcc_start_command(host, cmd, c);
 508                 }
 509         }
 510 }
 511
 512 static void
 513 msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
 514 {
 515         if (cmd == cmd->mrq->stop)
 516                 c |= MCI_CSPM_MCIABORT;
 517
 518         host->stats.cmds++;
 519
 520         msmsdcc_start_command_deferred(host, cmd, &c);
 521         msmsdcc_start_command_exec(host, cmd->arg, c);
 522 }
 523
 524 static void
 525 msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
 526                  unsigned int status)
 527 {
 528         if (status & MCI_DATACRCFAIL) {
 529                 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
 530                 pr_err("%s: opcode 0x%.8x\n", __func__,
 531                        data->mrq->cmd->opcode);
 532                 pr_err("%s: blksz %d, blocks %d\n", __func__,
 533                        data->blksz, data->blocks);
 534                 data->error = -EILSEQ;
 535         } else if (status & MCI_DATATIMEOUT) {
 536                 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
 537                 data->error = -ETIMEDOUT;
 538         } else if (status & MCI_RXOVERRUN) {
 539                 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
 540                 data->error = -EIO;
 541         } else if (status & MCI_TXUNDERRUN) {
 542                 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
 543                 data->error = -EIO;
 544         } else {
 545                 pr_err("%s: Unknown error (0x%.8x)\n",
 546                        mmc_hostname(host->mmc), status);
 547                 data->error = -EIO;
 548         }
 549 }
 550
 551
 552 static int
 553 msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
 554 {
 555         uint32_t        *ptr = (uint32_t *) buffer;
 556         int             count = 0;
 557
 558         while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
 559                 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
 560                 ptr++;
 561                 count += sizeof(uint32_t);
 562
 563                 remain -=  sizeof(uint32_t);
 564                 if (remain == 0)
 565                         break;
 566         }
 567         return count;
 568 }
 569
 570 static int
 571 msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
 572                   unsigned int remain, u32 status)
 573 {
 574         void __iomem *base = host->base;
 575         char *ptr = buffer;
 576
 577         do {
 578                 unsigned int count, maxcnt;
 579
 580                 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
 581                                                     MCI_FIFOHALFSIZE;
 582                 count = min(remain, maxcnt);
 583
 584                 writesl(base + MMCIFIFO, ptr, count >> 2);
 585                 ptr += count;
 586                 remain -= count;
 587
 588                 if (remain == 0)
 589                         break;
 590
 591                 status = msmsdcc_readl(host, MMCISTATUS);
 592         } while (status & MCI_TXFIFOHALFEMPTY);
 593
 594         return ptr - buffer;
 595 }
 596
 597 static int
 598 msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
 599 {
 600         while (maxspin) {
 601                 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
 602                         return 0;
 603                 udelay(1);
 604                 --maxspin;
 605         }
 606         return -ETIMEDOUT;
 607 }
 608
 609 static irqreturn_t
 610 msmsdcc_pio_irq(int irq, void *dev_id)
 611 {
 612         struct msmsdcc_host     *host = dev_id;
 613         uint32_t                status;
 614
 615         status = msmsdcc_readl(host, MMCISTATUS);
 616
 617         do {
 618                 unsigned long flags;
 619                 unsigned int remain, len;
 620                 char *buffer;
 621
 622                 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
 623                         if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
 624                                 break;
 625
 626                         if (msmsdcc_spin_on_status(host,
 627                                                    (MCI_TXFIFOHALFEMPTY |
 628                                                    MCI_RXDATAAVLBL),
 629                                                    PIO_SPINMAX)) {
 630                                 break;
 631                         }
 632                 }
 633
 634                 /* Map the current scatter buffer */
 635                 local_irq_save(flags);
 636                 buffer = kmap_atomic(sg_page(host->pio.sg),
 637                                      KM_BIO_SRC_IRQ) + host->pio.sg->offset;
 638                 buffer += host->pio.sg_off;
 639                 remain = host->pio.sg->length - host->pio.sg_off;
 640                 len = 0;
 641                 if (status & MCI_RXACTIVE)
 642                         len = msmsdcc_pio_read(host, buffer, remain);
 643                 if (status & MCI_TXACTIVE)
 644                         len = msmsdcc_pio_write(host, buffer, remain, status);
 645
 646                 /* Unmap the buffer */
 647                 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 648                 local_irq_restore(flags);
 649
 650                 host->pio.sg_off += len;
 651                 host->curr.xfer_remain -= len;
 652                 host->curr.data_xfered += len;
 653                 remain -= len;
 654
 655                 if (remain == 0) {
 656                         /* This sg page is full - do some housekeeping */
 657                         if (status & MCI_RXACTIVE && host->curr.user_pages)
 658                                 flush_dcache_page(sg_page(host->pio.sg));
 659
 660                         if (!--host->pio.sg_len) {
 661                                 memset(&host->pio, 0, sizeof(host->pio));
 662                                 break;
 663                         }
 664
 665                         /* Advance to next sg */
 666                         host->pio.sg++;
 667                         host->pio.sg_off = 0;
 668                 }
 669
 670                 status = msmsdcc_readl(host, MMCISTATUS);
 671         } while (1);
 672
 673         if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
 674                 msmsdcc_writel(host, MCI_RXDATAAVLBLMASK, MMCIMASK1);
 675
 676         if (!host->curr.xfer_remain)
 677                 msmsdcc_writel(host, 0, MMCIMASK1);
 678
 679         return IRQ_HANDLED;
 680 }
 681
 682 static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
 683 {
 684         struct mmc_command *cmd = host->curr.cmd;
 685
 686         host->curr.cmd = NULL;
 687         cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
 688         cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
 689         cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
 690         cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
 691
 692         if (status & MCI_CMDTIMEOUT) {
 693                 cmd->error = -ETIMEDOUT;
 694         } else if (status & MCI_CMDCRCFAIL &&
 695                    cmd->flags & MMC_RSP_CRC) {
 696                 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
 697                 cmd->error = -EILSEQ;
 698         }
 699
 700         if (!cmd->data || cmd->error) {
 701                 if (host->curr.data && host->dma.sg)
 702                         msm_dmov_stop_cmd(host->dma.channel,
 703                                           &host->dma.hdr, 0);
 704                 else if (host->curr.data) { /* Non DMA */
 705                         msmsdcc_stop_data(host);
 706                         msmsdcc_request_end(host, cmd->mrq);
 707                 } else /* host->data == NULL */
 708                         msmsdcc_request_end(host, cmd->mrq);
 709         } else if (cmd->data)
 710                 if (!(cmd->data->flags & MMC_DATA_READ))
 711                         msmsdcc_start_data(host, cmd->data,
 712                                                 NULL, 0);
 713 }
 714
 715 static void
 716 msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
 717                         void __iomem *base)
 718 {
 719         struct mmc_data *data = host->curr.data;
 720
 721         if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
 722                       MCI_CMDTIMEOUT) && host->curr.cmd) {
 723                 msmsdcc_do_cmdirq(host, status);
 724         }
 725
 726         if (!data)
 727                 return;
 728
 729         /* Check for data errors */
 730         if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
 731                       MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
 732                 msmsdcc_data_err(host, data, status);
 733                 host->curr.data_xfered = 0;
 734                 if (host->dma.sg)
 735                         msm_dmov_stop_cmd(host->dma.channel,
 736                                           &host->dma.hdr, 0);
 737                 else {
 738                         if (host->curr.data)
 739                                 msmsdcc_stop_data(host);
 740                         if (!data->stop)
 741                                 msmsdcc_request_end(host, data->mrq);
 742                         else
 743                                 msmsdcc_start_command(host, data->stop, 0);
 744                 }
 745         }
 746
 747         /* Check for data done */
 748         if (!host->curr.got_dataend && (status & MCI_DATAEND))
 749                 host->curr.got_dataend = 1;
 750
 751         if (!host->curr.got_datablkend && (status & MCI_DATABLOCKEND))
 752                 host->curr.got_datablkend = 1;
 753
 754         /*
 755          * If DMA is still in progress, we complete via the completion handler
 756          */
 757         if (host->curr.got_dataend && host->curr.got_datablkend &&
 758             !host->dma.busy) {
 759                 /*
 760                  * There appears to be an issue in the controller where
 761                  * if you request a small block transfer (< fifo size),
 762                  * you may get your DATAEND/DATABLKEND irq without the
 763                  * PIO data irq.
 764                  *
 765                  * Check to see if there is still data to be read,
 766                  * and simulate a PIO irq.
 767                  */
 768                 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
 769                         msmsdcc_pio_irq(1, host);
 770
 771                 msmsdcc_stop_data(host);
 772                 if (!data->error)
 773                         host->curr.data_xfered = host->curr.xfer_size;
 774
 775                 if (!data->stop)
 776                         msmsdcc_request_end(host, data->mrq);
 777                 else
 778                         msmsdcc_start_command(host, data->stop, 0);
 779         }
 780 }
 781
 782 static irqreturn_t
 783 msmsdcc_irq(int irq, void *dev_id)
 784 {
 785         struct msmsdcc_host     *host = dev_id;
 786         void __iomem            *base = host->base;
 787         u32                     status;
 788         int                     ret = 0;
 789         int                     cardint = 0;
 790
 791         spin_lock(&host->lock);
 792
 793         do {
 794                 status = msmsdcc_readl(host, MMCISTATUS);
 795                 status &= (msmsdcc_readl(host, MMCIMASK0) |
 796                                               MCI_DATABLOCKENDMASK);
 797                 msmsdcc_writel(host, status, MMCICLEAR);
 798
 799                 if (status & MCI_SDIOINTR)
 800                         status &= ~MCI_SDIOINTR;
 801
 802                 if (!status)
 803                         break;
 804
 805                 msmsdcc_handle_irq_data(host, status, base);
 806
 807                 if (status & MCI_SDIOINTOPER) {
 808                         cardint = 1;
 809                         status &= ~MCI_SDIOINTOPER;
 810                 }
 811                 ret = 1;
 812         } while (status);
 813
 814         spin_unlock(&host->lock);
 815
 816         /*
 817          * We have to delay handling the card interrupt as it calls
 818          * back into the driver.
 819          */
 820         if (cardint)
 821                 mmc_signal_sdio_irq(host->mmc);
 822
 823         return IRQ_RETVAL(ret);
 824 }
 825
 826 static void
 827 msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 828 {
 829         struct msmsdcc_host *host = mmc_priv(mmc);
 830         unsigned long flags;
 831
 832         WARN_ON(host->curr.mrq != NULL);
 833         WARN_ON(host->pwr == 0);
 834
 835         spin_lock_irqsave(&host->lock, flags);
 836
 837         host->stats.reqs++;
 838
 839         if (host->eject) {
 840                 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
 841                         mrq->cmd->error = 0;
 842                         mrq->data->bytes_xfered = mrq->data->blksz *
 843                                                   mrq->data->blocks;
 844                 } else
 845                         mrq->cmd->error = -ENOMEDIUM;
 846
 847                 spin_unlock_irqrestore(&host->lock, flags);
 848                 mmc_request_done(mmc, mrq);
 849                 return;
 850         }
 851
 852         msmsdcc_enable_clocks(host);
 853
 854         host->curr.mrq = mrq;
 855
 856         if (mrq->data && mrq->data->flags & MMC_DATA_READ)
 857                 /* Queue/read data, daisy-chain command when data starts */
 858                 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
 859         else
 860                 msmsdcc_start_command(host, mrq->cmd, 0);
 861
 862         if (host->cmdpoll && !msmsdcc_spin_on_status(host,
 863                                 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
 864                                 CMD_SPINMAX)) {
 865                 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
 866                 msmsdcc_do_cmdirq(host, status);
 867                 msmsdcc_writel(host,
 868                                MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
 869                                MMCICLEAR);
 870                 host->stats.cmdpoll_hits++;
 871         } else {
 872                 host->stats.cmdpoll_misses++;
 873         }
 874         spin_unlock_irqrestore(&host->lock, flags);
 875 }
 876
 877 static void
 878 msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 879 {
 880         struct msmsdcc_host *host = mmc_priv(mmc);
 881         u32 clk = 0, pwr = 0;
 882         int rc;
 883         unsigned long flags;
 884
 885         spin_lock_irqsave(&host->lock, flags);
 886
 887         msmsdcc_enable_clocks(host);
 888
 889         if (ios->clock) {
 890                 if (ios->clock != host->clk_rate) {
 891                         rc = clk_set_rate(host->clk, ios->clock);
 892                         if (rc < 0)
 893                                 pr_err("%s: Error setting clock rate (%d)\n",
 894                                        mmc_hostname(host->mmc), rc);
 895                         else
 896                                 host->clk_rate = ios->clock;
 897                 }
 898                 clk |= MCI_CLK_ENABLE;
 899         }
 900
 901         if (ios->bus_width == MMC_BUS_WIDTH_4)
 902                 clk |= (2 << 10); /* Set WIDEBUS */
 903
 904         if (ios->clock > 400000 && msmsdcc_pwrsave)
 905                 clk |= (1 << 9); /* PWRSAVE */
 906
 907         clk |= (1 << 12); /* FLOW_ENA */
 908         clk |= (1 << 15); /* feedback clock */
 909
 910         if (host->plat->translate_vdd)
 911                 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
 912
 913         switch (ios->power_mode) {
 914         case MMC_POWER_OFF:
 915                 break;
 916         case MMC_POWER_UP:
 917                 pwr |= MCI_PWR_UP;
 918                 break;
 919         case MMC_POWER_ON:
 920                 pwr |= MCI_PWR_ON;
 921                 break;
 922         }
 923
 924         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 925                 pwr |= MCI_OD;
 926
 927         msmsdcc_writel(host, clk, MMCICLOCK);
 928
 929         if (host->pwr != pwr) {
 930                 host->pwr = pwr;
 931                 msmsdcc_writel(host, pwr, MMCIPOWER);
 932         }
 933 #if BUSCLK_PWRSAVE
 934         msmsdcc_disable_clocks(host, 1);
 935 #endif
 936         spin_unlock_irqrestore(&host->lock, flags);
 937 }
 938
 939 static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 940 {
 941         struct msmsdcc_host *host = mmc_priv(mmc);
 942         unsigned long flags;
 943         u32 status;
 944
 945         spin_lock_irqsave(&host->lock, flags);
 946         if (msmsdcc_sdioirq == 1) {
 947                 status = msmsdcc_readl(host, MMCIMASK0);
 948                 if (enable)
 949                         status |= MCI_SDIOINTOPERMASK;
 950                 else
 951                         status &= ~MCI_SDIOINTOPERMASK;
 952                 host->saved_irq0mask = status;
 953                 msmsdcc_writel(host, status, MMCIMASK0);
 954         }
 955         spin_unlock_irqrestore(&host->lock, flags);
 956 }
 957
 958 static const struct mmc_host_ops msmsdcc_ops = {
 959         .request        = msmsdcc_request,
 960         .set_ios        = msmsdcc_set_ios,
 961         .enable_sdio_irq = msmsdcc_enable_sdio_irq,
 962 };
 963
 964 static void
 965 msmsdcc_check_status(unsigned long data)
 966 {
 967         struct msmsdcc_host *host = (struct msmsdcc_host *)data;
 968         unsigned int status;
 969
 970         if (!host->plat->status) {
 971                 mmc_detect_change(host->mmc, 0);
 972                 goto out;
 973         }
 974
 975         status = host->plat->status(mmc_dev(host->mmc));
 976         host->eject = !status;
 977         if (status ^ host->oldstat) {
 978                 pr_info("%s: Slot status change detected (%d -> %d)\n",
 979                         mmc_hostname(host->mmc), host->oldstat, status);
 980                 if (status)
 981                         mmc_detect_change(host->mmc, (5 * HZ) / 2);
 982                 else
 983                         mmc_detect_change(host->mmc, 0);
 984         }
 985
 986         host->oldstat = status;
 987
 988 out:
 989         if (host->timer.function)
 990                 mod_timer(&host->timer, jiffies + HZ);
 991 }
 992
 993 static irqreturn_t
 994 msmsdcc_platform_status_irq(int irq, void *dev_id)
 995 {
 996         struct msmsdcc_host *host = dev_id;
 997
 998         printk(KERN_DEBUG "%s: %d\n", __func__, irq);
 999         msmsdcc_check_status((unsigned long) host);
1000         return IRQ_HANDLED;
1001 }
1002
1003 static void
1004 msmsdcc_status_notify_cb(int card_present, void *dev_id)
1005 {
1006         struct msmsdcc_host *host = dev_id;
1007
1008         printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
1009                card_present);
1010         msmsdcc_check_status((unsigned long) host);
1011 }
1012
1013 static void
1014 msmsdcc_busclk_expired(unsigned long _data)
1015 {
1016         struct msmsdcc_host     *host = (struct msmsdcc_host *) _data;
1017
1018         if (host->clks_on)
1019                 msmsdcc_disable_clocks(host, 0);
1020 }
1021
1022 static int
1023 msmsdcc_init_dma(struct msmsdcc_host *host)
1024 {
1025         memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1026         host->dma.host = host;
1027         host->dma.channel = -1;
1028
1029         if (!host->dmares)
1030                 return -ENODEV;
1031
1032         host->dma.nc = dma_alloc_coherent(NULL,
1033                                           sizeof(struct msmsdcc_nc_dmadata),
1034                                           &host->dma.nc_busaddr,
1035                                           GFP_KERNEL);
1036         if (host->dma.nc == NULL) {
1037                 pr_err("Unable to allocate DMA buffer\n");
1038                 return -ENOMEM;
1039         }
1040         memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1041         host->dma.cmd_busaddr = host->dma.nc_busaddr;
1042         host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1043                                 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
1044         host->dma.channel = host->dmares->start;
1045
1046         return 0;
1047 }
1048
1049 static int
1050 msmsdcc_probe(struct platform_device *pdev)
1051 {
1052         struct msm_mmc_platform_data *plat = pdev->dev.platform_data;
1053         struct msmsdcc_host *host;
1054         struct mmc_host *mmc;
1055         struct resource *cmd_irqres = NULL;
1056         struct resource *pio_irqres = NULL;
1057         struct resource *stat_irqres = NULL;
1058         struct resource *memres = NULL;
1059         struct resource *dmares = NULL;
1060         int ret;
1061
1062         /* must have platform data */
1063         if (!plat) {
1064                 pr_err("%s: Platform data not available\n", __func__);
1065                 ret = -EINVAL;
1066                 goto out;
1067         }
1068
1069         if (pdev->id < 1 || pdev->id > 4)
1070                 return -EINVAL;
1071
1072         if (pdev->resource == NULL || pdev->num_resources < 2) {
1073                 pr_err("%s: Invalid resource\n", __func__);
1074                 return -ENXIO;
1075         }
1076
1077         memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1078         dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1079         cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1080                                                   "cmd_irq");
1081         pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1082                                                   "pio_irq");
1083         stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1084                                                    "status_irq");
1085
1086         if (!cmd_irqres || !pio_irqres || !memres) {
1087                 pr_err("%s: Invalid resource\n", __func__);
1088                 return -ENXIO;
1089         }
1090
1091         /*
1092          * Setup our host structure
1093          */
1094
1095         mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1096         if (!mmc) {
1097                 ret = -ENOMEM;
1098                 goto out;
1099         }
1100
1101         host = mmc_priv(mmc);
1102         host->pdev_id = pdev->id;
1103         host->plat = plat;
1104         host->mmc = mmc;
1105         host->curr.cmd = NULL;
1106
1107         host->cmdpoll = 1;
1108
1109         host->base = ioremap(memres->start, PAGE_SIZE);
1110         if (!host->base) {
1111                 ret = -ENOMEM;
1112                 goto out;
1113         }
1114
1115         host->cmd_irqres = cmd_irqres;
1116         host->pio_irqres = pio_irqres;
1117         host->memres = memres;
1118         host->dmares = dmares;
1119         spin_lock_init(&host->lock);
1120
1121         /*
1122          * Setup DMA
1123          */
1124         msmsdcc_init_dma(host);
1125
1126         /* Get our clocks */
1127         host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1128         if (IS_ERR(host->pclk)) {
1129                 ret = PTR_ERR(host->pclk);
1130                 goto host_free;
1131         }
1132
1133         host->clk = clk_get(&pdev->dev, "sdc_clk");
1134         if (IS_ERR(host->clk)) {
1135                 ret = PTR_ERR(host->clk);
1136                 goto pclk_put;
1137         }
1138
1139         /* Enable clocks */
1140         ret = msmsdcc_enable_clocks(host);
1141         if (ret)
1142                 goto clk_put;
1143
1144         ret = clk_set_rate(host->clk, msmsdcc_fmin);
1145         if (ret) {
1146                 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
1147                 goto clk_disable;
1148         }
1149
1150         host->pclk_rate = clk_get_rate(host->pclk);
1151         host->clk_rate = clk_get_rate(host->clk);
1152
1153         /*
1154          * Setup MMC host structure
1155          */
1156         mmc->ops = &msmsdcc_ops;
1157         mmc->f_min = msmsdcc_fmin;
1158         mmc->f_max = msmsdcc_fmax;
1159         mmc->ocr_avail = plat->ocr_mask;
1160
1161         if (msmsdcc_4bit)
1162                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1163         if (msmsdcc_sdioirq)
1164                 mmc->caps |= MMC_CAP_SDIO_IRQ;
1165         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1166
1167         mmc->max_segs = NR_SG;
1168         mmc->max_blk_size = 4096;       /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1169         mmc->max_blk_count = 65536;
1170
1171         mmc->max_req_size = 33554432;   /* MCI_DATA_LENGTH is 25 bits */
1172         mmc->max_seg_size = mmc->max_req_size;
1173
1174         msmsdcc_writel(host, 0, MMCIMASK0);
1175         msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
1176
1177         msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
1178         host->saved_irq0mask = MCI_IRQENABLE;
1179
1180         /*
1181          * Setup card detect change
1182          */
1183
1184         memset(&host->timer, 0, sizeof(host->timer));
1185
1186         if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1187                 unsigned long irqflags = IRQF_SHARED |
1188                         (stat_irqres->flags & IRQF_TRIGGER_MASK);
1189
1190                 host->stat_irq = stat_irqres->start;
1191                 ret = request_irq(host->stat_irq,
1192                                   msmsdcc_platform_status_irq,
1193                                   irqflags,
1194                                   DRIVER_NAME " (slot)",
1195                                   host);
1196                 if (ret) {
1197                         pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1198                                mmc_hostname(mmc), host->stat_irq, ret);
1199                         goto clk_disable;
1200                 }
1201         } else if (plat->register_status_notify) {
1202                 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1203         } else if (!plat->status)
1204                 pr_err("%s: No card detect facilities available\n",
1205                        mmc_hostname(mmc));
1206         else {
1207                 init_timer(&host->timer);
1208                 host->timer.data = (unsigned long)host;
1209                 host->timer.function = msmsdcc_check_status;
1210                 host->timer.expires = jiffies + HZ;
1211                 add_timer(&host->timer);
1212         }
1213
1214         if (plat->status) {
1215                 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1216                 host->eject = !host->oldstat;
1217         }
1218
1219         init_timer(&host->busclk_timer);
1220         host->busclk_timer.data = (unsigned long) host;
1221         host->busclk_timer.function = msmsdcc_busclk_expired;
1222
1223         ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1224                           DRIVER_NAME " (cmd)", host);
1225         if (ret)
1226                 goto stat_irq_free;
1227
1228         ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1229                           DRIVER_NAME " (pio)", host);
1230         if (ret)
1231                 goto cmd_irq_free;
1232
1233         mmc_set_drvdata(pdev, mmc);
1234         mmc_add_host(mmc);
1235
1236         pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1237                 mmc_hostname(mmc), (unsigned long long)memres->start,
1238                 (unsigned int) cmd_irqres->start,
1239                 (unsigned int) host->stat_irq, host->dma.channel);
1240         pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1241                 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1242         pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1243                 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1244         pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1245         pr_info("%s: Power save feature enable = %d\n",
1246                 mmc_hostname(mmc), msmsdcc_pwrsave);
1247
1248         if (host->dma.channel != -1) {
1249                 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1250                         mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1251                 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1252                         mmc_hostname(mmc), host->dma.cmd_busaddr,
1253                         host->dma.cmdptr_busaddr);
1254         } else
1255                 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
1256         if (host->timer.function)
1257                 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
1258
1259 #if BUSCLK_PWRSAVE
1260         msmsdcc_disable_clocks(host, 1);
1261 #endif
1262         return 0;
1263  cmd_irq_free:
1264         free_irq(cmd_irqres->start, host);
1265  stat_irq_free:
1266         if (host->stat_irq)
1267                 free_irq(host->stat_irq, host);
1268  clk_disable:
1269         msmsdcc_disable_clocks(host, 0);
1270  clk_put:
1271         clk_put(host->clk);
1272  pclk_put:
1273         clk_put(host->pclk);
1274  host_free:
1275         mmc_free_host(mmc);
1276  out:
1277         return ret;
1278 }
1279
1280 #ifdef CONFIG_PM
1281 #ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
1282 static void
1283 do_resume_work(struct work_struct *work)
1284 {
1285         struct msmsdcc_host *host =
1286                 container_of(work, struct msmsdcc_host, resume_task);
1287         struct mmc_host *mmc = host->mmc;
1288
1289         if (mmc) {
1290                 mmc_resume_host(mmc);
1291                 if (host->stat_irq)
1292                         enable_irq(host->stat_irq);
1293         }
1294 }
1295 #endif
1296
1297
1298 static int
1299 msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1300 {
1301         struct mmc_host *mmc = mmc_get_drvdata(dev);
1302         int rc = 0;
1303
1304         if (mmc) {
1305                 struct msmsdcc_host *host = mmc_priv(mmc);
1306
1307                 if (host->stat_irq)
1308                         disable_irq(host->stat_irq);
1309
1310                 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1311                         rc = mmc_suspend_host(mmc);
1312                 if (!rc)
1313                         msmsdcc_writel(host, 0, MMCIMASK0);
1314                 if (host->clks_on)
1315                         msmsdcc_disable_clocks(host, 0);
1316         }
1317         return rc;
1318 }
1319
1320 static int
1321 msmsdcc_resume(struct platform_device *dev)
1322 {
1323         struct mmc_host *mmc = mmc_get_drvdata(dev);
1324
1325         if (mmc) {
1326                 struct msmsdcc_host *host = mmc_priv(mmc);
1327
1328                 msmsdcc_enable_clocks(host);
1329
1330                 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
1331
1332                 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1333                         mmc_resume_host(mmc);
1334                 if (host->stat_irq)
1335                         enable_irq(host->stat_irq);
1336 #if BUSCLK_PWRSAVE
1337                 msmsdcc_disable_clocks(host, 1);
1338 #endif
1339         }
1340         return 0;
1341 }
1342 #else
1343 #define msmsdcc_suspend 0
1344 #define msmsdcc_resume 0
1345 #endif
1346
1347 static struct platform_driver msmsdcc_driver = {
1348         .probe          = msmsdcc_probe,
1349         .suspend        = msmsdcc_suspend,
1350         .resume         = msmsdcc_resume,
1351         .driver         = {
1352                 .name   = "msm_sdcc",
1353         },
1354 };
1355
1356 static int __init msmsdcc_init(void)
1357 {
1358         return platform_driver_register(&msmsdcc_driver);
1359 }
1360
1361 static void __exit msmsdcc_exit(void)
1362 {
1363         platform_driver_unregister(&msmsdcc_driver);
1364 }
1365
1366 module_init(msmsdcc_init);
1367 module_exit(msmsdcc_exit);
1368
1369 MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1370 MODULE_LICENSE("GPL");