drivers/mmc/host/imxmmc.c

   1 /*
   2  *  linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver
   3  *
   4  *  Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
   5  *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
   6  *
   7  *  derived from pxamci.c by Russell King
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/blkdev.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/mmc/host.h>
  23 #include <linux/mmc/card.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/io.h>
  27
  28 #include <asm/dma.h>
  29 #include <asm/irq.h>
  30 #include <asm/sizes.h>
  31 #include <mach/mmc.h>
  32 #include <mach/imx-dma.h>
  33
  34 #include "imxmmc.h"
  35
  36 #define DRIVER_NAME "imx-mmc"
  37
  38 #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
  39                                  INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
  40                                  INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
  41
  42 struct imxmci_host {
  43         struct mmc_host         *mmc;
  44         spinlock_t              lock;
  45         struct resource         *res;
  46         void __iomem            *base;
  47         int                     irq;
  48         imx_dmach_t             dma;
  49         volatile unsigned int   imask;
  50         unsigned int            power_mode;
  51         unsigned int            present;
  52         struct imxmmc_platform_data *pdata;
  53
  54         struct mmc_request      *req;
  55         struct mmc_command      *cmd;
  56         struct mmc_data         *data;
  57
  58         struct timer_list       timer;
  59         struct tasklet_struct   tasklet;
  60         unsigned int            status_reg;
  61         unsigned long           pending_events;
  62         /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
  63         u16                     *data_ptr;
  64         unsigned int            data_cnt;
  65         atomic_t                stuck_timeout;
  66
  67         unsigned int            dma_nents;
  68         unsigned int            dma_size;
  69         unsigned int            dma_dir;
  70         int                     dma_allocated;
  71
  72         unsigned char           actual_bus_width;
  73
  74         int                     prev_cmd_code;
  75
  76         struct clk              *clk;
  77 };
  78
  79 #define IMXMCI_PEND_IRQ_b       0
  80 #define IMXMCI_PEND_DMA_END_b   1
  81 #define IMXMCI_PEND_DMA_ERR_b   2
  82 #define IMXMCI_PEND_WAIT_RESP_b 3
  83 #define IMXMCI_PEND_DMA_DATA_b  4
  84 #define IMXMCI_PEND_CPU_DATA_b  5
  85 #define IMXMCI_PEND_CARD_XCHG_b 6
  86 #define IMXMCI_PEND_SET_INIT_b  7
  87 #define IMXMCI_PEND_STARTED_b   8
  88
  89 #define IMXMCI_PEND_IRQ_m       (1 << IMXMCI_PEND_IRQ_b)
  90 #define IMXMCI_PEND_DMA_END_m   (1 << IMXMCI_PEND_DMA_END_b)
  91 #define IMXMCI_PEND_DMA_ERR_m   (1 << IMXMCI_PEND_DMA_ERR_b)
  92 #define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
  93 #define IMXMCI_PEND_DMA_DATA_m  (1 << IMXMCI_PEND_DMA_DATA_b)
  94 #define IMXMCI_PEND_CPU_DATA_m  (1 << IMXMCI_PEND_CPU_DATA_b)
  95 #define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
  96 #define IMXMCI_PEND_SET_INIT_m  (1 << IMXMCI_PEND_SET_INIT_b)
  97 #define IMXMCI_PEND_STARTED_m   (1 << IMXMCI_PEND_STARTED_b)
  98
  99 static void imxmci_stop_clock(struct imxmci_host *host)
 100 {
 101         int i = 0;
 102         u16 reg;
 103
 104         reg = readw(host->base + MMC_REG_STR_STP_CLK);
 105         writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
 106         while (i < 0x1000) {
 107                 if (!(i & 0x7f)) {
 108                         reg = readw(host->base + MMC_REG_STR_STP_CLK);
 109                         writew(reg | STR_STP_CLK_STOP_CLK,
 110                                         host->base + MMC_REG_STR_STP_CLK);
 111                 }
 112
 113                 reg = readw(host->base + MMC_REG_STATUS);
 114                 if (!(reg & STATUS_CARD_BUS_CLK_RUN)) {
 115                         /* Check twice before cut */
 116                         reg = readw(host->base + MMC_REG_STATUS);
 117                         if (!(reg & STATUS_CARD_BUS_CLK_RUN))
 118                                 return;
 119                 }
 120
 121                 i++;
 122         }
 123         dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
 124 }
 125
 126 static int imxmci_start_clock(struct imxmci_host *host)
 127 {
 128         unsigned int trials = 0;
 129         unsigned int delay_limit = 128;
 130         unsigned long flags;
 131         u16 reg;
 132
 133         reg = readw(host->base + MMC_REG_STR_STP_CLK);
 134         writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
 135
 136         clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
 137
 138         /*
 139          * Command start of the clock, this usually succeeds in less
 140          * then 6 delay loops, but during card detection (low clockrate)
 141          * it takes up to 5000 delay loops and sometimes fails for the first time
 142          */
 143         reg = readw(host->base + MMC_REG_STR_STP_CLK);
 144         writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
 145
 146         do {
 147                 unsigned int delay = delay_limit;
 148
 149                 while (delay--) {
 150                         reg = readw(host->base + MMC_REG_STATUS);
 151                         if (reg & STATUS_CARD_BUS_CLK_RUN)
 152                                 /* Check twice before cut */
 153                                 reg = readw(host->base + MMC_REG_STATUS);
 154                                 if (reg & STATUS_CARD_BUS_CLK_RUN)
 155                                         return 0;
 156
 157                         if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
 158                                 return 0;
 159                 }
 160
 161                 local_irq_save(flags);
 162                 /*
 163                  * Ensure, that request is not doubled under all possible circumstances.
 164                  * It is possible, that cock running state is missed, because some other
 165                  * IRQ or schedule delays this function execution and the clocks has
 166                  * been already stopped by other means (response processing, SDHC HW)
 167                  */
 168                 if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) {
 169                         reg = readw(host->base + MMC_REG_STR_STP_CLK);
 170                         writew(reg | STR_STP_CLK_START_CLK,
 171                                         host->base + MMC_REG_STR_STP_CLK);
 172                 }
 173                 local_irq_restore(flags);
 174
 175         } while (++trials < 256);
 176
 177         dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
 178
 179         return -1;
 180 }
 181
 182 static void imxmci_softreset(struct imxmci_host *host)
 183 {
 184         int i;
 185
 186         /* reset sequence */
 187         writew(0x08, host->base + MMC_REG_STR_STP_CLK);
 188         writew(0x0D, host->base + MMC_REG_STR_STP_CLK);
 189
 190         for (i = 0; i < 8; i++)
 191                 writew(0x05, host->base + MMC_REG_STR_STP_CLK);
 192
 193         writew(0xff, host->base + MMC_REG_RES_TO);
 194         writew(512, host->base + MMC_REG_BLK_LEN);
 195         writew(1, host->base + MMC_REG_NOB);
 196 }
 197
 198 static int imxmci_busy_wait_for_status(struct imxmci_host *host,
 199                                        unsigned int *pstat, unsigned int stat_mask,
 200                                        int timeout, const char *where)
 201 {
 202         int loops = 0;
 203
 204         while (!(*pstat & stat_mask)) {
 205                 loops += 2;
 206                 if (loops >= timeout) {
 207                         dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
 208                                 where, *pstat, stat_mask);
 209                         return -1;
 210                 }
 211                 udelay(2);
 212                 *pstat |= readw(host->base + MMC_REG_STATUS);
 213         }
 214         if (!loops)
 215                 return 0;
 216
 217         /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
 218         if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
 219                 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
 220                          loops, where, *pstat, stat_mask);
 221         return loops;
 222 }
 223
 224 static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
 225 {
 226         unsigned int nob = data->blocks;
 227         unsigned int blksz = data->blksz;
 228         unsigned int datasz = nob * blksz;
 229         int i;
 230
 231         if (data->flags & MMC_DATA_STREAM)
 232                 nob = 0xffff;
 233
 234         host->data = data;
 235         data->bytes_xfered = 0;
 236
 237         writew(nob, host->base + MMC_REG_NOB);
 238         writew(blksz, host->base + MMC_REG_BLK_LEN);
 239
 240         /*
 241          * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
 242          * We are in big troubles for non-512 byte transfers according to note in the paragraph
 243          * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
 244          * The situation is even more complex in reality. The SDHC in not able to handle wll
 245          * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
 246          * This is required for SCR read at least.
 247          */
 248         if (datasz < 512) {
 249                 host->dma_size = datasz;
 250                 if (data->flags & MMC_DATA_READ) {
 251                         host->dma_dir = DMA_FROM_DEVICE;
 252
 253                         /* Hack to enable read SCR */
 254                         writew(1, host->base + MMC_REG_NOB);
 255                         writew(512, host->base + MMC_REG_BLK_LEN);
 256                 } else {
 257                         host->dma_dir = DMA_TO_DEVICE;
 258                 }
 259
 260                 /* Convert back to virtual address */
 261                 host->data_ptr = (u16 *)sg_virt(data->sg);
 262                 host->data_cnt = 0;
 263
 264                 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
 265                 set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
 266
 267                 return;
 268         }
 269
 270         if (data->flags & MMC_DATA_READ) {
 271                 host->dma_dir = DMA_FROM_DEVICE;
 272                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
 273                                              data->sg_len,  host->dma_dir);
 274
 275                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
 276                                  host->res->start + MMC_REG_BUFFER_ACCESS,
 277                                  DMA_MODE_READ);
 278
 279                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
 280                 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
 281         } else {
 282                 host->dma_dir = DMA_TO_DEVICE;
 283
 284                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
 285                                              data->sg_len,  host->dma_dir);
 286
 287                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
 288                                  host->res->start + MMC_REG_BUFFER_ACCESS,
 289                                  DMA_MODE_WRITE);
 290
 291                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
 292                 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
 293         }
 294
 295 #if 1   /* This code is there only for consistency checking and can be disabled in future */
 296         host->dma_size = 0;
 297         for (i = 0; i < host->dma_nents; i++)
 298                 host->dma_size += data->sg[i].length;
 299
 300         if (datasz > host->dma_size) {
 301                 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
 302                         datasz, host->dma_size);
 303         }
 304 #endif
 305
 306         host->dma_size = datasz;
 307
 308         wmb();
 309
 310         set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
 311         clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
 312
 313         /* start DMA engine for read, write is delayed after initial response */
 314         if (host->dma_dir == DMA_FROM_DEVICE)
 315                 imx_dma_enable(host->dma);
 316 }
 317
 318 static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
 319 {
 320         unsigned long flags;
 321         u32 imask;
 322
 323         WARN_ON(host->cmd != NULL);
 324         host->cmd = cmd;
 325
 326         /* Ensure, that clock are stopped else command programming and start fails */
 327         imxmci_stop_clock(host);
 328
 329         if (cmd->flags & MMC_RSP_BUSY)
 330                 cmdat |= CMD_DAT_CONT_BUSY;
 331
 332         switch (mmc_resp_type(cmd)) {
 333         case MMC_RSP_R1: /* short CRC, OPCODE */
 334         case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
 335                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
 336                 break;
 337         case MMC_RSP_R2: /* long 136 bit + CRC */
 338                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
 339                 break;
 340         case MMC_RSP_R3: /* short */
 341                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
 342                 break;
 343         default:
 344                 break;
 345         }
 346
 347         if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
 348                 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
 349
 350         if (host->actual_bus_width == MMC_BUS_WIDTH_4)
 351                 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
 352
 353         writew(cmd->opcode, host->base + MMC_REG_CMD);
 354         writew(cmd->arg >> 16, host->base + MMC_REG_ARGH);
 355         writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL);
 356         writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
 357
 358         atomic_set(&host->stuck_timeout, 0);
 359         set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
 360
 361
 362         imask = IMXMCI_INT_MASK_DEFAULT;
 363         imask &= ~INT_MASK_END_CMD_RES;
 364         if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
 365                 /* imask &= ~INT_MASK_BUF_READY; */
 366                 imask &= ~INT_MASK_DATA_TRAN;
 367                 if (cmdat & CMD_DAT_CONT_WRITE)
 368                         imask &= ~INT_MASK_WRITE_OP_DONE;
 369                 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
 370                         imask &= ~INT_MASK_BUF_READY;
 371         }
 372
 373         spin_lock_irqsave(&host->lock, flags);
 374         host->imask = imask;
 375         writew(host->imask, host->base + MMC_REG_INT_MASK);
 376         spin_unlock_irqrestore(&host->lock, flags);
 377
 378         dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
 379                 cmd->opcode, cmd->opcode, imask);
 380
 381         imxmci_start_clock(host);
 382 }
 383
 384 static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
 385 {
 386         unsigned long flags;
 387
 388         spin_lock_irqsave(&host->lock, flags);
 389
 390         host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
 391                                   IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
 392
 393         host->imask = IMXMCI_INT_MASK_DEFAULT;
 394         writew(host->imask, host->base + MMC_REG_INT_MASK);
 395
 396         spin_unlock_irqrestore(&host->lock, flags);
 397
 398         if (req && req->cmd)
 399                 host->prev_cmd_code = req->cmd->opcode;
 400
 401         host->req = NULL;
 402         host->cmd = NULL;
 403         host->data = NULL;
 404         mmc_request_done(host->mmc, req);
 405 }
 406
 407 static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
 408 {
 409         struct mmc_data *data = host->data;
 410         int data_error;
 411
 412         if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
 413                 imx_dma_disable(host->dma);
 414                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
 415                              host->dma_dir);
 416         }
 417
 418         if (stat & STATUS_ERR_MASK) {
 419                 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
 420                 if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
 421                         data->error = -EILSEQ;
 422                 else if (stat & STATUS_TIME_OUT_READ)
 423                         data->error = -ETIMEDOUT;
 424                 else
 425                         data->error = -EIO;
 426         } else {
 427                 data->bytes_xfered = host->dma_size;
 428         }
 429
 430         data_error = data->error;
 431
 432         host->data = NULL;
 433
 434         return data_error;
 435 }
 436
 437 static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
 438 {
 439         struct mmc_command *cmd = host->cmd;
 440         int i;
 441         u32 a, b, c;
 442         struct mmc_data *data = host->data;
 443
 444         if (!cmd)
 445                 return 0;
 446
 447         host->cmd = NULL;
 448
 449         if (stat & STATUS_TIME_OUT_RESP) {
 450                 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
 451                 cmd->error = -ETIMEDOUT;
 452         } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
 453                 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
 454                 cmd->error = -EILSEQ;
 455         }
 456
 457         if (cmd->flags & MMC_RSP_PRESENT) {
 458                 if (cmd->flags & MMC_RSP_136) {
 459                         for (i = 0; i < 4; i++) {
 460                                 a = readw(host->base + MMC_REG_RES_FIFO);
 461                                 b = readw(host->base + MMC_REG_RES_FIFO);
 462                                 cmd->resp[i] = a << 16 | b;
 463                         }
 464                 } else {
 465                         a = readw(host->base + MMC_REG_RES_FIFO);
 466                         b = readw(host->base + MMC_REG_RES_FIFO);
 467                         c = readw(host->base + MMC_REG_RES_FIFO);
 468                         cmd->resp[0] = a << 24 | b << 8 | c >> 8;
 469                 }
 470         }
 471
 472         dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
 473                 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
 474
 475         if (data && !cmd->error && !(stat & STATUS_ERR_MASK)) {
 476                 if (host->req->data->flags & MMC_DATA_WRITE) {
 477
 478                         /* Wait for FIFO to be empty before starting DMA write */
 479
 480                         stat = readw(host->base + MMC_REG_STATUS);
 481                         if (imxmci_busy_wait_for_status(host, &stat,
 482                                                         STATUS_APPL_BUFF_FE,
 483                                                         40, "imxmci_cmd_done DMA WR") < 0) {
 484                                 cmd->error = -EIO;
 485                                 imxmci_finish_data(host, stat);
 486                                 if (host->req)
 487                                         imxmci_finish_request(host, host->req);
 488                                 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
 489                                          stat);
 490                                 return 0;
 491                         }
 492
 493                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
 494                                 imx_dma_enable(host->dma);
 495                 }
 496         } else {
 497                 struct mmc_request *req;
 498                 imxmci_stop_clock(host);
 499                 req = host->req;
 500
 501                 if (data)
 502                         imxmci_finish_data(host, stat);
 503
 504                 if (req)
 505                         imxmci_finish_request(host, req);
 506                 else
 507                         dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
 508         }
 509
 510         return 1;
 511 }
 512
 513 static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
 514 {
 515         struct mmc_data *data = host->data;
 516         int data_error;
 517
 518         if (!data)
 519                 return 0;
 520
 521         data_error = imxmci_finish_data(host, stat);
 522
 523         if (host->req->stop) {
 524                 imxmci_stop_clock(host);
 525                 imxmci_start_cmd(host, host->req->stop, 0);
 526         } else {
 527                 struct mmc_request *req;
 528                 req = host->req;
 529                 if (req)
 530                         imxmci_finish_request(host, req);
 531                 else
 532                         dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
 533         }
 534
 535         return 1;
 536 }
 537
 538 static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
 539 {
 540         int i;
 541         int burst_len;
 542         int trans_done = 0;
 543         unsigned int stat = *pstat;
 544
 545         if (host->actual_bus_width != MMC_BUS_WIDTH_4)
 546                 burst_len = 16;
 547         else
 548                 burst_len = 64;
 549
 550         /* This is unfortunately required */
 551         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
 552                 stat);
 553
 554         udelay(20);     /* required for clocks < 8MHz*/
 555
 556         if (host->dma_dir == DMA_FROM_DEVICE) {
 557                 imxmci_busy_wait_for_status(host, &stat,
 558                                             STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
 559                                             STATUS_TIME_OUT_READ,
 560                                             50, "imxmci_cpu_driven_data read");
 561
 562                 while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
 563                        !(stat & STATUS_TIME_OUT_READ) &&
 564                        (host->data_cnt < 512)) {
 565
 566                         udelay(20);     /* required for clocks < 8MHz*/
 567
 568                         for (i = burst_len; i >= 2 ; i -= 2) {
 569                                 u16 data;
 570                                 data = readw(host->base + MMC_REG_BUFFER_ACCESS);
 571                                 udelay(10);     /* required for clocks < 8MHz*/
 572                                 if (host->data_cnt+2 <= host->dma_size) {
 573                                         *(host->data_ptr++) = data;
 574                                 } else {
 575                                         if (host->data_cnt < host->dma_size)
 576                                                 *(u8 *)(host->data_ptr) = data;
 577                                 }
 578                                 host->data_cnt += 2;
 579                         }
 580
 581                         stat = readw(host->base + MMC_REG_STATUS);
 582
 583                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
 584                                 host->data_cnt, burst_len, stat);
 585                 }
 586
 587                 if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
 588                         trans_done = 1;
 589
 590                 if (host->dma_size & 0x1ff)
 591                         stat &= ~STATUS_CRC_READ_ERR;
 592
 593                 if (stat & STATUS_TIME_OUT_READ) {
 594                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
 595                                 stat);
 596                         trans_done = -1;
 597                 }
 598
 599         } else {
 600                 imxmci_busy_wait_for_status(host, &stat,
 601                                             STATUS_APPL_BUFF_FE,
 602                                             20, "imxmci_cpu_driven_data write");
 603
 604                 while ((stat & STATUS_APPL_BUFF_FE) &&
 605                        (host->data_cnt < host->dma_size)) {
 606                         if (burst_len >= host->dma_size - host->data_cnt) {
 607                                 burst_len = host->dma_size - host->data_cnt;
 608                                 host->data_cnt = host->dma_size;
 609                                 trans_done = 1;
 610                         } else {
 611                                 host->data_cnt += burst_len;
 612                         }
 613
 614                         for (i = burst_len; i > 0 ; i -= 2)
 615                                 writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS);
 616
 617                         stat = readw(host->base + MMC_REG_STATUS);
 618
 619                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
 620                                 burst_len, stat);
 621                 }
 622         }
 623
 624         *pstat = stat;
 625
 626         return trans_done;
 627 }
 628
 629 static void imxmci_dma_irq(int dma, void *devid)
 630 {
 631         struct imxmci_host *host = devid;
 632         u32 stat = readw(host->base + MMC_REG_STATUS);
 633
 634         atomic_set(&host->stuck_timeout, 0);
 635         host->status_reg = stat;
 636         set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
 637         tasklet_schedule(&host->tasklet);
 638 }
 639
 640 static irqreturn_t imxmci_irq(int irq, void *devid)
 641 {
 642         struct imxmci_host *host = devid;
 643         u32 stat = readw(host->base + MMC_REG_STATUS);
 644         int handled = 1;
 645
 646         writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT,
 647                         host->base + MMC_REG_INT_MASK);
 648
 649         atomic_set(&host->stuck_timeout, 0);
 650         host->status_reg = stat;
 651         set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
 652         set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
 653         tasklet_schedule(&host->tasklet);
 654
 655         return IRQ_RETVAL(handled);
 656 }
 657
 658 static void imxmci_tasklet_fnc(unsigned long data)
 659 {
 660         struct imxmci_host *host = (struct imxmci_host *)data;
 661         u32 stat;
 662         unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
 663         int timeout = 0;
 664
 665         if (atomic_read(&host->stuck_timeout) > 4) {
 666                 char *what;
 667                 timeout = 1;
 668                 stat = readw(host->base + MMC_REG_STATUS);
 669                 host->status_reg = stat;
 670                 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
 671                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
 672                                 what = "RESP+DMA";
 673                         else
 674                                 what = "RESP";
 675                 else
 676                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
 677                                 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
 678                                         what = "DATA";
 679                                 else
 680                                         what = "DMA";
 681                         else
 682                                 what = "???";
 683
 684                 dev_err(mmc_dev(host->mmc),
 685                         "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
 686                         what, stat,
 687                         readw(host->base + MMC_REG_INT_MASK));
 688                 dev_err(mmc_dev(host->mmc),
 689                         "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
 690                         readw(host->base + MMC_REG_CMD_DAT_CONT),
 691                         readw(host->base + MMC_REG_BLK_LEN),
 692                         readw(host->base + MMC_REG_NOB),
 693                         CCR(host->dma));
 694                 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
 695                         host->cmd ? host->cmd->opcode : 0,
 696                         host->prev_cmd_code,
 697                         1 << host->actual_bus_width, host->dma_size);
 698         }
 699
 700         if (!host->present || timeout)
 701                 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
 702                         STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
 703
 704         if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
 705                 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
 706
 707                 stat = readw(host->base + MMC_REG_STATUS);
 708                 /*
 709                  * This is not required in theory, but there is chance to miss some flag
 710                  * which clears automatically by mask write, FreeScale original code keeps
 711                  * stat from IRQ time so do I
 712                  */
 713                 stat |= host->status_reg;
 714
 715                 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
 716                         stat &= ~STATUS_CRC_READ_ERR;
 717
 718                 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
 719                         imxmci_busy_wait_for_status(host, &stat,
 720                                                     STATUS_END_CMD_RESP | STATUS_ERR_MASK,
 721                                                     20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
 722                 }
 723
 724                 if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
 725                         if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
 726                                 imxmci_cmd_done(host, stat);
 727                         if (host->data && (stat & STATUS_ERR_MASK))
 728                                 imxmci_data_done(host, stat);
 729                 }
 730
 731                 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
 732                         stat |= readw(host->base + MMC_REG_STATUS);
 733                         if (imxmci_cpu_driven_data(host, &stat)) {
 734                                 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
 735                                         imxmci_cmd_done(host, stat);
 736                                 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
 737                                                   &host->pending_events);
 738                                 imxmci_data_done(host, stat);
 739                         }
 740                 }
 741         }
 742
 743         if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
 744             !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
 745
 746                 stat = readw(host->base + MMC_REG_STATUS);
 747                 /* Same as above */
 748                 stat |= host->status_reg;
 749
 750                 if (host->dma_dir == DMA_TO_DEVICE)
 751                         data_dir_mask = STATUS_WRITE_OP_DONE;
 752                 else
 753                         data_dir_mask = STATUS_DATA_TRANS_DONE;
 754
 755                 if (stat & data_dir_mask) {
 756                         clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
 757                         imxmci_data_done(host, stat);
 758                 }
 759         }
 760
 761         if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
 762
 763                 if (host->cmd)
 764                         imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
 765
 766                 if (host->data)
 767                         imxmci_data_done(host, STATUS_TIME_OUT_READ |
 768                                          STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
 769
 770                 if (host->req)
 771                         imxmci_finish_request(host, host->req);
 772
 773                 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
 774
 775         }
 776 }
 777
 778 static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
 779 {
 780         struct imxmci_host *host = mmc_priv(mmc);
 781         unsigned int cmdat;
 782
 783         WARN_ON(host->req != NULL);
 784
 785         host->req = req;
 786
 787         cmdat = 0;
 788
 789         if (req->data) {
 790                 imxmci_setup_data(host, req->data);
 791
 792                 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
 793
 794                 if (req->data->flags & MMC_DATA_WRITE)
 795                         cmdat |= CMD_DAT_CONT_WRITE;
 796
 797                 if (req->data->flags & MMC_DATA_STREAM)
 798                         cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
 799         }
 800
 801         imxmci_start_cmd(host, req->cmd, cmdat);
 802 }
 803
 804 #define CLK_RATE 19200000
 805
 806 static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 807 {
 808         struct imxmci_host *host = mmc_priv(mmc);
 809         int prescaler;
 810
 811         if (ios->bus_width == MMC_BUS_WIDTH_4) {
 812                 host->actual_bus_width = MMC_BUS_WIDTH_4;
 813                 imx_gpio_mode(PB11_PF_SD_DAT3);
 814                 BLR(host->dma) = 0;     /* burst 64 byte read/write */
 815         } else {
 816                 host->actual_bus_width = MMC_BUS_WIDTH_1;
 817                 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
 818                 BLR(host->dma) = 16;    /* burst 16 byte read/write */
 819         }
 820
 821         if (host->power_mode != ios->power_mode) {
 822                 switch (ios->power_mode) {
 823                 case MMC_POWER_OFF:
 824                         break;
 825                 case MMC_POWER_UP:
 826                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
 827                         break;
 828                 case MMC_POWER_ON:
 829                         break;
 830                 }
 831                 host->power_mode = ios->power_mode;
 832         }
 833
 834         if (ios->clock) {
 835                 unsigned int clk;
 836                 u16 reg;
 837
 838                 /* The prescaler is 5 for PERCLK2 equal to 96MHz
 839                  * then 96MHz / 5 = 19.2 MHz
 840                  */
 841                 clk = clk_get_rate(host->clk);
 842                 prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
 843                 switch (prescaler) {
 844                 case 0:
 845                 case 1: prescaler = 0;
 846                         break;
 847                 case 2: prescaler = 1;
 848                         break;
 849                 case 3: prescaler = 2;
 850                         break;
 851                 case 4: prescaler = 4;
 852                         break;
 853                 default:
 854                 case 5: prescaler = 5;
 855                         break;
 856                 }
 857
 858                 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
 859                         clk, prescaler);
 860
 861                 for (clk = 0; clk < 8; clk++) {
 862                         int x;
 863                         x = CLK_RATE / (1 << clk);
 864                         if (x <= ios->clock)
 865                                 break;
 866                 }
 867
 868                 /* enable controller */
 869                 reg = readw(host->base + MMC_REG_STR_STP_CLK);
 870                 writew(reg | STR_STP_CLK_ENABLE,
 871                                 host->base + MMC_REG_STR_STP_CLK);
 872
 873                 imxmci_stop_clock(host);
 874                 writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE);
 875                 /*
 876                  * Under my understanding, clock should not be started there, because it would
 877                  * initiate SDHC sequencer and send last or random command into card
 878                  */
 879                 /* imxmci_start_clock(host); */
 880
 881                 dev_dbg(mmc_dev(host->mmc),
 882                         "MMC_CLK_RATE: 0x%08x\n",
 883                         readw(host->base + MMC_REG_CLK_RATE));
 884         } else {
 885                 imxmci_stop_clock(host);
 886         }
 887 }
 888
 889 static int imxmci_get_ro(struct mmc_host *mmc)
 890 {
 891         struct imxmci_host *host = mmc_priv(mmc);
 892
 893         if (host->pdata && host->pdata->get_ro)
 894                 return !!host->pdata->get_ro(mmc_dev(mmc));
 895         /*
 896          * Board doesn't support read only detection; let the mmc core
 897          * decide what to do.
 898          */
 899         return -ENOSYS;
 900 }
 901
 902
 903 static const struct mmc_host_ops imxmci_ops = {
 904         .request        = imxmci_request,
 905         .set_ios        = imxmci_set_ios,
 906         .get_ro         = imxmci_get_ro,
 907 };
 908
 909 static void imxmci_check_status(unsigned long data)
 910 {
 911         struct imxmci_host *host = (struct imxmci_host *)data;
 912
 913         if (host->pdata && host->pdata->card_present &&
 914             host->pdata->card_present(mmc_dev(host->mmc)) != host->present) {
 915                 host->present ^= 1;
 916                 dev_info(mmc_dev(host->mmc), "card %s\n",
 917                       host->present ? "inserted" : "removed");
 918
 919                 set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
 920                 tasklet_schedule(&host->tasklet);
 921         }
 922
 923         if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
 924             test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
 925                 atomic_inc(&host->stuck_timeout);
 926                 if (atomic_read(&host->stuck_timeout) > 4)
 927                         tasklet_schedule(&host->tasklet);
 928         } else {
 929                 atomic_set(&host->stuck_timeout, 0);
 930
 931         }
 932
 933         mod_timer(&host->timer, jiffies + (HZ>>1));
 934 }
 935
 936 static int __init imxmci_probe(struct platform_device *pdev)
 937 {
 938         struct mmc_host *mmc;
 939         struct imxmci_host *host = NULL;
 940         struct resource *r;
 941         int ret = 0, irq;
 942         u16 rev_no;
 943
 944         printk(KERN_INFO "i.MX mmc driver\n");
 945
 946         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 947         irq = platform_get_irq(pdev, 0);
 948         if (!r || irq < 0)
 949                 return -ENXIO;
 950
 951         r = request_mem_region(r->start, resource_size(r), pdev->name);
 952         if (!r)
 953                 return -EBUSY;
 954
 955         mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
 956         if (!mmc) {
 957                 ret = -ENOMEM;
 958                 goto out;
 959         }
 960
 961         mmc->ops = &imxmci_ops;
 962         mmc->f_min = 150000;
 963         mmc->f_max = CLK_RATE/2;
 964         mmc->ocr_avail = MMC_VDD_32_33;
 965         mmc->caps = MMC_CAP_4_BIT_DATA;
 966
 967         /* MMC core transfer sizes tunable parameters */
 968         mmc->max_hw_segs = 64;
 969         mmc->max_phys_segs = 64;
 970         mmc->max_seg_size = 64*512;     /* default PAGE_CACHE_SIZE */
 971         mmc->max_req_size = 64*512;     /* default PAGE_CACHE_SIZE */
 972         mmc->max_blk_size = 2048;
 973         mmc->max_blk_count = 65535;
 974
 975         host = mmc_priv(mmc);
 976         host->base = ioremap(r->start, resource_size(r));
 977         if (!host->base) {
 978                 ret = -ENOMEM;
 979                 goto out;
 980         }
 981
 982         host->mmc = mmc;
 983         host->dma_allocated = 0;
 984         host->pdata = pdev->dev.platform_data;
 985         if (!host->pdata)
 986                 dev_warn(&pdev->dev, "No platform data provided!\n");
 987
 988         spin_lock_init(&host->lock);
 989         host->res = r;
 990         host->irq = irq;
 991
 992         host->clk = clk_get(&pdev->dev, "perclk2");
 993         if (IS_ERR(host->clk)) {
 994                 ret = PTR_ERR(host->clk);
 995                 goto out;
 996         }
 997         clk_enable(host->clk);
 998
 999         imx_gpio_mode(PB8_PF_SD_DAT0);
1000         imx_gpio_mode(PB9_PF_SD_DAT1);
1001         imx_gpio_mode(PB10_PF_SD_DAT2);
1002         /* Configured as GPIO with pull-up to ensure right MCC card mode */
1003         /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
1004         imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
1005         /* imx_gpio_mode(PB11_PF_SD_DAT3); */
1006         imx_gpio_mode(PB12_PF_SD_CLK);
1007         imx_gpio_mode(PB13_PF_SD_CMD);
1008
1009         imxmci_softreset(host);
1010
1011         rev_no = readw(host->base + MMC_REG_REV_NO);
1012         if (rev_no != 0x390) {
1013                 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1014                         readw(host->base + MMC_REG_REV_NO));
1015                 goto out;
1016         }
1017
1018         /* recommended in data sheet */
1019         writew(0x2db4, host->base + MMC_REG_READ_TO);
1020
1021         host->imask = IMXMCI_INT_MASK_DEFAULT;
1022         writew(host->imask, host->base + MMC_REG_INT_MASK);
1023
1024         host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
1025         if(host->dma < 0) {
1026                 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
1027                 ret = -EBUSY;
1028                 goto out;
1029         }
1030         host->dma_allocated = 1;
1031         imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
1032         RSSR(host->dma) = DMA_REQ_SDHC;
1033
1034         tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
1035         host->status_reg=0;
1036         host->pending_events=0;
1037
1038         ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
1039         if (ret)
1040                 goto out;
1041
1042         if (host->pdata && host->pdata->card_present)
1043                 host->present = host->pdata->card_present(mmc_dev(mmc));
1044         else    /* if there is no way to detect assume that card is present */
1045                 host->present = 1;
1046
1047         init_timer(&host->timer);
1048         host->timer.data = (unsigned long)host;
1049         host->timer.function = imxmci_check_status;
1050         add_timer(&host->timer);
1051         mod_timer(&host->timer, jiffies + (HZ >> 1));
1052
1053         platform_set_drvdata(pdev, mmc);
1054
1055         mmc_add_host(mmc);
1056
1057         return 0;
1058
1059 out:
1060         if (host) {
1061                 if (host->dma_allocated) {
1062                         imx_dma_free(host->dma);
1063                         host->dma_allocated = 0;
1064                 }
1065                 if (host->clk) {
1066                         clk_disable(host->clk);
1067                         clk_put(host->clk);
1068                 }
1069                 if (host->base)
1070                         iounmap(host->base);
1071         }
1072         if (mmc)
1073                 mmc_free_host(mmc);
1074         release_mem_region(r->start, resource_size(r));
1075         return ret;
1076 }
1077
1078 static int __exit imxmci_remove(struct platform_device *pdev)
1079 {
1080         struct mmc_host *mmc = platform_get_drvdata(pdev);
1081
1082         platform_set_drvdata(pdev, NULL);
1083
1084         if (mmc) {
1085                 struct imxmci_host *host = mmc_priv(mmc);
1086
1087                 tasklet_disable(&host->tasklet);
1088
1089                 del_timer_sync(&host->timer);
1090                 mmc_remove_host(mmc);
1091
1092                 free_irq(host->irq, host);
1093                 iounmap(host->base);
1094                 if (host->dma_allocated) {
1095                         imx_dma_free(host->dma);
1096                         host->dma_allocated = 0;
1097                 }
1098
1099                 tasklet_kill(&host->tasklet);
1100
1101                 clk_disable(host->clk);
1102                 clk_put(host->clk);
1103
1104                 release_mem_region(host->res->start, resource_size(host->res));
1105
1106                 mmc_free_host(mmc);
1107         }
1108         return 0;
1109 }
1110
1111 #ifdef CONFIG_PM
1112 static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
1113 {
1114         struct mmc_host *mmc = platform_get_drvdata(dev);
1115         int ret = 0;
1116
1117         if (mmc)
1118                 ret = mmc_suspend_host(mmc);
1119
1120         return ret;
1121 }
1122
1123 static int imxmci_resume(struct platform_device *dev)
1124 {
1125         struct mmc_host *mmc = platform_get_drvdata(dev);
1126         struct imxmci_host *host;
1127         int ret = 0;
1128
1129         if (mmc) {
1130                 host = mmc_priv(mmc);
1131                 if (host)
1132                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1133                 ret = mmc_resume_host(mmc);
1134         }
1135
1136         return ret;
1137 }
1138 #else
1139 #define imxmci_suspend  NULL
1140 #define imxmci_resume   NULL
1141 #endif /* CONFIG_PM */
1142
1143 static struct platform_driver imxmci_driver = {
1144         .remove         = __exit_p(imxmci_remove),
1145         .suspend        = imxmci_suspend,
1146         .resume         = imxmci_resume,
1147         .driver         = {
1148                 .name           = DRIVER_NAME,
1149                 .owner          = THIS_MODULE,
1150         }
1151 };
1152
1153 static int __init imxmci_init(void)
1154 {
1155         return platform_driver_probe(&imxmci_driver, imxmci_probe);
1156 }
1157
1158 static void __exit imxmci_exit(void)
1159 {
1160         platform_driver_unregister(&imxmci_driver);
1161 }
1162
1163 module_init(imxmci_init);
1164 module_exit(imxmci_exit);
1165
1166 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1167 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1168 MODULE_LICENSE("GPL");
1169 MODULE_ALIAS("platform:imx-mmc");