drivers/mmc/host/au1xmmc.c

   1 /*
   2  * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
   3  *
   4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
   5  *
   6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
   7  *  the following copyright notices:
   8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
   9  *     Portions Copyright (C) 2002 Embedix, Inc
  10  *     Copyright 2002 Hewlett-Packard Company
  11
  12  *  2.6 version of this driver inspired by:
  13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
  14  *     All Rights Reserved.
  15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
  16  *     All Rights Reserved.
  17  *
  18
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  */
  23
  24 /* Why don't we use the SD controllers' carddetect feature?
  25  *
  26  * From the AU1100 MMC application guide:
  27  * If the Au1100-based design is intended to support both MultiMediaCards
  28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
  29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
  30  * In doing so, a MMC card never enters SPI-mode communications,
  31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
  32  * (the low to high transition will not occur).
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/mm.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/scatterlist.h>
  42 #include <linux/leds.h>
  43 #include <linux/mmc/host.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/mach-au1x00/au1000.h>
  47 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  48 #include <asm/mach-au1x00/au1100_mmc.h>
  49
  50 #define DRIVER_NAME "au1xxx-mmc"
  51
  52 /* Set this to enable special debugging macros */
  53 /* #define DEBUG */
  54
  55 #ifdef DEBUG
  56 #define DBG(fmt, idx, args...)  \
  57         printk(KERN_DEBUG "au1xmmc(%d): DEBUG: " fmt, idx, ##args)
  58 #else
  59 #define DBG(fmt, idx, args...) do {} while (0)
  60 #endif
  61
  62 /* Hardware definitions */
  63 #define AU1XMMC_DESCRIPTOR_COUNT 1
  64
  65 /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
  66 #ifdef CONFIG_SOC_AU1100
  67 #define AU1XMMC_DESCRIPTOR_SIZE 0x0000ffff
  68 #else   /* Au1200 */
  69 #define AU1XMMC_DESCRIPTOR_SIZE 0x003fffff
  70 #endif
  71
  72 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
  73                      MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
  74                      MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
  75
  76 /* This gives us a hard value for the stop command that we can write directly
  77  * to the command register.
  78  */
  79 #define STOP_CMD        \
  80         (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
  81
  82 /* This is the set of interrupts that we configure by default. */
  83 #define AU1XMMC_INTERRUPTS                              \
  84         (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT |  \
  85          SD_CONFIG_CR | SD_CONFIG_I)
  86
  87 /* The poll event (looking for insert/remove events runs twice a second. */
  88 #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
  89
  90 struct au1xmmc_host {
  91         struct mmc_host *mmc;
  92         struct mmc_request *mrq;
  93
  94         u32 flags;
  95         u32 iobase;
  96         u32 clock;
  97         u32 bus_width;
  98         u32 power_mode;
  99
 100         int status;
 101
 102         struct {
 103                 int len;
 104                 int dir;
 105         } dma;
 106
 107         struct {
 108                 int index;
 109                 int offset;
 110                 int len;
 111         } pio;
 112
 113         u32 tx_chan;
 114         u32 rx_chan;
 115
 116         int irq;
 117
 118         struct tasklet_struct finish_task;
 119         struct tasklet_struct data_task;
 120         struct au1xmmc_platform_data *platdata;
 121         struct platform_device *pdev;
 122         struct resource *ioarea;
 123 };
 124
 125 /* Status flags used by the host structure */
 126 #define HOST_F_XMIT     0x0001
 127 #define HOST_F_RECV     0x0002
 128 #define HOST_F_DMA      0x0010
 129 #define HOST_F_ACTIVE   0x0100
 130 #define HOST_F_STOP     0x1000
 131
 132 #define HOST_S_IDLE     0x0001
 133 #define HOST_S_CMD      0x0002
 134 #define HOST_S_DATA     0x0003
 135 #define HOST_S_STOP     0x0004
 136
 137 /* Easy access macros */
 138 #define HOST_STATUS(h)  ((h)->iobase + SD_STATUS)
 139 #define HOST_CONFIG(h)  ((h)->iobase + SD_CONFIG)
 140 #define HOST_ENABLE(h)  ((h)->iobase + SD_ENABLE)
 141 #define HOST_TXPORT(h)  ((h)->iobase + SD_TXPORT)
 142 #define HOST_RXPORT(h)  ((h)->iobase + SD_RXPORT)
 143 #define HOST_CMDARG(h)  ((h)->iobase + SD_CMDARG)
 144 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
 145 #define HOST_CMD(h)     ((h)->iobase + SD_CMD)
 146 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
 147 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
 148 #define HOST_DEBUG(h)   ((h)->iobase + SD_DEBUG)
 149
 150 #define DMA_CHANNEL(h)  \
 151         (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
 152
 153 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
 154 {
 155         u32 val = au_readl(HOST_CONFIG(host));
 156         val |= mask;
 157         au_writel(val, HOST_CONFIG(host));
 158         au_sync();
 159 }
 160
 161 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
 162 {
 163         u32 val = au_readl(HOST_CONFIG2(host));
 164
 165         au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
 166         au_sync_delay(1);
 167
 168         /* SEND_STOP will turn off clock control - this re-enables it */
 169         val &= ~SD_CONFIG2_DF;
 170
 171         au_writel(val, HOST_CONFIG2(host));
 172         au_sync();
 173 }
 174
 175 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
 176 {
 177         u32 val = au_readl(HOST_CONFIG(host));
 178         val &= ~mask;
 179         au_writel(val, HOST_CONFIG(host));
 180         au_sync();
 181 }
 182
 183 static inline void SEND_STOP(struct au1xmmc_host *host)
 184 {
 185         u32 config2;
 186
 187         WARN_ON(host->status != HOST_S_DATA);
 188         host->status = HOST_S_STOP;
 189
 190         config2 = au_readl(HOST_CONFIG2(host));
 191         au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
 192         au_sync();
 193
 194         /* Send the stop commmand */
 195         au_writel(STOP_CMD, HOST_CMD(host));
 196 }
 197
 198 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
 199 {
 200         if (host->platdata && host->platdata->set_power)
 201                 host->platdata->set_power(host->mmc, state);
 202 }
 203
 204 static int au1xmmc_card_inserted(struct mmc_host *mmc)
 205 {
 206         struct au1xmmc_host *host = mmc_priv(mmc);
 207
 208         if (host->platdata && host->platdata->card_inserted)
 209                 return !!host->platdata->card_inserted(host->mmc);
 210
 211         return -ENOSYS;
 212 }
 213
 214 static int au1xmmc_card_readonly(struct mmc_host *mmc)
 215 {
 216         struct au1xmmc_host *host = mmc_priv(mmc);
 217
 218         if (host->platdata && host->platdata->card_readonly)
 219                 return !!host->platdata->card_readonly(mmc);
 220
 221         return -ENOSYS;
 222 }
 223
 224 static void au1xmmc_finish_request(struct au1xmmc_host *host)
 225 {
 226         struct mmc_request *mrq = host->mrq;
 227
 228         host->mrq = NULL;
 229         host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
 230
 231         host->dma.len = 0;
 232         host->dma.dir = 0;
 233
 234         host->pio.index  = 0;
 235         host->pio.offset = 0;
 236         host->pio.len = 0;
 237
 238         host->status = HOST_S_IDLE;
 239
 240         mmc_request_done(host->mmc, mrq);
 241 }
 242
 243 static void au1xmmc_tasklet_finish(unsigned long param)
 244 {
 245         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 246         au1xmmc_finish_request(host);
 247 }
 248
 249 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
 250                                 struct mmc_command *cmd, struct mmc_data *data)
 251 {
 252         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
 253
 254         switch (mmc_resp_type(cmd)) {
 255         case MMC_RSP_NONE:
 256                 break;
 257         case MMC_RSP_R1:
 258                 mmccmd |= SD_CMD_RT_1;
 259                 break;
 260         case MMC_RSP_R1B:
 261                 mmccmd |= SD_CMD_RT_1B;
 262                 break;
 263         case MMC_RSP_R2:
 264                 mmccmd |= SD_CMD_RT_2;
 265                 break;
 266         case MMC_RSP_R3:
 267                 mmccmd |= SD_CMD_RT_3;
 268                 break;
 269         default:
 270                 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
 271                         mmc_resp_type(cmd));
 272                 return -EINVAL;
 273         }
 274
 275         if (data) {
 276                 if (data->flags & MMC_DATA_READ) {
 277                         if (data->blocks > 1)
 278                                 mmccmd |= SD_CMD_CT_4;
 279                         else
 280                                 mmccmd |= SD_CMD_CT_2;
 281                 } else if (data->flags & MMC_DATA_WRITE) {
 282                         if (data->blocks > 1)
 283                                 mmccmd |= SD_CMD_CT_3;
 284                         else
 285                                 mmccmd |= SD_CMD_CT_1;
 286                 }
 287         }
 288
 289         au_writel(cmd->arg, HOST_CMDARG(host));
 290         au_sync();
 291
 292         if (wait)
 293                 IRQ_OFF(host, SD_CONFIG_CR);
 294
 295         au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
 296         au_sync();
 297
 298         /* Wait for the command to go on the line */
 299         while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
 300                 /* nop */;
 301
 302         /* Wait for the command to come back */
 303         if (wait) {
 304                 u32 status = au_readl(HOST_STATUS(host));
 305
 306                 while (!(status & SD_STATUS_CR))
 307                         status = au_readl(HOST_STATUS(host));
 308
 309                 /* Clear the CR status */
 310                 au_writel(SD_STATUS_CR, HOST_STATUS(host));
 311
 312                 IRQ_ON(host, SD_CONFIG_CR);
 313         }
 314
 315         return 0;
 316 }
 317
 318 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
 319 {
 320         struct mmc_request *mrq = host->mrq;
 321         struct mmc_data *data;
 322         u32 crc;
 323
 324         WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
 325
 326         if (host->mrq == NULL)
 327                 return;
 328
 329         data = mrq->cmd->data;
 330
 331         if (status == 0)
 332                 status = au_readl(HOST_STATUS(host));
 333
 334         /* The transaction is really over when the SD_STATUS_DB bit is clear */
 335         while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
 336                 status = au_readl(HOST_STATUS(host));
 337
 338         data->error = 0;
 339         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
 340
 341         /* Process any errors */
 342         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
 343         if (host->flags & HOST_F_XMIT)
 344                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
 345
 346         if (crc)
 347                 data->error = -EILSEQ;
 348
 349         /* Clear the CRC bits */
 350         au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
 351
 352         data->bytes_xfered = 0;
 353
 354         if (!data->error) {
 355                 if (host->flags & HOST_F_DMA) {
 356 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 357                         u32 chan = DMA_CHANNEL(host);
 358
 359                         chan_tab_t *c = *((chan_tab_t **)chan);
 360                         au1x_dma_chan_t *cp = c->chan_ptr;
 361                         data->bytes_xfered = cp->ddma_bytecnt;
 362 #endif
 363                 } else
 364                         data->bytes_xfered =
 365                                 (data->blocks * data->blksz) - host->pio.len;
 366         }
 367
 368         au1xmmc_finish_request(host);
 369 }
 370
 371 static void au1xmmc_tasklet_data(unsigned long param)
 372 {
 373         struct au1xmmc_host *host = (struct au1xmmc_host *)param;
 374
 375         u32 status = au_readl(HOST_STATUS(host));
 376         au1xmmc_data_complete(host, status);
 377 }
 378
 379 #define AU1XMMC_MAX_TRANSFER 8
 380
 381 static void au1xmmc_send_pio(struct au1xmmc_host *host)
 382 {
 383         struct mmc_data *data;
 384         int sg_len, max, count;
 385         unsigned char *sg_ptr, val;
 386         u32 status;
 387         struct scatterlist *sg;
 388
 389         data = host->mrq->data;
 390
 391         if (!(host->flags & HOST_F_XMIT))
 392                 return;
 393
 394         /* This is the pointer to the data buffer */
 395         sg = &data->sg[host->pio.index];
 396         sg_ptr = sg_virt(sg) + host->pio.offset;
 397
 398         /* This is the space left inside the buffer */
 399         sg_len = data->sg[host->pio.index].length - host->pio.offset;
 400
 401         /* Check if we need less than the size of the sg_buffer */
 402         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
 403         if (max > AU1XMMC_MAX_TRANSFER)
 404                 max = AU1XMMC_MAX_TRANSFER;
 405
 406         for (count = 0; count < max; count++) {
 407                 status = au_readl(HOST_STATUS(host));
 408
 409                 if (!(status & SD_STATUS_TH))
 410                         break;
 411
 412                 val = *sg_ptr++;
 413
 414                 au_writel((unsigned long)val, HOST_TXPORT(host));
 415                 au_sync();
 416         }
 417
 418         host->pio.len -= count;
 419         host->pio.offset += count;
 420
 421         if (count == sg_len) {
 422                 host->pio.index++;
 423                 host->pio.offset = 0;
 424         }
 425
 426         if (host->pio.len == 0) {
 427                 IRQ_OFF(host, SD_CONFIG_TH);
 428
 429                 if (host->flags & HOST_F_STOP)
 430                         SEND_STOP(host);
 431
 432                 tasklet_schedule(&host->data_task);
 433         }
 434 }
 435
 436 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
 437 {
 438         struct mmc_data *data;
 439         int max, count, sg_len = 0;
 440         unsigned char *sg_ptr = NULL;
 441         u32 status, val;
 442         struct scatterlist *sg;
 443
 444         data = host->mrq->data;
 445
 446         if (!(host->flags & HOST_F_RECV))
 447                 return;
 448
 449         max = host->pio.len;
 450
 451         if (host->pio.index < host->dma.len) {
 452                 sg = &data->sg[host->pio.index];
 453                 sg_ptr = sg_virt(sg) + host->pio.offset;
 454
 455                 /* This is the space left inside the buffer */
 456                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
 457
 458                 /* Check if we need less than the size of the sg_buffer */
 459                 if (sg_len < max)
 460                         max = sg_len;
 461         }
 462
 463         if (max > AU1XMMC_MAX_TRANSFER)
 464                 max = AU1XMMC_MAX_TRANSFER;
 465
 466         for (count = 0; count < max; count++) {
 467                 status = au_readl(HOST_STATUS(host));
 468
 469                 if (!(status & SD_STATUS_NE))
 470                         break;
 471
 472                 if (status & SD_STATUS_RC) {
 473                         DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
 474                                         host->pio.len, count);
 475                         break;
 476                 }
 477
 478                 if (status & SD_STATUS_RO) {
 479                         DBG("RX Overrun [%d + %d]\n", host->pdev->id,
 480                                         host->pio.len, count);
 481                         break;
 482                 }
 483                 else if (status & SD_STATUS_RU) {
 484                         DBG("RX Underrun [%d + %d]\n", host->pdev->id,
 485                                         host->pio.len,  count);
 486                         break;
 487                 }
 488
 489                 val = au_readl(HOST_RXPORT(host));
 490
 491                 if (sg_ptr)
 492                         *sg_ptr++ = (unsigned char)(val & 0xFF);
 493         }
 494
 495         host->pio.len -= count;
 496         host->pio.offset += count;
 497
 498         if (sg_len && count == sg_len) {
 499                 host->pio.index++;
 500                 host->pio.offset = 0;
 501         }
 502
 503         if (host->pio.len == 0) {
 504                 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 505                 IRQ_OFF(host, SD_CONFIG_NE);
 506
 507                 if (host->flags & HOST_F_STOP)
 508                         SEND_STOP(host);
 509
 510                 tasklet_schedule(&host->data_task);
 511         }
 512 }
 513
 514 /* This is called when a command has been completed - grab the response
 515  * and check for errors.  Then start the data transfer if it is indicated.
 516  */
 517 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
 518 {
 519         struct mmc_request *mrq = host->mrq;
 520         struct mmc_command *cmd;
 521         u32 r[4];
 522         int i, trans;
 523
 524         if (!host->mrq)
 525                 return;
 526
 527         cmd = mrq->cmd;
 528         cmd->error = 0;
 529
 530         if (cmd->flags & MMC_RSP_PRESENT) {
 531                 if (cmd->flags & MMC_RSP_136) {
 532                         r[0] = au_readl(host->iobase + SD_RESP3);
 533                         r[1] = au_readl(host->iobase + SD_RESP2);
 534                         r[2] = au_readl(host->iobase + SD_RESP1);
 535                         r[3] = au_readl(host->iobase + SD_RESP0);
 536
 537                         /* The CRC is omitted from the response, so really
 538                          * we only got 120 bytes, but the engine expects
 539                          * 128 bits, so we have to shift things up.
 540                          */
 541                         for (i = 0; i < 4; i++) {
 542                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
 543                                 if (i != 3)
 544                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
 545                         }
 546                 } else {
 547                         /* Techincally, we should be getting all 48 bits of
 548                          * the response (SD_RESP1 + SD_RESP2), but because
 549                          * our response omits the CRC, our data ends up
 550                          * being shifted 8 bits to the right.  In this case,
 551                          * that means that the OSR data starts at bit 31,
 552                          * so we can just read RESP0 and return that.
 553                          */
 554                         cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
 555                 }
 556         }
 557
 558         /* Figure out errors */
 559         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
 560                 cmd->error = -EILSEQ;
 561
 562         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
 563
 564         if (!trans || cmd->error) {
 565                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
 566                 tasklet_schedule(&host->finish_task);
 567                 return;
 568         }
 569
 570         host->status = HOST_S_DATA;
 571
 572         if (host->flags & HOST_F_DMA) {
 573 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 574                 u32 channel = DMA_CHANNEL(host);
 575
 576                 /* Start the DMA as soon as the buffer gets something in it */
 577
 578                 if (host->flags & HOST_F_RECV) {
 579                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
 580
 581                         while((status & mask) != mask)
 582                                 status = au_readl(HOST_STATUS(host));
 583                 }
 584
 585                 au1xxx_dbdma_start(channel);
 586 #endif
 587         }
 588 }
 589
 590 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
 591 {
 592         unsigned int pbus = get_au1x00_speed();
 593         unsigned int divisor;
 594         u32 config;
 595
 596         /* From databook:
 597          * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
 598          */
 599         pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
 600         pbus /= 2;
 601         divisor = ((pbus / rate) / 2) - 1;
 602
 603         config = au_readl(HOST_CONFIG(host));
 604
 605         config &= ~(SD_CONFIG_DIV);
 606         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
 607
 608         au_writel(config, HOST_CONFIG(host));
 609         au_sync();
 610 }
 611
 612 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
 613                                 struct mmc_data *data)
 614 {
 615         int datalen = data->blocks * data->blksz;
 616
 617         if (data->flags & MMC_DATA_READ)
 618                 host->flags |= HOST_F_RECV;
 619         else
 620                 host->flags |= HOST_F_XMIT;
 621
 622         if (host->mrq->stop)
 623                 host->flags |= HOST_F_STOP;
 624
 625         host->dma.dir = DMA_BIDIRECTIONAL;
 626
 627         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 628                                    data->sg_len, host->dma.dir);
 629
 630         if (host->dma.len == 0)
 631                 return -ETIMEDOUT;
 632
 633         au_writel(data->blksz - 1, HOST_BLKSIZE(host));
 634
 635         if (host->flags & HOST_F_DMA) {
 636 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 637                 int i;
 638                 u32 channel = DMA_CHANNEL(host);
 639
 640                 au1xxx_dbdma_stop(channel);
 641
 642                 for (i = 0; i < host->dma.len; i++) {
 643                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
 644                         struct scatterlist *sg = &data->sg[i];
 645                         int sg_len = sg->length;
 646
 647                         int len = (datalen > sg_len) ? sg_len : datalen;
 648
 649                         if (i == host->dma.len - 1)
 650                                 flags = DDMA_FLAGS_IE;
 651
 652                         if (host->flags & HOST_F_XMIT) {
 653                                 ret = au1xxx_dbdma_put_source_flags(channel,
 654                                         (void *)sg_virt(sg), len, flags);
 655                         } else {
 656                                 ret = au1xxx_dbdma_put_dest_flags(channel,
 657                                         (void *)sg_virt(sg), len, flags);
 658                         }
 659
 660                         if (!ret)
 661                                 goto dataerr;
 662
 663                         datalen -= len;
 664                 }
 665 #endif
 666         } else {
 667                 host->pio.index = 0;
 668                 host->pio.offset = 0;
 669                 host->pio.len = datalen;
 670
 671                 if (host->flags & HOST_F_XMIT)
 672                         IRQ_ON(host, SD_CONFIG_TH);
 673                 else
 674                         IRQ_ON(host, SD_CONFIG_NE);
 675                         /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 676         }
 677
 678         return 0;
 679
 680 dataerr:
 681         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 682                         host->dma.dir);
 683         return -ETIMEDOUT;
 684 }
 685
 686 /* This actually starts a command or data transaction */
 687 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
 688 {
 689         struct au1xmmc_host *host = mmc_priv(mmc);
 690         int ret = 0;
 691
 692         WARN_ON(irqs_disabled());
 693         WARN_ON(host->status != HOST_S_IDLE);
 694
 695         host->mrq = mrq;
 696         host->status = HOST_S_CMD;
 697
 698         /* fail request immediately if no card is present */
 699         if (0 == au1xmmc_card_inserted(mmc)) {
 700                 mrq->cmd->error = -ENOMEDIUM;
 701                 au1xmmc_finish_request(host);
 702                 return;
 703         }
 704
 705         if (mrq->data) {
 706                 FLUSH_FIFO(host);
 707                 ret = au1xmmc_prepare_data(host, mrq->data);
 708         }
 709
 710         if (!ret)
 711                 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
 712
 713         if (ret) {
 714                 mrq->cmd->error = ret;
 715                 au1xmmc_finish_request(host);
 716         }
 717 }
 718
 719 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
 720 {
 721         /* Apply the clock */
 722         au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
 723         au_sync_delay(1);
 724
 725         au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
 726         au_sync_delay(5);
 727
 728         au_writel(~0, HOST_STATUS(host));
 729         au_sync();
 730
 731         au_writel(0, HOST_BLKSIZE(host));
 732         au_writel(0x001fffff, HOST_TIMEOUT(host));
 733         au_sync();
 734
 735         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 736         au_sync();
 737
 738         au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
 739         au_sync_delay(1);
 740
 741         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 742         au_sync();
 743
 744         /* Configure interrupts */
 745         au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
 746         au_sync();
 747 }
 748
 749
 750 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 751 {
 752         struct au1xmmc_host *host = mmc_priv(mmc);
 753         u32 config2;
 754
 755         if (ios->power_mode == MMC_POWER_OFF)
 756                 au1xmmc_set_power(host, 0);
 757         else if (ios->power_mode == MMC_POWER_ON) {
 758                 au1xmmc_set_power(host, 1);
 759         }
 760
 761         if (ios->clock && ios->clock != host->clock) {
 762                 au1xmmc_set_clock(host, ios->clock);
 763                 host->clock = ios->clock;
 764         }
 765
 766         config2 = au_readl(HOST_CONFIG2(host));
 767         switch (ios->bus_width) {
 768         case MMC_BUS_WIDTH_4:
 769                 config2 |= SD_CONFIG2_WB;
 770                 break;
 771         case MMC_BUS_WIDTH_1:
 772                 config2 &= ~SD_CONFIG2_WB;
 773                 break;
 774         }
 775         au_writel(config2, HOST_CONFIG2(host));
 776         au_sync();
 777 }
 778
 779 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
 780 #define STATUS_DATA_IN  (SD_STATUS_NE)
 781 #define STATUS_DATA_OUT (SD_STATUS_TH)
 782
 783 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
 784 {
 785         struct au1xmmc_host *host = dev_id;
 786         u32 status;
 787
 788         status = au_readl(HOST_STATUS(host));
 789
 790         if (!(status & SD_STATUS_I))
 791                 return IRQ_NONE;        /* not ours */
 792
 793         if (status & SD_STATUS_SI)      /* SDIO */
 794                 mmc_signal_sdio_irq(host->mmc);
 795
 796         if (host->mrq && (status & STATUS_TIMEOUT)) {
 797                 if (status & SD_STATUS_RAT)
 798                         host->mrq->cmd->error = -ETIMEDOUT;
 799                 else if (status & SD_STATUS_DT)
 800                         host->mrq->data->error = -ETIMEDOUT;
 801
 802                 /* In PIO mode, interrupts might still be enabled */
 803                 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
 804
 805                 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
 806                 tasklet_schedule(&host->finish_task);
 807         }
 808 #if 0
 809         else if (status & SD_STATUS_DD) {
 810                 /* Sometimes we get a DD before a NE in PIO mode */
 811                 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
 812                         au1xmmc_receive_pio(host);
 813                 else {
 814                         au1xmmc_data_complete(host, status);
 815                         /* tasklet_schedule(&host->data_task); */
 816                 }
 817         }
 818 #endif
 819         else if (status & SD_STATUS_CR) {
 820                 if (host->status == HOST_S_CMD)
 821                         au1xmmc_cmd_complete(host, status);
 822
 823         } else if (!(host->flags & HOST_F_DMA)) {
 824                 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
 825                         au1xmmc_send_pio(host);
 826                 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
 827                         au1xmmc_receive_pio(host);
 828
 829         } else if (status & 0x203F3C70) {
 830                         DBG("Unhandled status %8.8x\n", host->pdev->id,
 831                                 status);
 832         }
 833
 834         au_writel(status, HOST_STATUS(host));
 835         au_sync();
 836
 837         return IRQ_HANDLED;
 838 }
 839
 840 #ifdef CONFIG_SOC_AU1200
 841 /* 8bit memory DMA device */
 842 static dbdev_tab_t au1xmmc_mem_dbdev = {
 843         .dev_id         = DSCR_CMD0_ALWAYS,
 844         .dev_flags      = DEV_FLAGS_ANYUSE,
 845         .dev_tsize      = 0,
 846         .dev_devwidth   = 8,
 847         .dev_physaddr   = 0x00000000,
 848         .dev_intlevel   = 0,
 849         .dev_intpolarity = 0,
 850 };
 851 static int memid;
 852
 853 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
 854 {
 855         struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
 856
 857         /* Avoid spurious interrupts */
 858         if (!host->mrq)
 859                 return;
 860
 861         if (host->flags & HOST_F_STOP)
 862                 SEND_STOP(host);
 863
 864         tasklet_schedule(&host->data_task);
 865 }
 866
 867 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
 868 {
 869         struct resource *res;
 870         int txid, rxid;
 871
 872         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
 873         if (!res)
 874                 return -ENODEV;
 875         txid = res->start;
 876
 877         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
 878         if (!res)
 879                 return -ENODEV;
 880         rxid = res->start;
 881
 882         if (!memid)
 883                 return -ENODEV;
 884
 885         host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
 886                                 au1xmmc_dbdma_callback, (void *)host);
 887         if (!host->tx_chan) {
 888                 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
 889                 return -ENODEV;
 890         }
 891
 892         host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
 893                                 au1xmmc_dbdma_callback, (void *)host);
 894         if (!host->rx_chan) {
 895                 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
 896                 au1xxx_dbdma_chan_free(host->tx_chan);
 897                 return -ENODEV;
 898         }
 899
 900         au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
 901         au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
 902
 903         au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 904         au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 905
 906         /* DBDMA is good to go */
 907         host->flags |= HOST_F_DMA;
 908
 909         return 0;
 910 }
 911
 912 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
 913 {
 914         if (host->flags & HOST_F_DMA) {
 915                 host->flags &= ~HOST_F_DMA;
 916                 au1xxx_dbdma_chan_free(host->tx_chan);
 917                 au1xxx_dbdma_chan_free(host->rx_chan);
 918         }
 919 }
 920 #endif
 921
 922 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
 923 {
 924         struct au1xmmc_host *host = mmc_priv(mmc);
 925
 926         if (en)
 927                 IRQ_ON(host, SD_CONFIG_SI);
 928         else
 929                 IRQ_OFF(host, SD_CONFIG_SI);
 930 }
 931
 932 static const struct mmc_host_ops au1xmmc_ops = {
 933         .request        = au1xmmc_request,
 934         .set_ios        = au1xmmc_set_ios,
 935         .get_ro         = au1xmmc_card_readonly,
 936         .get_cd         = au1xmmc_card_inserted,
 937         .enable_sdio_irq = au1xmmc_enable_sdio_irq,
 938 };
 939
 940 static int __devinit au1xmmc_probe(struct platform_device *pdev)
 941 {
 942         struct mmc_host *mmc;
 943         struct au1xmmc_host *host;
 944         struct resource *r;
 945         int ret;
 946
 947         mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
 948         if (!mmc) {
 949                 dev_err(&pdev->dev, "no memory for mmc_host\n");
 950                 ret = -ENOMEM;
 951                 goto out0;
 952         }
 953
 954         host = mmc_priv(mmc);
 955         host->mmc = mmc;
 956         host->platdata = pdev->dev.platform_data;
 957         host->pdev = pdev;
 958
 959         ret = -ENODEV;
 960         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 961         if (!r) {
 962                 dev_err(&pdev->dev, "no mmio defined\n");
 963                 goto out1;
 964         }
 965
 966         host->ioarea = request_mem_region(r->start, r->end - r->start + 1,
 967                                            pdev->name);
 968         if (!host->ioarea) {
 969                 dev_err(&pdev->dev, "mmio already in use\n");
 970                 goto out1;
 971         }
 972
 973         host->iobase = (unsigned long)ioremap(r->start, 0x3c);
 974         if (!host->iobase) {
 975                 dev_err(&pdev->dev, "cannot remap mmio\n");
 976                 goto out2;
 977         }
 978
 979         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 980         if (!r) {
 981                 dev_err(&pdev->dev, "no IRQ defined\n");
 982                 goto out3;
 983         }
 984
 985         host->irq = r->start;
 986         /* IRQ is shared among both SD controllers */
 987         ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
 988                           DRIVER_NAME, host);
 989         if (ret) {
 990                 dev_err(&pdev->dev, "cannot grab IRQ\n");
 991                 goto out3;
 992         }
 993
 994         mmc->ops = &au1xmmc_ops;
 995
 996         mmc->f_min =   450000;
 997         mmc->f_max = 24000000;
 998
 999         mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
1000         mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
1001
1002         mmc->max_blk_size = 2048;
1003         mmc->max_blk_count = 512;
1004
1005         mmc->ocr_avail = AU1XMMC_OCR;
1006         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1007
1008         host->status = HOST_S_IDLE;
1009
1010         /* board-specific carddetect setup, if any */
1011         if (host->platdata && host->platdata->cd_setup) {
1012                 ret = host->platdata->cd_setup(mmc, 1);
1013                 if (ret) {
1014                         dev_warn(&pdev->dev, "board CD setup failed\n");
1015                         mmc->caps |= MMC_CAP_NEEDS_POLL;
1016                 }
1017         } else
1018                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1019
1020         tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1021                         (unsigned long)host);
1022
1023         tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1024                         (unsigned long)host);
1025
1026 #ifdef CONFIG_SOC_AU1200
1027         ret = au1xmmc_dbdma_init(host);
1028         if (ret)
1029                 printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n");
1030 #endif
1031
1032 #ifdef CONFIG_LEDS_CLASS
1033         if (host->platdata && host->platdata->led) {
1034                 struct led_classdev *led = host->platdata->led;
1035                 led->name = mmc_hostname(mmc);
1036                 led->brightness = LED_OFF;
1037                 led->default_trigger = mmc_hostname(mmc);
1038                 ret = led_classdev_register(mmc_dev(mmc), led);
1039                 if (ret)
1040                         goto out5;
1041         }
1042 #endif
1043
1044         au1xmmc_reset_controller(host);
1045
1046         ret = mmc_add_host(mmc);
1047         if (ret) {
1048                 dev_err(&pdev->dev, "cannot add mmc host\n");
1049                 goto out6;
1050         }
1051
1052         platform_set_drvdata(pdev, host);
1053
1054         printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1055                 " (mode=%s)\n", pdev->id, host->iobase,
1056                 host->flags & HOST_F_DMA ? "dma" : "pio");
1057
1058         return 0;       /* all ok */
1059
1060 out6:
1061 #ifdef CONFIG_LEDS_CLASS
1062         if (host->platdata && host->platdata->led)
1063                 led_classdev_unregister(host->platdata->led);
1064 out5:
1065 #endif
1066         au_writel(0, HOST_ENABLE(host));
1067         au_writel(0, HOST_CONFIG(host));
1068         au_writel(0, HOST_CONFIG2(host));
1069         au_sync();
1070
1071 #ifdef CONFIG_SOC_AU1200
1072         au1xmmc_dbdma_shutdown(host);
1073 #endif
1074
1075         tasklet_kill(&host->data_task);
1076         tasklet_kill(&host->finish_task);
1077
1078         if (host->platdata && host->platdata->cd_setup &&
1079             !(mmc->caps & MMC_CAP_NEEDS_POLL))
1080                 host->platdata->cd_setup(mmc, 0);
1081
1082         free_irq(host->irq, host);
1083 out3:
1084         iounmap((void *)host->iobase);
1085 out2:
1086         release_resource(host->ioarea);
1087         kfree(host->ioarea);
1088 out1:
1089         mmc_free_host(mmc);
1090 out0:
1091         return ret;
1092 }
1093
1094 static int __devexit au1xmmc_remove(struct platform_device *pdev)
1095 {
1096         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1097
1098         if (host) {
1099                 mmc_remove_host(host->mmc);
1100
1101 #ifdef CONFIG_LEDS_CLASS
1102                 if (host->platdata && host->platdata->led)
1103                         led_classdev_unregister(host->platdata->led);
1104 #endif
1105
1106                 if (host->platdata && host->platdata->cd_setup &&
1107                     !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1108                         host->platdata->cd_setup(host->mmc, 0);
1109
1110                 au_writel(0, HOST_ENABLE(host));
1111                 au_writel(0, HOST_CONFIG(host));
1112                 au_writel(0, HOST_CONFIG2(host));
1113                 au_sync();
1114
1115                 tasklet_kill(&host->data_task);
1116                 tasklet_kill(&host->finish_task);
1117
1118 #ifdef CONFIG_SOC_AU1200
1119                 au1xmmc_dbdma_shutdown(host);
1120 #endif
1121                 au1xmmc_set_power(host, 0);
1122
1123                 free_irq(host->irq, host);
1124                 iounmap((void *)host->iobase);
1125                 release_resource(host->ioarea);
1126                 kfree(host->ioarea);
1127
1128                 mmc_free_host(host->mmc);
1129                 platform_set_drvdata(pdev, NULL);
1130         }
1131         return 0;
1132 }
1133
1134 #ifdef CONFIG_PM
1135 static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1136 {
1137         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1138         int ret;
1139
1140         ret = mmc_suspend_host(host->mmc, state);
1141         if (ret)
1142                 return ret;
1143
1144         au_writel(0, HOST_CONFIG2(host));
1145         au_writel(0, HOST_CONFIG(host));
1146         au_writel(0xffffffff, HOST_STATUS(host));
1147         au_writel(0, HOST_ENABLE(host));
1148         au_sync();
1149
1150         return 0;
1151 }
1152
1153 static int au1xmmc_resume(struct platform_device *pdev)
1154 {
1155         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1156
1157         au1xmmc_reset_controller(host);
1158
1159         return mmc_resume_host(host->mmc);
1160 }
1161 #else
1162 #define au1xmmc_suspend NULL
1163 #define au1xmmc_resume NULL
1164 #endif
1165
1166 static struct platform_driver au1xmmc_driver = {
1167         .probe         = au1xmmc_probe,
1168         .remove        = au1xmmc_remove,
1169         .suspend       = au1xmmc_suspend,
1170         .resume        = au1xmmc_resume,
1171         .driver        = {
1172                 .name  = DRIVER_NAME,
1173                 .owner = THIS_MODULE,
1174         },
1175 };
1176
1177 static int __init au1xmmc_init(void)
1178 {
1179 #ifdef CONFIG_SOC_AU1200
1180         /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1181          * of 8 bits.  And since devices are shared, we need to create
1182          * our own to avoid freaking out other devices.
1183          */
1184         memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1185         if (!memid)
1186                 printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n");
1187 #endif
1188         return platform_driver_register(&au1xmmc_driver);
1189 }
1190
1191 static void __exit au1xmmc_exit(void)
1192 {
1193 #ifdef CONFIG_SOC_AU1200
1194         if (memid)
1195                 au1xxx_ddma_del_device(memid);
1196 #endif
1197         platform_driver_unregister(&au1xmmc_driver);
1198 }
1199
1200 module_init(au1xmmc_init);
1201 module_exit(au1xmmc_exit);
1202
1203 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1204 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1205 MODULE_LICENSE("GPL");
1206 MODULE_ALIAS("platform:au1xxx-mmc");