drivers/mmc/host/au1xmmc.c

   1 /*
   2  * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
   3  *
   4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
   5  *
   6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
   7  *  the following copyright notices:
   8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
   9  *     Portions Copyright (C) 2002 Embedix, Inc
  10  *     Copyright 2002 Hewlett-Packard Company
  11
  12  *  2.6 version of this driver inspired by:
  13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
  14  *     All Rights Reserved.
  15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
  16  *     All Rights Reserved.
  17  *
  18
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  */
  23
  24 /* Why don't we use the SD controllers' carddetect feature?
  25  *
  26  * From the AU1100 MMC application guide:
  27  * If the Au1100-based design is intended to support both MultiMediaCards
  28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
  29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
  30  * In doing so, a MMC card never enters SPI-mode communications,
  31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
  32  * (the low to high transition will not occur).
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/mm.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/scatterlist.h>
  42 #include <linux/leds.h>
  43 #include <linux/mmc/host.h>
  44 #include <linux/slab.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/mach-au1x00/au1000.h>
  48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  49 #include <asm/mach-au1x00/au1100_mmc.h>
  50
  51 #define DRIVER_NAME "au1xxx-mmc"
  52
  53 /* Set this to enable special debugging macros */
  54 /* #define DEBUG */
  55
  56 #ifdef DEBUG
  57 #define DBG(fmt, idx, args...)  \
  58         printk(KERN_DEBUG "au1xmmc(%d): DEBUG: " fmt, idx, ##args)
  59 #else
  60 #define DBG(fmt, idx, args...) do {} while (0)
  61 #endif
  62
  63 /* Hardware definitions */
  64 #define AU1XMMC_DESCRIPTOR_COUNT 1
  65
  66 /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
  67 #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
  68 #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
  69
  70 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
  71                      MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
  72                      MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
  73
  74 /* This gives us a hard value for the stop command that we can write directly
  75  * to the command register.
  76  */
  77 #define STOP_CMD        \
  78         (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
  79
  80 /* This is the set of interrupts that we configure by default. */
  81 #define AU1XMMC_INTERRUPTS                              \
  82         (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT |  \
  83          SD_CONFIG_CR | SD_CONFIG_I)
  84
  85 /* The poll event (looking for insert/remove events runs twice a second. */
  86 #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
  87
  88 struct au1xmmc_host {
  89         struct mmc_host *mmc;
  90         struct mmc_request *mrq;
  91
  92         u32 flags;
  93         u32 iobase;
  94         u32 clock;
  95         u32 bus_width;
  96         u32 power_mode;
  97
  98         int status;
  99
 100         struct {
 101                 int len;
 102                 int dir;
 103         } dma;
 104
 105         struct {
 106                 int index;
 107                 int offset;
 108                 int len;
 109         } pio;
 110
 111         u32 tx_chan;
 112         u32 rx_chan;
 113
 114         int irq;
 115
 116         struct tasklet_struct finish_task;
 117         struct tasklet_struct data_task;
 118         struct au1xmmc_platform_data *platdata;
 119         struct platform_device *pdev;
 120         struct resource *ioarea;
 121 };
 122
 123 /* Status flags used by the host structure */
 124 #define HOST_F_XMIT     0x0001
 125 #define HOST_F_RECV     0x0002
 126 #define HOST_F_DMA      0x0010
 127 #define HOST_F_DBDMA    0x0020
 128 #define HOST_F_ACTIVE   0x0100
 129 #define HOST_F_STOP     0x1000
 130
 131 #define HOST_S_IDLE     0x0001
 132 #define HOST_S_CMD      0x0002
 133 #define HOST_S_DATA     0x0003
 134 #define HOST_S_STOP     0x0004
 135
 136 /* Easy access macros */
 137 #define HOST_STATUS(h)  ((h)->iobase + SD_STATUS)
 138 #define HOST_CONFIG(h)  ((h)->iobase + SD_CONFIG)
 139 #define HOST_ENABLE(h)  ((h)->iobase + SD_ENABLE)
 140 #define HOST_TXPORT(h)  ((h)->iobase + SD_TXPORT)
 141 #define HOST_RXPORT(h)  ((h)->iobase + SD_RXPORT)
 142 #define HOST_CMDARG(h)  ((h)->iobase + SD_CMDARG)
 143 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
 144 #define HOST_CMD(h)     ((h)->iobase + SD_CMD)
 145 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
 146 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
 147 #define HOST_DEBUG(h)   ((h)->iobase + SD_DEBUG)
 148
 149 #define DMA_CHANNEL(h)  \
 150         (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
 151
 152 static inline int has_dbdma(void)
 153 {
 154         switch (alchemy_get_cputype()) {
 155         case ALCHEMY_CPU_AU1200:
 156                 return 1;
 157         default:
 158                 return 0;
 159         }
 160 }
 161
 162 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
 163 {
 164         u32 val = au_readl(HOST_CONFIG(host));
 165         val |= mask;
 166         au_writel(val, HOST_CONFIG(host));
 167         au_sync();
 168 }
 169
 170 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
 171 {
 172         u32 val = au_readl(HOST_CONFIG2(host));
 173
 174         au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
 175         au_sync_delay(1);
 176
 177         /* SEND_STOP will turn off clock control - this re-enables it */
 178         val &= ~SD_CONFIG2_DF;
 179
 180         au_writel(val, HOST_CONFIG2(host));
 181         au_sync();
 182 }
 183
 184 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
 185 {
 186         u32 val = au_readl(HOST_CONFIG(host));
 187         val &= ~mask;
 188         au_writel(val, HOST_CONFIG(host));
 189         au_sync();
 190 }
 191
 192 static inline void SEND_STOP(struct au1xmmc_host *host)
 193 {
 194         u32 config2;
 195
 196         WARN_ON(host->status != HOST_S_DATA);
 197         host->status = HOST_S_STOP;
 198
 199         config2 = au_readl(HOST_CONFIG2(host));
 200         au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
 201         au_sync();
 202
 203         /* Send the stop command */
 204         au_writel(STOP_CMD, HOST_CMD(host));
 205 }
 206
 207 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
 208 {
 209         if (host->platdata && host->platdata->set_power)
 210                 host->platdata->set_power(host->mmc, state);
 211 }
 212
 213 static int au1xmmc_card_inserted(struct mmc_host *mmc)
 214 {
 215         struct au1xmmc_host *host = mmc_priv(mmc);
 216
 217         if (host->platdata && host->platdata->card_inserted)
 218                 return !!host->platdata->card_inserted(host->mmc);
 219
 220         return -ENOSYS;
 221 }
 222
 223 static int au1xmmc_card_readonly(struct mmc_host *mmc)
 224 {
 225         struct au1xmmc_host *host = mmc_priv(mmc);
 226
 227         if (host->platdata && host->platdata->card_readonly)
 228                 return !!host->platdata->card_readonly(mmc);
 229
 230         return -ENOSYS;
 231 }
 232
 233 static void au1xmmc_finish_request(struct au1xmmc_host *host)
 234 {
 235         struct mmc_request *mrq = host->mrq;
 236
 237         host->mrq = NULL;
 238         host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
 239
 240         host->dma.len = 0;
 241         host->dma.dir = 0;
 242
 243         host->pio.index  = 0;
 244         host->pio.offset = 0;
 245         host->pio.len = 0;
 246
 247         host->status = HOST_S_IDLE;
 248
 249         mmc_request_done(host->mmc, mrq);
 250 }
 251
 252 static void au1xmmc_tasklet_finish(unsigned long param)
 253 {
 254         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 255         au1xmmc_finish_request(host);
 256 }
 257
 258 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
 259                                 struct mmc_command *cmd, struct mmc_data *data)
 260 {
 261         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
 262
 263         switch (mmc_resp_type(cmd)) {
 264         case MMC_RSP_NONE:
 265                 break;
 266         case MMC_RSP_R1:
 267                 mmccmd |= SD_CMD_RT_1;
 268                 break;
 269         case MMC_RSP_R1B:
 270                 mmccmd |= SD_CMD_RT_1B;
 271                 break;
 272         case MMC_RSP_R2:
 273                 mmccmd |= SD_CMD_RT_2;
 274                 break;
 275         case MMC_RSP_R3:
 276                 mmccmd |= SD_CMD_RT_3;
 277                 break;
 278         default:
 279                 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
 280                         mmc_resp_type(cmd));
 281                 return -EINVAL;
 282         }
 283
 284         if (data) {
 285                 if (data->flags & MMC_DATA_READ) {
 286                         if (data->blocks > 1)
 287                                 mmccmd |= SD_CMD_CT_4;
 288                         else
 289                                 mmccmd |= SD_CMD_CT_2;
 290                 } else if (data->flags & MMC_DATA_WRITE) {
 291                         if (data->blocks > 1)
 292                                 mmccmd |= SD_CMD_CT_3;
 293                         else
 294                                 mmccmd |= SD_CMD_CT_1;
 295                 }
 296         }
 297
 298         au_writel(cmd->arg, HOST_CMDARG(host));
 299         au_sync();
 300
 301         if (wait)
 302                 IRQ_OFF(host, SD_CONFIG_CR);
 303
 304         au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
 305         au_sync();
 306
 307         /* Wait for the command to go on the line */
 308         while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
 309                 /* nop */;
 310
 311         /* Wait for the command to come back */
 312         if (wait) {
 313                 u32 status = au_readl(HOST_STATUS(host));
 314
 315                 while (!(status & SD_STATUS_CR))
 316                         status = au_readl(HOST_STATUS(host));
 317
 318                 /* Clear the CR status */
 319                 au_writel(SD_STATUS_CR, HOST_STATUS(host));
 320
 321                 IRQ_ON(host, SD_CONFIG_CR);
 322         }
 323
 324         return 0;
 325 }
 326
 327 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
 328 {
 329         struct mmc_request *mrq = host->mrq;
 330         struct mmc_data *data;
 331         u32 crc;
 332
 333         WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
 334
 335         if (host->mrq == NULL)
 336                 return;
 337
 338         data = mrq->cmd->data;
 339
 340         if (status == 0)
 341                 status = au_readl(HOST_STATUS(host));
 342
 343         /* The transaction is really over when the SD_STATUS_DB bit is clear */
 344         while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
 345                 status = au_readl(HOST_STATUS(host));
 346
 347         data->error = 0;
 348         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
 349
 350         /* Process any errors */
 351         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
 352         if (host->flags & HOST_F_XMIT)
 353                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
 354
 355         if (crc)
 356                 data->error = -EILSEQ;
 357
 358         /* Clear the CRC bits */
 359         au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
 360
 361         data->bytes_xfered = 0;
 362
 363         if (!data->error) {
 364                 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
 365                         u32 chan = DMA_CHANNEL(host);
 366
 367                         chan_tab_t *c = *((chan_tab_t **)chan);
 368                         au1x_dma_chan_t *cp = c->chan_ptr;
 369                         data->bytes_xfered = cp->ddma_bytecnt;
 370                 } else
 371                         data->bytes_xfered =
 372                                 (data->blocks * data->blksz) - host->pio.len;
 373         }
 374
 375         au1xmmc_finish_request(host);
 376 }
 377
 378 static void au1xmmc_tasklet_data(unsigned long param)
 379 {
 380         struct au1xmmc_host *host = (struct au1xmmc_host *)param;
 381
 382         u32 status = au_readl(HOST_STATUS(host));
 383         au1xmmc_data_complete(host, status);
 384 }
 385
 386 #define AU1XMMC_MAX_TRANSFER 8
 387
 388 static void au1xmmc_send_pio(struct au1xmmc_host *host)
 389 {
 390         struct mmc_data *data;
 391         int sg_len, max, count;
 392         unsigned char *sg_ptr, val;
 393         u32 status;
 394         struct scatterlist *sg;
 395
 396         data = host->mrq->data;
 397
 398         if (!(host->flags & HOST_F_XMIT))
 399                 return;
 400
 401         /* This is the pointer to the data buffer */
 402         sg = &data->sg[host->pio.index];
 403         sg_ptr = sg_virt(sg) + host->pio.offset;
 404
 405         /* This is the space left inside the buffer */
 406         sg_len = data->sg[host->pio.index].length - host->pio.offset;
 407
 408         /* Check if we need less than the size of the sg_buffer */
 409         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
 410         if (max > AU1XMMC_MAX_TRANSFER)
 411                 max = AU1XMMC_MAX_TRANSFER;
 412
 413         for (count = 0; count < max; count++) {
 414                 status = au_readl(HOST_STATUS(host));
 415
 416                 if (!(status & SD_STATUS_TH))
 417                         break;
 418
 419                 val = *sg_ptr++;
 420
 421                 au_writel((unsigned long)val, HOST_TXPORT(host));
 422                 au_sync();
 423         }
 424
 425         host->pio.len -= count;
 426         host->pio.offset += count;
 427
 428         if (count == sg_len) {
 429                 host->pio.index++;
 430                 host->pio.offset = 0;
 431         }
 432
 433         if (host->pio.len == 0) {
 434                 IRQ_OFF(host, SD_CONFIG_TH);
 435
 436                 if (host->flags & HOST_F_STOP)
 437                         SEND_STOP(host);
 438
 439                 tasklet_schedule(&host->data_task);
 440         }
 441 }
 442
 443 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
 444 {
 445         struct mmc_data *data;
 446         int max, count, sg_len = 0;
 447         unsigned char *sg_ptr = NULL;
 448         u32 status, val;
 449         struct scatterlist *sg;
 450
 451         data = host->mrq->data;
 452
 453         if (!(host->flags & HOST_F_RECV))
 454                 return;
 455
 456         max = host->pio.len;
 457
 458         if (host->pio.index < host->dma.len) {
 459                 sg = &data->sg[host->pio.index];
 460                 sg_ptr = sg_virt(sg) + host->pio.offset;
 461
 462                 /* This is the space left inside the buffer */
 463                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
 464
 465                 /* Check if we need less than the size of the sg_buffer */
 466                 if (sg_len < max)
 467                         max = sg_len;
 468         }
 469
 470         if (max > AU1XMMC_MAX_TRANSFER)
 471                 max = AU1XMMC_MAX_TRANSFER;
 472
 473         for (count = 0; count < max; count++) {
 474                 status = au_readl(HOST_STATUS(host));
 475
 476                 if (!(status & SD_STATUS_NE))
 477                         break;
 478
 479                 if (status & SD_STATUS_RC) {
 480                         DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
 481                                         host->pio.len, count);
 482                         break;
 483                 }
 484
 485                 if (status & SD_STATUS_RO) {
 486                         DBG("RX Overrun [%d + %d]\n", host->pdev->id,
 487                                         host->pio.len, count);
 488                         break;
 489                 }
 490                 else if (status & SD_STATUS_RU) {
 491                         DBG("RX Underrun [%d + %d]\n", host->pdev->id,
 492                                         host->pio.len,  count);
 493                         break;
 494                 }
 495
 496                 val = au_readl(HOST_RXPORT(host));
 497
 498                 if (sg_ptr)
 499                         *sg_ptr++ = (unsigned char)(val & 0xFF);
 500         }
 501
 502         host->pio.len -= count;
 503         host->pio.offset += count;
 504
 505         if (sg_len && count == sg_len) {
 506                 host->pio.index++;
 507                 host->pio.offset = 0;
 508         }
 509
 510         if (host->pio.len == 0) {
 511                 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 512                 IRQ_OFF(host, SD_CONFIG_NE);
 513
 514                 if (host->flags & HOST_F_STOP)
 515                         SEND_STOP(host);
 516
 517                 tasklet_schedule(&host->data_task);
 518         }
 519 }
 520
 521 /* This is called when a command has been completed - grab the response
 522  * and check for errors.  Then start the data transfer if it is indicated.
 523  */
 524 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
 525 {
 526         struct mmc_request *mrq = host->mrq;
 527         struct mmc_command *cmd;
 528         u32 r[4];
 529         int i, trans;
 530
 531         if (!host->mrq)
 532                 return;
 533
 534         cmd = mrq->cmd;
 535         cmd->error = 0;
 536
 537         if (cmd->flags & MMC_RSP_PRESENT) {
 538                 if (cmd->flags & MMC_RSP_136) {
 539                         r[0] = au_readl(host->iobase + SD_RESP3);
 540                         r[1] = au_readl(host->iobase + SD_RESP2);
 541                         r[2] = au_readl(host->iobase + SD_RESP1);
 542                         r[3] = au_readl(host->iobase + SD_RESP0);
 543
 544                         /* The CRC is omitted from the response, so really
 545                          * we only got 120 bytes, but the engine expects
 546                          * 128 bits, so we have to shift things up.
 547                          */
 548                         for (i = 0; i < 4; i++) {
 549                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
 550                                 if (i != 3)
 551                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
 552                         }
 553                 } else {
 554                         /* Techincally, we should be getting all 48 bits of
 555                          * the response (SD_RESP1 + SD_RESP2), but because
 556                          * our response omits the CRC, our data ends up
 557                          * being shifted 8 bits to the right.  In this case,
 558                          * that means that the OSR data starts at bit 31,
 559                          * so we can just read RESP0 and return that.
 560                          */
 561                         cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
 562                 }
 563         }
 564
 565         /* Figure out errors */
 566         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
 567                 cmd->error = -EILSEQ;
 568
 569         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
 570
 571         if (!trans || cmd->error) {
 572                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
 573                 tasklet_schedule(&host->finish_task);
 574                 return;
 575         }
 576
 577         host->status = HOST_S_DATA;
 578
 579         if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) {
 580                 u32 channel = DMA_CHANNEL(host);
 581
 582                 /* Start the DBDMA as soon as the buffer gets something in it */
 583
 584                 if (host->flags & HOST_F_RECV) {
 585                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
 586
 587                         while((status & mask) != mask)
 588                                 status = au_readl(HOST_STATUS(host));
 589                 }
 590
 591                 au1xxx_dbdma_start(channel);
 592         }
 593 }
 594
 595 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
 596 {
 597         unsigned int pbus = get_au1x00_speed();
 598         unsigned int divisor;
 599         u32 config;
 600
 601         /* From databook:
 602          * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
 603          */
 604         pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
 605         pbus /= 2;
 606         divisor = ((pbus / rate) / 2) - 1;
 607
 608         config = au_readl(HOST_CONFIG(host));
 609
 610         config &= ~(SD_CONFIG_DIV);
 611         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
 612
 613         au_writel(config, HOST_CONFIG(host));
 614         au_sync();
 615 }
 616
 617 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
 618                                 struct mmc_data *data)
 619 {
 620         int datalen = data->blocks * data->blksz;
 621
 622         if (data->flags & MMC_DATA_READ)
 623                 host->flags |= HOST_F_RECV;
 624         else
 625                 host->flags |= HOST_F_XMIT;
 626
 627         if (host->mrq->stop)
 628                 host->flags |= HOST_F_STOP;
 629
 630         host->dma.dir = DMA_BIDIRECTIONAL;
 631
 632         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 633                                    data->sg_len, host->dma.dir);
 634
 635         if (host->dma.len == 0)
 636                 return -ETIMEDOUT;
 637
 638         au_writel(data->blksz - 1, HOST_BLKSIZE(host));
 639
 640         if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
 641                 int i;
 642                 u32 channel = DMA_CHANNEL(host);
 643
 644                 au1xxx_dbdma_stop(channel);
 645
 646                 for (i = 0; i < host->dma.len; i++) {
 647                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
 648                         struct scatterlist *sg = &data->sg[i];
 649                         int sg_len = sg->length;
 650
 651                         int len = (datalen > sg_len) ? sg_len : datalen;
 652
 653                         if (i == host->dma.len - 1)
 654                                 flags = DDMA_FLAGS_IE;
 655
 656                         if (host->flags & HOST_F_XMIT) {
 657                                 ret = au1xxx_dbdma_put_source(channel,
 658                                         sg_phys(sg), len, flags);
 659                         } else {
 660                                 ret = au1xxx_dbdma_put_dest(channel,
 661                                         sg_phys(sg), len, flags);
 662                         }
 663
 664                         if (!ret)
 665                                 goto dataerr;
 666
 667                         datalen -= len;
 668                 }
 669         } else {
 670                 host->pio.index = 0;
 671                 host->pio.offset = 0;
 672                 host->pio.len = datalen;
 673
 674                 if (host->flags & HOST_F_XMIT)
 675                         IRQ_ON(host, SD_CONFIG_TH);
 676                 else
 677                         IRQ_ON(host, SD_CONFIG_NE);
 678                         /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 679         }
 680
 681         return 0;
 682
 683 dataerr:
 684         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 685                         host->dma.dir);
 686         return -ETIMEDOUT;
 687 }
 688
 689 /* This actually starts a command or data transaction */
 690 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
 691 {
 692         struct au1xmmc_host *host = mmc_priv(mmc);
 693         int ret = 0;
 694
 695         WARN_ON(irqs_disabled());
 696         WARN_ON(host->status != HOST_S_IDLE);
 697
 698         host->mrq = mrq;
 699         host->status = HOST_S_CMD;
 700
 701         /* fail request immediately if no card is present */
 702         if (0 == au1xmmc_card_inserted(mmc)) {
 703                 mrq->cmd->error = -ENOMEDIUM;
 704                 au1xmmc_finish_request(host);
 705                 return;
 706         }
 707
 708         if (mrq->data) {
 709                 FLUSH_FIFO(host);
 710                 ret = au1xmmc_prepare_data(host, mrq->data);
 711         }
 712
 713         if (!ret)
 714                 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
 715
 716         if (ret) {
 717                 mrq->cmd->error = ret;
 718                 au1xmmc_finish_request(host);
 719         }
 720 }
 721
 722 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
 723 {
 724         /* Apply the clock */
 725         au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
 726         au_sync_delay(1);
 727
 728         au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
 729         au_sync_delay(5);
 730
 731         au_writel(~0, HOST_STATUS(host));
 732         au_sync();
 733
 734         au_writel(0, HOST_BLKSIZE(host));
 735         au_writel(0x001fffff, HOST_TIMEOUT(host));
 736         au_sync();
 737
 738         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 739         au_sync();
 740
 741         au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
 742         au_sync_delay(1);
 743
 744         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 745         au_sync();
 746
 747         /* Configure interrupts */
 748         au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
 749         au_sync();
 750 }
 751
 752
 753 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 754 {
 755         struct au1xmmc_host *host = mmc_priv(mmc);
 756         u32 config2;
 757
 758         if (ios->power_mode == MMC_POWER_OFF)
 759                 au1xmmc_set_power(host, 0);
 760         else if (ios->power_mode == MMC_POWER_ON) {
 761                 au1xmmc_set_power(host, 1);
 762         }
 763
 764         if (ios->clock && ios->clock != host->clock) {
 765                 au1xmmc_set_clock(host, ios->clock);
 766                 host->clock = ios->clock;
 767         }
 768
 769         config2 = au_readl(HOST_CONFIG2(host));
 770         switch (ios->bus_width) {
 771         case MMC_BUS_WIDTH_4:
 772                 config2 |= SD_CONFIG2_WB;
 773                 break;
 774         case MMC_BUS_WIDTH_1:
 775                 config2 &= ~SD_CONFIG2_WB;
 776                 break;
 777         }
 778         au_writel(config2, HOST_CONFIG2(host));
 779         au_sync();
 780 }
 781
 782 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
 783 #define STATUS_DATA_IN  (SD_STATUS_NE)
 784 #define STATUS_DATA_OUT (SD_STATUS_TH)
 785
 786 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
 787 {
 788         struct au1xmmc_host *host = dev_id;
 789         u32 status;
 790
 791         status = au_readl(HOST_STATUS(host));
 792
 793         if (!(status & SD_STATUS_I))
 794                 return IRQ_NONE;        /* not ours */
 795
 796         if (status & SD_STATUS_SI)      /* SDIO */
 797                 mmc_signal_sdio_irq(host->mmc);
 798
 799         if (host->mrq && (status & STATUS_TIMEOUT)) {
 800                 if (status & SD_STATUS_RAT)
 801                         host->mrq->cmd->error = -ETIMEDOUT;
 802                 else if (status & SD_STATUS_DT)
 803                         host->mrq->data->error = -ETIMEDOUT;
 804
 805                 /* In PIO mode, interrupts might still be enabled */
 806                 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
 807
 808                 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
 809                 tasklet_schedule(&host->finish_task);
 810         }
 811 #if 0
 812         else if (status & SD_STATUS_DD) {
 813                 /* Sometimes we get a DD before a NE in PIO mode */
 814                 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
 815                         au1xmmc_receive_pio(host);
 816                 else {
 817                         au1xmmc_data_complete(host, status);
 818                         /* tasklet_schedule(&host->data_task); */
 819                 }
 820         }
 821 #endif
 822         else if (status & SD_STATUS_CR) {
 823                 if (host->status == HOST_S_CMD)
 824                         au1xmmc_cmd_complete(host, status);
 825
 826         } else if (!(host->flags & HOST_F_DMA)) {
 827                 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
 828                         au1xmmc_send_pio(host);
 829                 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
 830                         au1xmmc_receive_pio(host);
 831
 832         } else if (status & 0x203F3C70) {
 833                         DBG("Unhandled status %8.8x\n", host->pdev->id,
 834                                 status);
 835         }
 836
 837         au_writel(status, HOST_STATUS(host));
 838         au_sync();
 839
 840         return IRQ_HANDLED;
 841 }
 842
 843 /* 8bit memory DMA device */
 844 static dbdev_tab_t au1xmmc_mem_dbdev = {
 845         .dev_id         = DSCR_CMD0_ALWAYS,
 846         .dev_flags      = DEV_FLAGS_ANYUSE,
 847         .dev_tsize      = 0,
 848         .dev_devwidth   = 8,
 849         .dev_physaddr   = 0x00000000,
 850         .dev_intlevel   = 0,
 851         .dev_intpolarity = 0,
 852 };
 853 static int memid;
 854
 855 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
 856 {
 857         struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
 858
 859         /* Avoid spurious interrupts */
 860         if (!host->mrq)
 861                 return;
 862
 863         if (host->flags & HOST_F_STOP)
 864                 SEND_STOP(host);
 865
 866         tasklet_schedule(&host->data_task);
 867 }
 868
 869 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
 870 {
 871         struct resource *res;
 872         int txid, rxid;
 873
 874         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
 875         if (!res)
 876                 return -ENODEV;
 877         txid = res->start;
 878
 879         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
 880         if (!res)
 881                 return -ENODEV;
 882         rxid = res->start;
 883
 884         if (!memid)
 885                 return -ENODEV;
 886
 887         host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
 888                                 au1xmmc_dbdma_callback, (void *)host);
 889         if (!host->tx_chan) {
 890                 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
 891                 return -ENODEV;
 892         }
 893
 894         host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
 895                                 au1xmmc_dbdma_callback, (void *)host);
 896         if (!host->rx_chan) {
 897                 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
 898                 au1xxx_dbdma_chan_free(host->tx_chan);
 899                 return -ENODEV;
 900         }
 901
 902         au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
 903         au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
 904
 905         au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 906         au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 907
 908         /* DBDMA is good to go */
 909         host->flags |= HOST_F_DMA | HOST_F_DBDMA;
 910
 911         return 0;
 912 }
 913
 914 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
 915 {
 916         if (host->flags & HOST_F_DMA) {
 917                 host->flags &= ~HOST_F_DMA;
 918                 au1xxx_dbdma_chan_free(host->tx_chan);
 919                 au1xxx_dbdma_chan_free(host->rx_chan);
 920         }
 921 }
 922
 923 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
 924 {
 925         struct au1xmmc_host *host = mmc_priv(mmc);
 926
 927         if (en)
 928                 IRQ_ON(host, SD_CONFIG_SI);
 929         else
 930                 IRQ_OFF(host, SD_CONFIG_SI);
 931 }
 932
 933 static const struct mmc_host_ops au1xmmc_ops = {
 934         .request        = au1xmmc_request,
 935         .set_ios        = au1xmmc_set_ios,
 936         .get_ro         = au1xmmc_card_readonly,
 937         .get_cd         = au1xmmc_card_inserted,
 938         .enable_sdio_irq = au1xmmc_enable_sdio_irq,
 939 };
 940
 941 static int __devinit au1xmmc_probe(struct platform_device *pdev)
 942 {
 943         struct mmc_host *mmc;
 944         struct au1xmmc_host *host;
 945         struct resource *r;
 946         int ret;
 947
 948         mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
 949         if (!mmc) {
 950                 dev_err(&pdev->dev, "no memory for mmc_host\n");
 951                 ret = -ENOMEM;
 952                 goto out0;
 953         }
 954
 955         host = mmc_priv(mmc);
 956         host->mmc = mmc;
 957         host->platdata = pdev->dev.platform_data;
 958         host->pdev = pdev;
 959
 960         ret = -ENODEV;
 961         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 962         if (!r) {
 963                 dev_err(&pdev->dev, "no mmio defined\n");
 964                 goto out1;
 965         }
 966
 967         host->ioarea = request_mem_region(r->start, resource_size(r),
 968                                            pdev->name);
 969         if (!host->ioarea) {
 970                 dev_err(&pdev->dev, "mmio already in use\n");
 971                 goto out1;
 972         }
 973
 974         host->iobase = (unsigned long)ioremap(r->start, 0x3c);
 975         if (!host->iobase) {
 976                 dev_err(&pdev->dev, "cannot remap mmio\n");
 977                 goto out2;
 978         }
 979
 980         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 981         if (!r) {
 982                 dev_err(&pdev->dev, "no IRQ defined\n");
 983                 goto out3;
 984         }
 985
 986         host->irq = r->start;
 987         /* IRQ is shared among both SD controllers */
 988         ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
 989                           DRIVER_NAME, host);
 990         if (ret) {
 991                 dev_err(&pdev->dev, "cannot grab IRQ\n");
 992                 goto out3;
 993         }
 994
 995         mmc->ops = &au1xmmc_ops;
 996
 997         mmc->f_min =   450000;
 998         mmc->f_max = 24000000;
 999
1000         switch (alchemy_get_cputype()) {
1001         case ALCHEMY_CPU_AU1100:
1002                 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
1003                 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1004                 break;
1005         case ALCHEMY_CPU_AU1200:
1006                 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1007                 mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1008                 break;
1009         }
1010
1011         mmc->max_blk_size = 2048;
1012         mmc->max_blk_count = 512;
1013
1014         mmc->ocr_avail = AU1XMMC_OCR;
1015         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1016
1017         host->status = HOST_S_IDLE;
1018
1019         /* board-specific carddetect setup, if any */
1020         if (host->platdata && host->platdata->cd_setup) {
1021                 ret = host->platdata->cd_setup(mmc, 1);
1022                 if (ret) {
1023                         dev_warn(&pdev->dev, "board CD setup failed\n");
1024                         mmc->caps |= MMC_CAP_NEEDS_POLL;
1025                 }
1026         } else
1027                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1028
1029         /* platform may not be able to use all advertised caps */
1030         if (host->platdata)
1031                 mmc->caps &= ~(host->platdata->mask_host_caps);
1032
1033         tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1034                         (unsigned long)host);
1035
1036         tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1037                         (unsigned long)host);
1038
1039         if (has_dbdma()) {
1040                 ret = au1xmmc_dbdma_init(host);
1041                 if (ret)
1042                         printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; "
1043                                                      "using PIO\n");
1044         }
1045
1046 #ifdef CONFIG_LEDS_CLASS
1047         if (host->platdata && host->platdata->led) {
1048                 struct led_classdev *led = host->platdata->led;
1049                 led->name = mmc_hostname(mmc);
1050                 led->brightness = LED_OFF;
1051                 led->default_trigger = mmc_hostname(mmc);
1052                 ret = led_classdev_register(mmc_dev(mmc), led);
1053                 if (ret)
1054                         goto out5;
1055         }
1056 #endif
1057
1058         au1xmmc_reset_controller(host);
1059
1060         ret = mmc_add_host(mmc);
1061         if (ret) {
1062                 dev_err(&pdev->dev, "cannot add mmc host\n");
1063                 goto out6;
1064         }
1065
1066         platform_set_drvdata(pdev, host);
1067
1068         printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1069                 " (mode=%s)\n", pdev->id, host->iobase,
1070                 host->flags & HOST_F_DMA ? "dma" : "pio");
1071
1072         return 0;       /* all ok */
1073
1074 out6:
1075 #ifdef CONFIG_LEDS_CLASS
1076         if (host->platdata && host->platdata->led)
1077                 led_classdev_unregister(host->platdata->led);
1078 out5:
1079 #endif
1080         au_writel(0, HOST_ENABLE(host));
1081         au_writel(0, HOST_CONFIG(host));
1082         au_writel(0, HOST_CONFIG2(host));
1083         au_sync();
1084
1085         if (host->flags & HOST_F_DBDMA)
1086                 au1xmmc_dbdma_shutdown(host);
1087
1088         tasklet_kill(&host->data_task);
1089         tasklet_kill(&host->finish_task);
1090
1091         if (host->platdata && host->platdata->cd_setup &&
1092             !(mmc->caps & MMC_CAP_NEEDS_POLL))
1093                 host->platdata->cd_setup(mmc, 0);
1094
1095         free_irq(host->irq, host);
1096 out3:
1097         iounmap((void *)host->iobase);
1098 out2:
1099         release_resource(host->ioarea);
1100         kfree(host->ioarea);
1101 out1:
1102         mmc_free_host(mmc);
1103 out0:
1104         return ret;
1105 }
1106
1107 static int __devexit au1xmmc_remove(struct platform_device *pdev)
1108 {
1109         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1110
1111         if (host) {
1112                 mmc_remove_host(host->mmc);
1113
1114 #ifdef CONFIG_LEDS_CLASS
1115                 if (host->platdata && host->platdata->led)
1116                         led_classdev_unregister(host->platdata->led);
1117 #endif
1118
1119                 if (host->platdata && host->platdata->cd_setup &&
1120                     !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1121                         host->platdata->cd_setup(host->mmc, 0);
1122
1123                 au_writel(0, HOST_ENABLE(host));
1124                 au_writel(0, HOST_CONFIG(host));
1125                 au_writel(0, HOST_CONFIG2(host));
1126                 au_sync();
1127
1128                 tasklet_kill(&host->data_task);
1129                 tasklet_kill(&host->finish_task);
1130
1131                 if (host->flags & HOST_F_DBDMA)
1132                         au1xmmc_dbdma_shutdown(host);
1133
1134                 au1xmmc_set_power(host, 0);
1135
1136                 free_irq(host->irq, host);
1137                 iounmap((void *)host->iobase);
1138                 release_resource(host->ioarea);
1139                 kfree(host->ioarea);
1140
1141                 mmc_free_host(host->mmc);
1142                 platform_set_drvdata(pdev, NULL);
1143         }
1144         return 0;
1145 }
1146
1147 #ifdef CONFIG_PM
1148 static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1149 {
1150         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1151         int ret;
1152
1153         ret = mmc_suspend_host(host->mmc);
1154         if (ret)
1155                 return ret;
1156
1157         au_writel(0, HOST_CONFIG2(host));
1158         au_writel(0, HOST_CONFIG(host));
1159         au_writel(0xffffffff, HOST_STATUS(host));
1160         au_writel(0, HOST_ENABLE(host));
1161         au_sync();
1162
1163         return 0;
1164 }
1165
1166 static int au1xmmc_resume(struct platform_device *pdev)
1167 {
1168         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1169
1170         au1xmmc_reset_controller(host);
1171
1172         return mmc_resume_host(host->mmc);
1173 }
1174 #else
1175 #define au1xmmc_suspend NULL
1176 #define au1xmmc_resume NULL
1177 #endif
1178
1179 static struct platform_driver au1xmmc_driver = {
1180         .probe         = au1xmmc_probe,
1181         .remove        = au1xmmc_remove,
1182         .suspend       = au1xmmc_suspend,
1183         .resume        = au1xmmc_resume,
1184         .driver        = {
1185                 .name  = DRIVER_NAME,
1186                 .owner = THIS_MODULE,
1187         },
1188 };
1189
1190 static int __init au1xmmc_init(void)
1191 {
1192         if (has_dbdma()) {
1193                 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1194                 * of 8 bits.  And since devices are shared, we need to create
1195                 * our own to avoid freaking out other devices.
1196                 */
1197                 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1198                 if (!memid)
1199                         printk(KERN_ERR "au1xmmc: cannot add memory dbdma\n");
1200         }
1201         return platform_driver_register(&au1xmmc_driver);
1202 }
1203
1204 static void __exit au1xmmc_exit(void)
1205 {
1206         if (has_dbdma() && memid)
1207                 au1xxx_ddma_del_device(memid);
1208
1209         platform_driver_unregister(&au1xmmc_driver);
1210 }
1211
1212 module_init(au1xmmc_init);
1213 module_exit(au1xmmc_exit);
1214
1215 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1216 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1217 MODULE_LICENSE("GPL");
1218 MODULE_ALIAS("platform:au1xxx-mmc");