drivers/mfd/wm831x-irq.c

   1 /*
   2  * wm831x-irq.c  --  Interrupt controller support for Wolfson WM831x PMICs
   3  *
   4  * Copyright 2009 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/i2c.h>
  18 #include <linux/irq.h>
  19 #include <linux/mfd/core.h>
  20 #include <linux/interrupt.h>
  21
  22 #include <linux/mfd/wm831x/core.h>
  23 #include <linux/mfd/wm831x/pdata.h>
  24 #include <linux/mfd/wm831x/gpio.h>
  25 #include <linux/mfd/wm831x/irq.h>
  26
  27 #include <linux/delay.h>
  28
  29 struct wm831x_irq_data {
  30         int primary;
  31         int reg;
  32         int mask;
  33 };
  34
  35 static struct wm831x_irq_data wm831x_irqs[] = {
  36         [WM831X_IRQ_TEMP_THW] = {
  37                 .primary = WM831X_TEMP_INT,
  38                 .reg = 1,
  39                 .mask = WM831X_TEMP_THW_EINT,
  40         },
  41         [WM831X_IRQ_GPIO_1] = {
  42                 .primary = WM831X_GP_INT,
  43                 .reg = 5,
  44                 .mask = WM831X_GP1_EINT,
  45         },
  46         [WM831X_IRQ_GPIO_2] = {
  47                 .primary = WM831X_GP_INT,
  48                 .reg = 5,
  49                 .mask = WM831X_GP2_EINT,
  50         },
  51         [WM831X_IRQ_GPIO_3] = {
  52                 .primary = WM831X_GP_INT,
  53                 .reg = 5,
  54                 .mask = WM831X_GP3_EINT,
  55         },
  56         [WM831X_IRQ_GPIO_4] = {
  57                 .primary = WM831X_GP_INT,
  58                 .reg = 5,
  59                 .mask = WM831X_GP4_EINT,
  60         },
  61         [WM831X_IRQ_GPIO_5] = {
  62                 .primary = WM831X_GP_INT,
  63                 .reg = 5,
  64                 .mask = WM831X_GP5_EINT,
  65         },
  66         [WM831X_IRQ_GPIO_6] = {
  67                 .primary = WM831X_GP_INT,
  68                 .reg = 5,
  69                 .mask = WM831X_GP6_EINT,
  70         },
  71         [WM831X_IRQ_GPIO_7] = {
  72                 .primary = WM831X_GP_INT,
  73                 .reg = 5,
  74                 .mask = WM831X_GP7_EINT,
  75         },
  76         [WM831X_IRQ_GPIO_8] = {
  77                 .primary = WM831X_GP_INT,
  78                 .reg = 5,
  79                 .mask = WM831X_GP8_EINT,
  80         },
  81         [WM831X_IRQ_GPIO_9] = {
  82                 .primary = WM831X_GP_INT,
  83                 .reg = 5,
  84                 .mask = WM831X_GP9_EINT,
  85         },
  86         [WM831X_IRQ_GPIO_10] = {
  87                 .primary = WM831X_GP_INT,
  88                 .reg = 5,
  89                 .mask = WM831X_GP10_EINT,
  90         },
  91         [WM831X_IRQ_GPIO_11] = {
  92                 .primary = WM831X_GP_INT,
  93                 .reg = 5,
  94                 .mask = WM831X_GP11_EINT,
  95         },
  96         [WM831X_IRQ_GPIO_12] = {
  97                 .primary = WM831X_GP_INT,
  98                 .reg = 5,
  99                 .mask = WM831X_GP12_EINT,
 100         },
 101         [WM831X_IRQ_GPIO_13] = {
 102                 .primary = WM831X_GP_INT,
 103                 .reg = 5,
 104                 .mask = WM831X_GP13_EINT,
 105         },
 106         [WM831X_IRQ_GPIO_14] = {
 107                 .primary = WM831X_GP_INT,
 108                 .reg = 5,
 109                 .mask = WM831X_GP14_EINT,
 110         },
 111         [WM831X_IRQ_GPIO_15] = {
 112                 .primary = WM831X_GP_INT,
 113                 .reg = 5,
 114                 .mask = WM831X_GP15_EINT,
 115         },
 116         [WM831X_IRQ_GPIO_16] = {
 117                 .primary = WM831X_GP_INT,
 118                 .reg = 5,
 119                 .mask = WM831X_GP16_EINT,
 120         },
 121         [WM831X_IRQ_ON] = {
 122                 .primary = WM831X_ON_PIN_INT,
 123                 .reg = 1,
 124                 .mask = WM831X_ON_PIN_EINT,
 125         },
 126         [WM831X_IRQ_PPM_SYSLO] = {
 127                 .primary = WM831X_PPM_INT,
 128                 .reg = 1,
 129                 .mask = WM831X_PPM_SYSLO_EINT,
 130         },
 131         [WM831X_IRQ_PPM_PWR_SRC] = {
 132                 .primary = WM831X_PPM_INT,
 133                 .reg = 1,
 134                 .mask = WM831X_PPM_PWR_SRC_EINT,
 135         },
 136         [WM831X_IRQ_PPM_USB_CURR] = {
 137                 .primary = WM831X_PPM_INT,
 138                 .reg = 1,
 139                 .mask = WM831X_PPM_USB_CURR_EINT,
 140         },
 141         [WM831X_IRQ_WDOG_TO] = {
 142                 .primary = WM831X_WDOG_INT,
 143                 .reg = 1,
 144                 .mask = WM831X_WDOG_TO_EINT,
 145         },
 146         [WM831X_IRQ_RTC_PER] = {
 147                 .primary = WM831X_RTC_INT,
 148                 .reg = 1,
 149                 .mask = WM831X_RTC_PER_EINT,
 150         },
 151         [WM831X_IRQ_RTC_ALM] = {
 152                 .primary = WM831X_RTC_INT,
 153                 .reg = 1,
 154                 .mask = WM831X_RTC_ALM_EINT,
 155         },
 156         [WM831X_IRQ_CHG_BATT_HOT] = {
 157                 .primary = WM831X_CHG_INT,
 158                 .reg = 2,
 159                 .mask = WM831X_CHG_BATT_HOT_EINT,
 160         },
 161         [WM831X_IRQ_CHG_BATT_COLD] = {
 162                 .primary = WM831X_CHG_INT,
 163                 .reg = 2,
 164                 .mask = WM831X_CHG_BATT_COLD_EINT,
 165         },
 166         [WM831X_IRQ_CHG_BATT_FAIL] = {
 167                 .primary = WM831X_CHG_INT,
 168                 .reg = 2,
 169                 .mask = WM831X_CHG_BATT_FAIL_EINT,
 170         },
 171         [WM831X_IRQ_CHG_OV] = {
 172                 .primary = WM831X_CHG_INT,
 173                 .reg = 2,
 174                 .mask = WM831X_CHG_OV_EINT,
 175         },
 176         [WM831X_IRQ_CHG_END] = {
 177                 .primary = WM831X_CHG_INT,
 178                 .reg = 2,
 179                 .mask = WM831X_CHG_END_EINT,
 180         },
 181         [WM831X_IRQ_CHG_TO] = {
 182                 .primary = WM831X_CHG_INT,
 183                 .reg = 2,
 184                 .mask = WM831X_CHG_TO_EINT,
 185         },
 186         [WM831X_IRQ_CHG_MODE] = {
 187                 .primary = WM831X_CHG_INT,
 188                 .reg = 2,
 189                 .mask = WM831X_CHG_MODE_EINT,
 190         },
 191         [WM831X_IRQ_CHG_START] = {
 192                 .primary = WM831X_CHG_INT,
 193                 .reg = 2,
 194                 .mask = WM831X_CHG_START_EINT,
 195         },
 196         [WM831X_IRQ_TCHDATA] = {
 197                 .primary = WM831X_TCHDATA_INT,
 198                 .reg = 1,
 199                 .mask = WM831X_TCHDATA_EINT,
 200         },
 201         [WM831X_IRQ_TCHPD] = {
 202                 .primary = WM831X_TCHPD_INT,
 203                 .reg = 1,
 204                 .mask = WM831X_TCHPD_EINT,
 205         },
 206         [WM831X_IRQ_AUXADC_DATA] = {
 207                 .primary = WM831X_AUXADC_INT,
 208                 .reg = 1,
 209                 .mask = WM831X_AUXADC_DATA_EINT,
 210         },
 211         [WM831X_IRQ_AUXADC_DCOMP1] = {
 212                 .primary = WM831X_AUXADC_INT,
 213                 .reg = 1,
 214                 .mask = WM831X_AUXADC_DCOMP1_EINT,
 215         },
 216         [WM831X_IRQ_AUXADC_DCOMP2] = {
 217                 .primary = WM831X_AUXADC_INT,
 218                 .reg = 1,
 219                 .mask = WM831X_AUXADC_DCOMP2_EINT,
 220         },
 221         [WM831X_IRQ_AUXADC_DCOMP3] = {
 222                 .primary = WM831X_AUXADC_INT,
 223                 .reg = 1,
 224                 .mask = WM831X_AUXADC_DCOMP3_EINT,
 225         },
 226         [WM831X_IRQ_AUXADC_DCOMP4] = {
 227                 .primary = WM831X_AUXADC_INT,
 228                 .reg = 1,
 229                 .mask = WM831X_AUXADC_DCOMP4_EINT,
 230         },
 231         [WM831X_IRQ_CS1] = {
 232                 .primary = WM831X_CS_INT,
 233                 .reg = 2,
 234                 .mask = WM831X_CS1_EINT,
 235         },
 236         [WM831X_IRQ_CS2] = {
 237                 .primary = WM831X_CS_INT,
 238                 .reg = 2,
 239                 .mask = WM831X_CS2_EINT,
 240         },
 241         [WM831X_IRQ_HC_DC1] = {
 242                 .primary = WM831X_HC_INT,
 243                 .reg = 4,
 244                 .mask = WM831X_HC_DC1_EINT,
 245         },
 246         [WM831X_IRQ_HC_DC2] = {
 247                 .primary = WM831X_HC_INT,
 248                 .reg = 4,
 249                 .mask = WM831X_HC_DC2_EINT,
 250         },
 251         [WM831X_IRQ_UV_LDO1] = {
 252                 .primary = WM831X_UV_INT,
 253                 .reg = 3,
 254                 .mask = WM831X_UV_LDO1_EINT,
 255         },
 256         [WM831X_IRQ_UV_LDO2] = {
 257                 .primary = WM831X_UV_INT,
 258                 .reg = 3,
 259                 .mask = WM831X_UV_LDO2_EINT,
 260         },
 261         [WM831X_IRQ_UV_LDO3] = {
 262                 .primary = WM831X_UV_INT,
 263                 .reg = 3,
 264                 .mask = WM831X_UV_LDO3_EINT,
 265         },
 266         [WM831X_IRQ_UV_LDO4] = {
 267                 .primary = WM831X_UV_INT,
 268                 .reg = 3,
 269                 .mask = WM831X_UV_LDO4_EINT,
 270         },
 271         [WM831X_IRQ_UV_LDO5] = {
 272                 .primary = WM831X_UV_INT,
 273                 .reg = 3,
 274                 .mask = WM831X_UV_LDO5_EINT,
 275         },
 276         [WM831X_IRQ_UV_LDO6] = {
 277                 .primary = WM831X_UV_INT,
 278                 .reg = 3,
 279                 .mask = WM831X_UV_LDO6_EINT,
 280         },
 281         [WM831X_IRQ_UV_LDO7] = {
 282                 .primary = WM831X_UV_INT,
 283                 .reg = 3,
 284                 .mask = WM831X_UV_LDO7_EINT,
 285         },
 286         [WM831X_IRQ_UV_LDO8] = {
 287                 .primary = WM831X_UV_INT,
 288                 .reg = 3,
 289                 .mask = WM831X_UV_LDO8_EINT,
 290         },
 291         [WM831X_IRQ_UV_LDO9] = {
 292                 .primary = WM831X_UV_INT,
 293                 .reg = 3,
 294                 .mask = WM831X_UV_LDO9_EINT,
 295         },
 296         [WM831X_IRQ_UV_LDO10] = {
 297                 .primary = WM831X_UV_INT,
 298                 .reg = 3,
 299                 .mask = WM831X_UV_LDO10_EINT,
 300         },
 301         [WM831X_IRQ_UV_DC1] = {
 302                 .primary = WM831X_UV_INT,
 303                 .reg = 4,
 304                 .mask = WM831X_UV_DC1_EINT,
 305         },
 306         [WM831X_IRQ_UV_DC2] = {
 307                 .primary = WM831X_UV_INT,
 308                 .reg = 4,
 309                 .mask = WM831X_UV_DC2_EINT,
 310         },
 311         [WM831X_IRQ_UV_DC3] = {
 312                 .primary = WM831X_UV_INT,
 313                 .reg = 4,
 314                 .mask = WM831X_UV_DC3_EINT,
 315         },
 316         [WM831X_IRQ_UV_DC4] = {
 317                 .primary = WM831X_UV_INT,
 318                 .reg = 4,
 319                 .mask = WM831X_UV_DC4_EINT,
 320         },
 321 };
 322
 323 static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
 324 {
 325         return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
 326 }
 327
 328 static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data)
 329 {
 330         return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg;
 331 }
 332
 333 static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
 334                                                         int irq)
 335 {
 336         return &wm831x_irqs[irq - wm831x->irq_base];
 337 }
 338
 339 static void wm831x_irq_lock(struct irq_data *data)
 340 {
 341         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 342
 343         mutex_lock(&wm831x->irq_lock);
 344 }
 345
 346 static void wm831x_irq_sync_unlock(struct irq_data *data)
 347 {
 348         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 349         int i;
 350
 351         for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
 352                 if (wm831x->gpio_update[i]) {
 353                         wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
 354                                         WM831X_GPN_INT_MODE | WM831X_GPN_POL,
 355                                         wm831x->gpio_update[i]);
 356                         wm831x->gpio_update[i] = 0;
 357                 }
 358         }
 359
 360         for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
 361                 /* If there's been a change in the mask write it back
 362                  * to the hardware. */
 363                 if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
 364                         dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
 365                                 WM831X_INTERRUPT_STATUS_1_MASK + i,
 366                                 wm831x->irq_masks_cur[i]);
 367
 368                         wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
 369                         wm831x_reg_write(wm831x,
 370                                          WM831X_INTERRUPT_STATUS_1_MASK + i,
 371                                          wm831x->irq_masks_cur[i]);
 372                 }
 373         }
 374
 375         mutex_unlock(&wm831x->irq_lock);
 376 }
 377
 378 static void wm831x_irq_enable(struct irq_data *data)
 379 {
 380         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 381         struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
 382                                                              data->irq);
 383
 384         wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
 385 }
 386
 387 static void wm831x_irq_disable(struct irq_data *data)
 388 {
 389         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 390         struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
 391                                                              data->irq);
 392
 393         wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
 394 }
 395
 396 static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
 397 {
 398         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 399         int irq;
 400
 401         irq = data->irq - wm831x->irq_base;
 402
 403         if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
 404                 /* Ignore internal-only IRQs */
 405                 if (irq >= 0 && irq < WM831X_NUM_IRQS)
 406                         return 0;
 407                 else
 408                         return -EINVAL;
 409         }
 410
 411         /* Rebase the IRQ into the GPIO range so we've got a sensible array
 412          * index.
 413          */
 414         irq -= WM831X_IRQ_GPIO_1;
 415
 416         /* We set the high bit to flag that we need an update; don't
 417          * do the update here as we can be called with the bus lock
 418          * held.
 419          */
 420         switch (type) {
 421         case IRQ_TYPE_EDGE_BOTH:
 422                 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE;
 423                 wm831x->gpio_level[irq] = false;
 424                 break;
 425         case IRQ_TYPE_EDGE_RISING:
 426                 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
 427                 wm831x->gpio_level[irq] = false;
 428                 break;
 429         case IRQ_TYPE_EDGE_FALLING:
 430                 wm831x->gpio_update[irq] = 0x10000;
 431                 wm831x->gpio_level[irq] = false;
 432                 break;
 433         case IRQ_TYPE_LEVEL_HIGH:
 434                 wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
 435                 wm831x->gpio_level[irq] = true;
 436                 break;
 437         default:
 438                 return -EINVAL;
 439         }
 440
 441         return 0;
 442 }
 443
 444 static struct irq_chip wm831x_irq_chip = {
 445         .name                   = "wm831x",
 446         .irq_bus_lock           = wm831x_irq_lock,
 447         .irq_bus_sync_unlock    = wm831x_irq_sync_unlock,
 448         .irq_disable            = wm831x_irq_disable,
 449         .irq_enable             = wm831x_irq_enable,
 450         .irq_set_type           = wm831x_irq_set_type,
 451 };
 452
 453 /* The processing of the primary interrupt occurs in a thread so that
 454  * we can interact with the device over I2C or SPI. */
 455 static irqreturn_t wm831x_irq_thread(int irq, void *data)
 456 {
 457         struct wm831x *wm831x = data;
 458         unsigned int i;
 459         int primary, status_addr, ret;
 460         int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
 461         int read[WM831X_NUM_IRQ_REGS] = { 0 };
 462         int *status;
 463
 464         primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
 465         if (primary < 0) {
 466                 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
 467                         primary);
 468                 goto out;
 469         }
 470
 471         /* The touch interrupts are visible in the primary register as
 472          * an optimisation; open code this to avoid complicating the
 473          * main handling loop and so we can also skip iterating the
 474          * descriptors.
 475          */
 476         if (primary & WM831X_TCHPD_INT)
 477                 handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHPD);
 478         if (primary & WM831X_TCHDATA_INT)
 479                 handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHDATA);
 480         if (primary & (WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT))
 481                 goto out;
 482
 483         for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
 484                 int offset = wm831x_irqs[i].reg - 1;
 485
 486                 if (!(primary & wm831x_irqs[i].primary))
 487                         continue;
 488
 489                 status = &status_regs[offset];
 490
 491                 /* Hopefully there should only be one register to read
 492                  * each time otherwise we ought to do a block read. */
 493                 if (!read[offset]) {
 494                         status_addr = irq_data_to_status_reg(&wm831x_irqs[i]);
 495
 496                         *status = wm831x_reg_read(wm831x, status_addr);
 497                         if (*status < 0) {
 498                                 dev_err(wm831x->dev,
 499                                         "Failed to read IRQ status: %d\n",
 500                                         *status);
 501                                 goto out;
 502                         }
 503
 504                         read[offset] = 1;
 505
 506                         /* Ignore any bits that we don't think are masked */
 507                         *status &= ~wm831x->irq_masks_cur[offset];
 508
 509                         /* Acknowledge now so we don't miss
 510                          * notifications while we handle.
 511                          */
 512                         wm831x_reg_write(wm831x, status_addr, *status);
 513                 }
 514
 515                 if (*status & wm831x_irqs[i].mask)
 516                         handle_nested_irq(wm831x->irq_base + i);
 517
 518                 /* Simulate an edge triggered IRQ by polling the input
 519                  * status.  This is sucky but improves interoperability.
 520                  */
 521                 if (primary == WM831X_GP_INT &&
 522                     wm831x->gpio_level[i - WM831X_IRQ_GPIO_1]) {
 523                         ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
 524                         while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) {
 525                                 handle_nested_irq(wm831x->irq_base + i);
 526                                 ret = wm831x_reg_read(wm831x,
 527                                                       WM831X_GPIO_LEVEL);
 528                         }
 529                 }
 530         }
 531
 532 out:
 533         return IRQ_HANDLED;
 534 }
 535
 536 int wm831x_irq_init(struct wm831x *wm831x, int irq)
 537 {
 538         struct wm831x_pdata *pdata = wm831x->dev->platform_data;
 539         int i, cur_irq, ret;
 540
 541         mutex_init(&wm831x->irq_lock);
 542
 543         /* Mask the individual interrupt sources */
 544         for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
 545                 wm831x->irq_masks_cur[i] = 0xffff;
 546                 wm831x->irq_masks_cache[i] = 0xffff;
 547                 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
 548                                  0xffff);
 549         }
 550
 551         /* Try to dynamically allocate IRQs if no base is specified */
 552         if (!pdata || !pdata->irq_base)
 553                 wm831x->irq_base = -1;
 554         else
 555                 wm831x->irq_base = pdata->irq_base;
 556
 557         wm831x->irq_base = irq_alloc_descs(wm831x->irq_base, 0,
 558                                            WM831X_NUM_IRQS, 0);
 559         if (wm831x->irq_base < 0) {
 560                 dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n",
 561                          wm831x->irq_base);
 562                 wm831x->irq_base = 0;
 563                 return 0;
 564         }
 565
 566         if (pdata && pdata->irq_cmos)
 567                 i = 0;
 568         else
 569                 i = WM831X_IRQ_OD;
 570
 571         wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
 572                         WM831X_IRQ_OD, i);
 573
 574         /* Try to flag /IRQ as a wake source; there are a number of
 575          * unconditional wake sources in the PMIC so this isn't
 576          * conditional but we don't actually care *too* much if it
 577          * fails.
 578          */
 579         ret = enable_irq_wake(irq);
 580         if (ret != 0) {
 581                 dev_warn(wm831x->dev, "Can't enable IRQ as wake source: %d\n",
 582                          ret);
 583         }
 584
 585         wm831x->irq = irq;
 586
 587         /* Register them with genirq */
 588         for (cur_irq = wm831x->irq_base;
 589              cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base;
 590              cur_irq++) {
 591                 irq_set_chip_data(cur_irq, wm831x);
 592                 irq_set_chip_and_handler(cur_irq, &wm831x_irq_chip,
 593                                          handle_edge_irq);
 594                 irq_set_nested_thread(cur_irq, 1);
 595
 596                 /* ARM needs us to explicitly flag the IRQ as valid
 597                  * and will set them noprobe when we do so. */
 598 #ifdef CONFIG_ARM
 599                 set_irq_flags(cur_irq, IRQF_VALID);
 600 #else
 601                 irq_set_noprobe(cur_irq);
 602 #endif
 603         }
 604
 605         if (irq) {
 606                 ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
 607                                            IRQF_TRIGGER_LOW | IRQF_ONESHOT,
 608                                            "wm831x", wm831x);
 609                 if (ret != 0) {
 610                         dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
 611                                 irq, ret);
 612                         return ret;
 613                 }
 614         } else {
 615                 dev_warn(wm831x->dev,
 616                          "No interrupt specified - functionality limited\n");
 617         }
 618
 619         /* Enable top level interrupts, we mask at secondary level */
 620         wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
 621
 622         return 0;
 623 }
 624
 625 void wm831x_irq_exit(struct wm831x *wm831x)
 626 {
 627         if (wm831x->irq)
 628                 free_irq(wm831x->irq, wm831x);
 629 }