drivers/media/video/s5p-fimc/fimc-core.c

   1 /*
   2  * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
   3  *
   4  * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
   5  * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published
   9  * by the Free Software Foundation, either version 2 of the License,
  10  * or (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/errno.h>
  17 #include <linux/bug.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/list.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/clk.h>
  26 #include <media/v4l2-ioctl.h>
  27 #include <media/videobuf2-core.h>
  28 #include <media/videobuf2-dma-contig.h>
  29
  30 #include "fimc-core.h"
  31 #include "fimc-mdevice.h"
  32
  33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
  34         "sclk_fimc", "fimc"
  35 };
  36
  37 static struct fimc_fmt fimc_formats[] = {
  38         {
  39                 .name           = "RGB565",
  40                 .fourcc         = V4L2_PIX_FMT_RGB565X,
  41                 .depth          = { 16 },
  42                 .color          = S5P_FIMC_RGB565,
  43                 .memplanes      = 1,
  44                 .colplanes      = 1,
  45                 .flags          = FMT_FLAGS_M2M,
  46         }, {
  47                 .name           = "BGR666",
  48                 .fourcc         = V4L2_PIX_FMT_BGR666,
  49                 .depth          = { 32 },
  50                 .color          = S5P_FIMC_RGB666,
  51                 .memplanes      = 1,
  52                 .colplanes      = 1,
  53                 .flags          = FMT_FLAGS_M2M,
  54         }, {
  55                 .name           = "XRGB-8-8-8-8, 32 bpp",
  56                 .fourcc         = V4L2_PIX_FMT_RGB32,
  57                 .depth          = { 32 },
  58                 .color          = S5P_FIMC_RGB888,
  59                 .memplanes      = 1,
  60                 .colplanes      = 1,
  61                 .flags          = FMT_FLAGS_M2M,
  62         }, {
  63                 .name           = "YUV 4:2:2 packed, YCbYCr",
  64                 .fourcc         = V4L2_PIX_FMT_YUYV,
  65                 .depth          = { 16 },
  66                 .color          = S5P_FIMC_YCBYCR422,
  67                 .memplanes      = 1,
  68                 .colplanes      = 1,
  69                 .mbus_code      = V4L2_MBUS_FMT_YUYV8_2X8,
  70                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  71         }, {
  72                 .name           = "YUV 4:2:2 packed, CbYCrY",
  73                 .fourcc         = V4L2_PIX_FMT_UYVY,
  74                 .depth          = { 16 },
  75                 .color          = S5P_FIMC_CBYCRY422,
  76                 .memplanes      = 1,
  77                 .colplanes      = 1,
  78                 .mbus_code      = V4L2_MBUS_FMT_UYVY8_2X8,
  79                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  80         }, {
  81                 .name           = "YUV 4:2:2 packed, CrYCbY",
  82                 .fourcc         = V4L2_PIX_FMT_VYUY,
  83                 .depth          = { 16 },
  84                 .color          = S5P_FIMC_CRYCBY422,
  85                 .memplanes      = 1,
  86                 .colplanes      = 1,
  87                 .mbus_code      = V4L2_MBUS_FMT_VYUY8_2X8,
  88                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  89         }, {
  90                 .name           = "YUV 4:2:2 packed, YCrYCb",
  91                 .fourcc         = V4L2_PIX_FMT_YVYU,
  92                 .depth          = { 16 },
  93                 .color          = S5P_FIMC_YCRYCB422,
  94                 .memplanes      = 1,
  95                 .colplanes      = 1,
  96                 .mbus_code      = V4L2_MBUS_FMT_YVYU8_2X8,
  97                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  98         }, {
  99                 .name           = "YUV 4:2:2 planar, Y/Cb/Cr",
 100                 .fourcc         = V4L2_PIX_FMT_YUV422P,
 101                 .depth          = { 12 },
 102                 .color          = S5P_FIMC_YCBYCR422,
 103                 .memplanes      = 1,
 104                 .colplanes      = 3,
 105                 .flags          = FMT_FLAGS_M2M,
 106         }, {
 107                 .name           = "YUV 4:2:2 planar, Y/CbCr",
 108                 .fourcc         = V4L2_PIX_FMT_NV16,
 109                 .depth          = { 16 },
 110                 .color          = S5P_FIMC_YCBYCR422,
 111                 .memplanes      = 1,
 112                 .colplanes      = 2,
 113                 .flags          = FMT_FLAGS_M2M,
 114         }, {
 115                 .name           = "YUV 4:2:2 planar, Y/CrCb",
 116                 .fourcc         = V4L2_PIX_FMT_NV61,
 117                 .depth          = { 16 },
 118                 .color          = S5P_FIMC_YCRYCB422,
 119                 .memplanes      = 1,
 120                 .colplanes      = 2,
 121                 .flags          = FMT_FLAGS_M2M,
 122         }, {
 123                 .name           = "YUV 4:2:0 planar, YCbCr",
 124                 .fourcc         = V4L2_PIX_FMT_YUV420,
 125                 .depth          = { 12 },
 126                 .color          = S5P_FIMC_YCBCR420,
 127                 .memplanes      = 1,
 128                 .colplanes      = 3,
 129                 .flags          = FMT_FLAGS_M2M,
 130         }, {
 131                 .name           = "YUV 4:2:0 planar, Y/CbCr",
 132                 .fourcc         = V4L2_PIX_FMT_NV12,
 133                 .depth          = { 12 },
 134                 .color          = S5P_FIMC_YCBCR420,
 135                 .memplanes      = 1,
 136                 .colplanes      = 2,
 137                 .flags          = FMT_FLAGS_M2M,
 138         }, {
 139                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
 140                 .fourcc         = V4L2_PIX_FMT_NV12M,
 141                 .color          = S5P_FIMC_YCBCR420,
 142                 .depth          = { 8, 4 },
 143                 .memplanes      = 2,
 144                 .colplanes      = 2,
 145                 .flags          = FMT_FLAGS_M2M,
 146         }, {
 147                 .name           = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
 148                 .fourcc         = V4L2_PIX_FMT_YUV420M,
 149                 .color          = S5P_FIMC_YCBCR420,
 150                 .depth          = { 8, 2, 2 },
 151                 .memplanes      = 3,
 152                 .colplanes      = 3,
 153                 .flags          = FMT_FLAGS_M2M,
 154         }, {
 155                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
 156                 .fourcc         = V4L2_PIX_FMT_NV12MT,
 157                 .color          = S5P_FIMC_YCBCR420,
 158                 .depth          = { 8, 4 },
 159                 .memplanes      = 2,
 160                 .colplanes      = 2,
 161                 .flags          = FMT_FLAGS_M2M,
 162         }, {
 163                 .name           = "JPEG encoded data",
 164                 .fourcc         = V4L2_PIX_FMT_JPEG,
 165                 .color          = S5P_FIMC_JPEG,
 166                 .depth          = { 8 },
 167                 .memplanes      = 1,
 168                 .colplanes      = 1,
 169                 .mbus_code      = V4L2_MBUS_FMT_JPEG_1X8,
 170                 .flags          = FMT_FLAGS_CAM,
 171         },
 172 };
 173
 174 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
 175                             int dw, int dh, int rotation)
 176 {
 177         if (rotation == 90 || rotation == 270)
 178                 swap(dw, dh);
 179
 180         if (!ctx->scaler.enabled)
 181                 return (sw == dw && sh == dh) ? 0 : -EINVAL;
 182
 183         if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
 184                 return -EINVAL;
 185
 186         return 0;
 187 }
 188
 189 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
 190 {
 191         u32 sh = 6;
 192
 193         if (src >= 64 * tar)
 194                 return -EINVAL;
 195
 196         while (sh--) {
 197                 u32 tmp = 1 << sh;
 198                 if (src >= tar * tmp) {
 199                         *shift = sh, *ratio = tmp;
 200                         return 0;
 201                 }
 202         }
 203         *shift = 0, *ratio = 1;
 204         return 0;
 205 }
 206
 207 int fimc_set_scaler_info(struct fimc_ctx *ctx)
 208 {
 209         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 210         struct device *dev = &ctx->fimc_dev->pdev->dev;
 211         struct fimc_scaler *sc = &ctx->scaler;
 212         struct fimc_frame *s_frame = &ctx->s_frame;
 213         struct fimc_frame *d_frame = &ctx->d_frame;
 214         int tx, ty, sx, sy;
 215         int ret;
 216
 217         if (ctx->rotation == 90 || ctx->rotation == 270) {
 218                 ty = d_frame->width;
 219                 tx = d_frame->height;
 220         } else {
 221                 tx = d_frame->width;
 222                 ty = d_frame->height;
 223         }
 224         if (tx <= 0 || ty <= 0) {
 225                 dev_err(dev, "Invalid target size: %dx%d", tx, ty);
 226                 return -EINVAL;
 227         }
 228
 229         sx = s_frame->width;
 230         sy = s_frame->height;
 231         if (sx <= 0 || sy <= 0) {
 232                 dev_err(dev, "Invalid source size: %dx%d", sx, sy);
 233                 return -EINVAL;
 234         }
 235         sc->real_width = sx;
 236         sc->real_height = sy;
 237
 238         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 239         if (ret)
 240                 return ret;
 241
 242         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
 243         if (ret)
 244                 return ret;
 245
 246         sc->pre_dst_width = sx / sc->pre_hratio;
 247         sc->pre_dst_height = sy / sc->pre_vratio;
 248
 249         if (variant->has_mainscaler_ext) {
 250                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
 251                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
 252         } else {
 253                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
 254                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
 255
 256         }
 257
 258         sc->scaleup_h = (tx >= sx) ? 1 : 0;
 259         sc->scaleup_v = (ty >= sy) ? 1 : 0;
 260
 261         /* check to see if input and output size/format differ */
 262         if (s_frame->fmt->color == d_frame->fmt->color
 263                 && s_frame->width == d_frame->width
 264                 && s_frame->height == d_frame->height)
 265                 sc->copy_mode = 1;
 266         else
 267                 sc->copy_mode = 0;
 268
 269         return 0;
 270 }
 271
 272 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
 273 {
 274         struct vb2_buffer *src_vb, *dst_vb;
 275
 276         if (!ctx || !ctx->m2m_ctx)
 277                 return;
 278
 279         src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
 280         dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
 281
 282         if (src_vb && dst_vb) {
 283                 v4l2_m2m_buf_done(src_vb, vb_state);
 284                 v4l2_m2m_buf_done(dst_vb, vb_state);
 285                 v4l2_m2m_job_finish(ctx->fimc_dev->m2m.m2m_dev,
 286                                     ctx->m2m_ctx);
 287         }
 288 }
 289
 290 /* Complete the transaction which has been scheduled for execution. */
 291 static int fimc_m2m_shutdown(struct fimc_ctx *ctx)
 292 {
 293         struct fimc_dev *fimc = ctx->fimc_dev;
 294         int ret;
 295
 296         if (!fimc_m2m_pending(fimc))
 297                 return 0;
 298
 299         fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
 300
 301         ret = wait_event_timeout(fimc->irq_queue,
 302                            !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
 303                            FIMC_SHUTDOWN_TIMEOUT);
 304
 305         return ret == 0 ? -ETIMEDOUT : ret;
 306 }
 307
 308 static int start_streaming(struct vb2_queue *q, unsigned int count)
 309 {
 310         struct fimc_ctx *ctx = q->drv_priv;
 311         int ret;
 312
 313         ret = pm_runtime_get_sync(&ctx->fimc_dev->pdev->dev);
 314         return ret > 0 ? 0 : ret;
 315 }
 316
 317 static int stop_streaming(struct vb2_queue *q)
 318 {
 319         struct fimc_ctx *ctx = q->drv_priv;
 320         int ret;
 321
 322         ret = fimc_m2m_shutdown(ctx);
 323         if (ret == -ETIMEDOUT)
 324                 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
 325
 326         pm_runtime_put(&ctx->fimc_dev->pdev->dev);
 327         return 0;
 328 }
 329
 330 void fimc_capture_irq_handler(struct fimc_dev *fimc, bool final)
 331 {
 332         struct fimc_vid_cap *cap = &fimc->vid_cap;
 333         struct fimc_vid_buffer *v_buf;
 334         struct timeval *tv;
 335         struct timespec ts;
 336
 337         if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
 338                 wake_up(&fimc->irq_queue);
 339                 return;
 340         }
 341
 342         if (!list_empty(&cap->active_buf_q) &&
 343             test_bit(ST_CAPT_RUN, &fimc->state) && final) {
 344                 ktime_get_real_ts(&ts);
 345
 346                 v_buf = fimc_active_queue_pop(cap);
 347
 348                 tv = &v_buf->vb.v4l2_buf.timestamp;
 349                 tv->tv_sec = ts.tv_sec;
 350                 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
 351                 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
 352
 353                 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
 354         }
 355
 356         if (!list_empty(&cap->pending_buf_q)) {
 357
 358                 v_buf = fimc_pending_queue_pop(cap);
 359                 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
 360                 v_buf->index = cap->buf_index;
 361
 362                 /* Move the buffer to the capture active queue */
 363                 fimc_active_queue_add(cap, v_buf);
 364
 365                 dbg("next frame: %d, done frame: %d",
 366                     fimc_hw_get_frame_index(fimc), v_buf->index);
 367
 368                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 369                         cap->buf_index = 0;
 370         }
 371
 372         if (cap->active_buf_cnt == 0) {
 373                 if (final)
 374                         clear_bit(ST_CAPT_RUN, &fimc->state);
 375
 376                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 377                         cap->buf_index = 0;
 378         } else {
 379                 set_bit(ST_CAPT_RUN, &fimc->state);
 380         }
 381
 382         fimc_capture_config_update(cap->ctx);
 383
 384         dbg("frame: %d, active_buf_cnt: %d",
 385             fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
 386 }
 387
 388 static irqreturn_t fimc_irq_handler(int irq, void *priv)
 389 {
 390         struct fimc_dev *fimc = priv;
 391         struct fimc_vid_cap *cap = &fimc->vid_cap;
 392         struct fimc_ctx *ctx;
 393
 394         fimc_hw_clear_irq(fimc);
 395
 396         spin_lock(&fimc->slock);
 397
 398         if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
 399                 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
 400                         set_bit(ST_M2M_SUSPENDED, &fimc->state);
 401                         wake_up(&fimc->irq_queue);
 402                         goto out;
 403                 }
 404                 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
 405                 if (ctx != NULL) {
 406                         spin_unlock(&fimc->slock);
 407                         fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 408
 409                         spin_lock(&ctx->slock);
 410                         if (ctx->state & FIMC_CTX_SHUT) {
 411                                 ctx->state &= ~FIMC_CTX_SHUT;
 412                                 wake_up(&fimc->irq_queue);
 413                         }
 414                         spin_unlock(&ctx->slock);
 415                 }
 416                 return IRQ_HANDLED;
 417         } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
 418                 fimc_capture_irq_handler(fimc,
 419                                  !test_bit(ST_CAPT_JPEG, &fimc->state));
 420                 if (cap->active_buf_cnt == 1) {
 421                         fimc_deactivate_capture(fimc);
 422                         clear_bit(ST_CAPT_STREAM, &fimc->state);
 423                 }
 424         }
 425 out:
 426         spin_unlock(&fimc->slock);
 427         return IRQ_HANDLED;
 428 }
 429
 430 /* The color format (colplanes, memplanes) must be already configured. */
 431 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 432                       struct fimc_frame *frame, struct fimc_addr *paddr)
 433 {
 434         int ret = 0;
 435         u32 pix_size;
 436
 437         if (vb == NULL || frame == NULL)
 438                 return -EINVAL;
 439
 440         pix_size = frame->width * frame->height;
 441
 442         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 443                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 444
 445         paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
 446
 447         if (frame->fmt->memplanes == 1) {
 448                 switch (frame->fmt->colplanes) {
 449                 case 1:
 450                         paddr->cb = 0;
 451                         paddr->cr = 0;
 452                         break;
 453                 case 2:
 454                         /* decompose Y into Y/Cb */
 455                         paddr->cb = (u32)(paddr->y + pix_size);
 456                         paddr->cr = 0;
 457                         break;
 458                 case 3:
 459                         paddr->cb = (u32)(paddr->y + pix_size);
 460                         /* decompose Y into Y/Cb/Cr */
 461                         if (S5P_FIMC_YCBCR420 == frame->fmt->color)
 462                                 paddr->cr = (u32)(paddr->cb
 463                                                 + (pix_size >> 2));
 464                         else /* 422 */
 465                                 paddr->cr = (u32)(paddr->cb
 466                                                 + (pix_size >> 1));
 467                         break;
 468                 default:
 469                         return -EINVAL;
 470                 }
 471         } else {
 472                 if (frame->fmt->memplanes >= 2)
 473                         paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
 474
 475                 if (frame->fmt->memplanes == 3)
 476                         paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
 477         }
 478
 479         dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
 480             paddr->y, paddr->cb, paddr->cr, ret);
 481
 482         return ret;
 483 }
 484
 485 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
 486 void fimc_set_yuv_order(struct fimc_ctx *ctx)
 487 {
 488         /* The one only mode supported in SoC. */
 489         ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
 490         ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
 491
 492         /* Set order for 1 plane input formats. */
 493         switch (ctx->s_frame.fmt->color) {
 494         case S5P_FIMC_YCRYCB422:
 495                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
 496                 break;
 497         case S5P_FIMC_CBYCRY422:
 498                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
 499                 break;
 500         case S5P_FIMC_CRYCBY422:
 501                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
 502                 break;
 503         case S5P_FIMC_YCBYCR422:
 504         default:
 505                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
 506                 break;
 507         }
 508         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 509
 510         switch (ctx->d_frame.fmt->color) {
 511         case S5P_FIMC_YCRYCB422:
 512                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
 513                 break;
 514         case S5P_FIMC_CBYCRY422:
 515                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
 516                 break;
 517         case S5P_FIMC_CRYCBY422:
 518                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
 519                 break;
 520         case S5P_FIMC_YCBYCR422:
 521         default:
 522                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
 523                 break;
 524         }
 525         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
 526 }
 527
 528 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
 529 {
 530         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 531         u32 i, depth = 0;
 532
 533         for (i = 0; i < f->fmt->colplanes; i++)
 534                 depth += f->fmt->depth[i];
 535
 536         f->dma_offset.y_h = f->offs_h;
 537         if (!variant->pix_hoff)
 538                 f->dma_offset.y_h *= (depth >> 3);
 539
 540         f->dma_offset.y_v = f->offs_v;
 541
 542         f->dma_offset.cb_h = f->offs_h;
 543         f->dma_offset.cb_v = f->offs_v;
 544
 545         f->dma_offset.cr_h = f->offs_h;
 546         f->dma_offset.cr_v = f->offs_v;
 547
 548         if (!variant->pix_hoff) {
 549                 if (f->fmt->colplanes == 3) {
 550                         f->dma_offset.cb_h >>= 1;
 551                         f->dma_offset.cr_h >>= 1;
 552                 }
 553                 if (f->fmt->color == S5P_FIMC_YCBCR420) {
 554                         f->dma_offset.cb_v >>= 1;
 555                         f->dma_offset.cr_v >>= 1;
 556                 }
 557         }
 558
 559         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
 560             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
 561 }
 562
 563 /**
 564  * fimc_prepare_config - check dimensions, operation and color mode
 565  *                       and pre-calculate offset and the scaling coefficients.
 566  *
 567  * @ctx: hardware context information
 568  * @flags: flags indicating which parameters to check/update
 569  *
 570  * Return: 0 if dimensions are valid or non zero otherwise.
 571  */
 572 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
 573 {
 574         struct fimc_frame *s_frame, *d_frame;
 575         struct vb2_buffer *vb = NULL;
 576         int ret = 0;
 577
 578         s_frame = &ctx->s_frame;
 579         d_frame = &ctx->d_frame;
 580
 581         if (flags & FIMC_PARAMS) {
 582                 /* Prepare the DMA offset ratios for scaler. */
 583                 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
 584                 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
 585
 586                 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
 587                     s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
 588                         err("out of scaler range");
 589                         return -EINVAL;
 590                 }
 591                 fimc_set_yuv_order(ctx);
 592         }
 593
 594         if (flags & FIMC_SRC_ADDR) {
 595                 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
 596                 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
 597                 if (ret)
 598                         return ret;
 599         }
 600
 601         if (flags & FIMC_DST_ADDR) {
 602                 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
 603                 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
 604         }
 605
 606         return ret;
 607 }
 608
 609 static void fimc_dma_run(void *priv)
 610 {
 611         struct fimc_ctx *ctx = priv;
 612         struct fimc_dev *fimc;
 613         unsigned long flags;
 614         u32 ret;
 615
 616         if (WARN(!ctx, "null hardware context\n"))
 617                 return;
 618
 619         fimc = ctx->fimc_dev;
 620         spin_lock_irqsave(&fimc->slock, flags);
 621         set_bit(ST_M2M_PEND, &fimc->state);
 622
 623         spin_lock(&ctx->slock);
 624         ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
 625         ret = fimc_prepare_config(ctx, ctx->state);
 626         if (ret)
 627                 goto dma_unlock;
 628
 629         /* Reconfigure hardware if the context has changed. */
 630         if (fimc->m2m.ctx != ctx) {
 631                 ctx->state |= FIMC_PARAMS;
 632                 fimc->m2m.ctx = ctx;
 633         }
 634         fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
 635
 636         if (ctx->state & FIMC_PARAMS) {
 637                 fimc_hw_set_input_path(ctx);
 638                 fimc_hw_set_in_dma(ctx);
 639                 ret = fimc_set_scaler_info(ctx);
 640                 if (ret) {
 641                         spin_unlock(&fimc->slock);
 642                         goto dma_unlock;
 643                 }
 644                 fimc_hw_set_prescaler(ctx);
 645                 fimc_hw_set_mainscaler(ctx);
 646                 fimc_hw_set_target_format(ctx);
 647                 fimc_hw_set_rotation(ctx);
 648                 fimc_hw_set_effect(ctx, false);
 649         }
 650
 651         fimc_hw_set_output_path(ctx);
 652         if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
 653                 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
 654
 655         if (ctx->state & FIMC_PARAMS)
 656                 fimc_hw_set_out_dma(ctx);
 657
 658         fimc_activate_capture(ctx);
 659
 660         ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
 661                        FIMC_SRC_FMT | FIMC_DST_FMT);
 662         fimc_hw_activate_input_dma(fimc, true);
 663 dma_unlock:
 664         spin_unlock(&ctx->slock);
 665         spin_unlock_irqrestore(&fimc->slock, flags);
 666 }
 667
 668 static void fimc_job_abort(void *priv)
 669 {
 670         fimc_m2m_shutdown(priv);
 671 }
 672
 673 static int fimc_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
 674                             unsigned int *num_buffers, unsigned int *num_planes,
 675                             unsigned int sizes[], void *allocators[])
 676 {
 677         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 678         struct fimc_frame *f;
 679         int i;
 680
 681         f = ctx_get_frame(ctx, vq->type);
 682         if (IS_ERR(f))
 683                 return PTR_ERR(f);
 684         /*
 685          * Return number of non-contigous planes (plane buffers)
 686          * depending on the configured color format.
 687          */
 688         if (!f->fmt)
 689                 return -EINVAL;
 690
 691         *num_planes = f->fmt->memplanes;
 692         for (i = 0; i < f->fmt->memplanes; i++) {
 693                 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
 694                 allocators[i] = ctx->fimc_dev->alloc_ctx;
 695         }
 696         return 0;
 697 }
 698
 699 static int fimc_buf_prepare(struct vb2_buffer *vb)
 700 {
 701         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 702         struct fimc_frame *frame;
 703         int i;
 704
 705         frame = ctx_get_frame(ctx, vb->vb2_queue->type);
 706         if (IS_ERR(frame))
 707                 return PTR_ERR(frame);
 708
 709         for (i = 0; i < frame->fmt->memplanes; i++)
 710                 vb2_set_plane_payload(vb, i, frame->payload[i]);
 711
 712         return 0;
 713 }
 714
 715 static void fimc_buf_queue(struct vb2_buffer *vb)
 716 {
 717         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 718
 719         dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
 720
 721         if (ctx->m2m_ctx)
 722                 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
 723 }
 724
 725 static void fimc_lock(struct vb2_queue *vq)
 726 {
 727         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 728         mutex_lock(&ctx->fimc_dev->lock);
 729 }
 730
 731 static void fimc_unlock(struct vb2_queue *vq)
 732 {
 733         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 734         mutex_unlock(&ctx->fimc_dev->lock);
 735 }
 736
 737 static struct vb2_ops fimc_qops = {
 738         .queue_setup     = fimc_queue_setup,
 739         .buf_prepare     = fimc_buf_prepare,
 740         .buf_queue       = fimc_buf_queue,
 741         .wait_prepare    = fimc_unlock,
 742         .wait_finish     = fimc_lock,
 743         .stop_streaming  = stop_streaming,
 744         .start_streaming = start_streaming,
 745 };
 746
 747 /*
 748  * V4L2 controls handling
 749  */
 750 #define ctrl_to_ctx(__ctrl) \
 751         container_of((__ctrl)->handler, struct fimc_ctx, ctrl_handler)
 752
 753 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
 754 {
 755         struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
 756         struct fimc_dev *fimc = ctx->fimc_dev;
 757         struct samsung_fimc_variant *variant = fimc->variant;
 758         unsigned long flags;
 759         int ret = 0;
 760
 761         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
 762                 return 0;
 763
 764         switch (ctrl->id) {
 765         case V4L2_CID_HFLIP:
 766                 spin_lock_irqsave(&ctx->slock, flags);
 767                 ctx->hflip = ctrl->val;
 768                 break;
 769
 770         case V4L2_CID_VFLIP:
 771                 spin_lock_irqsave(&ctx->slock, flags);
 772                 ctx->vflip = ctrl->val;
 773                 break;
 774
 775         case V4L2_CID_ROTATE:
 776                 if (fimc_capture_pending(fimc) ||
 777                     fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
 778                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
 779                                         ctx->s_frame.height, ctx->d_frame.width,
 780                                         ctx->d_frame.height, ctrl->val);
 781                 }
 782                 if (ret) {
 783                         v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
 784                         return -EINVAL;
 785                 }
 786                 if ((ctrl->val == 90 || ctrl->val == 270) &&
 787                     !variant->has_out_rot)
 788                         return -EINVAL;
 789                 spin_lock_irqsave(&ctx->slock, flags);
 790                 ctx->rotation = ctrl->val;
 791                 break;
 792
 793         default:
 794                 v4l2_err(fimc->v4l2_dev, "Invalid control: 0x%X\n", ctrl->id);
 795                 return -EINVAL;
 796         }
 797         ctx->state |= FIMC_PARAMS;
 798         set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
 799         spin_unlock_irqrestore(&ctx->slock, flags);
 800         return 0;
 801 }
 802
 803 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
 804         .s_ctrl = fimc_s_ctrl,
 805 };
 806
 807 int fimc_ctrls_create(struct fimc_ctx *ctx)
 808 {
 809         if (ctx->ctrls_rdy)
 810                 return 0;
 811         v4l2_ctrl_handler_init(&ctx->ctrl_handler, 3);
 812
 813         ctx->ctrl_rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 814                                      V4L2_CID_HFLIP, 0, 1, 1, 0);
 815         ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 816                                     V4L2_CID_VFLIP, 0, 1, 1, 0);
 817         ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 818                                     V4L2_CID_ROTATE, 0, 270, 90, 0);
 819         ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
 820
 821         return ctx->ctrl_handler.error;
 822 }
 823
 824 void fimc_ctrls_delete(struct fimc_ctx *ctx)
 825 {
 826         if (ctx->ctrls_rdy) {
 827                 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
 828                 ctx->ctrls_rdy = false;
 829         }
 830 }
 831
 832 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
 833 {
 834         if (!ctx->ctrls_rdy)
 835                 return;
 836
 837         mutex_lock(&ctx->ctrl_handler.lock);
 838         v4l2_ctrl_activate(ctx->ctrl_rotate, active);
 839         v4l2_ctrl_activate(ctx->ctrl_hflip, active);
 840         v4l2_ctrl_activate(ctx->ctrl_vflip, active);
 841
 842         if (active) {
 843                 ctx->rotation = ctx->ctrl_rotate->val;
 844                 ctx->hflip    = ctx->ctrl_hflip->val;
 845                 ctx->vflip    = ctx->ctrl_vflip->val;
 846         } else {
 847                 ctx->rotation = 0;
 848                 ctx->hflip    = 0;
 849                 ctx->vflip    = 0;
 850         }
 851         mutex_unlock(&ctx->ctrl_handler.lock);
 852 }
 853
 854 /*
 855  * V4L2 ioctl handlers
 856  */
 857 static int fimc_m2m_querycap(struct file *file, void *fh,
 858                              struct v4l2_capability *cap)
 859 {
 860         struct fimc_ctx *ctx = fh_to_ctx(fh);
 861         struct fimc_dev *fimc = ctx->fimc_dev;
 862
 863         strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
 864         strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
 865         cap->bus_info[0] = 0;
 866         cap->capabilities = V4L2_CAP_STREAMING |
 867                 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
 868
 869         return 0;
 870 }
 871
 872 static int fimc_m2m_enum_fmt_mplane(struct file *file, void *priv,
 873                                     struct v4l2_fmtdesc *f)
 874 {
 875         struct fimc_fmt *fmt;
 876
 877         fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_M2M, f->index);
 878         if (!fmt)
 879                 return -EINVAL;
 880
 881         strncpy(f->description, fmt->name, sizeof(f->description) - 1);
 882         f->pixelformat = fmt->fourcc;
 883         return 0;
 884 }
 885
 886 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f)
 887 {
 888         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 889         int i;
 890
 891         pixm->width = frame->o_width;
 892         pixm->height = frame->o_height;
 893         pixm->field = V4L2_FIELD_NONE;
 894         pixm->pixelformat = frame->fmt->fourcc;
 895         pixm->colorspace = V4L2_COLORSPACE_JPEG;
 896         pixm->num_planes = frame->fmt->memplanes;
 897
 898         for (i = 0; i < pixm->num_planes; ++i) {
 899                 int bpl = frame->f_width;
 900                 if (frame->fmt->colplanes == 1) /* packed formats */
 901                         bpl = (bpl * frame->fmt->depth[0]) / 8;
 902                 pixm->plane_fmt[i].bytesperline = bpl;
 903                 pixm->plane_fmt[i].sizeimage = (frame->o_width *
 904                         frame->o_height * frame->fmt->depth[i]) / 8;
 905         }
 906         return 0;
 907 }
 908
 909 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f)
 910 {
 911         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 912
 913         frame->f_width  = pixm->plane_fmt[0].bytesperline;
 914         if (frame->fmt->colplanes == 1)
 915                 frame->f_width = (frame->f_width * 8) / frame->fmt->depth[0];
 916         frame->f_height = pixm->height;
 917         frame->width    = pixm->width;
 918         frame->height   = pixm->height;
 919         frame->o_width  = pixm->width;
 920         frame->o_height = pixm->height;
 921         frame->offs_h   = 0;
 922         frame->offs_v   = 0;
 923 }
 924
 925 /**
 926  * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
 927  * @fmt: fimc pixel format description (input)
 928  * @width: requested pixel width
 929  * @height: requested pixel height
 930  * @pix: multi-plane format to adjust
 931  */
 932 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
 933                                struct v4l2_pix_format_mplane *pix)
 934 {
 935         u32 bytesperline = 0;
 936         int i;
 937
 938         pix->colorspace = V4L2_COLORSPACE_JPEG;
 939         pix->field = V4L2_FIELD_NONE;
 940         pix->num_planes = fmt->memplanes;
 941         pix->height = height;
 942         pix->width = width;
 943
 944         for (i = 0; i < pix->num_planes; ++i) {
 945                 u32 bpl = pix->plane_fmt[i].bytesperline;
 946                 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
 947
 948                 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
 949                         bpl = pix->width; /* Planar */
 950
 951                 if (fmt->colplanes == 1 && /* Packed */
 952                     (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
 953                         bpl = (pix->width * fmt->depth[0]) / 8;
 954
 955                 if (i == 0) /* Same bytesperline for each plane. */
 956                         bytesperline = bpl;
 957
 958                 pix->plane_fmt[i].bytesperline = bytesperline;
 959                 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
 960         }
 961 }
 962
 963 static int fimc_m2m_g_fmt_mplane(struct file *file, void *fh,
 964                                  struct v4l2_format *f)
 965 {
 966         struct fimc_ctx *ctx = fh_to_ctx(fh);
 967         struct fimc_frame *frame = ctx_get_frame(ctx, f->type);
 968
 969         if (IS_ERR(frame))
 970                 return PTR_ERR(frame);
 971
 972         return fimc_fill_format(frame, f);
 973 }
 974
 975 /**
 976  * fimc_find_format - lookup fimc color format by fourcc or media bus format
 977  * @pixelformat: fourcc to match, ignored if null
 978  * @mbus_code: media bus code to match, ignored if null
 979  * @mask: the color flags to match
 980  * @index: offset in the fimc_formats array, ignored if negative
 981  */
 982 struct fimc_fmt *fimc_find_format(u32 *pixelformat, u32 *mbus_code,
 983                                   unsigned int mask, int index)
 984 {
 985         struct fimc_fmt *fmt, *def_fmt = NULL;
 986         unsigned int i;
 987         int id = 0;
 988
 989         if (index >= ARRAY_SIZE(fimc_formats))
 990                 return NULL;
 991
 992         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
 993                 fmt = &fimc_formats[i];
 994                 if (!(fmt->flags & mask))
 995                         continue;
 996                 if (pixelformat && fmt->fourcc == *pixelformat)
 997                         return fmt;
 998                 if (mbus_code && fmt->mbus_code == *mbus_code)
 999                         return fmt;
1000                 if (index == id)
1001                         def_fmt = fmt;
1002                 id++;
1003         }
1004         return def_fmt;
1005 }
1006
1007 static int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f)
1008 {
1009         struct fimc_dev *fimc = ctx->fimc_dev;
1010         struct samsung_fimc_variant *variant = fimc->variant;
1011         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1012         struct fimc_fmt *fmt;
1013         u32 max_w, mod_x, mod_y;
1014
1015         if (!IS_M2M(f->type))
1016                 return -EINVAL;
1017
1018         dbg("w: %d, h: %d", pix->width, pix->height);
1019
1020         fmt = fimc_find_format(&pix->pixelformat, NULL, FMT_FLAGS_M2M, 0);
1021         if (WARN(fmt == NULL, "Pixel format lookup failed"))
1022                 return -EINVAL;
1023
1024         if (pix->field == V4L2_FIELD_ANY)
1025                 pix->field = V4L2_FIELD_NONE;
1026         else if (pix->field != V4L2_FIELD_NONE)
1027                 return -EINVAL;
1028
1029         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1030                 max_w = variant->pix_limit->scaler_dis_w;
1031                 mod_x = ffs(variant->min_inp_pixsize) - 1;
1032         } else {
1033                 max_w = variant->pix_limit->out_rot_dis_w;
1034                 mod_x = ffs(variant->min_out_pixsize) - 1;
1035         }
1036
1037         if (tiled_fmt(fmt)) {
1038                 mod_x = 6; /* 64 x 32 pixels tile */
1039                 mod_y = 5;
1040         } else {
1041                 if (fimc->id == 1 && variant->pix_hoff)
1042                         mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
1043                 else
1044                         mod_y = mod_x;
1045         }
1046         dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_w);
1047
1048         v4l_bound_align_image(&pix->width, 16, max_w, mod_x,
1049                 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
1050
1051         fimc_adjust_mplane_format(fmt, pix->width, pix->height, &f->fmt.pix_mp);
1052         return 0;
1053 }
1054
1055 static int fimc_m2m_try_fmt_mplane(struct file *file, void *fh,
1056                                    struct v4l2_format *f)
1057 {
1058         struct fimc_ctx *ctx = fh_to_ctx(fh);
1059
1060         return fimc_try_fmt_mplane(ctx, f);
1061 }
1062
1063 static int fimc_m2m_s_fmt_mplane(struct file *file, void *fh,
1064                                  struct v4l2_format *f)
1065 {
1066         struct fimc_ctx *ctx = fh_to_ctx(fh);
1067         struct fimc_dev *fimc = ctx->fimc_dev;
1068         struct vb2_queue *vq;
1069         struct fimc_frame *frame;
1070         struct v4l2_pix_format_mplane *pix;
1071         int i, ret = 0;
1072
1073         ret = fimc_try_fmt_mplane(ctx, f);
1074         if (ret)
1075                 return ret;
1076
1077         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1078
1079         if (vb2_is_busy(vq)) {
1080                 v4l2_err(fimc->m2m.vfd, "queue (%d) busy\n", f->type);
1081                 return -EBUSY;
1082         }
1083
1084         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1085                 frame = &ctx->s_frame;
1086         else
1087                 frame = &ctx->d_frame;
1088
1089         pix = &f->fmt.pix_mp;
1090         frame->fmt = fimc_find_format(&pix->pixelformat, NULL,
1091                                       FMT_FLAGS_M2M, 0);
1092         if (!frame->fmt)
1093                 return -EINVAL;
1094
1095         for (i = 0; i < frame->fmt->colplanes; i++) {
1096                 frame->payload[i] =
1097                         (pix->width * pix->height * frame->fmt->depth[i]) / 8;
1098         }
1099
1100         fimc_fill_frame(frame, f);
1101
1102         ctx->scaler.enabled = 1;
1103
1104         if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1105                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1106         else
1107                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1108
1109         dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1110
1111         return 0;
1112 }
1113
1114 static int fimc_m2m_reqbufs(struct file *file, void *fh,
1115                             struct v4l2_requestbuffers *reqbufs)
1116 {
1117         struct fimc_ctx *ctx = fh_to_ctx(fh);
1118
1119         return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1120 }
1121
1122 static int fimc_m2m_querybuf(struct file *file, void *fh,
1123                              struct v4l2_buffer *buf)
1124 {
1125         struct fimc_ctx *ctx = fh_to_ctx(fh);
1126
1127         return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1128 }
1129
1130 static int fimc_m2m_qbuf(struct file *file, void *fh,
1131                          struct v4l2_buffer *buf)
1132 {
1133         struct fimc_ctx *ctx = fh_to_ctx(fh);
1134
1135         return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1136 }
1137
1138 static int fimc_m2m_dqbuf(struct file *file, void *fh,
1139                           struct v4l2_buffer *buf)
1140 {
1141         struct fimc_ctx *ctx = fh_to_ctx(fh);
1142
1143         return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1144 }
1145
1146 static int fimc_m2m_streamon(struct file *file, void *fh,
1147                              enum v4l2_buf_type type)
1148 {
1149         struct fimc_ctx *ctx = fh_to_ctx(fh);
1150
1151         /* The source and target color format need to be set */
1152         if (V4L2_TYPE_IS_OUTPUT(type)) {
1153                 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1154                         return -EINVAL;
1155         } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1156                 return -EINVAL;
1157         }
1158
1159         return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1160 }
1161
1162 static int fimc_m2m_streamoff(struct file *file, void *fh,
1163                             enum v4l2_buf_type type)
1164 {
1165         struct fimc_ctx *ctx = fh_to_ctx(fh);
1166
1167         return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1168 }
1169
1170 static int fimc_m2m_cropcap(struct file *file, void *fh,
1171                             struct v4l2_cropcap *cr)
1172 {
1173         struct fimc_ctx *ctx = fh_to_ctx(fh);
1174         struct fimc_frame *frame;
1175
1176         frame = ctx_get_frame(ctx, cr->type);
1177         if (IS_ERR(frame))
1178                 return PTR_ERR(frame);
1179
1180         cr->bounds.left         = 0;
1181         cr->bounds.top          = 0;
1182         cr->bounds.width        = frame->o_width;
1183         cr->bounds.height       = frame->o_height;
1184         cr->defrect             = cr->bounds;
1185
1186         return 0;
1187 }
1188
1189 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1190 {
1191         struct fimc_ctx *ctx = fh_to_ctx(fh);
1192         struct fimc_frame *frame;
1193
1194         frame = ctx_get_frame(ctx, cr->type);
1195         if (IS_ERR(frame))
1196                 return PTR_ERR(frame);
1197
1198         cr->c.left = frame->offs_h;
1199         cr->c.top = frame->offs_v;
1200         cr->c.width = frame->width;
1201         cr->c.height = frame->height;
1202
1203         return 0;
1204 }
1205
1206 static int fimc_m2m_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1207 {
1208         struct fimc_dev *fimc = ctx->fimc_dev;
1209         struct fimc_frame *f;
1210         u32 min_size, halign, depth = 0;
1211         int i;
1212
1213         if (cr->c.top < 0 || cr->c.left < 0) {
1214                 v4l2_err(fimc->m2m.vfd,
1215                         "doesn't support negative values for top & left\n");
1216                 return -EINVAL;
1217         }
1218         if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1219                 f = &ctx->d_frame;
1220         else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1221                 f = &ctx->s_frame;
1222         else
1223                 return -EINVAL;
1224
1225         min_size = (f == &ctx->s_frame) ?
1226                 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1227
1228         /* Get pixel alignment constraints. */
1229         if (fimc->id == 1 && fimc->variant->pix_hoff)
1230                 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1231         else
1232                 halign = ffs(min_size) - 1;
1233
1234         for (i = 0; i < f->fmt->colplanes; i++)
1235                 depth += f->fmt->depth[i];
1236
1237         v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1238                               ffs(min_size) - 1,
1239                               &cr->c.height, min_size, f->o_height,
1240                               halign, 64/(ALIGN(depth, 8)));
1241
1242         /* adjust left/top if cropping rectangle is out of bounds */
1243         if (cr->c.left + cr->c.width > f->o_width)
1244                 cr->c.left = f->o_width - cr->c.width;
1245         if (cr->c.top + cr->c.height > f->o_height)
1246                 cr->c.top = f->o_height - cr->c.height;
1247
1248         cr->c.left = round_down(cr->c.left, min_size);
1249         cr->c.top  = round_down(cr->c.top, fimc->variant->hor_offs_align);
1250
1251         dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1252             cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1253             f->f_width, f->f_height);
1254
1255         return 0;
1256 }
1257
1258 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1259 {
1260         struct fimc_ctx *ctx = fh_to_ctx(fh);
1261         struct fimc_dev *fimc = ctx->fimc_dev;
1262         struct fimc_frame *f;
1263         int ret;
1264
1265         ret = fimc_m2m_try_crop(ctx, cr);
1266         if (ret)
1267                 return ret;
1268
1269         f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1270                 &ctx->s_frame : &ctx->d_frame;
1271
1272         /* Check to see if scaling ratio is within supported range */
1273         if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1274                 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1275                         ret = fimc_check_scaler_ratio(ctx, cr->c.width,
1276                                         cr->c.height, ctx->d_frame.width,
1277                                         ctx->d_frame.height, ctx->rotation);
1278                 } else {
1279                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
1280                                         ctx->s_frame.height, cr->c.width,
1281                                         cr->c.height, ctx->rotation);
1282                 }
1283                 if (ret) {
1284                         v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
1285                         return -EINVAL;
1286                 }
1287         }
1288
1289         f->offs_h = cr->c.left;
1290         f->offs_v = cr->c.top;
1291         f->width  = cr->c.width;
1292         f->height = cr->c.height;
1293
1294         fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1295
1296         return 0;
1297 }
1298
1299 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1300         .vidioc_querycap                = fimc_m2m_querycap,
1301
1302         .vidioc_enum_fmt_vid_cap_mplane = fimc_m2m_enum_fmt_mplane,
1303         .vidioc_enum_fmt_vid_out_mplane = fimc_m2m_enum_fmt_mplane,
1304
1305         .vidioc_g_fmt_vid_cap_mplane    = fimc_m2m_g_fmt_mplane,
1306         .vidioc_g_fmt_vid_out_mplane    = fimc_m2m_g_fmt_mplane,
1307
1308         .vidioc_try_fmt_vid_cap_mplane  = fimc_m2m_try_fmt_mplane,
1309         .vidioc_try_fmt_vid_out_mplane  = fimc_m2m_try_fmt_mplane,
1310
1311         .vidioc_s_fmt_vid_cap_mplane    = fimc_m2m_s_fmt_mplane,
1312         .vidioc_s_fmt_vid_out_mplane    = fimc_m2m_s_fmt_mplane,
1313
1314         .vidioc_reqbufs                 = fimc_m2m_reqbufs,
1315         .vidioc_querybuf                = fimc_m2m_querybuf,
1316
1317         .vidioc_qbuf                    = fimc_m2m_qbuf,
1318         .vidioc_dqbuf                   = fimc_m2m_dqbuf,
1319
1320         .vidioc_streamon                = fimc_m2m_streamon,
1321         .vidioc_streamoff               = fimc_m2m_streamoff,
1322
1323         .vidioc_g_crop                  = fimc_m2m_g_crop,
1324         .vidioc_s_crop                  = fimc_m2m_s_crop,
1325         .vidioc_cropcap                 = fimc_m2m_cropcap
1326
1327 };
1328
1329 static int queue_init(void *priv, struct vb2_queue *src_vq,
1330                       struct vb2_queue *dst_vq)
1331 {
1332         struct fimc_ctx *ctx = priv;
1333         int ret;
1334
1335         memset(src_vq, 0, sizeof(*src_vq));
1336         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1337         src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1338         src_vq->drv_priv = ctx;
1339         src_vq->ops = &fimc_qops;
1340         src_vq->mem_ops = &vb2_dma_contig_memops;
1341         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1342
1343         ret = vb2_queue_init(src_vq);
1344         if (ret)
1345                 return ret;
1346
1347         memset(dst_vq, 0, sizeof(*dst_vq));
1348         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1349         dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1350         dst_vq->drv_priv = ctx;
1351         dst_vq->ops = &fimc_qops;
1352         dst_vq->mem_ops = &vb2_dma_contig_memops;
1353         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1354
1355         return vb2_queue_init(dst_vq);
1356 }
1357
1358 static int fimc_m2m_open(struct file *file)
1359 {
1360         struct fimc_dev *fimc = video_drvdata(file);
1361         struct fimc_ctx *ctx;
1362         int ret;
1363
1364         dbg("pid: %d, state: 0x%lx, refcnt: %d",
1365                 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1366
1367         /*
1368          * Return if the corresponding video capture node
1369          * is already opened.
1370          */
1371         if (fimc->vid_cap.refcnt > 0)
1372                 return -EBUSY;
1373
1374         ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1375         if (!ctx)
1376                 return -ENOMEM;
1377         v4l2_fh_init(&ctx->fh, fimc->m2m.vfd);
1378         ret = fimc_ctrls_create(ctx);
1379         if (ret)
1380                 goto error_fh;
1381
1382         /* Use separate control handler per file handle */
1383         ctx->fh.ctrl_handler = &ctx->ctrl_handler;
1384         file->private_data = &ctx->fh;
1385         v4l2_fh_add(&ctx->fh);
1386
1387         ctx->fimc_dev = fimc;
1388         /* Default color format */
1389         ctx->s_frame.fmt = &fimc_formats[0];
1390         ctx->d_frame.fmt = &fimc_formats[0];
1391         /* Setup the device context for memory-to-memory mode */
1392         ctx->state = FIMC_CTX_M2M;
1393         ctx->flags = 0;
1394         ctx->in_path = FIMC_DMA;
1395         ctx->out_path = FIMC_DMA;
1396         spin_lock_init(&ctx->slock);
1397
1398         ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1399         if (IS_ERR(ctx->m2m_ctx)) {
1400                 ret = PTR_ERR(ctx->m2m_ctx);
1401                 goto error_c;
1402         }
1403
1404         if (fimc->m2m.refcnt++ == 0)
1405                 set_bit(ST_M2M_RUN, &fimc->state);
1406         return 0;
1407
1408 error_c:
1409         fimc_ctrls_delete(ctx);
1410 error_fh:
1411         v4l2_fh_del(&ctx->fh);
1412         v4l2_fh_exit(&ctx->fh);
1413         kfree(ctx);
1414         return ret;
1415 }
1416
1417 static int fimc_m2m_release(struct file *file)
1418 {
1419         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1420         struct fimc_dev *fimc = ctx->fimc_dev;
1421
1422         dbg("pid: %d, state: 0x%lx, refcnt= %d",
1423                 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1424
1425         v4l2_m2m_ctx_release(ctx->m2m_ctx);
1426         fimc_ctrls_delete(ctx);
1427         v4l2_fh_del(&ctx->fh);
1428         v4l2_fh_exit(&ctx->fh);
1429
1430         if (--fimc->m2m.refcnt <= 0)
1431                 clear_bit(ST_M2M_RUN, &fimc->state);
1432         kfree(ctx);
1433         return 0;
1434 }
1435
1436 static unsigned int fimc_m2m_poll(struct file *file,
1437                                   struct poll_table_struct *wait)
1438 {
1439         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1440
1441         return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1442 }
1443
1444
1445 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1446 {
1447         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1448
1449         return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1450 }
1451
1452 static const struct v4l2_file_operations fimc_m2m_fops = {
1453         .owner          = THIS_MODULE,
1454         .open           = fimc_m2m_open,
1455         .release        = fimc_m2m_release,
1456         .poll           = fimc_m2m_poll,
1457         .unlocked_ioctl = video_ioctl2,
1458         .mmap           = fimc_m2m_mmap,
1459 };
1460
1461 static struct v4l2_m2m_ops m2m_ops = {
1462         .device_run     = fimc_dma_run,
1463         .job_abort      = fimc_job_abort,
1464 };
1465
1466 int fimc_register_m2m_device(struct fimc_dev *fimc,
1467                              struct v4l2_device *v4l2_dev)
1468 {
1469         struct video_device *vfd;
1470         struct platform_device *pdev;
1471         int ret = 0;
1472
1473         if (!fimc)
1474                 return -ENODEV;
1475
1476         pdev = fimc->pdev;
1477         fimc->v4l2_dev = v4l2_dev;
1478
1479         vfd = video_device_alloc();
1480         if (!vfd) {
1481                 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1482                 return -ENOMEM;
1483         }
1484
1485         vfd->fops       = &fimc_m2m_fops;
1486         vfd->ioctl_ops  = &fimc_m2m_ioctl_ops;
1487         vfd->v4l2_dev   = v4l2_dev;
1488         vfd->minor      = -1;
1489         vfd->release    = video_device_release;
1490         vfd->lock       = &fimc->lock;
1491
1492         snprintf(vfd->name, sizeof(vfd->name), "%s.m2m", dev_name(&pdev->dev));
1493         video_set_drvdata(vfd, fimc);
1494
1495         fimc->m2m.vfd = vfd;
1496         fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1497         if (IS_ERR(fimc->m2m.m2m_dev)) {
1498                 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1499                 ret = PTR_ERR(fimc->m2m.m2m_dev);
1500                 goto err_init;
1501         }
1502
1503         ret = media_entity_init(&vfd->entity, 0, NULL, 0);
1504         if (!ret)
1505                 return 0;
1506
1507         v4l2_m2m_release(fimc->m2m.m2m_dev);
1508 err_init:
1509         video_device_release(fimc->m2m.vfd);
1510         return ret;
1511 }
1512
1513 void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1514 {
1515         if (!fimc)
1516                 return;
1517
1518         if (fimc->m2m.m2m_dev)
1519                 v4l2_m2m_release(fimc->m2m.m2m_dev);
1520         if (fimc->m2m.vfd) {
1521                 media_entity_cleanup(&fimc->m2m.vfd->entity);
1522                 /* Can also be called if video device wasn't registered */
1523                 video_unregister_device(fimc->m2m.vfd);
1524         }
1525 }
1526
1527 static void fimc_clk_put(struct fimc_dev *fimc)
1528 {
1529         int i;
1530         for (i = 0; i < fimc->num_clocks; i++) {
1531                 if (fimc->clock[i])
1532                         clk_put(fimc->clock[i]);
1533         }
1534 }
1535
1536 static int fimc_clk_get(struct fimc_dev *fimc)
1537 {
1538         int i;
1539         for (i = 0; i < fimc->num_clocks; i++) {
1540                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1541                 if (!IS_ERR_OR_NULL(fimc->clock[i]))
1542                         continue;
1543                 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1544                         fimc_clocks[i]);
1545                 return -ENXIO;
1546         }
1547
1548         return 0;
1549 }
1550
1551 static int fimc_m2m_suspend(struct fimc_dev *fimc)
1552 {
1553         unsigned long flags;
1554         int timeout;
1555
1556         spin_lock_irqsave(&fimc->slock, flags);
1557         if (!fimc_m2m_pending(fimc)) {
1558                 spin_unlock_irqrestore(&fimc->slock, flags);
1559                 return 0;
1560         }
1561         clear_bit(ST_M2M_SUSPENDED, &fimc->state);
1562         set_bit(ST_M2M_SUSPENDING, &fimc->state);
1563         spin_unlock_irqrestore(&fimc->slock, flags);
1564
1565         timeout = wait_event_timeout(fimc->irq_queue,
1566                              test_bit(ST_M2M_SUSPENDED, &fimc->state),
1567                              FIMC_SHUTDOWN_TIMEOUT);
1568
1569         clear_bit(ST_M2M_SUSPENDING, &fimc->state);
1570         return timeout == 0 ? -EAGAIN : 0;
1571 }
1572
1573 static int fimc_m2m_resume(struct fimc_dev *fimc)
1574 {
1575         unsigned long flags;
1576
1577         spin_lock_irqsave(&fimc->slock, flags);
1578         /* Clear for full H/W setup in first run after resume */
1579         fimc->m2m.ctx = NULL;
1580         spin_unlock_irqrestore(&fimc->slock, flags);
1581
1582         if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
1583                 fimc_m2m_job_finish(fimc->m2m.ctx,
1584                                     VB2_BUF_STATE_ERROR);
1585         return 0;
1586 }
1587
1588 static int fimc_probe(struct platform_device *pdev)
1589 {
1590         struct fimc_dev *fimc;
1591         struct resource *res;
1592         struct samsung_fimc_driverdata *drv_data;
1593         struct s5p_platform_fimc *pdata;
1594         int ret = 0;
1595
1596         dev_dbg(&pdev->dev, "%s():\n", __func__);
1597
1598         drv_data = (struct samsung_fimc_driverdata *)
1599                 platform_get_device_id(pdev)->driver_data;
1600
1601         if (pdev->id >= drv_data->num_entities) {
1602                 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1603                         pdev->id);
1604                 return -EINVAL;
1605         }
1606
1607         fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1608         if (!fimc)
1609                 return -ENOMEM;
1610
1611         fimc->id = pdev->id;
1612
1613         fimc->variant = drv_data->variant[fimc->id];
1614         fimc->pdev = pdev;
1615         pdata = pdev->dev.platform_data;
1616         fimc->pdata = pdata;
1617
1618         set_bit(ST_LPM, &fimc->state);
1619
1620         init_waitqueue_head(&fimc->irq_queue);
1621         spin_lock_init(&fimc->slock);
1622         mutex_init(&fimc->lock);
1623
1624         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1625         if (!res) {
1626                 dev_err(&pdev->dev, "failed to find the registers\n");
1627                 ret = -ENOENT;
1628                 goto err_info;
1629         }
1630
1631         fimc->regs_res = request_mem_region(res->start, resource_size(res),
1632                         dev_name(&pdev->dev));
1633         if (!fimc->regs_res) {
1634                 dev_err(&pdev->dev, "failed to obtain register region\n");
1635                 ret = -ENOENT;
1636                 goto err_info;
1637         }
1638
1639         fimc->regs = ioremap(res->start, resource_size(res));
1640         if (!fimc->regs) {
1641                 dev_err(&pdev->dev, "failed to map registers\n");
1642                 ret = -ENXIO;
1643                 goto err_req_region;
1644         }
1645
1646         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1647         if (!res) {
1648                 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1649                 ret = -ENXIO;
1650                 goto err_regs_unmap;
1651         }
1652         fimc->irq = res->start;
1653
1654         fimc->num_clocks = MAX_FIMC_CLOCKS;
1655         ret = fimc_clk_get(fimc);
1656         if (ret)
1657                 goto err_regs_unmap;
1658         clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1659         clk_enable(fimc->clock[CLK_BUS]);
1660
1661         platform_set_drvdata(pdev, fimc);
1662
1663         ret = request_irq(fimc->irq, fimc_irq_handler, 0, pdev->name, fimc);
1664         if (ret) {
1665                 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1666                 goto err_clk;
1667         }
1668
1669         pm_runtime_enable(&pdev->dev);
1670         ret = pm_runtime_get_sync(&pdev->dev);
1671         if (ret < 0)
1672                 goto err_irq;
1673         /* Initialize contiguous memory allocator */
1674         fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1675         if (IS_ERR(fimc->alloc_ctx)) {
1676                 ret = PTR_ERR(fimc->alloc_ctx);
1677                 goto err_pm;
1678         }
1679
1680         dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id);
1681
1682         pm_runtime_put(&pdev->dev);
1683         return 0;
1684
1685 err_pm:
1686         pm_runtime_put(&pdev->dev);
1687 err_irq:
1688         free_irq(fimc->irq, fimc);
1689 err_clk:
1690         fimc_clk_put(fimc);
1691 err_regs_unmap:
1692         iounmap(fimc->regs);
1693 err_req_region:
1694         release_resource(fimc->regs_res);
1695         kfree(fimc->regs_res);
1696 err_info:
1697         kfree(fimc);
1698         return ret;
1699 }
1700
1701 static int fimc_runtime_resume(struct device *dev)
1702 {
1703         struct fimc_dev *fimc = dev_get_drvdata(dev);
1704
1705         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1706
1707         /* Enable clocks and perform basic initalization */
1708         clk_enable(fimc->clock[CLK_GATE]);
1709         fimc_hw_reset(fimc);
1710         if (fimc->variant->out_buf_count > 4)
1711                 fimc_hw_set_dma_seq(fimc, 0xF);
1712
1713         /* Resume the capture or mem-to-mem device */
1714         if (fimc_capture_busy(fimc))
1715                 return fimc_capture_resume(fimc);
1716         else if (fimc_m2m_pending(fimc))
1717                 return fimc_m2m_resume(fimc);
1718         return 0;
1719 }
1720
1721 static int fimc_runtime_suspend(struct device *dev)
1722 {
1723         struct fimc_dev *fimc = dev_get_drvdata(dev);
1724         int ret = 0;
1725
1726         if (fimc_capture_busy(fimc))
1727                 ret = fimc_capture_suspend(fimc);
1728         else
1729                 ret = fimc_m2m_suspend(fimc);
1730         if (!ret)
1731                 clk_disable(fimc->clock[CLK_GATE]);
1732
1733         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1734         return ret;
1735 }
1736
1737 #ifdef CONFIG_PM_SLEEP
1738 static int fimc_resume(struct device *dev)
1739 {
1740         struct fimc_dev *fimc = dev_get_drvdata(dev);
1741         unsigned long flags;
1742
1743         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1744
1745         /* Do not resume if the device was idle before system suspend */
1746         spin_lock_irqsave(&fimc->slock, flags);
1747         if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1748             (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1749                 spin_unlock_irqrestore(&fimc->slock, flags);
1750                 return 0;
1751         }
1752         fimc_hw_reset(fimc);
1753         if (fimc->variant->out_buf_count > 4)
1754                 fimc_hw_set_dma_seq(fimc, 0xF);
1755         spin_unlock_irqrestore(&fimc->slock, flags);
1756
1757         if (fimc_capture_busy(fimc))
1758                 return fimc_capture_resume(fimc);
1759
1760         return fimc_m2m_resume(fimc);
1761 }
1762
1763 static int fimc_suspend(struct device *dev)
1764 {
1765         struct fimc_dev *fimc = dev_get_drvdata(dev);
1766
1767         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1768
1769         if (test_and_set_bit(ST_LPM, &fimc->state))
1770                 return 0;
1771         if (fimc_capture_busy(fimc))
1772                 return fimc_capture_suspend(fimc);
1773
1774         return fimc_m2m_suspend(fimc);
1775 }
1776 #endif /* CONFIG_PM_SLEEP */
1777
1778 static int __devexit fimc_remove(struct platform_device *pdev)
1779 {
1780         struct fimc_dev *fimc = platform_get_drvdata(pdev);
1781
1782         pm_runtime_disable(&pdev->dev);
1783         fimc_runtime_suspend(&pdev->dev);
1784         pm_runtime_set_suspended(&pdev->dev);
1785
1786         vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1787
1788         clk_disable(fimc->clock[CLK_BUS]);
1789         fimc_clk_put(fimc);
1790         free_irq(fimc->irq, fimc);
1791         iounmap(fimc->regs);
1792         release_resource(fimc->regs_res);
1793         kfree(fimc->regs_res);
1794         kfree(fimc);
1795
1796         dev_info(&pdev->dev, "driver unloaded\n");
1797         return 0;
1798 }
1799
1800 /* Image pixel limits, similar across several FIMC HW revisions. */
1801 static struct fimc_pix_limit s5p_pix_limit[4] = {
1802         [0] = {
1803                 .scaler_en_w    = 3264,
1804                 .scaler_dis_w   = 8192,
1805                 .in_rot_en_h    = 1920,
1806                 .in_rot_dis_w   = 8192,
1807                 .out_rot_en_w   = 1920,
1808                 .out_rot_dis_w  = 4224,
1809         },
1810         [1] = {
1811                 .scaler_en_w    = 4224,
1812                 .scaler_dis_w   = 8192,
1813                 .in_rot_en_h    = 1920,
1814                 .in_rot_dis_w   = 8192,
1815                 .out_rot_en_w   = 1920,
1816                 .out_rot_dis_w  = 4224,
1817         },
1818         [2] = {
1819                 .scaler_en_w    = 1920,
1820                 .scaler_dis_w   = 8192,
1821                 .in_rot_en_h    = 1280,
1822                 .in_rot_dis_w   = 8192,
1823                 .out_rot_en_w   = 1280,
1824                 .out_rot_dis_w  = 1920,
1825         },
1826         [3] = {
1827                 .scaler_en_w    = 1920,
1828                 .scaler_dis_w   = 8192,
1829                 .in_rot_en_h    = 1366,
1830                 .in_rot_dis_w   = 8192,
1831                 .out_rot_en_w   = 1366,
1832                 .out_rot_dis_w  = 1920,
1833         },
1834 };
1835
1836 static struct samsung_fimc_variant fimc0_variant_s5p = {
1837         .has_inp_rot     = 1,
1838         .has_out_rot     = 1,
1839         .has_cam_if      = 1,
1840         .min_inp_pixsize = 16,
1841         .min_out_pixsize = 16,
1842         .hor_offs_align  = 8,
1843         .out_buf_count   = 4,
1844         .pix_limit       = &s5p_pix_limit[0],
1845 };
1846
1847 static struct samsung_fimc_variant fimc2_variant_s5p = {
1848         .has_cam_if      = 1,
1849         .min_inp_pixsize = 16,
1850         .min_out_pixsize = 16,
1851         .hor_offs_align  = 8,
1852         .out_buf_count   = 4,
1853         .pix_limit = &s5p_pix_limit[1],
1854 };
1855
1856 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1857         .pix_hoff        = 1,
1858         .has_inp_rot     = 1,
1859         .has_out_rot     = 1,
1860         .has_cam_if      = 1,
1861         .min_inp_pixsize = 16,
1862         .min_out_pixsize = 16,
1863         .hor_offs_align  = 8,
1864         .out_buf_count   = 4,
1865         .pix_limit       = &s5p_pix_limit[1],
1866 };
1867
1868 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1869         .pix_hoff        = 1,
1870         .has_inp_rot     = 1,
1871         .has_out_rot     = 1,
1872         .has_cam_if      = 1,
1873         .has_mainscaler_ext = 1,
1874         .min_inp_pixsize = 16,
1875         .min_out_pixsize = 16,
1876         .hor_offs_align  = 1,
1877         .out_buf_count   = 4,
1878         .pix_limit       = &s5p_pix_limit[2],
1879 };
1880
1881 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1882         .has_cam_if      = 1,
1883         .pix_hoff        = 1,
1884         .min_inp_pixsize = 16,
1885         .min_out_pixsize = 16,
1886         .hor_offs_align  = 8,
1887         .out_buf_count   = 4,
1888         .pix_limit       = &s5p_pix_limit[2],
1889 };
1890
1891 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1892         .pix_hoff        = 1,
1893         .has_inp_rot     = 1,
1894         .has_out_rot     = 1,
1895         .has_cam_if      = 1,
1896         .has_cistatus2   = 1,
1897         .has_mainscaler_ext = 1,
1898         .min_inp_pixsize = 16,
1899         .min_out_pixsize = 16,
1900         .hor_offs_align  = 2,
1901         .out_buf_count   = 32,
1902         .pix_limit       = &s5p_pix_limit[1],
1903 };
1904
1905 static struct samsung_fimc_variant fimc3_variant_exynos4 = {
1906         .pix_hoff        = 1,
1907         .has_cam_if      = 1,
1908         .has_cistatus2   = 1,
1909         .has_mainscaler_ext = 1,
1910         .min_inp_pixsize = 16,
1911         .min_out_pixsize = 16,
1912         .hor_offs_align  = 2,
1913         .out_buf_count   = 32,
1914         .pix_limit       = &s5p_pix_limit[3],
1915 };
1916
1917 /* S5PC100 */
1918 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1919         .variant = {
1920                 [0] = &fimc0_variant_s5p,
1921                 [1] = &fimc0_variant_s5p,
1922                 [2] = &fimc2_variant_s5p,
1923         },
1924         .num_entities = 3,
1925         .lclk_frequency = 133000000UL,
1926 };
1927
1928 /* S5PV210, S5PC110 */
1929 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1930         .variant = {
1931                 [0] = &fimc0_variant_s5pv210,
1932                 [1] = &fimc1_variant_s5pv210,
1933                 [2] = &fimc2_variant_s5pv210,
1934         },
1935         .num_entities = 3,
1936         .lclk_frequency = 166000000UL,
1937 };
1938
1939 /* S5PV310, S5PC210 */
1940 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1941         .variant = {
1942                 [0] = &fimc0_variant_exynos4,
1943                 [1] = &fimc0_variant_exynos4,
1944                 [2] = &fimc0_variant_exynos4,
1945                 [3] = &fimc3_variant_exynos4,
1946         },
1947         .num_entities = 4,
1948         .lclk_frequency = 166000000UL,
1949 };
1950
1951 static struct platform_device_id fimc_driver_ids[] = {
1952         {
1953                 .name           = "s5p-fimc",
1954                 .driver_data    = (unsigned long)&fimc_drvdata_s5p,
1955         }, {
1956                 .name           = "s5pv210-fimc",
1957                 .driver_data    = (unsigned long)&fimc_drvdata_s5pv210,
1958         }, {
1959                 .name           = "exynos4-fimc",
1960                 .driver_data    = (unsigned long)&fimc_drvdata_exynos4,
1961         },
1962         {},
1963 };
1964 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1965
1966 static const struct dev_pm_ops fimc_pm_ops = {
1967         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1968         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1969 };
1970
1971 static struct platform_driver fimc_driver = {
1972         .probe          = fimc_probe,
1973         .remove         = __devexit_p(fimc_remove),
1974         .id_table       = fimc_driver_ids,
1975         .driver = {
1976                 .name   = FIMC_MODULE_NAME,
1977                 .owner  = THIS_MODULE,
1978                 .pm     = &fimc_pm_ops,
1979         }
1980 };
1981
1982 int __init fimc_register_driver(void)
1983 {
1984         return platform_driver_probe(&fimc_driver, fimc_probe);
1985 }
1986
1987 void __exit fimc_unregister_driver(void)
1988 {
1989         platform_driver_unregister(&fimc_driver);
1990 }