2 * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
4 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
5 * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/errno.h>
17 #include <linux/bug.h>
18 #include <linux/interrupt.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/list.h>
24 #include <linux/slab.h>
25 #include <linux/clk.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
30 #include "fimc-core.h"
31 #include "fimc-mdevice.h"
33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
37 static struct fimc_fmt fimc_formats[] = {
40 .fourcc = V4L2_PIX_FMT_RGB565,
42 .color = S5P_FIMC_RGB565,
45 .flags = FMT_FLAGS_M2M,
48 .fourcc = V4L2_PIX_FMT_BGR666,
50 .color = S5P_FIMC_RGB666,
53 .flags = FMT_FLAGS_M2M,
55 .name = "XRGB-8-8-8-8, 32 bpp",
56 .fourcc = V4L2_PIX_FMT_RGB32,
58 .color = S5P_FIMC_RGB888,
61 .flags = FMT_FLAGS_M2M,
63 .name = "YUV 4:2:2 packed, YCbYCr",
64 .fourcc = V4L2_PIX_FMT_YUYV,
66 .color = S5P_FIMC_YCBYCR422,
69 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
70 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
72 .name = "YUV 4:2:2 packed, CbYCrY",
73 .fourcc = V4L2_PIX_FMT_UYVY,
75 .color = S5P_FIMC_CBYCRY422,
78 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
79 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
81 .name = "YUV 4:2:2 packed, CrYCbY",
82 .fourcc = V4L2_PIX_FMT_VYUY,
84 .color = S5P_FIMC_CRYCBY422,
87 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
88 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
90 .name = "YUV 4:2:2 packed, YCrYCb",
91 .fourcc = V4L2_PIX_FMT_YVYU,
93 .color = S5P_FIMC_YCRYCB422,
96 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
97 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
99 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
100 .fourcc = V4L2_PIX_FMT_YUV422P,
102 .color = S5P_FIMC_YCBYCR422,
105 .flags = FMT_FLAGS_M2M,
107 .name = "YUV 4:2:2 planar, Y/CbCr",
108 .fourcc = V4L2_PIX_FMT_NV16,
110 .color = S5P_FIMC_YCBYCR422,
113 .flags = FMT_FLAGS_M2M,
115 .name = "YUV 4:2:2 planar, Y/CrCb",
116 .fourcc = V4L2_PIX_FMT_NV61,
118 .color = S5P_FIMC_YCRYCB422,
121 .flags = FMT_FLAGS_M2M,
123 .name = "YUV 4:2:0 planar, YCbCr",
124 .fourcc = V4L2_PIX_FMT_YUV420,
126 .color = S5P_FIMC_YCBCR420,
129 .flags = FMT_FLAGS_M2M,
131 .name = "YUV 4:2:0 planar, Y/CbCr",
132 .fourcc = V4L2_PIX_FMT_NV12,
134 .color = S5P_FIMC_YCBCR420,
137 .flags = FMT_FLAGS_M2M,
139 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
140 .fourcc = V4L2_PIX_FMT_NV12M,
141 .color = S5P_FIMC_YCBCR420,
145 .flags = FMT_FLAGS_M2M,
147 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
148 .fourcc = V4L2_PIX_FMT_YUV420M,
149 .color = S5P_FIMC_YCBCR420,
150 .depth = { 8, 2, 2 },
153 .flags = FMT_FLAGS_M2M,
155 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
156 .fourcc = V4L2_PIX_FMT_NV12MT,
157 .color = S5P_FIMC_YCBCR420,
161 .flags = FMT_FLAGS_M2M,
163 .name = "JPEG encoded data",
164 .fourcc = V4L2_PIX_FMT_JPEG,
165 .color = S5P_FIMC_JPEG,
169 .mbus_code = V4L2_MBUS_FMT_JPEG_1X8,
170 .flags = FMT_FLAGS_CAM,
174 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
175 int dw, int dh, int rotation)
177 if (rotation == 90 || rotation == 270)
180 if (!ctx->scaler.enabled)
181 return (sw == dw && sh == dh) ? 0 : -EINVAL;
183 if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
189 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
198 if (src >= tar * tmp) {
199 *shift = sh, *ratio = tmp;
203 *shift = 0, *ratio = 1;
207 int fimc_set_scaler_info(struct fimc_ctx *ctx)
209 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
210 struct device *dev = &ctx->fimc_dev->pdev->dev;
211 struct fimc_scaler *sc = &ctx->scaler;
212 struct fimc_frame *s_frame = &ctx->s_frame;
213 struct fimc_frame *d_frame = &ctx->d_frame;
217 if (ctx->rotation == 90 || ctx->rotation == 270) {
219 tx = d_frame->height;
222 ty = d_frame->height;
224 if (tx <= 0 || ty <= 0) {
225 dev_err(dev, "Invalid target size: %dx%d", tx, ty);
230 sy = s_frame->height;
231 if (sx <= 0 || sy <= 0) {
232 dev_err(dev, "Invalid source size: %dx%d", sx, sy);
236 sc->real_height = sy;
238 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
242 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
246 sc->pre_dst_width = sx / sc->pre_hratio;
247 sc->pre_dst_height = sy / sc->pre_vratio;
249 if (variant->has_mainscaler_ext) {
250 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
251 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
253 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
254 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
258 sc->scaleup_h = (tx >= sx) ? 1 : 0;
259 sc->scaleup_v = (ty >= sy) ? 1 : 0;
261 /* check to see if input and output size/format differ */
262 if (s_frame->fmt->color == d_frame->fmt->color
263 && s_frame->width == d_frame->width
264 && s_frame->height == d_frame->height)
272 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
274 struct vb2_buffer *src_vb, *dst_vb;
276 if (!ctx || !ctx->m2m_ctx)
279 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
280 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
282 if (src_vb && dst_vb) {
283 v4l2_m2m_buf_done(src_vb, vb_state);
284 v4l2_m2m_buf_done(dst_vb, vb_state);
285 v4l2_m2m_job_finish(ctx->fimc_dev->m2m.m2m_dev,
290 /* Complete the transaction which has been scheduled for execution. */
291 static int fimc_m2m_shutdown(struct fimc_ctx *ctx)
293 struct fimc_dev *fimc = ctx->fimc_dev;
296 if (!fimc_m2m_pending(fimc))
299 fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
301 ret = wait_event_timeout(fimc->irq_queue,
302 !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
303 FIMC_SHUTDOWN_TIMEOUT);
305 return ret == 0 ? -ETIMEDOUT : ret;
308 static int start_streaming(struct vb2_queue *q, unsigned int count)
310 struct fimc_ctx *ctx = q->drv_priv;
313 ret = pm_runtime_get_sync(&ctx->fimc_dev->pdev->dev);
314 return ret > 0 ? 0 : ret;
317 static int stop_streaming(struct vb2_queue *q)
319 struct fimc_ctx *ctx = q->drv_priv;
322 ret = fimc_m2m_shutdown(ctx);
323 if (ret == -ETIMEDOUT)
324 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
326 pm_runtime_put(&ctx->fimc_dev->pdev->dev);
330 void fimc_capture_irq_handler(struct fimc_dev *fimc, bool final)
332 struct fimc_vid_cap *cap = &fimc->vid_cap;
333 struct fimc_vid_buffer *v_buf;
337 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
338 wake_up(&fimc->irq_queue);
342 if (!list_empty(&cap->active_buf_q) &&
343 test_bit(ST_CAPT_RUN, &fimc->state) && final) {
344 ktime_get_real_ts(&ts);
346 v_buf = fimc_active_queue_pop(cap);
348 tv = &v_buf->vb.v4l2_buf.timestamp;
349 tv->tv_sec = ts.tv_sec;
350 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
351 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
353 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
356 if (!list_empty(&cap->pending_buf_q)) {
358 v_buf = fimc_pending_queue_pop(cap);
359 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
360 v_buf->index = cap->buf_index;
362 /* Move the buffer to the capture active queue */
363 fimc_active_queue_add(cap, v_buf);
365 dbg("next frame: %d, done frame: %d",
366 fimc_hw_get_frame_index(fimc), v_buf->index);
368 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
372 if (cap->active_buf_cnt == 0) {
374 clear_bit(ST_CAPT_RUN, &fimc->state);
376 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
379 set_bit(ST_CAPT_RUN, &fimc->state);
382 fimc_capture_config_update(cap->ctx);
384 dbg("frame: %d, active_buf_cnt: %d",
385 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
388 static irqreturn_t fimc_irq_handler(int irq, void *priv)
390 struct fimc_dev *fimc = priv;
391 struct fimc_vid_cap *cap = &fimc->vid_cap;
392 struct fimc_ctx *ctx;
394 fimc_hw_clear_irq(fimc);
396 spin_lock(&fimc->slock);
398 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
399 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
400 set_bit(ST_M2M_SUSPENDED, &fimc->state);
401 wake_up(&fimc->irq_queue);
404 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
406 spin_unlock(&fimc->slock);
407 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
409 spin_lock(&ctx->slock);
410 if (ctx->state & FIMC_CTX_SHUT) {
411 ctx->state &= ~FIMC_CTX_SHUT;
412 wake_up(&fimc->irq_queue);
414 spin_unlock(&ctx->slock);
417 } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
418 fimc_capture_irq_handler(fimc,
419 !test_bit(ST_CAPT_JPEG, &fimc->state));
420 if (cap->active_buf_cnt == 1) {
421 fimc_deactivate_capture(fimc);
422 clear_bit(ST_CAPT_STREAM, &fimc->state);
426 spin_unlock(&fimc->slock);
430 /* The color format (colplanes, memplanes) must be already configured. */
431 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
432 struct fimc_frame *frame, struct fimc_addr *paddr)
437 if (vb == NULL || frame == NULL)
440 pix_size = frame->width * frame->height;
442 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
443 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
445 paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
447 if (frame->fmt->memplanes == 1) {
448 switch (frame->fmt->colplanes) {
454 /* decompose Y into Y/Cb */
455 paddr->cb = (u32)(paddr->y + pix_size);
459 paddr->cb = (u32)(paddr->y + pix_size);
460 /* decompose Y into Y/Cb/Cr */
461 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
462 paddr->cr = (u32)(paddr->cb
465 paddr->cr = (u32)(paddr->cb
472 if (frame->fmt->memplanes >= 2)
473 paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
475 if (frame->fmt->memplanes == 3)
476 paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
479 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
480 paddr->y, paddr->cb, paddr->cr, ret);
485 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
486 void fimc_set_yuv_order(struct fimc_ctx *ctx)
488 /* The one only mode supported in SoC. */
489 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
490 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
492 /* Set order for 1 plane input formats. */
493 switch (ctx->s_frame.fmt->color) {
494 case S5P_FIMC_YCRYCB422:
495 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
497 case S5P_FIMC_CBYCRY422:
498 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
500 case S5P_FIMC_CRYCBY422:
501 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
503 case S5P_FIMC_YCBYCR422:
505 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
508 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
510 switch (ctx->d_frame.fmt->color) {
511 case S5P_FIMC_YCRYCB422:
512 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
514 case S5P_FIMC_CBYCRY422:
515 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
517 case S5P_FIMC_CRYCBY422:
518 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
520 case S5P_FIMC_YCBYCR422:
522 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
525 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
528 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
530 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
533 for (i = 0; i < f->fmt->colplanes; i++)
534 depth += f->fmt->depth[i];
536 f->dma_offset.y_h = f->offs_h;
537 if (!variant->pix_hoff)
538 f->dma_offset.y_h *= (depth >> 3);
540 f->dma_offset.y_v = f->offs_v;
542 f->dma_offset.cb_h = f->offs_h;
543 f->dma_offset.cb_v = f->offs_v;
545 f->dma_offset.cr_h = f->offs_h;
546 f->dma_offset.cr_v = f->offs_v;
548 if (!variant->pix_hoff) {
549 if (f->fmt->colplanes == 3) {
550 f->dma_offset.cb_h >>= 1;
551 f->dma_offset.cr_h >>= 1;
553 if (f->fmt->color == S5P_FIMC_YCBCR420) {
554 f->dma_offset.cb_v >>= 1;
555 f->dma_offset.cr_v >>= 1;
559 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
560 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
564 * fimc_prepare_config - check dimensions, operation and color mode
565 * and pre-calculate offset and the scaling coefficients.
567 * @ctx: hardware context information
568 * @flags: flags indicating which parameters to check/update
570 * Return: 0 if dimensions are valid or non zero otherwise.
572 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
574 struct fimc_frame *s_frame, *d_frame;
575 struct vb2_buffer *vb = NULL;
578 s_frame = &ctx->s_frame;
579 d_frame = &ctx->d_frame;
581 if (flags & FIMC_PARAMS) {
582 /* Prepare the DMA offset ratios for scaler. */
583 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
584 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
586 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
587 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
588 err("out of scaler range");
591 fimc_set_yuv_order(ctx);
594 if (flags & FIMC_SRC_ADDR) {
595 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
596 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
601 if (flags & FIMC_DST_ADDR) {
602 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
603 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
609 static void fimc_dma_run(void *priv)
611 struct fimc_ctx *ctx = priv;
612 struct fimc_dev *fimc;
616 if (WARN(!ctx, "null hardware context\n"))
619 fimc = ctx->fimc_dev;
620 spin_lock_irqsave(&fimc->slock, flags);
621 set_bit(ST_M2M_PEND, &fimc->state);
623 spin_lock(&ctx->slock);
624 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
625 ret = fimc_prepare_config(ctx, ctx->state);
629 /* Reconfigure hardware if the context has changed. */
630 if (fimc->m2m.ctx != ctx) {
631 ctx->state |= FIMC_PARAMS;
634 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
636 if (ctx->state & FIMC_PARAMS) {
637 fimc_hw_set_input_path(ctx);
638 fimc_hw_set_in_dma(ctx);
639 ret = fimc_set_scaler_info(ctx);
641 spin_unlock(&fimc->slock);
644 fimc_hw_set_prescaler(ctx);
645 fimc_hw_set_mainscaler(ctx);
646 fimc_hw_set_target_format(ctx);
647 fimc_hw_set_rotation(ctx);
648 fimc_hw_set_effect(ctx, false);
651 fimc_hw_set_output_path(ctx);
652 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
653 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
655 if (ctx->state & FIMC_PARAMS)
656 fimc_hw_set_out_dma(ctx);
658 fimc_activate_capture(ctx);
660 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
661 FIMC_SRC_FMT | FIMC_DST_FMT);
662 fimc_hw_activate_input_dma(fimc, true);
664 spin_unlock(&ctx->slock);
665 spin_unlock_irqrestore(&fimc->slock, flags);
668 static void fimc_job_abort(void *priv)
670 fimc_m2m_shutdown(priv);
673 static int fimc_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
674 unsigned int *num_buffers, unsigned int *num_planes,
675 unsigned int sizes[], void *allocators[])
677 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
678 struct fimc_frame *f;
681 f = ctx_get_frame(ctx, vq->type);
685 * Return number of non-contigous planes (plane buffers)
686 * depending on the configured color format.
691 *num_planes = f->fmt->memplanes;
692 for (i = 0; i < f->fmt->memplanes; i++) {
693 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
694 allocators[i] = ctx->fimc_dev->alloc_ctx;
699 static int fimc_buf_prepare(struct vb2_buffer *vb)
701 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
702 struct fimc_frame *frame;
705 frame = ctx_get_frame(ctx, vb->vb2_queue->type);
707 return PTR_ERR(frame);
709 for (i = 0; i < frame->fmt->memplanes; i++)
710 vb2_set_plane_payload(vb, i, frame->payload[i]);
715 static void fimc_buf_queue(struct vb2_buffer *vb)
717 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
719 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
722 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
725 static void fimc_lock(struct vb2_queue *vq)
727 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
728 mutex_lock(&ctx->fimc_dev->lock);
731 static void fimc_unlock(struct vb2_queue *vq)
733 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
734 mutex_unlock(&ctx->fimc_dev->lock);
737 static struct vb2_ops fimc_qops = {
738 .queue_setup = fimc_queue_setup,
739 .buf_prepare = fimc_buf_prepare,
740 .buf_queue = fimc_buf_queue,
741 .wait_prepare = fimc_unlock,
742 .wait_finish = fimc_lock,
743 .stop_streaming = stop_streaming,
744 .start_streaming = start_streaming,
748 * V4L2 controls handling
750 #define ctrl_to_ctx(__ctrl) \
751 container_of((__ctrl)->handler, struct fimc_ctx, ctrl_handler)
753 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
755 struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
756 struct fimc_dev *fimc = ctx->fimc_dev;
757 struct samsung_fimc_variant *variant = fimc->variant;
761 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
766 spin_lock_irqsave(&ctx->slock, flags);
767 ctx->hflip = ctrl->val;
771 spin_lock_irqsave(&ctx->slock, flags);
772 ctx->vflip = ctrl->val;
775 case V4L2_CID_ROTATE:
776 if (fimc_capture_pending(fimc) ||
777 fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
778 ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
779 ctx->s_frame.height, ctx->d_frame.width,
780 ctx->d_frame.height, ctrl->val);
783 v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
786 if ((ctrl->val == 90 || ctrl->val == 270) &&
787 !variant->has_out_rot)
789 spin_lock_irqsave(&ctx->slock, flags);
790 ctx->rotation = ctrl->val;
794 v4l2_err(fimc->v4l2_dev, "Invalid control: 0x%X\n", ctrl->id);
797 ctx->state |= FIMC_PARAMS;
798 set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
799 spin_unlock_irqrestore(&ctx->slock, flags);
803 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
804 .s_ctrl = fimc_s_ctrl,
807 int fimc_ctrls_create(struct fimc_ctx *ctx)
811 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 3);
813 ctx->ctrl_rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
814 V4L2_CID_HFLIP, 0, 1, 1, 0);
815 ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
816 V4L2_CID_VFLIP, 0, 1, 1, 0);
817 ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
818 V4L2_CID_ROTATE, 0, 270, 90, 0);
819 ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
821 return ctx->ctrl_handler.error;
824 void fimc_ctrls_delete(struct fimc_ctx *ctx)
826 if (ctx->ctrls_rdy) {
827 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
828 ctx->ctrls_rdy = false;
832 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
837 mutex_lock(&ctx->ctrl_handler.lock);
838 v4l2_ctrl_activate(ctx->ctrl_rotate, active);
839 v4l2_ctrl_activate(ctx->ctrl_hflip, active);
840 v4l2_ctrl_activate(ctx->ctrl_vflip, active);
843 ctx->rotation = ctx->ctrl_rotate->val;
844 ctx->hflip = ctx->ctrl_hflip->val;
845 ctx->vflip = ctx->ctrl_vflip->val;
851 mutex_unlock(&ctx->ctrl_handler.lock);
855 * V4L2 ioctl handlers
857 static int fimc_m2m_querycap(struct file *file, void *fh,
858 struct v4l2_capability *cap)
860 struct fimc_ctx *ctx = fh_to_ctx(fh);
861 struct fimc_dev *fimc = ctx->fimc_dev;
863 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
864 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
865 cap->bus_info[0] = 0;
866 cap->capabilities = V4L2_CAP_STREAMING |
867 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
872 static int fimc_m2m_enum_fmt_mplane(struct file *file, void *priv,
873 struct v4l2_fmtdesc *f)
875 struct fimc_fmt *fmt;
877 fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_M2M, f->index);
881 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
882 f->pixelformat = fmt->fourcc;
886 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f)
888 struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
891 pixm->width = frame->o_width;
892 pixm->height = frame->o_height;
893 pixm->field = V4L2_FIELD_NONE;
894 pixm->pixelformat = frame->fmt->fourcc;
895 pixm->colorspace = V4L2_COLORSPACE_JPEG;
896 pixm->num_planes = frame->fmt->memplanes;
898 for (i = 0; i < pixm->num_planes; ++i) {
899 int bpl = frame->f_width;
900 if (frame->fmt->colplanes == 1) /* packed formats */
901 bpl = (bpl * frame->fmt->depth[0]) / 8;
902 pixm->plane_fmt[i].bytesperline = bpl;
903 pixm->plane_fmt[i].sizeimage = (frame->o_width *
904 frame->o_height * frame->fmt->depth[i]) / 8;
909 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f)
911 struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
913 frame->f_width = pixm->plane_fmt[0].bytesperline;
914 if (frame->fmt->colplanes == 1)
915 frame->f_width = (frame->f_width * 8) / frame->fmt->depth[0];
916 frame->f_height = pixm->height;
917 frame->width = pixm->width;
918 frame->height = pixm->height;
919 frame->o_width = pixm->width;
920 frame->o_height = pixm->height;
926 * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
927 * @fmt: fimc pixel format description (input)
928 * @width: requested pixel width
929 * @height: requested pixel height
930 * @pix: multi-plane format to adjust
932 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
933 struct v4l2_pix_format_mplane *pix)
935 u32 bytesperline = 0;
938 pix->colorspace = V4L2_COLORSPACE_JPEG;
939 pix->field = V4L2_FIELD_NONE;
940 pix->num_planes = fmt->memplanes;
941 pix->height = height;
944 for (i = 0; i < pix->num_planes; ++i) {
945 u32 bpl = pix->plane_fmt[i].bytesperline;
946 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
948 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
949 bpl = pix->width; /* Planar */
951 if (fmt->colplanes == 1 && /* Packed */
952 (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
953 bpl = (pix->width * fmt->depth[0]) / 8;
955 if (i == 0) /* Same bytesperline for each plane. */
958 pix->plane_fmt[i].bytesperline = bytesperline;
959 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
963 static int fimc_m2m_g_fmt_mplane(struct file *file, void *fh,
964 struct v4l2_format *f)
966 struct fimc_ctx *ctx = fh_to_ctx(fh);
967 struct fimc_frame *frame = ctx_get_frame(ctx, f->type);
970 return PTR_ERR(frame);
972 return fimc_fill_format(frame, f);
976 * fimc_find_format - lookup fimc color format by fourcc or media bus format
977 * @pixelformat: fourcc to match, ignored if null
978 * @mbus_code: media bus code to match, ignored if null
979 * @mask: the color flags to match
980 * @index: offset in the fimc_formats array, ignored if negative
982 struct fimc_fmt *fimc_find_format(u32 *pixelformat, u32 *mbus_code,
983 unsigned int mask, int index)
985 struct fimc_fmt *fmt, *def_fmt = NULL;
989 if (index >= ARRAY_SIZE(fimc_formats))
992 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
993 fmt = &fimc_formats[i];
994 if (!(fmt->flags & mask))
996 if (pixelformat && fmt->fourcc == *pixelformat)
998 if (mbus_code && fmt->mbus_code == *mbus_code)
1007 static int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f)
1009 struct fimc_dev *fimc = ctx->fimc_dev;
1010 struct samsung_fimc_variant *variant = fimc->variant;
1011 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1012 struct fimc_fmt *fmt;
1013 u32 max_w, mod_x, mod_y;
1015 if (!IS_M2M(f->type))
1018 dbg("w: %d, h: %d", pix->width, pix->height);
1020 fmt = fimc_find_format(&pix->pixelformat, NULL, FMT_FLAGS_M2M, 0);
1021 if (WARN(fmt == NULL, "Pixel format lookup failed"))
1024 if (pix->field == V4L2_FIELD_ANY)
1025 pix->field = V4L2_FIELD_NONE;
1026 else if (pix->field != V4L2_FIELD_NONE)
1029 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1030 max_w = variant->pix_limit->scaler_dis_w;
1031 mod_x = ffs(variant->min_inp_pixsize) - 1;
1033 max_w = variant->pix_limit->out_rot_dis_w;
1034 mod_x = ffs(variant->min_out_pixsize) - 1;
1037 if (tiled_fmt(fmt)) {
1038 mod_x = 6; /* 64 x 32 pixels tile */
1041 if (variant->min_vsize_align == 1)
1042 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
1044 mod_y = ffs(variant->min_vsize_align) - 1;
1047 v4l_bound_align_image(&pix->width, 16, max_w, mod_x,
1048 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
1050 fimc_adjust_mplane_format(fmt, pix->width, pix->height, &f->fmt.pix_mp);
1054 static int fimc_m2m_try_fmt_mplane(struct file *file, void *fh,
1055 struct v4l2_format *f)
1057 struct fimc_ctx *ctx = fh_to_ctx(fh);
1059 return fimc_try_fmt_mplane(ctx, f);
1062 static int fimc_m2m_s_fmt_mplane(struct file *file, void *fh,
1063 struct v4l2_format *f)
1065 struct fimc_ctx *ctx = fh_to_ctx(fh);
1066 struct fimc_dev *fimc = ctx->fimc_dev;
1067 struct vb2_queue *vq;
1068 struct fimc_frame *frame;
1069 struct v4l2_pix_format_mplane *pix;
1072 ret = fimc_try_fmt_mplane(ctx, f);
1076 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1078 if (vb2_is_busy(vq)) {
1079 v4l2_err(fimc->m2m.vfd, "queue (%d) busy\n", f->type);
1083 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1084 frame = &ctx->s_frame;
1086 frame = &ctx->d_frame;
1088 pix = &f->fmt.pix_mp;
1089 frame->fmt = fimc_find_format(&pix->pixelformat, NULL,
1094 for (i = 0; i < frame->fmt->colplanes; i++) {
1096 (pix->width * pix->height * frame->fmt->depth[i]) / 8;
1099 fimc_fill_frame(frame, f);
1101 ctx->scaler.enabled = 1;
1103 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1104 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1106 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1108 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1113 static int fimc_m2m_reqbufs(struct file *file, void *fh,
1114 struct v4l2_requestbuffers *reqbufs)
1116 struct fimc_ctx *ctx = fh_to_ctx(fh);
1118 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1121 static int fimc_m2m_querybuf(struct file *file, void *fh,
1122 struct v4l2_buffer *buf)
1124 struct fimc_ctx *ctx = fh_to_ctx(fh);
1126 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1129 static int fimc_m2m_qbuf(struct file *file, void *fh,
1130 struct v4l2_buffer *buf)
1132 struct fimc_ctx *ctx = fh_to_ctx(fh);
1134 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1137 static int fimc_m2m_dqbuf(struct file *file, void *fh,
1138 struct v4l2_buffer *buf)
1140 struct fimc_ctx *ctx = fh_to_ctx(fh);
1142 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1145 static int fimc_m2m_streamon(struct file *file, void *fh,
1146 enum v4l2_buf_type type)
1148 struct fimc_ctx *ctx = fh_to_ctx(fh);
1150 /* The source and target color format need to be set */
1151 if (V4L2_TYPE_IS_OUTPUT(type)) {
1152 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1154 } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1158 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1161 static int fimc_m2m_streamoff(struct file *file, void *fh,
1162 enum v4l2_buf_type type)
1164 struct fimc_ctx *ctx = fh_to_ctx(fh);
1166 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1169 static int fimc_m2m_cropcap(struct file *file, void *fh,
1170 struct v4l2_cropcap *cr)
1172 struct fimc_ctx *ctx = fh_to_ctx(fh);
1173 struct fimc_frame *frame;
1175 frame = ctx_get_frame(ctx, cr->type);
1177 return PTR_ERR(frame);
1179 cr->bounds.left = 0;
1181 cr->bounds.width = frame->o_width;
1182 cr->bounds.height = frame->o_height;
1183 cr->defrect = cr->bounds;
1188 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1190 struct fimc_ctx *ctx = fh_to_ctx(fh);
1191 struct fimc_frame *frame;
1193 frame = ctx_get_frame(ctx, cr->type);
1195 return PTR_ERR(frame);
1197 cr->c.left = frame->offs_h;
1198 cr->c.top = frame->offs_v;
1199 cr->c.width = frame->width;
1200 cr->c.height = frame->height;
1205 static int fimc_m2m_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1207 struct fimc_dev *fimc = ctx->fimc_dev;
1208 struct fimc_frame *f;
1209 u32 min_size, halign, depth = 0;
1212 if (cr->c.top < 0 || cr->c.left < 0) {
1213 v4l2_err(fimc->m2m.vfd,
1214 "doesn't support negative values for top & left\n");
1217 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1219 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1224 min_size = (f == &ctx->s_frame) ?
1225 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1227 /* Get pixel alignment constraints. */
1228 if (fimc->variant->min_vsize_align == 1)
1229 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1231 halign = ffs(fimc->variant->min_vsize_align) - 1;
1233 for (i = 0; i < f->fmt->colplanes; i++)
1234 depth += f->fmt->depth[i];
1236 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1238 &cr->c.height, min_size, f->o_height,
1239 halign, 64/(ALIGN(depth, 8)));
1241 /* adjust left/top if cropping rectangle is out of bounds */
1242 if (cr->c.left + cr->c.width > f->o_width)
1243 cr->c.left = f->o_width - cr->c.width;
1244 if (cr->c.top + cr->c.height > f->o_height)
1245 cr->c.top = f->o_height - cr->c.height;
1247 cr->c.left = round_down(cr->c.left, min_size);
1248 cr->c.top = round_down(cr->c.top, fimc->variant->hor_offs_align);
1250 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1251 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1252 f->f_width, f->f_height);
1257 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1259 struct fimc_ctx *ctx = fh_to_ctx(fh);
1260 struct fimc_dev *fimc = ctx->fimc_dev;
1261 struct fimc_frame *f;
1264 ret = fimc_m2m_try_crop(ctx, cr);
1268 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1269 &ctx->s_frame : &ctx->d_frame;
1271 /* Check to see if scaling ratio is within supported range */
1272 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1273 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1274 ret = fimc_check_scaler_ratio(ctx, cr->c.width,
1275 cr->c.height, ctx->d_frame.width,
1276 ctx->d_frame.height, ctx->rotation);
1278 ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
1279 ctx->s_frame.height, cr->c.width,
1280 cr->c.height, ctx->rotation);
1283 v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
1288 f->offs_h = cr->c.left;
1289 f->offs_v = cr->c.top;
1290 f->width = cr->c.width;
1291 f->height = cr->c.height;
1293 fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1298 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1299 .vidioc_querycap = fimc_m2m_querycap,
1301 .vidioc_enum_fmt_vid_cap_mplane = fimc_m2m_enum_fmt_mplane,
1302 .vidioc_enum_fmt_vid_out_mplane = fimc_m2m_enum_fmt_mplane,
1304 .vidioc_g_fmt_vid_cap_mplane = fimc_m2m_g_fmt_mplane,
1305 .vidioc_g_fmt_vid_out_mplane = fimc_m2m_g_fmt_mplane,
1307 .vidioc_try_fmt_vid_cap_mplane = fimc_m2m_try_fmt_mplane,
1308 .vidioc_try_fmt_vid_out_mplane = fimc_m2m_try_fmt_mplane,
1310 .vidioc_s_fmt_vid_cap_mplane = fimc_m2m_s_fmt_mplane,
1311 .vidioc_s_fmt_vid_out_mplane = fimc_m2m_s_fmt_mplane,
1313 .vidioc_reqbufs = fimc_m2m_reqbufs,
1314 .vidioc_querybuf = fimc_m2m_querybuf,
1316 .vidioc_qbuf = fimc_m2m_qbuf,
1317 .vidioc_dqbuf = fimc_m2m_dqbuf,
1319 .vidioc_streamon = fimc_m2m_streamon,
1320 .vidioc_streamoff = fimc_m2m_streamoff,
1322 .vidioc_g_crop = fimc_m2m_g_crop,
1323 .vidioc_s_crop = fimc_m2m_s_crop,
1324 .vidioc_cropcap = fimc_m2m_cropcap
1328 static int queue_init(void *priv, struct vb2_queue *src_vq,
1329 struct vb2_queue *dst_vq)
1331 struct fimc_ctx *ctx = priv;
1334 memset(src_vq, 0, sizeof(*src_vq));
1335 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1336 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1337 src_vq->drv_priv = ctx;
1338 src_vq->ops = &fimc_qops;
1339 src_vq->mem_ops = &vb2_dma_contig_memops;
1340 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1342 ret = vb2_queue_init(src_vq);
1346 memset(dst_vq, 0, sizeof(*dst_vq));
1347 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1348 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1349 dst_vq->drv_priv = ctx;
1350 dst_vq->ops = &fimc_qops;
1351 dst_vq->mem_ops = &vb2_dma_contig_memops;
1352 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1354 return vb2_queue_init(dst_vq);
1357 static int fimc_m2m_open(struct file *file)
1359 struct fimc_dev *fimc = video_drvdata(file);
1360 struct fimc_ctx *ctx;
1363 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1364 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1367 * Return if the corresponding video capture node
1368 * is already opened.
1370 if (fimc->vid_cap.refcnt > 0)
1373 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1376 v4l2_fh_init(&ctx->fh, fimc->m2m.vfd);
1377 ret = fimc_ctrls_create(ctx);
1381 /* Use separate control handler per file handle */
1382 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
1383 file->private_data = &ctx->fh;
1384 v4l2_fh_add(&ctx->fh);
1386 ctx->fimc_dev = fimc;
1387 /* Default color format */
1388 ctx->s_frame.fmt = &fimc_formats[0];
1389 ctx->d_frame.fmt = &fimc_formats[0];
1390 /* Setup the device context for memory-to-memory mode */
1391 ctx->state = FIMC_CTX_M2M;
1393 ctx->in_path = FIMC_DMA;
1394 ctx->out_path = FIMC_DMA;
1395 spin_lock_init(&ctx->slock);
1397 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1398 if (IS_ERR(ctx->m2m_ctx)) {
1399 ret = PTR_ERR(ctx->m2m_ctx);
1403 if (fimc->m2m.refcnt++ == 0)
1404 set_bit(ST_M2M_RUN, &fimc->state);
1408 fimc_ctrls_delete(ctx);
1410 v4l2_fh_del(&ctx->fh);
1411 v4l2_fh_exit(&ctx->fh);
1416 static int fimc_m2m_release(struct file *file)
1418 struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1419 struct fimc_dev *fimc = ctx->fimc_dev;
1421 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1422 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1424 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1425 fimc_ctrls_delete(ctx);
1426 v4l2_fh_del(&ctx->fh);
1427 v4l2_fh_exit(&ctx->fh);
1429 if (--fimc->m2m.refcnt <= 0)
1430 clear_bit(ST_M2M_RUN, &fimc->state);
1435 static unsigned int fimc_m2m_poll(struct file *file,
1436 struct poll_table_struct *wait)
1438 struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1440 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1444 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1446 struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1448 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1451 static const struct v4l2_file_operations fimc_m2m_fops = {
1452 .owner = THIS_MODULE,
1453 .open = fimc_m2m_open,
1454 .release = fimc_m2m_release,
1455 .poll = fimc_m2m_poll,
1456 .unlocked_ioctl = video_ioctl2,
1457 .mmap = fimc_m2m_mmap,
1460 static struct v4l2_m2m_ops m2m_ops = {
1461 .device_run = fimc_dma_run,
1462 .job_abort = fimc_job_abort,
1465 int fimc_register_m2m_device(struct fimc_dev *fimc,
1466 struct v4l2_device *v4l2_dev)
1468 struct video_device *vfd;
1469 struct platform_device *pdev;
1476 fimc->v4l2_dev = v4l2_dev;
1478 vfd = video_device_alloc();
1480 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1484 vfd->fops = &fimc_m2m_fops;
1485 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1486 vfd->v4l2_dev = v4l2_dev;
1488 vfd->release = video_device_release;
1489 vfd->lock = &fimc->lock;
1491 snprintf(vfd->name, sizeof(vfd->name), "%s.m2m", dev_name(&pdev->dev));
1492 video_set_drvdata(vfd, fimc);
1494 fimc->m2m.vfd = vfd;
1495 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1496 if (IS_ERR(fimc->m2m.m2m_dev)) {
1497 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1498 ret = PTR_ERR(fimc->m2m.m2m_dev);
1502 ret = media_entity_init(&vfd->entity, 0, NULL, 0);
1506 v4l2_m2m_release(fimc->m2m.m2m_dev);
1508 video_device_release(fimc->m2m.vfd);
1512 void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1517 if (fimc->m2m.m2m_dev)
1518 v4l2_m2m_release(fimc->m2m.m2m_dev);
1519 if (fimc->m2m.vfd) {
1520 media_entity_cleanup(&fimc->m2m.vfd->entity);
1521 /* Can also be called if video device wasn't registered */
1522 video_unregister_device(fimc->m2m.vfd);
1526 static void fimc_clk_put(struct fimc_dev *fimc)
1529 for (i = 0; i < fimc->num_clocks; i++) {
1531 clk_put(fimc->clock[i]);
1535 static int fimc_clk_get(struct fimc_dev *fimc)
1538 for (i = 0; i < fimc->num_clocks; i++) {
1539 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1540 if (!IS_ERR_OR_NULL(fimc->clock[i]))
1542 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1550 static int fimc_m2m_suspend(struct fimc_dev *fimc)
1552 unsigned long flags;
1555 spin_lock_irqsave(&fimc->slock, flags);
1556 if (!fimc_m2m_pending(fimc)) {
1557 spin_unlock_irqrestore(&fimc->slock, flags);
1560 clear_bit(ST_M2M_SUSPENDED, &fimc->state);
1561 set_bit(ST_M2M_SUSPENDING, &fimc->state);
1562 spin_unlock_irqrestore(&fimc->slock, flags);
1564 timeout = wait_event_timeout(fimc->irq_queue,
1565 test_bit(ST_M2M_SUSPENDED, &fimc->state),
1566 FIMC_SHUTDOWN_TIMEOUT);
1568 clear_bit(ST_M2M_SUSPENDING, &fimc->state);
1569 return timeout == 0 ? -EAGAIN : 0;
1572 static int fimc_m2m_resume(struct fimc_dev *fimc)
1574 unsigned long flags;
1576 spin_lock_irqsave(&fimc->slock, flags);
1577 /* Clear for full H/W setup in first run after resume */
1578 fimc->m2m.ctx = NULL;
1579 spin_unlock_irqrestore(&fimc->slock, flags);
1581 if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
1582 fimc_m2m_job_finish(fimc->m2m.ctx,
1583 VB2_BUF_STATE_ERROR);
1587 static int fimc_probe(struct platform_device *pdev)
1589 struct fimc_dev *fimc;
1590 struct resource *res;
1591 struct samsung_fimc_driverdata *drv_data;
1592 struct s5p_platform_fimc *pdata;
1595 dev_dbg(&pdev->dev, "%s():\n", __func__);
1597 drv_data = (struct samsung_fimc_driverdata *)
1598 platform_get_device_id(pdev)->driver_data;
1600 if (pdev->id >= drv_data->num_entities) {
1601 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1606 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1610 fimc->id = pdev->id;
1612 fimc->variant = drv_data->variant[fimc->id];
1614 pdata = pdev->dev.platform_data;
1615 fimc->pdata = pdata;
1618 init_waitqueue_head(&fimc->irq_queue);
1619 spin_lock_init(&fimc->slock);
1620 mutex_init(&fimc->lock);
1622 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1624 dev_err(&pdev->dev, "failed to find the registers\n");
1629 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1630 dev_name(&pdev->dev));
1631 if (!fimc->regs_res) {
1632 dev_err(&pdev->dev, "failed to obtain register region\n");
1637 fimc->regs = ioremap(res->start, resource_size(res));
1639 dev_err(&pdev->dev, "failed to map registers\n");
1641 goto err_req_region;
1644 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1646 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1648 goto err_regs_unmap;
1650 fimc->irq = res->start;
1652 fimc->num_clocks = MAX_FIMC_CLOCKS;
1653 ret = fimc_clk_get(fimc);
1655 goto err_regs_unmap;
1656 clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1657 clk_enable(fimc->clock[CLK_BUS]);
1659 platform_set_drvdata(pdev, fimc);
1661 ret = request_irq(fimc->irq, fimc_irq_handler, 0, pdev->name, fimc);
1663 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1667 pm_runtime_enable(&pdev->dev);
1668 ret = pm_runtime_get_sync(&pdev->dev);
1671 /* Initialize contiguous memory allocator */
1672 fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1673 if (IS_ERR(fimc->alloc_ctx)) {
1674 ret = PTR_ERR(fimc->alloc_ctx);
1678 dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id);
1680 pm_runtime_put(&pdev->dev);
1684 pm_runtime_put(&pdev->dev);
1686 free_irq(fimc->irq, fimc);
1690 iounmap(fimc->regs);
1692 release_resource(fimc->regs_res);
1693 kfree(fimc->regs_res);
1699 static int fimc_runtime_resume(struct device *dev)
1701 struct fimc_dev *fimc = dev_get_drvdata(dev);
1703 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1705 /* Enable clocks and perform basic initalization */
1706 clk_enable(fimc->clock[CLK_GATE]);
1707 fimc_hw_reset(fimc);
1709 /* Resume the capture or mem-to-mem device */
1710 if (fimc_capture_busy(fimc))
1711 return fimc_capture_resume(fimc);
1712 else if (fimc_m2m_pending(fimc))
1713 return fimc_m2m_resume(fimc);
1717 static int fimc_runtime_suspend(struct device *dev)
1719 struct fimc_dev *fimc = dev_get_drvdata(dev);
1722 if (fimc_capture_busy(fimc))
1723 ret = fimc_capture_suspend(fimc);
1725 ret = fimc_m2m_suspend(fimc);
1727 clk_disable(fimc->clock[CLK_GATE]);
1729 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1733 #ifdef CONFIG_PM_SLEEP
1734 static int fimc_resume(struct device *dev)
1736 struct fimc_dev *fimc = dev_get_drvdata(dev);
1737 unsigned long flags;
1739 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1741 /* Do not resume if the device was idle before system suspend */
1742 spin_lock_irqsave(&fimc->slock, flags);
1743 if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1744 (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1745 spin_unlock_irqrestore(&fimc->slock, flags);
1748 fimc_hw_reset(fimc);
1749 spin_unlock_irqrestore(&fimc->slock, flags);
1751 if (fimc_capture_busy(fimc))
1752 return fimc_capture_resume(fimc);
1754 return fimc_m2m_resume(fimc);
1757 static int fimc_suspend(struct device *dev)
1759 struct fimc_dev *fimc = dev_get_drvdata(dev);
1761 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1763 if (test_and_set_bit(ST_LPM, &fimc->state))
1765 if (fimc_capture_busy(fimc))
1766 return fimc_capture_suspend(fimc);
1768 return fimc_m2m_suspend(fimc);
1770 #endif /* CONFIG_PM_SLEEP */
1772 static int __devexit fimc_remove(struct platform_device *pdev)
1774 struct fimc_dev *fimc = platform_get_drvdata(pdev);
1776 pm_runtime_disable(&pdev->dev);
1777 pm_runtime_set_suspended(&pdev->dev);
1779 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1781 clk_disable(fimc->clock[CLK_BUS]);
1783 free_irq(fimc->irq, fimc);
1784 iounmap(fimc->regs);
1785 release_resource(fimc->regs_res);
1786 kfree(fimc->regs_res);
1789 dev_info(&pdev->dev, "driver unloaded\n");
1793 /* Image pixel limits, similar across several FIMC HW revisions. */
1794 static struct fimc_pix_limit s5p_pix_limit[4] = {
1796 .scaler_en_w = 3264,
1797 .scaler_dis_w = 8192,
1798 .in_rot_en_h = 1920,
1799 .in_rot_dis_w = 8192,
1800 .out_rot_en_w = 1920,
1801 .out_rot_dis_w = 4224,
1804 .scaler_en_w = 4224,
1805 .scaler_dis_w = 8192,
1806 .in_rot_en_h = 1920,
1807 .in_rot_dis_w = 8192,
1808 .out_rot_en_w = 1920,
1809 .out_rot_dis_w = 4224,
1812 .scaler_en_w = 1920,
1813 .scaler_dis_w = 8192,
1814 .in_rot_en_h = 1280,
1815 .in_rot_dis_w = 8192,
1816 .out_rot_en_w = 1280,
1817 .out_rot_dis_w = 1920,
1820 .scaler_en_w = 1920,
1821 .scaler_dis_w = 8192,
1822 .in_rot_en_h = 1366,
1823 .in_rot_dis_w = 8192,
1824 .out_rot_en_w = 1366,
1825 .out_rot_dis_w = 1920,
1829 static struct samsung_fimc_variant fimc0_variant_s5p = {
1833 .min_inp_pixsize = 16,
1834 .min_out_pixsize = 16,
1835 .hor_offs_align = 8,
1836 .min_vsize_align = 16,
1838 .pix_limit = &s5p_pix_limit[0],
1841 static struct samsung_fimc_variant fimc2_variant_s5p = {
1843 .min_inp_pixsize = 16,
1844 .min_out_pixsize = 16,
1845 .hor_offs_align = 8,
1846 .min_vsize_align = 16,
1848 .pix_limit = &s5p_pix_limit[1],
1851 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1856 .min_inp_pixsize = 16,
1857 .min_out_pixsize = 16,
1858 .hor_offs_align = 8,
1859 .min_vsize_align = 16,
1861 .pix_limit = &s5p_pix_limit[1],
1864 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1869 .has_mainscaler_ext = 1,
1870 .min_inp_pixsize = 16,
1871 .min_out_pixsize = 16,
1872 .hor_offs_align = 1,
1873 .min_vsize_align = 1,
1875 .pix_limit = &s5p_pix_limit[2],
1878 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1881 .min_inp_pixsize = 16,
1882 .min_out_pixsize = 16,
1883 .hor_offs_align = 8,
1884 .min_vsize_align = 16,
1886 .pix_limit = &s5p_pix_limit[2],
1889 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1895 .has_mainscaler_ext = 1,
1896 .min_inp_pixsize = 16,
1897 .min_out_pixsize = 16,
1898 .hor_offs_align = 2,
1899 .min_vsize_align = 1,
1900 .out_buf_count = 32,
1901 .pix_limit = &s5p_pix_limit[1],
1904 static struct samsung_fimc_variant fimc3_variant_exynos4 = {
1908 .has_mainscaler_ext = 1,
1909 .min_inp_pixsize = 16,
1910 .min_out_pixsize = 16,
1911 .hor_offs_align = 2,
1912 .min_vsize_align = 1,
1913 .out_buf_count = 32,
1914 .pix_limit = &s5p_pix_limit[3],
1918 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1920 [0] = &fimc0_variant_s5p,
1921 [1] = &fimc0_variant_s5p,
1922 [2] = &fimc2_variant_s5p,
1925 .lclk_frequency = 133000000UL,
1928 /* S5PV210, S5PC110 */
1929 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1931 [0] = &fimc0_variant_s5pv210,
1932 [1] = &fimc1_variant_s5pv210,
1933 [2] = &fimc2_variant_s5pv210,
1936 .lclk_frequency = 166000000UL,
1939 /* S5PV310, S5PC210 */
1940 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1942 [0] = &fimc0_variant_exynos4,
1943 [1] = &fimc0_variant_exynos4,
1944 [2] = &fimc0_variant_exynos4,
1945 [3] = &fimc3_variant_exynos4,
1948 .lclk_frequency = 166000000UL,
1951 static struct platform_device_id fimc_driver_ids[] = {
1954 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1956 .name = "s5pv210-fimc",
1957 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
1959 .name = "exynos4-fimc",
1960 .driver_data = (unsigned long)&fimc_drvdata_exynos4,
1964 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1966 static const struct dev_pm_ops fimc_pm_ops = {
1967 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1968 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1971 static struct platform_driver fimc_driver = {
1972 .probe = fimc_probe,
1973 .remove = __devexit_p(fimc_remove),
1974 .id_table = fimc_driver_ids,
1976 .name = FIMC_MODULE_NAME,
1977 .owner = THIS_MODULE,
1982 int __init fimc_register_driver(void)
1984 return platform_driver_probe(&fimc_driver, fimc_probe);
1987 void __exit fimc_unregister_driver(void)
1989 platform_driver_unregister(&fimc_driver);