2 * OmniVision OV96xx Camera Driver
4 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
6 * Based on ov772x camera driver:
8 * Copyright (C) 2008 Renesas Solutions Corp.
9 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
11 * Based on ov7670 and soc_camera_platform driver,
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
14 * Copyright (C) 2008 Magnus Damm
15 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/videodev2.h>
29 #include <media/soc_camera.h>
30 #include <media/soc_mediabus.h>
31 #include <media/v4l2-chip-ident.h>
32 #include <media/v4l2-common.h>
36 #define to_ov9640_sensor(sd) container_of(sd, struct ov9640_priv, subdev)
38 /* default register setup */
39 static const struct ov9640_reg ov9640_regs_dflt[] = {
40 { OV9640_COM5, OV9640_COM5_SYSCLK | OV9640_COM5_LONGEXP },
41 { OV9640_COM6, OV9640_COM6_OPT_BLC | OV9640_COM6_ADBLC_BIAS |
42 OV9640_COM6_FMT_RST | OV9640_COM6_ADBLC_OPTEN },
43 { OV9640_PSHFT, OV9640_PSHFT_VAL(0x01) },
44 { OV9640_ACOM, OV9640_ACOM_2X_ANALOG | OV9640_ACOM_RSVD },
45 { OV9640_TSLB, OV9640_TSLB_YUYV_UYVY },
46 { OV9640_COM16, OV9640_COM16_RB_AVG },
49 { 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 },
50 { 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 },
51 { 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 },
52 { 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 },
55 { 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 },
56 { 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 },
57 { 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e },
58 { 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 },
62 * NOTE: for YUV, alter the following registers:
63 * COM12 |= OV9640_COM12_YUV_AVG
65 * for RGB, alter the following registers:
66 * COM7 |= OV9640_COM7_RGB
67 * COM13 |= OV9640_COM13_RGB_AVG
68 * COM15 |= proper RGB color encoding mode
70 static const struct ov9640_reg ov9640_regs_qqcif[] = {
71 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) },
72 { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
73 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
74 { OV9640_COM7, OV9640_COM7_QCIF },
75 { OV9640_COM12, OV9640_COM12_RSVD },
76 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
77 { OV9640_COM15, OV9640_COM15_OR_10F0 },
80 static const struct ov9640_reg ov9640_regs_qqvga[] = {
81 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
82 { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
83 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
84 { OV9640_COM7, OV9640_COM7_QVGA },
85 { OV9640_COM12, OV9640_COM12_RSVD },
86 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
87 { OV9640_COM15, OV9640_COM15_OR_10F0 },
90 static const struct ov9640_reg ov9640_regs_qcif[] = {
91 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
92 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
93 { OV9640_COM7, OV9640_COM7_QCIF },
94 { OV9640_COM12, OV9640_COM12_RSVD },
95 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
96 { OV9640_COM15, OV9640_COM15_OR_10F0 },
99 static const struct ov9640_reg ov9640_regs_qvga[] = {
100 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
101 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
102 { OV9640_COM7, OV9640_COM7_QVGA },
103 { OV9640_COM12, OV9640_COM12_RSVD },
104 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
105 { OV9640_COM15, OV9640_COM15_OR_10F0 },
108 static const struct ov9640_reg ov9640_regs_cif[] = {
109 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
110 { OV9640_COM3, OV9640_COM3_VP },
111 { OV9640_COM7, OV9640_COM7_CIF },
112 { OV9640_COM12, OV9640_COM12_RSVD },
113 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
114 { OV9640_COM15, OV9640_COM15_OR_10F0 },
117 static const struct ov9640_reg ov9640_regs_vga[] = {
118 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
119 { OV9640_COM3, OV9640_COM3_VP },
120 { OV9640_COM7, OV9640_COM7_VGA },
121 { OV9640_COM12, OV9640_COM12_RSVD },
122 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
123 { OV9640_COM15, OV9640_COM15_OR_10F0 },
126 static const struct ov9640_reg ov9640_regs_sxga[] = {
127 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
128 { OV9640_COM3, OV9640_COM3_VP },
130 { OV9640_COM12, OV9640_COM12_RSVD },
131 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
132 { OV9640_COM15, OV9640_COM15_OR_10F0 },
135 static const struct ov9640_reg ov9640_regs_yuv[] = {
136 { OV9640_MTX1, 0x58 },
137 { OV9640_MTX2, 0x48 },
138 { OV9640_MTX3, 0x10 },
139 { OV9640_MTX4, 0x28 },
140 { OV9640_MTX5, 0x48 },
141 { OV9640_MTX6, 0x70 },
142 { OV9640_MTX7, 0x40 },
143 { OV9640_MTX8, 0x40 },
144 { OV9640_MTX9, 0x40 },
145 { OV9640_MTXS, 0x0f },
148 static const struct ov9640_reg ov9640_regs_rgb[] = {
149 { OV9640_MTX1, 0x71 },
150 { OV9640_MTX2, 0x3e },
151 { OV9640_MTX3, 0x0c },
152 { OV9640_MTX4, 0x33 },
153 { OV9640_MTX5, 0x72 },
154 { OV9640_MTX6, 0x00 },
155 { OV9640_MTX7, 0x2b },
156 { OV9640_MTX8, 0x66 },
157 { OV9640_MTX9, 0xd2 },
158 { OV9640_MTXS, 0x65 },
161 static enum v4l2_mbus_pixelcode ov9640_codes[] = {
162 V4L2_MBUS_FMT_UYVY8_2X8,
163 V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
164 V4L2_MBUS_FMT_RGB565_2X8_LE,
167 static const struct v4l2_queryctrl ov9640_controls[] = {
169 .id = V4L2_CID_VFLIP,
170 .type = V4L2_CTRL_TYPE_BOOLEAN,
171 .name = "Flip Vertically",
178 .id = V4L2_CID_HFLIP,
179 .type = V4L2_CTRL_TYPE_BOOLEAN,
180 .name = "Flip Horizontally",
188 /* read a register */
189 static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val)
193 struct i2c_msg msg = {
194 .addr = client->addr,
200 ret = i2c_transfer(client->adapter, &msg, 1);
204 msg.flags = I2C_M_RD;
205 ret = i2c_transfer(client->adapter, &msg, 1);
213 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
217 /* write a register */
218 static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val)
222 unsigned char data[2] = { reg, val };
223 struct i2c_msg msg = {
224 .addr = client->addr,
230 ret = i2c_transfer(client->adapter, &msg, 1);
232 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
236 /* we have to read the register back ... no idea why, maybe HW bug */
237 ret = ov9640_reg_read(client, reg, &_val);
239 dev_err(&client->dev,
240 "Failed reading back register 0x%02x!\n", reg);
246 /* Read a register, alter its bits, write it back */
247 static int ov9640_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset)
252 ret = ov9640_reg_read(client, reg, &val);
254 dev_err(&client->dev,
255 "[Read]-Modify-Write of register %02x failed!\n", reg);
262 ret = ov9640_reg_write(client, reg, val);
264 dev_err(&client->dev,
265 "Read-Modify-[Write] of register %02x failed!\n", reg);
270 /* Soft reset the camera. This has nothing to do with the RESET pin! */
271 static int ov9640_reset(struct i2c_client *client)
275 ret = ov9640_reg_write(client, OV9640_COM7, OV9640_COM7_SCCB_RESET);
277 dev_err(&client->dev,
278 "An error occurred while entering soft reset!\n");
283 /* Start/Stop streaming from the device */
284 static int ov9640_s_stream(struct v4l2_subdev *sd, int enable)
289 /* Get status of additional camera capabilities */
290 static int ov9640_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
292 struct ov9640_priv *priv = to_ov9640_sensor(sd);
296 ctrl->value = priv->flag_vflip;
299 ctrl->value = priv->flag_hflip;
305 /* Set status of additional camera capabilities */
306 static int ov9640_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
308 struct i2c_client *client = v4l2_get_subdevdata(sd);
309 struct ov9640_priv *priv = to_ov9640_sensor(sd);
315 priv->flag_vflip = ctrl->value;
317 ret = ov9640_reg_rmw(client, OV9640_MVFP,
320 ret = ov9640_reg_rmw(client, OV9640_MVFP,
324 priv->flag_hflip = ctrl->value;
326 ret = ov9640_reg_rmw(client, OV9640_MVFP,
329 ret = ov9640_reg_rmw(client, OV9640_MVFP,
337 /* Get chip identification */
338 static int ov9640_g_chip_ident(struct v4l2_subdev *sd,
339 struct v4l2_dbg_chip_ident *id)
341 struct ov9640_priv *priv = to_ov9640_sensor(sd);
343 id->ident = priv->model;
344 id->revision = priv->revision;
349 #ifdef CONFIG_VIDEO_ADV_DEBUG
350 static int ov9640_get_register(struct v4l2_subdev *sd,
351 struct v4l2_dbg_register *reg)
353 struct i2c_client *client = v4l2_get_subdevdata(sd);
357 if (reg->reg & ~0xff)
362 ret = ov9640_reg_read(client, reg->reg, &val);
366 reg->val = (__u64)val;
371 static int ov9640_set_register(struct v4l2_subdev *sd,
372 struct v4l2_dbg_register *reg)
374 struct i2c_client *client = v4l2_get_subdevdata(sd);
376 if (reg->reg & ~0xff || reg->val & ~0xff)
379 return ov9640_reg_write(client, reg->reg, reg->val);
383 /* select nearest higher resolution for capture */
384 static void ov9640_res_roundup(u32 *width, u32 *height)
387 enum { QQCIF, QQVGA, QCIF, QVGA, CIF, VGA, SXGA };
388 int res_x[] = { 88, 160, 176, 320, 352, 640, 1280 };
389 int res_y[] = { 72, 120, 144, 240, 288, 480, 960 };
391 for (i = 0; i < ARRAY_SIZE(res_x); i++) {
392 if (res_x[i] >= *width && res_y[i] >= *height) {
399 *width = res_x[SXGA];
400 *height = res_y[SXGA];
403 /* Prepare necessary register changes depending on color encoding */
404 static void ov9640_alter_regs(enum v4l2_mbus_pixelcode code,
405 struct ov9640_reg_alt *alt)
409 case V4L2_MBUS_FMT_UYVY8_2X8:
410 alt->com12 = OV9640_COM12_YUV_AVG;
411 alt->com13 = OV9640_COM13_Y_DELAY_EN |
412 OV9640_COM13_YUV_DLY(0x01);
414 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
415 alt->com7 = OV9640_COM7_RGB;
416 alt->com13 = OV9640_COM13_RGB_AVG;
417 alt->com15 = OV9640_COM15_RGB_555;
419 case V4L2_MBUS_FMT_RGB565_2X8_LE:
420 alt->com7 = OV9640_COM7_RGB;
421 alt->com13 = OV9640_COM13_RGB_AVG;
422 alt->com15 = OV9640_COM15_RGB_565;
427 /* Setup registers according to resolution and color encoding */
428 static int ov9640_write_regs(struct i2c_client *client, u32 width,
429 enum v4l2_mbus_pixelcode code, struct ov9640_reg_alt *alts)
431 const struct ov9640_reg *ov9640_regs, *matrix_regs;
432 int ov9640_regs_len, matrix_regs_len;
436 /* select register configuration for given resolution */
439 ov9640_regs = ov9640_regs_qqcif;
440 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqcif);
443 ov9640_regs = ov9640_regs_qqvga;
444 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqvga);
447 ov9640_regs = ov9640_regs_qcif;
448 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qcif);
451 ov9640_regs = ov9640_regs_qvga;
452 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qvga);
455 ov9640_regs = ov9640_regs_cif;
456 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_cif);
459 ov9640_regs = ov9640_regs_vga;
460 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_vga);
463 ov9640_regs = ov9640_regs_sxga;
464 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_sxga);
467 dev_err(&client->dev, "Failed to select resolution!\n");
471 /* select color matrix configuration for given color encoding */
472 if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
473 matrix_regs = ov9640_regs_yuv;
474 matrix_regs_len = ARRAY_SIZE(ov9640_regs_yuv);
476 matrix_regs = ov9640_regs_rgb;
477 matrix_regs_len = ARRAY_SIZE(ov9640_regs_rgb);
480 /* write register settings into the module */
481 for (i = 0; i < ov9640_regs_len; i++) {
482 val = ov9640_regs[i].val;
484 switch (ov9640_regs[i].reg) {
499 ret = ov9640_reg_write(client, ov9640_regs[i].reg, val);
504 /* write color matrix configuration into the module */
505 for (i = 0; i < matrix_regs_len; i++) {
506 ret = ov9640_reg_write(client, matrix_regs[i].reg,
515 /* program default register values */
516 static int ov9640_prog_dflt(struct i2c_client *client)
520 for (i = 0; i < ARRAY_SIZE(ov9640_regs_dflt); i++) {
521 ret = ov9640_reg_write(client, ov9640_regs_dflt[i].reg,
522 ov9640_regs_dflt[i].val);
527 /* wait for the changes to actually happen, 140ms are not enough yet */
533 /* set the format we will capture in */
534 static int ov9640_s_fmt(struct v4l2_subdev *sd,
535 struct v4l2_mbus_framefmt *mf)
537 struct i2c_client *client = v4l2_get_subdevdata(sd);
538 struct ov9640_reg_alt alts = {0};
539 enum v4l2_colorspace cspace;
540 enum v4l2_mbus_pixelcode code = mf->code;
543 ov9640_res_roundup(&mf->width, &mf->height);
544 ov9640_alter_regs(mf->code, &alts);
546 ov9640_reset(client);
548 ret = ov9640_prog_dflt(client);
553 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
554 case V4L2_MBUS_FMT_RGB565_2X8_LE:
555 cspace = V4L2_COLORSPACE_SRGB;
558 code = V4L2_MBUS_FMT_UYVY8_2X8;
559 case V4L2_MBUS_FMT_UYVY8_2X8:
560 cspace = V4L2_COLORSPACE_JPEG;
563 ret = ov9640_write_regs(client, mf->width, code, &alts);
566 mf->colorspace = cspace;
572 static int ov9640_try_fmt(struct v4l2_subdev *sd,
573 struct v4l2_mbus_framefmt *mf)
575 ov9640_res_roundup(&mf->width, &mf->height);
577 mf->field = V4L2_FIELD_NONE;
580 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
581 case V4L2_MBUS_FMT_RGB565_2X8_LE:
582 mf->colorspace = V4L2_COLORSPACE_SRGB;
585 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
586 case V4L2_MBUS_FMT_UYVY8_2X8:
587 mf->colorspace = V4L2_COLORSPACE_JPEG;
593 static int ov9640_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
594 enum v4l2_mbus_pixelcode *code)
596 if (index >= ARRAY_SIZE(ov9640_codes))
599 *code = ov9640_codes[index];
603 static int ov9640_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
608 a->c.height = H_SXGA;
609 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
614 static int ov9640_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
618 a->bounds.width = W_SXGA;
619 a->bounds.height = H_SXGA;
620 a->defrect = a->bounds;
621 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
622 a->pixelaspect.numerator = 1;
623 a->pixelaspect.denominator = 1;
628 static int ov9640_video_probe(struct soc_camera_device *icd,
629 struct i2c_client *client)
631 struct v4l2_subdev *sd = i2c_get_clientdata(client);
632 struct ov9640_priv *priv = to_ov9640_sensor(sd);
633 u8 pid, ver, midh, midl;
637 /* We must have a parent by now. And it cannot be a wrong one. */
638 BUG_ON(!icd->parent ||
639 to_soc_camera_host(icd->parent)->nr != icd->iface);
642 * check and show product ID and manufacturer ID
645 ret = ov9640_reg_read(client, OV9640_PID, &pid);
649 ret = ov9640_reg_read(client, OV9640_VER, &ver);
653 ret = ov9640_reg_read(client, OV9640_MIDH, &midh);
657 ret = ov9640_reg_read(client, OV9640_MIDL, &midl);
661 switch (VERSION(pid, ver)) {
664 priv->model = V4L2_IDENT_OV9640;
668 priv->model = V4L2_IDENT_OV9640;
672 dev_err(&client->dev, "Product ID error %x:%x\n", pid, ver);
677 dev_info(&client->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
678 devname, pid, ver, midh, midl);
684 static struct soc_camera_ops ov9640_ops = {
685 .controls = ov9640_controls,
686 .num_controls = ARRAY_SIZE(ov9640_controls),
689 static struct v4l2_subdev_core_ops ov9640_core_ops = {
690 .g_ctrl = ov9640_g_ctrl,
691 .s_ctrl = ov9640_s_ctrl,
692 .g_chip_ident = ov9640_g_chip_ident,
693 #ifdef CONFIG_VIDEO_ADV_DEBUG
694 .g_register = ov9640_get_register,
695 .s_register = ov9640_set_register,
700 /* Request bus settings on camera side */
701 static int ov9640_g_mbus_config(struct v4l2_subdev *sd,
702 struct v4l2_mbus_config *cfg)
704 struct i2c_client *client = v4l2_get_subdevdata(sd);
705 struct soc_camera_device *icd = client->dev.platform_data;
706 struct soc_camera_link *icl = to_soc_camera_link(icd);
708 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
709 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
710 V4L2_MBUS_DATA_ACTIVE_HIGH;
711 cfg->type = V4L2_MBUS_PARALLEL;
712 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
717 static struct v4l2_subdev_video_ops ov9640_video_ops = {
718 .s_stream = ov9640_s_stream,
719 .s_mbus_fmt = ov9640_s_fmt,
720 .try_mbus_fmt = ov9640_try_fmt,
721 .enum_mbus_fmt = ov9640_enum_fmt,
722 .cropcap = ov9640_cropcap,
723 .g_crop = ov9640_g_crop,
724 .g_mbus_config = ov9640_g_mbus_config,
727 static struct v4l2_subdev_ops ov9640_subdev_ops = {
728 .core = &ov9640_core_ops,
729 .video = &ov9640_video_ops,
733 * i2c_driver function
735 static int ov9640_probe(struct i2c_client *client,
736 const struct i2c_device_id *did)
738 struct ov9640_priv *priv;
739 struct soc_camera_device *icd = client->dev.platform_data;
740 struct soc_camera_link *icl;
744 dev_err(&client->dev, "Missing soc-camera data!\n");
748 icl = to_soc_camera_link(icd);
750 dev_err(&client->dev, "Missing platform_data for driver\n");
754 priv = kzalloc(sizeof(struct ov9640_priv), GFP_KERNEL);
756 dev_err(&client->dev,
757 "Failed to allocate memory for private data!\n");
761 v4l2_i2c_subdev_init(&priv->subdev, client, &ov9640_subdev_ops);
763 icd->ops = &ov9640_ops;
765 ret = ov9640_video_probe(icd, client);
775 static int ov9640_remove(struct i2c_client *client)
777 struct v4l2_subdev *sd = i2c_get_clientdata(client);
778 struct ov9640_priv *priv = to_ov9640_sensor(sd);
784 static const struct i2c_device_id ov9640_id[] = {
788 MODULE_DEVICE_TABLE(i2c, ov9640_id);
790 static struct i2c_driver ov9640_i2c_driver = {
794 .probe = ov9640_probe,
795 .remove = ov9640_remove,
796 .id_table = ov9640_id,
799 static int __init ov9640_module_init(void)
801 return i2c_add_driver(&ov9640_i2c_driver);
804 static void __exit ov9640_module_exit(void)
806 i2c_del_driver(&ov9640_i2c_driver);
809 module_init(ov9640_module_init);
810 module_exit(ov9640_module_exit);
812 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV96xx");
813 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
814 MODULE_LICENSE("GPL v2");