4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 * Based on ov7670 and soc_camera_platform driver,
9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 * Copyright (C) 2008 Magnus Damm
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/videodev2.h>
25 #include <media/ov772x.h>
26 #include <media/soc_camera.h>
27 #include <media/soc_mediabus.h>
28 #include <media/v4l2-chip-ident.h>
29 #include <media/v4l2-subdev.h>
34 #define GAIN 0x00 /* AGC - Gain control gain setting */
35 #define BLUE 0x01 /* AWB - Blue channel gain setting */
36 #define RED 0x02 /* AWB - Red channel gain setting */
37 #define GREEN 0x03 /* AWB - Green channel gain setting */
38 #define COM1 0x04 /* Common control 1 */
39 #define BAVG 0x05 /* U/B Average Level */
40 #define GAVG 0x06 /* Y/Gb Average Level */
41 #define RAVG 0x07 /* V/R Average Level */
42 #define AECH 0x08 /* Exposure Value - AEC MSBs */
43 #define COM2 0x09 /* Common control 2 */
44 #define PID 0x0A /* Product ID Number MSB */
45 #define VER 0x0B /* Product ID Number LSB */
46 #define COM3 0x0C /* Common control 3 */
47 #define COM4 0x0D /* Common control 4 */
48 #define COM5 0x0E /* Common control 5 */
49 #define COM6 0x0F /* Common control 6 */
50 #define AEC 0x10 /* Exposure Value */
51 #define CLKRC 0x11 /* Internal clock */
52 #define COM7 0x12 /* Common control 7 */
53 #define COM8 0x13 /* Common control 8 */
54 #define COM9 0x14 /* Common control 9 */
55 #define COM10 0x15 /* Common control 10 */
56 #define REG16 0x16 /* Register 16 */
57 #define HSTART 0x17 /* Horizontal sensor size */
58 #define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */
59 #define VSTART 0x19 /* Vertical frame (row) start high 8-bit */
60 #define VSIZE 0x1A /* Vertical sensor size */
61 #define PSHFT 0x1B /* Data format - pixel delay select */
62 #define MIDH 0x1C /* Manufacturer ID byte - high */
63 #define MIDL 0x1D /* Manufacturer ID byte - low */
64 #define LAEC 0x1F /* Fine AEC value */
65 #define COM11 0x20 /* Common control 11 */
66 #define BDBASE 0x22 /* Banding filter Minimum AEC value */
67 #define DBSTEP 0x23 /* Banding filter Maximum Setp */
68 #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
69 #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
70 #define VPT 0x26 /* AGC/AEC Fast mode operating region */
71 #define REG28 0x28 /* Register 28 */
72 #define HOUTSIZE 0x29 /* Horizontal data output size MSBs */
73 #define EXHCH 0x2A /* Dummy pixel insert MSB */
74 #define EXHCL 0x2B /* Dummy pixel insert LSB */
75 #define VOUTSIZE 0x2C /* Vertical data output size MSBs */
76 #define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
77 #define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */
78 #define YAVE 0x2F /* Y/G Channel Average value */
79 #define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */
80 #define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */
81 #define HREF 0x32 /* Image start and size control */
82 #define DM_LNL 0x33 /* Dummy line low 8 bits */
83 #define DM_LNH 0x34 /* Dummy line high 8 bits */
84 #define ADOFF_B 0x35 /* AD offset compensation value for B channel */
85 #define ADOFF_R 0x36 /* AD offset compensation value for R channel */
86 #define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */
87 #define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */
88 #define OFF_B 0x39 /* Analog process B channel offset value */
89 #define OFF_R 0x3A /* Analog process R channel offset value */
90 #define OFF_GB 0x3B /* Analog process Gb channel offset value */
91 #define OFF_GR 0x3C /* Analog process Gr channel offset value */
92 #define COM12 0x3D /* Common control 12 */
93 #define COM13 0x3E /* Common control 13 */
94 #define COM14 0x3F /* Common control 14 */
95 #define COM15 0x40 /* Common control 15*/
96 #define COM16 0x41 /* Common control 16 */
97 #define TGT_B 0x42 /* BLC blue channel target value */
98 #define TGT_R 0x43 /* BLC red channel target value */
99 #define TGT_GB 0x44 /* BLC Gb channel target value */
100 #define TGT_GR 0x45 /* BLC Gr channel target value */
102 #define LCC0 0x46 /* Lens correction control 0 */
103 #define LCC1 0x47 /* Lens correction option 1 - X coordinate */
104 #define LCC2 0x48 /* Lens correction option 2 - Y coordinate */
105 #define LCC3 0x49 /* Lens correction option 3 */
106 #define LCC4 0x4A /* Lens correction option 4 - radius of the circular */
107 #define LCC5 0x4B /* Lens correction option 5 */
108 #define LCC6 0x4C /* Lens correction option 6 */
110 #define LC_CTR 0x46 /* Lens correction control */
111 #define LC_XC 0x47 /* X coordinate of lens correction center relative */
112 #define LC_YC 0x48 /* Y coordinate of lens correction center relative */
113 #define LC_COEF 0x49 /* Lens correction coefficient */
114 #define LC_RADI 0x4A /* Lens correction radius */
115 #define LC_COEFB 0x4B /* Lens B channel compensation coefficient */
116 #define LC_COEFR 0x4C /* Lens R channel compensation coefficient */
118 #define FIXGAIN 0x4D /* Analog fix gain amplifer */
119 #define AREF0 0x4E /* Sensor reference control */
120 #define AREF1 0x4F /* Sensor reference current control */
121 #define AREF2 0x50 /* Analog reference control */
122 #define AREF3 0x51 /* ADC reference control */
123 #define AREF4 0x52 /* ADC reference control */
124 #define AREF5 0x53 /* ADC reference control */
125 #define AREF6 0x54 /* Analog reference control */
126 #define AREF7 0x55 /* Analog reference control */
127 #define UFIX 0x60 /* U channel fixed value output */
128 #define VFIX 0x61 /* V channel fixed value output */
129 #define AWBB_BLK 0x62 /* AWB option for advanced AWB */
130 #define AWB_CTRL0 0x63 /* AWB control byte 0 */
131 #define DSP_CTRL1 0x64 /* DSP control byte 1 */
132 #define DSP_CTRL2 0x65 /* DSP control byte 2 */
133 #define DSP_CTRL3 0x66 /* DSP control byte 3 */
134 #define DSP_CTRL4 0x67 /* DSP control byte 4 */
135 #define AWB_BIAS 0x68 /* AWB BLC level clip */
136 #define AWB_CTRL1 0x69 /* AWB control 1 */
137 #define AWB_CTRL2 0x6A /* AWB control 2 */
138 #define AWB_CTRL3 0x6B /* AWB control 3 */
139 #define AWB_CTRL4 0x6C /* AWB control 4 */
140 #define AWB_CTRL5 0x6D /* AWB control 5 */
141 #define AWB_CTRL6 0x6E /* AWB control 6 */
142 #define AWB_CTRL7 0x6F /* AWB control 7 */
143 #define AWB_CTRL8 0x70 /* AWB control 8 */
144 #define AWB_CTRL9 0x71 /* AWB control 9 */
145 #define AWB_CTRL10 0x72 /* AWB control 10 */
146 #define AWB_CTRL11 0x73 /* AWB control 11 */
147 #define AWB_CTRL12 0x74 /* AWB control 12 */
148 #define AWB_CTRL13 0x75 /* AWB control 13 */
149 #define AWB_CTRL14 0x76 /* AWB control 14 */
150 #define AWB_CTRL15 0x77 /* AWB control 15 */
151 #define AWB_CTRL16 0x78 /* AWB control 16 */
152 #define AWB_CTRL17 0x79 /* AWB control 17 */
153 #define AWB_CTRL18 0x7A /* AWB control 18 */
154 #define AWB_CTRL19 0x7B /* AWB control 19 */
155 #define AWB_CTRL20 0x7C /* AWB control 20 */
156 #define AWB_CTRL21 0x7D /* AWB control 21 */
157 #define GAM1 0x7E /* Gamma Curve 1st segment input end point */
158 #define GAM2 0x7F /* Gamma Curve 2nd segment input end point */
159 #define GAM3 0x80 /* Gamma Curve 3rd segment input end point */
160 #define GAM4 0x81 /* Gamma Curve 4th segment input end point */
161 #define GAM5 0x82 /* Gamma Curve 5th segment input end point */
162 #define GAM6 0x83 /* Gamma Curve 6th segment input end point */
163 #define GAM7 0x84 /* Gamma Curve 7th segment input end point */
164 #define GAM8 0x85 /* Gamma Curve 8th segment input end point */
165 #define GAM9 0x86 /* Gamma Curve 9th segment input end point */
166 #define GAM10 0x87 /* Gamma Curve 10th segment input end point */
167 #define GAM11 0x88 /* Gamma Curve 11th segment input end point */
168 #define GAM12 0x89 /* Gamma Curve 12th segment input end point */
169 #define GAM13 0x8A /* Gamma Curve 13th segment input end point */
170 #define GAM14 0x8B /* Gamma Curve 14th segment input end point */
171 #define GAM15 0x8C /* Gamma Curve 15th segment input end point */
172 #define SLOP 0x8D /* Gamma curve highest segment slope */
173 #define DNSTH 0x8E /* De-noise threshold */
174 #define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */
175 #define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
176 #define DNSOFF 0x91 /* Auto De-noise threshold control */
177 #define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */
178 #define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */
179 #define MTX1 0x94 /* Matrix coefficient 1 */
180 #define MTX2 0x95 /* Matrix coefficient 2 */
181 #define MTX3 0x96 /* Matrix coefficient 3 */
182 #define MTX4 0x97 /* Matrix coefficient 4 */
183 #define MTX5 0x98 /* Matrix coefficient 5 */
184 #define MTX6 0x99 /* Matrix coefficient 6 */
185 #define MTX_CTRL 0x9A /* Matrix control */
186 #define BRIGHT 0x9B /* Brightness control */
187 #define CNTRST 0x9C /* Contrast contrast */
188 #define CNTRST_CTRL 0x9D /* Contrast contrast center */
189 #define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */
190 #define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */
191 #define SCAL0 0xA0 /* Scaling control 0 */
192 #define SCAL1 0xA1 /* Scaling control 1 */
193 #define SCAL2 0xA2 /* Scaling control 2 */
194 #define FIFODLYM 0xA3 /* FIFO manual mode delay control */
195 #define FIFODLYA 0xA4 /* FIFO auto mode delay control */
196 #define SDE 0xA6 /* Special digital effect control */
197 #define USAT 0xA7 /* U component saturation control */
198 #define VSAT 0xA8 /* V component saturation control */
200 #define HUE0 0xA9 /* Hue control 0 */
201 #define HUE1 0xAA /* Hue control 1 */
203 #define HUECOS 0xA9 /* Cosine value */
204 #define HUESIN 0xAA /* Sine value */
206 #define SIGN 0xAB /* Sign bit for Hue and contrast */
207 #define DSPAUTO 0xAC /* DSP auto function ON/OFF control */
214 #define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
215 /* Output drive capability */
216 #define OCAP_1x 0x00 /* 1x */
217 #define OCAP_2x 0x01 /* 2x */
218 #define OCAP_3x 0x02 /* 3x */
219 #define OCAP_4x 0x03 /* 4x */
222 #define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
223 #define IMG_MASK (VFLIP_IMG | HFLIP_IMG)
225 #define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */
226 #define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */
227 #define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */
228 #define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */
229 #define SWAP_ML 0x08 /* Swap output MSB/LSB */
230 /* Tri-state option for output clock */
231 #define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */
232 /* 1: No tri-state at this period */
233 /* Tri-state option for output data */
234 #define NOTRI_DATA 0x02 /* 0: Tri-state at this period */
235 /* 1: No tri-state at this period */
236 #define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */
239 /* PLL frequency control */
240 #define PLL_BYPASS 0x00 /* 00: Bypass PLL */
241 #define PLL_4x 0x40 /* 01: PLL 4x */
242 #define PLL_6x 0x80 /* 10: PLL 6x */
243 #define PLL_8x 0xc0 /* 11: PLL 8x */
244 /* AEC evaluate window */
245 #define AEC_FULL 0x00 /* 00: Full window */
246 #define AEC_1p2 0x10 /* 01: 1/2 window */
247 #define AEC_1p4 0x20 /* 10: 1/4 window */
248 #define AEC_2p3 0x30 /* 11: Low 2/3 window */
251 #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
252 #define AFR_SPPED 0x40 /* Auto frame rate control speed selection */
253 /* Auto frame rate max rate control */
254 #define AFR_NO_RATE 0x00 /* No reduction of frame rate */
255 #define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */
256 #define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */
257 #define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */
258 /* Auto frame rate active point control */
259 #define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */
260 #define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */
261 #define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */
262 #define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */
263 /* AEC max step control */
264 #define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */
265 /* 1 : No limit to AEC increase step */
268 /* SCCB Register Reset */
269 #define SCCB_RESET 0x80 /* 0 : No change */
270 /* 1 : Resets all registers to default */
271 /* Resolution selection */
272 #define SLCT_MASK 0x40 /* Mask of VGA or QVGA */
273 #define SLCT_VGA 0x00 /* 0 : VGA */
274 #define SLCT_QVGA 0x40 /* 1 : QVGA */
275 #define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */
276 /* RGB output format control */
277 #define FMT_MASK 0x0c /* Mask of color format */
278 #define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */
279 #define FMT_RGB565 0x04 /* 01 : RGB 565 */
280 #define FMT_RGB555 0x08 /* 10 : RGB 555 */
281 #define FMT_RGB444 0x0c /* 11 : RGB 444 */
282 /* Output format control */
283 #define OFMT_MASK 0x03 /* Mask of output format */
284 #define OFMT_YUV 0x00 /* 00 : YUV */
285 #define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */
286 #define OFMT_RGB 0x02 /* 10 : RGB */
287 #define OFMT_BRAW 0x03 /* 11 : Bayer RAW */
290 #define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */
291 /* AEC Setp size limit */
292 #define UNLMT_STEP 0x40 /* 0 : Step size is limited */
293 /* 1 : Unlimited step size */
294 #define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */
295 #define AEC_BND 0x10 /* Enable AEC below banding value */
296 #define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */
297 #define AGC_ON 0x04 /* AGC Enable */
298 #define AWB_ON 0x02 /* AWB Enable */
299 #define AEC_ON 0x01 /* AEC Enable */
302 #define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */
303 /* Automatic gain ceiling - maximum AGC value */
304 #define GAIN_2x 0x00 /* 000 : 2x */
305 #define GAIN_4x 0x10 /* 001 : 4x */
306 #define GAIN_8x 0x20 /* 010 : 8x */
307 #define GAIN_16x 0x30 /* 011 : 16x */
308 #define GAIN_32x 0x40 /* 100 : 32x */
309 #define GAIN_64x 0x50 /* 101 : 64x */
310 #define GAIN_128x 0x60 /* 110 : 128x */
311 #define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
312 #define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
315 #define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */
316 #define SGLF_TRIG 0x01 /* Single frame transfer trigger */
319 #define VSIZE_LSB 0x04 /* Vertical data output size LSB */
322 #define FIFO_ON 0x80 /* FIFO enable/disable selection */
323 #define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */
324 #define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */
325 #define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */
326 #define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */
327 #define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */
328 #define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */
329 #define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */
332 #define UV_MASK 0x80 /* UV output sequence option */
333 #define UV_ON 0x80 /* ON */
334 #define UV_OFF 0x00 /* OFF */
335 #define CBAR_MASK 0x20 /* DSP Color bar mask */
336 #define CBAR_ON 0x20 /* ON */
337 #define CBAR_OFF 0x00 /* OFF */
341 #define HST_QVGA 0x3F
345 #define HSZ_QVGA 0x50
349 #define VST_QVGA 0x03
353 #define VSZ_QVGA 0x78
356 #define HOSZ_VGA 0xA0
357 #define HOSZ_QVGA 0x50
360 #define VOSZ_VGA 0xF0
361 #define VOSZ_QVGA 0x78
363 /* DSPAUTO (DSP Auto Function ON/OFF Control) */
364 #define AWB_ACTRL 0x80 /* AWB auto threshold control */
365 #define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */
366 #define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */
367 #define UV_ACTRL 0x10 /* UV adjust auto slope control */
368 #define SCAL0_ACTRL 0x08 /* Auto scaling factor control */
369 #define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */
374 #define OV7720 0x7720
375 #define OV7725 0x7721
376 #define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
382 unsigned char reg_num;
386 struct ov772x_color_format {
387 enum v4l2_mbus_pixelcode code;
388 enum v4l2_colorspace colorspace;
394 struct ov772x_win_size {
398 unsigned char com7_bit;
399 const struct regval_list *regs;
403 struct v4l2_subdev subdev;
404 struct ov772x_camera_info *info;
405 const struct ov772x_color_format *cfmt;
406 const struct ov772x_win_size *win;
408 unsigned short flag_vflip:1;
409 unsigned short flag_hflip:1;
410 /* band_filter = COM8[5] ? 256 - BDBASE : 0 */
411 unsigned short band_filter;
414 #define ENDMARKER { 0xff, 0xff }
417 * register setting for window size
419 static const struct regval_list ov772x_qvga_regs[] = {
420 { HSTART, HST_QVGA },
422 { VSTART, VST_QVGA },
424 { HOUTSIZE, HOSZ_QVGA },
425 { VOUTSIZE, VOSZ_QVGA },
429 static const struct regval_list ov772x_vga_regs[] = {
434 { HOUTSIZE, HOSZ_VGA },
435 { VOUTSIZE, VOSZ_VGA },
440 * supported color format list
442 static const struct ov772x_color_format ov772x_cfmts[] = {
444 .code = V4L2_MBUS_FMT_YUYV8_2X8,
445 .colorspace = V4L2_COLORSPACE_JPEG,
451 .code = V4L2_MBUS_FMT_YVYU8_2X8,
452 .colorspace = V4L2_COLORSPACE_JPEG,
458 .code = V4L2_MBUS_FMT_UYVY8_2X8,
459 .colorspace = V4L2_COLORSPACE_JPEG,
465 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
466 .colorspace = V4L2_COLORSPACE_SRGB,
469 .com7 = FMT_RGB555 | OFMT_RGB,
472 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE,
473 .colorspace = V4L2_COLORSPACE_SRGB,
476 .com7 = FMT_RGB555 | OFMT_RGB,
479 .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
480 .colorspace = V4L2_COLORSPACE_SRGB,
483 .com7 = FMT_RGB565 | OFMT_RGB,
486 .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
487 .colorspace = V4L2_COLORSPACE_SRGB,
490 .com7 = FMT_RGB565 | OFMT_RGB,
498 #define VGA_WIDTH 640
499 #define VGA_HEIGHT 480
500 #define QVGA_WIDTH 320
501 #define QVGA_HEIGHT 240
502 #define MAX_WIDTH VGA_WIDTH
503 #define MAX_HEIGHT VGA_HEIGHT
505 static const struct ov772x_win_size ov772x_win_vga = {
508 .height = VGA_HEIGHT,
509 .com7_bit = SLCT_VGA,
510 .regs = ov772x_vga_regs,
513 static const struct ov772x_win_size ov772x_win_qvga = {
516 .height = QVGA_HEIGHT,
517 .com7_bit = SLCT_QVGA,
518 .regs = ov772x_qvga_regs,
521 static const struct v4l2_queryctrl ov772x_controls[] = {
523 .id = V4L2_CID_VFLIP,
524 .type = V4L2_CTRL_TYPE_BOOLEAN,
525 .name = "Flip Vertically",
532 .id = V4L2_CID_HFLIP,
533 .type = V4L2_CTRL_TYPE_BOOLEAN,
534 .name = "Flip Horizontally",
541 .id = V4L2_CID_BAND_STOP_FILTER,
542 .type = V4L2_CTRL_TYPE_INTEGER,
543 .name = "Band-stop filter",
555 static struct ov772x_priv *to_ov772x(const struct i2c_client *client)
557 return container_of(i2c_get_clientdata(client), struct ov772x_priv,
561 static int ov772x_write_array(struct i2c_client *client,
562 const struct regval_list *vals)
564 while (vals->reg_num != 0xff) {
565 int ret = i2c_smbus_write_byte_data(client,
575 static int ov772x_mask_set(struct i2c_client *client,
580 s32 val = i2c_smbus_read_byte_data(client, command);
587 return i2c_smbus_write_byte_data(client, command, val);
590 static int ov772x_reset(struct i2c_client *client)
592 int ret = i2c_smbus_write_byte_data(client, COM7, SCCB_RESET);
598 * soc_camera_ops function
601 static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
603 struct i2c_client *client = v4l2_get_subdevdata(sd);
604 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
607 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE);
611 if (!priv->win || !priv->cfmt) {
612 dev_err(&client->dev, "norm or win select error\n");
616 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, 0);
618 dev_dbg(&client->dev, "format %d, win %s\n",
619 priv->cfmt->code, priv->win->name);
624 static int ov772x_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
626 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
630 ctrl->value = priv->flag_vflip;
633 ctrl->value = priv->flag_hflip;
635 case V4L2_CID_BAND_STOP_FILTER:
636 ctrl->value = priv->band_filter;
642 static int ov772x_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
644 struct i2c_client *client = v4l2_get_subdevdata(sd);
645 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
651 val = ctrl->value ? VFLIP_IMG : 0x00;
652 priv->flag_vflip = ctrl->value;
653 if (priv->info->flags & OV772X_FLAG_VFLIP)
655 ret = ov772x_mask_set(client, COM3, VFLIP_IMG, val);
658 val = ctrl->value ? HFLIP_IMG : 0x00;
659 priv->flag_hflip = ctrl->value;
660 if (priv->info->flags & OV772X_FLAG_HFLIP)
662 ret = ov772x_mask_set(client, COM3, HFLIP_IMG, val);
664 case V4L2_CID_BAND_STOP_FILTER:
665 if ((unsigned)ctrl->value > 256)
667 if (ctrl->value == priv->band_filter)
670 /* Switch the filter off, it is on now */
671 ret = ov772x_mask_set(client, BDBASE, 0xff, 0xff);
673 ret = ov772x_mask_set(client, COM8,
676 /* Switch the filter on, set AEC low limit */
677 val = 256 - ctrl->value;
678 ret = ov772x_mask_set(client, COM8,
679 BNDF_ON_OFF, BNDF_ON_OFF);
681 ret = ov772x_mask_set(client, BDBASE,
685 priv->band_filter = ctrl->value;
692 static int ov772x_g_chip_ident(struct v4l2_subdev *sd,
693 struct v4l2_dbg_chip_ident *id)
695 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
697 id->ident = priv->model;
703 #ifdef CONFIG_VIDEO_ADV_DEBUG
704 static int ov772x_g_register(struct v4l2_subdev *sd,
705 struct v4l2_dbg_register *reg)
707 struct i2c_client *client = v4l2_get_subdevdata(sd);
714 ret = i2c_smbus_read_byte_data(client, reg->reg);
718 reg->val = (__u64)ret;
723 static int ov772x_s_register(struct v4l2_subdev *sd,
724 struct v4l2_dbg_register *reg)
726 struct i2c_client *client = v4l2_get_subdevdata(sd);
728 if (reg->reg > 0xff ||
732 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
736 static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
739 const struct ov772x_win_size *win;
741 /* default is QVGA */
742 diff = abs(width - ov772x_win_qvga.width) +
743 abs(height - ov772x_win_qvga.height);
744 win = &ov772x_win_qvga;
748 abs(width - ov772x_win_vga.width) +
749 abs(height - ov772x_win_vga.height))
750 win = &ov772x_win_vga;
755 static int ov772x_set_params(struct i2c_client *client, u32 *width, u32 *height,
756 enum v4l2_mbus_pixelcode code)
758 struct ov772x_priv *priv = to_ov772x(client);
767 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
768 if (code == ov772x_cfmts[i].code) {
769 priv->cfmt = ov772x_cfmts + i;
774 goto ov772x_set_fmt_error;
779 priv->win = ov772x_select_win(*width, *height);
784 ov772x_reset(client);
789 if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
792 * Manual Edge Control Mode
794 * Edge auto strength bit is set by default.
795 * Remove it when manual mode.
798 ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00);
800 goto ov772x_set_fmt_error;
802 ret = ov772x_mask_set(client,
803 EDGE_TRSHLD, OV772X_EDGE_THRESHOLD_MASK,
804 priv->info->edgectrl.threshold);
806 goto ov772x_set_fmt_error;
808 ret = ov772x_mask_set(client,
809 EDGE_STRNGT, OV772X_EDGE_STRENGTH_MASK,
810 priv->info->edgectrl.strength);
812 goto ov772x_set_fmt_error;
814 } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
816 * Auto Edge Control Mode
818 * set upper and lower limit
820 ret = ov772x_mask_set(client,
821 EDGE_UPPER, OV772X_EDGE_UPPER_MASK,
822 priv->info->edgectrl.upper);
824 goto ov772x_set_fmt_error;
826 ret = ov772x_mask_set(client,
827 EDGE_LOWER, OV772X_EDGE_LOWER_MASK,
828 priv->info->edgectrl.lower);
830 goto ov772x_set_fmt_error;
836 ret = ov772x_write_array(client, priv->win->regs);
838 goto ov772x_set_fmt_error;
843 val = priv->cfmt->dsp3;
845 ret = ov772x_mask_set(client,
846 DSP_CTRL3, UV_MASK, val);
848 goto ov772x_set_fmt_error;
854 val = priv->cfmt->com3;
855 if (priv->info->flags & OV772X_FLAG_VFLIP)
857 if (priv->info->flags & OV772X_FLAG_HFLIP)
859 if (priv->flag_vflip)
861 if (priv->flag_hflip)
864 ret = ov772x_mask_set(client,
865 COM3, SWAP_MASK | IMG_MASK, val);
867 goto ov772x_set_fmt_error;
872 val = priv->win->com7_bit | priv->cfmt->com7;
873 ret = ov772x_mask_set(client,
874 COM7, SLCT_MASK | FMT_MASK | OFMT_MASK,
877 goto ov772x_set_fmt_error;
882 if (priv->band_filter) {
883 ret = ov772x_mask_set(client, COM8, BNDF_ON_OFF, 1);
885 ret = ov772x_mask_set(client, BDBASE,
886 0xff, 256 - priv->band_filter);
888 goto ov772x_set_fmt_error;
891 *width = priv->win->width;
892 *height = priv->win->height;
896 ov772x_set_fmt_error:
898 ov772x_reset(client);
905 static int ov772x_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
909 a->c.width = VGA_WIDTH;
910 a->c.height = VGA_HEIGHT;
911 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
916 static int ov772x_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
920 a->bounds.width = VGA_WIDTH;
921 a->bounds.height = VGA_HEIGHT;
922 a->defrect = a->bounds;
923 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
924 a->pixelaspect.numerator = 1;
925 a->pixelaspect.denominator = 1;
930 static int ov772x_g_fmt(struct v4l2_subdev *sd,
931 struct v4l2_mbus_framefmt *mf)
933 struct i2c_client *client = v4l2_get_subdevdata(sd);
934 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
936 if (!priv->win || !priv->cfmt) {
937 u32 width = VGA_WIDTH, height = VGA_HEIGHT;
938 int ret = ov772x_set_params(client, &width, &height,
939 V4L2_MBUS_FMT_YUYV8_2X8);
944 mf->width = priv->win->width;
945 mf->height = priv->win->height;
946 mf->code = priv->cfmt->code;
947 mf->colorspace = priv->cfmt->colorspace;
948 mf->field = V4L2_FIELD_NONE;
953 static int ov772x_s_fmt(struct v4l2_subdev *sd,
954 struct v4l2_mbus_framefmt *mf)
956 struct i2c_client *client = v4l2_get_subdevdata(sd);
957 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
958 int ret = ov772x_set_params(client, &mf->width, &mf->height,
962 mf->colorspace = priv->cfmt->colorspace;
967 static int ov772x_try_fmt(struct v4l2_subdev *sd,
968 struct v4l2_mbus_framefmt *mf)
970 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
971 const struct ov772x_win_size *win;
975 * select suitable win
977 win = ov772x_select_win(mf->width, mf->height);
979 mf->width = win->width;
980 mf->height = win->height;
981 mf->field = V4L2_FIELD_NONE;
983 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++)
984 if (mf->code == ov772x_cfmts[i].code)
987 if (i == ARRAY_SIZE(ov772x_cfmts)) {
988 /* Unsupported format requested. Propose either */
990 /* the current one or */
991 mf->colorspace = priv->cfmt->colorspace;
992 mf->code = priv->cfmt->code;
994 /* the default one */
995 mf->colorspace = ov772x_cfmts[0].colorspace;
996 mf->code = ov772x_cfmts[0].code;
999 /* Also return the colorspace */
1000 mf->colorspace = ov772x_cfmts[i].colorspace;
1006 static int ov772x_video_probe(struct soc_camera_device *icd,
1007 struct i2c_client *client)
1009 struct ov772x_priv *priv = to_ov772x(client);
1011 const char *devname;
1013 /* We must have a parent by now. And it cannot be a wrong one. */
1014 BUG_ON(!icd->parent ||
1015 to_soc_camera_host(icd->parent)->nr != icd->iface);
1018 * check and show product ID and manufacturer ID
1020 pid = i2c_smbus_read_byte_data(client, PID);
1021 ver = i2c_smbus_read_byte_data(client, VER);
1023 switch (VERSION(pid, ver)) {
1026 priv->model = V4L2_IDENT_OV7720;
1030 priv->model = V4L2_IDENT_OV7725;
1033 dev_err(&client->dev,
1034 "Product ID error %x:%x\n", pid, ver);
1038 dev_info(&client->dev,
1039 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
1043 i2c_smbus_read_byte_data(client, MIDH),
1044 i2c_smbus_read_byte_data(client, MIDL));
1049 static struct soc_camera_ops ov772x_ops = {
1050 .controls = ov772x_controls,
1051 .num_controls = ARRAY_SIZE(ov772x_controls),
1054 static struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
1055 .g_ctrl = ov772x_g_ctrl,
1056 .s_ctrl = ov772x_s_ctrl,
1057 .g_chip_ident = ov772x_g_chip_ident,
1058 #ifdef CONFIG_VIDEO_ADV_DEBUG
1059 .g_register = ov772x_g_register,
1060 .s_register = ov772x_s_register,
1064 static int ov772x_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
1065 enum v4l2_mbus_pixelcode *code)
1067 if (index >= ARRAY_SIZE(ov772x_cfmts))
1070 *code = ov772x_cfmts[index].code;
1074 static int ov772x_g_mbus_config(struct v4l2_subdev *sd,
1075 struct v4l2_mbus_config *cfg)
1077 struct i2c_client *client = v4l2_get_subdevdata(sd);
1078 struct soc_camera_device *icd = client->dev.platform_data;
1079 struct soc_camera_link *icl = to_soc_camera_link(icd);
1081 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
1082 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1083 V4L2_MBUS_DATA_ACTIVE_HIGH;
1084 cfg->type = V4L2_MBUS_PARALLEL;
1085 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
1090 static struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
1091 .s_stream = ov772x_s_stream,
1092 .g_mbus_fmt = ov772x_g_fmt,
1093 .s_mbus_fmt = ov772x_s_fmt,
1094 .try_mbus_fmt = ov772x_try_fmt,
1095 .cropcap = ov772x_cropcap,
1096 .g_crop = ov772x_g_crop,
1097 .enum_mbus_fmt = ov772x_enum_fmt,
1098 .g_mbus_config = ov772x_g_mbus_config,
1101 static struct v4l2_subdev_ops ov772x_subdev_ops = {
1102 .core = &ov772x_subdev_core_ops,
1103 .video = &ov772x_subdev_video_ops,
1107 * i2c_driver function
1110 static int ov772x_probe(struct i2c_client *client,
1111 const struct i2c_device_id *did)
1113 struct ov772x_priv *priv;
1114 struct soc_camera_device *icd = client->dev.platform_data;
1115 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1116 struct soc_camera_link *icl;
1120 dev_err(&client->dev, "OV772X: missing soc-camera data!\n");
1124 icl = to_soc_camera_link(icd);
1125 if (!icl || !icl->priv)
1128 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1129 dev_err(&adapter->dev,
1130 "I2C-Adapter doesn't support "
1131 "I2C_FUNC_SMBUS_BYTE_DATA\n");
1135 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1139 priv->info = icl->priv;
1141 v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
1143 icd->ops = &ov772x_ops;
1145 ret = ov772x_video_probe(icd, client);
1154 static int ov772x_remove(struct i2c_client *client)
1156 struct ov772x_priv *priv = to_ov772x(client);
1157 struct soc_camera_device *icd = client->dev.platform_data;
1164 static const struct i2c_device_id ov772x_id[] = {
1168 MODULE_DEVICE_TABLE(i2c, ov772x_id);
1170 static struct i2c_driver ov772x_i2c_driver = {
1174 .probe = ov772x_probe,
1175 .remove = ov772x_remove,
1176 .id_table = ov772x_id,
1183 static int __init ov772x_module_init(void)
1185 return i2c_add_driver(&ov772x_i2c_driver);
1188 static void __exit ov772x_module_exit(void)
1190 i2c_del_driver(&ov772x_i2c_driver);
1193 module_init(ov772x_module_init);
1194 module_exit(ov772x_module_exit);
1196 MODULE_DESCRIPTION("SoC Camera driver for ov772x");
1197 MODULE_AUTHOR("Kuninori Morimoto");
1198 MODULE_LICENSE("GPL v2");